A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

NASA Astrophysics Data System (ADS)

Aggarwal, Bhawna; Gupta, Maneesha; Gupta, Anil Kumar; Sangal, Ankur

2016-10-01

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0-440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.

Demonstration of the CDMA-mode CAOS smart camera.

PubMed

Riza, Nabeel A; Mazhar, Mohsin A

2017-12-11

Demonstrated is the code division multiple access (CDMA)-mode coded access optical sensor (CAOS) smart camera suited for bright target scenarios. Deploying a silicon CMOS sensor and a silicon point detector within a digital micro-mirror device (DMD)-based spatially isolating hybrid camera design, this smart imager first engages the DMD starring mode with a controlled factor of 200 high optical attenuation of the scene irradiance to provide a classic unsaturated CMOS sensor-based image for target intelligence gathering. Next, this CMOS sensor provided image data is used to acquire a focused zone more robust un-attenuated true target image using the time-modulated CDMA-mode of the CAOS camera. Using four different bright light test target scenes, successfully demonstrated is a proof-of-concept visible band CAOS smart camera operating in the CDMA-mode using up-to 4096 bits length Walsh design CAOS pixel codes with a maximum 10 KHz code bit rate giving a 0.4096 seconds CAOS frame acquisition time. A 16-bit analog-to-digital converter (ADC) with time domain correlation digital signal processing (DSP) generates the CDMA-mode images with a 3600 CAOS pixel count and a best spatial resolution of one micro-mirror square pixel size of 13.68 μm side. The CDMA-mode of the CAOS smart camera is suited for applications where robust high dynamic range (DR) imaging is needed for un-attenuated un-spoiled bright light spectrally diverse targets.

Convolving optically addressed VLSI liquid crystal SLM

NASA Astrophysics Data System (ADS)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

X-ray Fluorescence Spectroscopy: the Potential of Astrophysics-developed Techniques

NASA Astrophysics Data System (ADS)

Elvis, M.; Allen, B.; Hong, J.; Grindlay, J.; Kraft, R.; Binzel, R. P.; Masterton, R.

2012-12-01

X-ray fluorescence from the surface of airless bodies has been studied since the Apollo X-ray fluorescence experiment mapped parts of the lunar surface in 1971-1972. That experiment used a collimated proportional counter with a resolving power of ~1 and a beam size of ~1degree. Filters separated only Mg, Al and SI lines. We review progress in X-ray detectors and imaging for astrophysics and show how these advances enable much more powerful use of X-ray fluorescence for the study of airless bodies. Astrophysics X-ray instrumentation has developed enormously since 1972. Low noise, high quantum efficiency, X-ray CCDs have flown on ASCA, XMM-Newton, the Chandra X-ray Observatory, Swift and Suzaku, and are the workhorses of X-ray astronomy. They normally span 0.5 to ~8 keV with an energy resolution of ~100 eV. New developments in silicon based detectors, especially individual pixel addressable devices, such as CMOS detectors, can withstand many orders of magnitude more radiation than conventional CCDs before degradation. The capability of high read rates provides dynamic range and temporal resolution. Additionally, the rapid read rates minimize shot noise from thermal dark current and optical light. CMOS detectors can therefore run at warmer temperatures and with ultra-thin optical blocking filters. Thin OBFs mean near unity quantum efficiency below 1 keV, thus maximizing response at the C and O lines.such as CMOS detectors, promise advances. X-ray imaging has advanced similarly far. Two types of imager are now available: specular reflection and coded apertures. X-ray mirrors have been flown on the Einstein Observatory, XMM-Newton, Chandra and others. However, as X-ray reflection only occurs at small (~1degree) incidence angles, which then requires long focal lengths (meters), mirrors are not usually practical for planetary missions. Moreover the field of view of X-ray mirrors is comparable to the incident angle, so can only image relatively small regions. More useful are coded-aperture imagers, which have flown on ART-P, Integral, and Swift. The shadow pattern from a 50% full mask allows the distribution of X-rays from a wide (10s of degrees) field of view to be imaged, but uniform emission presents difficulties. A version of a coded-aperture plus CCD detector for airless bodies study is being built for OSIRIS-REx as the student experiment REXIS. We will show the quality of the spectra that can be expected from this class of instrument.

Improving the uniformity of luminous system in radial imaging capsule endoscope system

NASA Astrophysics Data System (ADS)

Ou-Yang, Mang; Jeng, Wei-De

2013-02-01

This study concerns the illumination system in a radial imaging capsule endoscope (RICE). Uniformly illuminating the object is difficult because the intensity of the light from the light emitting diodes (LEDs) varies with angular displacement. When light is emitted from the surface of the LED, it first encounters the cone mirror, from which it is reflected, before directly passing through the lenses and complementary metal oxide semiconductor (CMOS) sensor. The light that is strongly reflected from the transparent view window (TVW) propagates again to the cone mirror, to be reflected and to pass through the lenses and CMOS sensor. The above two phenomena cause overblooming on the image plane. Overblooming causes nonuniform illumination on the image plane and consequently reduced image quality. In this work, optical design software was utilized to construct a photometric model for the optimal design of the LED illumination system. Based on the original RICE model, this paper proposes an optimal design to improve the uniformity of the illumination. The illumination uniformity in the RICE is increased from its original value of 0.128 to 0.69, greatly improving light uniformity.

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Design and development of the Sentinel-2 Multi Spectral Instrument and satellite system

NASA Astrophysics Data System (ADS)

Chorvalli, Vincent; Cazaubiel, Vincent; Bursch, Stefan; Welsch, Mario; Sontag, Heinz; Martimort, Philippe; Del Bello, Umberto; Sy, Omar; Laberinti, Paolo; Spoto, François

2010-10-01

2A and Sentinel-2B satellites currently under development will ensure systematic global acquisition of all land and coastal waters in the visible and short-wave infrared spectral domain with a 5 day revisit time at the equator. The Multi Spectral Instrument is a push-broom imager providing imagery in 13 spectral channels with spatial resolutions ranging from 10 m to 60 m and a swath width of 290 Km, larger than SPOT and Landsat. The instrument features a full field of view calibration device, a silicon carbide Three Mirror Anastigmat telescope with mirror dimensions up to 600 mm, specific filter stripe assemblies, newly developed Si-CMOS and HgCDTe detectors and a low noise wavelet compression video electronics. The 1.4 Tbits/s raw image date rate is reduced down to 490 Mbits/s at the output of the instrument to cope with the overall system transmission capability. The Sentinel-2 program has entered in the CD phase in 2009. Launch of Sentinel-2A satellite is scheduled for 2013.

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Lazarev, Alexander A.; Nikitovich, Diana V.

2017-10-01

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The SMC ADCs based on CL BC and CM opens new prospects for realization of linear and matrix IP and photo-electronic structures with matrix operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers.

High-precision angle sensor based on a Köster’s prism with absolute zero-point

NASA Astrophysics Data System (ADS)

Ullmann, V.; Oertel, E.; Manske, E.

2018-06-01

In this publication, a novel approach will be presented to use a compact white-light interferometer based on a Köster’s prism for angle measurements. Experiments show that the resolution of this angle interferometer is in the range of a commercial digital autocollimator, with a focal length of f  =  300 mm, but with clearly reduced signal noise and without overshoot artifacts in the signal caused by digital filters. The angle detection of the reference mirror in the Köster’s interferometer is based on analysing the rotation angle of the fringe pattern, which is projected on a CMOS-matrix. The fringe pattern is generated by two displaced spherical wave fronts coming from one fiber-coupled white-light source and getting divided into a reference and a measurement beam by the Köster’s prism. The displacement correlates with the reference angle mirror in one linear direction and with the angle aberrations of the prism in the other orthogonal direction on the CMOS sensor. We will present the experimental and optical setup, the method and algorithms for the image-to-angle processing as well as the experimental results obtained in calibration and long-term measurements.

Towards High Throughput Cell Growth Screening: A New CMOS 8 × 8 Biosensor Array for Life Science Applications.

PubMed

Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Letourneau, Antoine; Sawan, Mohamad

2017-04-01

In this paper we present a CMOS capacitive sensor array as a compact and low-cost platform for high-throughput cell growth monitoring. The proposed biosensor, consists of an array of 8 × 8 CMOS fully differential charge-based capacitive measurement sensors. A DC-input Σ∆ modulator is used to convert the sensors' signals to digital values for reading out the biological/chemical data and further signal processing. To compensate the mismatch variations between the current mirror transistors, a calibration circuitry is proposed which removes the output voltage offset with less than 8.2% error. We validate the chip functionality using various organic solvents with different dielectric constants. Moreover, we show the response of the chip to different concentrations of Polystyrene beads that have the same electrical properties as the living cells. The experimental results show that the chip allows the detection of a wide range of Polystyrene beads concentrations from as low as 10 beads/ml to 100 k beads/ml. In addition, we present the experimental results from H1299 (human lung carcinoma) cell line where we show that the chip successfully allows the detection of cell attachment and growth over capacitive electrodes in a 30 h measurement time and the results are in consistency with the standard cell-based assays. The capability of proposed device for label-free and real-time detection of cell growth with very high sensitivity opens up the important opportunity for utilizing the device in rapid screening of living cells.

SU-F-T-434: Development of a Fan-Beam Optical Scanner Using CMOS Array for Small Field Dosimetry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brost, E; Warmington, L; Watanabe, Y

Purpose: To design and construct a second generation optical computed tomography (OCT) system using a fan-beam with a CMOS array detector for the 3D dosimetry with polymer gel and radiochromic solid dosimeters. The system was specifically designed for the small field dosimetry. Methods: The optical scanner used a fan-beam laser, which was produced from a collimated red laser beam (λ=620 nm) with a 15-degree laser-line generating lens. The fan-beam was sent through an index-matching bath which holds the sample stage and a sample. The emerging laser light was detected with a 2.54 cm-long CMOS array detector (512 elements). The samplemore » stage rotated through the full 360 degree projection angles at 0.9-degree increments. Each projection was normalized to the unirradiated sample at the projection angle to correct for imperfections in the dosimeter. A larger sample could be scanned by using a motorized mirror and linearly translating the CMOS detector. The height of the sample stage was varied for a full 3D scanning. The image acquisition and motor motion was controlled by a computer. The 3D image reconstruction was accomplished by a fan-beam reconstruction algorithm. All the software was developed inhouse with MATLAB. Results: The scanner was used on both PRESAGE and PAGAT gel dosimeters. Irreconcilable refraction errors were seen with PAGAT because the fan beam laser line refracted away from the detector when the field was highly varying in 3D. With PRESAGE, this type of error was not seen. Conclusion: We could acquire tomographic images of dose distributions by the new OCT system with both polymer gel and radiochromic solid dosimeters. Preliminary results showed that the system was more suited for radiochromic solid dosimeters since the radiochromic dosimeters exhibited minimal refraction and scattering errors. We are currently working on improving the image quality by thorough characterization of the OCT system.« less

Variability of multilevel switching in scaled hybrid RS/CMOS nanoelectronic circuits: theory

NASA Astrophysics Data System (ADS)

Heittmann, Arne; Noll, Tobias G.

2013-07-01

A theory is presented which describes the variability of multilevel switching in scaled hybrid resistive-switching/CMOS nanoelectronic circuits. Variability is quantified in terms of conductance variation using the first two moments derived from the probability density function (PDF) of the RS conductance. For RS, which are based on the electrochemical metallization effect (ECM), this variability is - to some extent - caused by discrete events such as electrochemical reactions, which occur on atomic scale and are at random. The theory shows that the conductance variation depends on the joint interaction between the programming circuit and the resistive switch (RS), and explicitly quantifies the impact of RS device parameters and parameters of the programming circuit on the conductance variance. Using a current mirror as an exemplary programming circuit an upper limit of 2-4 bits (dependent on the filament surface area) is estimated as the storage capacity exploiting the multilevel capabilities of an ECM cell. The theoretical results were verified by Monte Carlo circuit simulations on a standard circuit simulation environment using an ECM device model which models the filament growth by a Poisson process. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Terahertz adaptive optics with a deformable mirror.

PubMed

Brossard, Mathilde; Sauvage, Jean-François; Perrin, Mathias; Abraham, Emmanuel

2018-04-01

We report on the wavefront correction of a terahertz (THz) beam using adaptive optics, which requires both a wavefront sensor that is able to sense the optical aberrations, as well as a wavefront corrector. The wavefront sensor relies on a direct 2D electro-optic imaging system composed of a ZnTe crystal and a CMOS camera. By measuring the phase variation of the THz electric field in the crystal, we were able to minimize the geometrical aberrations of the beam, thanks to the action of a deformable mirror. This phase control will open the route to THz adaptive optics in order to optimize the THz beam quality for both practical and fundamental applications.

Integrated three-dimensional optical MEMS for chip-based fluorescence detection

NASA Astrophysics Data System (ADS)

Hung, Kuo-Yung; Tseng, Fan-Gang; Khoo, Hwa-Seng

2009-04-01

This paper presents a novel fluorescence sensing chip for parallel protein microarray detection in the context of a 3-in-1 protein chip system. This portable microchip consists of a monolithic integration of CMOS-based avalanche photo diodes (APDs) combined with a polymer micro-lens, a set of three-dimensional (3D) inclined mirrors for separating adjacent light signals and a low-noise transformer-free dc-dc boost mini-circuit to power the APDs (ripple below 1.28 mV, 0-5 V input, 142 V and 12 mA output). We fabricated our APDs using the planar CMOS process so as to facilitate the post-CMOS integration of optical MEMS components such as the lenses. The APD arrays were arranged in unique circular patterns appropriate for detecting the specific fluorescently labelled protein spots in our study. The array-type APDs were designed so as to compensate for any alignment error as detected by a positional error signal algorithm. The condenser lens was used as a structure for light collection to enhance the fluorescent signals by about 25%. This element also helped to reduce the light loss due to surface absorption. We fabricated an inclined mirror to separate two adjacent fluorescent signals from different specimens. Excitation using evanescent waves helped reduce the interference of the excitation light source. This approach also reduced the number of required optical lenses and minimized the complexity of the structural design. We achieved detection floors for anti-rabbit IgG and Cy5 fluorescent dye as low as 0.5 ng/µl (~3.268 nM). We argue that the intrinsic nature of point-to-point and batch-detection methods as showcased in our chip offers advantages over the serial-scanning approach used in traditional scanner systems. In addition, our system is low cost and lightweight.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

PubMed

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang; Xie, Huikai

2018-03-26

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from -5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

Real-time system for measuring three-dimensional shape of solder bump array by focus using varifocal mirror

NASA Astrophysics Data System (ADS)

Ishii, Akira; Tai, Haruka; Mitsudo, Jun

2007-10-01

This paper describes a real-time system for measuring the three-dimensional shape of solder bumps arrayed on an LSI chip-size-package (CSP) board presented for inspection based on the shape-from-focus technique. It uses a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror enabling a simple, fast, precise focusing mechanism without moving parts to be built. A practical measuring speed of 1.69 s/package for a small CSP board (4 x 4 mm2) was achieved by incorporating an exclusive field programmable gate array processor to calculate focus measure and by constructing a domed array of LEDs as a high-intensity, uniform illumination system so that a fast (150 fps) and high-resolution (1024 x 1024 pixels/frame) CMOS image sensor could be used. Accurate measurements of bump height were also achieved with errors of 10 μm (2σ) meeting the requirements for testing the coplanarity of a bump array.

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Fukuda, Koichi; Liu, Yongxun; Mori, Takahiro; Mizubayashi, Wataru; O'uchi, Shin-ichi; Fuketa, Hiroshi; Otsuka, Shintaro; Migita, Shinji; Masahara, Meishoku; Endo, Kazuhiko; Ota, Hiroyuki; Matsukawa, Takashi

2017-04-01

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Fundamental performance differences between CMOS and CCD imagers, part IV

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Design of time-pulse coded optoelectronic neuronal elements for nonlinear transformation and integration

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

2008-03-01

In the paper the actuality of neurophysiologically motivated neuron arrays with flexibly programmable functions and operations with possibility to select required accuracy and type of nonlinear transformation and learning are shown. We consider neurons design and simulation results of multichannel spatio-time algebraic accumulation - integration of optical signals. Advantages for nonlinear transformation and summation - integration are shown. The offered circuits are simple and can have intellectual properties such as learning and adaptation. The integrator-neuron is based on CMOS current mirrors and comparators. The performance: consumable power - 100...500 μW, signal period- 0.1...1ms, input optical signals power - 0.2...20 μW time delays - less 1μs, the number of optical signals - 2...10, integration time - 10...100 of signal periods, accuracy or integration error - about 1%. Various modifications of the neuron-integrators with improved performance and for different applications are considered in the paper.

SMART-X: Square Meter, Arcsecond Resolution Telescope for X-rays

NASA Astrophysics Data System (ADS)

Vikhlinin, Alexey; SMART-X Collaboration

2013-04-01

SMART-X is a concept for a next-generation X-ray observatory with large-area, 0.5" angular resolution grazing incidence adjustable X-ray mirrors, high-throughput critical angle transmission gratings, and X-ray microcalorimeter and CMOS-based imager in the focal plane. High angular resolution is enabled by new technology based on controlling the shape of mirror segments using thin film piezo actuators deposited on the back surface. Science applications include observations of growth of supermassive black holes since redshifts of ~10, ultra-deep surveys over 10's of square degrees, galaxy assembly at z=2-3, as well as new opportunities in the high-resolution X-ray spectroscopy and time domains. We also review the progress in technology development, tests, and mission design over the past year.

A CMOS enhanced solid-state nanopore based single molecule detection platform.

PubMed

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-01-01

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data.

An efficient current-based logic cell model for crosstalk delay analysis

NASA Astrophysics Data System (ADS)

Nazarian, Shahin; Das, Debasish

2013-04-01

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors

PubMed Central

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang

2018-01-01

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from −5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems. PMID:29587451

Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors.

PubMed

Nguyen, Dung C; Ma, Dongsheng Brian; Roveda, Janet M W

2012-01-01

As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers.

Wideband low-noise variable-gain BiCMOS transimpedance amplifier

NASA Astrophysics Data System (ADS)

Meyer, Robert G.; Mack, William D.

1994-06-01

A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kilo ohms, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/square root of Hz and input signal-current handling capability of 3 mA.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Versatile optical coherence tomography for imaging the human eye

PubMed Central

Tao, Aizhu; Shao, Yilei; Zhong, Jianguang; Jiang, Hong; Shen, Meixiao; Wang, Jianhua

2013-01-01

We demonstrated the feasibility of a CMOS-based spectral domain OCT (SD-OCT) for versatile ophthalmic applications of imaging the corneal epithelium, limbus, ocular surface, contact lens, crystalline lens, retina, and full eye in vivo. The system was based on a single spectrometer and an alternating reference arm with four mirrors. A galvanometer scanner was used to switch the reference beam among the four mirrors, depending on the imaging application. An axial resolution of 7.7 μm in air, a scan depth of up to 37.7 mm in air, and a scan speed of up to 70,000 A-lines per second were achieved. The approach has the capability to provide high-resolution imaging of the corneal epithelium, contact lens, ocular surface, and tear meniscus. Using two reference mirrors, the zero delay lines were alternatively placed on the front cornea or on the back lens. The entire ocular anterior segment was imaged by registering and overlapping the two images. The full eye through the pupil was measured when the reference arm was switched among the four reference mirrors. After mounting a 60 D lens in the sample arm, this SD-OCT was used to image the retina, including the macula and optical nerve head. This system demonstrates versatility and simplicity for multi-purpose ophthalmic applications. PMID:23847729

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

Overview of CMOS process and design options for image sensor dedicated to space applications

NASA Astrophysics Data System (ADS)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Ionizing doses and displacement damage testing of COTS CMOS imagers

NASA Astrophysics Data System (ADS)

Bernard, Frédéric; Petit, Sophie; Courtade, Sophie

2017-11-01

CMOS sensors begin to be a credible alternative to CCD sensors in some space missions. However, technology evolution of CMOS sensors is much faster than CCD one's. So a continuous technology evaluation is needed for CMOS imagers. Many of commercial COTS (Components Off The Shelf) CMOS sensors use organic filters, micro-lenses and non rad-hard technologies. An evaluation of the possibilities offered by such technologies is interesting before any custom development. This can be obtained by testing commercial COTS imagers. This article will present electro-optical performances evolution of off the shelves CMOS imagers after Ionizing Doses until 50kRad(Si) and Displacement Damage environment tests (until 1011 p/cm2 at 50 MeV). Dark current level and non uniformity evolutions are compared and discussed. Relative spectral response measurement and associated evolution with irradiation will also be presented and discussed. Tests have been performed on CNES detection benches.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Nanopore-CMOS Interfaces for DNA Sequencing

PubMed Central

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-01-01

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

Nanopore-CMOS Interfaces for DNA Sequencing.

PubMed

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-08-06

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

Poly-SiGe MEMS actuators for adaptive optics

NASA Astrophysics Data System (ADS)

Lin, Blake C.; King, Tsu-Jae; Muller, Richard S.

2006-01-01

Many adaptive optics (AO) applications require mirror arrays with hundreds to thousands of segments, necessitating a CMOS-compatible MEMS process to integrate the mirrors with their driving electronics. This paper proposes a MEMS actuator that is fabricated using low-temperature polycrystalline silicon-germanium (poly-SiGe) surface-micromaching technology (total thermal budget is 6 hours at or below 425°C). The MEMS actuator consists of three flexures and a hexagonal platform, on which a micromirror is to be assembled. The flexures are made of single-layer poly-SiGe with stress gradient across thickness of the film, making them bend out-of-plane after sacrificial-layer release to create a large nominal gap. The platform, on the other hand, has an additional stress-balancing SiGe layer deposited on top, making the dual-layer stack stay flat after release. Using this process, we have successfully fabricated the MEMS actuator which is lifted 14.6 μm out-of-plane by 290-μm-long flexures. The 2-μm-thick hexagonal mirror-platform exhibits a strain gradient of -5.5×10 -5 μm -1 (equivalent to 18 mm radius-of-curvature), which would be further reduced once the micromirror is assembled.

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

Development of a wavefront sensor for terahertz pulses.

PubMed

Abraham, Emmanuel; Cahyadi, Harsono; Brossard, Mathilde; Degert, Jérôme; Freysz, Eric; Yasui, Takeshi

2016-03-07

Wavefront characterization of terahertz pulses is essential to optimize far-field intensity distribution of time-domain (imaging) spectrometers or increase the peak power of intense terahertz sources. In this paper, we report on the wavefront measurement of terahertz pulses using a Hartmann sensor associated with a 2D electro-optic imaging system composed of a ZnTe crystal and a CMOS camera. We quantitatively determined the deformations of planar and converging spherical wavefronts using the modal Zernike reconstruction least-squares method. Associated with deformable mirrors, the sensor will also open the route to terahertz adaptive optics.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Large Area Field of View for Fast Temporal Resolution Astronomy

NASA Astrophysics Data System (ADS)

Covarrubias, Ricardo A.

2018-01-01

Scientific CMOS (sCMOS) technology is especially relevant for high temporal resolution astronomy combining high resolution, large field of view with very fast frame rates, without sacrificing ultra-low noise performance. Solar Astronomy, Near Earth Object detections, Space Debris Tracking, Transient Observations or Wavefront Sensing are among the many applications this technology can be utilized. Andor Technology is currently developing the next-generation, very large area sCMOS camera with an extremely low noise, rapid frame rates, high resolution and wide dynamic range.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Micro-Mechanical Voltage Tunable Fabry-Perot Filters Formed in (111) Silicon. Degree awarded by Colorado Univ., Boulder, CO

NASA Technical Reports Server (NTRS)

Patterson, James D.

1997-01-01

The MEMS (Micro-Electro-Mechanical-Systems) technology is quickly evolving as a viable means to combine micro-mechanical and micro-optical elements on the same chip. One MEMS technology that has recently gained attention by the research community is the micro-mechanical Fabry-Perot optical filter. A MEMS based Fabry-Perot consists of a vertically integrated structure composed of two mirrors separated by an air gap. Wavelength tuning is achieved by applying a bias between the two mirrors resulting in an attractive electrostatic force which pulls the mirrors closer. In this work, we present a new micro-mechanical Fabry-Perot structure which is simple to fabricate and is integratable with low cost silicon photodetectors and transistors. The structure consists of a movable gold coated oxide cantilever for the top mirror and a stationary Au/Ni plated silicon bottom mirror. The fabrication process is single mask level, self aligned, and requires only one grown or deposited layer. Undercutting of the oxide cantilever is carried out by a combination of RIE and anisotropic KOH etching of the (111) silicon substrate. Metallization of the mirrors is provided by thermal evaporation and electroplating. The optical and electrical characteristics of the fabricated devices were studied and show promissing results. A wavelength shift of 120nm with 53V applied bias was demonstrated by one device geometry using 6.27 micrometer air gap. The finesse of the structure was 2.4. Modulation bandwidths ranging from 91KHz to greater than 920KHz were also observed. Theoretical calculations show that if mirror reflectivity, smoothness, and parallelism are improved, a finesse of 30 is attainable. The predictions also suggest that a reduction of the air gap to 1 micrometer results in an increased wavelength tuning range of 175 nm with a CMOS compatible 4.75V.

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

NASA Technical Reports Server (NTRS)

Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

2002-01-01

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

NASA Astrophysics Data System (ADS)

Riyan, Wang; Jiwei, Huang; Zhengping, Li; Weifeng, Zhang; Longyue, Zeng

2012-03-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

New integration concept of PIN photodiodes in 0.35μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Teva, J.; Park, J. M.; Jessenig, S.; Rohrbacher, M.; Wachmann, E.

2012-06-01

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

PubMed

Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig

2018-02-05

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

USAF Logistics Process Optimization Study for the Aircraft Asset Sustainment Process. Volume 1.

DTIC Science & Technology

1998-12-31

solely to have a record that could be matched with the CMOS receipt data. (This problem is caused by DLA systems that currently do not populate CMOS with...unable to obtain passwords to the Depot D035 systems. Figure 16 shows daily savings as of 30 September 1998 (current time frame ) and projects savings...Engineering, modeling, and systems/software development company LAN Local Area Network LFA Large Frame Aircraft LMA Logistics Management Agency LMR

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

NASA Astrophysics Data System (ADS)

Vigani, L.; Bortoletto, D.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-02-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

High throughput imaging cytometer with acoustic focussing.

PubMed

Zmijan, Robert; Jonnalagadda, Umesh S; Carugo, Dario; Kochi, Yu; Lemm, Elizabeth; Packham, Graham; Hill, Martyn; Glynne-Jones, Peter

2015-10-31

We demonstrate an imaging flow cytometer that uses acoustic levitation to assemble cells and other particles into a sheet structure. This technique enables a high resolution, low noise CMOS camera to capture images of thousands of cells with each frame. While ultrasonic focussing has previously been demonstrated for 1D cytometry systems, extending the technology to a planar, much higher throughput format and integrating imaging is non-trivial, and represents a significant jump forward in capability, leading to diagnostic possibilities not achievable with current systems. A galvo mirror is used to track the images of the moving cells permitting exposure times of 10 ms at frame rates of 50 fps with motion blur of only a few pixels. At 80 fps, we demonstrate a throughput of 208 000 beads per second. We investigate the factors affecting motion blur and throughput, and demonstrate the system with fluorescent beads, leukaemia cells and a chondrocyte cell line. Cells require more time to reach the acoustic focus than beads, resulting in lower throughputs; however a longer device would remove this constraint.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

PubMed

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

NASA Astrophysics Data System (ADS)

de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

2008-05-01

CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

Contour mode resonators with acoustic reflectors

DOEpatents

Olsson, Roy H [Albuquerque, NM; Fleming, James G [Albuquerque, NM; Tuck, Melanie R [Albuquerque, NM

2008-06-10

A microelectromechanical (MEM) resonator is disclosed which has a linear or ring-shaped acoustic resonator suspended above a substrate by an acoustic reflector. The acoustic resonator can be formed with a piezoelectric material (e.g. aluminum nitride, zinc oxide or PZT), or using an electrostatically-actuated material. The acoustic reflector (also termed an acoustic mirror) uses alternating sections of a relatively low acoustic impedance Z.sub.L material and a relatively high acoustic impedance Z.sub.H material to isolate the acoustic resonator from the substrate. The MEM resonator, which can be formed on a silicon substrate with conventional CMOS circuitry, has applications for forming oscillators, rf filters, and acoustic sensors.

AlN based piezoelectric micromirror.

PubMed

Shao, Jian; Li, Qi; Feng, Chuhuan; Li, Wei; Yu, Hongbin

2018-03-01

Aiming to pursue a micromirror possessing many desired characteristics, such as linear control, low power consumption, fast response, and easy fabrication, a new piezoelectric actuation strategy is presented. Different from conventional piezoelectric actuation cases, we first propose using AlN film as the active layer for actuating the micromirror. Owing to its good CMOS compatible deposition and patterning techniques, the AlN based piezoelectric micromirror has been successfully fabricated with a modified silicon-on-insulator-based microelectromechanical system (MEMS) process. At the same time, various mirror movement modes operating at high frequencies and excellent linear relationship between the movement and the control signal both have been experimentally demonstrated.

Use of digital micromirror devices as dynamic pinhole arrays for adaptive confocal fluorescence microscopy

NASA Astrophysics Data System (ADS)

Pozzi, Paolo; Wilding, Dean; Soloviev, Oleg; Vdovin, Gleb; Verhaegen, Michel

2018-02-01

In this work, we present a new confocal laser scanning microscope capable to perform sensorless wavefront optimization in real time. The device is a parallelized laser scanning microscope in which the excitation light is structured in a lattice of spots by a spatial light modulator, while a deformable mirror provides aberration correction and scanning. A binary DMD is positioned in an image plane of the detection optical path, acting as a dynamic array of reflective confocal pinholes, images by a high performance cmos camera. A second camera detects images of the light rejected by the pinholes for sensorless aberration correction.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Integrated 3D porous C-MoS2/nitrogen-doped graphene electrode for high capacity and prolonged stability lithium storage

NASA Astrophysics Data System (ADS)

Xie, D.; Tang, W. J.; Xia, X. H.; Wang, D. H.; Zhou, D.; Shi, F.; Wang, X. L.; Gu, C. D.; Tu, J. P.

2015-11-01

Scrupulous design and fabrication of advanced anode materials are of great importance for developing high-performance lithium ion batteries. Herein, we report a facile strategy for construction of free-standing and free-binder 3D porous carbon coated MoS2/nitrogen-doped graphene (C-MoS2/N-G) integrated electrode via a hydrothermal-induced self-assembly process. The preformed carbon coated MoS2 is strongly anchored on the porous nitrogen-doped graphene aerogel architecture. As an anode for lithium ion batteries, the C-MoS2/N-G electrode delivers a high first discharge capacity of 1600 mAh g-1 and maintains 900 mAh g-1 after 500 cycles at a current density of 200 mA g-1. Impressively, superior high-rate capability is achieved for the C-MoS2/N-G with a reversible capacity of 500 mAh g-1 at a high current density of 4000 mA g-1. Furthermore, the lithium storage mechanism of the obtained integrated electrode is investigated by ex-situ X-ray photoelectron spectroscopy and transmission electron microscopy in detail.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

A 0.18 μm CMOS LDO Regulator for an On-Chip Sensor Array Impedance Measurement System.

PubMed

Pérez-Bailón, Jorge; Márquez, Alejandro; Calvo, Belén; Medrano, Nicolás

2018-05-02

This paper presents a fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator specifically designed to meet the stringent requirements of a battery-operated impedance spectrometry multichannel CMOS micro-instrument. The proposed LDO provides a regulated 1.8 V voltage from a 3.6 V to 1.94 V battery voltage over a −40 °C to 100 °C temperature range, with a compact topology (<0.10 mm² area) and a constant quiescent current of only 7.45 μA with 99.985% current efficiency, achieving remarkable state-of-art Figures of Merit (FoMs) for the regulating⁻transient performance. Experimental measurements validate its suitability for the target application, paving the way towards the future achievement of a truly portable System on Chip (SoC) platform for impedance sensors.

A high efficiency PWM CMOS class-D audio power amplifier

NASA Astrophysics Data System (ADS)

Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

2009-02-01

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Multi-view line-scan inspection system using planar mirrors

NASA Astrophysics Data System (ADS)

Holländer, Bransilav; Štolc, Svorad; Huber-Mörk, Reinhold

2013-04-01

We demonstrate the design, setup, and results for a line-scan stereo image acquisition system using a single area- scan sensor, single lens and two planar mirrors attached to the acquisition device. The acquired object is moving relatively to the acquisition device and is observed under three different angles at the same time. Depending on the specific configuration it is possible to observe the object under a straight view (i.e., looking along the optical axis) and two skewed views. The relative motion between an object and the acquisition device automatically fulfills the epipolar constraint in stereo vision. The choice of lines to be extracted from the CMOS sensor depends on various factors such as the number, position and size of the mirrors, the optical and sensor configuration, or other application-specific parameters like desired depth resolution. The acquisition setup presented in this paper is suitable for the inspection of a printed matter, small parts or security features such as optical variable devices and holograms. The image processing pipeline applied to the extracted sensor lines is explained in detail. The effective depth resolution achieved by the presented system, assembled from only off-the-shelf components, is approximately equal to the spatial resolution and can be smoothly controlled by changing positions and angles of the mirrors. Actual performance of the device is demonstrated on a 3D-printed ground-truth object as well as two real-world examples: (i) the EUR-100 banknote - a high-quality printed matter and (ii) the hologram at the EUR-50 banknote { an optical variable device.

Mirror neurons and imitation: a computationally guided review.

PubMed

Oztop, Erhan; Kawato, Mitsuo; Arbib, Michael

2006-04-01

Neurophysiology reveals the properties of individual mirror neurons in the macaque while brain imaging reveals the presence of 'mirror systems' (not individual neurons) in the human. Current conceptual models attribute high level functions such as action understanding, imitation, and language to mirror neurons. However, only the first of these three functions is well-developed in monkeys. We thus distinguish current opinions (conceptual models) on mirror neuron function from more detailed computational models. We assess the strengths and weaknesses of current computational models in addressing the data and speculations on mirror neurons (macaque) and mirror systems (human). In particular, our mirror neuron system (MNS), mental state inference (MSI) and modular selection and identification for control (MOSAIC) models are analyzed in more detail. Conceptual models often overlook the computational requirements for posited functions, while too many computational models adopt the erroneous hypothesis that mirror neurons are interchangeable with imitation ability. Our meta-analysis underlines the gap between conceptual and computational models and points out the research effort required from both sides to reduce this gap.

Adaptive optics compensation over a 3 km near horizontal path

NASA Astrophysics Data System (ADS)

Mackey, Ruth; Dainty, Chris

2008-10-01

We present results of adaptive optics compensation at the receiver of a 3km optical link using a beacon laser operating at 635nm. The laser is transmitted from the roof of a seven-storey building over a near horizontal path towards a 127 mm optical receiver located on the second-floor of the Applied Optics Group at the National University of Ireland, Galway. The wavefront of the scintillated beam is measured using a Shack-Hartmann wavefront sensor (SHWFS) with high-speed CMOS camera capable of frame rates greater than 1kHz. The strength of turbulence is determined from the fluctuations in differential angle-of-arrival in the wavefront sensor measurements and from the degree of scintillation in the pupil plane. Adaptive optics compensation is applied using a tip-tilt mirror and 37 channel membrane mirror and controlled using a single desktop computer. The performance of the adaptive optics system in real turbulence is compared with the performance of the system in a controlled laboratory environment, where turbulence is generated using a liquid crystal spatial light modulator.

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

PubMed

Oh, Sungjin; Ahn, Jae-Hyun; Lee, Sangmin; Ko, Hyoungho; Seo, Jong Mo; Goo, Yong-Sook; Cho, Dong-il Dan

2015-01-01

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 μm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 μ m × 55 μm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 μA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

MoS2/Ni3S4 composite nanosheets on interconnected carbon shells as an excellent supercapacitor electrode architecture for long term cycling at high current densities

NASA Astrophysics Data System (ADS)

Qin, Shengchun; Yao, Tinghui; Guo, Xin; Chen, Qiang; Liu, Dequan; Liu, Qiming; Li, Yali; Li, Junshuai; He, Deyan

2018-05-01

In this paper, we report an electrode architecture of molybdenum disulfide (MoS2)/nickel sulfide (Ni3S4) composite nanosheets anchored on interconnected carbon (C) shells (C@MoS2/Ni3S4). Electrochemical measurements indicate that the C@MoS2/Ni3S4 structure possesses excellent supercapacitive properties especially for long term cycling at high current densities. A specific capacitance as high as ∼640.7 F g-1 can still be delivered even after 10,000 cycles at a high current density of 20 A g-1. From comparison of microstructures and electrochemical properties of the related materials/structures, the improved performance of C@MoS2/Ni3S4 can be attributed to the relatively dispersedly distributed nanosheet-shaped MoS2/Ni3S4 that provides efficient contact with electrolyte and effectively buffers the volume change during charge/discharge processes, enhanced cycling stability by MoS2, and reduced equivalent series resistance by the interconnected C shells.

High temperature current mirror amplifier

DOEpatents

Patterson, III, Raymond B.

1984-05-22

A high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg.

A Broadband X-Ray Imaging Spectroscopy with High-Angular Resolution: the FORCE Mission

NASA Technical Reports Server (NTRS)

Mori, Koji; Tsuru, Takeshi Go; Nakazawac, Kazuhiro; Ueda, Yoshihiro; Okajima, Takashi; Murakami, Hiroshi; Awaki, Hisamitsu; Matsumoto, Hironori; Fukazawai, Yasushi; Tsunemi, Hiroshi;

A broadband x-ray imaging spectroscopy with high-angular resolution: the FORCE mission

NASA Astrophysics Data System (ADS)

Mori, Koji; Tsuru, Takeshi Go; Nakazawa, Kazuhiro; Ueda, Yoshihiro; Okajima, Takashi; Murakami, Hiroshi; Awaki, Hisamitsu; Matsumoto, Hironori; Fukazawa, Yasushi; Tsunemi, Hiroshi; Takahashi, Tadayuki; Zhang, William W.

2016-07-01

We are proposing FORCE (Focusing On Relativistic universe and Cosmic Evolution) as a future Japan-lead Xray observatory to be launched in the mid 2020s. Hitomi (ASTRO-H) possesses a suite of sensitive instruments enabling the highest energy-resolution spectroscopy in soft X-ray band, a broadband X-ray imaging spectroscopy in soft and hard X-ray bands, and further high energy coverage up to soft gamma-ray band. FORCE is the direct successor to the broadband X-ray imaging spectroscopy aspect of Hitomi (ASTRO-H) with significantly higher angular resolution. The current design of FORCE defines energy band pass of 1-80 keV with angular resolution of < 15 in half-power diameter, achieving a 10 times higher sensitivity above 10 keV compared to any previous missions with simultaneous soft X-ray coverage. Our primary scientific objective is to trace the cosmic formation history by searching for "missing black holes" in various mass-scales: "buried supermassive black holes (SMBHs)" (> 104 M⊙) residing in the center of galaxies in a cosmological distance, "intermediate-mass black holes" (102-104 M⊙) acting as the possible seeds from which SMBHs grow, and "orphan stellar-mass black holes" (< 102 M⊙) without companion in our Galaxy. In addition to these missing BHs, hunting for the nature of relativistic particles at various astrophysical shocks is also in our scope, utilizing the broadband X-ray coverage with high angular-resolution. FORCE are going to open a new era in these fields. The satellite is proposed to be launched with the Epsilon vehicle that is a Japanese current solid-fuel rocket. FORCE carries three identical pairs of Super-mirror and wide-band X-ray detector. The focal length is currently planned to be 10 m. The silicon mirror with multi-layer coating is our primary choice to achieve lightweight, good angular optics. The detector is a descendant of hard X-ray imager onboard Hitomi (ASTRO-H) replacing its silicon strip detector with SOI-CMOS silicon pixel detector, allowing an extension of the low energy threshold down to 1 keV or even less.

High temperature current mirror amplifier

DOEpatents

Patterson, R.B. III.

1984-05-22

Disclosed is a high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg. 2 figs.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

PubMed

Yan Lu; Wing-Hung Ki

2014-06-01

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

NASA Astrophysics Data System (ADS)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

High accuracy switched-current circuits using an improved dynamic mirror

NASA Technical Reports Server (NTRS)

Zweigle, G.; Fiez, T.

1991-01-01

The switched-current technique, a recently developed circuit approach to analog signal processing, has emerged as an alternative/compliment to the well established switched-capacitor circuit technique. High speed switched-current circuits offer potential cost and power savings over slower switched-capacitor circuits. Accuracy improvements are a primary concern at this stage in the development of the switched-current technique. Use of the dynamic current mirror has produced circuits that are insensitive to transistor matching errors. The dynamic current mirror has been limited by other sources of error including clock-feedthrough and voltage transient errors. In this paper we present an improved switched-current building block using the dynamic current mirror. Utilizing current feedback the errors due to current imbalance in the dynamic current mirror are reduced. Simulations indicate that this feedback can reduce total harmonic distortion by as much as 9 dB. Additionally, we have developed a clock-feedthrough reduction scheme for which simulations reveal a potential 10 dB total harmonic distortion improvement. The clock-feedthrough reduction scheme also significantly reduces offset errors and allows for cancellation with a constant current source. Experimental results confirm the simulated improvements.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Rolando, Sébastien; Corbière, Franck; Rizzolo, Serena; Chabane, Aziouz; Girard, Sylvain; Baer, Jérémy; Estribeau, Magali; Magnan, Pierre; Paillet, Philippe; Van Uffelen, Marco; Mont Casellas, Laura; Scott, Robin; Gaillardin, Marc; Marcandella, Claude; Marcelot, Olivier; Allanche, Timothé

2017-01-01

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

MEMS phase former kit for high-resolution wavefront control

NASA Astrophysics Data System (ADS)

Gehner, Andreas; Wildenhain, Michael; Neumann, Hannes; Elgner, Andreas; Schenk, Harald

2005-08-01

The MEMS Phase Former Kit developed by the Fraunhofer IPMS is a complete Spatial Light Modulator system based on a piston-type Micro Mirror Array (MMA) for the use in high-resolution, high-speed optical phase control. It has been designed for an easy system integration into an user-specific environment to offer a platform for first practical investigations to open up new applications in Adaptive Optics. The key component is a fine segmented 240 x 200 array of 40 μm piston-type mirror elements capable of 400 nm analog deflection for a 2pi phase modulation in the visible. Each mirror can be addressed and deflected independently by means of an integrated CMOS backplane address circuitry at an 8bit height resolution. Full user programmability and control is provided by a newly developed comfortable driver software for Windows XP based PCs supporting both a Graphical User Interface (GUI) for stand-alone operation with pre-defined data patterns as well as an open ActiveX programming interface for a closed-loop operation with real-time data from an external source. An IEEE1394a FireWire interface is used for high-speed data communication with an electronic driving board performing the actual MMA programming and control allowing for an overall frame rate of up to 500 Hz. Successful proof-of-concept demonstrations already have been given for eye aberration correction in ophthalmology, for error compensation of leightweight primary mirrors of future space telescopes and for ultra-short laser pulse shaping. Besides a presentation of the basic device concept and system architecture the paper will give an overview of the obtained results from these applications.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

NASA Astrophysics Data System (ADS)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

A CMOS smart temperature and humidity sensor with combined readout.

PubMed

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

Gasdynamic Mirror Fusion Propulsion Experiment

NASA Technical Reports Server (NTRS)

Emrich, Bill; Rodgers, Stephen L. (Technical Monitor)

2000-01-01

A gasdynamic mirror (GDM) fusion propulsion experiment is currently being constructed at the NASA Marshall Space Flight Center (MSFC) to test the feasibility of this particular type of fusion device. Because of the open magnetic field line configuration of mirror fusion devices, they are particularly well suited for propulsion system applications since they allow for the easy ejection of thrust producing plasma. Currently, the MSFC GDM is constructed in three segments. The vacuum chamber mirror segment, the plasma injector mirror segment, and the main plasma chamber segment. Enough magnets are currently available to construct up to three main plasma chamber segments. The mirror segments are also segmented such that they can be expanded to accommodate new end plugging strategies with out requiring the disassembly of the entire mirror segment. The plasma for the experiment is generated in a microwave cavity located between the main magnets and the mirror magnets. Ion heating is accomplished through ambipolar diffusion. The objective of the experiment is to investigate the stability characteristics of the gasdynamic mirror and to map a region of parameter space within which the plasma can be confined in a stable steady state configuration. The mirror ratio, plasma density, and plasma "b" will be varied over a range of values and measurements subsequently taken to determine the degree of plasma stability.

System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

PubMed

Lee, Sung Pil

2015-10-01

Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

A 4MP high-dynamic-range, low-noise CMOS image sensor

NASA Astrophysics Data System (ADS)

Ma, Cheng; Liu, Yang; Li, Jing; Zhou, Quan; Chang, Yuchun; Wang, Xinyang

2015-03-01

In this paper we present a 4 Megapixel high dynamic range, low dark noise and dark current CMOS image sensor, which is ideal for high-end scientific and surveillance applications. The pixel design is based on a 4-T PPD structure. During the readout of the pixel array, signals are first amplified, and then feed to a low- power column-parallel ADC array which is already presented in [1]. Measurement results show that the sensor achieves a dynamic range of 96dB, a dark noise of 1.47e- at 24fps speed. The dark current is 0.15e-/pixel/s at -20oC.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

Fundamental performance differences between CMOS and CCD imagers: Part II

NASA Astrophysics Data System (ADS)

Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

2007-09-01

A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

A PSD (position sensing device) to map the shift and tilt of the SRT secondary mirror

NASA Astrophysics Data System (ADS)

Pisanu, Tonino; Buffa, Franco; Concu, Raimondo; Marongiu, Pasqualino; Pili, Mauro; Poppi, Sergio; Serra, Giampaolo; Urru, Enrico; Vargiu, Gianpaolo

2014-07-01

The Sardinia Radio Telescope (SRT) Metrology team has started to install the initial group of devices on the new 64 meters radio-telescope. These devices will be devoted for the realization of the antenna deformation control system: an electronic inclinometer able to monitor the alidade deformations and a Position Sensing Device (PSD) able to map the secondary mirror (M2) displacements and tilts. The inclinometer is used to map the rail conditions, the azimuthal axis inclination and the thermal effects on the alidade structure. The PSD will be used to measure the secondary mirror displacements induced by the gravity and by the thermal deformations that produce shifts and tilts with respect to it s ideal optical alignment. The PSD will be traced by a laser diode installed on a mechanically stable position inside the vertex room. Preliminarly we decided to characterize excursion range of M2, in order to know if the PSD measuring range of about +/- 10 mm is enough for our purposes. We designed, built and tested an optical measuring device, based on commercial CMOS with a wider measurement range of +/- 40 mm and with a resolution of around 0.1 mm. After a laboratory characterization at the 23 meters real distance, the PSD and the laser have been installed in the antenna. In this paper we show the results of the measurements performed by moving the antenna in elevation.

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

NASA Astrophysics Data System (ADS)

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Kodak AMSD Concept Overview and Status (Semi-Rigid Mirror with Sparse Actuators)

NASA Technical Reports Server (NTRS)

Matthews, Gary; Maji, Arup K. (Technical Monitor)

2001-01-01

This talk will review Kodak's current AMSD technical and schedule status. For AMSD, Kodak is fabricating a semi-rigid closed-back egg-crate glass mirror, a graphite composite reaction structure, and 16 force actuators for figure control. The mirror is currently on schedule for cryotesting in early '02.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Low energy CMOS for space applications

NASA Technical Reports Server (NTRS)

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

NASA Astrophysics Data System (ADS)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

Detecting single-abasic residues within a DNA strand immobilized in a biological nanopore using an integrated CMOS sensor.

PubMed

Kim, Jungsuk; Maitra, Raj D; Pedrotti, Ken; Dunbar, William B

2013-02-01

In this paper, we demonstrate the application of a novel current-measuring sensor (CMS) customized for nanopore applications. The low-noise CMS is fabricated in a 0.35μm CMOS process and is implemented in experiments involving DNA captured in an α-hemolysin (α-HL) nanopore. Specifically, the CMS is used to build a current amplitude map as a function of varying positions of a single-abasic residue within a homopolymer cytosine single-stranded DNA (ssDNA) that is captured and held in the pore. Each ssDNA is immobilized using a biotin-streptavidin linkage. Five different DNA templates are measured and compared: one all-cytosine ssDNA, and four with a single-abasic residue substitution that resides in or near the ~1.5nm aperture of the α-HL channel when the strand is immobilized. The CMOS CMS is shown to resolves the ~5Å displacements of the abasic residue within the varying templates. The demonstration represents an advance in application-specific circuitry that is optimized for small-footprint nanopore applications, including genomic sequencing.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

PubMed

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.

PubMed

Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

2014-09-01

In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 μm × 400 μm sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. Copyright © 2014 IPEM. Published by Elsevier Ltd. All rights reserved.

Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.

PubMed

Nasri, Bayan; Wu, Ting; Alharbi, Abdullah; You, Kae-Dyi; Gupta, Mayank; Sebastian, Sunit P; Kiani, Roozbeh; Shahrjerdi, Davood

2017-12-01

We introduce a hybrid CMOS-graphene sensor array for subsecond measurement of dopamine via fast-scan cyclic voltammetry (FSCV). The prototype chip has four independent CMOS readout channels, fabricated in a 65-nm process. Using planar multilayer graphene as biologically compatible sensing material enables integration of miniaturized sensing electrodes directly above the readout channels. Taking advantage of the chemical specificity of FSCV, we introduce a region of interest technique, which subtracts a large portion of the background current using a programmable low-noise constant current at about the redox potentials. We demonstrate the utility of this feature for enhancing the sensitivity by measuring the sensor response to a known dopamine concentration in vitro at three different scan rates. This strategy further allows us to significantly reduce the dynamic range requirements of the analog-to-digital converter (ADC) without compromising the measurement accuracy. We show that an integrating dual-slope ADC is adequate for digitizing the background-subtracted current. The ADC operates at a sampling frequency of 5-10 kHz and has an effective resolution of about 60 pA, which corresponds to a theoretical dopamine detection limit of about 6 nM. Our hybrid sensing platform offers an effective solution for implementing next-generation FSCV devices that can enable precise recording of dopamine signaling in vivo on a large scale.

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Detection of Short-Waved Spin Waves in Individual Microscopic Spin-Wave Waveguides Using the Inverse Spin Hall Effect.

PubMed

Brächer, T; Fabre, M; Meyer, T; Fischer, T; Auffret, S; Boulle, O; Ebels, U; Pirro, P; Gaudin, G

2017-12-13

The miniaturization of complementary metal-oxide-semiconductor (CMOS) devices becomes increasingly difficult due to fundamental limitations and the increase of leakage currents. Large research efforts are devoted to find alternative concepts that allow for a larger data-density and lower power consumption than conventional semiconductor approaches. Spin waves have been identified as a potential technology that can complement and outperform CMOS in complex logic applications, profiting from the fact that these waves enable wave computing on the nanoscale. The practical application of spin waves, however, requires the demonstration of scalable, CMOS compatible spin-wave detection schemes in material systems compatible with standard spintronics as well as semiconductor circuitry. Here, we report on the wave-vector independent detection of short-waved spin waves with wavelengths down to 150 nm by the inverse spin Hall effect in spin-wave waveguides made from ultrathin Ta/Co 8 Fe 72 B 20 /MgO. These findings open up the path for miniaturized scalable interconnects between spin waves and CMOS and the use of ultrathin films made from standard spintronic materials in magnonics.

Swap intensified WDR CMOS module for I2/LWIR fusion

NASA Astrophysics Data System (ADS)

Ni, Yang; Noguier, Vincent

2015-05-01

The combination of high resolution visible-near-infrared low light sensor and moderate resolution uncooled thermal sensor provides an efficient way for multi-task night vision. Tremendous progress has been made on uncooled thermal sensors (a-Si, VOx, etc.). It's possible to make a miniature uncooled thermal camera module in a tiny 1cm3 cube with <1W power consumption. For silicon based solid-state low light CCD/CMOS sensors have observed also a constant progress in terms of readout noise, dark current, resolution and frame rate. In contrast to thermal sensing which is intrinsic day&night operational, the silicon based solid-state sensors are not yet capable to do the night vision performance required by defense and critical surveillance applications. Readout noise, dark current are 2 major obstacles. The low dynamic range at high sensitivity mode of silicon sensors is also an important limiting factor, which leads to recognition failure due to local or global saturations & blooming. In this context, the image intensifier based solution is still attractive for the following reasons: 1) high gain and ultra-low dark current; 2) wide dynamic range and 3) ultra-low power consumption. With high electron gain and ultra low dark current of image intensifier, the only requirement on the silicon image pickup device are resolution, dynamic range and power consumption. In this paper, we present a SWAP intensified Wide Dynamic Range CMOS module for night vision applications, especially for I2/LWIR fusion. This module is based on a dedicated CMOS image sensor using solar-cell mode photodiode logarithmic pixel design which covers a huge dynamic range (> 140dB) without saturation and blooming. The ultra-wide dynamic range image from this new generation logarithmic sensor can be used directly without any image processing and provide an instant light accommodation. The complete module is slightly bigger than a simple ANVIS format I2 tube with <500mW power consumption.

The meter-class carbon fiber reinforced polymer mirror and segmented mirror telescope at the Naval Postgraduate School

NASA Astrophysics Data System (ADS)

Wilcox, Christopher; Fernandez, Bautista; Bagnasco, John; Martinez, Ty; Romeo, Robert; Agrawal, Brij

2015-03-01

The Adaptive Optics Center of Excellence for National Security at the Naval Postgraduate School has implemented a technology testing platform and array of facilities for next-generation space-based telescopes and imaging system development. The Segmented Mirror Telescope is a 3-meter, 6 segment telescope with actuators on its mirrors for system optical correction. Currently, investigation is being conducted in the use of lightweight carbon fiber reinforced polymer structures for large monolithic optics. Advantages of this material include lower manufacturing costs, very low weight, and high durability and survivability compared to its glass counterparts. Design and testing has begun on a 1-meter, optical quality CFRP parabolic mirror for the purpose of injecting collimated laser light through the SMT primary and secondary mirrors as well as the following aft optics that include wavefront sensors and deformable mirrors. This paper will present the design, testing, and usage of this CFRP parabolic mirror and the current path moving forward with this ever-evolving technology.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Magnan, Pierre; Bernard, Frédéric; Rolland, Guy; Saint-Pé, Olivier; Huger, Nicolas; Corbière, Franck

2008-02-01

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 μm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Adaptive Optics for Industry and Medicine

NASA Astrophysics Data System (ADS)

Dainty, Christopher

2008-01-01

pt. 1. Wavefront correctors and control. Liquid crystal lenses for correction of presbyopia (Invited Paper) / Guoqiang Li and Nasser Peyghambarian. Converging and diverging liquid crystal lenses (oral paper) / Andrew X. Kirby, Philip J. W. Hands, and Gordon D. Love. Liquid lens technology for miniature imaging systems: status of the technology, performance of existing products and future trends (invited paper) / Bruno Berge. Carbon fiber reinforced polymer deformable mirrors for high energy laser applications (oral paper) / S. R. Restaino ... [et al.]. Tiny multilayer deformable mirrors (oral paper) / Tatiana Cherezova ... [et al.]. Performance analysis of piezoelectric deformable mirrors (oral paper) / Oleg Soloviev, Mikhail Loktev and Gleb Vdovin. Deformable membrane mirror with high actuator density and distributed control (oral paper) / Roger Hamelinck ... [et al.]. Characterization and closed-loop demonstration of a novel electrostatic membrane mirror using COTS membranes (oral paper) / David Dayton ... [et al.]. Electrostatic micro-deformable mirror based on polymer materials (oral paper) / Frederic Zamkotsian ... [et al.]. Recent progress in CMOS integrated MEMS A0 mirror development (oral paper) / A. Gehner ... [et al.]. Compact large-stroke piston-tip-tilt actuator and mirror (oral paper) / W. Noell ... [et al.]. MEMS deformable mirrors for high performance AO applications (oral paper) / Paul Bierden, Thomas Bifano and Steven Cornelissen. A versatile interferometric test-rig for the investigation and evaluation of ophthalmic AO systems (poster paper) / Steve Gruppetta, Jiang Jian Zhong and Luis Diaz-Santana. Woofer-tweeter adaptive optics (poster paper) / Thomas Farrell and Chris Dainty. Deformable mirrors based on transversal piezoeffect (poster paper) / Gleb Vdovin, Mikhail Loktev and Oleg Soloviev. Low-cost spatial light modulators for ophthalmic applications (poster paper) / Vincente Durán ... [et al.]. Latest MEMS DM developments and the path ahead at Iris AO (poster paper) / Michael A. Helmbrecht ... [et al.]. Electrostatic push pull mirror improvernents in visual optics (poster paper) / S. Bonora and L. Poletto. 25cm bimorph mirror for petawatt laser / S. Bonora ... [et al.]. Hysteresis compensation for piezo deformable mirror (poster paper) / H. Song ... [et al.]. Static and dynamic responses of an adaptive optics ferrofluidic mirror (poster paper) / A. Seaman ... [et al.]. New HDTV (1920 x 1080) phase-only SLM (poster paper) / Stefan Osten and Sven Krueger. Monomorph large aperture deformable mirror for laser applications (poster paper) / J-C Sinquin, J-M Lurcon, C. Guillemard. Low cost, high speed for adaptive optics control (oral paper) / Christopher D. Saunter and Gordon D. Love. Open loop woofer-tweeter adaptive control on the LAO multi-conjugate adaptive optics testbed (oral paper) / Edward Laag, Don Gavel and Mark Ammons -- pt. 2. Wavefront sensors. Wave front sensorless adaptive optics for imaging and microscopy (invited paper) / Martin J. Booth, Delphine Débarre and Tony Wilson. A fundamental limit for wavefront sensing (oral paper) / Carl Paterson. Coherent fibre-bundle wavefront sensor (oral paper) / Brian Vohnsen, I. Iglesias and Pablo Artal. Maximum-likelihood methods in wave-front sensing: nuisance parameters (oral paper) / David Lara, Harrison H. Barrett, and Chris Dainty. Real-time wavefront sensing for ultrafast high-power laser beams (oral paper) / Juan M. Bueno ... [et al.]. Wavefront sensing using a random phase screen (oral paper) / M. Loktev, G. Vdovin and O. Soloviev. Quadri-Wave Lateral Shearing Interferometry: a new mature technique for wave front sensing in adaptive optics (oral paper) / Benoit Wattellier ... [et al.]. In vivo measurement of ocular aberrations with a distorted grating wavefront sensor (oral paper) / P. Harrison ... [et al.]. Position-sensitive detector designed with unusual CMOS layout strategies for a Hartman-Shack wavefront sensor (oral Paper) / Davies W. de Lima Monteiro ... [et al.]. Adaptive optics system to compensate complex-shaped wavefronts (oral paper) / Miguel Ares, and Santiago Royo. A kind of novel linear phase retrieval wavefront sensor and its application in close-loop adaptive optics system (oral paper) / Xinyang Li ... [et al.]. Ophthalmic Shack-Hatmann wavefront sensor applications (oral paper) / Daniel R. Neal. Wave front sensing of an optical vortex and its correction with the help of bimorph mirror (poster paper) / F. A. Starikov ... [et al.]. Recent advances in laser metrology and correction of high numerical aperture laser beams using quadri-wave lateral shearing-interferometry (poster paper) / Benoit Wattellier, Ivan Doudet and William Boucher. Thin film optical metrology using principles of wavefront sensing and interference (poster paper) / D. M. Faichnie, A. H. Greenaway and I. Bain. Direct diffractive image simulation (poster paper) / A. P. Maryasov, N. P. Maryasov, A. P. Layko. High speed smart CMOS sensor for adaptive optics (poster paper) / T. D. Raymond ... [et al.]. Traceable astigmatism measurements for wavefront sensors (poster paper) / S. R. G. Hall, S. D. Knox, R. F. Stevens -- pt. 3. Adaptive optics in vision science. Dual-conjugate adaptive optics instrument for wide-field retinal imaging (oral paper) / Jörgen Thaung, Mette-Owner Petersen and Zoran Popovic. Visual simulation using electromagnetic adaptive-optics (oral paper) / Laurent Vabre ... [et al.]. High-resolution field-of-view widening in human eye retina imaging (oral paper) / Alexander V. Dubinin, Tatyana Yu. Cherezova, Alexis V. Kudryashov. Psychophysical experiments on visual performance with an ocular adaptive optics system (oral paper) / E. Dalimier, J. C. Dainty and J. Barbur. Does the accommodative mechanism of the eye calibrate itself using aberration dynamics? (oral paper) / K. M. Hampson, S. S. Chin and E. A. H. Mallen. A study of field aberrations in the human eye (oral paper) / Alexander V. Goncharov ... [et al.]. Dual wavefront corrector ophthalmic adaptive optics: design and alignment (oral paper) / Alfredo Dubra and David Williams. High speed simultaneous SLO/OCT imaging of the human retina with adaptive optics (oral paper) / M. Pircher ... [et al.]. Characterization of an AO-OCT system (oral paper) / Julia W. Evans ... [et al.]. Adaptive optics optical coherence tomography for retina imaging (oral paper) / Guohua Shi ... [et al.]. Development, calibration and performance of an electromagnetic-mirror-based adaptive optics system for visual optics (oral paper) / Enrique Gambra ... [et al.]. Adaptive eye model (poster paper) / Sergey O. Galetskzy and Alexty V. Kudryashov. Adaptive optics system for retinal imaging based on a pyramid wavefront sensor (poster paper) / Sabine Chiesa ... [et al.]. Modeling of non-stationary dynamic ocular aberrations (poster paper) / Conor Leahy and Chris Dainty. High-order aberrations and accommodation of human eye (poster paper) / Lixia Xue ... [et al.]. Electromagnetic deformable mirror: experimental assessment and first ophthalmic applications (poster paper) / L. Vabre ... [et al.]. Correcting ocular aberrations in optical coherence tomography (poster paper) / Simon Tuohy ... [et al.] -- pt. 4. Adaptive optics in optical storage and microscopy. The application of liquid crystal aberration compensator for the optical disc systems (invited paper) / Masakazu Ogasawara. Commercialization of the adaptive scanning optical microscope (ASOM) (oral paper) / Benjamin Potsaid ... [et al.]. A practical implementation of adaptive optics for aberration compensation in optical microscopy (oral paper) / A. J. Wright ... [et al.]. Active focus locking in an optically sectioning microscope using adaptive optics (poster paper) / S. Poland, A. J. Wright, J. M. Girkin. Towards four dimensional particle tracking for biological applications / Heather I. Campbell ... [et al.]. Adaptive optics for microscopy (poster paper) / Xavier Levecq -- pt. 5. Adaptive optics in lasers. Improved beam quality of a high power Yb: YAG laser (oral paper) / Dennis G. Harris ... [et al.]. Intracavity adaptive optics optimization of an end-pumped Nd:YVO4 laser (oral paper) / Petra Welp, Ulrich Wittrock. New results in high power lasers beam correction (oral paper) / Alexis Kudryashov ... [et al.]. Adaptive optical systems for the Shenguang-III prototype facility (oral paper) / Zeping Yang ... [et al.]. Adaptive optics control of solid-state lasers (poster paper) / Walter Lubeigt ... [et al.]. Gerchberg-Saxton algorithm for multimode beam reshaping (poster paper) / Inna V. Ilyina, Tatyana Yu. Cherezova. New algorithm of combining for spatial coherent beams (poster paper) / Ruofu Yang ... [et al.]. Intracavity mode control of a solid-state laser using a 19-element deformable mirror (poster paper) / Ping Yang ... [et al.] -- pt. 6. Adaptive optics in communication and atmospheric compensation. Fourier image sharpness sensor for laser communications (oral paper) / Kristin N. Walker and Robert K. Tyson. Fast closed-loop adaptive optics system for imaging through strong turbulence layers (oral paper) / Ivo Buske and Wolfgang Riede. Correction of wavefront aberrations and optical communication using aperture synthesis (oral paper) / R. J. Eastwood ... [et al.]. Adaptive optics system for a small telescope (oral paper) / G. Vdovin, M. Loktev and O. Soloviev. Fast correction of atmospheric turbulence using a membrane deformable mirror (poster paper) / Ivan Capraro, Stefano Bonora, Paolo Villoresi. Atmospheric turbulence measurements over a 3km horizontal path with a Shack-Hartmann wavefront sensor (poster paper) / Ruth Mackey, K. Murphy and Chris Dainty. Field-oriented wavefront sensor for laser guide stars (poster paper) / Lidija Bolbasova, Alexander Goncharov and Vladimir Lukin.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

A novel compact model for on-chip stacked transformers in RF-CMOS technology

NASA Astrophysics Data System (ADS)

Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

2013-08-01

A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

Reflecting on the mirror neuron system in autism: a systematic review of current theories.

PubMed

Hamilton, Antonia F de C

2013-01-01

There is much interest in the claim that dysfunction of the mirror neuron system in individuals with autism spectrum condition causes difficulties in social interaction and communication. This paper systematically reviews all published studies using neuroscience methods (EEG/MEG/TMS/eyetracking/EMG/fMRI) to examine the integrity of the mirror system in autism. 25 suitable papers are reviewed. The review shows that current data are very mixed and that studies using weakly localised measures of the integrity of the mirror system are hard to interpret. The only well localised measure of mirror system function is fMRI. In fMRI studies, those using emotional stimuli have reported group differences, but studies using non-emotional hand action stimuli do not. Overall, there is little evidence for a global dysfunction of the mirror system in autism. Current data can be better understood under an alternative model in which social top-down response modulation is abnormal in autism. The implications of this model and future research directions are discussed. Copyright © 2012 Elsevier Ltd. All rights reserved.

Demonstration of lithography patterns using reflective e-beam direct write

NASA Astrophysics Data System (ADS)

Freed, Regina; Sun, Jeff; Brodie, Alan; Petric, Paul; McCord, Mark; Ronse, Kurt; Haspeslagh, Luc; Vereecke, Bart

2011-04-01

Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this work, we report on the development and current status of a new maskless, direct write e-beam lithography tool which has the potential for high volume lithography at and below the 22 nm technology node. A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The lens elements on the DPG are fabricated at IMEC (Leuven, Belgium) under IMEC's CMORE program. The CMOS fabricated DPG contains ~ 1,000,000 lens elements, allowing for 1,000,000 individually controllable beamlets. A single lens element consists of 5 electrodes, each of which can be set at controlled voltage levels to either absorb or reflect the electron beam. A system using a linear movable stage and the DPG integrated into the electron optics module was used to expose patterns on device representative wafers. Results of these exposure tests are discussed.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

SU-D-BRC-07: System Design for a 3D Volumetric Scintillation Detector Using SCMOS Cameras

DOE Office of Scientific and Technical Information (OSTI.GOV)

Darne, C; Robertson, D; Alsanea, F

2016-06-15

Purpose: The purpose of this project is to build a volumetric scintillation detector for quantitative imaging of 3D dose distributions of proton beams accurately in near real-time. Methods: The liquid scintillator (LS) detector consists of a transparent acrylic tank (20×20×20 cm{sup 3}) filled with a liquid scintillator that when irradiated with protons generates scintillation light. To track rapid spatial and dose variations in spot scanning proton beams we used three scientific-complementary metal-oxide semiconductor (sCMOS) imagers (2560×2160 pixels). The cameras collect optical signal from three orthogonal projections. To reduce system footprint two mirrors oriented at 45° to the tank surfaces redirectmore » scintillation light to cameras for capturing top and right views. Selection of fixed focal length objective lenses for these cameras was based on their ability to provide large depth of field (DoF) and required field of view (FoV). Multiple cross-hairs imprinted on the tank surfaces allow for image corrections arising from camera perspective and refraction. Results: We determined that by setting sCMOS to 16-bit dynamic range, truncating its FoV (1100×1100 pixels) to image the entire volume of the LS detector, and using 5.6 msec integration time imaging rate can be ramped up to 88 frames per second (fps). 20 mm focal length lens provides a 20 cm imaging DoF and 0.24 mm/pixel resolution. Master-slave camera configuration enable the slaves to initiate image acquisition instantly (within 2 µsec) after receiving a trigger signal. A computer with 128 GB RAM was used for spooling images from the cameras and can sustain a maximum recording time of 2 min per camera at 75 fps. Conclusion: The three sCMOS cameras are capable of high speed imaging. They can therefore be used for quick, high-resolution, and precise mapping of dose distributions from scanned spot proton beams in three dimensions.« less

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Behavioral Model of Spin-Transfer Torque Driven Oscillation in a Nanomagnet

NASA Astrophysics Data System (ADS)

Buford, Benjamin; Jander, Albrecht; Dhagat, Pallavi

2011-10-01

We present a model written in Verilog-A, a behavioral description language, for spin-torque driven oscillations in a nanomagnet. Recent experiments have shown that spin-polarized current passing through a nanomagnet can cause magnetic dynamics from transfer of spin angular momentum. This can result in steady state oscillation of the magnetization at microwave frequencies [1]. Such spin torque oscillators are of interest due to the ability to rapidly tune their operating frequency by adjusting the applied magnetic field and their compatibility with existing CMOS fabrication methods. Our model is based upon the Landau-Lifshitz-Gilbert dynamics of a single- domain nanomagnet [2] and includes thermal agitation. We demonstrate the ability to model small angle, large angle, and out-of-plane precession. Additionally, we characterize the field and current boundaries between these regimes. Our Verilog-A model can be used in industry standard simulation tools alongside CMOS device models to simulate circuits that combine spintronic devices with CMOS control and processing circuitry. [4pt] [1] S. I. Kiselev et al., Nature, Vol. 425, pp. 380(3), (2003). [0pt] [2] L. Engelbrecht, Ph.D. Dissertation, Dept. Elect. Eng., Oregon State Univ., Corvallis, OR, (2011).

Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

NASA Astrophysics Data System (ADS)

Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

2009-05-01

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

A CMOS-based high-resolution fluoroscope (HRF) detector prototype with 49.5μm pixels for use in endovascular image guided interventions (EIGI)

NASA Astrophysics Data System (ADS)

Russ, M.; Shankar, A.; Setlur Nagesh, S. V.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

2017-03-01

X-ray detectors to meet the high-resolution requirements for endovascular image-guided interventions (EIGIs) are being developed and evaluated. A new 49.5-micron pixel prototype detector is being investigated and compared to the current suite of high-resolution fluoroscopic (HRF) detectors. This detector featuring a 300-micron thick CsI(Tl) scintillator, and low electronic noise CMOS readout is designated the HRF- CMOS50. To compare the abilities of this detector with other existing high resolution detectors, a standard performance metric analysis was applied, including the determination of the modulation transfer function (MTF), noise power spectra (NPS), noise equivalent quanta (NEQ), and detective quantum efficiency (DQE) for a range of energies and exposure levels. The advantage of the smaller pixel size and reduced blurring due to the thin phosphor was exemplified when the MTF of the HRF-CMOS50 was compared to the other high resolution detectors, which utilize larger pixels, other optical designs or thicker scintillators. However, the thinner scintillator has the disadvantage of a lower quantum detective efficiency (QDE) for higher diagnostic x-ray energies. The performance of the detector as part of an imaging chain was examined by employing the generalized metrics GMTF, GNEQ, and GDQE, taking standard focal spot size and clinical imaging parameters into consideration. As expected, the disparaging effects of focal spot unsharpness, exacerbated by increasing magnification, degraded the higher-frequency performance of the HRF-CMOS50, while increasing scatter fraction diminished low-frequency performance. Nevertheless, the HRF-CMOS50 brings improved resolution capabilities for EIGIs, but would require increased sensitivity and dynamic range for future clinical application.

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

PubMed

Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

2012-01-01

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

Integration of nanostructured planar diffractive lenses dedicated to near infrared detection for CMOS image sensors.

PubMed

Lopez, Thomas; Massenot, Sébastien; Estribeau, Magali; Magnan, Pierre; Pardo, Fabrice; Pelouard, Jean-Luc

2016-04-18

This paper deals with the integration of metallic and dielectric nanostructured planar lenses into a pixel from a silicon based CMOS image sensor, for a monochromatic application at 1.064 μm. The first is a Plasmonic Lens, based on the phase delay through nanoslits, which has been found to be hardly compatible with current CMOS technology and exhibits a notable metallic absorption. The second is a dielectric Phase-Fresnel Lens integrated at the top of a pixel, it exhibits an Optical Efficiency (OE) improved by a few percent and an angle of view of 50°. The third one is a metallic diffractive lens integrated inside a pixel, which shows a better OE and an angle of view of 24°. The last two lenses exhibit a compatibility with a spectral band close to 1.064 μm.

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.

PubMed

Wong, A K Y; Kong-Pang Pun; Yuan-Ting Zhang; Ka Nang Leung

2008-12-01

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

A two-dimensional location method based on digital micromirror device used in interactive projection systems

NASA Astrophysics Data System (ADS)

Chen, Liangjun; Ni, Kai; Zhou, Qian; Cheng, Xuemin; Ma, Jianshe; Gao, Yuan; Sun, Peng; Li, Yi; Liu, Minxia

2010-11-01

Interactive projection systems based on CCD/CMOS have been greatly developed in recent years. They can locate and trace the movement of a pen equipped with an infrared LED, and displays the user's handwriting or react to the user's operation in real time. However, a major shortcoming is that the location device and the projector are independent with each other, including both the optical system and the control system. This requires construction of two optical systems, calibration of the differences between the projector view and the camera view, and also synchronization between two control systems, etc. In this paper, we introduced a two-dimensional location method based on digital micro-mirror device (DMD). The DMD is used as the display device and the position detector in turn. By serially flipping the micro-mirrors on the DMD according to a specially designed scheme and monitoring the reflected light energy, the image spot of the infrared LED can be quickly located. By using this method, the same optical system as well as the DMD can be multiplexed for projection and location, which will reduce the complexity and cost of the whole system. Furthermore, this method can also achieve high positioning accuracy and sampling rates. The results of location experiments are given.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

NASA Astrophysics Data System (ADS)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

MMW/THz imaging using upconversion to visible, based on glow discharge detector array and CCD camera

NASA Astrophysics Data System (ADS)

Aharon, Avihai; Rozban, Daniel; Abramovich, Amir; Yitzhaky, Yitzhak; Kopeika, Natan S.

2017-10-01

An inexpensive upconverting MMW/THz imaging method is suggested here. The method is based on glow discharge detector (GDD) and silicon photodiode or simple CCD/CMOS camera. The GDD was previously found to be an excellent room-temperature MMW radiation detector by measuring its electrical current. The GDD is very inexpensive and it is advantageous due to its wide dynamic range, broad spectral range, room temperature operation, immunity to high power radiation, and more. An upconversion method is demonstrated here, which is based on measuring the visual light emitting from the GDD rather than its electrical current. The experimental setup simulates a setup that composed of a GDD array, MMW source, and a basic CCD/CMOS camera. The visual light emitting from the GDD array is directed to the CCD/CMOS camera and the change in the GDD light is measured using image processing algorithms. The combination of CMOS camera and GDD focal plane arrays can yield a faster, more sensitive, and very inexpensive MMW/THz camera, eliminating the complexity of the electronic circuits and the internal electronic noise of the GDD. Furthermore, three dimensional imaging systems based on scanning prohibited real time operation of such imaging systems. This is easily solved and is economically feasible using a GDD array. This array will enable us to acquire information on distance and magnitude from all the GDD pixels in the array simultaneously. The 3D image can be obtained using methods like frequency modulation continuous wave (FMCW) direct chirp modulation, and measuring the time of flight (TOF).

Electro-Formed Mirrors for Both X-Ray and Visible Astronomy

NASA Technical Reports Server (NTRS)

Ritter, J.; Smith, W. Scott; Rose, M. Frank (Technical Monitor)

2000-01-01

The Space Optics Manufacturing Technology Center of NASA's Marshall Space Flight Center is involved in the development of nickel and nickel alloy electroformed mirrors for rapid production of space-based optical systems. The current state of the process is discussed- for both cylindrical x-ray mirrors and normal incidence mirrors for visible and infrared applications.

Automated alignment system for optical wireless communication systems using image recognition.

PubMed

Brandl, Paul; Weiss, Alexander; Zimmermann, Horst

2014-07-01

In this Letter, we describe the realization of a tracked line-of-sight optical wireless communication system for indoor data distribution. We built a laser-based transmitter with adaptive focus and ray steering by a microelectromechanical systems mirror. To execute the alignment procedure, we used a CMOS image sensor at the transmitter side and developed an algorithm for image recognition to localize the receiver's position. The receiver is based on a self-developed optoelectronic integrated chip with low requirements on the receiver optics to make the system economically attractive. With this system, we were able to set up the communication link automatically without any back channel and to perform error-free (bit error rate <10⁻⁹) data transmission over a distance of 3.5 m with a data rate of 3 Gbit/s.

Design of optical axis jitter control system for multi beam lasers based on FPGA

NASA Astrophysics Data System (ADS)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Development of mirror coatings for gravitational-wave detectors

NASA Astrophysics Data System (ADS)

Steinlechner, J.

2018-05-01

Gravitational waves are detected by measuring length changes between mirrors in the arms of kilometre-long Michelson interferometers. Brownian thermal noise arising from thermal vibrations of the mirrors can limit the sensitivity to distance changes between the mirrors, and, therefore, the ability to measure gravitational-wave signals. Thermal noise arising from the highly reflective mirror coatings will limit the sensitivity both of current detectors (when they reach design performance) and of planned future detectors. Therefore, the development of coatings with low thermal noise, which at the same time meet strict optical requirements, is of great importance. This article gives an overview of the current status of coatings and of the different approaches for coating improvement. This article is part of a discussion meeting issue `The promises of gravitational-wave astronomy'.

Development of mirror coatings for gravitational-wave detectors.

PubMed

Steinlechner, J

2018-05-28

Gravitational waves are detected by measuring length changes between mirrors in the arms of kilometre-long Michelson interferometers. Brownian thermal noise arising from thermal vibrations of the mirrors can limit the sensitivity to distance changes between the mirrors, and, therefore, the ability to measure gravitational-wave signals. Thermal noise arising from the highly reflective mirror coatings will limit the sensitivity both of current detectors (when they reach design performance) and of planned future detectors. Therefore, the development of coatings with low thermal noise, which at the same time meet strict optical requirements, is of great importance. This article gives an overview of the current status of coatings and of the different approaches for coating improvement.This article is part of a discussion meeting issue 'The promises of gravitational-wave astronomy'. © 2018 The Author(s).

What We Know Currently about Mirror Neurons

PubMed Central

Kilner, J.M.; Lemon, R.N.

2013-01-01

Mirror neurons were discovered over twenty years ago in the ventral premotor region F5 of the macaque monkey. Since their discovery much has been written about these neurons, both in the scientific literature and in the popular press. They have been proposed to be the neuronal substrate underlying a vast array of different functions. Indeed so much has been written about mirror neurons that last year they were referred to, rightly or wrongly, as “The most hyped concept in neuroscience”. Here we try to cut through some of this hyperbole and review what is currently known (and not known) about mirror neurons. PMID:24309286

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

PubMed

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-05-02

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide–Semiconductor Image Sensors

PubMed Central

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-01-01

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components. PMID:28468324

Pixel pitch and particle energy influence on the dark current distribution of neutron irradiated CMOS image sensors.

PubMed

Belloir, Jean-Marc; Goiffon, Vincent; Virmontois, Cédric; Raine, Mélanie; Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Molina, Romain; Magnan, Pierre; Gilard, Olivier

2016-02-22

The dark current produced by neutron irradiation in CMOS Image Sensors (CIS) is investigated. Several CIS with different photodiode types and pixel pitches are irradiated with various neutron energies and fluences to study the influence of each of these optical detector and irradiation parameters on the dark current distribution. An empirical model is tested on the experimental data and validated on all the irradiated optical imagers. This model is able to describe all the presented dark current distributions with no parameter variation for neutron energies of 14 MeV or higher, regardless of the optical detector and irradiation characteristics. For energies below 1 MeV, it is shown that a single parameter has to be adjusted because of the lower mean damage energy per nuclear interaction. This model and these conclusions can be transposed to any silicon based solid-state optical imagers such as CIS or Charged Coupled Devices (CCD). This work can also be used when designing an optical imager instrument, to anticipate the dark current increase or to choose a mitigation technique.

Adaptive optics ophthalmologic systems using dual deformable mirrors

NASA Astrophysics Data System (ADS)

Jones, S. M.; Olivier, S.; Chen, D.; Joeres, S.; Sadda, S.; Zawadzki, R. J.; Werner, J. S.; Miller, D. T.

2007-02-01

Adaptive Optics (AO) have been increasingly combined with a variety of ophthalmic instruments over the last decade to provide cellular-level, in-vivo images of the eye. The use of MEMS deformable mirrors in these instruments has recently been demonstrated to reduce system size and cost while improving performance. However, currently available MEMS mirrors lack the required range of motion for correcting large ocular aberrations, such as defocus and astigmatism. In order to address this problem, we have developed an AO system architecture that uses two deformable mirrors, in a woofer / tweeter arrangement, with a bimorph mirror as the woofer and a MEMS mirror as the tweeter. This setup provides several advantages, including extended aberration correction range, due to the large stroke of the bimorph mirror, high order aberration correction using the MEMS mirror, and additionally, the ability to 'focus' through the retina. This AO system architecture is currently being used in four instruments, including an Optical Coherence Tomography (OCT) system and a retinal flood-illuminated imaging system at the UC Davis Medical Center, a Scanning Laser Ophthalmoscope (SLO) at the Doheny Eye Institute, and an OCT system at Indiana University. The design, operation and evaluation of this type of AO system architecture will be presented.

A focal plane metrology system and PSF centroiding experiment

NASA Astrophysics Data System (ADS)

Li, Haitao; Li, Baoquan; Cao, Yang; Li, Ligang

2016-10-01

In this paper, we present an overview of a detector array equipment metrology testbed and a micro-pixel centroiding experiment currently under development at the National Space Science Center, Chinese Academy of Sciences. We discuss on-going development efforts aimed at calibrating the intra-/inter-pixel quantum efficiency and pixel positions for scientific grade CMOS detector, and review significant progress in achieving higher precision differential centroiding for pseudo star images in large area back-illuminated CMOS detector. Without calibration of pixel positions and intrapixel response, we have demonstrated that the standard deviation of differential centroiding is below 2.0e-3 pixels.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness.

PubMed

Cao, Q; Brehler, M; Sisniega, A; Stayman, J W; Yorkston, J; Siewerdsen, J H; Zbijewski, W

2017-03-01

CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μ m, ~80 μ m and ~40 μ m, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μ m pixels) with CsI scintillator thicknesses of 400 μ m and 700 μ m, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6-5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μ m scintillator compared to the standard nominal CsI thickness of 700 μ m. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index ( d' 2 ) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μ m CsI compared to 700 μ m CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μ m panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μ m scinitllator. Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μ m CsI onto the clinical prototype of CMOS-based extremity CBCT.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness

PubMed Central

Cao, Q.; Brehler, M.; Sisniega, A.; Stayman, J. W.; Yorkston, J.; Siewerdsen, J. H.; Zbijewski, W.

2017-01-01

Purpose CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. Methods A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μm, ~80 μm and ~40 μm, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μm pixels) with CsI scintillator thicknesses of 400 μm and 700 μm, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6–5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Results Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μm scintillator compared to the standard nominal CsI thickness of 700 μm. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index (d′2) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μm CsI compared to 700 μm CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μm panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μm scinitllator. Conclusion Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μm CsI onto the clinical prototype of CMOS-based extremity CBCT. PMID:28989220

WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Q; Brehler, M; Sisniega, A

Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection)more » using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high-frequency imaging tasks through adoption of the CMOS detector and small FS x-ray source, motivating the use of these components in a new system for quantitative in-vivo imaging of trabecular bone. Financial Support: US NIH grant R01EB018896. Qian Cao is a Howard Hughes Medical Institute International Student Research Fellow. Disclosures: W Zbijewski, J Siewerdsen and A Sisniega receive research funding from Carestream Health.« less

EAGLE: relay mirror technology development

NASA Astrophysics Data System (ADS)

Hartman, Mary; Restaino, Sergio R.; Baker, Jeffrey T.; Payne, Don M.; Bukley, Jerry W.

2002-06-01

EAGLE (Evolutionary Air & Space Global Laser Engagement) is the proposed high power weapon system with a high power laser source, a relay mirror constellation, and the necessary ground and communications links. The relay mirror itself will be a satellite composed of two optically-coupled telescopes/mirrors used to redirect laser energy from ground, air, or space based laser sources to distant points on the earth or space. The receiver telescope captures the incoming energy, relays it through an optical system that cleans up the beam, then a separate transmitter telescope/mirror redirects the laser energy at the desired target. Not only is it a key component in extending the range of DoD's current laser weapon systems, it also enables ancillary missions. Furthermore, if the vacuum of space is utilized, then the atmospheric effects on the laser beam propagation will be greatly attenuated. Finally, several critical technologies are being developed to make the EAGLE/Relay Mirror concept a reality, and the Relay Mirror Technology Development Program was set up to address them. This paper will discuss each critical technology, the current state of the work, and the future implications of this program.

Axisymmetric MHD-stable Mirror as a Neutron Source and a Fusion Reactor

ScienceCinema

Dr. Dmitri Ryutov

2018-04-17

Dr. Ryutov discusses the concept of axisymmetric mirrors and presents an overview of current experiments and theories. Particular attention is paid to MHD stabilization and the advantages and disadvantages of using mirrors. Future work is identified and further discussed.

Understanding the role of mirror neurons in action understanding will require more than a domain-general account.

PubMed

Martin, Alia; Santos, Laurie R

2014-04-01

Cook et al. propose that mirror neurons emerge developmentally through a domain-general associative mechanism. We argue that experience-sensitivity does not rule out an adaptive or genetic argument for mirror neuron function, and that current evidence suggests that mirror neurons are more specialized than the authors' account would predict. We propose that future work integrate behavioral and neurophysiological techniques used with primates to examine the proposed functions of mirror neurons in action understanding.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

MEMS compatible illumination and imaging micro-optical systems

NASA Astrophysics Data System (ADS)

Bräuer, A.; Dannberg, P.; Duparré, J.; Höfer, B.; Schreiber, P.; Scholles, M.

2007-01-01

The development of new MOEMS demands for cooperation between researchers in micromechanics, optoelectronics and microoptics at a very early state. Additionally, microoptical technologies being compatible with structured silicon have to be developed. The microoptical technologies used for two silicon based microsystems are described in the paper. First, a very small scanning laser projector with a volume of less than 2 cm 3, which operates with a directly modulated lasers collimated with a microlens, is shown. The laser radiation illuminates a 2D-MEMS scanning mirror. The optical design is optimized for high resolution (VGA). Thermomechanical stability is realized by design and using a structured ceramics motherboard. Secondly, an ultrathin CMOS-camera having an insect inspired imaging system has been realized. It is the first experimental realization of an artificial compound eye. Micro-optical design principles and technology is used. The overall thickness of the imaging system is only 320 μm, the diagonal field of view is 21°, and the f-number is 2.6. The monolithic device consists of an UV-replicated microlens array upon a thin silica substrate with a pinhole array in a metal layer on the back side. The pitch of the pinholes differs from that of the lens array to provide individual viewing angle for each channel. The imaging chip is directly glued to a CMOS sensor with adapted pitch. The whole camera is less than 1mm thick. New packaging methods for these systems are under development.

NASA Tech Briefs, March 2009

NASA Technical Reports Server (NTRS)

2009-01-01

Topics covered include: Improved Instrument for Detecting Water and Ice in Soil; Real-Time Detection of Dust Devils from Pressure Readings; Determining Surface Roughness in Urban Areas Using Lidar Data; DSN Data Visualization Suite; Hamming and Accumulator Codes Concatenated with MPSK or QAM; Wide-Angle-Scanning Reflectarray Antennas Actuated by MEMS; Biasable Subharmonic Membrane Mixer for 520 to 600 GHz; Hardware Implementation of Serially Concatenated PPM Decoder; Symbolic Processing Combined with Model-Based Reasoning; Presentation Extensions of the SOAP; Spreadsheets for Analyzing and Optimizing Space Missions; Processing Ocean Images to Detect Large Drift Nets; Alternative Packaging for Back-Illuminated Imagers; Diamond Machining of an Off-Axis Biconic Aspherical Mirror; Laser Ablation Increases PEM/Catalyst Interfacial Area; Damage Detection and Self-Repair in Inflatable/Deployable Structures; Polyimide/Glass Composite High-Temperature Insulation; Nanocomposite Strain Gauges Having Small TCRs; Quick-Connect Windowed Non-Stick Penetrator Tips for Rapid Sampling; Modeling Unsteady Cavitation and Dynamic Loads in Turbopumps; Continuous-Flow System Produces Medical-Grade Water; Discrimination of Spore-Forming Bacilli Using spoIVA; nBn Infrared Detector Containing Graded Absorption Layer; Atomic References for Measuring Small Accelerations; Ultra-Broad-Band Optical Parametric Amplifier or Oscillator; Particle-Image Velocimeter Having Large Depth of Field; Enhancing SERS by Means of Supramolecular Charge Transfer; Improving 3D Wavelet-Based Compression of Hyperspectral Images; Improved Signal Chains for Readout of CMOS Imagers; SOI CMOS Imager with Suppression of Cross-Talk; Error-Rate Bounds for Coded PPM on a Poisson Channel; Biomorphic Multi-Agent Architecture for Persistent Computing; and Using Covariance Analysis to Assess Pointing Performance.

Large-Scale High-Resolution Cylinder Wake Measurements in a Wind Tunnel using Tomographic PIV with sCMOS Cameras

NASA Astrophysics Data System (ADS)

Michaelis, Dirk; Schroeder, Andreas

2012-11-01

Tomographic PIV has triggered vivid activity, reflected in a large number of publications, covering both: development of the technique and a wide range of fluid dynamic experiments. Maturing of tomo PIV allows the application in medium to large scale wind tunnels. Limiting factor for wind tunnel application is the small size of the measurement volume, being typically about of 50 × 50 × 15 mm3. Aim of this study is the optimization towards large measurement volumes and high spatial resolution performing cylinder wake measurements in a 1 meter wind tunnel. Main limiting factors for the volume size are the laser power and the camera sensitivity. So, a high power laser with 800 mJ per pulse is used together with low noise sCMOS cameras, mounted in forward scattering direction to gain intensity due to the Mie scattering characteristics. A mirror is used to bounce the light back, to have all cameras in forward scattering. Achievable particle density is growing with number of cameras, so eight cameras are used for a high spatial resolution. Optimizations lead to volume size of 230 × 200 × 52 mm3 = 2392 cm3, more than 60 times larger than previously. 281 × 323 × 68 vectors are calculated with spacing of 0.76 mm. The achieved measurement volume size and spatial resolution is regarded as a major step forward in the application of tomo PIV in wind tunnels. Supported by EU-project: no. 265695.

A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2014-01-01

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

Sneaking a peek: pigeons use peripheral vision (not mirrors) to find hidden food.

PubMed

Ünver, Emre; Garland, Alexis; Tabrik, Sepideh; Güntürkün, Onur

2017-07-01

A small number of species are capable of recognizing themselves in the mirror when tested with the mark-and-mirror test. This ability is often seen as evidence of self-recognition and possibly even self-awareness. Strangely, a number of species, for example monkeys, pigs and dogs, are unable to pass the mark test but can locate rewarding objects by using the reflective properties of a mirror. Thus, these species seem to understand how a visual reflection functions but cannot apply it to their own image. We tested this discrepancy in pigeons-a species that does not spontaneously pass the mark test. Indeed, we discovered that pigeons can successfully find a hidden food reward using only the reflection, suggesting that pigeons can also use and potentially understand the reflective properties of mirrors, even in the absence of self-recognition. However, tested under monocular conditions, the pigeons approached and attempted to walk through the mirror rather than approach the physical food, displaying similar behavior to patients with mirror agnosia. These findings clearly show that pigeons do not use the reflection of mirrors to locate reward, but actually see the food peripherally with their near-panoramic vision. A re-evaluation of our current understanding of mirror-mediated behavior might be necessary-especially taking more fully into account species differences in visual field. This study suggests that use of reflections in a mirrored surface as a tool may be less widespread than currently thought.

Mirror agnosia and the mirrored-self misidentification delusion: a hypnotic analogue.

PubMed

Connors, Michael H; Cox, Rochelle E; Barnier, Amanda J; Langdon, Robyn; Coltheart, Max

2012-05-01

Mirrored-self misidentification is the delusional belief that one's reflection in the mirror is a stranger. Current theories suggest that one pathway to the delusion is mirror agnosia (a deficit in which patients are unable to use mirror knowledge when interacting with mirrors). This study examined whether a hypnotic suggestion for mirror agnosia can recreate features of the delusion. Ten high hypnotisable participants were given either a suggestion to not understand mirrors or to see the mirror as a window. Participants were asked to look into a mirror and describe what they saw. Participants were tested on their understanding of mirrors and received a series of challenges. Participants then received a detailed postexperimental inquiry. Three of five participants given the suggestion to not understand mirrors reported seeing a stranger and maintained this belief when challenged. These participants also showed signs of mirror agnosia. No participants given the suggestion to see a window reported seeing a stranger. Results indicate that a hypnotic suggestion for mirror agnosia can be used to recreate the mirrored-self misidentification delusion. Factors influencing the effectiveness of hypnotic analogues of psychopathology, such as participants' expectations and interpretations, are discussed.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

Electroformed Nickel Mirrors for the Next Generation Space Telescope

NASA Technical Reports Server (NTRS)

Redmon, John W.; Engelhaupt, Darrel

1998-01-01

This paper summarizes the work to date on a novel mirror fabrication technique being developed at the Marshall Space Flight Center for potential use on the Next Generation Space Telescope (NGST). This technique involves forming an extremely lightweight mirror by electroplating nickel and nickel based alloys onto a highly polished precision mandrel. The resulting mirror shell can then be backed up with or attached to a lightweight structure to produce a mirror element that is on the order of 15 kg/sq m areal density. Since the mirrors are fabricated from a mandrel (or master), subsequent mirrors can be made with very high economy; this technique is particularly suited to segmented mirrors schemes whereby large apertures are achieved through the deployment of smaller segments. Control of the electroplating process is the key element for producing high quality optics; bath chemistry and real time control of the plating current density yields uniform grained electroforms with zero residual stress. To accomplish this, a special electronic sensor was developed whereby the residual stress can be monitored as the nickel is electrolytically deposited. This information is used in a feedback loop to modulate current density which, in turn, directly governs the residual stress. Details pertaining to this and other aspects of the fabrication of a half meter mirror will be published along with test results and metrology data.

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

NASA Astrophysics Data System (ADS)

Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

2017-02-01

This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

Progress Report on the University of Arizona NGST Mirror System Demonstrator

NASA Technical Reports Server (NTRS)

Baiocchi, Dave; Burge, Jim; Cuerden, Brian; Stahl, Philip (Technical Monitor)

2002-01-01

We will present an update for the University of Arizona NGST (Next Generation Space Telescope) Mirror System Demonstrator (NMSD). The 2-m, f/5 NMSD mirror uses a 2 mm thick glass substrate and an actuated lightweight structure for surface accuracy and support. We will review the mirror's basic design and summarize the fabrication process. We will also discuss the current results from system integration and testing.

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation.

PubMed

Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

2017-06-02

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-µm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping,analogcalibration,nordigitalcompensationtechnique. Whencoupledtoa2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW.

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation †

PubMed Central

Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

2017-01-01

Infrared imaging technology, used both to study deep-space bodies’ radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a 2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW. PMID:28574466

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

Material Targets for Scaling All-Spin Logic

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Recent progress and development of a speedster-EXD: a new event-triggered hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2015-08-01

We present the characterization of a new event-driven X-ray hybrid CMOS detector developed by Penn State University in collaboration with Teledyne Imaging Sensors. Along with its low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up, the Speedster-EXD has been designed with the capability to limit its readout to only those pixels containing charge, thus enabling even faster effective frame rates. The threshold for the comparator in each pixel can be set by the user so that only pixels with signal above the set threshold are read out. The Speedster-EXD hybrid CMOS detector also has two new in-pixel features that reduce noise from known noise sources: (1) a low-noise, high-gain CTIA amplifier to eliminate crosstalk from interpixel capacitance (IPC) and (2) in-pixel CDS subtraction to reduce kTC noise. We present the read noise, dark current, IPC, energy resolution, and gain variation measurements of one Speedster-EXD detector.

CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

PubMed

Li, Haitao; Boling, C Sam; Mason, Andrew J

2016-08-01

Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Ma, Wuying; Huang, Shaoyan

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a {sup 60}Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo responsemore » non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, H.; Benoit, M.; Chen, H.

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE PAGES

Liu, H.; Benoit, M.; Chen, H.; ...

2017-01-11

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

NASA Astrophysics Data System (ADS)

Dwi Kurniawan, Erry; Peng, Kang-Hui; Yang, Shang-Yi; Yang, Yi-Yun; Thirunavukkarasu, Vasanthan; Lin, Yu-Hsien; Wu, Yung-Chun

2018-04-01

We propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (F Wp = F Wn). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant for the application of the CMOS inverter and static random access memory (SRAM) application technology.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Wang, Zujun; Ma, Wuying; Huang, Shaoyan; Yao, Zhibin; Liu, Minbo; He, Baoping; Liu, Jing; Sheng, Jiangkun; Xue, Yuan

2016-03-01

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

PubMed Central

Chang, Sheng-Ren; Chen, Hsin

2009-01-01

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times. PMID:22408508

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

An introduction to the water recovery x-ray rocket

NASA Astrophysics Data System (ADS)

Miles, Drew M.; McEntaffer, Randall L.; Schultz, Ted B.; Donovan, Benjamin D.; Tutt, James H.; Yastishock, Daniel; Steiner, Tyler; Hillman, Christopher R.; McCoy, Jake A.; Wages, Mitchell; Hull, Sam; Falcone, Abe; Burrows, David N.; Chattopadhyay, Tanmoy; Anderson, Tyler; McQuaide, Maria

2017-08-01

The Water Recovery X-ray Rocket (WRXR) is a sounding rocket payload that will launch from the Kwajalein Atoll in April 2018 and seeks to be the first astrophysics sounding rocket payload to be water recovered by NASA. WRXR's primary instrument is a grating spectrometer that consists of a mechanical collimator, X-ray reflection gratings, grazing-incidence mirrors, and a hybrid CMOS detector. The instrument will obtain a spectrum of the diffuse soft X-ray emission from the northern part of the Vela supernova remnant and is optimized for 3rd and 4th order OVII emission. Utilizing a field of view of 3.25° × 3.25° and resolving power of λ/δλ ≍40-50 in the lines of interest, the WRXR spectrometer aims to achieve the most highly-resolved spectrum of Vela's diffuse soft X-ray emission. This paper presents introductions to the payload and the science target.

Optimum Design Rules for CMOS Hall Sensors

PubMed Central

Crescentini, Marco; Biondi, Michele; Romani, Aldo; Tartagni, Marco; Sangiorgi, Enrico

2017-01-01

This manuscript analyzes the effects of design parameters, such as aspect ratio, doping concentration and bias, on the performance of a general CMOS Hall sensor, with insight on current-related sensitivity, power consumption, and bandwidth. The article focuses on rectangular-shaped Hall probes since this is the most general geometry leading to shape-independent results. The devices are analyzed by means of 3D-TCAD simulations embedding galvanomagnetic transport model, which takes into account the Lorentz force acting on carriers due to a magnetic field. Simulation results define a set of trade-offs and design rules that can be used by electronic designers to conceive their own Hall probes. PMID:28375191

Optimum Design Rules for CMOS Hall Sensors.

PubMed

Crescentini, Marco; Biondi, Michele; Romani, Aldo; Tartagni, Marco; Sangiorgi, Enrico

2017-04-04

This manuscript analyzes the effects of design parameters, such as aspect ratio, doping concentration and bias, on the performance of a general CMOS Hall sensor, with insight on current-related sensitivity, power consumption, and bandwidth. The article focuses on rectangular-shaped Hall probes since this is the most general geometry leading to shape-independent results. The devices are analyzed by means of 3D-TCAD simulations embedding galvanomagnetic transport model, which takes into account the Lorentz force acting on carriers due to a magnetic field. Simulation results define a set of trade-offs and design rules that can be used by electronic designers to conceive their own Hall probes.

The DUV Stability of Superlattice-Doped CMOS Detector Arrays

NASA Technical Reports Server (NTRS)

Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

2013-01-01

JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel.

PubMed

Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien

2017-12-05

A submicron pixel's light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e - /s at 60 °C, an ultra-low read noise of 0.90 e - ·rms, a high full well capacity (FWC) of 4100 e - , and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Bendable X-ray Optics for High Resolution Imaging

NASA Technical Reports Server (NTRS)

Gubarev, M.; Ramsey, B.; Kilaru, K.; Atkins, C.; Broadway, D.

2014-01-01

Current state-of the-art for x-ray optics fabrication calls for either the polishing of massive substrates into high-angular-resolution mirrors or the replication of thin, lower-resolution, mirrors from perfectly figured mandrels. Future X-ray Missions will require a change in this optics fabrication paradigm in order to achieve sub-arcsecond resolution in light-weight optics. One possible approach to this is to start with perfectly flat, light-weight surface, bend it into a perfect cone, form the desired mirror figure by material deposition, and insert the resulting mirror into a telescope structure. Such an approach is currently being investigated at MSFC, and a status report will be presented detailing the results of finite element analyses, bending tests and differential deposition experiments.

Secondary concentrators for parabolic dish solar thermal power systems

NASA Technical Reports Server (NTRS)

Jaffe, L. D.; Poon, P. T.

1981-01-01

A variety of different concepts are currently being studied with the objective to lower the cost of parabolic mirrors and to provide alternatives. One of the considered approaches involves the use of compound concentrators. A compound solar concentrator is a concentrator in which the sunlight is reflected or refracted more than once. It consists of a primary mirror or lens, whose aperture determines the amount of sunlight gathered, and a smaller secondary mirror or lens. Additional small optical elements may also be incorporated. The possibilities and problems regarding a use of compound concentrators in parabolic dish systems are discussed. Attention is given to concentrating secondary lenses, secondary imaging and concentrating mirrors, conical secondary mirrors, compound elliptic secondary concentrating mirrors, and hyperbolic trumpet secondary concentrating mirrors.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization.

PubMed

Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C; Patel, Tushita

2015-11-01

Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50-300 e-) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). In this study, imaging performance of a large area (29×23 cm2) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165-400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. The LFW mode shows better DQE at low air kerma (Ka<10 μGy) and should be used for DBT. At current DBT applications, air kerma (Ka∼10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165-400 μm in size can be resolved using a MGD range of 0.3-1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for microcalcifications was observed using the Dexela 2923 MAM CMOS APS x-ray imager at a lower MGD (2.0 mGy). The Dexela 2923 MAM CMOS APS x-ray imager is capable to achieve a high imaging performance at spatial frequencies up to 6.7 lp/mm. Microcalcifications of 165 μm are distinguishable based on reported data and their modeling results due to the small pixel pitch of 75 μm. At the same time, potential dose reduction is expected using the studied CMOS APS x-ray imager.

High current proton beams production at Simple Mirror Ion Source 37.

PubMed

Skalyga, V; Izotov, I; Razin, S; Sidorov, A; Golubev, S; Kalvas, T; Koivisto, H; Tarvainen, O

2014-02-01

This paper presents the latest results of high current proton beam production at Simple Mirror Ion Source (SMIS) 37 facility at the Institute of Applied Physics (IAP RAS). In this experimental setup, the plasma is created and the electrons are heated by 37.5 GHz gyrotron radiation with power up to 100 kW in a simple mirror trap fulfilling the ECR condition. Latest experiments at SMIS 37 were performed using a single-aperture two-electrode extraction system. Proton beams with currents up to 450 mA at high voltages below 45 kV were obtained. The maximum beam current density was measured to be 600 mA/cm(2). A possibility of further improvement through the development of an advanced extraction system is discussed.

An integrated open-cavity system for magnetic bead manipulation.

PubMed

Abu-Nimeh, F T; Salem, F M

2013-02-01

Superparamagnetic beads are increasingly used in biomedical assays to manipulate, transport, and maneuver biomaterials. We present a low-cost integrated system designed in bulk CMOS to manipulate and separate biomedical magnetic beads. The system consists of 8 × 8 coil-arrays suitable for single bead manipulation, or collaborative multi-bead manipulation, using pseudo-parallel executions. We demonstrate the flexibility of the design in terms of different coil sizes, DC current levels, and layout techniques. In one array module example, the size of a single coil is 30 μm × 30 μm and the full array occupies an area of 248 μm × 248 μm in 0.5 μm CMOS technology. The programmable DC current source supports 8 discrete levels up to 1.5 mA. The total power consumption of the entire module is 9 mW when running at full power.

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

NASA Astrophysics Data System (ADS)

Ma, Rui; Zheng, Hao; Zhu, Zhangming

2017-08-01

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 k {{Ω }}, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/\\sqrt{{Hz}} (rms), resulting in a very low detectable input current of 1 μA with SNR = 5.

Phase-to-intensity conversion of magnonic spin currents and application to the design of a majority gate

PubMed Central

Brächer, T.; Heussner, F.; Pirro, P.; Meyer, T.; Fischer, T.; Geilen, M.; Heinz, B.; Lägel, B.; Serga, A. A.; Hillebrands, B.

2016-01-01

Magnonic spin currents in the form of spin waves and their quanta, magnons, are a promising candidate for a new generation of wave-based logic devices beyond CMOS, where information is encoded in the phase of travelling spin-wave packets. The direct readout of this phase on a chip is of vital importance to couple magnonic circuits to conventional CMOS electronics. Here, we present the conversion of the spin-wave phase into a spin-wave intensity by local non-adiabatic parallel pumping in a microstructure. This conversion takes place within the spin-wave system itself and the resulting spin-wave intensity can be conveniently transformed into a DC voltage. We also demonstrate how the phase-to-intensity conversion can be used to extract the majority information from an all-magnonic majority gate. This conversion method promises a convenient readout of the magnon phase in future magnon-based devices. PMID:27905539

Performance Evaluation of III-V Hetero/Homojunction Esaki Tunnel Diodes on Si and Lattice Matched Substrates

NASA Astrophysics Data System (ADS)

Thomas, Paul M.

Understanding of quantum tunneling phenomenon in semiconductor systems is increasingly important as CMOS replacement technologies are investigated. This work studies a variety of heterojunction materials and types to increase tunnel currents to CMOS competitive levels and to understand how integration onto Si substrates affects performance. Esaki tunnel diodes were grown by Molecular Beam Epitaxy (MBE) on Si substrates via a graded buffer and control Esaki tunnel diodes grown on lattice matched substrates for this work. Peak current density for each diode is extracted and benchmarked to build an empirical data set for predicting diode performance. Additionally, statistics are used as tool to show peak to valley ratio for the III-V on Si sample and the control perform similarly below a threshold area. This work has applications beyond logic, as multijunction solar cell, heterojunction bipolar transistor, and light emitting diode designs all benefit from better tunnel contact design.

Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

DOEpatents

Welch, James D.

2003-09-23

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Assessing Human Mirror Activity With EEG Mu Rhythm: A Meta-Analysis

PubMed Central

Fox, Nathan A.; Bakermans-Kranenburg, Marian J.; Yoo, Kathryn H.; Bowman, Lindsay C.; Cannon, Erin N.; Vanderwert, Ross E.; Ferrari, Pier F.; van IJzendoorn, Marinus H.

2016-01-01

A fundamental issue in cognitive neuroscience is how the brain encodes others’ actions and intentions. In recent years, a potential advance in our knowledge on this issue is the discovery of mirror neurons in the motor cortex of the nonhuman primate. These neurons fire to both execution and observation of specific types of actions. Researchers use this evidence to fuel investigations of a human mirror system, suggesting a common neural code for perceptual and motor processes. Among the methods used for inferring mirror system activity in humans are changes in a particular frequency band in the electroencephalogram (EEG) called the mu rhythm. Mu frequency appears to decrease in amplitude (reflecting cortical activity) during both action execution and action observation. The current meta-analysis reviewed 85 studies (1,707 participants) of mu that infer human mirror system activity. Results demonstrated significant effect sizes for mu during execution (Cohen’s d = 0.46, N = 701) as well as observation of action (Cohen’s d = 0.31, N = 1,508), confirming a mirroring property in the EEG. A number of moderators were examined to determine the specificity of these effects. We frame these meta-analytic findings within the current discussion about the development and functions of a human mirror system, and conclude that changes in EEG mu activity provide a valid means for the study of human neural mirroring. Suggestions for improving the experimental and methodological approaches in using mu to study the human mirror system are offered. PMID:26689088

Mesmerising mirror neurons.

PubMed

Heyes, Cecilia

2010-06-01

Mirror neurons have been hailed as the key to understanding social cognition. I argue that three currents of thought-relating to evolution, atomism and telepathy-have magnified the perceived importance of mirror neurons. When they are understood to be a product of associative learning, rather than an adaptation for social cognition, mirror neurons are no longer mesmerising, but they continue to raise important questions about both the psychology of science and the neural bases of social cognition. Copyright 2010 Elsevier Inc. All rights reserved.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

PubMed Central

Valente, Virgilio; Demosthenous, Andreas

2016-01-01

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Memory technology survey

NASA Technical Reports Server (NTRS)

1981-01-01

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

Annual Industrial Capabilities Report to Congress

DTIC Science & Technology

1999-02-01

suspension systems is not a concern. Deformable Mirrors (September 1998) The atmosphere, temperature variations, and vibration distort optical system...images. Deformable mirrors can compensate for these effects in real time. They are used in surveillance optics, laser weapons, and astronomical telescopes...This assessment investigated the availability of current and potential deformable mirror producers, and possible alternative technologies. The

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nam, Chang-Yong; Stein, Aaron

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE PAGES

Nam, Chang-Yong; Stein, Aaron

2017-11-15

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

PubMed Central

Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

2017-01-01

A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µVrms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter. PMID:28394289

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

PubMed

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

Advanced technology optical telescopes IV; Proceedings of the Meeting, Tucson, AZ, Feb. 12-16, 1990. Parts 1 & 2

NASA Technical Reports Server (NTRS)

Barr, Lawrence D. (Editor)

1990-01-01

The present conference on the current status of large, advanced-technology optical telescope development and construction projects discusses topics on such factors as their novel optical system designs, the use of phased arrays, seeing and site performance factors, mirror fabrication and testing, pointing and tracking techniques, mirror thermal control, structural design strategies, mirror supports and coatings, and the control of segmented mirrors. Attention is given to the proposed implementation of the VLT Interferometer, the first diffraction-limited astronomical images with adaptive optics, a fiber-optic telescope using a large cross-section image-transmitting bundle, the design of wide-field arrays, Hartmann test data reductions, liquid mirrors, inertial drives for telescope pointing, temperature control of large honeycomb mirrors, evaporative coatings for very large telescope mirrors, and the W. M. Keck telescope's primary mirror active control system software.

Water Cooled Mirror Design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dale, Gregory E.; Holloway, Michael Andrew; Pulliam, Elias Noel

2015-03-30

This design is intended to replace the current mirror setup being used for the NorthStar Moly 99 project in order to monitor the target coupon. The existing setup has limited movement for camera alignment and is difficult to align properly. This proposed conceptual design for a water cooled mirror will allow for greater thermal transfer between the mirror and the water block. It will also improve positioning of the mirror by using flexible vacuum hosing and a ball head joint capable of a wide range of motion. Incorporating this design into the target monitoring system will provide more efficient coolingmore » of the mirror which will improve the amount of diffraction caused by the heating of the mirror. The process of aligning the mirror for accurate position will be greatly improved by increasing the range of motion by offering six degrees of freedom.« less

Finite Element Modeling of a Semi-Rigid Hybrid Mirror and a Highly Actuated Membrane Mirror as Candidates for the Next Generation Space Telescope

NASA Technical Reports Server (NTRS)

Craig, Larry; Jacobson, Dave; Mosier, Gary; Nein, Max; Page, Timothy; Redding, Dave; Sutherlin, Steve; Wilkerson, Gary

2000-01-01

Advanced space telescopes, which will eventually replace the Hubble Space Telescope (HTS), will have apertures of 8 - 20 n. Primary mirrors of these dimensions will have to be foldable to fit into the space launcher. By necessity these mirrors will be extremely light weight and flexible and the historical approaches to mirror designs, where the mirror is made as rigid as possible to maintain figure and to serve as the anchor for the entire telescope, cannot be applied any longer. New design concepts and verifications will depend entirely on analytical methods to predict optical performance. Finite element modeling of the structural and thermal behavior of such mirrors is becoming the tool for advanced space mirror designs. This paper discusses some of the preliminary tasks and study results, which are currently the basis for the design studies of the Next Generation Space Telescope.

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording.

PubMed

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-05-19

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

PubMed Central

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-01-01

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter. PMID:27213382

A robust low quiescent current power receiver for inductive power transmission in bio implants

NASA Astrophysics Data System (ADS)

Helalian, Hamid; Pasandi, Ghasem; Jafarabadi Ashtiani, Shahin

2017-05-01

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC-DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC-DC converter has variable conversion ratios and synchronous controller that lets the DC-DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0-10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.

The mirrors for the Extreme Ultraviolet Explorer

NASA Technical Reports Server (NTRS)

Finley, David S.; Green, James C.; Bowyer, Stuart; Malina, Roger F.

1986-01-01

Flight mirrors for the Extreme Ultraviolet Explorer satellite are currently under fabrication. The grazing incidence metal mirrors are Wolter-Schwarzschild Type I and II and are figured by diamond turning. Imaging performance is excellent, with the figure after polishing for the best mirror being such that the full width-half maximum is 1.0 arc seconds and the half energy width is 8 arc seconds measured at visible wavelengths. Surface finish, as determined from scattering measurements in the extreme ultraviolet, is about 20 A rms.

Current-controlled curvature of coated micromirrors

NASA Astrophysics Data System (ADS)

Liu, Wei; Talghader, Joseph J.

2003-06-01

Precise control of micromirror curvature is critical in many optical microsystems. Micromirrors with current-controlled curvature are demonstrated. The working principle is that resistive heating changes the temperature of the micromirrors and thermal expansion induces a controlled curvature whose magnitude is determined by coating design. For example, for wide focal-length tuning, the radius of curvature of a gold-coated mirror was tuned from 2.5 to 8.2 mm over a current-induced temperature range from 22° to 72 °C. For fine focal-length tuning, the radius of curvature of a dielectric-coated (SiO2/Y2O3 λ/4 pairs) mirror was tuned from -0.68 to -0.64 mm over a current-induced temperature range from 22 to 84 °C. These results should be readily extendable to mirror flattening or real-time adaptive shape control.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

The effects of transistor source-to-gate bridging faults in complex CMOS gates

NASA Astrophysics Data System (ADS)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

An integrated CMOS bio-potential amplifier with a feed-forward DC cancellation topology.

PubMed

Parthasarathy, Jayant; Erdman, Arthur G; Redish, Aaron D; Ziaie, Babak

2006-01-01

This paper describes a novel technique to realize an integrated CMOS bio-potential amplifier with a feedforward DC cancellation topology. The amplifier is designed to provide substantial DC cancellation even while amplifying very low frequency signals. More than 80 dB offset rejection ratio is achieved without any external capacitors. The cancellation scheme is robust against process and temperature variations. The amplifier is fabricated through MOSIS AMI 1.5 microm technology (0.05 mm2 area). Measurement results show a gain of 43.5 dB in the pass band (<1 mHz-5 KHz), an input referred noise of 3.66 microVrms, and a current consumption of 22 microA.

Performance and Transient Behavior of Vertically Integrated Thin-film Silicon Sensors

PubMed Central

Wyrsch, Nicolas; Choong, Gregory; Miazza, Clément; Ballif, Christophe

2008-01-01

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode. PMID:27873778

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel †

PubMed Central

Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien

2017-01-01

A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. PMID:29206162

Gemini 8.2-m primary mirror no. 1 polishing

NASA Astrophysics Data System (ADS)

Cayrel, Marc; Beraud, P.; Paseri, Jacques; Dromas, E.

1998-08-01

The 8-m class primary mirrors of the GEMINI Telescopes are thin ULE menisci actively supported. The two mirror blanks are produced by CORNING, the optical figuring, manufacturing and assembling of interfaces are done by REOSC. REOSC is as well in charge of the transportation of the mirror blanks from CORNING to REOSC, and of the shipment of the finished optics to Hawaii and to Chile. The mirror assembly requirements are summarized, the manufacturing and testing methods are addressed. REOSC had to design and manufacture a dedicated active supporting system, representative of the one used at the telescope level. Its design and performance are presented. The manufacturing steps undertaken at REOSC and the results achieved are then detailed: mirror blank surface generating and grinding, polishing, testing. The current status of the mirrors is finally presented.

Systematic review of the effectiveness of mirror therapy in upper extremity function.

PubMed

Ezendam, Daniëlle; Bongers, Raoul M; Jannink, Michiel J A

2009-01-01

This review gives an overview of the current state of research regarding the effectiveness of mirror therapy in upper extremity function. A systematic literature search was performed to identify studies concerning mirror therapy in upper extremity. The included journal articles were reviewed according to a structured diagram and the methodological quality was assessed. Fifteen studies were identified and reviewed. Five different patient categories were studied: two studies focussed on mirror therapy after an amputation of the upper limb, five studies focussed on mirror therapy after stroke, five studies focussed on mirror therapy with complex regional pain syndrome type 1 (CRPS1) patients, one study on mirror therapy with complex regional pain syndrome type 2 (CRPS2) and two studies focussed on mirror therapy after hand surgery other than amputation. Most of the evidence for mirror therapy is from studies with weak methodological quality. The present review showed a trend that mirror therapy is effective in upper limb treatment of stroke patients and patients with CRPS, whereas the effectiveness in other patient groups has yet to be determined.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

NASA Astrophysics Data System (ADS)

Fulkerson, David E.

2010-02-01

This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

NASA Astrophysics Data System (ADS)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, James D.

1997-01-01

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controled switching and effecting a direction of rectification.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, J.D.

1997-09-02

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controlled switching and effecting a direction of rectification. 89 figs.

A miniaturized neuroprosthesis suitable for implantation into the brain

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Binkley, David; Blalock, Benjamin; Andersen, Richard; Ulshoefer, Norbert; Johnson, Travis; Del Castillo, Linda

2003-01-01

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

NASA Astrophysics Data System (ADS)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhao, Chumin; Kanicki, Jerzy, E-mail: kanicki@eecs.umich.edu; Konstantinidis, Anastasios C.

Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterizedmore » and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for microcalcifications was observed using the Dexela 2923 MAM CMOS APS x-ray imager at a lower MGD (2.0 mGy). Conclusions: The Dexela 2923 MAM CMOS APS x-ray imager is capable to achieve a high imaging performance at spatial frequencies up to 6.7 lp/mm. Microcalcifications of 165 μm are distinguishable based on reported data and their modeling results due to the small pixel pitch of 75 μm. At the same time, potential dose reduction is expected using the studied CMOS APS x-ray imager.« less

Multiplane and Spectrally-Resolved Single Molecule Localization Microscopy with Industrial Grade CMOS cameras.

PubMed

Babcock, Hazen P

2018-01-29

This work explores the use of industrial grade CMOS cameras for single molecule localization microscopy (SMLM). We show that industrial grade CMOS cameras approach the performance of scientific grade CMOS cameras at a fraction of the cost. This makes it more economically feasible to construct high-performance imaging systems with multiple cameras that are capable of a diversity of applications. In particular we demonstrate the use of industrial CMOS cameras for biplane, multiplane and spectrally resolved SMLM. We also provide open-source software for simultaneous control of multiple CMOS cameras and for the reduction of the movies that are acquired to super-resolution images.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

PubMed

Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

2013-04-01

In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

Next Generation Space Telescope Ultra-Lightweight Mirror Program

NASA Technical Reports Server (NTRS)

Bilbro, James W.

1998-01-01

The Next Generation Space Telescope is currently envisioned as a eight meter diameter cryogenic deployable telescope that will operate at the earth sun libration point L2. A number of different designs are being examined within NASA and under industry studies by Ball Aerospace, Lockheed-Martin and TRW. Although these designs differ in many respects, they all require significant advancements in the state-of-the-art with respect to large diameter, ultra-lightweight, mirrors. The purpose of this paper is to provide insight into the current status of the mirror development program NGST is a tremendously ambitious undertaking that sets the mark for new NASA missions. In order to achieve the weight, cost and performance requirements of NGST, the primary mirror must be made lighter, cheaper and better than anything that has ever been done. In order to accomplish this an aggressive technology program has been put in place. The scope of the program was determined by examining historically what has been accomplished; assessing recent technological advances in fabrication and testing; and evaluating the effect of these advances relative to enabling the manufacture of lightweight mirrors that meet NGST requirements. As it is currently envisioned, the primary mirror for NGST is on the order of eight meters in diameter, it is to be diffraction limited at a wave length of 2 microns and has an overall weight requirement of 15 kilograms per square meter. Two large scale demonstration projects are under way along with a number of smaller scale demonstrations on a variety of mirror materials and concepts. The University of Arizona (UA) mirror concept is based around a 2mm thick Borosilicate glass face sheet mounted to a composite backplane structure via actuators for mirror figure correction. The Composite Optics Inc.(COI) concept consists of a 3.2mm thick Zerodur face sheet bonded to a composite support structure which in turn is mounted to a composite backplane structure via actuators for mirror phasing. These mirrors are due to be performance tested in ambient conditions in the fall of '98, and cryogenically tested in the spring of '99. The smaller scale efforts include the following: Beryllium is being investigated at Ball Aerospace, Electroform nickel is being investigated in-house at MSFC, Chemical Vapor Deposition (CVD) Silicon Carbide (SiC) is being investigated at Morton International Silicon mirrors are being investigated at Schafer, Carbon Fiber Reinforced Silicon Carbide (CSIC) is being investigated at IABG. SiC at SSG, Composite mirrors at COI, pyrolyzed graphite mirrors at Ultramet, reaction bonded SiC mirrors at Xinetics, along with techniques for lightweighting using waterjets at Waterjet Technology Inc. are all being investigated under the Small Business innovative Research Program SBIR program. A procurement for a third large scale demonstration (nominally 1.5m in diameter) is being planned for release this fall.

Method and apparatus for linear low-frequency feedback in monolithic low-noise charge amplifiers

DOEpatents

DeGeronimo, Gianluigi

2006-02-14

A charge amplifier includes an amplifier, feedback circuit, and cancellation circuit. The feedback circuit includes a capacitor, inverter, and current mirror. The capacitor is coupled across the signal amplifier, the inverter is coupled to the output of the signal amplifier, and the current mirror is coupled to the input of the signal amplifier. The cancellation circuit is coupled to the output of the signal amplifier. A method of charge amplification includes providing a signal amplifier; coupling a first capacitor across the signal amplifier; coupling an inverter to the output of the signal amplifier; coupling a current mirror to the input of the signal amplifier; and coupling a cancellation circuit to the output of the signal amplifier. A front-end system for use with radiation sensors includes a charge amplifier and a current amplifier, shaping amplifier, baseline stabilizer, discriminator, peak detector, timing detector, and logic circuit coupled to the charge amplifier.

Monolithic CMOS imaging x-ray spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

A 3.2-GHz fully integrated low-phase noise CMOS VCO with self-biasing current source for the IEEE 802.11a/hiperLAN WLAN standard

NASA Astrophysics Data System (ADS)

Quemada, C.; Adin, I.; Bistue, G.; Berenguer, R.; Mendizabal, J.

2005-06-01

A 3.3V, fully integrated 3.2-GHz voltage-controlled oscillator (VCO) is designed in a 0.18μm CMOS technology for the IEE 802.11a/HiperLAN WLAN standard for the UNII band from 5.15 to 5.35 GHz. The VCO is tunable between 2.85 GHz and 3.31 GHz. NMOS architecture with self-biasing current of the tank source is chosen. A startup circuit has been employed to avoid zero initial current. Current variation is lower than 1% for voltage supply variations of 10%. The use of a self-biasing current source in the tank provides a greater safety in the transconductance value and allows running along more extreme point operation The designed VCO displays a phase noise and output power of -98dBc/Hz (at 100 KHz offset frequency) and 0dBm respectively. This phase noise has been obtained with inductors of 2.2nH and quality factor of 12 at 3.2 GHz, and P-N junction varactors whose quality factor is estimated to exceed 40 at 3.2 GHz. These passive components have been fabricated, measured and modeled previously. The core of the VCO consumes 33mW DC power.

GeSn Based Near and Mid Infrared Heterostructure Detectors

DTIC Science & Technology

2018-02-07

prestigious journals. 15.  SUBJECT TERMS Plasmonic Enhancement, Metal Nanostructures, CMOS, Photodetectors, Germanium- Tin Diode, IR Focal Plane Array...can be achieved by using current developed chemical vapor deposition technique. Optical properties of germanium tin (Ge1-xSnx) alloys have been

Enhancing the mirror illusion with transcranial direct current stimulation.

PubMed

Jax, Steven A; Rosa-Leyra, Diana L; Coslett, H Branch

2015-05-01

Visual feedback has a strong impact on upper-extremity movement production. One compelling example of this phenomena is the mirror illusion (MI), which has been used as a treatment for post-stroke movement deficits (mirror therapy). Previous research indicates that the MI increases primary motor cortex excitability, and this change in excitability is strongly correlated with the mirror's effects on behavioral performance of neurologically-intact controls. Based on evidence that primary motor cortex excitability can also be increased using transcranial direct current stimulation (tDCS), we tested whether bilateral tDCS to the primary motor cortices (anode right-cathode left and anode left-cathode right) would modify the MI. We measured the MI using a previously-developed task in which participants make reaching movements with the unseen arm behind a mirror while viewing the reflection of the other arm. When an offset in the positions of the two limbs relative to the mirror is introduced, reaching errors of the unseen arm are biased by the reflected arm's position. We found that active tDCS in the anode right-cathode left montage increased the magnitude of the MI relative to sham tDCS and anode left-cathode right tDCS. We take these data as a promising indication that tDCS could improve the effect of mirror therapy in patients with hemiparesis. Copyright © 2015 Elsevier Ltd. All rights reserved.

Graded Mirror Self-Recognition by Clark's Nutcrackers.

PubMed

Clary, Dawson; Kelly, Debbie M

2016-11-04

The traditional 'mark test' has shown some large-brained species are capable of mirror self-recognition. During this test a mark is inconspicuously placed on an animal's body where it can only be seen with the aid of a mirror. If the animal increases the number of actions directed to the mark region when presented with a mirror, the animal is presumed to have recognized the mirror image as its reflection. However, the pass/fail nature of the mark test presupposes self-recognition exists in entirety or not at all. We developed a novel mirror-recognition task, to supplement the mark test, which revealed gradation in the self-recognition of Clark's nutcrackers, a large-brained corvid. To do so, nutcrackers cached food alone, observed by another nutcracker, or with a regular or blurry mirror. The nutcrackers suppressed caching with a regular mirror, a behavioural response to prevent cache theft by conspecifics, but did not suppress caching with a blurry mirror. Likewise, during the mark test, most nutcrackers made more self-directed actions to the mark with a blurry mirror than a regular mirror. Both results suggest self-recognition was more readily achieved with the blurry mirror and that self-recognition may be more broadly present among animals than currently thought.

Manufacture of a combined primary and tertiary mirror for the Large Synoptic Survey Telescope

NASA Astrophysics Data System (ADS)

Martin, H. M.; Burge, J. H.; Cuerden, B.; Davison, W. B.; Kingsley, J. S.; Lutz, R. D.; Miller, S. M.; Tuell, M.

2008-07-01

The Large Synoptic Survey Telescope uses a unique optomechanical design that places the primary and tertiary mirrors on a single glass substrate. The honeycomb sandwich mirror blank was formed in March 2008 by spin-casting. The surface is currently a paraboloid with a 9.9 m focal length matching the primary. The deeper curve of the tertiary mirror will be produced when the surfaces are generated. Both mirrors will be lapped and polished using stressed laps and other tools on an 8.4 m polishing machine. The highly aspheric primary mirror will be measured through a refractive null lens, and a computer-generated hologram will be used to validate the null lens. The tertiary mirror will be measured through a diffractive null corrector, also validated with a separate hologram. The holograms for the two tests provide alignment references that will be used to make the axes of the two surfaces coincide.

Phase-Controlled Magnetic Mirror for Wavefront Correction

NASA Technical Reports Server (NTRS)

Hagopian, John; Wollack, Edward

2011-01-01

Typically, light interacts with matter via the electric field and interaction with weakly bound electrons. In a magnetic mirror, a patterned nanowire is fabricated over a metallic layer with a dielectric layer in between. Oscillation of the electrons in the nanowires in response to the magnetic field of incident photons causes a re-emission of photons and operation as a "magnetic mirror." By controlling the index of refraction in the dielectric layer using a local applied voltage, the phase of the emitted radiation can be controlled. This allows electrical modification of the reflected wavefront, resulting in a deformable mirror that can be used for wavefront control. Certain applications require wavefront quality in the few-nanometer regime, which is a major challenge for optical fabrication and alignment of mirrors or lenses. The use of a deformable magnetic mirror allows for a device with no moving parts that can modify the phase of incident light over many spatial scales, potentially with higher resolution than current approaches. Current deformable mirrors modify the incident wavefront by using nano-actuation of a substrate to physically bend the mirror to a desired shape. The purpose of the innovation is to modify the incident wavefront for the purpose of correction of fabrication and alignment-induced wavefront errors at the system level. The advanced degree of precision required for some applications such as gravity wave detection (LISA - Laser Interferometer Space Antenna) or planet finding (FKSI - Fourier-Kelvin Stellar Interferometer) requires wavefront control at the limits of the current state of the art. All the steps required to fabricate a magnetic mirror have been demonstrated. The modification is to apply a bias voltage to the dielectric layer so as to change the index of refraction and modify the phase of the reflected radiation. Light is reflected off the device and collected by a phase-sensing interferometer. The interferometer determines the initial wavefront of the device and fore optics. A wavefront correction is calculated, and voltage profile for each nanowire strip is determined. The voltage is applied, modifying the local index of refraction of the dielectric under the nanowire strip. This modifies the phase of the reflected light to allow wavefront correction.

Surface roughness measurements

NASA Technical Reports Server (NTRS)

Howard, Thomas G.

1994-01-01

The Optics Division is currently in the research phase of producing grazing-incidence mirrors to be used in x-ray detector applications. The traditional method of construction involves labor-intensive glass grinding. This also culminates in a relatively heavy mirror. For lower resolution applications, the mirrors may be of a replicated design which involves milling a mandrel as a negative of the final shape and electroplating the cylindrical mirror onto it. The mirror is then separated from the mandrel by cooling. The mandrel will shrink more than the 'shell' (mirror) allowing it to be pulled from the mandrel. Ulmer (2) describes this technique and its variations in more detail. To date, several mirrors have been tested at MSFC by the Optical Fabrication Branch by focusing x-ray energy onto a detector with limited success. Little is known about the surface roughness of the actual mirror. Hence, the attempt to gather data on these surfaces. The test involves profiling the surface of a sample, replicating the surface as described above, and then profiling the replicated surface.

Development of reaction-sintered SiC mirror for space-borne optics

NASA Astrophysics Data System (ADS)

Yui, Yukari Y.; Kimura, Toshiyoshi; Tange, Yoshio

2017-11-01

We are developing high-strength reaction-sintered silicon carbide (RS-SiC) mirror as one of the new promising candidates for large-diameter space-borne optics. In order to observe earth surface or atmosphere with high spatial resolution from geostationary orbit, larger diameter primary mirrors of 1-2 m are required. One of the difficult problems to be solved to realize such optical system is to obtain as flat mirror surface as possible that ensures imaging performance in infrared - visible - ultraviolet wavelength region. This means that homogeneous nano-order surface flatness/roughness is required for the mirror. The high-strength RS-SiC developed and manufactured by TOSHIBA is one of the most excellent and feasible candidates for such purpose. Small RS-SiC plane sample mirrors have been manufactured and basic physical parameters and optical performances of them have been measured. We show the current state of the art of the RS-SiC mirror and the feasibility of a large-diameter RS-SiC mirror for space-borne optics.

Mirror Neurons Modeled Through Spike-Timing-Dependent Plasticity are Affected by Channelopathies Associated with Autism Spectrum Disorder.

PubMed

Antunes, Gabriela; Faria da Silva, Samuel F; Simoes de Souza, Fabio M

2018-06-01

Mirror neurons fire action potentials both when the agent performs a certain behavior and watches someone performing a similar action. Here, we present an original mirror neuron model based on the spike-timing-dependent plasticity (STDP) between two morpho-electrical models of neocortical pyramidal neurons. Both neurons fired spontaneously with basal firing rate that follows a Poisson distribution, and the STDP between them was modeled by the triplet algorithm. Our simulation results demonstrated that STDP is sufficient for the rise of mirror neuron function between the pairs of neocortical neurons. This is a proof of concept that pairs of neocortical neurons associating sensory inputs to motor outputs could operate like mirror neurons. In addition, we used the mirror neuron model to investigate whether channelopathies associated with autism spectrum disorder could impair the modeled mirror function. Our simulation results showed that impaired hyperpolarization-activated cationic currents (Ih) affected the mirror function between the pairs of neocortical neurons coupled by STDP.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Thermal annealing response following irradiation of a CMOS imager for the JUICE JANUS instrument

NASA Astrophysics Data System (ADS)

Lofthouse-Smith, D.-D.; Soman, M. R.; Allanwood, E. A. H.; Stefanov, K. D.; Holland, A. D.; Leese, M.; Turne, P.

2018-03-01

ESA's JUICE (JUpiter ICy moon Explorer) spacecraft is an L-class mission destined for the Jovian system in 2030. Its primary goals are to investigate the conditions for planetary formation and the emergence of life, and how does the solar system work. The JANUS camera, an instrument on JUICE, uses a 4T back illuminated CMOS image sensor, the CIS115 designed by Teledyne e2v. JANUS imager test campaigns are studying the CIS115 following exposure to gammas, protons, electrons and heavy ions, simulating the harsh radiation environment present in the Jovian system. The degradation of 4T CMOS device performance following proton fluences is being studied, as well as the effectiveness of thermal annealing to reverse radiation damage. One key parameter for the JANUS mission is the Dark current of the CIS115, which has been shown to degrade in previous radiation campaigns. A thermal anneal of the CIS115 has been used to accelerate any annealing following the irradiation as well as to study the evolution of any performance characteristics. CIS115s have been irradiated to double the expected End of Life (EOL) levels for displacement damage radiation (2×1010 protons, 10 MeV equivalent). Following this, devices have undergone a thermal anneal cycle at 100oC for 168 hours to reveal the extent to which CIS115 recovers pre-irradiation performance. Dark current activation energy analysis following proton fluence gives information on trap species present in the device and how effective anneal is at removing these trap species. Thermal anneal shows no quantifiable change in the activation energy of the dark current following irradiation.

Comparative study of various pixel photodiodes for digital radiography: Junction structure, corner shape and noble window opening

NASA Astrophysics Data System (ADS)

Kang, Dong-Uk; Cho, Minsik; Lee, Dae Hee; Yoo, Hyunjun; Kim, Myung Soo; Bae, Jun Hyung; Kim, Hyoungtaek; Kim, Jongyul; Kim, Hyunduk; Cho, Gyuseong

2012-05-01

Recently, large-size 3-transistors (3-Tr) active pixel complementary metal-oxide silicon (CMOS) image sensors have been being used for medium-size digital X-ray radiography, such as dental computed tomography (CT), mammography and nondestructive testing (NDT) for consumer products. We designed and fabricated 50 µm × 50 µm 3-Tr test pixels having a pixel photodiode with various structures and shapes by using the TSMC 0.25-m standard CMOS process to compare their optical characteristics. The pixel photodiode output was continuously sampled while a test pixel was continuously illuminated by using 550-nm light at a constant intensity. The measurement was repeated 300 times for each test pixel to obtain reliable results on the mean and the variance of the pixel output at each sampling time. The sampling rate was 50 kHz, and the reset period was 200 msec. To estimate the conversion gain, we used the mean-variance method. From the measured results, the n-well/p-substrate photodiode, among 3 photodiode structures available in a standard CMOS process, showed the best performance at a low illumination equivalent to the typical X-ray signal range. The quantum efficiencies of the n+/p-well, n-well/p-substrate, and n+/p-substrate photodiodes were 18.5%, 62.1%, and 51.5%, respectively. From a comparison of pixels with rounded and rectangular corners, we found that a rounded corner structure could reduce the dark current in large-size pixels. A pixel with four rounded corners showed a reduced dark current of about 200fA compared to a pixel with four rectangular corners in our pixel sample size. Photodiodes with round p-implant openings showed about 5% higher dark current, but about 34% higher sensitivities, than the conventional photodiodes.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Maintenance and testing of anodized aluminum mirrors on the Whipple 10 m Whipple Telescope

NASA Astrophysics Data System (ADS)

Badran, H. M.; Weekes, T. C.

2001-08-01

Threshold energy sensitivity depends not only on the high reflectivity of the mirrors used in atmospheric Cherenkov telescopes but also on the maintenance of this reflectivity over months/years. The successful application of a mirror maintenance technique depends on the type of mirror coating and the contamination that must be removed. The uncovered mirrors in use on the 10-m Whipple gamma-ray telescope are anodized aluminum mirrors. A standard cleaning technique for such mirrors is not available. With the aim of extending the life of the aluminum coating exposed to the Mt ˙Hopkins environment, several cleaning procedures were tested on mirrors that had been exposed for three years. Evaluation of the most effective cleaners is presented. Preliminary results are also presented from a long-term experiment using newly coated mirrors at the proposed VERITAS site and at the current 10 m site. This experiment is designed to reveal the rates at which the reflectance degrades as a function of time, depth of anodization, storage direction, degree of covering, and maintenance procedures.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

High throughput imaging cytometer with acoustic focussing† †Electronic supplementary information (ESI) available: High throughput imaging cytometer with acoustic focussing. See DOI: 10.1039/c5ra19497k Click here for additional data file. Click here for additional data file. Click here for additional data file. Click here for additional data file. Click here for additional data file. Click here for additional data file. Click here for additional data file. Click here for additional data file.

PubMed Central

Zmijan, Robert; Jonnalagadda, Umesh S.; Carugo, Dario; Kochi, Yu; Lemm, Elizabeth; Packham, Graham; Hill, Martyn

2015-01-01

We demonstrate an imaging flow cytometer that uses acoustic levitation to assemble cells and other particles into a sheet structure. This technique enables a high resolution, low noise CMOS camera to capture images of thousands of cells with each frame. While ultrasonic focussing has previously been demonstrated for 1D cytometry systems, extending the technology to a planar, much higher throughput format and integrating imaging is non-trivial, and represents a significant jump forward in capability, leading to diagnostic possibilities not achievable with current systems. A galvo mirror is used to track the images of the moving cells permitting exposure times of 10 ms at frame rates of 50 fps with motion blur of only a few pixels. At 80 fps, we demonstrate a throughput of 208 000 beads per second. We investigate the factors affecting motion blur and throughput, and demonstrate the system with fluorescent beads, leukaemia cells and a chondrocyte cell line. Cells require more time to reach the acoustic focus than beads, resulting in lower throughputs; however a longer device would remove this constraint. PMID:29456838

High current multicharged metal ion source using high power gyrotron heating of vacuum arc plasma.

PubMed

Vodopyanov, A V; Golubev, S V; Khizhnyak, V I; Mansfeld, D A; Nikolaev, A G; Oks, E M; Savkin, K P; Vizir, A V; Yushkov, G Yu

2008-02-01

A high current, multi charged, metal ion source using electron heating of vacuum arc plasma by high power gyrotron radiation has been developed. The plasma is confined in a simple mirror trap with peak magnetic field in the plug up to 2.5 T, mirror ratio of 3-5, and length variable from 15 to 20 cm. Plasma formed by a cathodic vacuum arc is injected into the trap either (i) axially using a compact vacuum arc plasma gun located on axis outside the mirror trap region or (ii) radially using four plasma guns surrounding the trap at midplane. Microwave heating of the mirror-confined, vacuum arc plasma is accomplished by gyrotron microwave radiation of frequency 75 GHz, power up to 200 kW, and pulse duration up to 150 micros, leading to additional stripping of metal ions by electron impact. Pulsed beams of platinum ions with charge state up to 10+, a mean charge state over 6+, and total (all charge states) beam current of a few hundred milliamperes have been formed.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

A study of charged particles/radiation damage to VLSI device materials

NASA Technical Reports Server (NTRS)

Okyere, John G.

1987-01-01

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Engagement: Looking beyond the mirror to understand action understanding.

PubMed

Reddy, Vasudevi; Uithol, Sebo

2016-03-01

In this paper, we argue that the current focus on mirroring as the route to explaining the development of action understanding is misleading and problematic. It facilitates a fundamentally spectatorial stance, ignoring engagement and dialogue; it focuses on similarity between self and other and neglects difference; and it succumbs to the static terminology of mechanism rather than a dynamic language of process. Contrary to this view, dialogic exchanges are evident from the start of life, revealing infants' ability to engage with and respond appropriately to actions that are outside their own motor repertoire. We suggest that engagement rather than mirroring better accounts for many current findings in action understanding. The neurological evidence to date shows that action perception involves a process of continuous synchronization and change, suggesting that it might be more fruitful for research and theory to look beyond mirroring and instead adopt dynamic processual explanations of action understanding within interaction. © 2015 The British Psychological Society.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

PubMed

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

The vertical-cavity surface-emitting laser incorporating a high contrast grating mirror as a sensing device

NASA Astrophysics Data System (ADS)

Marciniak, Magdalena; Gebski, Marcin; Piskorski, Łukasz; Dems, Maciej; Wasiak, M.; Panajotov, Krassimir; Lott, James A.; Czyszanowski, Tomasz

2018-02-01

We propose a novel optical sensing system based on one device that both emits and detects light consisting of a verticalcavity surface-emitting laser (VCSEL) incorporating an high contrast grating (HCG) as a top mirror. Since HCGs can be very sensitive to the optical properties of surrounding media, they can be used to detect gases and liquid. The presence of a gas or a liquid around an HCG mirror causes changes of the power reflectance of the mirror, which corresponds to changes of the VCSEL's cavity quality factor and current-voltage characteristic. By observation of the current-voltage characteristic we can collect information about the medium around the HCG. In this paper we investigate how the properties of the HCG mirror depend on the refractive index of the HCG surroundings. We present results of a computer simulation performed with a three-dimensional fully vectorial model. We consider silicon HCGs on silica and designed for a 1300 nm VCSEL emission wavelength. We demonstrate that our approach can be applied to other wavelengths and material systems.

MEMS analog light processing: an enabling technology for adaptive optical phase control

NASA Astrophysics Data System (ADS)

Gehner, Andreas; Wildenhain, Michael; Neumann, Hannes; Knobbe, Jens; Komenda, Ondrej

2006-01-01

Various applications in modern optics are demanding for Spatial Light Modulators (SLM) with a true analog light processing capability, e.g. the generation of arbitrary analog phase patterns for an adaptive optical phase control. For that purpose the Fraunhofer IPMS has developed a high-resolution MEMS Micro Mirror Array (MMA) with an integrated active-matrix CMOS address circuitry. The device provides 240 x 200 piston-type mirror elements with 40 μm pixel size, where each of them can be addressed and deflected independently at an 8bit height resolution with a vertical analog deflection range of up to 400 nm suitable for a 2pi phase modulation in the visible. Full user programmability and control is provided by a newly developed comfortable driver software for Windows XP based PCs supporting both a Graphical User Interface (GUI) for stand-alone operation with pre-defined data patterns as well as an open ActiveX programming interface for a direct data feed-through within a closed-loop environment. High-speed data communication is established by an IEEE1394a FireWire interface together with an electronic driving board performing the actual MMA programming and control at a maximum frame rate of up to 500 Hz. Successful application demonstrations have been given in eye aberration correction, coupling efficiency optimization into a monomode fiber, ultra-short laser pulse modulation and diffractive beam shaping. Besides a presentation of the basic device concept the paper will give an overview of the obtained results from these applications.

A current-assisted CMOS photonic sampler with two taps for fluorescence lifetime sensing

NASA Astrophysics Data System (ADS)

Ingelberts, H.; Kuijk, M.

2016-04-01

Imaging based on fluorescence lifetime is becoming increasingly important in medical and biological applications. State-of- the-art fluorescence lifetime microscopes either use bulky and expensive gated image intensifiers coupled to a CCD or single-photon detectors in a slow scanning setup. Numerous attempts are being made to create compact, cost-effective all- CMOS imagers for fluorescence lifetime sensing. Single-photon avalanche diode (SPAD) imagers can have very good timing resolution and noise characteristics but have low detection efficiency. Another approach is to use CMOS imagers based on demodulation detectors. These imagers can be either very fast or very efficient but it remains a challenge to combine both characteristics. Recently we developed the current-assisted photonic sampler (CAPS) to tackle these problems and in this work, we present a new CAPS with two detection taps that can sample a fluorescence decay in two time windows. In the case of mono-exponential decays, two windows provide enough information to resolve the lifetime. We built an electro-optical setup to characterize the detector and use it for fluorescence lifetime measurements. It consists of a supercontinuum pulsed laser source, an optical system to focus light into the detector and picosecond timing electronics. We describe the structure and operation of the two-tap CAPS and provide basic characterization of the speed performance at multiple wavelengths in the visible and near-infrared spectrum. We also record fluorescence decays of different visible and NIR fluorescent dyes and provide different methods to resolve the fluorescence lifetime.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

High density submicron magnetoresistive random access memory (invited)

NASA Astrophysics Data System (ADS)

Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

1999-04-01

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

Thermopile Detector Arrays for Space Science Applications

NASA Technical Reports Server (NTRS)

Foote, M. C.; Kenyon, M.; Krueger, T. R.; McCann, T. A.; Chacon, R.; Jones, E. W.; Dickie, M. R.; Schofield, J. T.; McCleese, D. J.; Gaalema, S.

2004-01-01

Thermopile detectors are widely used in uncooled applications where small numbers of detectors are required, particularly in low-cost commercial applications or applications requiring accurate radiometry. Arrays of thermopile detectors, however, have not been developed to the extent of uncooled bolometer and pyroelectric/ferroelectric arrays. Efforts at JPL seek to remedy this deficiency by developing high performance thin-film thermopile detectors in both linear and two-dimensional formats. The linear thermopile arrays are produced by bulk micromachining and wire bonded to separate CMOS readout electronic chips. Such arrays are currently being fabricated for the Mars Climate Sounder instrument, scheduled for launch in 2005. Progress is also described towards realizing a two-dimensional thermopile array built over CMOS readout circuitry in the substrate.

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications

DOE PAGES

Zhang, T.; Tavernier, F.; Moreira, P.; ...

2015-02-19

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system at the transmitter side. We have developed a 10 Gb/s GBLD (GBLD10) in a 130 nm CMOS technology, as part of the design efforts towards the upgrade of the electrical components of the LHC experiments. The GBLD10 is based on the distributed-amplifier (DA) architecture and achieves data rates up to 10 Gb/s. It is capable of driving VCSELs with modulation currents up to 12 mA. Furthermore, a pre-emphasis function has been included in the proposed laser driver in order to compensate for the capacitivemore » load and channel losses.« less

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Introduction of performance boosters like Ge as channel material for the future of CMOS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samia, Slimani, E-mail: slimani.samia@gmail.com; Laboratoire de Modélisation et Méthodes de calcul LMMC,20002 Saida; Bouaza, Djellouli, E-mail: djelbou@hotmail.fr

High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge is one of new attractive channel materials that require CMOS scaling For future technology nodes and future high performance P-MOSFETS, we have studied a nanoscale SOI DG MOSFETs using quantum simulation approach on DG MOSFETs within the variation of Ge channel concentration and in the presence of source and drain doping by replacing Silicon in the channel by Ge using various dielectric constant. The use of high mobility channel (like Ge) to maximize the MOSFET IDsat and simultaneously circumventmore » the poor electrostatic control to suppress short-channel effects and enhance source injection velocity. The leakage current (I{sub off}) can be controlled by different gates oxide thickness more ever the required threshold voltage (V{sub TH}) can be achieved by keeping gate work function and altering the doping channel.« less

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Verification procedure for the wavefront quality of the primary mirrors for the MRO interferometer

NASA Astrophysics Data System (ADS)

Bakker, Eric J.; Olivares, Andres; Schmell, Reed A.; Schmell, Rodney A.; Gartner, Darren; Jaramillo, Anthony; Romero, Kelly; Rael, Andres; Lewis, Jeff

2009-08-01

We present the verification procedure for the 1.4 meter primary mirrors of the Magdalena Ridge Observatory Interferometer (MROI). Six mirrors are in mass production at Optical Surface Technologies (OST) in Albuquerque. The six identical parabolic mirrors will have a radius of curvature of 6300 mm and a final surface wavefront quality of 29 nm rms. The mirrors will be tested in a tower using a computer generated hologram, and the Intellium⢠H2000 interferometer from Engineering Synthesis Design, Inc. (ESDI). The mirror fabrication activities are currently in the early stage of polishing and have already delivered some promising results with the interferometer. A complex passive whiffle tree has been designed and fabricated by Advanced Mechanical and Optical Systems (AMOS, Belgium) that takes into account the gravity loading for an alt-alt mount. The final testing of the primary mirrors will be completed with the mirror cells that will be used in the telescopes. In addition we report on shear tests performed on the mirror cell pads on the back of the primary mirrors. These pads are glued to the mirror. The shear test has demonstrated that the glue can withstand at least 4.9 kilo Newton. This is within the requirements.

Global Radius of Curvature Estimation and Control System for Segmented Mirrors

NASA Technical Reports Server (NTRS)

Rakoczy, John M. (Inventor)

2006-01-01

An apparatus controls positions of plural mirror segments in a segmented mirror with an edge sensor system and a controller. Current mirror segment edge sensor measurements and edge sensor reference measurements are compared with calculated edge sensor bias measurements representing a global radius of curvature. Accumulated prior actuator commands output from an edge sensor control unit are combined with an estimator matrix to form the edge sensor bias measurements. An optimal control matrix unit then accumulates the plurality of edge sensor error signals calculated by the summation unit and outputs the corresponding plurality of actuator commands. The plural mirror actuators respond to the actuator commands by moving respective positions of the mixor segments. A predetermined number of boundary conditions, corresponding to a plurality of hexagonal mirror locations, are removed to afford mathematical matrix calculation.

Opto-Mechanics of the Constellation-X SXT Mirrors: Challenges in Mounting and Assembling the Mirror Segments

NASA Technical Reports Server (NTRS)

Chan, Kai-Wing; Zhang, WIlliam W.; Saha, Timo; Lehan, John P.; Mazzarella, James; Lozipone, Lawrence; Hong, Melinda; Byron, Glenn

2008-01-01

The Constellation-X Spectroscopy X-Ray Telescopes consists of segmented glass mirrors with an axial length of 200 mm, a width of up to 400 mm, and a thickness of 0.4 mm. To meet the requirement of less than 15 arc-second half-power diameter with the small thickness and relatively large size is a tremendous challenge in opto-mechanics. How shall we limit distortion of the mirrors due to gravity in ground tests, that arises from thermal stress, and that occurs in the process of mounting, affixing and assembling of these mirrors? In this paper, we will describe our current opto-mechanical approach to these problems. We will discuss, in particular, the approach and experiment where the mirrors are mounted vertically by first suspending it at two points.

The mirror neuron system in post-stroke rehabilitation

PubMed Central

2013-01-01

Different treatments for stroke patients have been proposed; among them the mirror therapy and motion imagery lead to functional recovery by providing a cortical reorganization. Up today the basic concepts of the current literature on mirror neurons and the major findings regarding the use of mirror therapy and motor imagery as potential tools to promote reorganization and functional recovery in post-stroke patients. Bibliographic research was conducted based on publications over the past thirteen years written in English in the databases Scielo, Pubmed/MEDLINE, ISI Web of Knowledge. The studies showed how the interaction among vision, proprioception and motor commands promotes the recruitment of mirror neurons, thus providing cortical reorganization and functional recovery of post-stroke patients. We conclude that the experimental advances on Mirror Neurons will bring new rational therapeutic approaches to post-stroke rehabilitation. PMID:24134862

The mirror neuron system in post-stroke rehabilitation.

PubMed

Carvalho, Diana; Teixeira, Silmar; Lucas, Marina; Yuan, Ti-Fei; Chaves, Fernanda; Peressutti, Caroline; Machado, Sergio; Bittencourt, Juliana; Menéndez-González, Manuel; Nardi, Antonio Egidio; Velasques, Bruna; Cagy, Mauricio; Piedade, Roberto; Ribeiro, Pedro; Arias-Carrión, Oscar

2013-10-17

Different treatments for stroke patients have been proposed; among them the mirror therapy and motion imagery lead to functional recovery by providing a cortical reorganization. Up today the basic concepts of the current literature on mirror neurons and the major findings regarding the use of mirror therapy and motor imagery as potential tools to promote reorganization and functional recovery in post-stroke patients. Bibliographic research was conducted based on publications over the past thirteen years written in English in the databases Scielo, Pubmed/MEDLINE, ISI Web of Knowledge. The studies showed how the interaction among vision, proprioception and motor commands promotes the recruitment of mirror neurons, thus providing cortical reorganization and functional recovery of post-stroke patients. We conclude that the experimental advances on Mirror Neurons will bring new rational therapeutic approaches to post-stroke rehabilitation.

Large optics technology; Proceedings of the Meeting, San Diego, CA, August 19-21, 1985. Volume 571

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanger, G.M.

1986-01-01

The present conference on telescope primary mirror design and manufacturing technologies considers topics in mirror fabrication and testing, novel technology currently under development, recently instituted large optics development programs, and large mirror materials. Among the topics discussed are aspheric figure generation using feedback from an IR phase-shifting interferometer, thermal stability tests of CFRP sandwich panels for far-IR astronomy, Zerodur lightweight (large mirror) blanks, and the precision machining of grazing-incidence X-ray mirror substrates. Also treated are the rapid fabrication of large aspheric optics, steps toward 8-m honeycomb mirrors, a novel telescope design employing the refraction of prism rows, telescope technology formore » the Far-UV Spectroscopic Explorer, hot isostatic-pressed Be for large optics, and a concept for a moderate cost large deployable reflector.« less

The secondary mirror concept for the European Extremely Large Telescope

NASA Astrophysics Data System (ADS)

Mueller, Michael; Cayrel, Marc; Bonnet, Henri; Ciattaglia, Emanuela; Esselborn, Michael; Koch, Franz; Kurlandczyk, Herve; Pettazzi, Lorenzo; Rakich, Andrew; Sedghi, Babak

2014-07-01

The E-ELT is an active and adaptive 39-m telescope, with an anastigmat optical solution (5 mirrors including two flats), currently being developed by the European Southern Observatory (ESO). The convex 4-metre-class secondary mirror (M2) is a thin Zerodur meniscus passively supported by an 18 point axial whiffletree. A warping harness system allows to correct low order deformations of the M2 Mirror. Laterally the mirror is supported on 12 points along the periphery by pneumatic jacks. Due to its high optical sensitivity and the telescope gravity deflections, the M2 unit needs to allow repositioning the mirror during observation. Considering its exposed position 30m above the primary, the M2 unit has to provide good wind rejection. The M2 concept is described and major performance characteristics are presented.

The Comfort Measures Order Set at a Tertiary Care Academic Hospital: Is There a Comparable Difference in End-of-Life Care Between Patients Dying in Acute Care When CMOS Is Utilized?

PubMed

Lau, Christine; Stilos, Kalli; Nowell, Allyson; Lau, Fanchea; Moore, Jennifer; Wynnychuk, Lesia

2018-04-01

Standardized protocols have been previously shown to be helpful in managing end-of-life (EOL) care in hospital. The comfort measures order set (CMOS), a standardized framework for assessing imminently dying patients' symptoms and needs, was implemented at a tertiary academic hospital. We assessed whether there were comparable differences in the care of a dying patient when the CMOS was utilized and when it was not. A retrospective chart review was completed on patients admitted under oncology and general internal medicine, who were referred to the inpatient palliative care team for "EOL care" between February 2015 and March 2016. Of 83 patients, 56 (67%) received intiation of the CMOS and 27 (33%) did not for EOL care. There was significant involvement of spiritual care with the CMOS (66%), as compared to the group without CMOS (19%), P < .05. The use of CMOS resulted in 1.7 adjustments to symptom management per patient by palliative care, which was significantly less than the number of symptom management adjustments per patient when CMOS was not used (3.3), P < .05. However, initiating CMOS did not result in a signficant difference in patient distress around the time of death ( P = .11). Dyspnea was the most frequently identified symptom causing distress in actively dying patients. Implementation of the CMOS is helpful in providing a foundation to a comfort approach in imminently dying patients. However, more education on its utility as a framework for EOL care and assessment across the organization is still required.

Experimental investigation of plasma sheaths in magnetic mirror and cusp configurations

NASA Astrophysics Data System (ADS)

Jiang, Zhengqi; Wei, Zi-an; Ma, J. X.

2017-11-01

Sheath structures near a metal plate in a magnetized plasma were experimentally investigated in magnetic mirror and cusp configurations. Plasma parameters and the sheath potential distributions were probed by a planar and an emissive probe, respectively. The measured sheath profiles in the mirror configuration show that the sheath thickness first decreases and then increases when the magnetic strength is raised. A magnetic flux-tube model was used to explain this result. In the cusp configuration, the measured sheath thickness decreases with the increase of the coil current creating the magnetic cusp. However, when normalized by the electron Debye length, the dependence of the sheath thickness on the coil current is reversed.

Three-meter telescope study

NASA Technical Reports Server (NTRS)

Wissinger, A.; Scott, R. M.; Peters, W.; Augustyn, W., Jr.; Arnold, R.; Offner, A.; Damast, M.; Boyce, B.; Kinnaird, R.; Mangus, J. D.

1971-01-01

A means is presented whereby the effect of various changes in the most important parameters of a three meter aperature space astronomy telescope can be evaluated to determine design trends and to optimize the optical design configuration. Methods are defined for evaluating the theoretical optical performance of axisymmetric, centrally obscured telescopes based upon the intended astronomy research usage. A series of design parameter variations is presented to determine the optimum telescope configuration. The design optimum requires very fast primary mirrors, so the study also examines the current state of the art in fabricating large, fast primary mirrors. The conclusion is that a 3-meter primary mirror having a focal ratio as low as f/2 is feasible using currently established techniques.

Cargo Movement Operations System (CMOS). Software Test Description

DTIC Science & Technology

1990-10-28

resulting in errors in paragraph numbers and titles. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...location to test the update of the truck manifest. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Optical levitation of a mirror for reaching the standard quantum limit.

PubMed

Michimura, Yuta; Kuwahara, Yuya; Ushiba, Takafumi; Matsumoto, Nobuyuki; Ando, Masaki

2017-06-12

We propose a new method to optically levitate a macroscopic mirror with two vertical Fabry-Pérot cavities linearly aligned. This configuration gives the simplest possible optical levitation in which the number of laser beams used is the minimum of two. We demonstrate that reaching the standard quantum limit (SQL) of a displacement measurement with our system is feasible with current technology. The cavity geometry and the levitated mirror parameters are designed to ensure that the Brownian vibration of the mirror surface is smaller than the SQL. Our scheme provides a promising tool for testing macroscopic quantum mechanics.

Optical levitation of a mirror for reaching the standard quantum limit

NASA Astrophysics Data System (ADS)

Michimura, Yuta; Kuwahara, Yuya; Ushiba, Takafumi; Matsumoto, Nobuyuki; Ando, Masaki

2017-06-01

We propose a new method to optically levitate a macroscopic mirror with two vertical Fabry-P{\\'e}rot cavities linearly aligned. This configuration gives the simplest possible optical levitation in which the number of laser beams used is the minimum of two. We demonstrate that reaching the standard quantum limit (SQL) of a displacement measurement with our system is feasible with current technology. The cavity geometry and the levitated mirror parameters are designed to ensure that the Brownian vibration of the mirror surface is smaller than the SQL. Our scheme provides a promising tool for testing macroscopic quantum mechanics.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Data Processing for the Space-Based Desis Hyperspectral Sensor

NASA Astrophysics Data System (ADS)

Carmona, E.; Avbelj, J.; Alonso, K.; Bachmann, M.; Cerra, D.; Eckardt, A.; Gerasch, B.; Graham, L.; Günther, B.; Heiden, U.; Kerr, G.; Knodt, U.; Krutz, D.; Krawcyk, H.; Makarau, A.; Miller, R.; Müller, R.; Perkins, R.; Walter, I.

2017-05-01

The German Aerospace Center (DLR) and Teledyne Brown Engineering (TBE) have established a collaboration to develop and operate a new space-based hyperspectral sensor, the DLR Earth Sensing Imaging Spectrometer (DESIS). DESIS will provide spacebased hyperspectral data in the VNIR with high spectral resolution and near-global coverage. While TBE provides the platform and infrastructure for operation of the DESIS instrument on the International Space Station, DLR is responsible for providing the instrument and the processing software. The DESIS instrument is equipped with novel characteristics for an imaging spectrometer such high spectral resolution (2.55 nm), a mirror pointing unit or a CMOS sensor operated in rolling shutter mode. We present here an overview of the DESIS instrument and its processing chain, emphasizing the effect of the novel characteristics of DESIS in the data processing and final data products. Furthermore, we analyse in more detail the effect of the rolling shutter on the DESIS data and possible mitigation/correction strategies.

Functionalizing a Tapered Microcavity as a Gas Cell for On-Chip Mid-Infrared Absorption Spectroscopy

PubMed Central

Mandon, Julien; Harren, Frans J. M.; Wolffenbuttel, Reinoud F.

2017-01-01

Increasing demand for field instruments designed to measure gas composition has strongly promoted the development of robust, miniaturized and low-cost handheld absorption spectrometers in the mid-infrared. Efforts thus far have focused on miniaturizing individual components. However, the optical absorption path that the light beam travels through the sample defines the length of the gas cell and has so far limited miniaturization. Here, we present a functionally integrated linear variable optical filter and gas cell, where the sample to be measured is fed through the resonator cavity of the filter. By using multiple reflections from the mirrors on each side of the cavity, the optical absorption path is elongated from the physical μm-level to the effective mm-level. The device is batch-fabricated at the wafer level in a CMOS-compatible approach. The optical performance is analyzed using the Fizeau interferometer model and demonstrated with actual gas measurements. PMID:28878167

Forming Mandrels for X-Ray Mirror Substrates

NASA Technical Reports Server (NTRS)

Blake, Peter N.; Saha. To,p; Zhang, Will; O'Dell, Stephen; Kester, Thomas; Jones, William

2011-01-01

Precision forming mandrels are one element in X-ray mirror development at NASA. Current mandrel fabrication process is capable of meeting the allocated precision requirements for a 5 arcsec telescope. A manufacturing plan is outlined for a large IXO-scale program.

CMOS image sensors: State-of-the-art

NASA Astrophysics Data System (ADS)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

Variation and Defect Tolerance for Nano Crossbars

NASA Astrophysics Data System (ADS)

Tunc, Cihan

With the extreme shrinking in CMOS technology, quantum effects and manufacturing issues are getting more crucial. Hence, additional shrinking in CMOS feature size seems becoming more challenging, difficult, and costly. On the other hand, emerging nanotechnology has attracted many researchers since additional scaling down has been demonstrated by manufacturing nanowires, Carbon nanotubes as well as molecular switches using bottom-up manufacturing techniques. In addition to the progress in manufacturing, developments in architecture show that emerging nanoelectronic devices will be promising for the future system designs. Using nano crossbars, which are composed of two sets of perpendicular nanowires with programmable intersections, it is possible to implement logic functions. In addition, nano crossbars present some important features as regularity, reprogrammability, and interchangeability. Combining these features, researchers have presented different effective architectures. Although bottom-up nanofabrication can greatly reduce manufacturing costs, due to low controllability in the manufacturing process, some critical issues occur. Bottom- up nanofabrication process results in high variation compared to conventional top- down lithography used in CMOS technology. In addition, an increased failure rate is expected. Variation and defect tolerance methods used for conventional CMOS technology seem inadequate for adapting to emerging nano technology because the variation and the defect rate for emerging nano technology is much more than current CMOS technology. Therefore, variations and defect tolerance methods for emerging nano technology are necessary for a successful transition. In this work, in order to tolerate variations for crossbars, we introduce a framework that is established based on reprogrammability and interchangeability features of nano crossbars. This framework is shown to be applicable for both FET-based and diode-based nano crossbars. We present a characterization testing method which requires minimal number of test vectors. We formulate the variation optimization problem using Simulated Annealing with different optimization goals. Furthermore, we extend the framework for defect tolerance. Experimental results and comparison of proposed framework with exhaustive methods confirm its effectiveness for both variation and defect tolerance.

Characterization and development of an event-driven hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher

2015-06-01

Hybrid CMOS detectors (HCD) have provided great benefit to the infrared and optical fields of astronomy, and they are poised to do the same for X-ray astronomy. Infrared HCDs have already flown on the Hubble Space Telescope and the Wide-Field Infrared Survey Explorer (WISE) mission and are slated to fly on the James Webb Space Telescope (JWST). Hybrid CMOS X-ray detectors offer low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up. The fast readout time is necessary for future high throughput X-ray missions. The Speedster-EXD X-ray HCD presented in this dissertation offers new in-pixel features and reduces known noise sources seen on previous generation HCDs. The Speedster-EXD detector makes a great step forward in the development of these detectors for future space missions. This dissertation begins with an overview of future X-ray space mission concepts and their detector requirements. The background on the physics of semiconductor devices and an explanation of the detection of X-rays with these devices will be discussed followed by a discussion on CCDs and CMOS detectors. Next, hybrid CMOS X-ray detectors will be explained including their advantages and disadvantages. The Speedster-EXD detector and its new features will be outlined including its ability to only read out pixels which contain X-ray events. Test stand design and construction for the Speedster-EXD detector is outlined and the characterization of each parameter on two Speedster-EXD detectors is detailed including read noise, dark current, interpixel capacitance crosstalk (IPC), and energy resolution. Gain variation is also characterized, and a Monte Carlo simulation of its impact on energy resolution is described. This analysis shows that its effect can be successfully nullified with proper calibration, which would be important for a flight mission. Appendix B contains a study of the extreme tidal disruption event, Swift J1644+57, to search for periodicities in its X-ray light curve. iii.

A Design Methodology for Optoelectronic VLSI

DTIC Science & Technology

2007-01-01

current gets converted to a CMOS voltage level through a transimpedance amplifier circuit called a receiver. The output of the receiver is then...change the current flowing from the diode to a voltage that the logic inputs can use. That circuit is called a receiver. It is a transimpedance amplifier ...incorpo- rate random access memory circuits, SRAM or dynamic RAM (DRAM). These circuits use weak internal analog signals that are amplified by sense

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seco, Joao; Depauw, Nicolas

2011-02-15

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissuemore » contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.« less

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

PubMed

Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2012-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems

PubMed Central

Dey, Samrat; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2013-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs). PMID:24301987

Characterization of a medium-sized washer-gun for an axisymmetric mirror

NASA Astrophysics Data System (ADS)

Yi, Hongshen; Liu, Ming; Shi, Peiyun; Yang, Zhida; Zhu, Guanghui; Lu, Quanming; Sun, Xuan

2018-04-01

A new medium-sized washer gun is developed for a plasma start-up in a fully axisymmetric mirror. The gun is positioned at the east end of the Keda Mirror with AXisymmetricity facility and operated in the pulsed mode with an arc discharging time of 1.2 ms and a typical arc current of 8.5 kA with 1.5 kV discharge voltage. To optimize the operation, a systematic scan of the neutral pressure, the arc voltage, the bias voltage on a mesh grid 6 cm in front of the gun and an end electrode located on the west end of mirror, and the mirror ratio was performed. The streaming plasma was measured with triple probes in the three mirror cells and a diamagnetic loop in the central cell. Floating potential measurements suggest that the plasma could be divided into streaming and mirror-confined plasmas. The floating potential for the streaming plasma is negative, with an electric field pointing inwards. The mirror-confined plasma has a typical lifetime of 0.5 ms.

Characterization of a medium-sized washer-gun for an axisymmetric mirror.

PubMed

Yi, Hongshen; Liu, Ming; Shi, Peiyun; Yang, Zhida; Zhu, Guanghui; Lu, Quanming; Sun, Xuan

2018-04-01

A new medium-sized washer gun is developed for a plasma start-up in a fully axisymmetric mirror. The gun is positioned at the east end of the Keda Mirror with AXisymmetricity facility and operated in the pulsed mode with an arc discharging time of 1.2 ms and a typical arc current of 8.5 kA with 1.5 kV discharge voltage. To optimize the operation, a systematic scan of the neutral pressure, the arc voltage, the bias voltage on a mesh grid 6 cm in front of the gun and an end electrode located on the west end of mirror, and the mirror ratio was performed. The streaming plasma was measured with triple probes in the three mirror cells and a diamagnetic loop in the central cell. Floating potential measurements suggest that the plasma could be divided into streaming and mirror-confined plasmas. The floating potential for the streaming plasma is negative, with an electric field pointing inwards. The mirror-confined plasma has a typical lifetime of 0.5 ms.

Distributed sensing signal analysis of deformable plate/membrane mirrors

NASA Astrophysics Data System (ADS)

Lu, Yifan; Yue, Honghao; Deng, Zongquan; Tzou, Hornsen

2017-11-01

Deformable optical mirrors usually play key roles in aerospace and optical structural systems applied to space telescopes, radars, solar collectors, communication antennas, etc. Limited by the payload capacity of current launch vehicles, the deformable mirrors should be lightweight and are generally made of ultra-thin plates or even membranes. These plate/membrane mirrors are susceptible to external excitations and this may lead to surface inaccuracy and jeopardize relevant working performance. In order to investigate the modal vibration characteristics of the mirror, a piezoelectric layer is fully laminated on its non-reflective side to serve as sensors. The piezoelectric layer is segmented into infinitesimal elements so that microscopic distributed sensing signals can be explored. In this paper, the deformable mirror is modeled as a pre-tensioned plate and membrane respectively and sensing signal distributions of the two models are compared. Different pre-tensioning forces are also applied to reveal the tension effects on the mode shape and sensing signals of the mirror. Analytical results in this study could be used as guideline of optimal sensor/actuator placement for deformable space mirrors.

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Cargo Movement Operations System (CMOS) System Segment Design Document (Draft) Increment II

DTIC Science & Technology

1990-05-02

and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR

Heightened motor and sensory (mirror-touch) referral induced by nerve block or topical anesthetic.

PubMed

Case, Laura K; Gosavi, Radhika; Ramachandran, Vilayanur S

2013-08-01

Mirror neurons allow us to covertly simulate the sensation and movement of others. If mirror neurons are sensory and motor neurons, why do we not actually feel this simulation- like "mirror-touch synesthetes"? Might afferent sensation normally inhibit mirror representations from reaching consciousness? We and others have reported heightened sensory referral to phantom limbs and temporarily anesthetized arms. These patients, however, had experienced illness or injury of the deafferented limb. In the current study we observe heightened sensory and motor referral to the face after unilateral nerve block for routine dental procedures. We also obtain double-blind, quantitative evidence of heightened sensory referral in healthy participants completing a mirror-touch confusion task after topical anesthetic cream is applied. We suggest that sensory and motor feedback exist in dynamic equilibrium with mirror representations; as feedback is reduced, the brain draws more upon visual information to determine- perhaps in a Bayesian manner- what to feel. Copyright © 2013 Elsevier Ltd. All rights reserved.

Lightweight ZERODUR mirror blanks: recent advances supporting faster, cheaper, and better spaceborne optical telescope assemblies

NASA Astrophysics Data System (ADS)

Hull, Tony; Westerhoff, Thomas

2014-10-01

While there is no single material solution ideal for all missions, recent advances by SCHOTT in fabricating lightweight mirror blanks makes ZERODUR® a highly viable solution for many spaceborne telescopes. ZERODUR® is a well-characterized very low-expansion material. Monolithic mirrors are made without bonding or fusing out of highly homogeneous and isotropic blanks currently available in sizes up to 4m plus. We will summarize results recently given in a series of papers on the characteristics of these lightweight mirror blanks in sizes from 0.3m up, and describe the method of blank fabrication, with its compatibility to contemporary optical fabrication techniques that control of all optical spatial frequencies. ZERODUR® has a 35 year heritage in space on numerous missions, including the secondary mirror of Hubble, and all the Chandra mirrors. With the lightweighting we will discuss, ZERODUR® is now a high performing, affordable and rapidly produced mirror substrate suitable for lightweight imaging telescopes.

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

PubMed

Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

2017-09-09

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

PubMed Central

Han, Seong-Tae; Baek, Donghyun

2017-01-01

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB. PMID:28891927

A CMOS active pixel sensor for retinal stimulation

NASA Astrophysics Data System (ADS)

Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

2006-02-01

Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

NASA Astrophysics Data System (ADS)

Ren, Kun; Zheng, Jiachen; Lu, Haiyan; Liu, Jun; Wu, Lishu; Zhou, Wenyong; Cheng, Wei

2018-05-01

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate. The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger, of 0.8 μm in width and 5 μm in length, are changed unobviously, while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz, respectively. In order to have a detailed insight on the degradation of the RF performance, small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted. The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself. Project supported by the National Natural Science Foundation of China (No. 61331006) and the Natural Science Foundation of Zhejiang Province (No. Y14F010017).

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Kuan, Bao; Xiangning, Fan; Wei, Li; Zhigong, Wang

2013-01-01

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a -1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

NASA Astrophysics Data System (ADS)

Toriumi, Akira; Nishimura, Tomonori

2018-01-01

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO2/Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO2/Ge interface should be intensively studied to make the best of Ge’s advantages. Therefore we first discuss the GeO2/Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge’s intrinsic properties because they are derived from the strong Fermi-level pinning and the narrow energy band gap, respectively. Even if the carrier transport in the channel may be ideally ballistic, these properties should degrade FET properties. The narrower energy band gap of Ge is often addressed, but the higher dielectric constant of Ge is rarely discussed. This is also the case for most of the other high-mobility materials. The dielectric constant is directly and negatively related to short-channel effects, and we have not been able to provide a substantial solution to overcome this hardship. We have to keep this in mind for the short-channel FET operation. Although a number of problems remain to be solved, in this paper, we view the current status of Ge FET technology positively. A number of (but not all) Ge-related challenges have been overcome in the past 10 years, which seems to be a good time to summarize the status of Ge technology, particularly materials engineering aspects rather than device integration issues. Since we cannot cover all of the results published to date, we mainly discuss fundamental aspects based on our experimental results. Remaining challenges are also addressed but not comprehensively. Integration issues are not discussed in this review. Finally, new types of electron devices utilizing Ge’s advantages are briefly introduced on the basis of our experimental results.

Do 'literate' pigeons (Columba livia) show mirror-word generalization?

PubMed

Scarf, Damian; Corballis, Michael C; Güntürkün, Onur; Colombo, Michael

2017-09-01

Many children pass through a mirror stage in reading, where they write individual letters or digits in mirror and find it difficult to correctly utilize letters that are mirror images of one another (e.g., b and d). This phenomenon is thought to reflect the fact that the brain does not naturally discriminate left from right. Indeed, it has been argued that reading acquisition involves the inhibition of this default process. In the current study, we tested the ability of literate pigeons, which had learned to discriminate between 30 and 62 words from 7832 nonwords, to discriminate between words and their mirror counterparts. Subjects were sensitive to the left-right orientation of the individual letters, but not the order of letters within a word. This finding may reflect the fact that, in the absence of human-unique top-down processes, the inhibition of mirror generalization may be limited.

Constraints on mirror models of dark matter from observable neutron-mirror neutron oscillation

NASA Astrophysics Data System (ADS)

Mohapatra, Rabindra N.; Nussinov, Shmuel

2018-01-01

The process of neutron-mirror neutron oscillation, motivated by symmetric mirror dark matter models, is governed by two parameters: n -n‧ mixing parameter δ and n -n‧ mass splitting Δ. For neutron mirror neutron oscillation to be observable, the splitting between their masses Δ must be small and current experiments lead to δ ≤ 2 ×10-27 GeV and Δ ≤10-24 GeV. We show that in mirror universe models where this process is observable, this small mass splitting constrains the way that one must implement asymmetric inflation to satisfy the limits of Big Bang Nucleosynthesis on the number of effective light degrees of freedom. In particular we find that if asymmetric inflation is implemented by inflaton decay to color or electroweak charged particles, the oscillation is unobservable. Also if one uses SM singlet fields for this purpose, they must be weakly coupled to the SM fields.

A ferrofluidic deformable mirror for ophthalmology

NASA Astrophysics Data System (ADS)

Macpherson, J. B.; Thibault, S.; Borra, E. F.; Ritcey, A. M.; Carufel, N.; Asselin, D.; Jerominek, H.; Campbell, M. C. W.

2005-09-01

Optical aberrations reduce the imaging quality of the human eye. In addition to degrading vision, this limits our ability to illuminate small points of the retina for therapeutic, surgical or diagnostic purposes. When viewing the rear of the eye, aberrations cause structures in the fundus to appear blurred, limiting the resolution of ophthalmoscopes (diagnostic instruments used to image the eye). Adaptive optics, such as deformable mirrors may be used to compensate for aberrations, allowing the eye to work as a diffraction-limited optical element. Unfortunately, this type of correction has not been widely available for ophthalmic applications because of the expense and technical limitations of current deformable mirrors. We present preliminary design and characterisation of a deformable mirror suitable for ophthalmology. In this ferrofluidic mirror, wavefronts are reflected from a fluid whose surface shape is controlled by a magnetic field. Challenges in design are outlined, as are advantages over traditional deformable mirrors.

Active Optical Zoom for Tracking

DTIC Science & Technology

2008-09-01

optical system. 2. Current Setup Deformable Flat Two Deformable Flat Figure 1. Zemax lens design layout and experimental layout on the...optical bench. Figure 1 is a ZEMAX design and setup on the optical bench of two Deformable Mirrors (DMs) from OKO technologies. These mirrors have

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Detection of CMOS bridging faults using minimal stuck-at fault test sets

NASA Technical Reports Server (NTRS)

Ijaz, Nabeel; Frenzel, James F.

1993-01-01

The performance of minimal stuck-at fault test sets at detecting bridging faults are evaluated. New functional models of circuit primitives are presented which allow accurate representation of bridging faults under switch-level simulation. The effectiveness of the patterns is evaluated using both voltage and current testing.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

High-resolution wavefront control of high-power laser systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brase, J; Brown, C; Carrano, C

1999-07-08

Nearly every new large-scale laser system application at LLNL has requirements for beam control which exceed the current level of available technology. For applications such as inertial confinement fusion, laser isotope separation, laser machining, and laser the ability to transport significant power to a target while maintaining good beam quality is critical. There are many ways that laser wavefront quality can be degraded. Thermal effects due to the interaction of high-power laser or pump light with the internal optical components or with the ambient gas are common causes of wavefront degradation. For many years, adaptive optics based on thing deformablemore » glass mirrors with piezoelectric or electrostrictive actuators have be used to remove the low-order wavefront errors from high-power laser systems. These adaptive optics systems have successfully improved laser beam quality, but have also generally revealed additional high-spatial-frequency errors, both because the low-order errors have been reduced and because deformable mirrors have often introduced some high-spatial-frequency components due to manufacturing errors. Many current and emerging laser applications fall into the high-resolution category where there is an increased need for the correction of high spatial frequency aberrations which requires correctors with thousands of degrees of freedom. The largest Deformable Mirrors currently available have less than one thousand degrees of freedom at a cost of approximately $1M. A deformable mirror capable of meeting these high spatial resolution requirements would be cost prohibitive. Therefore a new approach using a different wavefront control technology is needed. One new wavefront control approach is the use of liquid-crystal (LC) spatial light modulator (SLM) technology for the controlling the phase of linearly polarized light. Current LC SLM technology provides high-spatial-resolution wavefront control, with hundreds of thousands of degrees of freedom, more than two orders of magnitude greater than the best Deformable Mirrors currently made. Even with the increased spatial resolution, the cost of these devices is nearly two orders of magnitude less than the cost of the largest deformable mirror.« less

Mirror force induced wave dispersion in Alfvén waves

DOE Office of Scientific and Technical Information (OSTI.GOV)

Damiano, P. A.; Johnson, J. R.

2013-06-15

Recent hybrid MHD-kinetic electron simulations of global scale standing shear Alfvén waves along the Earth's closed dipolar magnetic field lines show that the upward parallel current region within these waves saturates and broadens perpendicular to the ambient magnetic field and that this broadening increases with the electron temperature. Using resistive MHD simulations, with a parallel Ohm's law derived from the linear Knight relation (which expresses the current-voltage relationship along an auroral field line), we explore the nature of this broadening in the context of the increased perpendicular Poynting flux resulting from the increased parallel electric field associated with mirror forcemore » effects. This increased Poynting flux facilitates wave energy dispersion across field lines which in-turn allows for electron acceleration to carry the field aligned current on adjacent field lines. This mirror force driven dispersion can dominate over that associated with electron inertial effects for global scale waves.« less

Compact antenna for two-dimensional beam scan in the JT-60U electron cyclotron heating/current drive system

NASA Astrophysics Data System (ADS)

Moriyama, S.; Kajiwara, K.; Takahashi, K.; Kasugai, A.; Seki, M.; Ikeda, Y.; Fujii, T.

2005-11-01

A compact antenna system was designed and fabricated to enable millimeter-wave beam scanning in the toroidal and poloidal directions of the JT-60U tokamak for electron cyclotron heating (ECH) and electron cyclotron current drive (ECCD) experiments. The antenna consists of a fast movable flat mirror mounted on the tokamak vacuum vessel and a rotary focusing mirror attached at the end of the waveguide that is supported from outside the vacuum vessel. This separate support concept enables a compact structure inside a shallow port (0.68×0.54×0.2m) that is shared with a subport for an independent diagnostic system. During a plasma shot, the flat mirror is driven by a servomotor with a 3-m-long drive shaft to reduce the influence of the high magnetic field on the motor. The focusing mirror is rotated by a simple mechanism utilizing a push rod and an air cylinder. The antenna has been operated reliably for 3 years after a small improvement to the rotary drive mechanism. It has made significant contributions to ECH and ECCD experiments, especially the current profile control in JT-60U.

Adaptive grazing incidence optics for the next generation of x-ray observatories

NASA Astrophysics Data System (ADS)

Lillie, C.; Pearson, D.; Plinta, A.; Metro, B.; Lintz, E.; Shropshire, D.; Danner, R.

2010-09-01

Advances in X-ray astronomy require high spatial resolution and large collecting area. Unfortunately, X-ray telescopes with grazing incidence mirrors require hundreds of concentric mirror pairs to obtain the necessary collecting area, and these mirrors must be thin shells packed tightly together... They must also be light enough to be placed in orbit with existing launch vehicles, and able to be fabricated by the thousands for an affordable cost. The current state of the art in X-ray observatories is represented by NASA's Chandra X-ray observatory with 0.5 arc-second resolution, but only 400 cm2 of collecting area, and by ESA's XMM-Newton observatory with 4,300 cm2 of collecting area but only 15 arc-second resolution. The joint NASA/ESA/JAXA International X-ray Observatory (IXO), with {15,000 cm2 of collecting area and 5 arc-second resolution which is currently in the early study phase, is pushing the limits of passive mirror technology. The Generation-X mission is one of the Advanced Strategic Mission Concepts that NASA is considering for development in the post-2020 period. As currently conceived, Gen-X would be a follow-on to IXO with a collecting area >= 50 m2, a 60-m focal length and 0.1 arc-second spatial resolution. Gen-X would be launched in {2030 with a heavy lift Launch Vehicle to an L2 orbit. Active figure control will be necessary to meet the challenging requirements of the Gen-X optics. In this paper we present our adaptive grazing incidence mirror design and the results from laboratory tests of a prototype mirror.

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix, Version 3 Increment II

DTIC Science & Technology

1990-12-17

above SCs should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...These two documents should be in agreement with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...completeness, they should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

InGaAsP/InP buried-heterostructure lasers /lambda = 1.5 microns/ with chemically etched mirrors

NASA Astrophysics Data System (ADS)

Adachi, S.; Kawaguchi, H.; Takahei, K.; Noguchi, Y.

1981-09-01

The monolithic fabrication of buried heterostructure InGaAsP/InP lasers operating at a wavelength of 1.5 microns with chemically etched mirrors is reported. The buried heterostructure lasers were prepared from InGaAsP/InP DH wafers reverse-mesa etched with a Br2:CH3OH solution, with the reverse-mesa walls buried by subsequent LPE growth. To fabricate the etched mirror laser, Au-Zn metal was evaporated onto the epitaxial-layer side of the wafer and an Au-Zn contact was defined by photolithography; photolithographic techniques were used to define a SiO2 mask directly over the Au-Zn contact for etched mirror definition using either 0.3 vol % Br2:CH3OH or HCl:CH3COOH:H2O2 1:2:1 solutions. A threshold current of 50 mA is obtained from lasers thus produced, which is nearly the same as that of conventionally fabricated cleaved-mirror lasers. The procedure presented thus allows low threshold-current devices to be obtained with a much greater flexibility in design and fabrication than previously attained.

High-density CMOS Microelectrode Array System for Impedance Spectroscopy and Imaging of Biological Cells.

PubMed

Vijay, Viswam; Raziyeh, Bounik; Amir, Shadmani; Jelena, Dragas; Alicia, Boos Julia; Axel, Birchler; Jan, Müller; Yihui, Chen; Andreas, Hierlemann

2017-01-26

A monolithic measurement platform was implemented to enable label-free in-vitro electrical impedance spectroscopy measurements of cells on multi-functional CMOS microelectrode array. The array includes 59,760 platinum microelectrodes, densely packed within a 4.5 mm × 2.5 mm sensing region at a pitch of 13.5 μm. The 32 on-chip lock-in amplifiers can be used to measure the impedance of any arbitrarily chosen electrodes on the array by applying a sinusoidal voltage, generated by an on-chip waveform generator with a frequency range from 1 Hz to 1 MHz, and measuring the respective current. Proof-of-concept measurements of impedance sensing and imaging are shown in this paper. Correlations between cell detection through optical microscopy and electrochemical impedance scanning were established.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

Aluminum Mirror Coatings for UVOIR Telescope Optics Including the Far UV

NASA Technical Reports Server (NTRS)

Balasubramanian, Kunjithapatha; Hennessy, John; Raouf, Nasrat; Nikzad, Shouleh; Ayala, Michael; Shaklan, Stuart; Scowen, Paul; Del Hoyo, Javier; Quijada, Manuel

2015-01-01

NASA Cosmic Origins (COR) Program identified the development of high reflectivity mirror coatings for large astronomical telescopes particularly for the far ultra violet (FUV) part of the spectrum as a key technology requiring significant materials research and process development. In this paper we describe the challenges and accomplishments in producing stable high reflectance aluminum mirror coatings with conventional evaporation and advanced Atomic Layer Deposition (ALD) techniques. We present the current status of process development with reflectance of approx. 55 to 80% in the FUV achieved with little or no degradation over a year. Keywords: Large telescope optics, Aluminum mirror, far UV astrophysics, ALD, coating technology development.

Cryogenic Optical Performance of a Light-weight Mirror Assembly for Future Space Astronomical Telescopes: Optical Test Results and Thermal Optical Model

NASA Technical Reports Server (NTRS)

Eng, Ron; Arnold, William; Baker, Markus A.; Bevan, Ryan M.; Carpenter, James R.; Effinger, Michael R.; Gaddy, Darrell E.; Goode, Brian K.; Kegley, Jeffrey R.; Hogue, William D.;

Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor

PubMed Central

Dennis, John Ojur; Ahmad, Farooq; Khir, M. Haris Bin Md; Hamid, Nor Hisham Bin

2015-01-01

Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT. PMID:26225972

Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor.

PubMed

Dennis, John Ojur; Ahmad, Farooq; Khir, M Haris Bin Md; Bin Hamid, Nor Hisham

2015-07-27

Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

PubMed

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

2015-10-01

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Cargo Movement Operations System (CMOS) Final Software User’s Manual

DTIC Science & Technology

1990-12-20

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ I COMMENT STATUS: OPEN...is correct. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS CO1MENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...RATIONALE: .."DA001041" is in the SUM but not in the SDD. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

The multispectral instrument of the Sentinel2 program

NASA Astrophysics Data System (ADS)

Cazaubiel, V.; Chorvalli, Vincent; Miesch, Christophe

2017-11-01

The Sentinel-2 program will provide a permanent record of comprehensive data to help inform the agricul-tural sector (utilisation, coverage), forestry industry (population, damage, forest fires), disaster control (management, early warning) and humanitarian relief programmes. Sentinel-2 will also be able to observe natural disasters such as floods, volcanic eruptions, subsidence and landslides. In the Sentinel-2 mission programme, Astrium in Friedrichshafen is responsible for the satellite's system design and platform, as well as for satellite integration and testing. Astrium Toulouse will supply the Multi-Spectral imaging Instrument (MSI), and Astrium Spain will be in charge of the satellite's structure and will produce its thermal equipment and cable harness. The industrial core team also comprises Jena Optronik (Germany), Boostec (France), Sener and GMV (Spain). Sentinel-2 is intended to image the Earth's landmasses from its orbit for at least 7.25 years. In addition, its onboardresources will be designed so that the mission can be prolonged by an extra five years. From 2012 onwards, the 1.1-metric-ton satellite will circle the Earth in a sun-synchronous, polar orbit at an altitude of 786kilometres, fully covering the planet's landmasses in just ten days. The multi-spectral instrument (MSI) will generate optical images in 13 spectral channels in the visible and shortwave infrared range down to a resolution of 10 metres with an image width of 290 kilometres. The instrument is composed of two main parts: • The telescope assembly , combining in one instrument both VNIR and SWIR channels, is mounted on the upper plate of the Bus • The Video and Compression Electronic Units mounted inside the Bus. This telescope is based on a Three Mirror Anastigmat optical concept. This three mirror optical combination is corrected from spherical aberration, coma and astigmatism. It provides a large field of view with very good optical quality. The telescope mirrors and structural baseplate are made of Silicon Carbide material in order to minimise thermo-elastic distortions. Isostatic mounts decouple the instrument from potential deformations of the platform upper plate. The optical beam is spectrally separated thanks to a dichroic filter towards two different focal planes with different detector technologies: Silicon is used for the VNIR domain whereas Mercury Cadmium Telluride is required for the SWIR spectral domain. The VNIR detector is a CMOS device. The SWIR detector is a hybridised component where the MCT photosensitive arrays are hybridised on top of a CMOS circuit. The separation of the individual spectral bands(10 spectral bands, for the VNIR detectors and 3 spectral bands for the SWIR detectors) is performed by specific strip filters mounted on top of the detectors. The telescope is thermally decoupled from the external environment and the platform thanks to a thermal enclosure. A calibration and shutter mechanism avoids direct sun incidence inside the telescope during launch, specific platform manoeuvres and safe mode. The video signals coming out of the VNIR and SWIR focal planes are digitised and compressed inside the Video and Electronic Units prior to be sent to the bus.

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

The challenge of sCMOS image sensor technology to EMCCD

NASA Astrophysics Data System (ADS)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

APF-The Lick Observatory Automated Planet Finder

DTIC Science & Technology

2014-04-01

resolutions up to 150,000. Overall system efficiency (fraction of photons incident on the primary mirror that are detected by the science CCD) on blaze at...A second (currently unused) Nasmyth focus can be quickly accessed via a rotatable tertiary mirror . The telescope uses a 2.41 m diameter f=1:5 primary...within 0.5″, and 90% encircled energy within 1″. The mount for the secondary mirror M2 incorporates an active tip/tilt and focus system that corrects for

Measurement of Electron Beam Emittance Using Optical Transition Radiation and Development of a Diffuse Screen Electron Beam Monitor

DTIC Science & Technology

1990-12-01

Zerodur ,irror, 2" relfects light. 1OZ20BD.1; 20th wave zerodur mirror , 1" reflects light. LS-35; 3’ x 5’ optical breadboard; for mounting components...profile measurements using the diffuse screen were compared with measurements using a front surface mirror and a fluorescent screen. The 20 DISTRIBUTION...Beam current and profile measurements using the diffuse screen were compared with measurements using a front surface mirror and a fluorescent screen

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Towards plasma cleaning of ITER first mirrors

NASA Astrophysics Data System (ADS)

Moser, L.; Marot, L.; Eren, B.; Steiner, R.; Mathys, D.; Leipold, F.; Reichle, R.; Meyer, E.

2015-06-01

To avoid reflectivity losses in ITER's optical diagnostic systems, on-site cleaning of metallic first mirrors via plasma sputtering is foreseen to remove deposit build-ups migrating from the main wall. In this work, the influence of aluminium and tungsten deposits on the reflectivity of molybdenum mirrors as well as the possibility to clean them with plasma exposure is investigated. Porous ITER-like deposits are grown to mimic the edge conditions expected in ITER, and a severe degradation in the specular reflectivity is observed as these deposits build up on the mirror surface. In addition, dense oxide films are produced for comparisons with porous films. The composition, morphology and crystal structure of several films were characterized by means of scanning electron microscopy, x-ray photoelectron spectroscopy, x-ray diffraction and secondary ion mass spectrometry. The cleaning of the deposits and the restoration of the mirrors' optical properties are possible either with a Kaufman source or radio frequency directly applied to the mirror (or radio frequency plasma generated directly around the mirror surface). Accelerating ions of an external plasma source through a direct current applied onto the mirror does not remove deposits composed of oxides. A possible implementation of plasma cleaning in ITER is addressed.

Gondola for High Altitude Planetary Science (GHAPS) Telescope Secondary Mirror Positioning Hexapod Issues and Alternatives

NASA Technical Reports Server (NTRS)

Wells, Mark

2017-01-01

Active positioning of the GHAPS secondary telescope mirror is desired to correct for rigid body deflections due to temperature variations and gravity sag in the telescope structure that may impact optical performance. The current design concept for the secondary mirror mount uses a Commercial-Off -the-Shelf hexapod for mirror positioning and fine adjustment. The Hexapod specification states that motions as small as 0.1 microns along the optical axis and 2 microns perpendicular to the optical axis will cause optical aberrations that will require correction by repositioning the secondary mirror. In addition, the secondary mirror mount and positioning system must survive a 15g shock of parachute opening and landing during the instrument recovery operation. The secondary mirror positioning system must operate at a minimum specified temperature of -50 C. The telescope operates in the IR and the secondary mirror mount and positioning device is in the metering path between the primary and secondary mirrors. I2R losses in positioning system actuator devices, which may cause heating of the positioning system and secondary mirror, must be minimized due to the previously mentioned alignment sensitivity and the viewing spectrum of interest. The GHAPs project was cancelled on June 30, 2017. The purpose of this study is to address some of the issues identified with the hexapod secondary mirror positioning system and identify alternative approaches. This information may be used if the project is re-started at a later date.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Investigation of Gallium Nitride Transistor Reliability through Accelerated Life Testing and Modeling

DTIC Science & Technology

2011-12-01

Carbon Cd Cadmium CdS Cadmium Sulfide CMOS Complementary Metal Oxide Semiconductor DC Direct Current DoD Department of Defense EBL Electron...Crane Division [NAVSEA Crane], Crane, Indiana ) are Section 4.1and Section 4.3, Condition 2. Eight devices were stressed for over 1000 hours each and

A 0.2 V Micro-Electromechanical Switch Enabled by a Phase Transition.

PubMed

Dong, Kaichen; Choe, Hwan Sung; Wang, Xi; Liu, Huili; Saha, Bivas; Ko, Changhyun; Deng, Yang; Tom, Kyle B; Lou, Shuai; Wang, Letian; Grigoropoulos, Costas P; You, Zheng; Yao, Jie; Wu, Junqiao

2018-04-01

Micro-electromechanical (MEM) switches, with advantages such as quasi-zero leakage current, emerge as attractive candidates for overcoming the physical limits of complementary metal-oxide semiconductor (CMOS) devices. To practically integrate MEM switches into CMOS circuits, two major challenges must be addressed: sub 1 V operating voltage to match the voltage levels in current circuit systems and being able to deliver at least millions of operating cycles. However, existing sub 1 V mechanical switches are mostly subject to significant body bias and/or limited lifetimes, thus failing to meet both limitations simultaneously. Here 0.2 V MEM switching devices with ≳10 6 safe operating cycles in ambient air are reported, which achieve the lowest operating voltage in mechanical switches without body bias reported to date. The ultralow operating voltage is mainly enabled by the abrupt phase transition of nanolayered vanadium dioxide (VO 2 ) slightly above room temperature. The phase-transition MEM switches open possibilities for sub 1 V hybrid integrated devices/circuits/systems, as well as ultralow power consumption sensors for Internet of Things applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Microbeam mapping of single event latchups and single event upsets in CMOS SRAMs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barak, J.; Adler, E.; Fischer, B.E.

1998-06-01

The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. The authors found that the shapes of the sensitive areas depend on V{sub DD}, on the ions being used and on the site on the chip being hit by the ion. In particular, they found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which they call indirect SEUs in contrast to the well known SEUs induced inmore » the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only indirect SEL sensitive sites could be detected. They interpret these events as latent latchups in contrast to the classical ones detected by their induced current surge. These latent SELs were probably decoupled from the main supply lines by the high resistivity of the local supply lines.« less

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

NASA Astrophysics Data System (ADS)

Hande, Vinayak; Shojaei Baghini, Maryam

2015-08-01

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/°C is achieved over -25 to 125 °C temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm2

Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

2016-12-01

Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

Development of CMOS pixel sensors for the upgrade of the ALICE Inner Tracking System

NASA Astrophysics Data System (ADS)

Molnar, L.

2014-12-01

The ALICE Collaboration is preparing a major upgrade of the current detector, planned for installation during the second long LHC shutdown in the years 2018-19, in order to enhance its low-momentum vertexing and tracking capability, and exploit the planned increase of the LHC luminosity with Pb beams. One of the cornerstones of the ALICE upgrade strategy is to replace the current Inner Tracking System in its entirety with a new, high resolution, low-material ITS detector. The new ITS will consist of seven concentric layers equipped with Monolithic Active Pixel Sensors (MAPS) implemented using the 0.18 μm CMOS technology of TowerJazz. In this contribution, the main key features of the ITS upgrade will be illustrated with emphasis on the functionality of the pixel chip. The ongoing developments on the readout architectures, which have been implemented in several fabricated prototypes, will be discussed. The operational features of these prototypes as well as the results of the characterisation tests before and after irradiation will also be presented.

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE PAGES

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua; ...

2017-05-08

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

THE DESIGN AND FABRICATION OF A LOWER COST HELIOSTAT MIRROR SYSTEM FOR UTILIZING SOLAR ENERGY

EPA Science Inventory

A heliostat is a mirror based system which is used to continuously reflect sunlight onto a central receiver. The collected solar energy is then converted into electrical power. Currently, costs associated with the construction and maintenance of heliostats have proven prohibit...

Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

NASA Technical Reports Server (NTRS)

Lee, C.; Johnston, A.

1998-01-01

This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Mirror Observation of Finger Action Enhances Activity in Anterior Intraparietal Sulcus: A Functional Magnetic Resonance Imaging Study

PubMed Central

Murayama, Takashi; Takasugi, Jun; Monma, Masahiko; Oga, Masaru

2013-01-01

Mirror therapy can be used to promote recovery from paralysis in patients with post-stroke hemiplegia, There are a lot of reports that mirror-image observation of the unilateral moving hand enhanced the excitability of the primary motor area (M1) ipsilateral to the moving hand in healthy subjects. but the neural mechanisms underlying its therapeutic effects are currently unclear. To investigate this issue, we used functional magnetic resonance imaging to measure activity in brain regions related to visual information processing during mirror image movement observation. Thirteen healthy subjects performed a finger-thumb opposition task with the left and right hands separately, with or without access to mirror observation. In the mirror condition, one hand was reflected in a mirror placed above the abdomen in the MRI scanner. In the masked mirror condition, subjects performed the same task but with the mirror obscured. In both conditions, the other hand was held at rest behind the mirror. A between-task comparison (mirror versus masked mirror) revealed significant activation in the ipsilateral hemisphere in the anterior intraparietal sulcus (aIP) while performing all tasks, regardless of which hand was used. The right aIP was significantly activated while moving the right hand. In contrast, in the left aIP, a small number of voxels showed a tendency toward activation during both left and right hand movement. The enhancement of ipsilateral aIP activity by the mirror image observation of finger action suggests that bimodal aIP neurons can be activated by visual information. We propose that activation in the M1 ipsilateral to the moving hand can be induced by information passing through the ventral premotor area from the aIP. PMID:25792898

Cryogenic Optical Performance of a Lightweighted Mirror Assembly for Future Space Astronomical Telescopes: Correlating Optical Test Results and Thermal Optical Model

NASA Technical Reports Server (NTRS)

Eng, Ron; Arnold, William R.; Baker, Marcus A.; Bevan, Ryan M.; Burdick, Gregory; Effinger, Michael R.; Gaddy, Darrell E.; Goode, Brian K.; Hanson, Craig; Hogue, William D.;

Electroformed Nickel-Graphite Composite

NASA Technical Reports Server (NTRS)

Xiong-Skiba, Pei

2005-01-01

Future x-ray astronomy will demand larger optics than Chandra, currently in orbit. Ways must be devised to produce cheaper and lighter x-ray mirrors to save the cost of manufacturing and launching this future telescope. One technique, being developed at Marshall Space Flight Center and elsewhere, is electroformed nickel replication technique, wherein mirror shells are electroformed (using pure nickel or a nickel alloy) onto super-polished and figured aluminum mandrels and are subsequently released by cooling. This technique can produce relatively inexpensive mirrors, but is hampered by the high density of nickel (8.9 g / cm3). An alternative is to develop a composite, with lower mass density and compatible mechanical properties to the nickel cobalt alloy, as the mirror shell material.

Self-amplified CMOS image sensor using a current-mode readout circuit

NASA Astrophysics Data System (ADS)

Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

2014-05-01

The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Status of the Advanced Mirror Technology Development (AMTD) Phase 2, 1.5m ULE(Registered Trademark) Mirror

NASA Technical Reports Server (NTRS)

Egerman, Robert; Matthews, Gary W.; Johnson, Matthew; Ferland, Albert; Stahl, H. Philip; Eng, Ron; Effinger, Michael R.

2015-01-01

The Decadal Survey stated that an advanced large-aperture ultraviolet, optical, near-infrared (UVOIR) telescope is required to enable the next generation of compelling astrophysics and exoplanet science; and, that present technology is not mature enough to affordably build and launch any potential UVOIR mission concept. Under Science and Technology funding, NASA's Marshall Space Flight Center (MSFC) and Exelis have developed a more cost effective process to make up to 4m monolithic spaceflight UV quality, low areal density, thermally and dynamically stable primary mirrors. Under a Phase I program, a proof of concept mirror was completed at Exelis and tested down to 250K at MSFC which would allow imaging out to 2.5 microns. In 2014, Exelis and NASA started a Phase II program to design and build a 1.5m mirror to demonstrate lateral scalability to a 4m monolithic primary mirror. The current status of the Phase II development program will be provided along with a Phase II program summary.

Low-stress mounting configuration design for large aperture laser transport mirror

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Quan, Xusong; Yao, Chao; Wang, Hui

2016-10-01

TM1-6S1 large aperture laser transport mirror is a crucial optical unit of high power solid-state laser in the Inertial Confinement Fusion (ICF) facility. This article focuses on the low-stress and precise mounting method of large-aperture mirror. Based on the engineering practice of SG-III, the state-of-the-art and key problems of current mounting configuration are clarified firstly. Subsequently, a brand new low-stress mounting configuration with flexure supports is proposed. Opto-mechanical model of the mirror under mounting force is built up with elastic mechanics theory. Further, numerical methods and field tests are employed to verify the favorable load uniform capacity and load adjust capacity of flexure supports. With FEM, the relation between the mounting force from new configuration and the mirror surface distortion (wavefront error) is clarified. The novel mounting method of large aperture optics could be not only used on this laser transport mirror, but also on the other transmission optics and large crystals in ICF facilities.

James Webb Space Telescope's Golden Mirror Unveiled

NASA Image and Video Library

2017-12-08

NASA engineers unveil the giant golden mirror of NASA's James Webb Space Telescope, and it's goldenly delicious! The 18 mirrors that make up the primary mirror were individually protected with a black covers when they were assembled on the telescope structure. Now, for the first time since the primary mirror was completed, the covers have been lifted. Standing tall and glimmering gold inside NASA's Goddard Space Flight Center's clean room in Greenbelt, Maryland, this mirror will be the largest yet sent into space. Currently, engineers are busy assembling and testing the other pieces of the telescope. Read more: go.nasa.gov/1TejHg4 Credit: NASA/Goddard/Chris Gunn NASA image use policy. NASA Goddard Space Flight Center enables NASA’s mission through four scientific endeavors: Earth Science, Heliophysics, Solar System Exploration, and Astrophysics. Goddard plays a leading role in NASA’s accomplishments by contributing compelling scientific knowledge to advance the Agency’s mission. Follow us on Twitter Like us on Facebook Find us on Instagram

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

The Pr 2O 3/Si(0 0 1) interface studied by synchrotron radiation photo-electron spectroscopy

NASA Astrophysics Data System (ADS)

Schmeißer, D.; Müssig, H.-J.

2003-10-01

Pr 2O 3 is currently under consideration as a potential replacement for SiO 2 as the gate-dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. We studied the Pr 2O 3/Si(0 0 1) interface by a non-destructive depth profiling using synchrotron radiation photoelectron spectroscopy. Our data suggests that there is no silicide formation at the interface. Based on reported results, a chemical reactive interface exists, consisting of a mixed Si-Pr oxide such as (Pr 2O 3) x(SiO 2) 1- x, i.e. as a silicate phase with variable silicon content. This pseudo-binary alloy at the interface offers large flexibility toward successful integration of Pr 2O 3 into future CMOS technologies.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

PubMed

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

PubMed Central

Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

2016-01-01

The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

Centroid Position as a Function of Total Counts in a Windowed CMOS Image of a Point Source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wurtz, R E; Olivier, S; Riot, V

2010-05-27

We obtained 960,200 22-by-22-pixel windowed images of a pinhole spot using the Teledyne H2RG CMOS detector with un-cooled SIDECAR readout. We performed an analysis to determine the precision we might expect in the position error signals to a telescope's guider system. We find that, under non-optimized operating conditions, the error in the computed centroid is strongly dependent on the total counts in the point image only below a certain threshold, approximately 50,000 photo-electrons. The LSST guider camera specification currently requires a 0.04 arcsecond error at 10 Hertz. Given the performance measured here, this specification can be delivered with a singlemore » star at 14th to 18th magnitude, depending on the passband.« less

Subwavelength InSb-based Slot wavguides for THz transport: concept and practical implementations.

PubMed

Ma, Youqiao; Zhou, Jun; Pištora, Jaromír; Eldlio, Mohamed; Nguyen-Huu, Nghia; Maeda, Hiroshi; Wu, Qiang; Cada, Michael

2016-12-07

Seeking better surface plasmon polariton (SPP) waveguides is of critical importance to construct the frequency-agile terahertz (THz) front-end circuits. We propose and investigate here a new class of semiconductor-based slot plasmonic waveguides for subwavelength THz transport. Optimizations of the key geometrical parameters demonstrate its better guiding properties for simultaneous realization of long propagation lengths (up to several millimeters) and ultra-tight mode confinement (~λ 2 /530) in the THz spectral range. The feasibility of the waveguide for compact THz components is also studied to lay the foundations for its practical implementations. Importantly, the waveguide is compatible with the current complementary metal-oxide-semiconductor (CMOS) fabrication technique. We believe the proposed waveguide configuration could offer a potential for developing a CMOS plasmonic platform and can be designed into various components for future integrated THz circuits (ITCs).

The LBT experience of adaptive secondary mirror operations for routine seeing- and diffraction-limited science operations

NASA Astrophysics Data System (ADS)

Guerra, J. C.; Brusa, G.; Christou, J.; Miller, D.; Ricardi, A.; Xompero, M.; Briguglio, R.; Wagner, M.; Lefebvre, M.; Sosa, R.

2013-09-01

The Large Binocular Telescope (LBT) is unique in that it is currently the only large telescope (2 x 8.4m primary mirrors) with permanently mounted adaptive secondary mirrors (ASMs). These ASMs have been used for regular observing since early 2010 on the right side and since late 2011 on the left side. They are currently regularly used for seeing-limited observing as well as for selective diffraction-limited observing and are required to be fully operational every observing night. By comparison the other telescopes using ASMs, the Multi Mirrot Telescope (MMT) and more recently Magellan, use fixed secondaries of seeing-limited observing and switch in the ASMs for diffraction-limited observing. We will discuss the night-to-night operational requirements for ASMs specifically for seeing-limited but also for diffraction-limited observations based on the LBT experience. These will include preparation procedures for observing (mirror flattening and resting as examples); hardware failure statistics and how to deal with them such as for the actuators; observing protocols for; and current limitations of use due to the ASM technology such as the minimum elevation limit (25 degrees) and the hysteresis of the gravity-vector induced astigmatism. We will also discuss the impact of ASM maintenance and preparation

Scalable Testing Platform for CMOS Read In Integrated Circuits

DTIC Science & Technology

2016-03-31

light - emitting - diode (SLED) current on a monitor out (MOUT) pin. The MOUT pin can produce voltage or current readings, depending on the test case. The...in it means the SPI communication works correctly. Lighting up LEDs: All the RIICs have the corner pixels brought out to output pins. Thus...external LEDs can be connected to pins in order to test the behavior of the pixel drive circuitry. Lighting up LEDs is a great visual representation that

Design, Construction, and Testing of Lightweight X-ray Mirror Modules

NASA Technical Reports Server (NTRS)

McClelland, Ryan S.; Biskach, Michael P.; Chan, Kai-Wing; Espina, Rebecca A.; Hohl, Bruce R.; Matson, Elizabeth A.; Saha, Timo C.; Zhang, William W.

2013-01-01

Lightweight and high resolution optics are needed for future space-based X-ray telescopes to achieve advances in high-energy astrophysics. The Next Generation X-ray Optics (NGXO) team at NASA GSFC is nearing mission readiness for a 10 arc-second Half Power Diameter (HPD) slumped glass mirror technology while laying the groundwork for a future 1-2 arc-second technology based on polished silicon mirrors. Technology Development Modules (TDMs) have been designed, fabricated, integrated with mirrors segments, and extensively tested to demonstrate technology readiness. Tests include X-ray performance, thermal vacuum, acoustic load, and random vibration. The thermal vacuum and acoustic load environments have proven relatively benign, while the random vibration environment has proven challenging due to large input amplification at frequencies above 500 Hz. Epoxy selection, surface preparation, and larger bond area have increased bond strength while vibration isolation has decreased vibration amplification allowing for space launch requirements to be met in the near term. The next generation of TDMs, which demonstrates a lightweight structure supporting more mirror segments, is currently being fabricated. Analysis predicts superior performance characteristics due to the use of E-60 Beryllium-Oxide Metal Matrix Composite material, with only a modest cost increase. These TDMs will be larger, lighter, stiffer, and stronger than the current generation. Preliminary steps are being taken to enable mounting and testing of 1-2 arc-second mirror segments expected to be available in the future. A Vertical X-ray Test Facility (VXTF) will minimize module gravity distortion and allow for less constrained mirror mounts, such as fully kinematic mounts. Permanent kinematic mounting into a modified TDM has been demonstrated to achieve 2 arc-second level distortion free alignment.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

CMOS compatible electrode materials selection in oxide-based memory devices

NASA Astrophysics Data System (ADS)

Zhuo, V. Y.-Q.; Li, M.; Guo, Y.; Wang, W.; Yang, Y.; Jiang, Y.; Robertson, J.

2016-07-01

Electrode materials selection guidelines for oxide-based memory devices are constructed from the combined knowledge of observed device operation characteristics, ab-initio calculations, and nano-material characterization. It is demonstrated that changing the top electrode material from Ge to Cr to Ta in the Ta2O5-based memory devices resulted in a reduction of the operation voltages and current. Energy Dispersed X-ray (EDX) Spectrometer analysis clearly shows that the different top electrode materials scavenge oxygen ions from the Ta2O5 memory layer at various degrees, leading to different oxygen vacancy concentrations within the Ta2O5, thus the observed trends in the device performance. Replacing the Pt bottom electrode material with CMOS compatible materials (Ru and Ir) further reduces the power consumption and can be attributed to the modification of the Schottky barrier height and oxygen vacancy concentration at the electrode/oxide interface. Both trends in the device performance and EDX results are corroborated by the ab-initio calculations which reveal that the electrode material tunes the oxygen vacancy concentration via the oxygen chemical potential and defect formation energy. This experimental-theoretical approach strongly suggests that the proper selection of CMOS compatible electrode materials will create the critical oxygen vacancy concentration to attain low power memory performance.

Backside illuminated CMOS-TDI line scanner for space applications

NASA Astrophysics Data System (ADS)

Cohen, O.; Ben-Ari, N.; Nevo, I.; Shiloah, N.; Zohar, G.; Kahanov, E.; Brumer, M.; Gershon, G.; Ofer, O.

2017-09-01

A new multi-spectral line scanner CMOS image sensor is reported. The backside illuminated (BSI) image sensor was designed for continuous scanning Low Earth Orbit (LEO) space applications including A custom high quality CMOS Active Pixels, Time Delayed Integration (TDI) mechanism that increases the SNR, 2-phase exposure mechanism that increases the dynamic Modulation Transfer Function (MTF), very low power internal Analog to Digital Converters (ADC) with resolution of 12 bit per pixel and on chip controller. The sensor has 4 independent arrays of pixels where each array is arranged in 2600 TDI columns with controllable TDI depth from 8 up to 64 TDI levels. A multispectral optical filter with specific spectral response per array is assembled at the package level. In this paper we briefly describe the sensor design and present some electrical and electro-optical recent measurements of the first prototypes including high Quantum Efficiency (QE), high MTF, wide range selectable Full Well Capacity (FWC), excellent linearity of approximately 1.3% in a signal range of 5-85% and approximately 1.75% in a signal range of 2-95% out of the signal span, readout noise of approximately 95 electrons with 64 TDI levels, negligible dark current and power consumption of less than 1.5W total for 4 bands sensor at all operation conditions .

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

CMOS-TDI detector technology for reconnaissance application

NASA Astrophysics Data System (ADS)

Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

2014-10-01

The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

A wireless narrowband imaging chip for capsule endoscope.

PubMed

Lan-Rong Dung; Yin-Yi Wu

2010-12-01

This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now. The narrowband image acquisition and power dissipation reduction are the main challenges of NBI capsule endoscope. In this paper, we present the first narrowband imaging capsule endoscope that can assist clinical doctors to effectively diagnose early gastrointestinal cancers, profited from our dedicated dual-mode complementary metal-oxide semiconductor (CMOS) sensor. The dedicated dual-mode CMOS sensor can offer white-light and narrowband images. Implementation results show that the proposed 512 × 512 CMOS sensor consumes only 2 mA at a 3-V power supply. The average current of the NBI capsule with an 8-Mb/s RF transmitter is nearly 7 ~ 8 mA that can continuously work for 6 ~ 8 h with two 1.5-V 80-mAh button batteries while the frame rate is 2 fps. Experimental results on backside mucosa of a human tongue and pig's small intestine showed that the wireless NBI capsule endoscope can significantly improve the image quality, compared with a commercial-of-the-shelf capsule endoscope for gastrointestinal tract diagnosis.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

A mathematical model of the inline CMOS matrix sensor for investigation of particles in hydraulic liquids

NASA Astrophysics Data System (ADS)

Kornilin, DV; Kudryavtsev, IA

2016-10-01

One of the most effective ways to diagnose the state of hydraulic system is an investigation of the particles in their liquids. The sizes of such particles range from 2 to 200 gm and their concentration and shape reveal important information about the current state of equipment and the necessity of maintenance. In-line automatic particle counters (APC), which are built into hydraulic system, are widely used for determination of particle size and concentration. These counters are based on a single photodiode and a light emitting diode (LED); however, samples of liquid are needed for analysis using microscope or industrial video camera in order to get information about particle shapes. The act of obtaining the sample leads to contamination by other particles from the air or from the sample tube, meaning that the results are usually corrupted. Using the CMOS or CCD matrix sensor without any lens for inline APC is the solution proposed by authors. In this case the matrix sensors are put into the liquid channel of the hydraulic system and illuminated by LED. This system could be stable in arduous conditions like high pressure and the vibration of the hydraulic system; however, the image or signal from that matrix sensor needs to be processed differently in comparison with the signal from microscope or industrial video camera because of relatively short distance between LED and sensor. This paper introduces mathematical model of a sensor with CMOS and LED, which can be built into hydraulic system. It is also provided a computational algorithm and results, which can be useful for calculation of particle sizes and shapes using the signal from the CMOS matrix sensor.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Domengie, F., E-mail: florian.domengie@st.com; Morin, P.; Bauza, D.

We propose a model for dark current induced by metallic contamination in a CMOS image sensor. Based on Shockley-Read-Hall kinetics, the expression of dark current proposed accounts for the electric field enhanced emission factor due to the Poole-Frenkel barrier lowering and phonon-assisted tunneling mechanisms. To that aim, we considered the distribution of the electric field magnitude and metal atoms in the depth of the pixel. Poisson statistics were used to estimate the random distribution of metal atoms in each pixel for a given contamination dose. Then, we performed a Monte-Carlo-based simulation for each pixel to set the number of metalmore » atoms the pixel contained and the enhancement factor each atom underwent, and obtained a histogram of the number of pixels versus dark current for the full sensor. Excellent agreement with the dark current histogram measured on an ion-implanted gold-contaminated imager has been achieved, in particular, for the description of the distribution tails due to the pixel regions in which the contaminant atoms undergo a large electric field. The agreement remains very good when increasing the temperature by 15 °C. We demonstrated that the amplification of the dark current generated for the typical electric fields encountered in the CMOS image sensors, which depends on the nature of the metal contaminant, may become very large at high electric field. The electron and hole emissions and the resulting enhancement factor are described as a function of the trap characteristics, electric field, and temperature.« less

Impact of time-dependent annealing on TiO2 films for CMOS application

NASA Astrophysics Data System (ADS)

Gyanan, Mondal, Sandip; Kumar, Arvind

2017-05-01

Post-deposition annealing (PDA) is the inherent part of sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. The annealing removes the oxygen vacancies and improves the structural order of dielectric films. The process also reduces the interface related defects and improves the interfacial properties. In this work, we have integrated the sol-gel spin-coating deposited high-κ TiO2 films in MOS. The films are fired at 400°C for the duration of 20, 40, 60 and 80 min. The thicknesses of the films were found to be of ˜ 30 nm using ellipsometry. The (Al/TiO2/p-Si) devices were examined with current-voltage (I-V) and capacitance-voltage (C-V) at room temperature to understand the influence of firing time. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. The accumulation capacitance (Cox), dielectric constant (κ) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25nm, respectively with a low leakage current density (1.09 × 10-6 A/cm2) fired for 80 min at +1 V.

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

PubMed

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-07-22

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

Current Technology Development Efforts on the International X-Ray Observatory

NASA Technical Reports Server (NTRS)

Robinson, David

2011-01-01

The International X-ray Observatory (IXO) is a collaboration between NASA, ESA, and JAXA which is under study for launch in 2021. IXO will be a large 6600 kilogram Great Observatory-class mission which will build upon the legacies of the Chandra and XMM-Newton X-ray observatories. There is an extensive ongoing effort to raise the technology readiness level of the X-ray mirror from TRL 3 to TRL 6 in the next decade. Improvements have recently been made in the area of positioning and bonding mirrors on the nanometer scale and developing metals and composites with a matching coefficient of thermal expansion to the glass X-ray mirrors. On the mission systems side, the NASA reference design has been through a preliminary coupled loads analysis and a STOP analysis of the flight mirror assembly has been initiated. An impact study was performed comparing launching IXO on an Ariane 5 or a U.S. EELV. This paper will provide a snapshot of NASA's current observatory configuration and summarize the progress of these various technology and design efforts.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... credit union may invest in and hold exchangeable collateralized mortgage obligations (exchangeable CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio of the market...

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Cargo Movement Operations System (CMOS). Final Software Requirements Specification, (Applications CSCI), Increment II

DTIC Science & Technology

1991-01-29

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL Nt3MBFR: SRS1-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...floppy diskette interface with CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES ( 3 NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Tests of commercial colour CMOS cameras for astronomical applications

NASA Astrophysics Data System (ADS)

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

Alignment and Integration Techniques for Mirror Segment Pairs on the Constellation X Telescope

NASA Technical Reports Server (NTRS)

Hadjimichael, Theo; Lehan, John; Olsen, Larry; Owens, Scott; Saha, Timo; Wallace, Tom; Zhang, Will

2007-01-01

We present the concepts behind current alignment and integration techniques for testing a Constellation-X primary-secondary mirror segment pair in an x-ray beam line test. We examine the effects of a passive mount on thin glass x-ray mirror segments, and the issues of mount shape and environment on alignment. We also investigate how bonding and transfer to a permanent housing affects the quality of the final image, comparing predicted results to a full x-ray test on a primary secondary pair.

Mirror Measurement Device

NASA Technical Reports Server (NTRS)

1992-01-01

A Small Business Innovation Research (SBIR) contract led to a commercially available instrument used to measure the shape profile of mirror surfaces in scientific instruments. Bauer Associates, Inc.'s Bauer Model 200 Profilometer is based upon a different measurement concept. The local curvature of the mirror's surface is measured at many points, and the collection of data is computer processed to yield the desired shape profile. (Earlier profilometers are based on the principle of interferometry.) The system is accurate and immune to problems like vibration and turbulence. Two profilometers are currently marketed, and a third will soon be commercialized.

Seal Materials Compatible with the Electroplating Solvent Used in Constellation-X Mirrors

NASA Technical Reports Server (NTRS)

Pei, Xiong-Skiba

1999-01-01

The existing gasket seals used in electroplating of the Constellation-X mirrors are difficult to assemble, and the current seal material is hydrophobic and too thick. The combination of the above problems result in: 1) non-uniform plating; 2) defect sites such as pits on the mirror edges; 3) "bear claws" on the edges of the mandrels and mirrors causing difficulties in shell-mirror separations; and 4) leakage of the plating solution past the seals into the mandrel causing chemical etching of the mandrel interior. This paper reports the results of this summer study in searching for alternate seal materials chemically compatible with the electroplating solvent. Fifteen common elastomeric rubber seal materials made-by Parker Seals were investigated including butyl, ethylene propylene, fluorosilicone, nitrile, Viton fluorocarbon, and silicone. Test results showed that Viton fluorocarbon compounds as a group were superior to the other tested compounds for chemical compatibility with the plating bath.

Cosmological signals of a mirror twin Higgs

DOE PAGES

Craig, Nathaniel; Koren, Seth; Trott, Timothy

2017-05-08

We investigate the cosmology of the minimal model of neutral naturalness, the mirror Twin Higgs. The softly-broken mirror symmetry relating the Standard Model to its twin counterpart leads to significant dark radiation in tension with BBN and CMB observations. We quantify this tension and illustrate how it can be mitigated in several simple scenarios that alter the relative energy densities of the two sectors while respecting the softly-broken mirror symmetry. In particular, we consider both the out-of-equilibrium decay of a new scalar as well as reheating in a toy model of twinned inflation, Twinflation. In both cases the dilution ofmore » energy density in the twin sector does not merely reconcile the existence of a mirror Twin Higgs with cosmological constraints, but predicts contributions to cosmological observables that may be probed in current and future CMB experiments. This raises the prospect of discovering evidence of neutral naturalness through cosmology rather than colliders.« less

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Vision Sensors and Cameras

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Silicon charge-coupled-device (CCD) imagers have been and are a specialty market ruled by a few companies for decades. Based on CMOS technologies, active-pixel sensors (APS) began to appear in 1990 at the 1 μm technology node. These pixels allow random access, global shutters, and they are compatible with focal-plane imaging systems combining sensing and first-level image processing. The progress towards smaller features and towards ultra-low leakage currents has provided reduced dark currents and μm-size pixels. All chips offer Mega-pixel resolution, and many have very high sensitivities equivalent to ASA 12.800. As a result, HDTV video cameras will become a commodity. Because charge-integration sensors suffer from a limited dynamic range, significant processing effort is spent on multiple exposure and piece-wise analog-digital conversion to reach ranges >10,000:1. The fundamental alternative is log-converting pixels with an eye-like response. This offers a range of almost a million to 1, constant contrast sensitivity and constant colors, important features in professional, technical and medical applications. 3D retino-morphic stacking of sensing and processing on top of each other is being revisited with sub-100 nm CMOS circuits and with TSV technology. With sensor outputs directly on top of neurons, neural focal-plane processing will regain momentum, and new levels of intelligent vision will be achieved. The industry push towards thinned wafers and TSV enables backside-illuminated and other pixels with a 100% fill-factor. 3D vision, which relies on stereo or on time-of-flight, high-speed circuitry, will also benefit from scaled-down CMOS technologies both because of their size as well as their higher speed.

Ultra-miniature wireless temperature sensor for thermal medicine applications.

PubMed

Khairi, Ahmad; Hung, Shih-Chang; Paramesh, Jeyanandh; Fedder, Gary; Rabin, Yoed

2011-01-01

This study presents a prototype design of an ultra-miniature, wireless, battery-less, and implantable temperature-sensor, with applications to thermal medicine such as cryosurgery, hyperthermia, and thermal ablation. The design aims at a sensory device smaller than 1.5 mm in diameter and 3 mm in length, to enable minimally invasive deployment through a hypodermic needle. While the new device may be used for local temperature monitoring, simultaneous data collection from an array of such sensors can be used to reconstruct the 3D temperature field in the treated area, offering a unique capability in thermal medicine. The new sensory device consists of three major subsystems: a temperature-sensing core, a wireless data-communication unit, and a wireless power reception and management unit. Power is delivered wirelessly to the implant from an external source using an inductive link. To meet size requirements while enhancing reliability and minimizing cost, the implant is fully integrated in a regular foundry CMOS technology (0.15 μm in the current study), including the implant-side inductor of the power link. A temperature-sensing core that consists of a proportional-to-absolute-temperature (PTAT) circuit has been designed and characterized. It employs a microwatt chopper stabilized op-amp and dynamic element-matched current sources to achieve high absolute accuracy. A second order sigma-delta (Σ-Δ) analog-to-digital converter (ADC) is designed to convert the temperature reading to a digital code, which is transmitted by backscatter through the same antenna used for receiving power. A high-efficiency multi-stage differential CMOS rectifier has been designed to provide a DC supply to the sensing and communication subsystems. This paper focuses on the development of the all-CMOS temperature sensing core circuitry part of the device, and briefly reviews the wireless power delivery and communication subsystems.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.