Solid State Research.

DTIC Science & Technology

1984-08-15

for the Same Signal 30 3 -1 Schematic Diagrams of Two Configurations with SOI/ CMOS and Bipolar Devices Fabricated on the Same Si Wafer. The Bipolar...Waveform of 39-Stage SOI/ CMOS Ring Oscillator for 5-V Supply Voltage. The Propagation Delay per Stage is 藨 ps 33 3 -4 Common-Emitter I-V...multiple beam splitters and delay lines. 3 . MATERIALS RESEARCH Two merged CMOS ! bipolar technologies utilizing S01 films have been developed for

Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

NASA Astrophysics Data System (ADS)

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo; Steyaert, Michiel; Leroux, Paul

2018-04-01

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

NASA Astrophysics Data System (ADS)

Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

2017-06-01

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Period locking due to delayed feedback in a laser with saturable absorber.

PubMed

Carr, T W

2003-08-01

We consider laser with saturable absorber operating in the pulsating regime that is subject to delayed feedback. Alone, both the saturable absorber and delayed feedback cause the clockwise output to become unstable to periodic output via Hopf bifurcations. The delay feedback causes the laser pulse period to lock to an integer fraction of the feedback time. We derive a map from the original model to describe the periodic pulsations of the laser. Equations for the period of the laser predict the occurrence of the different locking states as well as the value of the pump when there is a switch between the locked states.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Low-noise sub-harmonic injection locked multiloop ring oscillator

NASA Astrophysics Data System (ADS)

Weilin, Xu; Di, Wu; Xueming, Wei; Baolin, Wei; Jihai, Duan; Fadi, Gui

2016-09-01

A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μm 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology. Project supported by the National Natural Science Foundation of China (No. 61264001), the Guangxi Natural Science Foundation (Nos. 2013GXNSFAA019333, 2015GXNSFAA139301, 2014GXNSFAA118386), the Graduate Education Innovation Program of GUET (No. GDYCSZ201457), the Project of Guangxi Education Department (No. LD14066B) and the High-Level-Innovation Team and Outstanding Scholar Project of Guangxi Higher Education Institutes.

A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

NASA Technical Reports Server (NTRS)

Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

2013-01-01

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

NASA Astrophysics Data System (ADS)

Yang, Jiaqi; Li, Ting; Yu, Mingyuan; Zhang, Shuangshuang; Lin, Fujiang; He, Lin

2017-08-01

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203 μW. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

A Coherent VLSI Design Environment.

DTIC Science & Technology

1986-03-31

Schema were a CMOS sorter and a TTL PC board for gathering statistics from a Multibus. Neither design was completed using Schema, but at least in the...technique for automatically adjusting signal delays in an MOS system has been developed. The Dynamic Delay Adjustment (DDA) technique provides...34Synchronization Reliability in CMOS Technology," IEEE J. of Solid - State Circuits, Vol. SC-20, No. 4, pp. 880-883, 1985. * [8] J. Hohl, W. Larsen and L. Schooley

A low jitter PLL clock used for phase change memory

NASA Astrophysics Data System (ADS)

Xiao, Hong; Houpeng, Chen; Zhitang, Song; Daolin, Cai; Xi, Li

2013-02-01

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

A 7 ke-SD-FWC 1.2 e-RMS Temporal Random Noise 128×256 Time-Resolved CMOS Image Sensor With Two In-Pixel SDs for Biomedical Applications.

PubMed

Seo, Min-Woong; Kawahito, Shoji

2017-12-01

A large full well capacity (FWC) for wide signal detection range and low temporal random noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two in-pixel storage diodes (SDs) has been developed and presented in this paper. For fast charge transfer from photodiode to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal random noise of 1.2e-rms at 20 fps with true correlated double sampling operation and fast intrinsic response less than 500 ps at 635 nm. The proposed imager has an effective pixel array of and a pixel size of . The sensor chip is fabricated by Dongbu HiTek 1P4M 0.11 CIS process.

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Robustness of delayed multistable systems with application to droop-controlled inverter-based microgrids

NASA Astrophysics Data System (ADS)

Efimov, Denis; Schiffer, Johannes; Ortega, Romeo

2016-05-01

Motivated by the problem of phase-locking in droop-controlled inverter-based microgrids with delays, the recently developed theory of input-to-state stability (ISS) for multistable systems is extended to the case of multistable systems with delayed dynamics. Sufficient conditions for ISS of delayed systems are presented using Lyapunov-Razumikhin functions. It is shown that ISS multistable systems are robust with respect to delays in a feedback. The derived theory is applied to two examples. First, the ISS property is established for the model of a nonlinear pendulum and delay-dependent robustness conditions are derived. Second, it is shown that, under certain assumptions, the problem of phase-locking analysis in droop-controlled inverter-based microgrids with delays can be reduced to the stability investigation of the nonlinear pendulum. For this case, corresponding delay-dependent conditions for asymptotic phase-locking are given.

Radiation dependence of inverter propagation delay from timing sampler measurements

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Lin, Y.-S.

1989-01-01

A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.

Material Targets for Scaling All-Spin Logic

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Demonstration of a stable ultrafast laser based on a nonlinear microcavity

PubMed Central

Peccianti, M.; Pasquazi, A.; Park, Y.; Little, B.E.; Chu, S.T.; Moss, D.J.; Morandotti, R.

2012-01-01

Ultrashort pulsed lasers, operating through the phenomenon of mode-locking, have had a significant role in many facets of our society for 50 years, for example, in the way we exchange information, measure and diagnose diseases, process materials, and in many other applications. Recently, high-quality resonators have been exploited to demonstrate optical combs. The ability to phase-lock their modes would allow mode-locked lasers to benefit from their high optical spectral quality, helping to realize novel sources such as precision optical clocks for applications in metrology, telecommunication, microchip-computing, and many other areas. Here we demonstrate the first mode-locked laser based on a microcavity resonator. It operates via a new mode-locking method, which we term filter-driven four-wave mixing, and is based on a CMOS-compatible high quality factor microring resonator. It achieves stable self-starting oscillation with negligible amplitude noise at ultrahigh repetition rates, and spectral linewidths well below 130 kHz. PMID:22473009

Experimental verification of arm-locking for LISA using electronic phase delay [rapid communication

NASA Astrophysics Data System (ADS)

Thorpe, J. I.; Mueller, G.

2005-07-01

We present results of an electronic model of arm-locking, a proposed technique for reducing the laser phase noise in the laser interferometer space antenna (LISA). The model is based on a delay of 500 ms, achieved using the electronic phase delay (EPD) method. The observed behavior is consistent with predictions.

A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector

NASA Astrophysics Data System (ADS)

Parkalian, N.; Robens, M.; Grewing, C.; Christ, V.; Kruth, A.; Liebau, D.; Muralidharan, P.; Nielinger, D.; Roth, C.; Yegin, U.; Zambanini, A.; van Waasen, S.

2018-02-01

This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1 V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5 mW power at 1.8 V supply for the VCO and 1 V supply for the other parts.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

High speed CMOS/SOS standard cell notebook

NASA Technical Reports Server (NTRS)

1978-01-01

The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

NASA Astrophysics Data System (ADS)

Utagawa, Akira; Asai, Tetsuya; Hirose, Tetsuya; Amemiya, Yoshihito

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1], [2]. We regard neural oscillators as independent clock sources on LSIs; i. e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (<1GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

Optical injection phase-lock loops

NASA Astrophysics Data System (ADS)

Bordonalli, Aldario Chrestani

Locking techniques have been widely applied for frequency synchronisation of semiconductor lasers used in coherent communication and microwave signal generation systems. Two main locking techniques, the optical phase-lock loop (OPLL) and optical injection locking (OIL) are analysed in this thesis. The principal limitations on OPLL performance result from the loop propagation delay, which makes difficult the implementation of high gain and wide bandwidth loops, leading to poor phase noise suppression performance and requiring the linewidths of the semiconductor laser sources to be less than a few megahertz for practical values of loop delay. The OIL phase noise suppression is controlled by the injected power. The principal limitations of the OIL implementation are the finite phase error under locked conditions and the narrow stable locking range the system provides at injected power levels required to reduce the phase noise output of semiconductor lasers significantly. This thesis demonstrates theoretically and experimentally that it is possible to overcome the limitations of OPLL and OIL systems by combining them, to form an optical injection phase-lock loop (OIPLL). The modelling of an OIPLL system is presented and compared with the equivalent OPLL and OIL results. Optical and electrical design of an homodyne OIPLL is detailed. Experimental results are given which verify the theoretical prediction that the OIPLL would keep the phase noise suppression as high as that of the OIL system over a much wider stable locking range, even with wide linewidth lasers and long loop delays. The experimental results for lasers with summed linewidth of 36 MHz and a loop delay of 15 ns showed measured phase error variances as low as 0.006 rad2 (500 MHz bandwidth) for locking bandwidths greater than 26 GHz, compared with the equivalent OPLL phase error variance of around 1 rad2 (500 MHz bandwidth) and the equivalent OIL locking bandwidth of less than 1.2 GHz.

Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

NASA Astrophysics Data System (ADS)

Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

2017-02-01

The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

A time-resolved image sensor for tubeless streak cameras

NASA Astrophysics Data System (ADS)

Yasutomi, Keita; Han, SangMan; Seo, Min-Woong; Takasawa, Taishi; Kagawa, Keiichiro; Kawahito, Shoji

2014-03-01

This paper presents a time-resolved CMOS image sensor with draining-only modulation (DOM) pixels for tube-less streak cameras. Although the conventional streak camera has high time resolution, the device requires high voltage and bulky system due to the structure with a vacuum tube. The proposed time-resolved imager with a simple optics realize a streak camera without any vacuum tubes. The proposed image sensor has DOM pixels, a delay-based pulse generator, and a readout circuitry. The delay-based pulse generator in combination with an in-pixel logic allows us to create and to provide a short gating clock to the pixel array. A prototype time-resolved CMOS image sensor with the proposed pixel is designed and implemented using 0.11um CMOS image sensor technology. The image array has 30(Vertical) x 128(Memory length) pixels with the pixel pitch of 22.4um. .

Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

PubMed

Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

2017-09-04

We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

Defect-sensitivity analysis of an SEU immune CMOS logic family

NASA Technical Reports Server (NTRS)

Ingermann, Erik H.; Frenzel, James F.

1992-01-01

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

Multifrequency zero-jitter delay-locked loop

NASA Astrophysics Data System (ADS)

Efendovich, Avner; Afek, Yachin; Sella, Coby; Bikowsky, Zeev

1994-01-01

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions.

Toward a reduced-wire readout system for ultrasound imaging.

PubMed

Lim, Jaemyung; Arkan, Evren F; Degertekin, F Levent; Ghovanloo, Maysam

2014-01-01

We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply.

Toward a Reduced-Wire Readout System for Ultrasound Imaging

PubMed Central

Lim, Jaemyung; Arkan, Evren F.; Degertekin, F. Levent; Ghovanloo, Maysam

2015-01-01

We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply. PMID:25571135

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Nanosecond monolithic CMOS readout cell

DOEpatents

Souchkov, Vitali V.

2004-08-24

A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

An improved fast acquisition phase frequency detector for high speed phase-locked loops

NASA Astrophysics Data System (ADS)

Zhang, Lei; Wang, Zongmin; Zhang, Tieliang; Peng, Xinmang

2018-04-01

Phase-locked loops (PLL) have been widely applied in many high-speed designs, such as microprocessors or communication systems. In this paper, an improved fast acquisition phase frequency detector for high speed phase-locked loops is proposed. An improved structure based on dynamic latch is used to eliminate the non-ideal effect such as dead zone and blind zone. And frequency dividers are utilized to vastly extend the phase difference detection range and enhance the operation frequency of the PLL. Proposed PFD has been implemented in 65nm CMOS technology, which occupies an area of 0.0016mm2 and consumes 1.5mW only. Simulation results demonstrate that maximum operation frequency can be up to 5GHz. In addition, the acquisition time of PLL using proposed PFD is 1.0us which is 2.6 times faster than that of the PLL using latch-based PFD without divider.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

Theoretical investigations of quantum correlations in NMR multiple-pulse spin-locking experiments

NASA Astrophysics Data System (ADS)

Gerasev, S. A.; Fedorova, A. V.; Fel'dman, E. B.; Kuznetsova, E. I.

2018-04-01

Quantum correlations are investigated theoretically in a two-spin system with the dipole-dipole interactions in the NMR multiple-pulse spin-locking experiments. We consider two schemes of the multiple-pulse spin-locking. The first scheme consists of π /2-pulses only and the delays between the pulses can differ. The second scheme contains φ-pulses (0<φ <π ) and has equal delays between them. We calculate entanglement for both schemes for an initial separable state. We show that entanglement is absent for the first scheme at equal delays between π /2-pulses at arbitrary temperatures. Entanglement emerges after several periods of the pulse sequence in the second scheme at φ =π /4 at milliKelvin temperatures. The necessary number of the periods increases with increasing temperature. We demonstrate the dependence of entanglement on the number of the periods of the multiple-pulse sequence. Quantum discord is obtained for the first scheme of the multiple-pulse spin-locking experiment at different temperatures.

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

2.4-3.2 GHz robust self-injecting injection-locked phase-locked loop

NASA Astrophysics Data System (ADS)

Yang, Jincheng; Zhang, Zhao; Qi, Nan; Liu, Liyuan; Liu, Jian; Wu, Nanjian

2018-04-01

In this paper, we propose a robust self-injecting injection-locked phase-locked loop (SI-ILPLL). It adopts a phase alignment loop (PAL) based on a subsampling phase frequency detector to align the phase between the injected pulse and the voltage-controlled oscillator (VCO) output. With the proposed phase frequency detector, the PAL performs phase alignment and the pulse generator can self-inject pulses into the VCO for injection locking. The subsampling phase detection and self-injection locking techniques can suppress the phase noise of the SI-ILPLL. The SI-ILPLL shows excellent robustness to environmental interference. The SI-ILPLL is implemented in 65 nm CMOS technology. It occupies an active area of 0.7 mm2. The measured root-mean-square (RMS) jitters at 3.2 GHz output without and with injection locking are 216 and 131 fs, respectively. When the supply voltage varies from 1.17 to 1.23 V and the temperature varies from 0 to 80 °C, the maximum jitter variation of all the output frequencies is less than 50 fs. The measured results demonstrate that even when a large interference appears at the supply voltage and unlocks the SI-ILPLL, the SI-ILPLL can self-recover its injection-locked state rapidly after the disturbance disappears, whereas the conventional ILPLL cannot self-recover its locked state after losing it. The power consumption of the SI-ILPLL is 7.4 mW under a 1.2 V supply voltage. The SI-ILPLL achieves a figure of merit (FOM) of -249 dB.

DOE Office of Scientific and Technical Information (OSTI.GOV)

McKenzie, Kirk; Spero, Robert E.; Shaddock, Daniel A.

For the Laser Interferometer Space Antenna (LISA) to reach its design sensitivity, the coupling of the free-running laser frequency noise to the signal readout must be reduced by more than 14 orders of magnitude. One technique employed to reduce the laser frequency noise will be arm locking, where the laser frequency is locked to the LISA arm length. In this paper we detail an implementation of arm locking. We investigate orbital effects (changing arm lengths and Doppler frequencies), the impact of errors in the Doppler knowledge that can cause pulling of the laser frequency, and the noise limit of armmore » locking. Laser frequency pulling is examined in two regimes: at lock acquisition and in steady state. The noise performance of arm locking is calculated with the inclusion of the dominant expected noise sources: ultrastable oscillator (clock) noise, spacecraft motion, and shot noise. We find that clock noise and spacecraft motion limit the performance of dual arm locking in the LISA science band. Studying these issues reveals that although dual arm locking [A. Sutton and D. A. Shaddock, Phys. Rev. D 78, 082001 (2008)] has advantages over single (or common) arm locking in terms of allowing high gain, it has disadvantages in both laser frequency pulling and noise performance. We address this by proposing a modification to the dual arm-locking sensor, a hybrid of common and dual arm-locking sensors. This modified dual arm-locking sensor has the laser frequency pulling characteristics and low-frequency noise coupling of common arm locking, but retains the control system advantages of dual arm locking. We present a detailed design of an arm-locking controller and perform an analysis of the expected performance when used with and without laser prestabilization. We observe that the sensor phase changes beneficially near unity-gain frequencies of the arm-locking controller, allowing a factor of 10 more gain than previously believed, without degrading stability. With a time-delay error of 3 ns (equivalent of 1 m interspacecraft ranging error), time-delay interferometry (TDI) is capable of suppressing 300 Hz/{radical}(Hz) of laser frequency noise to the required level. We show that if no interspacecraft laser links fail, arm locking alone surpasses this noise performance for the entire mission. If one interspacecraft laser link fails, arm locking alone will achieve this performance for all but approximately 1 h per year, when the arm length mismatch of the two remaining arms passes through zero. Therefore, the LISA sensitivity can be realized with arm locking and time-delay interferometry only, without any form of prestabilization.« less

High-density CMOS Microelectrode Array System for Impedance Spectroscopy and Imaging of Biological Cells.

PubMed

Vijay, Viswam; Raziyeh, Bounik; Amir, Shadmani; Jelena, Dragas; Alicia, Boos Julia; Axel, Birchler; Jan, Müller; Yihui, Chen; Andreas, Hierlemann

2017-01-26

A monolithic measurement platform was implemented to enable label-free in-vitro electrical impedance spectroscopy measurements of cells on multi-functional CMOS microelectrode array. The array includes 59,760 platinum microelectrodes, densely packed within a 4.5 mm × 2.5 mm sensing region at a pitch of 13.5 μm. The 32 on-chip lock-in amplifiers can be used to measure the impedance of any arbitrarily chosen electrodes on the array by applying a sinusoidal voltage, generated by an on-chip waveform generator with a frequency range from 1 Hz to 1 MHz, and measuring the respective current. Proof-of-concept measurements of impedance sensing and imaging are shown in this paper. Correlations between cell detection through optical microscopy and electrochemical impedance scanning were established.

A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.

PubMed

Wang, Yi-Xiao; Chen, Wei-Ming; Wu, Chung-Yu

2014-01-01

This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Designing Estimator/Predictor Digital Phase-Locked Loops

NASA Technical Reports Server (NTRS)

Statman, J. I.; Hurd, W. J.

1988-01-01

Signal delays in equipment compensated automatically. New approach to design of digital phase-locked loop (DPLL) incorporates concepts from estimation theory and involves decomposition of closed-loop transfer function into estimator and predictor. Estimator provides recursive estimates of phase, frequency, and higher order derivatives of phase with respect to time, while predictor compensates for delay, called "transport lag," caused by PLL equipment and by DPLL computations.

Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

NASA Astrophysics Data System (ADS)

Nasir, Qassim

2018-01-01

This article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low.

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

NASA Astrophysics Data System (ADS)

Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

2011-08-01

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

The Gigatracker: An ultra-fast and low-mass silicon pixel detector for the NA62 experiment

NASA Astrophysics Data System (ADS)

Fiorini, M.; Carassiti, V.; Ceccucci, A.; Cortina, E.; Cotta Ramusino, A.; Dellacasa, G.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Mapelli, A.; Marchetto, F.; Martin, E.; Martoiu, S.; Mazza, G.; Morel, M.; Noy, M.; Nuessle, G.; Petrucci, F.; Riedler, P.; Aglieri Rinella, G.; Rivetti, A.; Tiuraniemi, S.

2011-02-01

The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron beam with a time resolution of 150 ps (rms). The beam spectrometer of the experiment is composed of three Gigatracker stations installed in vacuum in order to precisely measure momentum, time and direction of every traversing particle. Precise tracking demands a very low mass of the detector assembly ( <0.5% X0 per station) in order to limit multiple scattering and beam hadronic interactions. The high rate and especially the high timing precision requirements are very demanding: two R&D options are ongoing and the corresponding prototype read-out chips have been recently designed and produced in 0.13 μm CMOS technology. One solution makes use of a constant fraction discriminator and on-pixel analogue-based time-to-digital-converter (TDC); the other comprises a delay-locked loop based TDC placed at the end of each pixel column and a time-over-threshold discriminator with time-walk correction technique. The current status of the R&D program is overviewed and results from the prototype read-out chips test are presented.

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

An Integrated Low-Power Lock-In Amplifier and Its Application to Gas Detection

PubMed Central

Maya-Hernández, Paulina M.; Álvarez-Simón, Luis C.; Sanz-Pascual, María Teresa; Calvo-López, Belén

2014-01-01

This paper presents a new micropower analog lock-in amplifier (LIA) suitable for battery-operated applications thanks to its reduced size and power consumption as well as its operation with single-supply voltage. The proposed LIA was designed in a 0.18 μm CMOS process with a single supply voltage of 1.8 V. Experimental results show a variable DC gain ranging from 24.7 to 42 dB, power consumption of 417 μW and integration area of 0.013 mm2. The LIA performance was demonstrated by measuring carbon monoxide concentrations as low as 1 ppm in dry N2. The experimental results show that the response to CO of the sensing system can be considerably improved by means of the proposed LIA. PMID:25166501

Willing to Wait: Elevated Reward-Processing EEG Activity Associated with a Greater Preference for Larger-But-Delayed Rewards

PubMed Central

Pornpattananangkul, Narun; Nusslock, Robin

2016-01-01

While almost everyone discounts the value of future rewards over immediate rewards, people differ in their so-called delay-discounting. One of the several factors that may explain individual differences in delay-discounting is reward-processing. To study individual-differences in reward-processing, however, one needs to consider the heterogeneity of neural-activity at each reward-processing stage. Here using EEG, we separated reward-related neural activity into distinct reward-anticipation and reward-outcome stages using time-frequency characteristics. Thirty-seven individuals completed a behavioral delay-discounting task. Reward-processing EEG activity was assessed using a separate reward-learning task, called a reward time-estimation task. During this task, participants were instructed to estimate time duration and were provided performance feedback on a trial-by-trial basis. Participants received monetary-reward for accurate-performance on Reward trials, but not on No-Reward trials. Reward trials, relative to No-Reward trials, enhanced EEG activity during both reward-anticipation stage (including, cued-locked delta power during cue-evaluation and pre-feedback alpha suppression during feedback-anticipation) and at the reward-outcome stage (including, feedback-locked delta, theta and beta power). Moreover, all of these EEG indices correlated with behavioral performance in the time-estimation task, suggesting their essential roles in learning and adjusting performance to maximize winnings in a reward-learning situation. Importantly, enhanced EEG power during Reward trials for 1) pre-feedback alpha suppression, 2) feedback-locked theta and 3) feedback-locked beta was associated with a greater preference for larger-but-delayed rewards. Results highlight the association between a stronger preference toward larger-but-delayed rewards and enhanced reward-processing. Moreover, our reward-processing EEG indices detail the specific stages of reward-processing where these associations occur. PMID:27477630

Wavelength-stepped, actively mode-locked fiber laser based on wavelength-division-multiplexed optical delay lines

NASA Astrophysics Data System (ADS)

Lee, Eunjoo; Kim, Byoung Yoon

2017-12-01

We propose a new scheme for an actively mode-locked wavelength-swept fiber laser that produces a train of discretely wavelength-stepped pulses from a short fiber cavity. Pulses with different wavelengths are split and combined by standard wavelength division multiplexers with fiber delay lines. As a proof of concept, we demonstrate a laser using an erbium doped fiber amplifier and commercially available wavelength-division multiplexers with wavelength spacing of 0.8 nm. The results show simultaneous mode-locking at three different wavelengths. Laser output parameters in time domain, optical and radio frequency spectral domain, and the noise characteristics are presented. Suggestions for the improved design are discussed.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering

PubMed Central

Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro

2017-01-01

Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system. PMID:29120358

Single-chip fully integrated direct-modulation CMOS RF transmitters for short-range wireless applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed; Deen, M Jamal

2013-08-02

Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of -122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of -120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering.

PubMed

Mars, Kamel; Lioe, De Xing; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

2017-11-09

Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system.

Measuring a Fiber-Optic Delay Line Using a Mode-Locked Laser

NASA Technical Reports Server (NTRS)

Tu, Meirong; McKee, Michael R.; Pak, Kyung S.; Yu, Nan

2010-01-01

The figure schematically depicts a laboratory setup for determining the optical length of a fiber-optic delay line at a precision greater than that obtainable by use of optical time-domain reflectometry or of mechanical measurement of length during the delay-line-winding process. In this setup, the delay line becomes part of the resonant optical cavity that governs the frequency of oscillation of a mode-locked laser. The length can then be determined from frequency-domain measurements, as described below. The laboratory setup is basically an all-fiber ring laser in which the delay line constitutes part of the ring. Another part of the ring - the laser gain medium - is an erbium-doped fiber amplifier pumped by a diode laser at a wavelength of 980 nm. The loop also includes an optical isolator, two polarization controllers, and a polarizing beam splitter. The optical isolator enforces unidirectional lasing. The polarization beam splitter allows light in only one polarization mode to pass through the ring; light in the orthogonal polarization mode is rejected from the ring and utilized as a diagnostic output, which is fed to an optical spectrum analyzer and a photodetector. The photodetector output is fed to a radio-frequency spectrum analyzer and an oscilloscope. The fiber ring laser can generate continuous-wave radiation in non-mode-locked operation or ultrashort optical pulses in mode-locked operation. The mode-locked operation exhibited by this ring is said to be passive in the sense that no electro-optical modulator or other active optical component is used to achieve it. Passive mode locking is achieved by exploiting optical nonlinearity of passive components in such a manner as to obtain ultra-short optical pulses. In this setup, the particular nonlinear optical property exploited to achieve passive mode locking is nonlinear polarization rotation. This or any ring laser can support oscillation in multiple modes as long as sufficient gain is present to overcome losses in the ring. When mode locking is achieved, oscillation occurs in all the modes having the same phase and same polarization. The frequency interval between modes, often denoted the free spectral range (FSR), is given by c/nL, where c is the speed of light in vacuum, n is the effective index of refraction of the fiber, and L is the total length of optical path around the ring. Therefore, the length of the fiber-optic delay line, as part of the length around the ring, can be calculated from the FSRs measured with and without the delay line incorporated into the ring. For this purpose, the FSR measurements are made by use of the optical and radio-frequency spectrum analyzers. In experimentation on a 10-km-long fiber-optic delay line, it was found that this setup made it possible to measure the length to within a fractional error of about 3 10(exp -6), corresponding to a length error of 3 cm. In contrast, measurements by optical time-domain reflectometry and mechanical measurement were found to be much less precise: For optical time-domain reflectometry, the fractional error was found no less than 10(exp -4) (corresponding to a length error of 1 m) and for mechanical measurement, the fractional error was found to be about 10(exp -2) (corresponding to a length error of 100 m).

Willing to wait: Elevated reward-processing EEG activity associated with a greater preference for larger-but-delayed rewards.

PubMed

Pornpattananangkul, Narun; Nusslock, Robin

2016-10-01

While almost everyone discounts the value of future rewards over immediate rewards, people differ in their so-called delay-discounting. One of the several factors that may explain individual differences in delay-discounting is reward-processing. To study individual-differences in reward-processing, however, one needs to consider the heterogeneity of neural-activity at each reward-processing stage. Here using EEG, we separated reward-related neural activity into distinct reward-anticipation and reward-outcome stages using time-frequency characteristics. Thirty-seven individuals first completed a behavioral delay-discounting task. Then reward-processing EEG activity was assessed using a separate reward-learning task, called a reward time-estimation task. During this EEG task, participants were instructed to estimate time duration and were provided performance feedback on a trial-by-trial basis. Participants received monetary-reward for accurate-performance on Reward trials, but not on No-Reward trials. Reward trials, relative to No-Reward trials, enhanced EEG activity during both reward-anticipation (including, cued-locked delta power during cue-evaluation and pre-feedback alpha suppression during feedback-anticipation) and reward-outcome (including, feedback-locked delta, theta and beta power) stages. Moreover, all of these EEG indices correlated with behavioral performance in the time-estimation task, suggesting their essential roles in learning and adjusting performance to maximize winnings in a reward-learning situation. Importantly, enhanced EEG power during Reward trials, as reflected by stronger 1) pre-feedback alpha suppression, 2) feedback-locked theta and 3) feedback-locked beta, was associated with a greater preference for larger-but-delayed rewards in a separate, behavioral delay-discounting task. Results highlight the association between a stronger preference toward larger-but-delayed rewards and enhanced reward-processing. Moreover, our reward-processing EEG indices detail the specific stages of reward-processing where these associations occur. Copyright © 2016 Elsevier Ltd. All rights reserved.

The Performance of A Sampled Data Delay Lock Loop Implemented with a Kalman Loop Filter.

DTIC Science & Technology

1980-01-01

que for analysis is computer simulation. Other techniques include state variable techniques and z-transform methods. Since the Kalman filter is linear...LOGIC NOT SHOWN Figure 2. Block diagram of the sampled data delay lock loop (SDDLL) Es A/ A 3/A/ Figure 3. Sampled error voltage ( Es ) as a function of...from a sum of two components. The first component is the previous filtered es - timate advanced one step forward by the state transition matrix. The 8

Class-A mode-locked lasers: Fundamental solutions

NASA Astrophysics Data System (ADS)

Kovalev, Anton V.; Viktorov, Evgeny A.

2017-11-01

We consider a delay differential equation (DDE) model for mode-locked operation in class-A semiconductor lasers containing both gain and absorber sections. The material processes are adiabatically eliminated as these are considered fast in comparison to the delay time for a long cavity device. We determine the steady states and analyze their bifurcations using DDE-BIFTOOL [Engelborghs et al., ACM Trans. Math. Software 28, 1 (2002)]. Multiple forms of coexistence, transformation, and hysteretic behavior of stable steady states and fundamental periodic regimes are discussed in bifurcation diagrams.

Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

PubMed

Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

2015-05-18

This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C.

Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips

PubMed Central

Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

2015-01-01

This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of −0.7/0.6 °C from −30 °C to 70 °C after 1-point calibration at 30 °C. PMID:25993518

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Phase-locked-loop-based delay-line-free picosecond electro-optic sampling system

NASA Astrophysics Data System (ADS)

Lin, Gong-Ru; Chang, Yung-Cheng

2003-04-01

A delay-line-free, high-speed electro-optic sampling (EOS) system is proposed by employing a delay-time-controlled ultrafast laser diode as the optical probe. Versatile optoelectronic delay-time controllers (ODTCs) based on modified voltage-controlled phase-locked-loop phase-shifting technologies are designed for the laser. The integration of the ODTC circuit and the pulsed laser diode has replaced the traditional optomechanical delay-line module used in the conventional EOS system. This design essentially prevents sampling distortion from misalignment of the probe beam, and overcomes the difficulty in sampling free-running high-speed transients. The maximum tuning range, error, scanning speed, tuning responsivity, and resolution of the ODTC are 3.9π (700°), <5% deviation, 25-2405 ns/s, 0.557 ps/mV, and ˜1 ps, respectively. Free-running wave forms from the analog, digital, and pulsed microwave signals are sampled and compared with those measured by the commercial apparatus.

Wafer Scale Distributed Radio

DTIC Science & Technology

2009-07-01

equation, we can derive: ∆ flock = f0 2Q Ain j A (5.34) with Ain j and A , the relative amplitude of the injecting signal and the oscillator signal, both...center of the line (Ain j = A ), then the locking range is equal to 1250MHz for a 10GHz oscillation frequency. With the architecture previously described...resonator in 90nm CMOS. In 2008 IEEE MTT-S International Microwave Symposium Digest (2008), pp. 775–778. [27] MCLEAN, J . A re-examination of the fundamental

Efficient design of CMOS TSC checkers

NASA Technical Reports Server (NTRS)

Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

1990-01-01

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches

NASA Astrophysics Data System (ADS)

Lee, Jaejun; Lee, Sungho; Song, Yonghoon; Nam, Sangwook

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13µm standard CMOS technology and the experimental results agree well with the theory.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

PubMed

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-11-17

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Anticipated and zero-lag synchronization in motifs of delay-coupled systems

NASA Astrophysics Data System (ADS)

Mirasso, Claudio R.; Carelli, Pedro V.; Pereira, Tiago; Matias, Fernanda S.; Copelli, Mauro

2017-11-01

Anticipated and zero-lag synchronization have been observed in different scientific fields. In the brain, they might play a fundamental role in information processing, temporal coding and spatial attention. Recent numerical work on anticipated and zero-lag synchronization studied the role of delays. However, an analytical understanding of the conditions for these phenomena remains elusive. In this paper, we study both phenomena in systems with small delays. By performing a phase reduction and studying phase locked solutions, we uncover the functional relation between the delay, excitation and inhibition for the onset of anticipated synchronization in a sender-receiver-interneuron motif. In the case of zero-lag synchronization in a chain motif, we determine the stability conditions. These analytical solutions provide an excellent prediction of the phase-locked regimes of Hodgkin-Huxley models and Roessler oscillators.

[Comparison of effect between early and delayed in primary intramedullary nailing combined with locked plate fixation for the treatment of multi-segments tibial fractures of type].

PubMed

Gao, Wei-qiang; Hu, Jiang-hai; Gu, Zhu-chao; Zhang, Huai-xian; Min, Peng; Zhang, Lin-jun; Yu, Wen-wen; Wang, Guang-lin

2015-02-01

To compare the clinical results of early and delayed intramedullary nailing and locked plating for the treatment of multi-segments tibial fractures of type AO/ASIF-42C2. Between January 2010 and January 2013,45 patients with multi-segments closed tibial fractures of AO/ASIF-42C2 were treated by early primary intramedullary nailing and locked plating in 20 cases as early group and delayed in 25 cases as delayed group. In early group,20 cases included 13 males and 7 females with an average age of (37.9±14.3) years old ranging from 20 to 56 years;according to soft tissue injury Tscherne classification, 8 fractures were frade I,12 were grade II. In delayed group, 25 cases included 17 males and 8 females with an average age of (38.7±17.2) years old ranging from 24 to 55 years,4 fractures were grade I ,19 were grade II ,2 were grade III. The operative time, blood loss, hospital stay,fracture healing time and complications were recorded. At final follow-up, the Johner-Wruhs score were used to evaluate functional efficacy, and the posterior-anterior and lateral X-ray to evaluate fracture reduction and alignment. All the patients were followed up for (12.5±2.5) months in early group and (13.2±2.8) months in delayed group (P>0.05). No wounds infections were happened. At the last follow-up, the mean range of knee joint was 10°-0°-120°. According to Johner-Wruhs scoring,there were 15 cases in excellent,3 in good,fair in 2 in early group; 21 in excellent,2 in good,2 in fair. The average operative time,blood loss had no significant differences between two groups (P>0.05), but hospital stay in early group was significantly shorter than those in delayed group(P<0.05). Average fracture healing time of early group and delayed group were (5.3±2.6) months and (6.0±2.9) months, respectively (P>0.05). For multi-segments tibial fractures of type AO/ASIF-42C2 with preoperative minor soft tissue injuries lighter of Tscherne grade I or II, early primary intramedullary nailing and locked plating does not significantly increase the postoperative incidence of soft tissue complications for patients. The early and delayed primary intramedullary nailing and locked plating for treatment of AO/ASIF-42C2 proximal third tibial fractures can get similar curative effect.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

NASA Astrophysics Data System (ADS)

Wei, Liu; Wei, Li; Peng, Ren; Qinglong, Lin; Shengdong, Zhang; Yangyuan, Wang

2009-09-01

A time-domain digitally controlled oscillator (DCO) is proposed. The DCO is composed of a free-running ring oscillator (FRO) and a two lap-selectors integrated flying-adder (FA). With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13 μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

Introduction of a new opto-electrical phase-locked loop in CMOS technology: the PMD-PLL

NASA Astrophysics Data System (ADS)

Ringbeck, Thorsten; Schwarte, Rudolf; Buxbaum, Bernd

1999-12-01

The huge and increasing need of information in the industrial world demands an enormous potential of bandwidth in telecommunication systems. Optical communication provides all participants with the whole spectrum of digital services like videophone, cable TV, video conferencing and online services. Especially fast and low cost opto-electrical receivers are badly needed in order to expand fiber networks to every home (FTTH--fiber to the home or FTTD--fiber to the desk, respectively). This paper proposes a new receiver structure which is designed to receiver optical data which are encoded by code division multiple access techniques (CDMA). For data recovery in such CDMA networks phase locked loops (PLL) are needed, which synchronize the local oscillator with the incoming clock. In optical code division multiple access networks these PLLs could be realized either with an electrical PLL after opto-electrical converting or directly in the optical path with a pure optical PLL.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Phase noise mitigation of QPSK signal utilizing phase-locked multiplexing of signal harmonics and amplitude saturation.

PubMed

Mohajerin-Ariaei, Amirhossein; Ziyadi, Morteza; Chitgarha, Mohammad Reza; Almaiman, Ahmed; Cao, Yinwen; Shamee, Bishara; Yang, Jeng-Yuan; Akasaka, Youichi; Sekiya, Motoyoshi; Takasaka, Shigehiro; Sugizaki, Ryuichi; Touch, Joseph D; Tur, Moshe; Langrock, Carsten; Fejer, Martin M; Willner, Alan E

2015-07-15

We demonstrate an all-optical phase noise mitigation scheme based on the generation, delay, and coherent summation of higher order signal harmonics. The signal, its third-order harmonic, and their corresponding delayed variant conjugates create a staircase phase-transfer function that quantizes the phase of quadrature-phase-shift-keying (QPSK) signal to mitigate phase noise. The signal and the harmonics are automatically phase-locked multiplexed, avoiding the need for phase-based feedback loop and injection locking to maintain coherency. The residual phase noise converts to amplitude noise in the quantizer stage, which is suppressed by parametric amplification in the saturation regime. Phase noise reduction of ∼40% and OSNR-gain of ∼3  dB at BER 10(-3) are experimentally demonstrated for 20- and 30-Gbaud QPSK input signals.

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

NASA Astrophysics Data System (ADS)

Deng, Xiaoying; Yang, Jun; Wu, Jianhui

2011-09-01

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13 µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100 mVpk-pk, the measured jitters were 33.9 ps at the rate of fG = 192 MHz and 148.5 ps at the rate of fG = 40 MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40 MHz, respectively.

A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

PubMed Central

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-01-01

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

A CMOS pressure sensor tag chip for passive wireless applications.

PubMed

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-03-23

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

PubMed

An Hu; Chodavarapu, Vamsy P

2010-10-01

We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

Ultralow-frequency-noise stabilization of a laser by locking to an optical fiber-delay line.

PubMed

Kéfélian, Fabien; Jiang, Haifeng; Lemonde, Pierre; Santarelli, Giorgio

2009-04-01

We report the frequency stabilization of an erbium-doped fiber distributed-feedback laser using an all-fiber-based Michelson interferometer of large arm imbalance. The interferometer uses a 1 km SMF-28 optical fiber spool and an acousto-optic modulator allowing heterodyne detection. The frequency-noise power spectral density is reduced by more than 40 dB for Fourier frequencies ranging from 1 Hz to 10 kHz, corresponding to a level well below 1 Hz2/Hz over the entire range; it reaches 10(-2) Hz2/Hz at 1 kHz. Between 40 Hz and 30 kHz, the frequency noise is shown to be comparable to the one obtained by Pound-Drever-Hall locking to a high-finesse Fabry-Perot cavity. Locking to a fiber delay line could consequently represent a reliable, simple, and compact alternative to cavity stabilization for short-term linewidth reduction.

Efficient laser noise reduction method via actively stabilized optical delay line.

PubMed

Li, Dawei; Qian, Cheng; Li, Ye; Zhao, Jianye

2017-04-17

We report a fiber laser noise reduction method by locking it to an actively stabilized optical delay line, specifically a fiber-based Mach-Zehnder interferometer with a 10 km optical fiber spool. The fiber spool is used to achieve large arm imbalance. The heterodyne signal of the two arms converts the laser noise from the optical domain to several megahertz, and it is used in laser noise reduction by a phase-locked loop. An additional phase-locked loop is induced in the system to compensate the phase noise due to environmentally induced length fluctuations of the optical fiber spool. A major advantage of this structure is the efficient reduction of out-of-loop frequency noise, particularly at low Fourier frequency. The frequency noise reaches -30 dBc/Hz at 1 Hz, which is reduced by more than 90 dB compared with that of the laser in its free-running state.

Integration of nanostructured planar diffractive lenses dedicated to near infrared detection for CMOS image sensors.

PubMed

Lopez, Thomas; Massenot, Sébastien; Estribeau, Magali; Magnan, Pierre; Pardo, Fabrice; Pelouard, Jean-Luc

2016-04-18

This paper deals with the integration of metallic and dielectric nanostructured planar lenses into a pixel from a silicon based CMOS image sensor, for a monochromatic application at 1.064 μm. The first is a Plasmonic Lens, based on the phase delay through nanoslits, which has been found to be hardly compatible with current CMOS technology and exhibits a notable metallic absorption. The second is a dielectric Phase-Fresnel Lens integrated at the top of a pixel, it exhibits an Optical Efficiency (OE) improved by a few percent and an angle of view of 50°. The third one is a metallic diffractive lens integrated inside a pixel, which shows a better OE and an angle of view of 24°. The last two lenses exhibit a compatibility with a spectral band close to 1.064 μm.

Optical, analog and digital domain architectural considerations for visual communications

NASA Astrophysics Data System (ADS)

Metz, W. A.

2008-01-01

The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations and into new architectures. Future architectures for visual communications will require extending the implementation into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Army Corps of Engineers: Factors Contributing to Cost Increases and Schedule Delays in the Olmsted Locks and Dam Project

DTIC Science & Technology

2017-02-01

to cost increases and schedule delays and (2) what is known about the costs of benefits foregone because of project delays. GAO compared the...Contributors to Cost Increases and Schedule Delays 13 Total Cost of Benefits Foregone from Project Delays at Olmsted Is Uncertain 27 Agency Comments...would take 7 years. The Corps also estimated benefits , such as transportation cost savings, associated with the project. However, once the project was

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

PubMed Central

Kim, Sungho; Lepkowski, William; Wilk, Seth J.; Thornton, Trevor J.; Bakkaloglu, Bertan

2014-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of −70dBm and −98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10−3 at the input powers of −70dBm at 1.2V and −98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

A high-throughput flow cytometry-on-a-CMOS platform for single-cell dielectric spectroscopy at microwave frequencies.

PubMed

Chien, Jun-Chau; Ameri, Ali; Yeh, Erh-Chia; Killilea, Alison N; Anwar, Mekhail; Niknejad, Ali M

2018-06-06

This work presents a microfluidics-integrated label-free flow cytometry-on-a-CMOS platform for the characterization of the cytoplasm dielectric properties at microwave frequencies. Compared with MHz impedance cytometers, operating at GHz frequencies offers direct intracellular permittivity probing due to electric fields penetrating through the cellular membrane. To overcome the detection challenges at high frequencies, the spectrometer employs on-chip oscillator-based sensors, which embeds simultaneous frequency generation, electrode excitation, and signal detection capabilities. By employing an injection-locking phase-detection technique, the spectrometer offers state-of-the-art sensitivity, achieving a less than 1 aFrms capacitance detection limit (or 5 ppm in frequency-shift) at a 100 kHz noise filtering bandwidth, enabling high throughput (>1k cells per s), with a measured cellular SNR of more than 28 dB. With CMOS/microfluidics co-design, we distribute four sensing channels at 6.5, 11, 17.5, and 30 GHz in an arrayed format whereas the frequencies are selected to center around the water relaxation frequency at 18 GHz. An issue in the integration of CMOS and microfluidics due to size mismatch is also addressed through introducing a cost-efficient epoxy-molding technique. With 3-D hydrodynamic focusing microfluidics, we perform characterization on four different cell lines including two breast cell lines (MCF-10A and MDA-MB-231) and two leukocyte cell lines (K-562 and THP-1). After normalizing the higher frequency signals to the 6.5 GHz ones, the size-independent dielectric opacity shows a differentiable distribution at 17.5 GHz between normal (0.905 ± 0.160, mean ± std.) and highly metastatic (1.033 ± 0.107) breast cells with p ≪ 0.001.

A High Performance 50% Clock Duty Cycle Regulator

NASA Astrophysics Data System (ADS)

Huang, Peng; Deng, Hong-Hui; Yin, Yong-Sheng

A low-jitter clock duty cycle corrector circuit applied in high performance ADC is presented in the paper, such circuits can change low accuracy input signals with different frequencies into 50% pulse width clock. The result have show that the circuit could lock duty cycle rapidly with an accuracy of 50% ± 1% in 200ns. This circuit have 10%-90% of duty cycle input, and clock jitter could be suppressed to less than 5ps. The method used in the circuit, which provides little relationship with the noise and process mismatch, is widely used Implemented in 0.18μm CMOS process.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

PubMed

Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

2016-09-23

In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

Asymmetric dual-loop feedback to suppress spurious tones and reduce timing jitter in self-mode-locked quantum-dash lasers emitting at 155 μm

NASA Astrophysics Data System (ADS)

Asghar, Haroon; McInerney, John G.

2017-09-01

We demonstrate an asymmetric dual-loop feedback scheme to suppress external cavity side-modes induced in self-mode-locked quantum-dash lasers with conventional single and dual-loop feedback. In this letter, we achieved optimal suppression of spurious tones by optimizing the length of second delay time. We observed that asymmetric dual-loop feedback, with large (~8x) disparity in cavity lengths, eliminates all external-cavity side-modes and produces flat RF spectra close to the main peak with low timing jitter compared to single-loop feedback. Significant reduction in RF linewidth and reduced timing jitter was also observed as a function of increased second feedback delay time. The experimental results based on this feedback configuration validate predictions of recently published numerical simulations. This interesting asymmetric dual-loop feedback scheme provides simplest, efficient and cost effective stabilization of side-band free optoelectronic oscillators based on mode-locked lasers.

Delayed unlatching mechanism

DOEpatents

Bzorgi, Fariborz M.

2015-05-19

In various embodiments an apparatus is presented for securing a structure such as a door, window, hatch, or gate that moves between an open and a closed position relative to a fixed structure to provide or deny access to a compartment, a room, an outdoor area, or a facility. Various embodiments provide a delay in opening the closure of sufficient duration to frustrate a rapid activation that might be desired by a person who is attempting to pass through the closure for some illicit purpose. Typically, hydraulics are used to activate the apparatus and no electrical energy or electronic signals are employed. In one embodiment, a plurality of actuations of a hand lever operates a hydraulic pump that moves a locking bolt from a first position in which a locking bolt is engaged with a recess in the fixed structure (preventing opening of a gate) to a second position in which the locking bolt is disengaged from the recess to permit opening of the gate.

High-speed and low-power repeater for VLSI interconnects

NASA Astrophysics Data System (ADS)

Karthikeyan, A.; Mallick, P. S.

2017-10-01

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.

Phase-sensitive techniques applied to a micromachined vacuum sensor

NASA Astrophysics Data System (ADS)

Chapman, Glenn H.; Sawadsky, N.; Juneja, P. P.

1996-09-01

Phase sensitive AC measurement techniques are particularly applicable to micromachined sensors detecting temperature changes at a sensor caused by a microheater. The small mass produces rapid thermal response to AC signals which are easily detectable with lock-in amplifiers. Phase sensitive measurements were applied to a CMOS compatible micromachined pressure sensor consisting a polysilicon sense line, 760 microns long, on an oxide microbridge separated by 6 microns on each horizontal side from similar polysilicon heaters, all over a micromachined cavity. Sinusoidal heater signals at 32 Hz induced temperature caused sense line resistance changes at 64 Hz. The lock-in detected this as a first harmonic sense resistor voltage from a DC constant sense current. By observing the first harmonic the lock-in rejects all AC coupling of noise by capacitance or inductance, by measuring only those signals at the 64 Hz frequency and with a fixed phase relationship to the heater driver signals. This sensor produces large signals near atmospheric pressure, declining to 7 (mu) V below 0.1 mTorr. Phase measurements between 760 and 100 Torr where the air's thermal conductivity changes little, combined with amplitude changes at low pressure generate a pressure measurement accurate at 5 percent from 760 Torr to 10 mTorr, sensing of induced temperature changes of 0.001 degree C.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

A low power MICS band phase-locked loop for high resolution retinal prosthesis.

PubMed

Yang, Jiawei; Skafidas, Efstratios

2013-08-01

Ultra low power dissipation is essential in retinal prosthesis and many other biomedical implants. Extensive research has been undertaken in designing low power biomedical transceivers, however to date, most effort has been focused on low frequency inductive links. For higher frequency, more robust and more complex applications, such as Medical Implant Communication Service (MICS) band multichannel transceivers, power consumption remains high. This paper explores the design of micro-power data links at 400 MHz for a high resolution retinal prosthesis. By taking advantage of advanced small geometry CMOS technology and precise transistor-level modeling, we successfully utilized subthreshold FET operation, which has been historically limited to low frequency circuits due to the inadequate transistor operating speed in and near weak inversion; we have implemented a low power MICS transceiver. Particularly, a low power, MICS band multichannel phase-locked loop (PLL) that employs a subthreshold voltage controlled oscillator (VCO) and digital synchronous dividers has been implemented on a 65-nm CMOS. A design methodology is presented in detail with the demonstration of EKV model parameters extraction. This PLL provides 600- mVpp quadrature oscillations and exhibits a phase noise of -102 dBc/Hz at 200-kHz offset, while only consuming 430- μW from a 1-V supply. The VCO has a gain (KVCO) of 12 MHz/V and is designed to operate in the near-weak inversion region and consumes 220- μA DC current. The designed PLL has a core area of 0.54 mm(2). It satisfies all specifications of MICS band operation with the advantage of significant reduction in power which is crucial for high resolution retinal prosthesis.

Investigation of monolithic passively mode-locked quantum dot lasers with extremely low repetition frequency.

PubMed

Xu, Tianhong; Cao, Juncheng; Montrosset, Ivo

2015-01-01

The dynamical regimes and performance optimization of quantum dot monolithic passively mode-locked lasers with extremely low repetition rate are investigated using the numerical method. A modified multisection delayed differential equation model is proposed to accomplish simulations of both two-section and three-section passively mode-locked lasers with long cavity. According to the numerical simulations, it is shown that fundamental and harmonic mode-locking regimes can be multistable over a wide current range. These dynamic regimes are studied, and the reasons for their existence are explained. In addition, we demonstrate that fundamental pulses with higher peak power can be achieved when the laser is designed to work in a region with smaller differential gain.

Injection locking of a two-mode electron oscillator with close frequencies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Starodubova, E. N.; Usacheva, S. A.; Ryskin, N. M.

2015-03-15

Theory of injection locking is developed for a two-mode electron maser with close frequencies, when the driving signal affects both modes. There exist two regimes of phase locking in which either first or second mode dominates. Hard transitions between the two regimes are observed with variation of the driving frequency. The results of numerical simulations are presented for the case of driving by a signal with linear frequency chirp, as well as by a signal with sinusoidal frequency modulation. The effect of bifurcation delay is observed with the increase of chirp rate.

Emergence of resonant mode-locking via delayed feedback in quantum dot semiconductor lasers.

PubMed

Tykalewicz, B; Goulding, D; Hegarty, S P; Huyet, G; Erneux, T; Kelleher, B; Viktorov, E A

2016-02-22

With conventional semiconductor lasers undergoing external optical feedback, a chaotic output is typically observed even for moderate levels of the feedback strength. In this paper we examine single mode quantum dot lasers under strong optical feedback conditions and show that an entirely new dynamical regime is found consisting of spontaneous mode-locking via a resonance between the relaxation oscillation frequency and the external cavity repetition rate. Experimental observations are supported by detailed numerical simulations of rate equations appropriate for this laser type. The phenomenon constitutes an entirely new mode-locking mechanism in semiconductor lasers.

Integer, Fractional, and Sideband Injection Locking of a Spintronic Feedback Nano-Oscillator to a Microwave Signal

NASA Astrophysics Data System (ADS)

Singh, Hanuman; Konishi, K.; Bhuktare, S.; Bose, A.; Miwa, S.; Fukushima, A.; Yakushiji, K.; Yuasa, S.; Kubota, H.; Suzuki, Y.; Tulapurkar, A. A.

2017-12-01

In this paper we demonstrate the injection locking of a recently demonstrated spintronic feedback nano-oscillator to microwave magnetic fields at integers (n =1 , 2, 3) as well as fractional multiples (f =1 /2 , 3 /2 , and 5 /2 ) of its auto-oscillation frequency. Feedback oscillators have delay as a new "degree of freedom" which is absent for spin-transfer torque-based oscillators, which gives rise to side peaks along with a main peak. We show that it is also possible to lock the oscillator on its sideband peaks, which opens an alternative avenue to phase-locked oscillators with large frequency differences. We observe that for low driving fields, sideband locking improves the quality factor of the main peak, whereas for higher driving fields the main peak is suppressed. Further, measurements at two field angles provide some insight into the role of the symmetry of oscillation orbit in determining the fractional locking.

Relationship between locking-bolt torque and load pre-tension in the Ilizarov frame.

PubMed

Osei, N A; Bradley, B M; Culpan, P; Mitchell, J B; Barry, M; Tanner, K E

2006-10-01

The wire-bolt interface in an Ilizarov frame has been mechanically tested. The optimal torque to be applied to the frame locking-bolts during physiological loading has been defined. The set-up configuration was as is used clinically except a copper tube was used to simulate bone. The force-displacement curves of the Ilizarov wires are not altered by locking-bolt torque. The force in the bone model at which pre-tension is lost increases as the locking-bolts are tightened to 14 Nm torque, but decreases if torque exceeds 14 Nm. Thus, 14 Nm is the optimal locking-bolt torque in frame. The relationship between pre-tension versus load for different locking-bolt torques arises because at low and high clamping torques poor wire holding and plastic deformation respectively occur. Wire damage was seen under light and electron microscopy. Clinically, over or under-tightening locking-bolts will cause loss of pre-tension, reduction in frame stiffness and excessive movement at the fracture site, which may be associated with delayed union.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors.

PubMed

Zhang, Xiang; Zhao, Jianwen; Dou, Junyan; Tange, Masayoshi; Xu, Weiwei; Mo, Lixin; Xie, Jianjun; Xu, Wenya; Ma, Changqi; Okazaki, Toshiya; Cui, Zheng

2016-09-01

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO 2 thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10 5 , mobility of ≈15 cm 2 V -1 s -1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V dd = 1.5 V) and maximum voltage gain of 30 at V dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V dd of 1 V is achieved. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High frequency optoelectronic oscillators based on the optical feedback of semiconductor mode-locked laser diodes.

PubMed

Haji, Mohsin; Hou, Lianping; Kelly, Anthony E; Akbar, Jehan; Marsh, John H; Arnold, John M; Ironside, Charles N

2012-01-30

Optical self seeding feedback techniques can be used to improve the noise characteristics of passively mode-locked laser diodes. External cavities such as fiber optic cables can increase the memory of the phase and subsequently improve the timing jitter. In this work, an improved optical feedback architecture is proposed using an optical fiber loop delay as a cavity extension of the mode-locked laser. We investigate the effect of the noise reduction as a function of the loop length and feedback power. The well known composite cavity technique is also implemented for suppressing supermode noise artifacts presented due to harmonic mode locking effects. Using this method, we achieve a record low radio frequency linewidth of 192 Hz for any high frequency (>1 GHz) passively mode-locked laser to date (to the best of the authors' knowledge), making it promising for the development of high frequency optoelectronic oscillators.

77 FR 63380 - Self-Regulatory Organizations; NYSE Arca, Inc.; Order Granting Approval of Proposed Rule Change...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-16

... purchase fixed income securities issued by U.S. or foreign corporations \\6\\ or financial institutions... also may purchase securities issued or guaranteed by the U.S. Government or foreign governments... (``CMOs'').\\8\\ The Fund may purchase or sell securities on a when issued, delayed delivery or forward...

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Solid State Research

DTIC Science & Technology

1985-08-15

Hz. The high-speed performance is consis- tent with the low stage delay observed in the ring-oscillator measurements , and the low - frequency ...Phase-Locked Loop 41 5-10 Phase-Locked-Loop Output Spectrum . Note that a 10-kHz Measure - ment Bandwidth Is Used. 42 5-11 Phase Error Response to an...the niobium. Reflections of bulk acoustic waves from optically generated holograms in Fe-doped LiNb03 have been observed and measured . Holographic

Millimeter Wave Spectroscopy in a Semi-Confocal Fabry-Perot Cavity

NASA Astrophysics Data System (ADS)

Drouin, Brian; Tang, Adrian; Reck, Theodore J.; Nemchick, Deacon J.; Cich, Matthew J.; Crawford, Timothy J.; Raymond, Alexander W.; Chang, M.-C. Frank; Kim, Rod M.

2017-06-01

A new generation of CMOS circuits operating at 89-104 GHz with improved output power and pulse switch isolation have enhanced the performance of the miniaturized pulsed-echo Fourier transform spectrometer under development for planetary exploration at the Jet Propulsion laboratory. Additional progress has been made by creating a waveguide-fed structure for the novel planar coupler design. This structure has enabled characterization of each component in the system and enabled spectroscopy to be done with conventional millimeter hardware that enables (1) direct comparisons to the CMOS components, (2) enhanced bandwidth of 74-109 GHz, and (3) amplification of the transmitter prior to cavity injection. We have now demonstrated the technique with room temperature detections on multiple species including N_2O, OCS, CH_3CN, CH_3OH, CH_3NH_2, CH_3CHO, CH_3Cl, HDO, D_2O, CH_3CH_2CN and CH_3CH_2OH. Of particular interest to spectroscopic work in the millimeter range is the ongoing incorporation of a ΔΣ radio-frequency source into the millimeter-wave lock-loop - this has improved the phase-noise of the tunable CMOS transceiver to better than the room-temperature Doppler limit and provides a promising source for general use that may replace the high end microwave synthesizers. We are in the process of building a functional interface to the various subsystems. We will present a trade-space study to determine the optimal operating conditions of the pulse-echo system.

Distal tibia fractures: locked or non-locked plating? A systematic review of outcomes.

PubMed

Khalsa, Amrit S; Toossi, Nader; Tabb, Loni P; Amin, Nirav H; Donohue, Kenneth W; Cerynik, Douglas L

2014-06-01

Although plating is considered to be the treatment of choice in distal tibia fractures, controversies abound regarding the type of plating for optimal fixation. We conducted a systematic review to evaluate and compare the outcomes of locked plating and non-locked plating in treatment of distal tibia fractures. A systematic review was conducted using PubMed to identify articles on the outcomes of plating in distal tibia fractures that were published up to June 2012. We included English language articles involving a minimum of 10 adult cases with acute fractures treated using single-plate, minimally invasive techniques. Study-level binomial regression on the pooled data was conducted to determine the effect of locking status on different outcomes, adjusted for age, sex, and other independent variables. 27 studies met the inclusion criteria and were included in the final analysis of 764 cases (499 locking, 265 non-locking). Based on descriptive analysis only, delayed union was reported in 6% of cases with locked plating and in 4% of cases with non-locked plating. Non-union was reported in 2% of cases with locked plating and 3% of cases with non-locked plating. Comparing locked and non-locked plating, the odds ratio (OR) for reoperation was 0.13 (95% CI: 0.03-0.57) and for malalignment it was 0.10 (95% CI: 0.02-0.42). Both values were statistically significant. This study showed that locked plating reduces the odds of reoperation and malalignment after treatment for acute distal tibia fracture. Future studies should accurately assess causality and the clinical and economic impact of these findings.

A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

PubMed

Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

2015-11-06

This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

Under Voltage Lock-Out Design Rules for Proper Start-Up of Energy Autonomous Systems Powered by Supercapacitors

NASA Astrophysics Data System (ADS)

Boitier, V.; Durand Estèbe, P.; Monthéard, R.; Bafleur, M.; Dilhac, J. M.

2013-12-01

This paper deals with the issue of the initial start-up of an autonomous and battery-free system powered by an energy harvester associated with a storage subsystem based on supercapacitors initially discharged. A review of different low power Under Voltage Lock-Out (UVLO) solutions used to delay the load start-up and to avoid a useless discharge of supercapacitors is presented and discussed.

Time Delay in the Kuramoto Model of Coupled Oscillators

NASA Astrophysics Data System (ADS)

Yeung, M. K. Stephen; Strogatz, Steven H.

1999-01-01

We generalize the Kuramoto model of coupled oscillators to allow time-delayed interactions. New phenomena include bistability between synchronized and incoherent states, and unsteady solutions with time-dependent order parameters. We derive exact formulas for the stability boundaries of the incoherent and synchronized states, as a function of the delay, in the special case where the oscillators are identical. The experimental implications of the model are discussed for populations of chirping crickets, where the finite speed of sound causes communication delays, and for physical systems such as coupled phase-locked loops or lasers.

Locked-mode avoidance and recovery without momentum input

NASA Astrophysics Data System (ADS)

Delgado-Aparicio, L.; Rice, J. E.; Wolfe, S.; Cziegler, I.; Gao, C.; Granetz, R.; Wukitch, S.; Terry, J.; Greenwald, M.; Sugiyama, L.; Hubbard, A.; Hugges, J.; Marmar, E.; Phillips, P.; Rowan, W.

2015-11-01

Error-field-induced locked-modes (LMs) have been studied in Alcator C-Mod at ITER-Bϕ, without NBI fueling and momentum input. Delay of the mode-onset and locked-mode recovery has been successfully obtained without external momentum input using Ion Cyclotron Resonance Heating (ICRH). The use of external heating in-sync with the error-field ramp-up resulted in a successful delay of the mode-onset when PICRH > 1 MW, which demonstrates the existence of a power threshold to ``unlock'' the mode; in the presence of an error field the L-mode discharge can transition into H-mode only when PICRH > 2 MW and at high densities, avoiding also the density pump-out. The effects of ion heating observed on unlocking the core plasma may be due to ICRH induced flows in the plasma boundary, or modifications of plasma profiles that changed the underlying turbulence. This work was performed under US DoE contracts including DE-FC02-99ER54512 and others at MIT, DE-FG03-96ER-54373 at University of Texas at Austin, and DE-AC02-09CH11466 at PPPL.

Optoelectronic frequency discriminated phase tuning technology and its applications

NASA Astrophysics Data System (ADS)

Lin, Gong-Ru; Chang, Yung-Cheng

2000-07-01

By using a phase-tunable optoelectronic phase-locked loop, we are able to continuously change the phase as well as the delay-time of optically distributed microwave clock signals or optical pulse train. The advantages of the proposed technique include such as wide-band operation up to 20GHz, wide-range tuning up to 640 degrees, high tuning resolution of <6x10-2 degree/mV, ultra-low short-term phase fluctuation and drive of 4.7x10-2 degree and 3.4x10- 3 degree/min, good linearity with acceptable deviations, and frequency-independent transferred function with slope of nearly 90 degrees/volt, etc. The novel optoelectronic phase shifter is performed by using a DC-voltage controlled, optoelectronic-mixer-based, frequency-down-converted digital phase-locked-loop. The maximum delay-time is continuously tunable up to 3.9 ns for optical pulses repeated at 500 MHz from a gain-switched laser diode. This corresponds to a delay responsivity of about 0.54 ps/mV. The using of the OEPS as being an optoelectronic delay-time controller for optical pulses is demonstrated with temporal resolution of <0.2 ps. Electro-optic sampling of high-frequency microwave signals by using the in-situ delay-time-tunable pulsed laser as a novel optical probe is primarily reported.

Distal tibia fractures: locked or non-locked plating?

PubMed Central

Khalsa, Amrit S; Toossi, Nader; Tabb, Loni P; Amin, Nirav H; Donohue, Kenneth W; Cerynik, Douglas L

2014-01-01

Background and purpose Although plating is considered to be the treatment of choice in distal tibia fractures, controversies abound regarding the type of plating for optimal fixation. We conducted a systematic review to evaluate and compare the outcomes of locked plating and non-locked plating in treatment of distal tibia fractures. Patients and methods A systematic review was conducted using PubMed to identify articles on the outcomes of plating in distal tibia fractures that were published up to June 2012. We included English language articles involving a minimum of 10 adult cases with acute fractures treated using single-plate, minimally invasive techniques. Study-level binomial regression on the pooled data was conducted to determine the effect of locking status on different outcomes, adjusted for age, sex, and other independent variables. Results 27 studies met the inclusion criteria and were included in the final analysis of 764 cases (499 locking, 265 non-locking). Based on descriptive analysis only, delayed union was reported in 6% of cases with locked plating and in 4% of cases with non-locked plating. Non-union was reported in 2% of cases with locked plating and 3% of cases with non-locked plating. Comparing locked and non-locked plating, the odds ratio (OR) for reoperation was 0.13 (95% CI: 0.03–0.57) and for malalignment it was 0.10 (95% CI: 0.02–0.42). Both values were statistically significant. Interpretation This study showed that locked plating reduces the odds of reoperation and malalignment after treatment for acute distal tibia fracture. Future studies should accurately assess causality and the clinical and economic impact of these findings. PMID:24758325

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Noncoherent pseudonoise code tracking performance of spread spectrum receivers

NASA Technical Reports Server (NTRS)

Simon, M. K.

1977-01-01

The optimum design and performance of two noncoherent PN tracking loop configurations, namely, the delay-locked loop and tau-dither loop, are described. In particular, the bandlimiting effects of the bandpass arm filters are considered by demonstrating that for a fixed data rate and data signal-to-noise ratio, there exists an optimum filter bandwidth in the sense of minimizing the loop's tracking jitter. Both the linear and nonlinear loop analyses are presented, and the region of validity of the former relative to the latter is indicated. In addition, numerical results are given for several filter types. For example, assuming ideal bandpass arm filters, it is shown that the tau-dither loop requires approximately 1 dB more signal-to-noise ratio than the delay-locked loop for equal rms tracking jitters.

A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

NASA Astrophysics Data System (ADS)

Yuanxin, Zhao; Yuanpei, Gao; Wei, Li; Ning, Li; Junyan, Ren

2015-01-01

A 0.8-4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper. Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the “pulse-swallowing” phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary. The measurement results show that the output frequency range of this frequency synthesizer is 0.8-4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached -100 dBc/Hz, and -125 dBc/Hz respectively. The lowest reference spur is -58 dBc.

Phase-locked loop design with fast-digital-calibration charge pump

NASA Astrophysics Data System (ADS)

Wang, San-Fu; Hwang, Tsuen-Shiau; Wang, Jhen-Ji

2016-02-01

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27-2.88 GHz frequency synthesiser fabricated in TSMC 0.18 μm CMOS 1.8 V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6 V. The proposed PLL has a total power consumption of 22.57 mW and a settling time of 10 μs or less.

A High Performance LIA-Based Interface for Battery Powered Sensing Devices

PubMed Central

García-Romeo, Daniel; Valero, María R.; Medrano, Nicolás; Calvo, Belén; Celma, Santiago

2015-01-01

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to −39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment. PMID:26437408

A High Performance LIA-Based Interface for Battery Powered Sensing Devices.

PubMed

García-Romeo, Daniel; Valero, María R; Medrano, Nicolás; Calvo, Belén; Celma, Santiago

2015-09-30

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to -39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment.

Analysis of Recreational Boating Impact on Navigation Lock Performance

DTIC Science & Technology

1989-12-01

seeing the large craft at night. Another comment, a common one at most locks, was the lack of knowledge of rules by many recreational boaters. Several...cause of time delays, and not recreational boats. However, one of the pilots indicated that water skiers were major hazards to commercial barges as...they cut across the path of commercial tows below the line of sight of the pilot. Recreational boaters and particularly those pulling skiers should be

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

On-chip programmable ultra-wideband microwave photonic phase shifter and true time delay unit.

PubMed

Burla, Maurizio; Cortés, Luis Romero; Li, Ming; Wang, Xu; Chrostowski, Lukas; Azaña, José

2014-11-01

We proposed and experimentally demonstrated an ultra-broadband on-chip microwave photonic processor that can operate both as RF phase shifter (PS) and true-time-delay (TTD) line, with continuous tuning. The processor is based on a silicon dual-phase-shifted waveguide Bragg grating (DPS-WBG) realized with a CMOS compatible process. We experimentally demonstrated the generation of delay up to 19.4 ps over 10 GHz instantaneous bandwidth and a phase shift of approximately 160° over the bandwidth 22-29 GHz. The available RF measurement setup ultimately limits the phase shifting demonstration as the device is capable of providing up to 300° phase shift for RF frequencies over a record bandwidth approaching 1 THz.

IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

NASA Astrophysics Data System (ADS)

Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

2011-04-01

This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

The front-end electronics of the LSPE-SWIPE experiment

NASA Astrophysics Data System (ADS)

Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

2016-07-01

The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

Introduction to Focus Issue: Time-delay dynamics

NASA Astrophysics Data System (ADS)

Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

2017-11-01

The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

Symbol lock detection implemented with nonoverlapping integration intervals

NASA Technical Reports Server (NTRS)

Shihabi, Mazen M. (Inventor); Hinedi, Sami M. (Inventor); Shah, Biren N. (Inventor)

1995-01-01

A symbol lock detector is introduced for an incoming coherent digital communication signal which utilizes a subcarrier modulated with binary symbol data, d(sub k), and known symbol interval T by integrating binary values of the signal over nonoverlapping first and second intervals selected to be T/2, delaying the first integral an interval T/2, and either summing or multiplying the second integral with the first one that preceded it to form a value X(sub k). That value is then averaged over a number M of symbol intervals to produce a static value Y. A symbol lock decision can then be made when the static value Y exceeds a threshold level delta.

11-GHz waveguide Nd:YAG laser CW mode-locked with single-layer graphene.

PubMed

Okhrimchuk, Andrey G; Obraztsov, Petr A

2015-06-08

We report stable, passive, continuous-wave (CW) mode-locking of a compact diode-pumped waveguide Nd:YAG laser with a single-layer graphene saturable absorber. The depressed cladding waveguide in the Nd:YAG crystal is fabricated with an ultrafast laser inscription method. The saturable absorber is formed by direct deposition of CVD single-layer graphene on the output coupler. The few millimeter-long cavity provides generation of 16-ps pulses with repetition rates in the GHz range (up to 11.3 GHz) and 12 mW average power. Stable CW mode-locking operation is achieved by controlling the group delay dispersion in the laser cavity with a Gires-Tournois interferometer.

The performance of a sampled data delay lock loop implemented with a Kalman loop filter

NASA Astrophysics Data System (ADS)

Eilts, H. S.

1980-01-01

The purpose of this study is to evaluate the steady-state and transient (lock-up) performance of a tracking loop implemented with a Kalman filter. Steady-state performance criteria are errors due to measurement noise (jitter) and Doppler errors due to motion of the tracking loop. Trade-offs exist between the two criteria such that increasing performance with respect to either one will cause performance decrease with respect to the other. It is shown that by carefully selecting filter parameters reasonable performance can be obtained for both criteria simultaneously. It is also shown that lock-up performance for the loop is acceptable when these parameters are used.

11-GHz waveguide Nd:YAG laser CW mode-locked with single-layer graphene

PubMed Central

Okhrimchuk, Andrey G.; Obraztsov, Petr A.

2015-01-01

We report stable, passive, continuous-wave (CW) mode-locking of a compact diode-pumped waveguide Nd:YAG laser with a single-layer graphene saturable absorber. The depressed cladding waveguide in the Nd:YAG crystal is fabricated with an ultrafast laser inscription method. The saturable absorber is formed by direct deposition of CVD single-layer graphene on the output coupler. The few millimeter-long cavity provides generation of 16-ps pulses with repetition rates in the GHz range (up to 11.3 GHz) and 12 mW average power. Stable CW mode-locking operation is achieved by controlling the group delay dispersion in the laser cavity with a Gires–Tournois interferometer. PMID:26052678

All-digital pulse-expansion-based CMOS digital-to-time converter.

PubMed

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm 2 . Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

All-digital pulse-expansion-based CMOS digital-to-time converter

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

DOE PAGES

Mincey, John Stephen; Su, Eric C.; Silva-Martinez, Jose; ...

2018-02-28

A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. Also, to eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse widths in the radar. Employing a total of 128 taps, the FIR filtermore » provides greater than 50-dB sharp attenuation in the stopband in order to minimize all out-of-band noise in the low signal-to-noise received radar signal. Fabricated in a 0.18-μm silicon on insulator CMOS process, the proposed filter consumes approximately 3.5 mW/tap with a 1.8-V supply. Finally, a 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3 greater than 8.5 dBm.« less

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mincey, John Stephen; Su, Eric C.; Silva-Martinez, Jose

A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. Also, to eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse widths in the radar. Employing a total of 128 taps, the FIR filtermore » provides greater than 50-dB sharp attenuation in the stopband in order to minimize all out-of-band noise in the low signal-to-noise received radar signal. Fabricated in a 0.18-μm silicon on insulator CMOS process, the proposed filter consumes approximately 3.5 mW/tap with a 1.8-V supply. Finally, a 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3 greater than 8.5 dBm.« less

A high-speed, tunable silicon photonic ring modulator integrated with ultra-efficient active wavelength control.

PubMed

Zheng, Xuezhe; Chang, Eric; Amberg, Philip; Shubin, Ivan; Lexau, Jon; Liu, Frankie; Thacker, Hiren; Djordjevic, Stevan S; Lin, Shiyun; Luo, Ying; Yao, Jin; Lee, Jin-Hyoung; Raj, Kannan; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

2014-05-19

We report the first complete 10G silicon photonic ring modulator with integrated ultra-efficient CMOS driver and closed-loop wavelength control. A selective substrate removal technique was used to improve the ring tuning efficiency. Limited by the thermal tuner driver output power, a maximum open-loop tuning range of about 4.5nm was measured with about 14mW of total tuning power including the heater driver circuit power consumption. Stable wavelength locking was achieved with a low-power mixed-signal closed-loop wavelength controller. An active wavelength tracking range of > 500GHz was demonstrated with controller energy cost of only 20fJ/bit.

Dynamics and Synchronization of Nonlinear Oscillators with Time Delays: A Study with Fiber Lasers

DTIC Science & Technology

2007-07-19

or coupling lines PC Polarization Controller PD Photodetector VA Variable Attenuator WDM Wavelength Division Multiplexer x Chapter 1 Introduction 1.1...lasers and detectors. Injection locking of lasers is a common practice that can be used to lock the frequency and phase of a laser to an injected signal...finding a basis vector that maximizes the mean squared projection of the data. Succeeding basis vectors are found that max- imize the projection with the

Frequency-Domain Channel Estimation and Equalization for Single Carrier Underwater Acoustic Communications

DTIC Science & Technology

2007-01-01

synchronization ; vm(k) white Gaussian noise with average power σ2. If the Doppler shift f m,k is significant, then it causes the received signal ym(k) to be time ...intersymbol interference (ISI) to extend over 20-300 symbols at a data rate of 2-10 kilosymbols per second. Another obstacle is the time -varying Doppler... synchronization that employs a phase-locked loop (PLL) or delay-locked loop (DLL). However, the DFE and PLL/DLL have to interact in a nonlinear fashion

Impulsive effects of phase-locked pulse pairs on nuclear motion in the electronic ground state

NASA Astrophysics Data System (ADS)

Cina, J. A.; Smith, T. J.

1993-06-01

The nonlinear effects of ultrashort phase-locked electronically resonant pulse pairs on the ground state nuclear motion are investigated theoretically. The pulse-pair propagator, momentum impulse, and displacement are determined in the weak field limit for pulse pairs separated by a time delay short on a nuclear time scale. Possible application to large amplitude vibrational excitation of the 104 cm-1 mode of α-perylene is considered and comparisons are made to other Raman excitation methods.

Effects of channel tap spacing on delay-lock tracking

NASA Astrophysics Data System (ADS)

Dana, Roger A.; Milner, Brian R.; Bogusch, Robert L.

1995-12-01

High fidelity simulations of communication links operating through frequency selective fading channels require both accurate channel models and faithful reproduction of the received signal. In modern radio receivers, processing beyond the analog-to-digital converter (A/D) is done digitally, so a high fidelity simulation is actually an emulation of this digital signal processing. The 'simulation' occurs in constructing the output of the A/D. One approach to constructing the A/D output is to convolve the channel impulse response function with the combined impulse response of the transmitted modulation and the A/D. For both link simulations and hardware channel simulators, the channel impulse response function is then generated with a finite number of samples per chip, and the convolution is implemented in a tapped delay line. In this paper we discuss the effects of the channel model tap spacing on the performance of delay locked loops (DLLs) in both direct sequence and frequency hopped spread spectrum systems. A frequency selective fading channel is considered, and the channel impulse response function is constructed with an integer number of taps per modulation symbol or chip. The tracking loop time delay is computed theoretically for this tapped delay line channel model and is compared to the results of high fidelity simulations of actual DLLs. A surprising result is obtained. The performance of the DLL depends strongly on the number of taps per chip. As this number increases the DLL delay approaches the theoretical limit.

Natural resources technical support program. Recreational use of Chickamauga Lock, Tennessee, and recreational boaters' perceptions of lock use conflicts. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Patterson, M.E.; Hammitt, W.E.; Titre, J.P.

1992-12-01

Recreational use of the Chickamauga Lock has more than doubled since 1984, when 3,139 recreational craft used the lock. Forty percent of the total annual use occurs during the month of June. The most common reason for heavy use during the month is to attend special events, although other locks in the Tennessee River Navigation System have also shown an increase in recreational use since 1984. Overall, the study suggests a low level of conflict between recreational and commercial users. Conflict among recreational users appears to be even less of a problem. The biggest source of conflict at the currentmore » time is not the actual delays, but recreational boaters' inability to predict whether the lock will be available for use prior to arriving at the dam. Nearly one half of the boaters indicated that this is a common problem during special events. The Corps can reduce this source of conflict to some extent by using an FM repeater to announce the estimated time of recreational and commercial lockages. A majority of the respondents supported this management alternative. The second most popular management alternative was the construction of a separate lock for commercial traffic.« less

A new modem for microwave time synchronisation via geosynchronous telecommunication satellites

NASA Astrophysics Data System (ADS)

Dienert, Michael

1992-06-01

A study illustrating the two way time transfer technique and describing the use of this technique with the MITREX (Microwave Time and Range Experiment) SATRE (Satellite Time and Range Experiment) modems is presented. The two way time transfer technique via geosynchronous telecom satellites is one of the most accurate methods for synchronization and comparison of remote clocks. Most of the unknown propagation delays can be eliminated by the two way principle. The use of a coherent spread spectrum technique with a truncated pseudonoise code offers a resolution better than 30 ps of the measured time interval. The receiver is built around a Delay Locked Loop (DLL), which correlates the received signal with the known PN sequence to derive the control signal of the loop. In the locked state both PN sequences are synchronous and tracking errors of less than 30 ps are possible. Results showing the accuracy of the modem depending on signal to noise ratio and variation of total input power levels are presented and show that the expected improvement of the jitter of the internal delay by an increase of the chip rate is possible.

Low mass MEMS/NEMS switch for a substitute of CMOS transistor using single-walled carbon nanotube thin film

NASA Astrophysics Data System (ADS)

Jang, Min-Woo

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied to reduce power dissipation of deeply scaled CMOS ICs. One possible candidate is the electrostatic electromechanical switch, which could be fabricated with conventional CMOS processing techniques. They have critical advantages compared to CMOS devices such as almost zero standby leakage in the off-state due to the absence of a pn junction and a gate oxide, as well as excellent drive current in the on-state due to a metallic channel. Despite their excellent standby power dissipation, the electrostatic MEMS/NEMS switches have not been considered as a viable replacement for CMOS devices due to their large mechanical delay. Moreover, previous literature reveals that their pull-in voltage and switching speed are strongly proportional to each other. This reduces their potential advantage. However, in this work, we theoretically and experimentally demonstrated that the use of single-walled carbon nanotube (SWNT) with very low mass density and strong mechanical properties could provide a route to move off of the conventional trend with respect to the pull-in voltage / switching speed tradeoff observed in the literature. We fabricated 2-terminal fixed- beam switches with aligned composite SWNT thin films. In this work, layer-by-layer (LbL) self-assembly and dielectrophoresis were selected for aligned-composite SWNT thin film deposition. The dense membranes were successfully patterned to form submicron beams by e-beam lithography and oxygen plasma etching. Fixed-fixed beam switches using these membranes successfully operated with approximately 600 psec switching delay and as low as a 3 V dc pull-in. From this we confirmed that the SWNT-based thin films have the potential to make fast MEMS switches with a low operation voltage due to its low mass density and high stiffness. However, the copolymer caused a serious reliability issue and a copolymer-free SWNT film deposition method was developed by replacing positive copolymer with a dispersion of positively functionalized SWNTs. The electrical and physical properties of pure single-walled carbon nanotube thin films deposited through a copolymer-free LbL self-assembly process are then discussed. The film thickness was proportional to the number of dipping cycles. The film resistivity was estimated as 2.19x10-3 Ω-cm after thermal treatments were performed. The estimated specific contact resistance to gold electrodes was 6.33x10-9 Ω-m2 from contact chain measurements. The fabricated 3-terminal MEMS switches using these films functioned as a beam for multiple switching cycles with a 4.5V pull-in voltage, which was operated like a 2-input NAND gate. The SWNT-based thin film switch is promising for a variety of applications to high-end nanoelectronics and high- performance MEMS/NEMS.

Digital phase-lock loop

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1991-01-01

An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.

Impact of adaptation currents on synchronization of coupled exponential integrate-and-fire neurons.

PubMed

Ladenbauer, Josef; Augustin, Moritz; Shiau, LieJune; Obermayer, Klaus

2012-01-01

The ability of spiking neurons to synchronize their activity in a network depends on the response behavior of these neurons as quantified by the phase response curve (PRC) and on coupling properties. The PRC characterizes the effects of transient inputs on spike timing and can be measured experimentally. Here we use the adaptive exponential integrate-and-fire (aEIF) neuron model to determine how subthreshold and spike-triggered slow adaptation currents shape the PRC. Based on that, we predict how synchrony and phase locked states of coupled neurons change in presence of synaptic delays and unequal coupling strengths. We find that increased subthreshold adaptation currents cause a transition of the PRC from only phase advances to phase advances and delays in response to excitatory perturbations. Increased spike-triggered adaptation currents on the other hand predominantly skew the PRC to the right. Both adaptation induced changes of the PRC are modulated by spike frequency, being more prominent at lower frequencies. Applying phase reduction theory, we show that subthreshold adaptation stabilizes synchrony for pairs of coupled excitatory neurons, while spike-triggered adaptation causes locking with a small phase difference, as long as synaptic heterogeneities are negligible. For inhibitory pairs synchrony is stable and robust against conduction delays, and adaptation can mediate bistability of in-phase and anti-phase locking. We further demonstrate that stable synchrony and bistable in/anti-phase locking of pairs carry over to synchronization and clustering of larger networks. The effects of adaptation in aEIF neurons on PRCs and network dynamics qualitatively reflect those of biophysical adaptation currents in detailed Hodgkin-Huxley-based neurons, which underscores the utility of the aEIF model for investigating the dynamical behavior of networks. Our results suggest neuronal spike frequency adaptation as a mechanism synchronizing low frequency oscillations in local excitatory networks, but indicate that inhibition rather than excitation generates coherent rhythms at higher frequencies.

Impact of Adaptation Currents on Synchronization of Coupled Exponential Integrate-and-Fire Neurons

PubMed Central

Ladenbauer, Josef; Augustin, Moritz; Shiau, LieJune; Obermayer, Klaus

2012-01-01

The ability of spiking neurons to synchronize their activity in a network depends on the response behavior of these neurons as quantified by the phase response curve (PRC) and on coupling properties. The PRC characterizes the effects of transient inputs on spike timing and can be measured experimentally. Here we use the adaptive exponential integrate-and-fire (aEIF) neuron model to determine how subthreshold and spike-triggered slow adaptation currents shape the PRC. Based on that, we predict how synchrony and phase locked states of coupled neurons change in presence of synaptic delays and unequal coupling strengths. We find that increased subthreshold adaptation currents cause a transition of the PRC from only phase advances to phase advances and delays in response to excitatory perturbations. Increased spike-triggered adaptation currents on the other hand predominantly skew the PRC to the right. Both adaptation induced changes of the PRC are modulated by spike frequency, being more prominent at lower frequencies. Applying phase reduction theory, we show that subthreshold adaptation stabilizes synchrony for pairs of coupled excitatory neurons, while spike-triggered adaptation causes locking with a small phase difference, as long as synaptic heterogeneities are negligible. For inhibitory pairs synchrony is stable and robust against conduction delays, and adaptation can mediate bistability of in-phase and anti-phase locking. We further demonstrate that stable synchrony and bistable in/anti-phase locking of pairs carry over to synchronization and clustering of larger networks. The effects of adaptation in aEIF neurons on PRCs and network dynamics qualitatively reflect those of biophysical adaptation currents in detailed Hodgkin-Huxley-based neurons, which underscores the utility of the aEIF model for investigating the dynamical behavior of networks. Our results suggest neuronal spike frequency adaptation as a mechanism synchronizing low frequency oscillations in local excitatory networks, but indicate that inhibition rather than excitation generates coherent rhythms at higher frequencies. PMID:22511861

Stabilization of self-mode-locked quantum dash lasers by symmetric dual-loop optical feedback

NASA Astrophysics Data System (ADS)

Asghar, Haroon; Wei, Wei; Kumar, Pramod; Sooudi, Ehsan; McInerney, John. G.

2018-02-01

We report experimental studies of the influence of symmetric dual-loop optical feedback on the RF linewidth and timing jitter of self-mode-locked two-section quantum dash lasers emitting at 1550 nm. Various feedback schemes were investigated and optimum levels determined for narrowest RF linewidth and low timing jitter, for single-loop and symmetric dual-loop feedback. Two symmetric dual-loop configurations, with balanced and unbalanced feedback ratios, were studied. We demonstrate that unbalanced symmetric dual loop feedback, with the inner cavity resonant and fine delay tuning of the outer loop, gives narrowest RF linewidth and reduced timing jitter over a wide range of delay, unlike single and balanced symmetric dual-loop configurations. This configuration with feedback lengths 80 and 140 m narrows the RF linewidth by 4-67x and 10-100x, respectively, across the widest delay range, compared to free-running. For symmetric dual-loop feedback, the influence of different power split ratios through the feedback loops was determined. Our results show that symmetric dual-loop feedback is markedly more effective than single-loop feedback in reducing RF linewidth and timing jitter, and is much less sensitive to delay phase, making this technique ideal for applications where robustness and alignment tolerance are essential.

Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

PubMed Central

Zhou, Bo; Zhang, Kun; Zhou, Wenbiao; Zhang, Yanjun; Liu, Dake

2013-01-01

The carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in 180 nm CMOS for high reconfiguration. The proposed architecture achieves wide CF range of 2 M–1 GHz, high power efficiency of 70%, and low error vector magnitude (EVM) of 3%, with spectrum purity of 20 dB optimized in comparison to the existing designs. PMID:24223503

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Phase stabilization for mode locked lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baer, M.T.

A method is described for stabilizing a phase relationship between two mode locked lasers, comprising: driving through a power splitter the mode lockers of both lasers from a single stable radio frequency source; monitoring the phase of pulses from each laser utilizing a fast photodiode output of each laser; feeding the output of the fast photodiodes to a phase detector and comparator; measuring a relative phase difference between the lasers with a phase detector and comparator, producing a voltage output signal or phase error signal representing the phase difference; amplifying and filtering the voltage output signal with an amplifier andmore » loop filter; feeding the resulting output signal to a voltage controlled phase delay between the power splitter and one of the lasers; and delaying the RF drive to the one laser to achieve a desired phase relationship, between the two lasers.« less

Stability of the mode-locking regime in tapered quantum-dot lasers

NASA Astrophysics Data System (ADS)

Bardella, P.; Drzewietzki, L.; Rossetti, M.; Weber, C.; Breuer, S.

2018-02-01

We study numerically and experimentally the role of the injection current and reverse bias voltage on the pulse stability of tapered, passively mode-locked, Quantum Dot (QD) lasers. By using a multi-section delayed differential equation and introducing in the model the QD inhomogenous broadening, we are able to predict the onset of leading and trailing edge instabilities in the emitted pulse trains and to identify specific trends of stability in dependence on the laser biasing conditions. The numerical results are confirmed experimentally trough amplitude and timing stability analysis of the pulses.

APPLICATIONS OF LASERS AND OTHER TOPICS IN QUANTUM ELECTRONICS: Determination of reflection coefficients of mirrors using a mode-locked laser and a dissector

NASA Astrophysics Data System (ADS)

Apolonskiĭ, A. A.; Vinokurov, Nikolai A.; Zinin, É. I.; Ishchenko, P. I.; Kuklin, A. E.; Popik, V. M.; Sokolov, A. S.; Shchebetov, S. D.

1992-09-01

A method is described for determining the reflection coefficients of high-density mirrors, based on the use of a mode-locked laser and a sensitive detector with a fast time resolution. The laser light is transmitted through an optical resonator formed by the investigated mirrors. The measured delay in the decay of a light pulse gives the damping time of the optical resonator. This is related to its Q factor determined by the reflection coefficients of its mirrors.

Centering a DDR Strobe in the Middle of a Data Packet

NASA Technical Reports Server (NTRS)

Johnson, Michael; Nelson, Dave; Seefeldt, James; Roper, Weston; Passow, Craig

2014-01-01

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

NASA Astrophysics Data System (ADS)

Park, Chester Sungchung; Park, Sungkyung

2018-07-01

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

High-speed line-scan camera with digital time delay integration

NASA Astrophysics Data System (ADS)

Bodenstorfer, Ernst; Fürtler, Johannes; Brodersen, Jörg; Mayer, Konrad J.; Eckel, Christian; Gravogl, Klaus; Nachtnebel, Herbert

2007-02-01

Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical application are discussed and key features of the camera are listed.

High linearity SPAD and TDC array for TCSPC and 3D ranging applications

NASA Astrophysics Data System (ADS)

Villa, Federica; Lussana, Rudi; Bronzi, Danilo; Dalla Mora, Alberto; Contini, Davide; Tisa, Simone; Tosi, Alberto; Zappa, Franco

2015-01-01

An array of 32x32 Single-Photon Avalanche-Diodes (SPADs) and Time-to-Digital Converters (TDCs) has been fabricated in a 0.35 μm automotive-certified CMOS technology. The overall dimension of the chip is 9x9 mm2. Each pixel is able to detect photons in the 300 nm - 900 nm wavelength range with a fill-factor of 3.14% and either to count them or to time stamp their arrival time. In photon-counting mode an in-pixel 6-bit counter provides photon-numberresolved intensity movies at 100 kfps, whereas in photon-timing mode the 10-bit in-pixel TDC provides time-resolved maps (Time-Correlated Single-Photon Counting measurements) or 3D depth-resolved (through direct time-of-flight technique) images and movies, with 312 ps resolution. The photodetector is a 30 μm diameter SPAD with low Dark Count Rate (120 cps at room temperature, 3% hot-pixels) and 55% peak Photon Detection Efficiency (PDE) at 450 nm. The TDC has a 6-bit counter and a 4-bit fine interpolator, based on a Delay Locked Loop (DLL) line, which makes the TDC insensitive to process, voltage, and temperature drifts. The implemented sliding-scale technique improves linearity, giving 2% LSB DNL and 10% LSB INL. The single-shot precision is 260 ps rms, comprising SPAD, TDC and driving board jitter. Both optical and electrical crosstalk among SPADs and TDCs are negligible. 2D fast movies and 3D reconstructions with centimeter resolution are reported.

From perception to action: phase-locked gamma oscillations correlate with reaction times in a speeded response task

PubMed Central

Fründ, Ingo; Busch, Niko A; Schadow, Jeanette; Körner, Ursula; Herrmann, Christoph S

2007-01-01

Background Phase-locked gamma oscillations have so far mainly been described in relation to perceptual processes such as sensation, attention or memory matching. Due to its very short latency (≈90 ms) such oscillations are a plausible candidate for very rapid integration of sensory and motor processes. Results We measured EEG in 13 healthy participants in a speeded reaction task. Participants had to press a button as fast as possible whenever a visual stimulus was presented. The stimulus was always identical and did not have to be discriminated from other possible stimuli. In trials in which the participants showed a fast response, a slow negative potential over central electrodes starting approximately 800 ms before the response and highly phase-locked gamma oscillations over central and posterior electrodes between 90 and 140 ms after the stimulus were observed. In trials in which the participants showed a slow response, no slow negative potential was observed and phase-locked gamma oscillations were significantly reduced. Furthermore, for slow response trials the phase-locked gamma oscillations were significantly delayed with respect to fast response trials. Conclusion These results indicate the relevance of phase-locked gamma oscillations for very fast (not necessarily detailed) integration processes. PMID:17439642

Synchronizable Q-switched, mode-locked, and cavity-dumped ruby laser for plasma diagnostics

NASA Astrophysics Data System (ADS)

Houtman, H.; Meyer, J.

1985-06-01

We report on the design and operation of an optimized version of a Q-switched, mode-locked, and cavity-dumped ruby-laser oscillator. The modulator window is much narrower than that assumed in conventional active mode-lock theory, and is shown to yield much shorter pulses than the latter in cases where the number of round trips is restricted. To allow a high-power pulse (≊1 GW) to evolve in the oscillator, and to allow simple synchronization to a (˜100 ns fixed delay) CO2 laser, a limit of 23 round trips was chosen, but similar limits may be imposed by lasers having short-gain duration as in an excimer laser. Details are given on the single spark gap switching element and Pockels cells, with an analysis of their expected switching speeds, in order to establish the effectiveness of the modulator, as compared to conventional sinusoidally driven active mode lockers. Single pulses of 50-70 mJ are reliably cavity-dumped after only 100-ns delay (23 round trips) with pulse length adjustable from 50-100 ps with ±5-ps stability. Relative timing between the main (CO2) and probe (ruby) pulses allows a measurement accuracy of ±50 ps to be attained.

Synchronizable Q-switched, mode-locked, and cavity-dumped ruby laser for plasma diagnostics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Houtman, H.; Meyer, J.

We report on the design and operation of an optimized version of a Q-switched, mode-locked, and cavity-dumped ruby-laser oscillator. The modulator window is much narrower than that assumed in conventional active mode-lock theory, and is shown to yield much shorter pulses than the latter in cases where the number of round trips is restricted. To allow a high-power pulse (roughly-equal1 GW) to evolve in the oscillator, and to allow simple synchronization to a (approx.100 ns fixed delay) CO/sub 2/ laser, a limit of 23 round trips was chosen, but similar limits may be imposed by lasers having short-gain duration asmore » in an excimer laser. Details are given on the single spark gap switching element and Pockels cells, with an analysis of their expected switching speeds, in order to establish the effectiveness of the modulator, as compared to conventional sinusoidally driven active mode lockers. Single pulses of 50--70 mJ are reliably cavity-dumped after only 100-ns delay (23 round trips) with pulse length adjustable from 50--100 ps with +- 5-ps stability. Relative timing between the main (CO/sub 2/) and probe (ruby) pulses allows a measurement accuracy of +- 50 ps to be attained.« less

Temporal evolution of oscillations and synchrony in GPi/muscle pairs in Parkinson's disease.

PubMed

Hurtado, José M; Rubchinsky, Leonid L; Sigvardt, Karen A; Wheelock, Vicki L; Pappas, Conrad T E

2005-03-01

Both standard spectral analysis and time-dependent phase correlation techniques were applied to 27 pairs of tremor-related single units in the globus pallidus internus (GPi) and EMG of patients with Parkinson's disease (PD) undergoing stereotactic neurosurgery. Over long time-scales (approximately 60 s), GPi tremor-related units were statistically coherent with restricted regions of the peripheral musculature displaying tremor. The distribution of pooled coherence across all pairs supports a classification of GPi cell/EMG oscillatory pairs into coherent or noncoherent. Analysis using approximately 2-s sliding windows shows that oscillatory activity in both GPi tremor units and muscles occurs intermittently over time. For brain/muscle pairs that are coherent, there is partial overlap in the times of oscillatory activity but, in most cases, no significant correlation between the times of oscillatory subepisodes in the two signals. Phase locking between coherent pairs occurs transiently; however, the phase delay is similar for different phase-locking subepisodes. Noncoherent pairs also show episodes of transient phase locking, but they occurred less frequently, and no preferred phase delay was seen across subepisodes. Tremor oscillations in pallidum and EMGs are punctuated by phase slips, which were classified as synchronizing or desynchronizing depending on their effect on phase locking. In coherent pairs, the incidence of synchronizing slips is higher than desynchronizing slips, whereas no significant difference was seen for noncoherent pairs. The results of this quantitative characterization of parkinsonian tremor provide a foundation for hypotheses about the structure and dynamical functioning of basal ganglia motor control networks involved in tremor generation.

A pseudo differential Gm—C complex filter with frequency tuning for IEEE802.15.4 applications

NASA Astrophysics Data System (ADS)

Xin, Cheng; Lungui, Zhong; Haigang, Yang; Fei, Liu; Tongqiang, Gao

2011-07-01

This paper presents a CMOS Gm—C complex filter for a low-IF receiver of the IEEE 802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements oftheIEEE802.15.4 standard.

Accurate Modeling Method for Cu Interconnect

NASA Astrophysics Data System (ADS)

Yamada, Kenta; Kitahara, Hiroshi; Asai, Yoshihiko; Sakamoto, Hideo; Okada, Norio; Yasuda, Makoto; Oda, Noriaki; Sakurai, Michio; Hiroi, Masayuki; Takewaki, Toshiyuki; Ohnishi, Sadayuki; Iguchi, Manabu; Minda, Hiroyasu; Suzuki, Mieko

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

Self-organized synchronization of digital phase-locked loops with delayed coupling in theory and experiment

PubMed Central

Wetzel, Lucas; Jörg, David J.; Pollakis, Alexandros; Rave, Wolfgang; Fettweis, Gerhard; Jülicher, Frank

2017-01-01

Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common time reference is key to coordinate signal transmission and processing. Here we show how the self-organized synchronization of mutually coupled digital phase-locked loops (DPLLs) can provide robust clocking in large-scale systems. We develop a nonlinear phase description of individual and coupled DPLLs that takes into account filter impulse responses and delayed signal transmission. Our phase model permits analytical expressions for the collective frequencies of synchronized states, the analysis of stability properties and the time scale of synchronization. In particular, we find that signal filtering introduces stability transitions that are not found in systems without filtering. To test our theoretical predictions, we designed and carried out experiments using networks of off-the-shelf DPLL integrated circuitry. We show that the phase model can quantitatively predict the existence, frequency, and stability of synchronized states. Our results demonstrate that mutually delay-coupled DPLLs can provide robust and self-organized synchronous clocking in electronic systems. PMID:28207779

Optically stabilized Erbium fiber frequency comb with hybrid mode-locking and a broad tunable range of repetition rate.

PubMed

Yang, Honglei; Wu, Xuejian; Zhang, Hongyuan; Zhao, Shijie; Yang, Lijun; Wei, Haoyun; Li, Yan

2016-12-01

We present an optically stabilized Erbium fiber frequency comb with a broad repetition rate tuning range based on a hybrid mode-locked oscillator. We lock two comb modes to narrow-linewidth reference lasers in turn to investigate the best performance of control loops. The control bandwidth of fast and slow piezoelectric transducers reaches 70 kHz, while that of pump current modulation with phase-lead compensation is extended to 32 kHz, exceeding laser intrinsic response. Eventually, simultaneous lock of both loops is realized to totally phase-stabilize the comb, which will facilitate precision dual-comb spectroscopy, laser ranging, and timing distribution. In addition, a 1.8-MHz span of the repetition rate is achieved by an automatic optical delay line that is helpful in manufacturing a secondary comb with a similar repetition rate. The oscillator is housed in a homemade temperature-controlled box with an accuracy of ±0.02  K, which not only keeps high signal-to-noise ratio of the beat notes with reference lasers, but also guarantees self-starting at the same mode-locking every time.

High performance pipelined multiplier with fast carry-save adder

NASA Technical Reports Server (NTRS)

Wu, Angus

1990-01-01

A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

Gaining Insight Into Femtosecond-scale CMOS Effects using FPGAs

DTIC Science & Technology

2015-03-24

paths or detecting gross path delay faults , but for characterizing subtle aging effects, there is a need to isolate very short paths and detect very...data using COTS FPGAs and novel self-test. Hardware experiments using a 28 nm FPGA demonstrate isolation of small sets of transistors, detection of...hold the static configuration data specifying the LUT function. A set of inverters drive the SRAM contents into a pass-gate multiplexor tree; we

High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor.

PubMed

Ren, Ximing; Connolly, Peter W R; Halimi, Abderrahim; Altmann, Yoann; McLaughlin, Stephen; Gyongy, Istvan; Henderson, Robert K; Buller, Gerald S

2018-03-05

A CMOS single-photon avalanche diode (SPAD) quanta image sensor is used to reconstruct depth and intensity profiles when operating in a range-gated mode used in conjunction with pulsed laser illumination. By designing the CMOS SPAD array to acquire photons within a pre-determined temporal gate, the need for timing circuitry was avoided and it was therefore possible to have an enhanced fill factor (61% in this case) and a frame rate (100,000 frames per second) that is more difficult to achieve in a SPAD array which uses time-correlated single-photon counting. When coupled with appropriate image reconstruction algorithms, millimeter resolution depth profiles were achieved by iterating through a sequence of temporal delay steps in synchronization with laser illumination pulses. For photon data with high signal-to-noise ratios, depth images with millimeter scale depth uncertainty can be estimated using a standard cross-correlation approach. To enhance the estimation of depth and intensity images in the sparse photon regime, we used a bespoke clustering-based image restoration strategy, taking into account the binomial statistics of the photon data and non-local spatial correlations within the scene. For sparse photon data with total exposure times of 75 ms or less, the bespoke algorithm can reconstruct depth images with millimeter scale depth uncertainty at a stand-off distance of approximately 2 meters. We demonstrate a new approach to single-photon depth and intensity profiling using different target scenes, taking full advantage of the high fill-factor, high frame rate and large array format of this range-gated CMOS SPAD array.

Commutated automatic gain control system

NASA Technical Reports Server (NTRS)

Yost, S. R.

1982-01-01

A commutated automatic gain control (AGC) system was designed and built for a prototype Loran C receiver. The receiver uses a microcomputer to control a memory aided phase-locked loop (MAPLL). The microcomputer also controls the input/output, latitude/longitude conversion, and the recently added AGC system. The circuit designed for the AGC is described, and bench and flight test results are presented. The AGC circuit described actually samples starting at a point 40 microseconds after a zero crossing determined by the software lock pulse ultimately generated by a 30 microsecond delay and add network in the receiver front end envelope detector.

Proceedings of the Symposium on Electromagnetic Windows (17th) Held at Georgia Institute of Technology, Engineering Experiment Station, Atlanta, Georgia on 25-27 July 1984. Part 2

DTIC Science & Technology

1984-01-01

and that a residual 1100 quadratic phase error across the aperture remained uncorrected. K --] In Fig.4 the measured far field pattern of the horn...The radio frequency (RF) source consists of a 10-mW klystron at 35 GHz which is phase locked to a stable 5 MHz crystal oscillator . The 35 GHz sig...electronics, the purchased components have worked to specifica- tions, but our earliest work was delayed by phase locked oscillator instabil- ities until

High-frequency heterodyne lock-in thermography (HeLIT): A highly sensitive method to detect early caries

NASA Astrophysics Data System (ADS)

Wang, Fei; Liu, Jun-yan; Yang, Jun-han; Oliullah, Md.; Wang, Xiao-chun; Wang, Yang

2016-10-01

In this letter, a nonlinear photothermal characteristic of dental tissues has been verified by photothermal radiometry at a given frequency with changing of the laser intensity. Subsequently, the high-frequency heterodyne lock-in thermography (HeLIT) scheme has been introduced to overcome shortages of the low infrared camera frame rate and the poor signal-noise ratio. The smooth surface tooth was artificially demineralized at a different time, and then it was detected by HeLIT, Results illustrated that the phase delay increases with the extension of the demineralized treatment time. The comparison experiments between HeLIT and the homodyne lock-in thermography for detecting artificial caries were carried out. Experimental results illustrated that the HeLIT has the merits of high sensitivity and specificity in detecting early caries.

Fractures of the distal tibia treated with polyaxial locking plating.

PubMed

Gao, Hong; Zhang, Chang-Qing; Luo, Cong-Feng; Zhou, Zu-Bin; Zeng, Bing-Fang

2009-03-01

We evaluated the healing rate, complications, and functional outcomes in 32 adult patients with very short metaphyseal fragments in fractures of the distal tibia treated with a polyaxial locking system. The average distance from the distal extent of the fracture to the tibial plafond was 11 mm. All fractures healed and the average time to union was 14 weeks. Six patients (19%) reported occasional local disturbance over the medial malleolus. There were two cases of postoperative superficial infections and evidence of delayed wound healing. Using the American Orthopaedic Foot and Ankle Society ankle score, the average functional score was 87.3 points (of 100 total possible points). Our results show the polyaxial locking plates, which offer more fixation versatility, may be a reasonable treatment option for distal tibia fractures with very short metaphyseal segments.

Reverse distal femoral locking compression plate a salvage option in nonunion of proximal femoral fractures.

PubMed

Dumbre Patil, Sampat S; Karkamkar, Sachin S; Patil, Vaishali S Dumbre; Patil, Shailesh S; Ranaware, Abhijeet S

2016-01-01

When primary fixation of proximal femoral fractures with implants fails, revision osteosynthesis may be challenging. Tracts of previous implants and remaining insufficient bone stock in the proximal femur pose unique problems for the treatment. Intramedullary implants like proximal femoral nail (PFN) or surface implants like Dynamic Condylar Screw (DCS) are few of the described implants for revision surgery. There is no evidence in the literature to choose one implant over the other. We used the reverse distal femur locking compression plate (LCP) of the contralateral side in such cases undergoing revision surgery. This implant has multiple options of fixation in proximal femur and its curvature along the length matches the anterior bow of the femur. We aimed to evaluate the efficacy of this implant in salvage situations. Twenty patients of failed primary proximal femoral fractures who underwent revision surgery with reverse distal femoral locking plate from February 2009 to November 2012 were included in this retrospective study. There were 18 subtrochanteric fractures and two ipsilateral femoral neck and shaft fractures, which exhibited delayed union or nonunion. The study included 14 males and six females. The mean patient age was 43.6 years (range 22-65 years) and mean followup period was 52.1 months (range 27-72 months). Delayed union was considered when clinical and radiological signs of union failed to progress at the end of four months from initial surgery. All fractures exhibited union without any complications. Union was assessed clinically and radiologically. One case of ipsilateral femoral neck and shaft fracture required bone grafting at the second stage for delayed union of the femoral shaft fracture. Reverse distal femoral LCP of the contralateral side can be used as a salvage option for failed fixation of proximal femoral fractures exhibiting nonunion.

A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2014-01-01

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

Backside illuminated CMOS-TDI line scanner for space applications

NASA Astrophysics Data System (ADS)

Cohen, O.; Ben-Ari, N.; Nevo, I.; Shiloah, N.; Zohar, G.; Kahanov, E.; Brumer, M.; Gershon, G.; Ofer, O.

2017-09-01

A new multi-spectral line scanner CMOS image sensor is reported. The backside illuminated (BSI) image sensor was designed for continuous scanning Low Earth Orbit (LEO) space applications including A custom high quality CMOS Active Pixels, Time Delayed Integration (TDI) mechanism that increases the SNR, 2-phase exposure mechanism that increases the dynamic Modulation Transfer Function (MTF), very low power internal Analog to Digital Converters (ADC) with resolution of 12 bit per pixel and on chip controller. The sensor has 4 independent arrays of pixels where each array is arranged in 2600 TDI columns with controllable TDI depth from 8 up to 64 TDI levels. A multispectral optical filter with specific spectral response per array is assembled at the package level. In this paper we briefly describe the sensor design and present some electrical and electro-optical recent measurements of the first prototypes including high Quantum Efficiency (QE), high MTF, wide range selectable Full Well Capacity (FWC), excellent linearity of approximately 1.3% in a signal range of 5-85% and approximately 1.75% in a signal range of 2-95% out of the signal span, readout noise of approximately 95 electrons with 64 TDI levels, negligible dark current and power consumption of less than 1.5W total for 4 bands sensor at all operation conditions .

CMOS-TDI detector technology for reconnaissance application

NASA Astrophysics Data System (ADS)

Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

2014-10-01

The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

A low-noise delta-sigma phase modulator for polar transmitters.

PubMed

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μ m CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of -104 dBc/Hz and -120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

High speed, real-time, camera bandwidth converter

DOEpatents

Bower, Dan E; Bloom, David A; Curry, James R

2014-10-21

Image data from a CMOS sensor with 10 bit resolution is reformatted in real time to allow the data to stream through communications equipment that is designed to transport data with 8 bit resolution. The incoming image data has 10 bit resolution. The communication equipment can transport image data with 8 bit resolution. Image data with 10 bit resolution is transmitted in real-time, without a frame delay, through the communication equipment by reformatting the image data.

Ultrashort, high power, and ultralow noise mode-locked optical pulse generation using quantum-dot semiconductor lasers

NASA Astrophysics Data System (ADS)

Choi, Myoung-Taek

This dissertation explores various aspects and potential of optical pulse generation based on active, passive, and hybrid mode-locked quantum dot semiconductor lasers with target applications such as optical interconnect and high speed signal processing. Design guidelines are developed for the single mode operation with suppressed reflection from waveguide discontinuities. The device fabrication procedure is explained, followed by characteristics of FP laser, SOA, and monolithic two-section devices. Short pulse generation from an external cavity mode-locked QD two-section diode laser is studied. High quality, sub-picosecond (960 fs), high peak power (1.2 W) pulse trains are obtained. The sign and magnitude of pulse chirp were measured for the first time. The role of the self-phase modulation and the linewidth enhancement factor in QD mode-locked lasers is addressed. The noise performance of two-section mode-locked lasers and a SOA-based ring laser was investigated. Significant reduction of the timing jitter under hybrid mode-locked operation was achieved owing to more than one order of magnitude reduction of the linewidth in QD gain media. Ultralow phase noise performance (integrated timing jitter of a few fs at a 10 GHz repetition rate) was demonstrated from an actively mode-locked unidirectional ring laser. These results show that quantum dot mode-locked lasers are strong competitors to conventional semiconductor lasers in noise performance. Finally we demonstrated an opto-electronic oscillator (OEO) and coupled opto-electronic oscillators (COEO) which have the potential for both high purity microwave and low noise optical pulse generation. The phase noise of the COEO is measured by the photonic delay line frequency discriminator method. Based on this study we discuss the prospects of the COEO as a low noise optical pulse source.

A Low Power Linear Phase Programmable Long Delay Circuit.

PubMed

Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, Alexander J

2014-06-01

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

A monolithic K-band phase-locked loop for microwave radar application

NASA Astrophysics Data System (ADS)

Zhou, Guangyao; Ma, Shunli; Li, Ning; Ye, Fan; Ren, Junyan

2017-02-01

A monolithic K-band phase-locked loop (PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator (VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic (CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of ‑0.84 dBm and phase noise of ‑91.92 dBc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm2 without pads under a 1.2 V single voltage supply. Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

A 400 MHz Wireless Neural Signal Processing IC With 625 $\\times$ On-Chip Data Reduction and Reconfigurable BFSK/QPSK Transmitter Based on Sequential Injection Locking.

PubMed

Teng, Kok-Hin; Wu, Tong; Liu, Xiayun; Yang, Zhi; Heng, Chun-Huat

2017-06-01

An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, and feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK transmitter (TX) at MICS/MedRadio band is incorporated to support different data rate requirement. By using an Exponential Component-Polynomial Component (EC-PC) spike processing unit with an incremental principal component analysis (IPCA) engine, the detection of neural spikes with poor SNR is possible while achieving 625× data reduction. For the TX, a dual-channel at 401 MHz and 403.8 MHz are supported by applying sequential injection locked techniques while attaining phase noise of -102 dBc/Hz at 100 kHz offset. From the measurement, error vector magnitude (EVM) of 4.60%/9.55% with power amplifier (PA) output power of -15 dBm is achieved for the QPSK at 8 Mbps and the BFSK at 12.5 kbps. Fabricated in 65 nm CMOS with an active area of 1 mm 2 , the design consumes a total current of 5  ∼ 5.6 mA with a maximum energy efficiency of 0.7 nJ/b.

Experimental observation of different soliton types in a net-normal group-dispersion fiber laser.

PubMed

Feng, Zhongyao; Rong, Qiangzhou; Qiao, Xueguang; Shao, Zhihua; Su, Dan

2014-09-20

Different soliton types are observed in a net-normal group-dispersion fiber laser based on nonlinear polarization rotation for passive mode locking. The proposed laser can deliver a dispersion-managed soliton, typical dissipation solitons, and a quasi-harmonic mode-locked pulse, a soliton bundle, and especially a dark pulse by only appropriately adjusting the linear cavity phase delay bias using one polarization controller at the fixed pump power. These nonlinear waves show different features, including the spectral shapes and time traces. The experimental observations show that the five soliton types could exist in the same laser cavity, which implies that integrable systems, dissipative systems, and dark pulse regimes can transfer and be switched in a passively mode-locked laser. Our studies not only verify the numeral simulation of the different soliton-types formation in a net-normal group-dispersion operation but also provide insight into Ginzburg-Landau equation systems.

Gas spectroscopy system with transmitters and receivers in SiGe BiCMOS for 225-273 GHz

NASA Astrophysics Data System (ADS)

Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

2017-10-01

This paper updates results of our work on gas spectroscopy based on transmitters (TXs) and receivers (RXs) in IHP's 0.13 μm SiGe BiCMOS technology. The improved performance of our system is shown by the absorption spectra of gaseous methanol in the range 241 - 242 GHz at 1.4 Pa, corresponding to an absorption line width of about 1 MHz. The signal-noise ratio (SNR) for the absorption line of methanol at 241.7 GHz is used as measure. The system includes two fractional-n phase-locked loops (PLLs), which allow frequency ramps for the TX and RX, and a superimposed frequency shift keying modulation (FSK) for the TX. Another option includes reference frequency ramps for the PLLs in integer-n mode, which are realized by a direct digital synthesizer (DDS). An SNR of 1515 is observed for the 241.7 GHz absorption line at 1.4 Pa. We extend our single band TX/RX system with the range 238 - 252 GHz to a multi-band system to cover the range 225 - 273 GHz. It is built by combining corresponding pairs of TXs and RXs of three frequency bands in this range. The multi-band operation allows parallel spectra acquisition for these bands. For the TXs and RXs appropriate frequency ramps are generated by their external fractional-n PLL devices.

An ultra-low-power RF transceiver for WBANs in medical applications

NASA Astrophysics Data System (ADS)

Qi, Zhang; Xiaofei, Kuang; Nanjian, Wu

2011-06-01

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks (WBANs) in medical applications is presented. The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The transceiver consists of a main receiver (RX) with an ultra-low-power free-running ring oscillator and a high speed main transmitter (TX) with fast lock-in PLL. A passive wake-up receiver (WuRx) for wake-up function with a high power conversion efficiency (PCE) CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power. The chip is implemented in a 0.18 μm CMOS process. Its core area is 1.6 mm2. The main RX achieves a sensitivity of -55 dBm at a 100 kbps OOK data rate while consuming just 210 μA current from the 1 V power supply. The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is -15 dBm and the PCE is more than 25%.

Phase-locking and coherent power combining of broadband linearly chirped optical waves.

PubMed

Satyan, Naresh; Vasilyev, Arseny; Rakuljic, George; White, Jeffrey O; Yariv, Amnon

2012-11-05

We propose, analyze and demonstrate the optoelectronic phase-locking of optical waves whose frequencies are chirped continuously and rapidly with time. The optical waves are derived from a common optoelectronic swept-frequency laser based on a semiconductor laser in a negative feedback loop, with a precisely linear frequency chirp of 400 GHz in 2 ms. In contrast to monochromatic waves, a differential delay between two linearly chirped optical waves results in a mutual frequency difference, and an acoustooptic frequency shifter is therefore used to phase-lock the two waves. We demonstrate and characterize homodyne and heterodyne optical phase-locked loops with rapidly chirped waves, and show the ability to precisely control the phase of the chirped optical waveform using a digital electronic oscillator. A loop bandwidth of ~ 60 kHz, and a residual phase error variance of < 0.01 rad(2) between the chirped waves is obtained. Further, we demonstrate the simultaneous phase-locking of two optical paths to a common master waveform, and the ability to electronically control the resultant two-element optical phased array. The results of this work enable coherent power combining of high-power fiber amplifiers-where a rapidly chirping seed laser reduces stimulated Brillouin scattering-and electronic beam steering of chirped optical waves.

A front-end readout mixed chip for high-efficiency small animal PET imaging

NASA Astrophysics Data System (ADS)

Ollivier-Henry, N.; Berst, J. D.; Colledani, C.; Hu-Guo, Ch.; Mbow, N. A.; Staub, D.; Guyonnet, J. L.; Hu, Y.

2007-02-01

Today, the main challenge of Positron Emission Tomography (PET) systems dedicated to small animal imaging is to obtain high detection efficiency and a highly accurate localization of radioisotopes. If we focus only on the PET characteristics such as the spatial resolution, its accuracy depends on the design of detector and on the electronics readout system as well. In this paper, we present a new design of such readout system with full custom submicrometer CMOS implementation. The front end chip consists of two main blocks from which the energy information and the time stamp with subnanosecond resolution can be obtained. In our A Multi-Modality Imaging System for Small Animal (AMISSA) PET system design, a matrix of LYSO crystals has to be read at each end by a 64 channels multianode photomultiplier tube. A specific readout electronic has been developed at the Hubert Curien Multidisciplinary Institute (IPHC, France). The architecture of this readout for the energy information detection is composed of a low-noise preamplifier, a CR-RC shaper and an analogue memory. In order to obtain the required dynamic range from 15 to 650 photoelectrons with good linearity, a current mode approach has been chosen for the preamplifier. To detect the signal with a temporal resolution of 1 ns, a comparator with a very low threshold (˜0.3 photoelectron) has been implemented. It gives the time reference of arrival signal coming from the detector. In order to obtain the time coincidence with a temporal resolution of 1 ns, a Time-to-Digital Converter (TDC) based on a Delay-Locked-Loop (DLL) has been designed. The chip is fabricated with AMS 0.35 μm process. The ASIC architecture and some simulation results will be presented in the paper.

NASA Tech Briefs, September 2009

NASA Technical Reports Server (NTRS)

2009-01-01

opics covered include: Filtering Water by Use of Ultrasonically Vibrated Nanotubes; Computer Code for Nanostructure Simulation; Functionalizing CNTs for Making Epoxy/CNT Composites; Improvements in Production of Single-Walled Carbon Nanotubes; Progress Toward Sequestering Carbon Nanotubes in PmPV; Two-Stage Variable Sample-Rate Conversion System; Estimating Transmitted-Signal Phase Variations for Uplink Array Antennas; Board Saver for Use with Developmental FPGAs; Circuit for Driving Piezoelectric Transducers; Digital Synchronizer without Metastability; Compact, Low-Overhead, MIL-STD-1553B Controller; Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM; Differential InP HEMT MMIC Amplifiers Embedded in Waveguides; Improved Aerogel Vacuum Thermal Insulation; Fluoroester Co-Solvents for Low-Temperature Li+ Cells; Using Volcanic Ash to Remove Dissolved Uranium and Lead; High-Efficiency Artificial Photosynthesis Using a Novel Alkaline Membrane Cell; Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays; Micro-Horn Arrays for Ultrasonic Impedance Matching; Improved Controller for a Three-Axis Piezoelectric Stage; Nano-Pervaporation Membrane with Heat Exchanger Generates Medical-Grade Water; Micro-Organ Devices; Nonlinear Thermal Compensators for WGM Resonators; Dynamic Self-Locking of an OEO Containing a VCSEL; Internal Water Vapor Photoacoustic Calibration; Mid-Infrared Reflectance Imaging of Thermal-Barrier Coatings; Improving the Visible and Infrared Contrast Ratio of Microshutter Arrays; Improved Scanners for Microscopic Hyperspectral Imaging; Rate-Compatible LDPC Codes with Linear Minimum Distance; PrimeSupplier Cross-Program Impact Analysis and Supplier Stability Indicator Simulation Model; Integrated Planning for Telepresence With Time Delays; Minimizing Input-to-Output Latency in Virtual Environment; Battery Cell Voltage Sensing and Balancing Using Addressable Transformers; Gaussian and Lognormal Models of Hurricane Gust Factors; Simulation of Attitude and Trajectory Dynamics and Control of Multiple Spacecraft; Integrated Modeling of Spacecraft Touch-and-Go Sampling; Spacecraft Station-Keeping Trajectory and Mission Design Tools; Efficient Model-Based Diagnosis Engine; and DSN Simulator.

Hardware Verification of Laser Noise Cancellation and Gravitational Wave Extraction using Time-Delay Interferometry

NASA Astrophysics Data System (ADS)

Mitryk, Shawn; Mueller, Guido

The Laser Interferometer Space Antenna (LISA) is a space-based modified Michelson interfer-ometer designed to measure gravitational radiation in the frequency range from 30 uHz to 1 Hz. The interferometer measurement system (IMS) utilizes one-way laser phase measurements to cancel the laser phase noise, reconstruct the proof-mass motion, and extract the gravitational wave (GW) induced laser phase modulations in post-processing using a technique called time-delay interferometry (TDI). Unfortunately, there exist few hard-ware verification experiments of the IMS. The University of Florida LISA Interferometry Simulator (UFLIS) is designed to perform hardware-in-the-loop simulations of the LISA interferometry system, modeling the characteris-tics of the LISA mission as accurately as possible. This depends, first, on replicating the laser pre-stabilization by locking the laser phase to an ultra-stable Zerodur cavity length reference using the PDH locking method. Phase measurements of LISA-like photodetector beat-notes are taken using the UF-phasemeter (PM) which can measure the laser BN frequency to within an accuracy of 0.22 uHz. The inter-space craft (SC) laser links including the time-delay due to the 5 Gm light travel time along the LISA arms, the laser Doppler shifts due to differential SC motion, and the GW induced laser phase modulations are simulated electronically using the electronic phase delay (EPD) unit. The EPD unit replicates the laser field propagation between SC by measuring a photodetector beat-note frequency with the UF-phasemeter and storing the information in memory. After the requested delay time, the frequency information is added to a Doppler offset and a GW-like frequency modulation. The signal is then regenerated with the inter-SC laser phase affects applied. Utilizing these components, I will present the first complete TDI simulations performed using the UFLIS. The LISA model is presented along-side the simulation, comparing the generation and measurement of LISA-like signals. Phasemeter measurements are used in post-processing and combined in the linear combinations defined by TDI, thus, canceling the laser phase and phase-lock loop noise to extract the applied GW modulation buried under the noise. Nine order of magnitude common mode laser noise cancellation is achieved at a frequency of 1 mHz and the GW signal is clearly visible after the laser and PLL noise cancellation.

Locking Down the Software Development Environment

DTIC Science & Technology

2014-12-01

OpenSSL code [13]. The OpenSSL software is, as the name implies, open source, a result of many developers coding beginning in 1998 using the C...programming language to build crypto services. OpenSSL is used widely both on the Internet and in firmware [13], further delaying the ability of many

Microchannel plate cross-talk mitigation for spatial autocorrelation measurements

NASA Astrophysics Data System (ADS)

Lipka, Michał; Parniak, Michał; Wasilewski, Wojciech

2018-05-01

Microchannel plates (MCP) are the basis for many spatially resolved single-particle detectors such as ICCD or I-sCMOS cameras employing image intensifiers (II), MCPs with delay-line anodes for the detection of cold gas particles or Cherenkov radiation detectors. However, the spatial characterization provided by an MCP is severely limited by cross-talk between its microchannels, rendering MCP and II ill-suited for autocorrelation measurements. Here, we present a cross-talk subtraction method experimentally exemplified for an I-sCMOS based measurement of pseudo-thermal light second-order intensity autocorrelation function at the single-photon level. The method merely requires a dark counts measurement for calibration. A reference cross-correlation measurement certifies the cross-talk subtraction. While remaining universal for MCP applications, the presented cross-talk subtraction, in particular, simplifies quantum optical setups. With the possibility of autocorrelation measurements, the signal needs no longer to be divided into two camera regions for a cross-correlation measurement, reducing the experimental setup complexity and increasing at least twofold the simultaneously employable camera sensor region.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

PubMed

Yan Lu; Wing-Hung Ki

2014-06-01

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

PubMed Central

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively. PMID:24719578

Electro-optical co-simulation for integrated CMOS photonic circuits with VerilogA.

PubMed

Sorace-Agaskar, Cheryl; Leu, Jonathan; Watts, Michael R; Stojanovic, Vladimir

2015-10-19

We present a Cadence toolkit library written in VerilogA for simulation of electro-optical systems. We have identified and described a set of fundamental photonic components at the physical level such that characteristics of composite devices (e.g. ring modulators) are created organically - by simple instantiation of fundamental primitives. Both the amplitude and phase of optical signals as well as optical-electrical interactions are simulated. We show that the results match other simulations and analytic solutions that have previously been compared to theory for both simple devices, such as ring resonators, and more complicated devices and systems such as single-sideband modulators, WDM links and Pound Drever Hall Locking loops. We also illustrate the capability of such toolkit for co-simulation with electronic circuits, which is a key enabler of the electro-optic system development and verification.

Tone-assisted time delay interferometry on GRACE Follow-On

NASA Astrophysics Data System (ADS)

Francis, Samuel P.; Shaddock, Daniel A.; Sutton, Andrew J.; de Vine, Glenn; Ware, Brent; Spero, Robert E.; Klipstein, William M.; McKenzie, Kirk

2015-07-01

We have demonstrated the viability of using the Laser Ranging Interferometer on the Gravity Recovery and Climate Experiment Follow-On (GRACE-FO) space mission to test key aspects of the interspacecraft interferometry proposed for detecting gravitational waves. The Laser Ranging Interferometer on GRACE-FO will be the first demonstration of interspacecraft interferometry. GRACE-FO shares many similarities with proposed space-based gravitational wave detectors based on the Laser Interferometer Space Antenna (LISA) concept. Given these similarities, GRACE-FO provides a unique opportunity to test novel interspacecraft interferometry techniques that a LISA-like mission will use. The LISA Experience from GRACE-FO Optical Payload (LEGOP) is a project developing tests of arm locking and time delay interferometry (TDI), two frequency stabilization techniques, that could be performed on GRACE-FO. In the proposed LEGOP TDI demonstration one GRACE-FO spacecraft will have a free-running laser while the laser on the other spacecraft will be locked to a cavity. It is proposed that two one-way interspacecraft phase measurements will be combined with an appropriate delay in order to produce a round-trip, dual one-way ranging (DOWR) measurement independent of the frequency noise of the free-running laser. This paper describes simulated and experimental tests of a tone-assisted TDI ranging (TDIR) technique that uses a least-squares fitting algorithm and fractional-delay interpolation to find and implement the delays needed to form the DOWR TDI combination. The simulation verifies tone-assisted TDIR works under GRACE-FO conditions. Using simulated GRACE-FO signals the tone-assisted TDIR algorithm estimates the time-varying interspacecraft range with a rms error of ±0.2 m , suppressing the free-running laser frequency noise by 8 orders of magnitude. The experimental results demonstrate the practicability of the technique, measuring the delay at the 6 ns level in the presence of a significant displacement signal.

Improvements to a five-phase ABS algorithm for experimental validation

NASA Astrophysics Data System (ADS)

Gerard, Mathieu; Pasillas-Lépine, William; de Vries, Edwin; Verhaegen, Michel

2012-10-01

The anti-lock braking system (ABS) is the most important active safety system for passenger cars. Unfortunately, the literature is not really precise about its description, stability and performance. This research improves a five-phase hybrid ABS control algorithm based on wheel deceleration [W. Pasillas-Lépine, Hybrid modeling and limit cycle analysis for a class of five-phase anti-lock brake algorithms, Veh. Syst. Dyn. 44 (2006), pp. 173-188] and validates it on a tyre-in-the-loop laboratory facility. Five relevant effects are modelled so that the simulation matches the reality: oscillations in measurements, wheel acceleration reconstruction, brake pressure dynamics, brake efficiency changes and tyre relaxation. The time delays in measurement and actuation have been identified as the main difficulty for the initial algorithm to work in practice. Three methods are proposed in order to deal with these delays. It is verified that the ABS limit cycles encircle the optimal braking point, without assuming any tyre parameter being a priori known. The ABS algorithm is compared with the commercial algorithm developed by Bosch.

CMOS time-to-digital converter based on a pulse-mixing scheme

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Liu, Keng-Chih; Chen, Guan-Hong

2014-11-01

This paper proposes a new pulse-mixing scheme utilizing both pulse-shrinking and pulse-stretching mechanisms to improve the performance of time-to-digital converters (TDCs). The temporal resolution of the conventional pulse-shrinking mechanism is determined by the size ratio between homogeneous and inhomogeneous elements. The proposed scheme which features double-stage operation derives its resolution according to the time difference between pulse-shrinking and pulse-stretching amounts. Thus, it can achieve greater immunity against temperature and ambient variations than that of the single-stage scheme. The circuit area also can be reduced by the proposed pulse-mixing scheme. In addition, this study proposes an improved cyclic delay line to eliminate the undesirable shift in the temporal resolution successfully. Therefore, the effective resolution can be controlled completely by the pulse-mixing unit to improve accuracy. The proposed TDC composed of only one cyclic delay line and one counter is fabricated in a TSMC CMOS 0.35-μm DPQM process. The chip core occupies an extremely small area of 0.02 mm2, which is the best among the related works. The experimental result shows that an effective resolution of around 53 ps within ±13% variation over a 0-100 °C temperature range is achieved. The power consumption is 90 μW at a sample rate of 1000 samples/s. In addition to the reduced area, the proposed TDC circuit achieves its resolution with less thermal-sensitivity and better fluctuations caused by process variations.

A class of optimum digital phase locked loops

NASA Technical Reports Server (NTRS)

Kumar, R.; Hurd, W. J.

1986-01-01

This paper presents a class of optimum digital filters for digital phase locked loops, for the important case in which the maximum update rate of the loop filter and numerically controlled oscillator (NCO) is limited. This case is typical when the loop filter is implemented in a microprocessor. In these situations, pure delay is encountered in the loop transfer function and thus the stability and gain margin of the loop are of crucial interest. The optimum filters designed for such situations are evaluated in terms of their gain margin for stability, dynamic error, and steady-state error performance. For situations involving considerably high phase dynamics an adaptive and programmable implementation is also proposed to obtain an overall optimum strategy.

Palaeomagnetic dating method accounting for post-depositional remanence and its application to geomagnetic field modelling

NASA Astrophysics Data System (ADS)

Nilsson, A.; Suttie, N.

2016-12-01

Sedimentary palaeomagnetic data may exhibit some degree of smoothing of the recorded field due to the gradual processes by which the magnetic signal is `locked-in' over time. Here we present a new Bayesian method to construct age-depth models based on palaeomagnetic data, taking into account and correcting for potential lock-in delay. The age-depth model is built on the widely used "Bacon" dating software by Blaauw and Christen (2011, Bayesian Analysis 6, 457-474) and is designed to combine both radiocarbon and palaeomagnetic measurements. To our knowledge, this is the first palaeomagnetic dating method that addresses the potential problems related post-depositional remanent magnetisation acquisition in age-depth modelling. Age-depth models, including site specific lock-in depth and lock-in filter function, produced with this method are shown to be consistent with independent results based on radiocarbon wiggle match dated sediment sections. Besides its primary use as a dating tool, our new method can also be used specifically to identify the most likely lock-in parameters for a specific record. We explore the potential to use these results to construct high-resolution geomagnetic field models based on sedimentary palaeomagnetic data, adjusting for smoothing induced by post-depositional remanent magnetisation acquisition. Potentially, this technique could enable reconstructions of Holocene geomagnetic field with the same amplitude of variability observed in archaeomagnetic field models for the past three millennia.

Design and Implementation of an RTK-Based Vector Phase Locked Loop

PubMed Central

Shafaati, Ahmad; Lin, Tao; Broumandan, Ali; Lachapelle, Gérard

2018-01-01

This paper introduces a novel double-differential vector phase-locked loop (DD-VPLL) for Global Navigation Satellite Systems (GNSS) that leverages carrier phase position solutions as well as base station measurements in the estimation of rover tracking loop parameters. The use of double differencing alleviates the need for estimating receiver clock dynamics and atmospheric delays; therefore, the navigation filter consists of the baseline dynamic states only. It is shown that using vector processing for carrier phase tracking leads to a significant enhancement in the receiver sensitivity compared to using the conventional scalar-based tracking loop (STL) and vector frequency locked loop (VFLL). The sensitivity improvement of 8 to 10 dB compared to STL, and 7 to 8 dB compared to VFLL, is obtained based on the test cases reported in the paper. Also, an increased probability of ambiguity resolution in the proposed method results in better availability for real time kinematic (RTK) applications. PMID:29533994

Rayleigh-enhanced attosecond sum-frequency polarization beats via twin color-locking noisy lights

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang Yanpeng; Li Long; Ma Ruiqiong

2005-07-15

Based on color-locking noisy field correlation, a time-delayed method is proposed to suppress the thermal effect, and the ultrafast longitudinal relaxation time can be measured even in an absorbing medium. One interesting feature in field-correlation effects is that Rayleigh-enhanced four-wave mixing (RFWM) with color-locking noisy light exhibits spectral symmetry and temporal asymmetry with no coherence spike at {tau}=0. Due to the interference between the Rayleigh-resonant signal and the nonresonant background, RFWM exhibits hybrid radiation-matter detuning with terahertz damping oscillations. The subtle Markovian high-order correlation effects have been investigated in the homodyne- or heterodyne-detected Rayleigh-enhanced attosecond sum-frequency polarization beats (RASPBs). Analyticmore » closed forms of fourth-order Markovian stochastic correlations are characterized for homodyne (quadratic) and heterodyne (linear) detection, respectively. Based on the polarization interference between two four-wave mixing processes, the phase-sensitive detection of RASPBs has also been used to obtain the real and imaginary parts of the Rayleigh resonance.« less

Wideband and high-gain frequency stabilization of a 100-W injection-locked Nd:YAG laser for second-generation gravitational wave detectors.

PubMed

Ohmae, Noriaki; Moriwaki, Shigenori; Mio, Norikatsu

2010-07-01

Second-generation gravitational wave detectors require a highly stable laser with an output power greater than 100 W to attain their target sensitivity. We have developed a frequency stabilization system for a 100-W injection-locked Nd:YAG (yttrium aluminum garnet) laser. By placing an external wideband electro-optic modulator used as a fast-frequency actuator in the optical path of the slave output, we can circumvent a phase delay in the frequency control loop originating from the pole of an injection-locked slave cavity. Thus, we have developed an electro-optic modulator made of a MgO-doped stoichiometric LiNbO(3) crystal. Using this modulator, we achieve a frequency control bandwidth of 800 kHz and a control gain of 180 dB at 1 kHz. These values satisfy the requirement for a laser frequency control loop in second-generation gravitational wave detectors.

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

NASA Astrophysics Data System (ADS)

Li, Hangbiao; Zhang, Bo; Luo, Ping; Liao, Pengfei; Liu, Junjie; Li, Zhaoji

2015-03-01

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.

A 2.4 GHz ULP reconfigurable asymmetric transceiver for single-chip wireless neural recording IC.

PubMed

Tan, Jun; Liew, Wen-Sin; Heng, Chun-Huat; Lian, Yong

2014-08-01

This paper presents a 2.4 GHz ultra-low-power (ULP) reconfigurable asymmetric transceiver and demonstrates its application in wireless neural recording. Fabricated in 0.13 μm CMOS technology, the transceiver is optimized for sensor-gateway communications within a star-shaped network, and supports both the sensor and gateway operation modes. Binary phase-shift keying (BPSK) modulation with high data rate (DR) of 1 to 8 Mbps is used in the uplink from sensor to gateway, while on-off keying (OOK) modulation with low DR of 100 kbps is adopted in the downlink. A fully integrated Class-E PA with moderate output power has also been proposed and achieves power efficiency of 53%. To minimize area usage, inductor reuse is adopted between PA and LNA, and eliminates the need of lossy T/R switch in the RF signal path. When used as sensor, the transceiver with frequency locked phase-locked loop (PLL) achieves TX (BPSK) power efficiency of 28% @ 0 dBm output power, and RX (OOK) sensitivity of -80 dBm @ 100 kbps while consuming only 780 μW . When configured as gateway, the transceiver achieves sensitivity levels of -92, -84.5, and -77 dBm for 1, 5, and 8 Mbps BPSK, respectively. The transceiver is integrated with an 8-channel neural recording front-end, and neural signals from a rat are captured to verify the system functionality.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Compact and low-cost THz QTDS system.

PubMed

Probst, Thorsten; Rehn, Arno; Koch, Martin

2015-08-24

We present a terahertz quasi time domain spectroscopy (QTDS) system setup which is improved regarding cost and compactness. The diode laser is mounted directly onto the optical delay line, making the optical setup more compact. The system is operated using a Raspberry Pi and an additional sound card. This combination replaces the desktop/laptop computer, the lock-in-amplifier, the stage controller and the signal generator. We examined not only a commercially available stepper motor driven delay line, but also the repurposed internal mechanics from a DVD drive. We characterize the performance of the new system concept.

LISA Long-Arm Interferometry

NASA Technical Reports Server (NTRS)

Thorpe, James I.

2009-01-01

An overview of LISA Long-Arm Interferometry is presented. The contents include: 1) LISA Interferometry; 2) Constellation Design; 3) Telescope Design; 4) Constellation Acquisition; 5) Mechanisms; 6) Optical Bench Design; 7) Phase Measurement Subsystem; 8) Phasemeter Demonstration; 9) Time Delay Interferometry; 10) TDI Limitations; 11) Active Frequency Stabilization; 12) Spacecraft Level Stabilization; 13) Arm-Locking; and 14) Embarassment of Riches.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

NASA Astrophysics Data System (ADS)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

Clock recovery PLL with gated PFD for NRZ ON-OFF Modulated Signals in a retinal implant system.

PubMed

Brendler, Christian; Aryan, Naser Pour; Rieger, Viola; Rothermel, Albrecht

2013-01-01

A Clock Recovery Phase Locked Loop with Gated Phase Frequency Detector (GPLL) for NRZ ON-OFF Modulated Signals with low data transmission rates for an inductively powered subretinal implant system is presented. Low data transmission rate leads to a long absence of inductive powering in the system when zeros are transmitted. Consequently there is no possibility to extract any clock in these pauses, thus the digital circuitry can not work any more. Compared to a commonly used PLL for clock extraction, no certain amount of data transitions is needed. This is achieved by having two operating modes. In one mode the GPLL tracks the HF input signal. In the other, the GPLL is an adjustable oscillator oscillating at the last used frequency. The proposed GPLL is fabricated and measured using a 350 nm High Voltage CMOS technology.

A dynamically reconfigurable multi-functional PLL for SRAM-based FPGA in 65nm CMOS technology

NASA Astrophysics Data System (ADS)

Yang, Mingqian; Chen, Lei; Li, Xuewu; Zhang, Yanlong

2018-04-01

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts' running or halting the FPGA device.

A linearization time-domain CMOS smart temperature sensor using a curvature compensation oscillator.

PubMed

Chen, Chun-Chi; Chen, Hao-Wen

2013-08-28

This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a -40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of -1.2 to 0.2 °C is achieved in an operation range of -40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

NASA Astrophysics Data System (ADS)

Chen, R. M.; Mahatme, N. N.; Diggins, Z. J.; Wang, L.; Zhang, E. X.; Chen, Y. P.; Liu, Y. N.; Narasimham, B.; Witulski, A. F.; Bhuva, B. L.; Fleetwood, D. M.

2017-08-01

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.

Time delay in the Kuramoto model of coupled-phase oscillators

NASA Astrophysics Data System (ADS)

Yeung, Man Kit Stephen

1999-10-01

The Kuramoto model is a mean-field model of coupled phase oscillators with distributed natural frequencies. It was proposed to study collective synchronization in large systems of nonlinear oscillators. Here we generalize this model to allow time-delayed interactions. Despite the delay, synchronization is still possible. We derive exact stability conditions for the incoherent state, and for synchronized states and clustering states in the special case of noiseless identical oscillators. We also study the bifurcations of these states. We find that the incoherent state loses stability in a Hopf bifurcation. In the absence of noise, this leads to partial synchrony, where some oscillators are entrained to a common frequency. New phenomena caused by the delay include multistability among synchronization, incoherence, and clustering; and unsteady solutions with time-dependent order parameters. The experimental implications of the model are discussed for populations of chirping crickets, where the finite speed of sound causes communication delays, and for physical systems such as coupled phase- locked loops, lasers, and communication satellites.

Broadband pump-probe spectroscopy at 20-MHz modulation frequency.

PubMed

Preda, Fabrizio; Kumar, Vikas; Crisafi, Francesco; Figueroa Del Valle, Diana Gisell; Cerullo, Giulio; Polli, Dario

2016-07-01

We introduce an innovative high-sensitivity broadband pump-probe spectroscopy system, based on Fourier-transform detection, operating at 20-MHz modulation frequency. A common-mode interferometer employing birefringent wedges creates two phase-locked delayed replicas of the broadband probe pulse, interfering at a single photodetector. A single-channel lock-in amplifier demodulates the interferogram, whose Fourier transform provides the differential transmission spectrum. Our approach combines broad spectral coverage with high sensitivity, due to high-frequency modulation and detection. We demonstrate its performances by measuring two-dimensional differential transmission maps of a carbon nanotubes sample, simultaneously acquiring the signal over the entire 950-1350 nm range with 2.7·10^-6  rms noise over 1.5 s integration time.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

Reaction Times to Consecutive Automation Failures: A Function of Working Memory and Sustained Attention.

PubMed

Jipp, Meike

2016-12-01

This study explored whether working memory and sustained attention influence cognitive lock-up, which is a delay in the response to consecutive automation failures. Previous research has demonstrated that the information that automation provides about failures and the time pressure that is associated with a task influence cognitive lock-up. Previous research has also demonstrated considerable variability in cognitive lock-up between participants. This is why individual differences might influence cognitive lock-up. The present study tested whether working memory-including flexibility in executive functioning-and sustained attention might be crucial in this regard. Eighty-five participants were asked to monitor automated aircraft functions. The experimental manipulation consisted of whether or not an initial automation failure was followed by a consecutive failure. Reaction times to the failures were recorded. Participants' working-memory and sustained-attention abilities were assessed with standardized tests. As expected, participants' reactions to consecutive failures were slower than their reactions to initial failures. In addition, working-memory and sustained-attention abilities enhanced the speed with which participants reacted to failures, more so with regard to consecutive than to initial failures. The findings highlight that operators with better working memory and sustained attention have small advantages when initial failures occur, but their advantages increase across consecutive failures. The results stress the need to consider personnel selection strategies to mitigate cognitive lock-up in general and training procedures to enhance the performance of low ability operators. © 2016, Human Factors and Ergonomics Society.

CNES developments of key detection technologies to prepare next generation focal planes for high resolution Earth observation

NASA Astrophysics Data System (ADS)

Materne, A.; Virmontois, C.; Bardoux, A.; Gimenez, T.; Biffi, J. M.; Laubier, D.; Delvit, J. M.

2014-10-01

This paper describes the activities managed by CNES (French National Space Agency) for the development of focal planes for next generation of optical high resolution Earth observation satellites, in low sun-synchronous orbit. CNES has launched a new programme named OTOS, to increase the level of readiness (TRL) of several key technologies for high resolution Earth observation satellites. The OTOS programme includes several actions in the field of detection and focal planes: a new generation of CCD and CMOS image sensors, updated analog front-end electronics and analog-to-digital converters. The main features that must be achieved on focal planes for high resolution Earth Observation, are: readout speed, signal to noise ratio at low light level, anti-blooming efficiency, geometric stability, MTF and line of sight stability. The next steps targeted are presented in comparison to the in-flight measured performance of the PLEIADES satellites launched in 2011 and 2012. The high resolution panchromatic channel is still based upon Backside illuminated (BSI) CCDs operated in Time Delay Integration (TDI). For the multispectral channel, the main evolution consists in moving to TDI mode and the competition is open with the concurrent development of a CCD solution versus a CMOS solution. New CCDs will be based upon several process blocks under evaluation on the e2v 6 inches BSI wafer manufacturing line. The OTOS strategy for CMOS image sensors investigates on one hand custom TDI solutions within a similar approach to CCDs, and, on the other hand, investigates ways to take advantage of existing performance of off-the-shelf 2D arrays CMOS image sensors. We present the characterization results obtained from test vehicles designed for custom TDI operation on several CIS technologies and results obtained before and after radiation on snapshot 2D arrays from the CMOSIS CMV family.

Free-running waveform characterization using a delay-time tunable laser based delay-line-free electro-optic sampling oscilloscope

NASA Astrophysics Data System (ADS)

Lin, Gong-Ru

2002-12-01

We develop a delay-line-free and frequency traceable electro-optic sampling oscilloscope by use of a digital phase-locked loop phase shifter (PLL-PS) controlled delay-time-tunable gain-switched laser diode (GSLD). The home-made voltage-controllable PLL-PS exhibits a linear transfer function with ultra-wide phase shifting range of ±350° and tuning error of <±5%, which benefits the advantages of frequency tracking to free-running signals with suppressed timing-jitter. The maximum delay-time of PLL-PS controlled GSLD is up to 1.95 periods by changing the controlling voltage ( VREF) from -3.5 to 3.5 V, which corresponds to 3.9 ns at repetition frequency of 500 MHz. The tuning responsivity and resolution are about 0.56 ns/V and 0.15˜0.2 ps, respectively. The maximum delay-time switching bandwidth of 100 Hz is determined under the control of a saw-tooth modulated VREF function. The waveform sampling of microwave PECL signals generated from a free-running digital frequency divider is performed with acceptable measuring deviation.

Reference-free, high-resolution measurement method of timing jitter spectra of optical frequency combs

PubMed Central

Kwon, Dohyeon; Jeon, Chan-Gi; Shin, Junho; Heo, Myoung-Sun; Park, Sang Eon; Song, Youjian; Kim, Jungwon

2017-01-01

Timing jitter is one of the most important properties of femtosecond mode-locked lasers and optical frequency combs. Accurate measurement of timing jitter power spectral density (PSD) is a critical prerequisite for optimizing overall noise performance and further advancing comb applications both in the time and frequency domains. Commonly used jitter measurement methods require a reference mode-locked laser with timing jitter similar to or lower than that of the laser-under-test, which is a demanding requirement for many laser laboratories, and/or have limited measurement resolution. Here we show a high-resolution and reference-source-free measurement method of timing jitter spectra of optical frequency combs using an optical fibre delay line and optical carrier interference. The demonstrated method works well for both mode-locked oscillators and supercontinua, with 2 × 10−9 fs2/Hz (equivalent to −174 dBc/Hz at 10-GHz carrier frequency) measurement noise floor. The demonstrated method can serve as a simple and powerful characterization tool for timing jitter PSDs of various comb sources including mode-locked oscillators, supercontinua and recently emerging Kerr-frequency combs; the jitter measurement results enabled by our method will provide new insights for understanding and optimizing timing noise in such comb sources. PMID:28102352

Percutaneous locking plates for fractures of the distal tibia: our experience and a review of the literature.

PubMed

Ahmad, Mudussar Abrar; Sivaraman, Alagappan; Zia, Ahmed; Rai, Amarjit; Patel, Amratlal D

2012-02-01

Distal tibial metaphyseal fractures pose many complexities. This study assessed the outcomes of distal tibial fractures treated with medial locking plates. Eighteen patients were selected based on the fracture pattern and classified using the AO classification and stabilized with an AO medial tibial locking plate. Time to fracture union, complications, and outcomes were assessed with the American Orthopedic Foot and Ankle Society Ankle score at 12 months. Sixteen of the 18 patients achieved fracture union, with 1 patient lost to follow-up. Twelve fractures united within 24 weeks, with an average union time of 23.1 weeks. Three delayed unions, two at 28 weeks and one at 56 weeks. The average time to union was 32 weeks in the smokers and 15.3 weeks in the nonsmokers. Five of the 18 patients (27%) developed complications. One superficial wound infection, and one chronic wound infection, resulting in nonunion at 56 weeks, requiring revision. Two patients required plate removal, one after sustaining an open fracture at the proximal end of the plate 6 months after surgery (postfracture union)and the other for painful hardware. One patient had implant failure of three proximal diaphyseal locking screws at the screwhead/neck junction, but successful fracture union. The average American Orthopedic Foot and Ankle Society ankle score was 88.8 overall, and 92.1 in fractures that united within 24 weeks. Distal tibial locking plates have high fracture union rates, minimum soft tissue complications, and good functional outcomes. The literature shows similar fracture union and complication rates in locking and nonlocking plates. Copyright © 2012 by Lippincott Williams & Wilkins

Dynamic locked plating for fixation of distal femur fractures using near- cortical over-drilling: Preliminary results of a prospective observational study.

PubMed

Galal, Sherif

2017-01-01

Nonunion after locked plating of distal femur fractures is not uncommon. Authors wanted to assess if "Dynamic" locked plating using near-cortex over-Drilling technique would provide a mechanical environment the promotes callus formation, thereby avoiding non-union encountered when applying locked plates with the conventional method. This study was conducted at an academic Level 1 Trauma Center. This is a prospective study conducted from November 2015 to November 2016. Follow-up was 10 months on average (ranging from 8 to 12 months). The study included 20 patients with 20 fractures (13 males, 7 females). The average patients' age was 41.2 years (18-64 years). According to the Müller AO classification of distal femur fractures (33A-C) there were 15 cases with extra-articular fractures (AO 33A), 5 patients with intra-articular fractures (AO 33C). Dynamic Locked plating using near-cortical over-drilling technique was done for all patients. Two blinded observers assessed callus score on 6-week radiographs using a 4-point ordinal scale. A 2-tailed t -test. Two-way mixed intra-class correlation testing was performed to determine reliability of the callus measurements by the 2 observers. All patients achieved union, time to union was 13.4 weeks on average (range form 8-24 weeks). Delayed union was observed in 2 patients. The average callus score for fractures was 1.8 (SD 0.6). All fractures united in alignment except 1 fracture which united in valgus malalignment, the deformity was appreciated in the postoperative radiographs. No wound related complications, no loss of reduction, no catastrophic implant failure or screw breakage were detected. Dynamic locked plating using near-cortex over-drilling is a simple technique that uses standard locked plates that promotes callus formation when used for fixing distal femur fractures.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Phase noise analysis of a 10-GHz optical injection-locked vertical-cavity surface-emitting laser-based optoelectronic oscillator

NASA Astrophysics Data System (ADS)

Coronel, Juan; Varón, Margarita; Rissons, Angélique

2016-09-01

The optical injection locking (OIL) technique is proposed to reduce the phase noise of a carrier generated for a vertical-cavity surface-emitting laser (VCSEL)-based optoelectronic oscillator. The OIL technique permits the enhancement of the VCSEL direct modulation bandwidth as well as the stabilization of the optical noise of the laser. A 2-km delay line, 10-GHz optical injection-locked VCSEL-based optoelectronic oscillator (OILVBO) was implemented. The internal noise sources of the optoelectronic oscillator components were characterized and analyzed to understand the noise conversion of the system into phase noise in the oscillator carrier. The implemented OILVBO phase noise was -105.7 dBc/Hz at 10 kHz from the carrier; this value agrees well with the performed simulated analysis. From the computed and measured phase noise curves, it is possible to infer the noise processes that take place inside the OILVBO. As a second measurement of the oscillation quality, a time-domain analysis was done through the Allan's standard deviation measurement, reported for first time for an optoelectronic oscillator using the OIL technique.

Repetition rate multiplication of frequency comb using all-pass fiber resonator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Lijun; Yang, Honglei; Zhang, Hongyuan

2016-09-15

We propose a stable method for repetition rate multiplication of a 250-MHz Er-fiber frequency comb by a phase-locked all-pass fiber ring resonator, whose phase-locking configuration is simple. The optical path length of the fiber ring resonator is automatically controlled to be accurately an odd multiple of half of the original cavity length using an electronical phase-locking unit with an optical delay line. As for shorter cavity length of the comb, high-order odd multiple is preferable. Because the power loss depends only on the net-attenuation of the fiber ring resonator, the energetic efficiency of the proposed method is high. The inputmore » and output optical spectrums show that the spectral width of the frequency comb is clearly preserved. Besides, experimental results show less pulse intensity fluctuation and 35 dB suppression ratio of side-modes while providing a good long-term and short-term frequency stability. Higher-order repetition rate multiplication to several GHz can be obtained by using several fiber ring resonators in cascade configuration.« less

Locked-mode avoidance and recovery without external momentum input

NASA Astrophysics Data System (ADS)

Delgado-Aparicio, L.; Gates, D. A.; Wolfe, S.; Rice, J. E.; Gao, C.; Wukitch, S.; Greenwald, M.; Hughes, J.; Marmar, E.; Scott, S.

2014-10-01

Error-field-induced locked-modes (LMs) have been studied in C-Mod at ITER toroidal fields without NBI fueling and momentum input. The use of ICRH heating in synch with the error-field ramp-up resulted in a successful delay of the mode-onset when PICRH > 1 MW and a transition into H-mode when PICRH > 2 MW. The recovery experiments consisted in applying ICRH power during the LM non-rotating phase successfully unlocking the core plasma. The ``induced'' toroidal rotation was in the counter-current direction, restoring the direction and magnitude of the toroidal flow before the LM formation, but contrary to the expected Rice-scaling in the co-current direction. However, the LM occurs near the LOC/SOC transition where rotation reversals are commonly observed. Once PICRH is turned off, the core plasma ``locks'' at later times depending on the evolution of ne and Vt. This work was performed under US DoE contracts including DE-FC02-99ER54512 and others at MIT and DE-AC02-09CH11466 at PPPL.

Time Difference Amplifier with Robust Gain Using Closed-Loop Control

NASA Astrophysics Data System (ADS)

Nakura, Toru; Mandai, Shingo; Ikeda, Makoto; Asada, Kunihiro

This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

Backside illuminated CMOS-TDI line scan sensor for space applications

NASA Astrophysics Data System (ADS)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Impact of Partial Time Delay on Temporal Dynamics of Watts-Strogatz Small-World Neuronal Networks

NASA Astrophysics Data System (ADS)

Yan, Hao; Sun, Xiaojuan

2017-06-01

In this paper, we mainly discuss effects of partial time delay on temporal dynamics of Watts-Strogatz (WS) small-world neuronal networks by controlling two parameters. One is the time delay τ and the other is the probability of partial time delay pdelay. Temporal dynamics of WS small-world neuronal networks are discussed with the aid of temporal coherence and mean firing rate. With the obtained simulation results, it is revealed that for small time delay τ, the probability pdelay could weaken temporal coherence and increase mean firing rate of neuronal networks, which indicates that it could improve neuronal firings of the neuronal networks while destroying firing regularity. For large time delay τ, temporal coherence and mean firing rate do not have great changes with respect to pdelay. Time delay τ always has great influence on both temporal coherence and mean firing rate no matter what is the value of pdelay. Moreover, with the analysis of spike trains and histograms of interspike intervals of neurons inside neuronal networks, it is found that the effects of partial time delays on temporal coherence and mean firing rate could be the result of locking between the period of neuronal firing activities and the value of time delay τ. In brief, partial time delay could have great influence on temporal dynamics of the neuronal networks.

Homodyne Phase-Shift-Keying Systems: Past Challenges and Future Opportunities

NASA Astrophysics Data System (ADS)

Kazovsky, Leonid G.; Kalogerakis, Georgios; Shaw, Wei-Tao

2006-12-01

Homodyne phase-shift-keying systems can achieve the best receiver sensitivity and the longest transmission distance among all optical communication systems. This paper reviews recent research efforts in the field and examines future possibilities that might lead toward potential practical use of these systems. Additionally, phase estimation techniques based on feed-forward phase recovery and digital delay-lock loop approaches are examined, simulated, and compared.

Financial Crisis Now Striking Home for School Districts: Project Delays, Worries About Cash Flow Result of Tight Credit Markets

ERIC Educational Resources Information Center

Davis, Michelle R.

2008-01-01

This article reports that the crisis besetting U.S. and world financial markets is hitting school districts hard, as they struggle to float the bonds needed for capital projects, borrow money to ensure cash flow, and get access to investment funds locked up in troubled institutions. Some schools districts depend heavily on borrowed money to pay…

Hybrid optical and electronic laser locking using slow light due to spectral holes

NASA Astrophysics Data System (ADS)

Tay, Jian Wei; Farr, Warrick G.; Ledingham, Patrick M.; Korystov, Dmitry; Longdell, Jevon J.

2013-06-01

We report on a narrow linewidth laser diode system that is stabilized using both optical and electronic feedback to a spectral hole in cryogenic Tm:YAG. The large group delay of the spectral hole leads to a laser with very low phase noise. The laser has proved useful for quantum optics and sensing applications involving cryogenic rare-earth-ion dopants.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Irrelevant singletons in visual search do not capture attention but can produce nonspatial filtering costs.

PubMed

Wykowska, Agnieszka; Schubö, Anna

2011-03-01

It is not clear how salient distractors affect visual processing. The debate concerning the issue of whether irrelevant salient items capture spatial attention [e.g., Theeuwes, J., Atchley, P., & Kramer, A. F. On the time course of top-down and bottom-up control of visual attention. In S. Monsell & J. Driver (Eds.), Attention and performance XVIII: Control of cognitive performance (pp. 105-124). Cambridge, MA: MIT Press, 2000] or produce only nonspatial interference in the form of, for example, filtering costs [Folk, Ch. L., & Remington, R. Top-down modulation of preattentive processing: Testing the recovery account of contingent capture. Visual Cognition, 14, 445-465, 2006] has not yet been settled. The present ERP study examined deployment of attention in visual search displays that contained an additional irrelevant singleton. Display-locked N2pc showed that attention was allocated to the target and not to the irrelevant singleton. However, the onset of the N2pc to the target was delayed when the irrelevant singleton was presented in the opposite hemifield relative to the same hemifield. Thus, although attention was successfully focused on the target, the irrelevant singleton produced some interference resulting in a delayed allocation of attention to the target. A subsequent probe discrimination task allowed for locking ERPs to probe onsets and investigating the dynamics of sensory gain control for probes appearing at relevant (target) or irrelevant (singleton distractor) positions. Probe-locked P1 showed sensory gain for probes positioned at the target location but no such effect for irrelevant singletons in the additional singleton condition. Taken together, the present data support the claim that irrelevant singletons do not capture attention. If they produce any interference, it is rather due to nonspatial filtering costs.

Locking plate fixation in distal metaphyseal tibial fractures: series of 79 patients.

PubMed

Gupta, Rakesh K; Rohilla, Rajesh Kumar; Sangwan, Kapil; Singh, Vijendra; Walia, Saurav

2010-12-01

Open reduction and internal fixation in distal tibial fractures jeopardises fracture fragment vascularity and often results in soft tissue complications. Minimally invasive osteosynthesis, if possible, offers the best possible option as it permits adequate fixation in a biological manner. Seventy-nine consecutive adult patients with distal tibial fractures, including one patient with a bilateral fracture of the distal tibia, treated with locking plates, were retrospectively reviewed. The 4.5-mm limited-contact locking compression plate (LC-LCP) was used in 33 fractures, the metaphyseal LCP in 27 fractures and the distal medial tibial LCP in the remaining 20 fractures. Fibula fixation was performed in the majority of comminuted fractures (n = 41) to maintain the second column of the ankle so as to achieve indirect reduction and to prevent collapse of the fracture. There were two cases of delayed wound breakdown in fractures fixed with the 4.5-mm LC-LCP. Five patients required primary bone grafting and three patients required secondary bone grafting. All cases of delayed union (n = 7) and nonunion (n = 3) were observed in cases where plates were used in bridge mode. Minimally invasive plate osteosynthesis (MIPO) with LCP was observed to be a reliable method of stabilisation for these fractures. Peri-operative docking of fracture ends may be a good option in severely impacted fractures with gap. The precontoured distal medial tibial LCP was observed to be a better tolerated implant in comparison to the 4.5-mm LC-LCP or metaphyseal LCP with respect to complications of soft tissues, bone healing and functional outcome, though its contour needs to be modified.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

PubMed

Um, Ji-Yong; Kim, Yoon-Jee; Cho, Seong-Eun; Chae, Min-Kyun; Kim, Byungsub; Sim, Jae-Yoon; Park, Hong-June

2015-02-01

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

The WS transform for the Kuramoto model with distributed amplitudes, phase lag and time delay

NASA Astrophysics Data System (ADS)

Lohe, M. A.

2017-12-01

We apply the Watanabe-Strogatz (WS) transform to a generalized Kuramoto model with distributed parameters describing the amplitude of oscillation, phase lag, and time delay at each node of the system. The model has global coupling and identical frequencies, but allows for repulsive interactions at arbitrary nodes leading to conformist-contrarian phenomena together with variable amplitude and time-delay effects. We show how to determine the initial values of the WS system for any initial conditions for the Kuramoto system, and investigate the asymptotic behaviour of the WS variables. For the case of zero time delay the possible asymptotic configurations are determined by the sign of a single parameter μ which measures whether or not the attractive nodes dominate the repulsive nodes. If μ>0 the system completely synchronizes from general initial conditions, whereas if μ<0 one of two types of phase-locked synchronization occurs, depending on the initial values, while for μ=0 periodic solutions can occur. For the case of arbitrary non-uniform time delays we derive a stability condition for completely synchronized solutions.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

NASA Astrophysics Data System (ADS)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Ultrafast dynamics of Al-doped zinc oxide under optical excitation (Presentation Recording)

NASA Astrophysics Data System (ADS)

Kinsey, Nathaniel; DeVault, Clayton T.; Kim, Jongbum; Ferrera, Marcello; Kildishev, Alexander V.; Shalaev, Vladimir M.; Boltasseva, Alexandra

2015-09-01

There is a continual need to explore new and promising dynamic materials to power next-generation switchable devices. In recent years, transparent conducting oxides have been shown to be vital materials for such systems, allowing for both optical and electrical tunability. Using a pump-probe technique, we investigate the optical tunability of CMOS-compatible, highly aluminum doped zinc oxide (AZO) thin films. The sample was pumped at 325 nm and probed with a weak beam at 1.3 μm to determine the timescale and magnitude of the changes by altering the temporal delay between the pulses with a delay line. For an incident fluence of 3.9 mJ/cm2 a change of 40% in reflection and 30% (max 6.3dB/μm modulation depth) in transmission is observed which is fully recovered within 1ps. Using a computational model, the experimental results were fitted for the given fluence allowing the recombination time and induced carrier density to be extracted. For a fluence of 3.9 mJ/cm2 the average excess carrier density within the material is 0.7×10^20cm-3 and the recombination time is 88fs. The ultrafast temporal response is the result of Auger recombination due to the extremely high carrier concentration present in our films, ~10^21 cm-3. By measuring and fitting the results at several incident fluence levels, the recombination time versus carrier density was determined and fitted with an Auger model resulting in an Auger coefficient of C = 1.03×10^20cm6/sec. Consequently, AZO is shown to be a unique, promising, and CMOS-compatible material for high performance dynamic devices in the near future.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

A Fixed-Pattern Noise Correction Method Based on Gray Value Compensation for TDI CMOS Image Sensor.

PubMed

Liu, Zhenwang; Xu, Jiangtao; Wang, Xinlei; Nie, Kaiming; Jin, Weimin

2015-09-16

In order to eliminate the fixed-pattern noise (FPN) in the output image of time-delay-integration CMOS image sensor (TDI-CIS), a FPN correction method based on gray value compensation is proposed. One hundred images are first captured under uniform illumination. Then, row FPN (RFPN) and column FPN (CFPN) are estimated based on the row-mean vector and column-mean vector of all collected images, respectively. Finally, RFPN are corrected by adding the estimated RFPN gray value to the original gray values of pixels in the corresponding row, and CFPN are corrected by subtracting the estimated CFPN gray value from the original gray values of pixels in the corresponding column. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination with the proposed method, the standard-deviation of row-mean vector decreases from 5.6798 to 0.4214 LSB, and the standard-deviation of column-mean vector decreases from 15.2080 to 13.4623 LSB. Both kinds of FPN in the real images captured by TDI-CIS are eliminated effectively with the proposed method.

Fixed-pattern noise correction method based on improved moment matching for a TDI CMOS image sensor.

PubMed

Xu, Jiangtao; Nie, Huafeng; Nie, Kaiming; Jin, Weimin

2017-09-01

In this paper, an improved moment matching method based on a spatial correlation filter (SCF) and bilateral filter (BF) is proposed to correct the fixed-pattern noise (FPN) of a time-delay-integration CMOS image sensor (TDI-CIS). First, the values of row FPN (RFPN) and column FPN (CFPN) are estimated and added to the original image through SCF and BF, respectively. Then the filtered image will be processed by an improved moment matching method with a moving window. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination, the standard deviation of row mean vector (SDRMV) decreases from 5.6761 LSB to 0.1948 LSB, while the standard deviation of the column mean vector (SDCMV) decreases from 15.2005 LSB to 13.1949LSB. In addition, for different images captured by different TDI-CISs, the average decrease of SDRMV and SDCMV is 5.4922/2.0357 LSB, respectively. Comparative experimental results indicate that the proposed method can effectively correct the FPNs of different TDI-CISs while maintaining image details without any auxiliary equipment.

Spin-neurons: A possible path to energy-efficient neuromorphic computers

NASA Astrophysics Data System (ADS)

Sharad, Mrigank; Fan, Deliang; Roy, Kaushik

2013-12-01

Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices. Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and "thresholding" operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that "spin-neurons" (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.

An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Khosroshahy, Milad Bagherian; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

Nanotechnologies, notably quantum-dot cellular automata, have achieved major attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, high switching speed and ultra-low energy consumption, is considered as a potential alternative for the CMOS technology. As the memory unit is one of the most essential components in a digital system, designing a well-optimized QCA random access memory (RAM) cell is an important area of research. In this paper, a new five-input majority gate is presented which is suitable for implementing efficient single-layer QCA circuits. In addition, a new RAM cell with set and reset capabilities is designed based on the proposed majority gate, which has an efficient and low-energy structure. The functionality, performance and energy consumption of the proposed designs are evaluated based on the QCADesigner and QCAPro tools. According to the simulation results, the proposed RAM design leads to on average 38% lower total energy dissipation, 25% smaller area, 20% lower cell count, 28% lower delay and 60% lower QCA cost as compared to its previous counterparts.

Spin-neurons: A possible path to energy-efficient neuromorphic computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharad, Mrigank; Fan, Deliang; Roy, Kaushik

Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices.more » Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and “thresholding” operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that “spin-neurons” (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.« less

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Design of a Humidity Sensor Tag for Passive Wireless Applications.

PubMed

Wu, Xiang; Deng, Fangming; Hao, Yong; Fu, Zhihui; Zhang, Lihua

2015-10-07

This paper presents a wireless humidity sensor tag for low-cost and low-power applications. The proposed humidity sensor tag, based on radio frequency identification (RFID) technology, was fabricated in a standard 0.18 μm complementary metal oxide semiconductor (CMOS) process. The top metal layer was deposited to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture, resulting in a flat power conversion efficiency curve. The capacitive sensor interface, based on phase-locked loop (PLL) theory, employs a simple architecture and can work with 0.5 V supply voltage. The measurement results show that humidity sensor tag achieves excellent linearity, hysteresis and stability performance. The total power-dissipation of the sensor tag is 2.5 μW, resulting in a maximum operating distance of 23 m under 4 W of radiation power of the RFID reader.

Design of a Humidity Sensor Tag for Passive Wireless Applications

PubMed Central

Wu, Xiang; Deng, Fangming; Hao, Yong; Fu, Zhihui; Zhang, Lihua

2015-01-01

This paper presents a wireless humidity sensor tag for low-cost and low-power applications. The proposed humidity sensor tag, based on radio frequency identification (RFID) technology, was fabricated in a standard 0.18 μm complementary metal oxide semiconductor (CMOS) process. The top metal layer was deposited to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture, resulting in a flat power conversion efficiency curve. The capacitive sensor interface, based on phase-locked loop (PLL) theory, employs a simple architecture and can work with 0.5 V supply voltage. The measurement results show that humidity sensor tag achieves excellent linearity, hysteresis and stability performance. The total power-dissipation of the sensor tag is 2.5 μW, resulting in a maximum operating distance of 23 m under 4 W of radiation power of the RFID reader. PMID:26457707

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Dynamic Fixation of Humeral Shaft Fractures Using Active Locking Plates: A Prospective Observational Study.

PubMed

Madey, Steven M; Tsai, Stanley; Fitzpatrick, Daniel C; Earley, Kathleen; Lutsch, Michael; Bottlang, Michael

2017-01-01

Rigid locked plating constructs can suppress fracture healing by inhibiting interfragmentary motion required to stimulate natural bone healing by callus formation. Dynamic fixation with active locking plates reduces construct stiffness, enables controlled interfragmentary motion, and has been shown to induce faster and stronger bone healing in vivo compared to rigid locking plates. This prospective observational study represents the first clinical use of active locking plates. It documents our early clinical experience with active plates for stabilization of humeral shaft fractures to assess their durability and understand potential complications. Eleven consecutive patients with humeral shaft fractures (AO/OTA types 12 A-C) were prospectively enrolled at a level I and a level II trauma center. Fractures were stabilized by using active locking plates without supplemental bone graft or bone morphogenic proteins. The screw holes of active locking plates are elastically suspended in elastomer envelopes inside the plate, enabling up to 1.5 mm of controlled interfragmentary motion. Progression of fracture healing and integrity of implant fixation was assessed radiographically at 3, 6, 12, and 24 weeks post surgery. Patient-reported functional outcome measures were obtained at 6, 12, and 24 weeks post surgery. The primary endpoint of this study was plate durability in absence of plate bending or breakage, or failure of the elastically suspended locking hole mechanism. Secondary endpoints included fracture healing, complications requiring revision surgery, and functional outcome scores. The eleven patients had six simple AO/ OTA type 12A fractures, three wedge type 12B fractures, and two comminuted type 12C fracture, including one open fracture. All active locking plates endured the 6-month loading period without any signs of fatigue or failure. Ten of eleven fractures healed at 10.9 ± 5.2 weeks, as evident by bridging callus and pain-free function. One fracture required revision surgery 37 weeks post surgery due to late fixation failure at the screwbone interface in the presence of a atrophic delayed union. The average Disability of the Arm, Shoulder and Hand (DASH) score improved from 31 ± 22 at week 6 to 13 ± 15 by week 24, approaching that of the normal, healthy population (DASH = 10.1). By week 12, the difference between Constant shoulder scores, expressed as the difference between the affected and contralateral arm (8 ± 8), was considered excellent. By week 24, the SF-12 physical health score (44 ± 9) and mental health score (48 ± 11) approached the mean value of 50 that represents the norm for the general U.S. population. Absence of failure of the plate and locking holes suggests that dynamic fixation of humeral shaft fractures with active plates provides safe and effective fixation. Moreover, early callus bridging and excellent functional outcome scores suggest that dynamic fixation with active locking plates may promote increased fracture healing over standard locked plating.

Design of a delayed XOR phase detector for an optical phase-locked loop toward high-speed coherent laser communication.

PubMed

Liu, Yang; Tong, Shoufeng; Chang, Shuai; Song, Yansong; Dong, Yan; Zhao, Xin; An, Zhe; Yu, Fuwan

2018-05-10

Optical phase-locked loops are an effective detection method in high-speed and long-distance laser communication. Although this method can detect weak signal light and maintain a small bit error rate, it is difficult to perform because identifying the phase difference between the signal light and the local oscillator accurately has always been a technical challenge. Thus, a series of studies is conducted to address this issue. First, a delayed exclusive or gate (XOR) phase detector with multi-level loop compound control is proposed. Then, a 50 ps delay line and relative signal-to-noise ratio control at 15 dB are produced through theoretical derivation and simulation. Thereafter, a phase discrimination module is designed on a 15  cm×5  cm printed circuit board board. Finally, the experiment platform is built for verification. Experimental results show that the phase discrimination range is -1.1 to 1.1 GHz, and the gain is 0.82 mV/MHz. Three times the standard deviation, that is, 0.064 V, is observed between the test and theoretical values. The accuracy of phase detection is better than 0.07 V, which meets the design standards. A coherent carrier recovery test system is established. The delayed XOR gate has good performance in this system. When the communication rate is 5 Gbps, the system realizes a bit error rate of 1.55×10 -8 when the optical power of the signal is -40.4  dBm. When the communication rate is increased to 10 Gbps, the detection sensitivity drops to -39.5  dBm and still shows good performance in high-speed communications. This work provides a reference for future high-speed coherent homodyne detection in space. Ideas for the next phase of this study are presented at the end of this paper.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

The Biolink Implantable Telemetry System

NASA Technical Reports Server (NTRS)

Betancourt-Zamora, Rafael J.

1999-01-01

Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHZ offset, showing good agreement with the theory. We also propose a novel superregenerative receiver architecture for implementing the command receiver. The superregenerative receiver's simplicity, low cost, and low power consumption has made it the receiver of choice for short-distance data communications, remote control and home automation. We present the design of a superregenerative AM receiver implemented in a 0.5um CMOS technology that operates at 433.92MHz and dissipates only 300uW. Further work entails detailed transistor-level design of the FLL and superregenerative receiver and a monolithic implementation of an implantable transceiver in 0.5um CMOS technology.

JPRS Report. Science & Technology: China.

DTIC Science & Technology

1989-03-17

From Simple Colliding-Pulse Mode- Locking Dye Laser With Double Coated Stack Mirrors [Wang Qingyue, et al.; GUANGXUE XUEBAO, No 11, Nov 88] 82...86 Influence of Stimulated Raman Process on Fundamental Solitons in Fibers [Qu Linjie, et al.; GUANGXUE XUEBAO, No 11, Nov 88] 87 650 nm...synapses are the same regarding the relationship of he and hi to N. Each component of the vector lat represents the delay time lat of each synapse as it

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

Management of distal femoral periprosthetic fractures by distal femoral locking plate: A retrospective study.

PubMed Central

Thukral, Rajiv; Marya, SKS; Singh, Chandeep

2015-01-01

Background: Management of periprosthetic supracondylar femoral fractures is difficult. Osteoporosis, comminution and bone loss, compromise stability with delayed mobility and poor functional outcomes. Open reduction and internal fixation (ORIF) with anatomic distal femoral (DF) locking plate permits early mobilization. However, this usually necessitates bone grafting (BG). Biological fixation using minimally invasive techniques minimizes periosteal stripping and morbidity. Materials and Methods: 31 patients with comminuted periprosthetic DF fractures were reviewed retrospectively from October 2006 to September 2012. All patients underwent fixation using a DF locking compression plate (Synthes). 17 patients underwent ORIF with primary BG, whereas 14 were treated by closed reduction (CR) and internal fixation using biological minimally invasive techniques. Clinical and radiological followup were recorded for an average 36 months. Results: Mean time to union for the entire group was 5.6 months (range 3-9 months). Patients of ORIF group took longer (Mean 6.4 months, range 4.5-9 months) than the CR group (mean 4.6 months, range 3-7 months). Three patients of ORIF and one in CR group had poor results. Mean knee society scores were higher for CR group at 6 months, but nearly identical at 12 months, with similar eventual range of motion. Discussion: Locked plating of comminuted periprosthetic DF fractures permits stable rigid fixation and early mobilization. Fixation using minimally invasive biological techniques minimizes morbidity and may obviate the need for primary BG. PMID:26015610

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

All-digital GPS receiver mechanization

NASA Astrophysics Data System (ADS)

Ould, P. C.; van Wechel, R. J.

The paper describes the all-digital baseband correlation processing of GPS signals, which is characterized by (1) a potential for improved antijamming performance, (2) fast acquisition by a digital matched filter, (3) reduction of adjustment, (4) increased system reliability, and (5) provision of a basis for the realization of a high degree of VLSI potential for the development of small economical GPS sets. The basic technical approach consists of a broadband fix-tuned RF converter followed by a digitizer; digital-matched-filter acquisition section; phase- and delay-lock tracking via baseband digital correlation; software acquisition logic and loop filter implementation; and all-digital implementation of the feedback numerical controlled oscillators and code generator. Broadband in-phase and quadrature tracking is performed by an arctangent angle detector followed by a phase-unwrapping algorithm that eliminates false locks induced by sampling and data bit transitions, and yields a wide pull-in frequency range approaching one-fourth of the loop iteration frequency.

Stable fiber-optic time transfer by active radio frequency phase locking.

PubMed

Yin, Feifei; Wu, Zhongle; Dai, Yitang; Ren, Tianpeng; Xu, Kun; Lin, Jintong; Tang, Geshi

2014-05-15

In this Letter we demonstrate a fiber link capable of stable time signal transfer utilizing our active long-distance radio frequency (RF) stabilization technology. Taking advantage of the chromatic dispersion in optical fiber, our scheme compensates dynamically the link delay variation by tuning the optical carrier wavelength to phase lock a round-trip RF reference. Since the time signal and the RF reference are carried by the same optical carrier, a highly stable time transfer is achieved at the same time. Experimentally, we demonstrate a stability of the time signal transfer over 50-km fiber with a time deviation of 40 ps at 1-s average and 2.3 ps at 1000-s average. The performance of the RF reference delivery is also tested, with an Allan deviation of 2×10(-15) at 1000-s average. According to our proposal, a simultaneous stable time and frequency transfer is expected.

Pulsed phase locked loop strain monitor

NASA Technical Reports Server (NTRS)

Froggatt, Mark E. (Inventor)

1995-01-01

A pulse phase locked loop system according to the present invention is described. A frequency generator such as a voltage controlled oscillator (VCO) generates an output signal and a reference signal having a frequency equal to that of the output signal. A transmitting gate gates the output frequency signal and this gated signal drives a transmitting transducer which transmits an acoustic wave through a material. A sample/hold samples a signal indicative of the transmitted wave which is received by a receiving transducer. Divide-by-n counters control these gating and sampling functions in response to the reference signal of the frequency generator. Specifically, the output signal is gated at a rate of F/h, wherein F is the frequency of the output signal and h is an integer; and the received signal is sampled at a delay of F/n wherein n is an integer.

Autaptic pacemaker mediated propagation of weak rhythmic activity across small-world neuronal networks

NASA Astrophysics Data System (ADS)

Yilmaz, Ergin; Baysal, Veli; Ozer, Mahmut; Perc, Matjaž

2016-02-01

We study the effects of an autapse, which is mathematically described as a self-feedback loop, on the propagation of weak, localized pacemaker activity across a Newman-Watts small-world network consisting of stochastic Hodgkin-Huxley neurons. We consider that only the pacemaker neuron, which is stimulated by a subthreshold periodic signal, has an electrical autapse that is characterized by a coupling strength and a delay time. We focus on the impact of the coupling strength, the network structure, the properties of the weak periodic stimulus, and the properties of the autapse on the transmission of localized pacemaker activity. Obtained results indicate the existence of optimal channel noise intensity for the propagation of the localized rhythm. Under optimal conditions, the autapse can significantly improve the propagation of pacemaker activity, but only for a specific range of the autaptic coupling strength. Moreover, the autaptic delay time has to be equal to the intrinsic oscillation period of the Hodgkin-Huxley neuron or its integer multiples. We analyze the inter-spike interval histogram and show that the autapse enhances or suppresses the propagation of the localized rhythm by increasing or decreasing the phase locking between the spiking of the pacemaker neuron and the weak periodic signal. In particular, when the autaptic delay time is equal to the intrinsic period of oscillations an optimal phase locking takes place, resulting in a dominant time scale of the spiking activity. We also investigate the effects of the network structure and the coupling strength on the propagation of pacemaker activity. We find that there exist an optimal coupling strength and an optimal network structure that together warrant an optimal propagation of the localized rhythm.

Multiplane and Spectrally-Resolved Single Molecule Localization Microscopy with Industrial Grade CMOS cameras.

PubMed

Babcock, Hazen P

2018-01-29

This work explores the use of industrial grade CMOS cameras for single molecule localization microscopy (SMLM). We show that industrial grade CMOS cameras approach the performance of scientific grade CMOS cameras at a fraction of the cost. This makes it more economically feasible to construct high-performance imaging systems with multiple cameras that are capable of a diversity of applications. In particular we demonstrate the use of industrial CMOS cameras for biplane, multiplane and spectrally resolved SMLM. We also provide open-source software for simultaneous control of multiple CMOS cameras and for the reduction of the movies that are acquired to super-resolution images.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

Annual Technical Report, Materials Research Laboratory, July 1, 1973-June 30, 1974

DTIC Science & Technology

1974-06-30

Office, Durham (AROD) Picosecond Laser Research An Experimental study of the linear growth region of ultrashort pulse generation was made. The pulse ...Experimental Study of the Linear Growth Region of Ultrashort - Pulse Generation in a Mode-locked Nd:glass Laser ," Appl. Phys. Letters 24, 631 (1974...the loading pulse which may be incident from any direction, and the onset of fast fracture. The dependence of the delay time on the pulse intensity

The LISA benchtop simulator at the University of Florida

NASA Astrophysics Data System (ADS)

Thorpe, James; Cruz, Rachel; Guntaka, Sridhar; Mueller, Guido

2006-11-01

The Laser Interferometer Space Antenna (LISA) is a joint NASA-ESA mission to detect gravitational radiation in space. The detector is designed to see gravitational waves from various exciting sources in the frequency range of 3x10-5 to 1 Hz. LISA consists of three spacecraft forming a triangle with 5x10^9 m long arms. The spacecraft house proof masses and act to shield the proof masses from external forces so that they act as freely-falling test particles of the gravitational radiation. Laser interferometry is used to monitor the distance between proof masses on different spacecraft and will be designed to see variations on the order of 10 pm. Pre-stabilization, arm-locking, and time delay interferometry (TDI) will be employed to meet this sensitivity. At the University of Florida, we are developing an experimental LISA simulator to test aspects of LISA interferometry. The foundation of the simulator is a pair of cavity-stabilized lasers that provide realistic, LISA-like phase noise for our measurements. The light travel time between spacecraft is recreated in the lab by use of an electronic phase delay technique. Initial tests of the simulator have focused on phasemeter implementation, first-generation TDI, and arm-locking. We will present results from these experiments as well as discuss current and future upgrades in the effort to make the LISA simulator as realistic as possible.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

PubMed

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

High-speed railway signal trackside equipment patrol inspection system

NASA Astrophysics Data System (ADS)

Wu, Nan

2018-03-01

High-speed railway signal trackside equipment patrol inspection system comprehensively applies TDI (time delay integration), high-speed and highly responsive CMOS architecture, low illumination photosensitive technique, image data compression technique, machine vision technique and so on, installed on high-speed railway inspection train, and achieves the collection, management and analysis of the images of signal trackside equipment appearance while the train is running. The system will automatically filter out the signal trackside equipment images from a large number of the background image, and identify of the equipment changes by comparing the original image data. Combining with ledger data and train location information, the system accurately locate the trackside equipment, conscientiously guiding maintenance.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Are Locking Constructs in Distal Femoral Fractures Always Best? A Prospective Multicenter Randomized Controlled Trial Comparing the Less Invasive Stabilization System With the Minimally Invasive Dynamic Condylar Screw System.

PubMed

2016-01-01

The purpose of this clinical study is to determine whether the rate of fracture healing and fracture union, repaired with a locked device, will be as good as or better than standard nonlocking bicortical fixation in distal femoral fractures. Institutional review board-approved, multicenter prospective randomized controlled trial. Seven level 1 trauma centers across Canada. Fifty-two patients with distal femoral fractures (AO/OTA 33A1 to 33C2) were enrolled in the randomized trial. Twelve AO/OTA 33C3 fractures were excluded from the randomized trial but followed up as a nonrandomized cohort. Patients were treated through a standardized minimally invasive approach. Fractures were randomized 1:1 to treatment with the locked Less Invasive Stabilization System (LISS; Synthes, Paoli, PA) or the dynamic condylar screw (DCS). The nonrandomized cohort was treated at the surgeon's discretion. Primary outcomes were time to radiological union and number of delayed/nonunions at 12 months. Secondary outcomes were postoperative function and complications. Fifty-two patients were randomized including 34 women and 18 men. The mean age was 59 years. Twenty-eight patients were treated with the LISS and 24 with the DCS. There was no statistically significant difference between the LISS and the DCS in terms of the number of fractures healed, time to union, or functional scores. Complications and revisions were more common in the LISS group. There were 7 reoperations in the LISS group and one in the DCS group. Only 52% of the LISS group healed without intervention by 12 months compared with 91% in the DCS group. There was no advantage to the locking plate design in the management of distal femoral fractures in this study. The higher cost of the locking plates, challenges in technique, and lack of superiority have led the authors to discontinue the use of this lateral unicortical locking device in favor of other devices that allow locked or nonlocked bicortical fixation, articular compression, and bridging of the comminuted fracture segments. The cost-effective treatment for a subgroup or periarticular fractures may be a fixed-angle nonlocked device in patients with reasonable bone quality. Therapeutic Level II. See Instructions for Authors for a complete description of levels of evidence.

Instrumentation for one-way satellite PTTI applications. [calibration and synchronization of clocks from navigation satellite

NASA Technical Reports Server (NTRS)

Osborne, A. E.

1973-01-01

A review of general principles and operational procedures illustrates how the typical passive user and omni receiving antenna can recover Precise Time and Time Interval (PTTI) information from a low altitude navigation satellite system for clock calibration and synchronization. Detailed discussions of concepts and theory of the receiver design are presented. The importance of RF correlation of the received and local PN encoded sequences is emphasized as a means of reducing delay uncertainties of the instrumentation to values compatible with nanosecond to submicrosecond PTTI objectives. Two receiver configurations were fabricated for use in satellite-to-laboratory experiments. In one receiver the delay-locked loop for PN signals synchronization used a dithered amplitude detection process while the second receiver used a complex sums phase detection method for measurement of delay error. The necessity for compensation of Doppler shift is discussed. Differences in theoretical signal acquisition and tracking performance of the design concepts are noted.

Dynamics of temporally localized states in passively mode-locked semiconductor lasers

NASA Astrophysics Data System (ADS)

Schelte, C.; Javaloyes, J.; Gurevich, S. V.

2018-05-01

We study the emergence and the stability of temporally localized structures in the output of a semiconductor laser passively mode locked by a saturable absorber in the long-cavity regime. For large yet realistic values of the linewidth enhancement factor, we disclose the existence of secondary dynamical instabilities where the pulses develop regular and subsequent irregular temporal oscillations. By a detailed bifurcation analysis we show that additional solution branches that consist of multipulse (molecules) solutions exist. We demonstrate that the various solution curves for the single and multipeak pulses can splice and intersect each other via transcritical bifurcations, leading to a complex web of solutions. Our analysis is based on a generic model of mode locking that consists of a time-delayed dynamical system, but also on a much more numerically efficient, yet approximate, partial differential equation. We compare the results of the bifurcation analysis of both models in order to assess up to which point the two approaches are equivalent. We conclude our analysis by the study of the influence of group velocity dispersion, which is only possible in the framework of the partial differential equation model, and we show that it may have a profound impact on the dynamics of the localized states.

The Comfort Measures Order Set at a Tertiary Care Academic Hospital: Is There a Comparable Difference in End-of-Life Care Between Patients Dying in Acute Care When CMOS Is Utilized?

PubMed

Lau, Christine; Stilos, Kalli; Nowell, Allyson; Lau, Fanchea; Moore, Jennifer; Wynnychuk, Lesia

2018-04-01

Standardized protocols have been previously shown to be helpful in managing end-of-life (EOL) care in hospital. The comfort measures order set (CMOS), a standardized framework for assessing imminently dying patients' symptoms and needs, was implemented at a tertiary academic hospital. We assessed whether there were comparable differences in the care of a dying patient when the CMOS was utilized and when it was not. A retrospective chart review was completed on patients admitted under oncology and general internal medicine, who were referred to the inpatient palliative care team for "EOL care" between February 2015 and March 2016. Of 83 patients, 56 (67%) received intiation of the CMOS and 27 (33%) did not for EOL care. There was significant involvement of spiritual care with the CMOS (66%), as compared to the group without CMOS (19%), P < .05. The use of CMOS resulted in 1.7 adjustments to symptom management per patient by palliative care, which was significantly less than the number of symptom management adjustments per patient when CMOS was not used (3.3), P < .05. However, initiating CMOS did not result in a signficant difference in patient distress around the time of death ( P = .11). Dyspnea was the most frequently identified symptom causing distress in actively dying patients. Implementation of the CMOS is helpful in providing a foundation to a comfort approach in imminently dying patients. However, more education on its utility as a framework for EOL care and assessment across the organization is still required.

A clock steering method: using a third-order type 3 DPLL equivalent to a Kalman filter with a delay

NASA Astrophysics Data System (ADS)

Wu, Yiwei; Gong, Hang; Zhu, Xiangwei; Ou, Gang

2015-12-01

In this paper we propose a new clock steering method, which uses a third-order type 3 digital phase locked loop (DPLL) which is equivalent to a Kalman filter with a delay. A general overview of the theoretical framework is described in detail including the transfer functions, the structure and control values, the specifications, and the approach to choosing a parameter. Simulations show that the performance of the time and frequency steering errors and the frequency stability are quite desirable. Comparing with traditional clock steering methods, it is easier to work with just one parameter. The DPLL method satisfies the requirements of generating a local representation of universal time coordinated and the system time of a global navigation satellite system.

Cargo Movement Operations System (CMOS). Software Test Description

DTIC Science & Technology

1990-10-28

resulting in errors in paragraph numbers and titles. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...location to test the update of the truck manifest. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Femtosecond Lasers with Diode Pumping for Using in Precision Metrology and Optical Fiber Communication

DTIC Science & Technology

2008-11-24

folding angle of 32° to compensate astigmatism of the Brewster -cut Cr:F crystal. The gain crystal was 17 mm long and introduced positive group-delay...accomplished. For complete stabilization of the femtosecond comb one needs to control its absolute frequency. To realize this we use either angle - tilted...Kerr- lens mode-locking. To the best of our knowledge there is no published works on KLM ytterbium femtosecond lasers with multimode pumping. Stable

Application of Time-Resolved Spectroscopies to the Study of Energetic Materials - 1982

DTIC Science & Technology

1983-05-24

fluores- cence intensity as a function of UV pulse energy, for individual laser shots. The lower curve shows the UV + probe induced fluorescence... intensity as a function of UV pulse energy, for individual laser shots. The lower curve shows the UV + probe Induced fluorescence, at 1 ns delay...locked Nd:YAG Laser Pulse ", Appl. Phys. Lett 26, 501-503 (1975). 97 43. A. J. Campillo, V. H. Kollman and S. L. Shapiro, " Intensity Dependence of

Foreword

NASA Astrophysics Data System (ADS)

Caraveo, Patrizia; Gehrels, Neil; Tagliaferri, Gianpiero

2015-09-01

The Swift launch in 2004 was a nail-biter as one storm after another pummeled Cape Canaveral. The satellite had arrived in July, and our launch team fretted over whether its baby, locked away in a hangar, could survive the hurricane-force winds. The October launch was delayed a week, then another week, and then a few more days. Finally, on November 20, Swift launched under clear Florida skies. Pre-launch jitters gave way to an adrenaline rush as the first data came down showing a perfectly operating observatory.

CMOS image sensors: State-of-the-art

NASA Astrophysics Data System (ADS)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seco, Joao; Depauw, Nicolas

2011-02-15

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissuemore » contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.« less

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Cargo Movement Operations System (CMOS) System Segment Design Document (Draft) Increment II

DTIC Science & Technology

1990-05-02

and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR

CMOL/CMOS hardware architectures and performance/price for Bayesian memory - The building block of intelligent systems

NASA Astrophysics Data System (ADS)

Zaveri, Mazad Shaheriar

The semiconductor/computer industry has been following Moore's law for several decades and has reaped the benefits in speed and density of the resultant scaling. Transistor density has reached almost one billion per chip, and transistor delays are in picoseconds. However, scaling has slowed down, and the semiconductor industry is now facing several challenges. Hybrid CMOS/nano technologies, such as CMOL, are considered as an interim solution to some of the challenges. Another potential architectural solution includes specialized architectures for applications/models in the intelligent computing domain, one aspect of which includes abstract computational models inspired from the neuro/cognitive sciences. Consequently in this dissertation, we focus on the hardware implementations of Bayesian Memory (BM), which is a (Bayesian) Biologically Inspired Computational Model (BICM). This model is a simplified version of George and Hawkins' model of the visual cortex, which includes an inference framework based on Judea Pearl's belief propagation. We then present a "hardware design space exploration" methodology for implementing and analyzing the (digital and mixed-signal) hardware for the BM. This particular methodology involves: analyzing the computational/operational cost and the related micro-architecture, exploring candidate hardware components, proposing various custom hardware architectures using both traditional CMOS and hybrid nanotechnology - CMOL, and investigating the baseline performance/price of these architectures. The results suggest that CMOL is a promising candidate for implementing a BM. Such implementations can utilize the very high density storage/computation benefits of these new nano-scale technologies much more efficiently; for example, the throughput per 858 mm2 (TPM) obtained for CMOL based architectures is 32 to 40 times better than the TPM for a CMOS based multiprocessor/multi-FPGA system, and almost 2000 times better than the TPM for a PC implementation. We later use this methodology to investigate the hardware implementations of cortex-scale spiking neural system, which is an approximate neural equivalent of BICM based cortex-scale system. The results of this investigation also suggest that CMOL is a promising candidate to implement such large-scale neuromorphic systems. In general, the assessment of such hypothetical baseline hardware architectures provides the prospects for building large-scale (mammalian cortex-scale) implementations of neuromorphic/Bayesian/intelligent systems using state-of-the-art and beyond state-of-the-art silicon structures.

Rapid Alterations in Perirenal Adipose Tissue Transcriptomic Networks with Cessation of Voluntary Running

PubMed Central

Toedebusch, Ryan G.; Roberts, Christian K.; Roberts, Michael D.; Booth, Frank W.

2015-01-01

In maturing rats, the growth of abdominal fat is attenuated by voluntary wheel running. After the cessation of running by wheel locking, a rapid increase in adipose tissue growth to a size that is similar to rats that have never run (i.e. catch-up growth) has been previously reported by our lab. In contrast, diet-induced increases in adiposity have a slower onset with relatively delayed transcriptomic responses. The purpose of the present study was to identify molecular pathways associated with the rapid increase in adipose tissue after ending 6 wks of voluntary running at the time of puberty. Age-matched, male Wistar rats were given access to running wheels from 4 to 10 weeks of age. From the 10th to 11th week of age, one group of rats had continued wheel access, while the other group had one week of wheel locking. Perirenal adipose tissue was extracted, RNA sequencing was performed, and bioinformatics analyses were executed using Ingenuity Pathway Analysis (IPA). IPA was chosen to assist in the understanding of complex ‘omics data by integrating data into networks and pathways. Wheel locked rats gained significantly more fat mass and significantly increased body fat percentage between weeks 10–11 despite having decreased food intake, as compared to rats with continued wheel access. IPA identified 646 known transcripts differentially expressed (p < 0.05) between continued wheel access and wheel locking. In wheel locked rats, IPA revealed enrichment of transcripts for the following functions: extracellular matrix, macrophage infiltration, immunity, and pro-inflammatory. These findings suggest that increases in visceral adipose tissue that accompanies the cessation of pubertal physical activity are associated with the alteration of multiple pathways, some of which may potentiate the development of pubertal obesity and obesity-associated systemic low-grade inflammation that occurs later in life. PMID:26678390

[Effectiveness of mini locking plate combined with Kirschner wire in treatment of comminuted Jones fracture].

PubMed

Yan, Rongliang; Qu, Jiafu; Cao, Lihai; Liu, Hongda; Chen, Jianghua; Gao, Yan; Peng, Yi

2018-05-01

To summarize the effectiveness of mini locking plate combined with Kirschner wire in treatment of comminuted Jones fracture. Between January 2011 and October 2016, 25 cases with comminuted Jones fracture were treated with mini locking plate combined with Kirschner wire. There were 9 males and 16 females with an average age of 31.4 years (range, 16-66 years). The fractures located on the left side in 11 cases and on the right side in 14 cases. The causes of injury included spraining in 21 cases, falling down in 3 cases, and bruise in 1 case. The bone fragment of all cases was more than 3 pieces. The fracture line was mostly Y-shape or T-shape. Twelve of them were combined with other fractures. The time from injury to operation was 1-9 days (mean, 5 days). The mini locking plate and Kirschner wire were removed at 9-12 months postoperatively. At 12 months postoperatively, the pain was evaluated by the visual analogue scale (VAS) score, and the function by the American Orthopaedic Foot & Ankle Society (AOFAS) score. All incisions healed by first intention. All cases were followed up 12-36 months with an average of 21.7 months. Fracture union was observed in all patients without complications such as nonunion, delayed union, and malunion. The fracture union time was 8-12 weeks (mean, 9.4 weeks). At 12 months postoperatively, the VAS score was 1.15±0.87; the AOFAS score was 89.45±6.24, and the results were excellent in 14 cases, good in 9 cases, fair in 1 case, and poor in 1 case, with an excellent and good rate of 92%. The procedure of mini locking plate combined with Kirschner wire for comminuted Jones fracture has such advantages as convenient operation, more rigid fixation, high rate of fracture healing, and good functional recovery in foot.

Rapid Alterations in Perirenal Adipose Tissue Transcriptomic Networks with Cessation of Voluntary Running.

PubMed

Ruegsegger, Gregory N; Company, Joseph M; Toedebusch, Ryan G; Roberts, Christian K; Roberts, Michael D; Booth, Frank W

2015-01-01

In maturing rats, the growth of abdominal fat is attenuated by voluntary wheel running. After the cessation of running by wheel locking, a rapid increase in adipose tissue growth to a size that is similar to rats that have never run (i.e. catch-up growth) has been previously reported by our lab. In contrast, diet-induced increases in adiposity have a slower onset with relatively delayed transcriptomic responses. The purpose of the present study was to identify molecular pathways associated with the rapid increase in adipose tissue after ending 6 wks of voluntary running at the time of puberty. Age-matched, male Wistar rats were given access to running wheels from 4 to 10 weeks of age. From the 10th to 11th week of age, one group of rats had continued wheel access, while the other group had one week of wheel locking. Perirenal adipose tissue was extracted, RNA sequencing was performed, and bioinformatics analyses were executed using Ingenuity Pathway Analysis (IPA). IPA was chosen to assist in the understanding of complex 'omics data by integrating data into networks and pathways. Wheel locked rats gained significantly more fat mass and significantly increased body fat percentage between weeks 10-11 despite having decreased food intake, as compared to rats with continued wheel access. IPA identified 646 known transcripts differentially expressed (p < 0.05) between continued wheel access and wheel locking. In wheel locked rats, IPA revealed enrichment of transcripts for the following functions: extracellular matrix, macrophage infiltration, immunity, and pro-inflammatory. These findings suggest that increases in visceral adipose tissue that accompanies the cessation of pubertal physical activity are associated with the alteration of multiple pathways, some of which may potentiate the development of pubertal obesity and obesity-associated systemic low-grade inflammation that occurs later in life.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

A power scalable PLL frequency synthesizer for high-speed Δ—Σ ADC

NASA Astrophysics Data System (ADS)

Siyang, Han; Baoyong, Chi; Xinwang, Zhang; Zhihua, Wang

2014-08-01

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for Δ—Σ analog-to-digital converter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300-360 MHz) or in low-power mode (35-130 MHz) to satisfy the ADC's requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of -132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of -112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.

An 11-bit and 39 ps resolution time-to-digital converter for ADPLL in digital television

NASA Astrophysics Data System (ADS)

Liu, Wei; (Ruth) Li, Wei; Ren, P.; Lin, C. L.; Zhang, Shengdong; Wang, Yangyuan

2010-04-01

We propose and demonstrate an 11-bit time-to-digital converter (TDC) for all-digital phase-locked loops (ADPLLs) in digital television. The proposed TDC converts the width of the input pulse into digital output with the tap space of the outputs of a free-running ring oscillator (FRO) being the conversion resolution. The FRO is in a structure of coiled cell array and the TDC core is symmetrical in the input structure. This leads to equally spaced taps in the reference clocks and thereby a high TDC conversion linearity. The TDC is fabricated in 0.13 μm CMOS process and the chip area is 0.025 mm2. The measurement results show that the TDC has a conversion resolution of 39 ps at 1.2 V power supply and a 4.5 ns dead time in the 11-bits output case. Both the differential non-linearity (DNL) and integral non-linearity (INL) are below 0.5 LSB. The power consumption of the whole circuit is 4.2 mW.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix, Version 3 Increment II

DTIC Science & Technology

1990-12-17

above SCs should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...These two documents should be in agreement with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...completeness, they should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

Cargo Movement Operations System (CMOS) Final Software User’s Manual

DTIC Science & Technology

1990-12-20

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ I COMMENT STATUS: OPEN...is correct. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS CO1MENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...RATIONALE: .."DA001041" is in the SUM but not in the SDD. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Ionizing doses and displacement damage testing of COTS CMOS imagers

NASA Astrophysics Data System (ADS)

Bernard, Frédéric; Petit, Sophie; Courtade, Sophie

2017-11-01

CMOS sensors begin to be a credible alternative to CCD sensors in some space missions. However, technology evolution of CMOS sensors is much faster than CCD one's. So a continuous technology evaluation is needed for CMOS imagers. Many of commercial COTS (Components Off The Shelf) CMOS sensors use organic filters, micro-lenses and non rad-hard technologies. An evaluation of the possibilities offered by such technologies is interesting before any custom development. This can be obtained by testing commercial COTS imagers. This article will present electro-optical performances evolution of off the shelves CMOS imagers after Ionizing Doses until 50kRad(Si) and Displacement Damage environment tests (until 1011 p/cm2 at 50 MeV). Dark current level and non uniformity evolutions are compared and discussed. Relative spectral response measurement and associated evolution with irradiation will also be presented and discussed. Tests have been performed on CNES detection benches.

Flight phasemeter on the Laser Ranging Interferometer on the GRACE Follow-On mission

NASA Astrophysics Data System (ADS)

Bachman, B.; de Vine, G.; Dickson, J.; Dubovitsky, S.; Liu, J.; Klipstein, W.; McKenzie, K.; Spero, R.; Sutton, A.; Ware, B.; Woodruff, C.

2017-05-01

As the first inter-spacecraft laser interferometer, the Laser Ranging Interferometer (LRI) on the GRACE Follow-On Mission will demonstrate interferometry technology relevant to the LISA mission. This paper focuses on the completed LRI Laser Ranging Processor (LRP), which includes heterodyne signal phase tracking at μ {{cycle/}}\\sqrt{{{Hz}}} precision, differential wavefront sensing, offset frequency phase locking and Pound-Drever-Hall laser stabilization. The LRI design has characteristics that are similar to those for LISA: 1064 nm NPRO laser source, science bandwidth in the mHz range, MHz-range intermediate frequency and Doppler shift, detected optical power of tens of picoWatts. Laser frequency stabilization has been demonstrated at a level below 30{{Hz/}}\\sqrt{{{Hz}}}, better than the LISA requirement of 300{{Hz/}}\\sqrt{{{Hz}}}. The LRP has completed all performance testing and environmental qualification and has been delivered to the GRACE Follow-On spacecraft. The LRI is poised to test the LISA techniques of tone-assisted time delay interferometry and arm-locking. GRACE Follow-On launches in 2017.

The Role of Inhibition in a Computational Model of an Auditory Cortical Neuron during the Encoding of Temporal Information

PubMed Central

Bendor, Daniel

2015-01-01

In auditory cortex, temporal information within a sound is represented by two complementary neural codes: a temporal representation based on stimulus-locked firing and a rate representation, where discharge rate co-varies with the timing between acoustic events but lacks a stimulus-synchronized response. Using a computational neuronal model, we find that stimulus-locked responses are generated when sound-evoked excitation is combined with strong, delayed inhibition. In contrast to this, a non-synchronized rate representation is generated when the net excitation evoked by the sound is weak, which occurs when excitation is coincident and balanced with inhibition. Using single-unit recordings from awake marmosets (Callithrix jacchus), we validate several model predictions, including differences in the temporal fidelity, discharge rates and temporal dynamics of stimulus-evoked responses between neurons with rate and temporal representations. Together these data suggest that feedforward inhibition provides a parsimonious explanation of the neural coding dichotomy observed in auditory cortex. PMID:25879843

Picosecond pulses from wavelength-swept continuous-wave Fourier domain mode-locked lasers.

PubMed

Eigenwillig, Christoph M; Wieser, Wolfgang; Todor, Sebastian; Biedermann, Benjamin R; Klein, Thomas; Jirauschek, Christian; Huber, Robert

2013-01-01

Ultrafast lasers have a crucial function in many fields of science; however, up to now, high-energy pulses directly from compact, efficient and low-power semiconductor lasers are not available. Therefore, we introduce a new approach based on temporal compression of the continuous-wave, wavelength-swept output of Fourier domain mode-locked lasers, where a narrowband optical filter is tuned synchronously to the round-trip time of light in a kilometre-long laser cavity. So far, these rapidly swept lasers enabled orders-of-magnitude speed increase in optical coherence tomography. Here we report on the generation of ~60-70 ps pulses at 390 kHz repetition rate. As energy is stored optically in the long-fibre delay line and not as population inversion in the laser-gain medium, high-energy pulses can now be generated directly from a low-power, compact semiconductor-based oscillator. Our theory predicts subpicosecond pulses with this new technique in the future.

Picosecond pulses from wavelength-swept continuous-wave Fourier domain mode-locked lasers

NASA Astrophysics Data System (ADS)

Eigenwillig, Christoph M.; Wieser, Wolfgang; Todor, Sebastian; Biedermann, Benjamin R.; Klein, Thomas; Jirauschek, Christian; Huber, Robert

2013-05-01

Ultrafast lasers have a crucial function in many fields of science; however, up to now, high-energy pulses directly from compact, efficient and low-power semiconductor lasers are not available. Therefore, we introduce a new approach based on temporal compression of the continuous-wave, wavelength-swept output of Fourier domain mode-locked lasers, where a narrowband optical filter is tuned synchronously to the round-trip time of light in a kilometre-long laser cavity. So far, these rapidly swept lasers enabled orders-of-magnitude speed increase in optical coherence tomography. Here we report on the generation of ~60-70 ps pulses at 390 kHz repetition rate. As energy is stored optically in the long-fibre delay line and not as population inversion in the laser-gain medium, high-energy pulses can now be generated directly from a low-power, compact semiconductor-based oscillator. Our theory predicts subpicosecond pulses with this new technique in the future.

Delay induced high order locking effects in semiconductor lasers

NASA Astrophysics Data System (ADS)

Kelleher, B.; Wishon, M. J.; Locquet, A.; Goulding, D.; Tykalewicz, B.; Huyet, G.; Viktorov, E. A.

2017-11-01

Multiple time scales appear in many nonlinear dynamical systems. Semiconductor lasers, in particular, provide a fertile testing ground for multiple time scale dynamics. For solitary semiconductor lasers, the two fundamental time scales are the cavity repetition rate and the relaxation oscillation frequency which is a characteristic of the field-matter interaction in the cavity. Typically, these two time scales are of very different orders, and mutual resonances do not occur. Optical feedback endows the system with a third time scale: the external cavity repetition rate. This is typically much longer than the device cavity repetition rate and suggests the possibility of resonances with the relaxation oscillations. We show that for lasers with highly damped relaxation oscillations, such resonances can be obtained and lead to spontaneous mode-locking. Two different laser types-—a quantum dot based device and a quantum well based device—are analysed experimentally yielding qualitatively identical dynamics. A rate equation model is also employed showing an excellent agreement with the experimental results.

Delay induced high order locking effects in semiconductor lasers.

PubMed

Kelleher, B; Wishon, M J; Locquet, A; Goulding, D; Tykalewicz, B; Huyet, G; Viktorov, E A

2017-11-01

Multiple time scales appear in many nonlinear dynamical systems. Semiconductor lasers, in particular, provide a fertile testing ground for multiple time scale dynamics. For solitary semiconductor lasers, the two fundamental time scales are the cavity repetition rate and the relaxation oscillation frequency which is a characteristic of the field-matter interaction in the cavity. Typically, these two time scales are of very different orders, and mutual resonances do not occur. Optical feedback endows the system with a third time scale: the external cavity repetition rate. This is typically much longer than the device cavity repetition rate and suggests the possibility of resonances with the relaxation oscillations. We show that for lasers with highly damped relaxation oscillations, such resonances can be obtained and lead to spontaneous mode-locking. Two different laser types--a quantum dot based device and a quantum well based device-are analysed experimentally yielding qualitatively identical dynamics. A rate equation model is also employed showing an excellent agreement with the experimental results.

Application of system identification to analytic rotor modeling from simulated and wind tunnel dynamic test data, part 2

NASA Technical Reports Server (NTRS)

Hohenemser, K. H.; Banerjee, D.

1977-01-01

An introduction to aircraft state and parameter identification methods is presented. A simplified form of the maximum likelihood method is selected to extract analytical aeroelastic rotor models from simulated and dynamic wind tunnel test results for accelerated cyclic pitch stirring excitation. The dynamic inflow characteristics for forward flight conditions from the blade flapping responses without direct inflow measurements were examined. The rotor blades are essentially rigid for inplane bending and for torsion within the frequency range of study, but flexible in out-of-plane bending. Reverse flow effects are considered for high rotor advance ratios. Two inflow models are studied; the first is based on an equivalent blade Lock number, the second is based on a time delayed momentum inflow. In addition to the inflow parameters, basic rotor parameters like the blade natural frequency and the actual blade Lock number are identified together with measurement bias values. The effect of the theoretical dynamic inflow on the rotor eigenvalues is evaluated.

Modeling the Effects of Asynchronous Rotation on Secondary Eclipse Timings in HW VIr Binaries

NASA Astrophysics Data System (ADS)

Clancy, Padraig

2018-01-01

HW Vir binaries are post common envelope binaries consisting of a hot subdwarf and red dwarf, with light curves dominated by primary eclipses, a strong reflection effect, and secondary eclipses. They have orbital periods ranging from a few hours to half a day and are generally thought to be tidally locked; most studies assume both synchronous rotation and zero eccentricity when modeling HW Vir light curves and radial velocities. Their stable eclipse timings are frequently used in O-C studies to look for the presence of circumbinary objects, measure evolutionary changes in the orbital period, and even constrain the component masses through Roemer delay measurements of the secondary eclipse. While most systems are probably tidally locked or close to it, even slightly asynchronous rotation could theoretically shift the orbital phase of the reflection effect. Here we investigate how asynchronous rotation might affect measurements of secondary eclipse timings by generating thousands of synthetic light curves with a range of reflection effect phases, fitting eclipse timings, and creating O-C diagrams.

Evaluation the course of the vehicle braking process in case of hydraulic circuit malfunction

NASA Astrophysics Data System (ADS)

Szczypiński-Sala, W.; Lubas, J.

2016-09-01

In the paper, the results of the research were discussed, the aim of which was the evaluation of the vehicle braking performance efficiency and the course of this process with regard to the dysfunction which may occur in braking hydraulic circuit. As part of the research, on-road tests were conducted. During the research, the delay of the vehicle when braking was measured with the use of the set of sensors placed in the parallel and the perpendicular axis of the vehicle. All the tests were conducted on the same flat section of asphalt road with wet surface. Conditions of diminished tire-to-road adhesion were chosen in order to force the activity of anti-lock braking system. The research was conducted comparatively for the vehicle with acting anti-lock braking system and subsequently for the vehicle without the system. In both cases, there was a subsequent evaluation of the course of braking with efficient braking system and with the dysfunction of hydraulic circuit.

Versatile single-chip event sequencer for atomic physics experiments

NASA Astrophysics Data System (ADS)

Eyler, Edward

2010-03-01

A very inexpensive dsPIC microcontroller with internal 32-bit counters is used to produce a flexible timing signal generator with up to 16 TTL-compatible digital outputs, with a time resolution and accuracy of 50 ns. This time resolution is easily sufficient for event sequencing in typical experiments involving cold atoms or laser spectroscopy. This single-chip device is capable of triggered operation and can also function as a sweeping delay generator. With one additional chip it can also concurrently produce accurately timed analog ramps, and another one-chip addition allows real-time control from an external computer. Compared to an FPGA-based digital pattern generator, this design is slower but simpler and more flexible, and it can be reprogrammed using ordinary `C' code without special knowledge. I will also describe the use of the same microcontroller with additional hardware to implement a digital lock-in amplifier and PID controller for laser locking, including a simple graphics-based control unit. This work is supported in part by the NSF.

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

NASA Technical Reports Server (NTRS)

Kulkarni, Shriram; Mazumder, Pinaki; Haddad, George I.

1995-01-01

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.

The challenge of sCMOS image sensor technology to EMCCD

NASA Astrophysics Data System (ADS)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Structural and functional networks in complex systems with delay.

PubMed

Eguíluz, Víctor M; Pérez, Toni; Borge-Holthoefer, Javier; Arenas, Alex

2011-05-01

Functional networks of complex systems are obtained from the analysis of the temporal activity of their components, and are often used to infer their unknown underlying connectivity. We obtain the equations relating topology and function in a system of diffusively delay-coupled elements in complex networks. We solve exactly the resulting equations in motifs (directed structures of three nodes) and in directed networks. The mean-field solution for directed uncorrelated networks shows that the clusterization of the activity is dominated by the in-degree of the nodes, and that the locking frequency decreases with increasing average degree. We find that the exponent of a power law degree distribution of the structural topology γ is related to the exponent of the associated functional network as α=(2-γ)(-1) for γ<2. © 2011 American Physical Society

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Intramedullary fixation of forearm fractures with new locked nail.

PubMed

Bansal, Himanshu

2011-09-01

Lack of availability of interlocked nails made plate osteosynthesis the first choice of treatment of forearm fractures inspite of more surgical exposure, periosteal stripping and big skin incision subsequent scar along with higher risk of refracture on implant removal. We hereby report the first 12 cases with 19 forearm bone fractures internally fixed by indegenous interlocked nail. Existing square nails were modified to have a broad proximal end of 5.5 mm with a hole for locking screw of 2.5 mm. The nail has a distal hole of 1/1.2/1.5 mm in 2.5/3/3.5 mm diameter nail, respectively. A new method of distal locking with a clip made of k wire is designed. The clip after insertion into the bone and hole in nail and opposite cortex snuggly fits the bone providing a secure locking system. Twelve skeletally mature patients, mean age 32 years (range 24-45 years) with 19 diaphyseal fractures of the forearm were treated with this indigenously made new nail. The patient were evaluated for fracture union, functional recovery and complications. The functional outcome was assessed by disabilities of arm, shoulder and hand questionnaire (DASH score). Time to radiographic union ranged between 12 and 28 weeks, with a 100% union rate. Complications were minimal, with mild infection in open fracture (n=1) and delayed union (n=1) in patient with comminuted fracture of the ulna only. The clinical results were excellent. The DASH score ranged between 0 and 36 points. This new interlocking nail may be considered as an alternative to plate osteosynthesis for fractures of the forearm in adults. The advantages are benefit of closed reduction, smaller residual scar, reduced cost and early union with allowance of immediate movements.

Frequency domain phase noise analysis of dual injection-locked optoelectronic oscillators.

PubMed

Jahanbakht, Sajad

2016-10-01

Dual injection-locked optoelectronic oscillators (DIL-OEOs) have been introduced as a means to achieve very low-noise microwave oscillations while avoiding the large spurious peaks that occur in the phase noise of the conventional single-loop OEOs. In these systems, two OEOs are inter-injection locked to each other. The OEO with the longer optical fiber delay line is called the master OEO, and the other is called the slave OEO. Here, a frequency domain approach for simulating the phase noise spectrum of each of the OEOs in a DIL-OEO system and based on the conversion matrix approach is presented. The validity of the new approach is verified by comparing its results with previously published data in the literature. In the new approach, first, in each of the master or slave OEOs, the power spectral densities (PSDs) of two white and 1/f noise sources are optimized such that the resulting simulated phase noise of any of the master or slave OEOs in the free-running state matches the measured phase noise of that OEO. After that, the proposed approach is able to simulate the phase noise PSD of both OEOs at the injection-locked state. Because of the short run-time requirements, especially compared to previously proposed time domain approaches, the new approach is suitable for optimizing the power injection ratios (PIRs), and potentially other circuit parameters, in order to achieve good performance regarding the phase noise in each of the OEOs. Through various numerical simulations, the optimum PIRs for achieving good phase noise performance are presented and discussed; they are in agreement with the previously published results. This further verifies the applicability of the new approach. Moreover, some other interesting results regarding the spur levels are also presented.

Molecular laser stabilization for LISA

NASA Astrophysics Data System (ADS)

Halloin, Hubert; Acef, Ouali; Argence, Berengere; Jeannin, Olivier; Prat, Pierre; de Vismes, Eden; Plagnol, Eric; Brillet, Alain; Mondin, Linda; Berthon, Jacques; Turazza, Oscar

2017-11-01

The expected performance of LISA relies on two main technical challenges: the ability for the spacecrafts to precisely follow the free-flying masses and the outstanding precision of the phase shift measurement. This latter constraint requires frequency stabilized lasers and efficient numerical algorithms to account for the redundant, delayed noise propagation, thus cancelling laser phase noise by many orders of magnitude (TDI methods). Recently involved in the technical developments for LISA, the goal of our team at APC (France) is to contribute on these two subjects: frequency reference for laser stabilization and benchtop simulation of the interferometer. In the present design of LISA, two stages of laser stabilization are used (not accounting for the "post-processed" TDI algorithm): laser pre-stabilization on a frequency reference and lock on the ultra stable distance between spacecrafts (arm-locking). While the foreseen (and deeply studied) laser reference consists of a Fabry-Perot cavity, other techniques may be suitable for LISA or future metrology missions. In particular, locking to a molecular reference (namely iodine in the case of the LISA Nd:YAG laser) is an interesting alternative. It offers the required performance with very good long-term stability (absolute frequency reference) though the reference can be slightly tuned to account for arm-locking. This technique is currently being investigated by our team and optimized for LISA (compactness, vacuum compatibility, ease of use and initialization, etc.). A collaboration with a French laboratory (the SYRTE) had been started aiming to study a second improved technique consisting in inserting the iodine cell in a Fabry-Perot cavity. Ongoing results and prospects to increase the performance of the system are presented in the present article.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

NASA Technical Reports Server (NTRS)

Lee, C.; Johnston, A.

1998-01-01

This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Fundamental performance differences between CMOS and CCD imagers, part IV

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

BRIEF COMMUNICATIONS: Dynamics of lasing of two TEA CO2 lasers coupled by a nonlinear SF6 cell

NASA Astrophysics Data System (ADS)

Baranov, V. Yu; Dyad'kin, A. P.; Shpilyun, O. V.

1991-10-01

A study was made of the kinetics of stimulated emission from two TEA CO2 lasers in a system with frequency locking by phase conjugation as a result of a four-wave interaction of light [V. Yu. Baranov, A. P. Dyad'kin, V. V. Likhanskiĭ et al., Sov. J. Quantum Electron. 18, 1462 (1988)]. A simple method for ensuring two-pulse lasing with a variable time delay between the pulses in one gas-discharge chamber was proposed.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

Resonant current in coupled inertial Brownian particles with delayed-feedback control

NASA Astrophysics Data System (ADS)

Gao, Tian-Fu; Zheng, Zhi-Gang; Chen, Jin-Can

2017-12-01

The transport of a walker in rocking feedback-controlled ratchets is investigated. The walker consists of two coupled "feet" that allow the interchange of the order of particles while the walker moves. In the underdamped case, the deterministic dynamics of the walker in a tilted asymmetric ratchet with an external periodic force is considered. It is found that delayed feedback ratchets with a switching-onand-off dependence of the states of the system can lead to absolute negative mobility. In such a novel phenomenon, the particles move against the bias. Moreover, the walker can acquire a series of resonant steps for different values of the current. It is interesting to find that the resonant currents of the walker are induced by the phase locked motion that corresponds to the synchronization of the motion with the change in the frequency of the external driving. These resonant steps can be well predicted in terms of time-space symmetry analysis, which is in good agreement with dynamics simulations. The transport performances can be optimized and controlled by suitably adjusting the parameters of the delayed-feedback ratchets.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... credit union may invest in and hold exchangeable collateralized mortgage obligations (exchangeable CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio of the market...

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Cargo Movement Operations System (CMOS). Final Software Requirements Specification, (Applications CSCI), Increment II

DTIC Science & Technology

1991-01-29

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL Nt3MBFR: SRS1-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...floppy diskette interface with CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES ( 3 NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Tests of commercial colour CMOS cameras for astronomical applications

NASA Astrophysics Data System (ADS)

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

NASA Astrophysics Data System (ADS)

de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

2008-05-01

CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

Performance evaluation of the time delay digital tanlock loop architectures

NASA Astrophysics Data System (ADS)

Al-Kharji Al-Ali, Omar; Anani, Nader; Al-Qutayri, Mahmoud; Al-Araji, Saleh; Ponnapalli, Prasad

2016-01-01

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

Sensitivity to external signals and synchronization properties of a non-isochronous auto-oscillator with delayed feedback

PubMed Central

Tiberkevich, Vasil S.; Khymyn, Roman S.; Tang, Hong X.; Slavin, Andrei N.

2014-01-01

For auto-oscillators of different nature (e.g. active cells in a human heart under the action of a pacemaker, neurons in brain, spin-torque nano-oscillators, micro and nano-mechanical oscillators, or generating Josephson junctions) a critically important property is their ability to synchronize with each other. The synchronization properties of an auto oscillator are directly related to its sensitivity to external signals. Here we demonstrate that a non-isochronous (having generation frequency dependent on the amplitude) auto-oscillator with delayed feedback can have an extremely high sensitivity to external signals and unusually large width of the phase-locking band near the boundary of the stable auto-oscillation regime. This property could be used for the development of synchronized arrays of non-isochronous auto-oscillators in physics and engineering, and, for instance, might bring a better fundamental understanding of ways to control a heart arrythmia in medicine. PMID:24464086

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

PubMed

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

The $500 Million Question: Can Charter Management Organizations Deliver Quality Education at Scale?

ERIC Educational Resources Information Center

Hall, Kevin; Lake, Robin

2011-01-01

Charter school management organizations (CMOs) have emerged as a popular means for bringing charter schooling to scale. Advocates credit CMOs with delivering a coherent model of charter schooling to a growing number of children across numerous sites. Skeptics have wondered whether CMOs constitute an effective management approach, whether they…

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and..., the sale for importation, and the sale within the United States after importation of certain CMOS image sensors and products containing same by reason of infringement of certain claims of U.S. Patent No...

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Huang, Shaoyan; Liu, Minbo

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic rangemore » (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.« less

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

No evidence of benefit from antibiotic lock therapy in pediatric oncology patients with central line-related bloodstream infection: results of a retrospective matched cohort study and review of the literature.

PubMed

Wolf, Joshua; Allison, Kim J; Tang, Li; Sun, Yilun; Hayden, Randall T; Flynn, Patricia M

2014-10-01

Long-term central venous catheters (CVCs) are essential to modern pediatric oncology practice, but central line-related bloodstream infection (CRBSI) is a frequent and important complication. CVC salvage is often attempted but treatment failure is common due to persistent infection, delayed catheter removal, or subsequent relapse of infection, which can be associated with significant morbidity and cost. Adjunctive antibiotic lock therapy (ALT) has been proposed to reduce the risk of treatment failure, but insufficient data are available to confirm efficacy of this intervention. We undertook a retrospective matched cohort study of ALT use for treatment of CRBSI in pediatric hematology/oncology patients at St. Jude Children's Research Hospital between 2006 and 2012. Thirty-eight eligible episodes of CRBSI treated with adjunctive ALT were identified and compared to 73 episodes treated with standard therapy (ST) alone, matched by catheter-type and organism. Overall, treatment failure was similar between ALT and ST groups (50.0 vs. 38.4%; P = 0.24), but the timing was different; in the ALT cohort, immediate CVC removal was less common (0.0 vs. 12.3%; P = 0.03) but delayed removal (4-13 days) and relapse of infection was more common (50.0 vs. 24.7%; P = 0.01). This retrospective study was unable to identify any benefit of adjunctive ALT in pediatric oncology patients with CRBSI. The available evidence does not support routine ALT use, and well-conducted prospective studies are needed. © 2014 Wiley Periodicals, Inc.

Induced membrane technique combined with two-stage internal fixation for the treatment of tibial osteomyelitis defects.

PubMed

Luo, Fei; Wang, Xiaohua; Wang, Shulin; Fu, Jingshu; Xie, Zhao

2017-07-01

The purpose of this study was to observe the effects of induced membrane technique combined with two-stage internal fixation in the treatment of tibial osteomyelitis defects. A retrospective analyses for 67 cases of tibialosteomyelitis defects were admitted to our department between September 2012 to February 2015, which were treated with induced membrane technique. At the first stage, implanted with a PMMA cement spacer in the defects after radical debridement and fixed with reconstructive locked plate. Bone grafting and exchanged the plate with intramedullary nail at the second stage. In current study, all patients were followed up for 18-35 months. Sixty-six patients achieved bone union with the average radiographic and clinical healing times of 5.55±2.19 and 7.45±1.69months, respectively. Seven patients required a second debridement before grafting, while four patients experienced a recurrence of infection or a relapse following second stage treatment. Twelve patients experienced either knee or ankle dysfunctions and 2 patients faced delayed wound healing. Donor site complications includes pain and infection were found in 7 and 3 patients, respectively with delayed stress fracture in 1 patient only. Induced membrane technique for the treatment of tibial osteomyelitis defects, seems a reliable method. The use of reconstructive locked plate as a temporary internal fixation at the first stage and exchanged with intramedullary nail at the second stage, potentially achieves good clinical efficacy. Care should be taken to restore the joint function especially in distal tibia. Copyright © 2017 Elsevier Ltd. All rights reserved.

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Carbon Nanotube Integration with a CMOS Process

PubMed Central

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

PubMed Central

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

PubMed Central

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-01-01

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction.

PubMed

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-07-14

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

Cargo Movement Operations System (CMOS) Interface Requirements Specification (Draft). Increment II

DTIC Science & Technology

1990-05-17

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ 3 CLOSED [ ] ORIGINATOR CONTROL NUMBER: IRS1-0003 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM DISCREPANCY WORKSHEET CDRL NUMBER: A004-05 DATE: 05/17/90 ORIGINATOR NAME: Ronald J. Lacour OFFICE SYMBOL: SAIC TELEPHONE NUMBER: 272-2999 SUBSTANTIVE: X EDITORIAL: PAGE NUMBER: 9 PARA NUMBER: 3.2 c. COMMENT OR RECOMMENDED CHANGE: Change line 2 to read, "CMOS IRD/SBSS-01 and SBSS-03." Move "CMOS IRD/SBSS-02" to paragraph 3.3 c. RATIONALE: The CMOS IRD/SBSS-02 covers the Shipment Suspense

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Cargo Movement Operations System (CMOS). Software Requirements Specification

DTIC Science & Technology

1990-03-12

was erroneously deleted. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...previous SRS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] 0 ORIGINATOR CONTROL NUMBER

Cargo Movement Operations System (CMOS). System Segment Specification, Updated, Increment II

DTIC Science & Technology

1990-05-02

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ 3 COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL...the LAN. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED

Dynamics of response-conflict monitoring and individual differences in response control and behavioral control: an electrophysiological investigation using a stop-signal task.

PubMed

Stahl, Jutta; Gibbons, Henning

2007-03-01

The aim of the present study was to investigate the functional significance of error (related) negativity Ne/ERN and individual differences in human action monitoring. A response-conflict model of Ne/ERN should be tested applying a stop-signal paradigm. After a few modifications of Ne/ERN response-conflict theory (Yeung N, Botvinick MM, Cohen JD. The neural basis of error detection: conflict monitoring and the error-related negativity. Psychological Review 2004:111(4);931-959), strength and time course of response conflict could be modeled as a function of stop-signal delay. In Experiment 1, 35 participants performed a visual two-choice response-time task but tried to withhold the response if an auditory stop signal was presented. Probability of stopping errors was held at 50% using variable delays between visual and auditory stimuli. Experiment 2 (n=10) employed both auditory go and stop signals and confirmed that Ne/ERN effects are due to conflict induced by the auditory stop signal, and not the mere presence or absence of an additional stimulus. As predicted, amplitudes of both the stimulus-locked and response-locked Ne/ERN were largest for non-stopped responses, followed by successfully stopped and go responses. However, independently of response type Ne/ERN also increased with increasing stop-signal delay. Since longer delay invokes stronger response conflict, results specifically support the notion of Ne/ERN reflecting response-conflict monitoring. Furthermore, individual differences related to measures of response control and behavioral control were observed. Both low response control estimated from stop-task performance and high psychometric impulsivity were accompanied by smaller Ne/ERN amplitude on stop trials, suggesting reduced response-conflict monitoring. The present study supported the response-conflict view of Ne/ERN. Furthermore, the observed relationship between impulsivity and Ne/ERN amplitude suggested that individuals with low behavioral control were characterized by lower activity in anterior cingulate cortex, the neural generator of Ne/ERN, in situations of strong response conflict. The present study, for the first time, employed a stop-signal paradigm to verify predictions regarding the temporal dynamics of response-conflict processing as derived from response-conflict theory of ERN.

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

Design and simulation of multi-color infrared CMOS metamaterial absorbers

NASA Astrophysics Data System (ADS)

Cheng, Zhengxi; Chen, Yongping; Ma, Bin

2016-05-01

Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Design of CMOS imaging system based on FPGA

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

PubMed

Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig

2018-02-05

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

The heterogeneous integration of single-walled carbon nanotubes onto complementary metal oxide semiconductor circuitry for sensing applications.

PubMed

Chen, Chia-Ling; Agarwal, Vinay; Sonkusale, Sameer; Dokmeci, Mehmet R

2009-06-03

A simple methodology for integrating single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry is presented. The SWNTs were incorporated onto the CMOS chip as the feedback resistor of a two-stage Miller compensated operational amplifier utilizing dielectrophoretic assembly. The measured electrical properties from the integrated SWNTs yield ohmic behavior with a two-terminal resistance of approximately 37.5 kOmega and the measured small signal ac gain (-2) from the inverting amplifier confirmed successful integration of carbon nanotubes onto the CMOS circuitry. Furthermore, the temperature response of the SWNTs integrated onto CMOS circuitry has been measured and had a thermal coefficient of resistance (TCR) of -0.4% degrees C(-1). This methodology, demonstrated for the integration of SWNTs onto CMOS technology, is versatile, high yield and paves the way for the realization of novel miniature carbon-nanotube-based sensor systems.

SOI-CMOS Process for Monolithic, Radiation-Tolerant, Science-Grade Imagers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, George; Lee, Adam

In Phase I, Voxtel worked with Jazz and Sandia to document and simulate the processes necessary to implement a DH-BSI SOI CMOS imaging process. The development is based upon mature SOI CMOS process at both fabs, with the addition of only a few custom processing steps for integration and electrical interconnection of the fully-depleted photodetectors. In Phase I, Voxtel also characterized the Sandia process, including the CMOS7 design rules, and we developed the outline of a process option that included a “BOX etch”, that will permit a “detector in handle” SOI CMOS process to be developed The process flows weremore » developed in cooperation with both Jazz and Sandia process engineers, along with detailed TCAD modeling and testing of the photodiode array architectures. In addition, Voxtel tested the radiation performance of the Jazz’s CA18HJ process, using standard and circular-enclosed transistors.« less

A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

NASA Astrophysics Data System (ADS)

Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

2014-01-01

A CMOS image sensor with stacked photodiodes was fabricated using 0.18 µm mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

Visualization of hair follicles using high-speed optical coherence tomography based on a Fourier domain mode locking laser

NASA Astrophysics Data System (ADS)

Tsai, M.-T.; Chang, F.-Y.

2012-04-01

In this study, a swept-source optical coherence tomography (SS-OCT) system with a Fourier domain mode locking (FDML) laser is proposed for a dermatology study. The homemade FDML laser is one kind of frequency-sweeping light source, which can provide output power of >20 mW and an output spectrum of 65 nm in bandwidth centered at 1300 nm, enabling imaging with an axial resolution of 12 μm in the OCT system. To eliminate the forward scans from the laser output and insert the delayed backward scans, a Mach-Zehnder configuration is implemented. Compared with conventional frequency-sweeping light sources, the FDML laser can achieve much higher scan rates, as high as ˜240 kHz, which can provide a three-dimensional imaging rate of 4 volumes/s. Furthermore, the proposed high-speed SS-OCT system can provide three-dimensional (3D) images with reduced motion artifacts. Finally, a high-speed SS-OCT system is used to visualize hair follicles, demonstrating the potential of this technology as a tool for noninvasive diagnosis of alopecia.

No more lock-step retirement: Boomers' shifting meanings of work and retirement.

PubMed

Kojola, Erik; Moen, Phyllis

2016-01-01

Standard pathways for work and retirement are being transformed as the large Boomer cohort moves through typical retirement ages during a moment of economic, social and political change. People are delaying retirement and moving into and out of paid work as the standard lock-step retirement becomes less dominant. However, little research has explored how and why Boomers are taking on these diverse pathways in their later careers. Accordingly, we conduct in-depth interviews with working and retired white-collar Boomers, exploring how they are working and the meanings and motivations for their decisions and plans in their later careers. We find that there is no single dominant pattern for retirement, but rather a diverse mix of pathways shaped by occupational identities, finances, health and perceptions of retirement. Boomers express a desire to have control over their time and to find meaning and purpose in either paid or unpaid activities. However, life course transitions, normative cultural scripts, and gender and class locations as well as workplace and social policies constrain their decisions and plans. Copyright © 2016 Elsevier Inc. All rights reserved.

Anatomically precontoured LCP for delayed union of a medial third clavicle fracture. Case report with review of the literature.

PubMed

Siebenlist, S; Sandmann, G; Kirchhoff, C; Biberthaler, P; Neumaier, M

2013-01-01

Fractures of the medial clavicle third are rare injuries. Even in case of significant fracture displacement, their therapeutic management has been nonoperative. Recently, surgical intervention has become mandatory for displaced fractures types to prevent non-union and functional complaints, but the optimal operative strategy is being discussed controversially. We describe the case of a 63-year-old male patient with a significantly displaced medial clavicle fracture after failed conservative treatment resulting in restricted, painful shoulder function. The patient underwent open reduction and osteosynthesis with an anatomically precontoured locking compression plate (LCP). One year after surgery the patient is free of complaints and has returned to his preinjury activity level without any functional restrictions. As a not yet reported operative approach, anatomically preshaped locking plating seems to be an effective fixation method for displaced fractures of the medial clavicle third. The operative management is described in detail and discussed with the current literature. Based on the presented case, we underline the statement that displaced medial clavicle fractures should be surgically addressed to avoid late damage.

Reactive control processes contributing to residual switch cost and mixing cost across the adult lifespan.

PubMed

Whitson, Lisa R; Karayanidis, Frini; Fulham, Ross; Provost, Alexander; Michie, Patricia T; Heathcote, Andrew; Hsieh, Shulan

2014-01-01

In task-switching paradigms, performance is better when repeating the same task than when alternating between tasks (switch cost) and when repeating a task alone rather than intermixed with another task (mixing cost). These costs remain even after extensive practice and when task cues enable advanced preparation (residual costs). Moreover, residual reaction time mixing cost has been consistently shown to increase with age. Residual switch and mixing costs modulate the amplitude of the stimulus-locked P3b. This mixing effect is disproportionately larger in older adults who also prepare more for and respond more cautiously on these "mixed" repeat trials (Karayanidis et al., 2011). In this paper, we analyze stimulus-locked and response-locked P3 and lateralized readiness potentials to identify whether residual switch and mixing cost arise from the need to control interference at the level of stimulus processing or response processing. Residual mixing cost was associated with control of stimulus-level interference, whereas residual switch cost was also associated with a delay in response selection. In older adults, the disproportionate increase in mixing cost was associated with greater interference at the level of decision-response mapping and response programming for repeat trials in mixed-task blocks. These findings suggest that older adults strategically recruit greater proactive and reactive control to overcome increased susceptibility to post-stimulus interference. This interpretation is consistent with recruitment of compensatory strategies to compensate for reduced repetition benefit rather than an overall decline on cognitive flexibility.

Reactive control processes contributing to residual switch cost and mixing cost across the adult lifespan

PubMed Central

Whitson, Lisa R.; Karayanidis, Frini; Fulham, Ross; Provost, Alexander; Michie, Patricia T.; Heathcote, Andrew; Hsieh, Shulan

2014-01-01

In task-switching paradigms, performance is better when repeating the same task than when alternating between tasks (switch cost) and when repeating a task alone rather than intermixed with another task (mixing cost). These costs remain even after extensive practice and when task cues enable advanced preparation (residual costs). Moreover, residual reaction time mixing cost has been consistently shown to increase with age. Residual switch and mixing costs modulate the amplitude of the stimulus-locked P3b. This mixing effect is disproportionately larger in older adults who also prepare more for and respond more cautiously on these “mixed” repeat trials (Karayanidis et al., 2011). In this paper, we analyze stimulus-locked and response-locked P3 and lateralized readiness potentials to identify whether residual switch and mixing cost arise from the need to control interference at the level of stimulus processing or response processing. Residual mixing cost was associated with control of stimulus-level interference, whereas residual switch cost was also associated with a delay in response selection. In older adults, the disproportionate increase in mixing cost was associated with greater interference at the level of decision-response mapping and response programming for repeat trials in mixed-task blocks. These findings suggest that older adults strategically recruit greater proactive and reactive control to overcome increased susceptibility to post-stimulus interference. This interpretation is consistent with recruitment of compensatory strategies to compensate for reduced repetition benefit rather than an overall decline on cognitive flexibility. PMID:24817859

Design of a 0.13 µm SiGe Limiting Amplifier with 14.6 THz Gain-Bandwidth-Product

NASA Astrophysics Data System (ADS)

Park, Sehoon; Du, Xuan-Quang; Grözing, Markus; Berroth, Manfred

2017-09-01

This paper presents the design of a limiting amplifier with 1-to-3 fan-out implementation in a 0.13 µm SiGe BiCMOS technology and gives a detailed guideline to determine the circuit parameters of the amplifier for optimum high-frequency performance based on simplified gain estimations. The proposed design uses a Cherry-Hooper topology for bandwidth enhancement and is optimized for maximum group delay flatness to minimize phase distortion of the input signal. With regard to a high integration density and a small chip area, the design employs no passive inductors which might be used to boost the circuit bandwidth with inductive peaking. On a RLC-extracted post-layout simulation level, the limiting amplifier exhibits a gain-bandwidth-product of 14.6 THz with 56.6 dB voltage gain and 21.5 GHz 3 dB bandwidth at a peak-to-peak input voltage of 1.5 mV. The group delay variation within the 3 dB bandwidth is less than 0.5 ps and the power dissipation at a power supply voltage of 3 V including output drivers is 837 mW.

Optimal design of leak-proof SRAM cell using MCDM method

NASA Astrophysics Data System (ADS)

Wang, Qi; Kang, Sung-Mo

2003-04-01

As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor's performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit's performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.

Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC

NASA Astrophysics Data System (ADS)

Xu, Zule; Miyahara, Masaya; Matsuzawa, Akira

2014-04-01

A picosecond resolution time-to-digital converter (TDC) is presented. The resolution of a conventional delay chain TDC is limited by the delay of a logic buffer. Various types of recent TDCs are successful in breaking this limitation, but they require a significant calibration effort to achieve picosecond resolution with a sufficient linear range. To address these issues, we propose a simple method to break the resolution limitation without any calibration: a Gm-C integrator followed by a successive approximation register analog-to-digital converter (SAR-ADC). This translates the time interval into charge, and then the charge is quantized. A prototype chip was fabricated in 90 nm CMOS. The measurement results reveal a 1 ps resolution, a -0.6/0.7 LSB differential nonlinearity (DNL), a -1.1/2.3 LSB integral nonlinearity (INL), and a 9-bit range. The measured 11.74 ps single-shot precision is caused by the noise of the integrator. We analyze the noise of the integrator and propose an improved front-end circuit to reduce this noise. The proposal is verified by simulations showing the maximum single-shot precision is less than 1 ps. The proposed front-end circuit can also diminish the mismatch effects.

Implementation study of an analog spiking neural network for assisting cardiac delay prediction in a cardiac resynchronization therapy device.

PubMed

Sun, Qing; Schwartz, François; Michel, Jacques; Herve, Yannick; Dalmolin, Renzo

2011-06-01

In this paper, we aim at developing an analog spiking neural network (SNN) for reinforcing the performance of conventional cardiac resynchronization therapy (CRT) devices (also called biventricular pacemakers). Targeting an alternative analog solution in 0.13- μm CMOS technology, this paper proposes an approach to improve cardiac delay predictions in every cardiac period in order to assist the CRT device to provide real-time optimal heartbeats. The primary analog SNN architecture is proposed and its implementation is studied to fulfill the requirement of very low energy consumption. By using the Hebbian learning and reinforcement learning algorithms, the intended adaptive CRT device works with different functional modes. The simulations of both learning algorithms have been carried out, and they were shown to demonstrate the global functionalities. To improve the realism of the system, we introduce various heart behavior models (with constant/variable heart rates) that allow pathologic simulations with/without noise on the signals of the input sensors. The simulations of the global system (pacemaker models coupled with heart models) have been investigated and used to validate the analog spiking neural network implementation.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Cargo Movement Operations System (CMOS). Software User’s Manual

DTIC Science & Technology

1990-06-27

RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SUM-0003 PROGRAM...3.1.11. RATIONALE: Clarity. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS). Software Design Document

DTIC Science & Technology

1990-04-29

order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT...inadvertently omitted from the table. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDDI-0005 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

A Review on Passive and Integrated Near-Field Microwave Biosensors

PubMed Central

Guha, Subhajit; Jamal, Farabi Ibne

2017-01-01

In this paper we review the advancement of passive and integrated microwave biosensors. The interaction of microwave with biological material is discussed in this paper. Passive microwave biosensors are microwave structures, which are fabricated on a substrate and are used for sensing biological materials. On the other hand, integrated biosensors are microwave structures fabricated in standard semiconductor technology platform (CMOS or BiCMOS). The CMOS or BiCMOS sensor technology offers a more compact sensing approach which has the potential in the future for point of care testing systems. Various applications of the passive and the integrated sensors have been discussed in this review paper. PMID:28946617

Nanopore-CMOS Interfaces for DNA Sequencing

PubMed Central

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-01-01

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

Nanopore-CMOS Interfaces for DNA Sequencing.

PubMed

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-08-06

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

Delay Differential Equation-Based Modeling of Passively Mode-Locked Quantum Dot Lasers Using Measured Gain and Loss Spectra (Postprint)

DTIC Science & Technology

2013-01-01

semiconductor laser8, 9: ATAe d dA TQiTGi qg 12 11 2 1 (1) 2 0 1 AeeGgd dG GQ (2) Proc. of SPIE Vol. 8255 82551K-2 Downloaded From: http...1 Downloaded From: http://spiedigitallibrary.org/ on 01/14/2013 Terms of Use: http://spiedl.org/terms 1 Approved for public release; distribution...parameters ( 0g and 0q , respectively) have been derived to yield: Gg0 (10) Proc. of SPIE Vol. 8255 82551K-3 Downloaded From: http

Collaborative Research: Robust Climate Projections and Stochastic Stability of Dynamical Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ilya Zaliapin

This project focused on conceptual exploration of El Nino/Southern Oscillation (ENSO) variability and sensitivity using a Delay Differential Equation developed in the project. We have (i) established the existence and continuous dependence of solutions of the model (ii) explored multiple models solutions, and the distribution of solutions extrema, and (iii) established and explored the phase locking phenomenon and the existence of multiple solutions for the same values of model parameters. In addition, we have applied to our model the concept of pullback attractor, which greatly facilitated predictive understanding of the nonlinear model's behavior.

Identification of atmospheric structure by coherent microwave sounding

NASA Technical Reports Server (NTRS)

Birkemeier, W. P.

1969-01-01

Two atmospheric probing experiments involving beyond-the-horizon propagation of microwave signals are reported. In the first experiment, Doppler-shift caused by the cross path wind is measured by a phase lock receiver with the common volume displaced in azimuth from the great circle. Variations in the measured Doppler shift values are explained in terms of variations in atmospheric structure. The second experiment makes use of the pseudorandom sounding signal used in a RAKE communication system. Both multipath delay and Doppler shift are provided by the receiver, permitting the cross section of the atmospheric layer structure to be deduced.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Perspective: 2D for beyond CMOS

NASA Astrophysics Data System (ADS)

Robinson, Joshua A.

2018-05-01

Two-Dimensional (2D) materials have been a "beyond CMOS" focus for more than a decade now, and we are on the verge of a variety of breakthroughs in the science to enable their incorporation into next generation electronics. This perspective discusses some of the challenges that must be overcome, as well as various opportunities that await us in the world of 2D for beyond CMOS.

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

Cargo Movement Operations System (CMOS) System Segment Design Document. Revision. Increment 2

DTIC Science & Technology

1990-06-14

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ J CLOSED [ ] Cmnt Page Paragraph No. No. Number...provided (SSDDII-0004). CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ 3 ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...but not in paragraph 10.1. CMOS PMO ACCEPTS COMMENT: YES [ ) NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] * COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS): Revised Preliminary Software Design Document (Applications CSCI), Increment II

DTIC Science & Technology

1991-05-23

background color does not change. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: CONMENT STATUS: OPEN...NO ( ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ) CLOSED [ ] ,$ ...collected on this worksheet and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO

Cargo Movement Operations System (CMOS). Software Requirements Specification (Applications CSCI) Increment 1, Update

DTIC Science & Technology

1990-05-31

12. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SRS1-0004 PROGRAM OFFICE...operational state of the SBSS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS) Draft Software User’s Manual Increment II

DTIC Science & Technology

1991-06-26

the user. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...indicated. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN r I CLOSED [ ] ORIGINATOR CONTROL NUMBER: SUM-0006 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

Large Format CMOS-based Detectors for Diffraction Studies

NASA Astrophysics Data System (ADS)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Llamas: Large-area microphone arrays and sensing systems

NASA Astrophysics Data System (ADS)

Sanz-Robinson, Josue

Large-area electronics (LAE) provides a platform to build sensing systems, based on distributing large numbers of densely spaced sensors over a physically-expansive space. Due to their flexible, "wallpaper-like" form factor, these systems can be seamlessly deployed in everyday spaces. They go beyond just supplying sensor readings, but rather they aim to transform the wealth of data from these sensors into actionable inferences about our physical environment. This requires vertically integrated systems that span the entirety of the signal processing chain, including transducers and devices, circuits, and signal processing algorithms. To this end we develop hybrid LAE / CMOS systems, which exploit the complementary strengths of LAE, enabling spatially distributed sensors, and CMOS ICs, providing computational capacity for signal processing. To explore the development of hybrid sensing systems, based on vertical integration across the signal processing chain, we focus on two main drivers: (1) thin-film diodes, and (2) microphone arrays for blind source separation: 1) Thin-film diodes are a key building block for many applications, such as RFID tags or power transfer over non-contact inductive links, which require rectifiers for AC-to-DC conversion. We developed hybrid amorphous / nanocrystalline silicon diodes, which are fabricated at low temperatures (<200 °C) to be compatible with processing on plastic, and have high current densities (5 A/cm2 at 1 V) and high frequency operation (cutoff frequency of 110 MHz). 2) We designed a system for separating the voices of multiple simultaneous speakers, which can ultimately be fed to a voice-command recognition engine for controlling electronic systems. On a device level, we developed flexible PVDF microphones, which were used to create a large-area microphone array. On a circuit level we developed localized a-Si TFT amplifiers, and a custom CMOS IC, for system control, sensor readout and digitization. On a signal processing level we developed an algorithm for blind source separation in a real, reverberant room, based on beamforming and binary masking. It requires no knowledge about the location of the speakers or microphones. Instead, it uses cluster analysis techniques to determine the time delays for beamforming; thus, adapting to the unique acoustic environment of the room.

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

NASA Astrophysics Data System (ADS)

Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Multiple-target tracking implementation in the ebCMOS camera system: the LUSIPHER prototype

NASA Astrophysics Data System (ADS)

Doan, Quang Tuyen; Barbier, Remi; Dominjon, Agnes; Cajgfinger, Thomas; Guerin, Cyrille

2012-06-01

The domain of the low light imaging systems progresses very fast, thanks to detection and electronic multiplication technology evolution, such as the emCCD (electron multiplying CCD) or the ebCMOS (electron bombarded CMOS). We present an ebCMOS camera system that is able to track every 2 ms more than 2000 targets with a mean number of photons per target lower than two. The point light sources (targets) are spots generated by a microlens array (Shack-Hartmann) used in adaptive optics. The Multiple-Target-Tracking designed and implemented on a rugged workstation is described. The results and the performances of the system on the identification and tracking are presented and discussed.

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Simulation of tectonic evolution of the Kanto basin of Japan since 1 Ma due to subduction of the Pacific and Philippine sea plates and collision of the Izu-Bonin arc

NASA Astrophysics Data System (ADS)

Hashima, Akinori; Sato, Toshinori; Sato, Hiroshi; Asao, Kazumi; Furuya, Hiroshi; Yamamoto, Shuji; Kameo, Koji; Miyauchi, Takahiro; Ito, Tanio; Tsumura, Noriko; Kaneda, Heitaro

2015-04-01

The Kanto basin, the largest lowland in Japan, developed by flexure as a result of (1) the subduction of the Philippine Sea (PHS) and the Pacific (PAC) plates and (2) the collision of the Izu-Bonin arc with the Japanese island arc. Geomorphological, geological, and thermochronological data on long-term vertical movements over the last 1 My suggest that subsidence initially affected the entire Kanto basin after which the area of subsidence gradually narrowed until, finally, the basin began to experience uplift. In this study, we modelled the tectonic evolution of the Kanto basin following the method of Matsu'ura and Sato (1989) for a kinematic subduction model with dislocations, in order to quantitatively assess the effects of PHS and PAC subduction. We include the steady slip-rate deficit (permanent locking rate at the plate interface) in our model to account for collision process. We explore how the arc-arc collision process has been affected by a westerly shift in the PHS plate motion vector with respect to the Eurasian plate, thought to have occurred between 1.0-0.5 Ma, using long-term vertical deformation data to constrain extent of the locked zone on the plate interface. We evaluated the change in vertical deformation rate for two scenarios: (1) a synchronous shift in the orientation of the locked zone as PHS plate motion shifts and (2) a delayed shift in the orientation of the locked zone following a change in plate motion. Observed changes in the subsidence/uplift pattern are better explained by scenario (2), suggesting that recent (<1 My) deformation in the Kanto basin shows a lag in crustal response to the shift in plate motion. We also calculated recent stress accumulation rates and found a good match with observed earthquake mechanisms, which shows that intraplate earthquakes serve to release stress accumulated through long-term plate interactions.

Simulation of tectonic evolution of the Kanto Basin of Japan since 1 Ma due to subduction of the Pacific and Philippine Sea plates and the collision of the Izu-Bonin arc

NASA Astrophysics Data System (ADS)

Hashima, Akinori; Sato, Toshinori; Sato, Hiroshi; Asao, Kazumi; Furuya, Hiroshi; Yamamoto, Shuji; Kameo, Koji; Miyauchi, Takahiro; Ito, Tanio; Tsumura, Noriko; Kaneda, Heitaro

2016-06-01

The Kanto Basin, the largest lowland in Japan, developed by flexure as a result of (1) the subduction of the Philippine Sea (PHS) and the Pacific (PAC) plates and (2) the repeated collision of the Izu-Bonin arc fragments with the Japanese island arc. Geomorphological, geological, and thermochronological data on vertical movements over the last 1 My suggest that subsidence initially affected the entire basin after which the area of subsidence gradually narrowed until, finally, the basin began to experience uplift. In this study, we modeled the tectonic evolution of the Kanto Basin following the method of Matsu'ura and Sato (1989) for a kinematic subduction model with dislocations, in order to quantitatively assess the effects of PHS and PAC subduction. We include the steady slip-rate deficit (permanent locking rate at the plate interface) in our model to account for collision process. We explore how the latest collision of the Izu Peninsula block has been affected by a westerly shift in the PHS plate motion vector with respect to the Eurasian plate, thought to have occurred between 1.0-0.5 Ma, using long-term vertical deformation data to constrain extent of the locked zone on the plate interface. We evaluated the change in vertical deformation rate for two scenarios: (1) a synchronous shift in the orientation of the locked zone as PHS plate motion shifts and (2) a delayed shift in the orientation of the locked zone following the shift in plate motion. Observed changes in the uplift/subsidence pattern are better explained by scenario (2), suggesting that recent (< 1 My) deformation in the Kanto Basin shows a lag in crustal response to the plate motion shift. We also calculated stress accumulation rates and found a good match with observed earthquake mechanisms, which shows that intraplate earthquakes serve to release stress accumulated through long-term plate interactions.

Cognitive-behavioral therapy induces sensorimotor and specific electrocortical changes in chronic tic and Tourette's disorder.

PubMed

Morand-Beaulieu, Simon; O'Connor, Kieron P; Sauvé, Geneviève; Blanchet, Pierre J; Lavoie, Marc E

2015-12-01

Tic disorders, such as the Gilles de la Tourette syndrome and persistent tic disorder, are neurodevelopmental movement disorders involving impaired motor control. Hence, patients show repetitive unwanted muscular contractions in one or more parts of the body. A cognitive-behavioral therapy, with a particular emphasis on the psychophysiology of tic expression and sensorimotor activation, can reduce the frequency and intensity of tics. However, its impact on motor activation and inhibition is not fully understood. To study the effects of a cognitive-behavioral therapy on electrocortical activation, we recorded the event-related potentials (ERP) and lateralized readiness potentials (LRP), before and after treatment, of 20 patients with tic disorders and 20 healthy control participants (matched on age, sex and intelligence), during a stimulus-response compatibility inhibition task. The cognitive-behavioral therapy included informational, awareness training, relaxation, muscle discrimination, cognitive restructuration and relapse prevention strategies. Our results revealed that prior to treatment; tic patients had delayed stimulus-locked LRP onset latency, larger response-locked LRP peak amplitude, and a frontal overactivation during stimulus inhibition processing. Both stimulus-locked LRP onset latency and response-locked LRP peak amplitude normalized after the cognitive behavioral therapy completion. However, the frontal overactivation related to inhibition remained unchanged following therapy. Our results showed that P300 and reaction times are sensitive to stimulus-response compatibility, but are not related to tic symptoms. Secondly, overactivity of the frontal LPC and impulsivity in TD patients were not affected by treatment. Finally, CBT had normalizing effects on the activation of the pre-motor and motor cortex in TD patients. These results imply specific modifications of motor processes following therapy, while inhibition processes remained unchanged. Given that LRPs are partially generated within the sensorimotor and supplementary motor area, the reported reduction in tic frequency and improvements of LRPs components suggest that CBT induced a physiological change in patients' motor area. Copyright © 2015 Elsevier Ltd. All rights reserved.

Masked and unmasked error-related potentials during continuous control and feedback

NASA Astrophysics Data System (ADS)

Lopes Dias, Catarina; Sburlea, Andreea I.; Müller-Putz, Gernot R.

2018-06-01

The detection of error-related potentials (ErrPs) in tasks with discrete feedback is well established in the brain–computer interface (BCI) field. However, the decoding of ErrPs in tasks with continuous feedback is still in its early stages. Objective. We developed a task in which subjects have continuous control of a cursor’s position by means of a joystick. The cursor’s position was shown to the participants in two different modalities of continuous feedback: normal and jittered. The jittered feedback was created to mimic the instability that could exist if participants controlled the trajectory directly with brain signals. Approach. This paper studies the electroencephalographic (EEG)—measurable signatures caused by a loss of control over the cursor’s trajectory, causing a target miss. Main results. In both feedback modalities, time-locked potentials revealed the typical frontal-central components of error-related potentials. Errors occurring during the jittered feedback (masked errors) were delayed in comparison to errors occurring during normal feedback (unmasked errors). Masked errors displayed lower peak amplitudes than unmasked errors. Time-locked classification analysis allowed a good distinction between correct and error classes (average Cohen-, average TPR  =  81.8% and average TNR  =  96.4%). Time-locked classification analysis between masked error and unmasked error classes revealed results at chance level (average Cohen-, average TPR  =  60.9% and average TNR  =  58.3%). Afterwards, we performed asynchronous detection of ErrPs, combining both masked and unmasked trials. The asynchronous detection of ErrPs in a simulated online scenario resulted in an average TNR of 84.0% and in an average TPR of 64.9%. Significance. The time-locked classification results suggest that the masked and unmasked errors were indistinguishable in terms of classification. The asynchronous classification results suggest that the feedback modality did not hinder the asynchronous detection of ErrPs.

Cross delay line sensor characterization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Owens, Israel J; Remelius, Dennis K; Tiee, Joe J

There exists a wealth of information in the scientific literature on the physical properties and device characterization procedures for complementary metal oxide semiconductor (CMOS), charge coupled device (CCD) and avalanche photodiode (APD) format detectors. Numerous papers and books have also treated photocathode operation in the context of photomultiplier tube (PMT) operation for either non imaging applications or limited night vision capability. However, much less information has been reported in the literature about the characterization procedures and properties of photocathode detectors with novel cross delay line (XDL) anode structures. These allow one to detect single photons and create images by recordingmore » space and time coordinate (X, Y & T) information. In this paper, we report on the physical characteristics and performance of a cross delay line anode sensor with an enhanced near infrared wavelength response photocathode and high dynamic range micro channel plate (MCP) gain (> 10{sup 6}) multiplier stage. Measurement procedures and results including the device dark event rate (DER), pulse height distribution, quantum and electronic device efficiency (QE & DQE) and spatial resolution per effective pixel region in a 25 mm sensor array are presented. The overall knowledge and information obtained from XDL sensor characterization allow us to optimize device performance and assess capability. These device performance properties and capabilities make XDL detectors ideal for remote sensing field applications that require single photon detection, imaging, sub nano-second timing response, high spatial resolution (10's of microns) and large effective image format.« less

CMOS image sensor-based immunodetection by refractive-index change.

PubMed

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

Drop casting of stiffness gradients for chip integration into stretchable substrates

NASA Astrophysics Data System (ADS)

Naserifar, Naser; LeDuc, Philip R.; Fedder, Gary K.

2017-04-01

Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems.

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

CMOS image sensors as an efficient platform for glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-07

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

DTIC Science & Technology

2013-04-01

structures; v) developed CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vi) also engaged in a partnership with...CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vii. exploring approaches to enhance spontaneous emission in...size and bandwidth, we are exploring phase-change materials and, in particular, vanadium dioxide. VO2 undergoes an insulator-to-metal phase transition

Registration of Large Motion Blurred Images

DTIC Science & Technology

2016-05-09

in handling the dynamics of the capturing system, for example, a drone. CMOS sensors , used in recent times, when employed in these cameras produce...handling the dynamics of the capturing system, for example, a drone. CMOS sensors , used in recent times, when employed in these cameras produce two types...blur in the captured image when there is camera motion during exposure. However, contemporary CMOS sensors employ an electronic rolling shutter (RS

Cargo Movement Operations System (CMOS). Final Software Design Document. Increment III. (PC Unix - Air Force Configuration)

DTIC Science & Technology

1991-07-03

required changes to this matrix. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...this appendix should be updated to include all necessary changes. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDD3-0004 PROGRAM OFFICE

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Organic-on-silicon complementary metal–oxide–semiconductor colour image sensors

PubMed Central

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-01

Complementary metal–oxide–semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor. PMID:25578322

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.