Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

MEMS-Electronic-Photonic Heterogeneous Integrated FMCW Ladar Source

DTIC Science & Technology

2015-12-18

CMOS  ICs  in  a  seamless  manner,  and...the   heterogeneous   integration   is   to   leverage   on   the   available   foundry   capabilities   ( CMOS   and...dies”   or   “known  good  wafers”).  We  have  adopted  a  three-­‐dimensional  (3D)  integration  strategy:  The   CMOS

A low-power CMOS readout IC design for bolometer applications

NASA Astrophysics Data System (ADS)

Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

2017-02-01

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Data encryption standard ASIC design and development report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

2003-10-01

This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATMmore » or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.« less

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

A CMOS VLSI IC for Real-Time Opto-Electronic Two-Dimensional Histogram Generation

DTIC Science & Technology

1993-12-01

large scale integration) design; MAGIC ; CMOS; optics; image processing; 93 16. PRICE CODE 17. SECURITY CLASSIFICATION 18. SECURITY CLASSIFICATiON 19...1. Sun SPARCstation ............. .............. 6 2. Magic .................. ................... 6 a. Peg ................. .................. 7 b...38 v APPENDIX B. MAGIC CELL LAYOUTS .... ............ .. 39 APPENDIX C: SIMULATION DATA ....... ............. .. 56 A. FINITE STATE MACHINE

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.

PubMed

Ali, Imran; Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

2018-05-14

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of -16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

PubMed Central

Rikhan, Behnam Samadpoor; Kim, Dong-Gyu; Lee, Dong-Soo; Rehman, Muhammad Riaz Ur; Abbasizadeh, Hamed; Asif, Muhammad; Lee, Minjae; Yang, Youngoo; Lee, Kang-Yoon

2018-01-01

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard. PMID:29757996

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

PubMed

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

PubMed Central

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

2014-01-01

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

A CAM-based LZ data compression IC

NASA Technical Reports Server (NTRS)

Winters, K.; Bode, R.; Schneider, E.

1993-01-01

A custom CMOS processor is introduced that implements the Data Compression Lempel-Ziv (DCLZ) standard, a variation of the LZ2 Algorithm. This component presently achieves a sustained compression and decompression rate of 10 megabytes/second by employing an on-chip content-addressable memory for string table storage.

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

PubMed

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

PubMed

Oh, Sungjin; Ahn, Jae-Hyun; Lee, Sangmin; Ko, Hyoungho; Seo, Jong Mo; Goo, Yong-Sook; Cho, Dong-il Dan

2015-01-01

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 μm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 μ m × 55 μm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 μA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

Narrowband Interference Suppression in Spread Spectrum Communication Systems

DTIC Science & Technology

1995-12-01

receiver input. As stated earlier, these waveforms must be sampled to obtain the discrete time sequences. The sampling theorem states: A bandlimited...From the FFT chips, the data is passed to a Plessey PDSP16330 Pythagoras Processor. The 16330 is a high-speed digital CMOS IC that converts real and

Si light-emitting device in integrated photonic CMOS ICs

NASA Astrophysics Data System (ADS)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

An RFID-based on-lens sensor system for long-term IOP monitoring.

PubMed

Hsu, Shun-Hsi; Chiou, Jin-Chern; Liao, Yu-Te; Yang, Tzu-Sen; Kuei, Cheng-Kai; Wu, Tsung-Wei; Huang, Yu-Chieh

2015-01-01

In this paper, an RFID-based on-lens sensor system is proposed for noninvasive long-term intraocular pressure monitoring. The proposed sensor IC, fabricated in a 0.18um CMOS process, consists of capacitive sensor readout circuitry, RFID communication circuits, and digital processing units. The sensor IC is integrated with electroplating capacitive sensors and a receiving antenna on the contact lens. The sensor IC can be wirelessly powered, communicate with RFID compatible equipment, and perform IOP measurement using on-lens capacitive sensor continuously from a 2cm distance while the incident power from an RFID reader is 20 dBm. The proposed system is compatible to Gen2 RFID protocol, extending the flexibility and reducing the self-developed firmware efforts.

Wireless Interconnects for Intra-chip & Inter-chip Transmission

NASA Astrophysics Data System (ADS)

Narde, Rounak Singh

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications.

PubMed

Bhattacharyya, Mayukh; Gruenwald, Waldemar; Jansen, Dirk; Reindl, Leonhard; Aghassi-Hagmann, Jasmin

2018-05-07

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

PubMed Central

Gruenwald, Waldemar; Jansen, Dirk; Aghassi-Hagmann, Jasmin

2018-01-01

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches. PMID:29735939

A Miniaturized 0.78-mW/cm2 Autonomous Thermoelectric Energy-Harvesting Platform for Biomedical Sensors.

PubMed

Rozgic, Dejan; Markovic, Dejan

2017-08-01

In order to use thermoelectric energy harvesters (TEHs) as a truly autonomous energy source for size-limited sensing applications, it is essential to improve the power conversion efficiency and energy density. This study presents a thin-film, array-based TEH with a surface area of 0.83 cm 2 . The TEH autonomously supplies a power management IC fabricated in a 65-nm CMOS technology. The IC utilizes a single-inductor topology with integrated analog maximum power point tracking (MPPT), resulting in a 68% peak end-to-end efficiency (92% converter efficiency) and less than 20-ms MPPT. In an in-vivo test, a 645-μW regulated output power (effective 3.5 K of temperature gradient) was harvested from a rat implanted with our TEH, demonstrating true energy independence in a real environment while showing a 7.9 × improvement in regulated power density compared to the state-of-the-art. The system showed autonomous operation down to 65-mV TEH input.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

PubMed

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Sensitivity-Enhanced CMOS Phase Luminometry System Using Xerogel-Based Sensors.

PubMed

Lei Yao; Khan, R; Chodavarapu, V P; Tripathi, V S; Bright, F V

2009-10-01

We present the design and implementation of a phase luminometry sensor system with improved and tunable detection sensitivity achieved using a complementary metal-oxide semiconductor (CMOS) integrated circuit. We use sol-gel derived xerogel thin films as an immobilization media to house oxygen (O2) responsive luminescent molecules. The sensor operates on the principal of phase luminometry wherein a sinusoidal modulation signal is used to excite the luminophores encapsulated in the porous xerogel films and the corresponding phase shift of the emission signals is monitored. The phase shift is directly related to excited state lifetimes of the luminophores which in turn are related to the concentration of the target analyte species present in the vicinity of the luminophores. The CMOS IC, which consists of a 16 times 16 high-gain phototransistor array, current-to-voltage converter, amplifier and tunable phase shift detector, consumes an average power of 14 mW with 5-V power supply operating at a 38-kHz modulation frequency. The output of the IC is a dc voltage that corresponds to the detected luminescence phase shift with respect to the excitation signal. As a prototype, we demonstrate an oxygen sensor system by encapsulating the luminophore tris(4,7-diphenyl-1,10-phenanthroline)ruthenium(II) within the xerogel matrices. The sensor system showed a fast response on the order of few seconds and we obtained a detection sensitivity of 118 mV per 1% change in O2 concentration. The system demonstrates a novel concept to tune and improve the detection sensitivity for specific concentrations of the target analyte in many biomedical monitoring applications.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

The optical design of 3D ICs for smartphone and optro-electronics sensing module

NASA Astrophysics Data System (ADS)

Huang, Jiun-Woei

2018-03-01

Smartphone require limit space for image system, current lens, used in smartphones are refractive type, the effective focal length is limited the thickness of phone physical size. Other, such as optro-electronics sensing chips, proximity optical sensors, and UV indexer chips are integrated into smart phone with limit space. Due to the requirement of multiple lens in smartphone, proximity optical sensors, UV indexer and other optro-electronics sensing chips in a limited space of CPU board in future smart phone, optro-electronics 3D IC's integrated with optical lens or components may be a key technology for 3 C products. A design for reflective lens is fitted to CMOS, proximity optical sensors, UV indexer and other optro-electronics sensing chips based on 3-D IC. The reflective lens can be threes times of effective focal lens, and be able to resolve small object. The system will be assembled and integrated in one 3-D IC more easily.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

A low-power RFID integrated circuits for intelligent healthcare systems.

PubMed

Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

2010-11-01

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

A novel multi-actuation CMOS RF MEMS switch

NASA Astrophysics Data System (ADS)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Cargo Movement Operations System (CMOS). Software Test Description

DTIC Science & Technology

1990-10-28

resulting in errors in paragraph numbers and titles. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...location to test the update of the truck manifest. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Ionizing doses and displacement damage testing of COTS CMOS imagers

NASA Astrophysics Data System (ADS)

Bernard, Frédéric; Petit, Sophie; Courtade, Sophie

2017-11-01

CMOS sensors begin to be a credible alternative to CCD sensors in some space missions. However, technology evolution of CMOS sensors is much faster than CCD one's. So a continuous technology evaluation is needed for CMOS imagers. Many of commercial COTS (Components Off The Shelf) CMOS sensors use organic filters, micro-lenses and non rad-hard technologies. An evaluation of the possibilities offered by such technologies is interesting before any custom development. This can be obtained by testing commercial COTS imagers. This article will present electro-optical performances evolution of off the shelves CMOS imagers after Ionizing Doses until 50kRad(Si) and Displacement Damage environment tests (until 1011 p/cm2 at 50 MeV). Dark current level and non uniformity evolutions are compared and discussed. Relative spectral response measurement and associated evolution with irradiation will also be presented and discussed. Tests have been performed on CNES detection benches.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

PREFACE: The Second Conference on Microelectronics, Microsystems and Nanotechnology

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.; Papanikolaou, Nikos; Tsamis, Christos

2005-01-01

The Second Conference on Microelectronics, Microsystems and Nanotechnology took place at the National Centre for Scientific Research `Demokritos', in Athens, Greece, between 14 and 17 November 2004. The conference was organized by the Institute of Microelectronics (IMEL) with the aim to bring together scientists and engineers working in the above exciting fields in an interactive forum. The conference included 45 oral presentations with 9 invited papers and was attended by 146 participants from 16 countries. The topics covered were nanotechnologies, quantum devices, sensors, micro- and nano-systems, semiconductor devices, C-MOS fabrication and characterization techniques, new materials, and IC design. Quantum devices and nanostructured materials attracted considerable attention. Both theoretical and experimental studies of metallic and semiconducting quantum systems were presented, with emphasis on their applications in electronics, optoelectronics, and nanocrystal memory devices. Another exciting topic was the recent developments in biocompatible lithographic processes for applications in biosensors. In particular novel processes for bio-friendly lithography, together with innovations in Si sensors for applications in medicine and food industry were presented. Recent developments and perspectives in CMOS technology towards the ultimate limit were also discussed. The conference covered issues and concepts of IC design with two invited talks on RF design and cryptography.The conference included presentations from several companies active in the field of microelectronics and systems in Greece.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

NASA Astrophysics Data System (ADS)

Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

2009-09-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

Low mass MEMS/NEMS switch for a substitute of CMOS transistor using single-walled carbon nanotube thin film

NASA Astrophysics Data System (ADS)

Jang, Min-Woo

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied to reduce power dissipation of deeply scaled CMOS ICs. One possible candidate is the electrostatic electromechanical switch, which could be fabricated with conventional CMOS processing techniques. They have critical advantages compared to CMOS devices such as almost zero standby leakage in the off-state due to the absence of a pn junction and a gate oxide, as well as excellent drive current in the on-state due to a metallic channel. Despite their excellent standby power dissipation, the electrostatic MEMS/NEMS switches have not been considered as a viable replacement for CMOS devices due to their large mechanical delay. Moreover, previous literature reveals that their pull-in voltage and switching speed are strongly proportional to each other. This reduces their potential advantage. However, in this work, we theoretically and experimentally demonstrated that the use of single-walled carbon nanotube (SWNT) with very low mass density and strong mechanical properties could provide a route to move off of the conventional trend with respect to the pull-in voltage / switching speed tradeoff observed in the literature. We fabricated 2-terminal fixed- beam switches with aligned composite SWNT thin films. In this work, layer-by-layer (LbL) self-assembly and dielectrophoresis were selected for aligned-composite SWNT thin film deposition. The dense membranes were successfully patterned to form submicron beams by e-beam lithography and oxygen plasma etching. Fixed-fixed beam switches using these membranes successfully operated with approximately 600 psec switching delay and as low as a 3 V dc pull-in. From this we confirmed that the SWNT-based thin films have the potential to make fast MEMS switches with a low operation voltage due to its low mass density and high stiffness. However, the copolymer caused a serious reliability issue and a copolymer-free SWNT film deposition method was developed by replacing positive copolymer with a dispersion of positively functionalized SWNTs. The electrical and physical properties of pure single-walled carbon nanotube thin films deposited through a copolymer-free LbL self-assembly process are then discussed. The film thickness was proportional to the number of dipping cycles. The film resistivity was estimated as 2.19x10-3 Ω-cm after thermal treatments were performed. The estimated specific contact resistance to gold electrodes was 6.33x10-9 Ω-m2 from contact chain measurements. The fabricated 3-terminal MEMS switches using these films functioned as a beam for multiple switching cycles with a 4.5V pull-in voltage, which was operated like a 2-input NAND gate. The SWNT-based thin film switch is promising for a variety of applications to high-end nanoelectronics and high- performance MEMS/NEMS.

Improving yield and reliability of FIB modifications using electrical testing

NASA Astrophysics Data System (ADS)

Desplats, Romain; Benbrik, Jamel; Benteo, Bruno; Perdu, Philippe

1998-08-01

Focused Ion Beam technology has two main areas of application for ICs: modification and preparation for technological analysis. The most solicited area is modification. This involves physically modifying a circuit by cutting lines and creating new ones in order to change the electrical function of the circuit. IC planar technologies have an increasing number of metal interconnections making FIB modifications more complex and decreasing their changes of success. The yield of FIB operations on ICs reflects a downward trend that imposes a greater number of circuits to be modified in order to successfully correct a small number of them. This requires extended duration, which is not compatible with production line turn around times. To respond to this problem, two solutions can be defined: either, reducing the duration of each FIB operation or increasing the success rate of FIB modifications. Since reducing the time depends mainly on FIB operator experience, insuring a higher success rate represents a more crucial aspect as both experienced and novice operators could benefit from this improvement. In order to insure successful modifications, it is necessary to control each step of a FIB operation. To do this, we have developed a new method using in situ electrical testing which has a direct impact on the yield of FIB modifications. We will present this innovative development through a real case study of a CMOS ASIC for high-speed communications. Monitoring the electrical behavior at each step in a FIB operation makes it possible to reduce the number of circuits to be modified and consequently reduces system costs thanks to better yield control. Knowing the internal electrical behavior also gives us indications about the impact on reliability of FIB modified circuits. Finally, this approach can be applied to failure analysis and FIB operations on flip chip circuits.

Tests of commercial colour CMOS cameras for astronomical applications

NASA Astrophysics Data System (ADS)

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

Improved Signal Chains for Readout of CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1982-01-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Architecture for VLSI design of Reed-Solomon encoders

NASA Astrophysics Data System (ADS)

Liu, K. Y.

1982-02-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

The next generation in optical transport semiconductors: IC solutions at the system level

NASA Astrophysics Data System (ADS)

Gomatam, Badri N.

2005-02-01

In this tutorial overview, we survey some of the challenging problems facing Optical Transport and their solutions using new semiconductor-based technologies. Advances in 0.13um CMOS, SiGe/HBT and InP/HBT IC process technologies and mixed-signal design strategies are the fundamental breakthroughs that have made these solutions possible. In combination with innovative packaging and transponder/transceiver architectures IC approaches have clearly demonstrated enhanced optical link budgets with simultaneously lower (perhaps the lowest to date) cost and manufacturability tradeoffs. This paper will describe: *Electronic Dispersion Compensation broadly viewed as the overcoming of dispersion based limits to OC-192 links and extending link budgets, *Error Control/Coding also known as Forward Error Correction (FEC), *Adaptive Receivers for signal quality monitoring for real-time estimation of Q/OSNR, eye-pattern, signal BER and related temporal statistics (such as jitter). We will discuss the theoretical underpinnings of these receiver and transmitter architectures, provide examples of system performance and conclude with general market trends. These Physical layer IC solutions represent a fundamental new toolbox of options for equipment designers in addressing systems level problems. With unmatched cost and yield/performance tradeoffs, it is expected that IC approaches will provide significant flexibility in turn, for carriers and service providers who must ultimately manage the network and assure acceptable quality of service under stringent cost constraints.

Thermal annealing of radiation damage in CMOS ICs in the temperature range -140 C to +375 C

NASA Technical Reports Server (NTRS)

Danchenko, V.; Fang, P. H.; Brashears, S. S.

1982-01-01

Annealing of radiation damage was investigated in the commercial, Z- and J-processes of the RCA CD4007A ICs in the temperature range from -140 C to +375 C. Tempering curves were analyzed for activation energies of thermal annealing, following irradiation at -140 C. It was found that at -140 C, the radiation-induced shifts in the threshold potentials were similar for all three processes. The radiation hardness of the Z- and J-process is primarily due to rapid annealing of radiation damage at room temperature. In the region -140 to 20 C, no dopant-dependent charge trapping is seen, similar to that observed at higher temperatures. In the unbiased Z-process n-channels, after 1 MeV electron irradiation, considerable negative charge remains in the gate oxide.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Design and assessment of a robust voltage amplifier with 2.5 GHz GBW and >100 kGy total dose tolerance

NASA Astrophysics Data System (ADS)

Verbeeck, J.; Leroux, P.; Steyaert, M.

2011-01-01

A differential voltage amplifier with a gain-bandwidth product of 2.5Ghz and using adaptive biasing has been designed in a standard CMOS technology and assessed under radiation and temperature variations. The principle used in this ASIC will be employed in the design of a Gbps TIA with improved tolerance for γ-irradiation and temperature for an optical instrumentation (LIDAR) receiver aiming at operation in harsh environments. The voltage amplifier was tested under gamma radiation and features a gain degradation of merely 4.5% up to a total dose of 100kGy. In order to verify the radiation effects on the IC, the threshold voltage shift of the separate transistors has been investigated. Temperature characterization has shown that the amplifier features a reduction of the voltage gain by only 5.6% for a temperature range of -40 till 130 °C.

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

PubMed

Cho, Hwasuk; Son, Hyunwoo; Seong, Kihwan; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2018-02-01

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

Efficient coupling between Si3N4 photonic and hybrid slot-based CMOS plasmonic waveguide

NASA Astrophysics Data System (ADS)

Chatzianagnostou, E.; Ketzaki, D.; Manolis, A.; Dabos, G.; Pleros, N.; Markey, L.; Weeber, J.-C.; Dereux, A.; Giesecke, A. L.; Porschatis, C.; Tsiokos, D.

2018-02-01

Bringing photonics and electronics into a common integration platform can unleash unprecedented performance capabilities in data communication and sensing applications. Plasmonics were proposed as the key technology that can merge ultra-fast photonics and low-dimension electronics due to their metallic nature and their unique ability to guide light at sub-wavelength scales. However, inherent high losses of plasmonics in conjunction with the use of CMOS incompatible metals like gold and silver which are broadly utilized in plasmonic applications impede their broad utilization in Photonic Integrated Circuits (PICs). To overcome those limitations and fully exploit the profound benefits of plasmonics, they have to be developed along two technology directives. 1) Selectively co-integrate nanoscale plasmonics with low-loss photonics and 2) replace noble metals with alternative CMOS-compatible counterparts accelerating volume manufacturing of plasmo-photonic ICs. In this context, a hybrid plasmo-photonic structure utilizing the CMOS-compatible metals Aluminum (Al) and Copper (Cu) is proposed to efficiently transfer light between a low-loss Si3N4 photonic waveguide and a hybrid plasmonic slot waveguide. Specifically, a Si3N4 strip waveguide (photonic part) is located below a metallic slot (plasmonic part) forming a hybrid structure. This configuration, if properly designed, can support modes that exhibit quasi even or odd symmetry allowing power exchange between the two parts. According to 3D FDTD simulations, the proposed directional coupling scheme can achieve coupling efficiencies at 1550nm up to 60% and 74% in the case of Al and Cu respectively within a coupling length of just several microns.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases.

PubMed

Guo, Jing; Ng, Waichiu; Yuan, Jie; Li, Suwen; Chan, Mansun

2016-06-01

Microelectrode array (MEA) can be used in the study of neurodegenerative diseases by monitoring the chemical neurotransmitter release and the electrical potential simultaneously at the cellular level. Currently, the MEA technology is migrating to more electrodes and higher electrode density, which raises power and area constraints on the design of acquisition IC. In this paper, we report the design of a 200-channel dual-mode acquisition IC with highly efficient usage of power and area. Under the constraints of target noise and fast settling, the current channel design saves power by including a novel current buffer biased in discrete time (DT) before the TIA (transimpedance amplifier). The 200 channels are sampled at 20 kS/s and quantized by column-wise SAR ADCs. The prototype IC was fabricated in a 0.18 μm CMOS process. Silicon measurements show the current channel has 21.6 pArms noise with cyclic voltammetry (CV) and 0.48 pArms noise with constant amperometry (CA) while consuming 12.1 μW . The voltage channel has 4.07 μVrms noise in the bandwidth of 100 kHz and 0.2% nonlinearity while consuming 9.1 μW. Each channel occupies 0.03 mm(2) area, which is among the smallest.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1981-01-01

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

A multi-channel instrumentation system for biosignal recording.

PubMed

Yu, Hong; Li, Pengfei; Xiao, Zhiming; Peng, Chung-Ching; Bashirullah, Rizwan

2008-01-01

This paper reports a highly integrated battery operated multi-channel instrumentation system intended for physiological signal recording. The mixed signal IC has been fabricated in standard 0.5microm 5V 3M-2P CMOS process and features 32 instrumentation amplifiers, four 8b SAR ADCs, a wireless power interface with Li-ion battery charger, low power bidirectional telemetry and FSM controller with power gating control for improved energy efficiency. The chip measures 3.2mm by 4.8mm and dissipates approximately 2.1mW when fully operational.

Design of high-speed burst mode clock and data recovery IC for passive optical network

NASA Astrophysics Data System (ADS)

Yan, Minhui; Hong, Xiaobin; Huang, Wei-Ping; Hong, Jin

2005-09-01

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the behavioural model. The newly designed BMCDR utilizes the 0.18um standard CMOS technology and is shown to be capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The developed behaviour model is verified by comparing with the detailed circuit simulation.

Driver-receiver combined optical transceiver modules for bidirectional optical interconnection

NASA Astrophysics Data System (ADS)

Park, Hyo-Hoon; Kang, Sae-Kyoung; Kim, Do-Won; Nga, Nguyen T. H.; Hwang, Sung-Hwan; Lee, Tae-Woo

2008-02-01

We review a bidirectional optical link scheme for memory-interface applications. A driver-receiver combined optical transceiver (TRx) modules was demonstrated on an optical printed-circuit board (OPCB) platform. To select the bidirectional electric input/output signals, a driver-receiver combined TRx IC with a switching function was designed in 0.18-μm CMOS technology. The TRx IC was integrated with VCSEL/PD chips for optical link in the TRx module. The optical TRx module was assembled on a fiber-embedded OPCB, employing a 90°-bent fiber connector for 90° deflection of light beams between the TRx module and the OPCB. The TRx module and the 90° connector were passively assembled on the OPCB, using ferrule-type guide pins/ holes. Employing these constituent components, the bidirectional optical link between a pair of TRx modules has been successfully demonstrated up to 1.25 Gb/s on the OPCB.

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

NASA Astrophysics Data System (ADS)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-11-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed.

Total Ionizing Dose Effects in Bipolar and BiCMOS Devices

NASA Technical Reports Server (NTRS)

Chavez, Rosa M.; Rax, Bernard G.; Scheick, Leif Z.; Johnston, Allan H.

2005-01-01

This paper describes total ionizing dose (TID) test results performed at JPL. Bipolar and BiCMOS device samples were tested exhibiting significant degradation and failures at different irradiation levels. Linear technology which is susceptible to low-dose dependency (ELDRS) exhibited greater damage for devices tested under zero bias condition.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

SOI-CMOS Process for Monolithic, Radiation-Tolerant, Science-Grade Imagers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, George; Lee, Adam

In Phase I, Voxtel worked with Jazz and Sandia to document and simulate the processes necessary to implement a DH-BSI SOI CMOS imaging process. The development is based upon mature SOI CMOS process at both fabs, with the addition of only a few custom processing steps for integration and electrical interconnection of the fully-depleted photodetectors. In Phase I, Voxtel also characterized the Sandia process, including the CMOS7 design rules, and we developed the outline of a process option that included a “BOX etch”, that will permit a “detector in handle” SOI CMOS process to be developed The process flows weremore » developed in cooperation with both Jazz and Sandia process engineers, along with detailed TCAD modeling and testing of the photodiode array architectures. In addition, Voxtel tested the radiation performance of the Jazz’s CA18HJ process, using standard and circular-enclosed transistors.« less

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

NASA Technical Reports Server (NTRS)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

Action potential-based MEA platform for in vitro screening of drug-induced cardiotoxicity using human iPSCs and rat neonatal myocytes.

PubMed

Jans, Danny; Callewaert, Geert; Krylychkina, Olga; Hoffman, Luis; Gullo, Francesco; Prodanov, Dimiter; Braeken, Dries

2017-09-01

Drug-induced cardiotoxicity poses a negative impact on public health and drug development. Cardiac safety pharmacology issues urged for the preclinical assessment of drug-induced ventricular arrhythmia leading to the design of several in vitro electrophysiological screening assays. In general, patch clamp systems allow for intracellular recordings, while multi-electrode array (MEA) technology detect extracellular activity. Here, we demonstrate a complementary metal oxide semiconductor (CMOS)-based MEA system as a reliable platform for non-invasive, long-term intracellular recording of cardiac action potentials at high resolution. Quinidine (8 concentrations from 10 -7 to 2.10 -5 M) and verapamil (7 concentrations from 10 -11 to 10 -5 M) were tested for dose-dependent responses in a network of cardiomyocytes. Electrophysiological parameters, such as the action potential duration (APD), rates of depolarization and repolarization and beating frequency were assessed. In hiPSC, quinidine prolonged APD with EC 50 of 2.2·10 -6 M. Further analysis indicated a multifactorial action potential prolongation by quinidine: (1) decreasing fast repolarization with IC 50 of 1.1·10 -6 M; (2) reducing maximum upstroke velocity with IC 50 of 2.6·10 -6 M; and (3) suppressing spontaneous activity with EC 50 of 3.8·10 -6 M. In rat neonatal cardiomyocytes, verapamil blocked spontaneous activity with EC 50 of 5.3·10 -8 M and prolonged the APD with EC 50 of 2.5·10 -8 M. Verapamil reduced rates of fast depolarization and repolarization with IC 50 s of 1.8 and 2.2·10 -7 M, respectively. In conclusion, the proposed action potential-based MEA platform offers high quality and stable long-term recordings with high information content allowing to characterize multi-ion channel blocking drugs. We anticipate application of the system as a screening platform to efficiently and cost-effectively test drugs for cardiac safety. Copyright © 2017 Elsevier Inc. All rights reserved.

Test results for SEU and SEL immune memory circuits

NASA Technical Reports Server (NTRS)

Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.

1993-01-01

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Llamas: Large-area microphone arrays and sensing systems

NASA Astrophysics Data System (ADS)

Sanz-Robinson, Josue

Large-area electronics (LAE) provides a platform to build sensing systems, based on distributing large numbers of densely spaced sensors over a physically-expansive space. Due to their flexible, "wallpaper-like" form factor, these systems can be seamlessly deployed in everyday spaces. They go beyond just supplying sensor readings, but rather they aim to transform the wealth of data from these sensors into actionable inferences about our physical environment. This requires vertically integrated systems that span the entirety of the signal processing chain, including transducers and devices, circuits, and signal processing algorithms. To this end we develop hybrid LAE / CMOS systems, which exploit the complementary strengths of LAE, enabling spatially distributed sensors, and CMOS ICs, providing computational capacity for signal processing. To explore the development of hybrid sensing systems, based on vertical integration across the signal processing chain, we focus on two main drivers: (1) thin-film diodes, and (2) microphone arrays for blind source separation: 1) Thin-film diodes are a key building block for many applications, such as RFID tags or power transfer over non-contact inductive links, which require rectifiers for AC-to-DC conversion. We developed hybrid amorphous / nanocrystalline silicon diodes, which are fabricated at low temperatures (<200 °C) to be compatible with processing on plastic, and have high current densities (5 A/cm2 at 1 V) and high frequency operation (cutoff frequency of 110 MHz). 2) We designed a system for separating the voices of multiple simultaneous speakers, which can ultimately be fed to a voice-command recognition engine for controlling electronic systems. On a device level, we developed flexible PVDF microphones, which were used to create a large-area microphone array. On a circuit level we developed localized a-Si TFT amplifiers, and a custom CMOS IC, for system control, sensor readout and digitization. On a signal processing level we developed an algorithm for blind source separation in a real, reverberant room, based on beamforming and binary masking. It requires no knowledge about the location of the speakers or microphones. Instead, it uses cluster analysis techniques to determine the time delays for beamforming; thus, adapting to the unique acoustic environment of the room.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

PubMed Central

Jeong, Gyu-Seob

2017-01-01

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies. PMID:28841154

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

PubMed

Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

2017-08-25

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

ZnO on nickel RF micromechanical resonators for monolithic wireless communication applications

NASA Astrophysics Data System (ADS)

Wei, Mian; Avila, Adrian; Rivera, Ivan; Baghelani, Masoud; Wang, Jing

2017-05-01

On-chip integrability of high-Q RF passives alongside CMOS transistors is crucial for the implementation of monolithic radio transceivers. One of the most significant bottlenecks in back-end-of-line (BEoL) integration of MEMS devices on CMOS processed wafers is their relatively low thermal budget, which is less than that required for typical MEMS material deposition processes. This paper investigates electroplated nickel as a structural material for piezoelectrically-transduced resonators to demonstrate ZnO-on-nickel resonators with a CMOS-compatible low temperature process for the first time. Aside from the obvious manufacturing cost benefit, electroplated nickel is a reasonable substitute for polycrystalline or single crystal silicon and thin-film microcrystalline diamond device layers, while realizing decent acoustic velocity and moderate Q. Electroplated nickel has been already adopted by MEMSCAP, a multi-user MEMS process foundry, in its MetalMUMPs process. Furthermore, it is observed that a localized annealing process through Joule heating can be exploited to significantly improve the effective mechanical quality factor for the ZnO-on-nickel resonators, which is still lower than the reported AlN resonators. This work demonstrates ZnO-on-nickel piezoelectrically-actuated MEMS resonators and resonator arrays by using an IC compatible low temperature process. There is room for performance improvement by lowering the acoustic energy losses in the ZnO and nickel layers.

A 25μm pitch LWIR focal plane array with pixel-level 15-bit ADC providing high well capacity and targeting 2mK NETD

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Peizerat, Arnaud; Tchagaspanian, Michael; de Borniol, Eric; Bisotto, Sylvette; Mollard, Laurent; Castelein, Pierre; Zanatta, Jean-Paul; Maillart, Patrick; Zecri, Michel; Peyrard, Jean-Christophe

2010-04-01

CEA Leti has recently developed a new readout IC (ROIC) with pixel-level ADC for cooled infrared focal plane arrays (FPAs). It operates at 50Hz frame rate in a snapshot Integrate-While-Read (IWR) mode. It targets applications that provide a large amount of integrated charge thanks to a long integration time. The pixel-level analog-to-digital conversion is based on charge packets counting. This technique offers a large well capacity that paves the way for a breakthrough in NETD performances. The 15 bits ADC resolution preserves the excellent detector SNR at full well (3Ge-). These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The ROIC, featuring a 320x256 array with 25μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The IC has been hybridized to a LWIR detector fabricated using our in-house HgCdTe process. The first electro-optical test results of the detector dewar assembly are presented. They validate both the pixel-level ADC concept and its circuit implementation. Finally, the benefit of this LWIR FPA in terms of NETD performance is demonstrated.

Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

PubMed Central

White, Daniel J.; William, Peter E.; Hoffman, Michael W.; Balkir, Sina

2013-01-01

A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouriér Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC). Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0.13 μm complementary metal-oxide-silicon (CMOS) integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction. PMID:23892765

An ultra low-power front-end IC for wearable health monitoring system.

PubMed

Yu-Pin Hsu; Zemin Liu; Hella, Mona M

2016-08-01

This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

113Gb/s (10 x 11.3Gb/s) ultra-low power EAM driver array.

PubMed

Vaernewyck, Renato; Bauwelinck, Johan; Yin, Xin; Pierco, Ramses; Verbrugghe, Jochen; Torfs, Guy; Li, Zhisheng; Qiu, Xing-Zhi; Vandewege, Jan; Cronin, Richard; Borghesani, Anna; Moodie, David

2013-01-14

This paper presents an ultra-low power SiGe BiCMOS IC for driving a 10 channel electro-absorption modulator (EAM) array at 113Gb/s for wavelength division multiplexing passive optical network (WDM-PON) applications. With an output swing of 2.5V(pp), the EAM driver array consumes only 2.2W or 220mW per channel, 50% below the state of the art. Both the output swing and bias are configurable between 1.5 and 3.0V(pp) and 0.75-2.15V respectively.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

X-ray performance of 0.18 µm CMOS APS test arrays for solar observation

NASA Astrophysics Data System (ADS)

Dryer, B. J.; Holland, A. D.; Jerram, P.; Sakao, Taro

2012-07-01

Solar-C is the third generation solar observatory led by JAXA. The accepted ‘Plan-B’ payload calls for a radiation-hard solar-staring photon-counting x-ray spectrometer. CMOS APS technology offers advantages over CCDs for such an application such as increased radiation hardness and high frame rate (instrument target of 1000 fps). Looking towards the solution of a bespoke CMOS APS, this paper reports the x-ray spectroscopy performance, concentrating on charge collection efficiency and split event analysis, of two baseline e2v CMOS APSs not designed for x-ray performance, the EV76C454 and the Ocean Colour Imager (OCI) test array. The EV76C454 is an industrial 5T APS designed for machine vision, available back and front illuminated. The OCI test arrays have varying pixel design across the chips, but are 4T, back illuminated and have thin low-resistivity and thick high-resistivity variants. The OCI test arrays’ pixel variants allow understanding of how pixel design can affect x-ray performance.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

PubMed

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

A Review on Passive and Integrated Near-Field Microwave Biosensors

PubMed Central

Guha, Subhajit; Jamal, Farabi Ibne

2017-01-01

In this paper we review the advancement of passive and integrated microwave biosensors. The interaction of microwave with biological material is discussed in this paper. Passive microwave biosensors are microwave structures, which are fabricated on a substrate and are used for sensing biological materials. On the other hand, integrated biosensors are microwave structures fabricated in standard semiconductor technology platform (CMOS or BiCMOS). The CMOS or BiCMOS sensor technology offers a more compact sensing approach which has the potential in the future for point of care testing systems. Various applications of the passive and the integrated sensors have been discussed in this review paper. PMID:28946617

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Fundamental performance differences between CMOS and CCD imagers, part IV

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.

Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

NASA Technical Reports Server (NTRS)

Maximow, B.

1976-01-01

An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

NASA Technical Reports Server (NTRS)

Cable, J. S.; Carter, J. R.; Witteles, A. A.

1986-01-01

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Electrical Characterization of Hughes HCMP 1852D and RCA CDP1852D 8-bit, CMOS, I/O Ports

NASA Technical Reports Server (NTRS)

Stokes, R. L.

1979-01-01

Twenty-five Hughes HCMP 1852D and 25 RCA CDP1852D 8-bit, CMOS, I/O port microcircuits underwent electrical characterization tests. All electrical measurements were performed on a Tektronix S-3260 Test System. Before electrical testing, the devices were subjected to a 168-hour burn-in at 125 C with the inputs biased at 10V. Four of the Hughes parts became inoperable during testing. They exhibited functional failures and out-of-range parametric measurements after a few runs of the test program.

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

NASA Technical Reports Server (NTRS)

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

Apparatus and method for defect testing of integrated circuits

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Efficient design of CMOS TSC checkers

NASA Technical Reports Server (NTRS)

Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

1990-01-01

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

A new physical unclonable function architecture

NASA Astrophysics Data System (ADS)

Chuang, Bai; Xuecheng, Zou; Kui, Dai

2015-03-01

This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 °C, and supply voltage variation from 1.7 to 1.9 V. Project supported by the National Natural Science Foundation of China (No. 61376031).

UV-visible sensors based on polymorphous silicon

NASA Astrophysics Data System (ADS)

Guedj, Cyril S.; Cabarrocas, Pere R. i.; Massoni, Nicolas; Moussy, Norbert; Morel, Damien; Tchakarov, Svetoslav; Bonnassieux, Yvan

2003-09-01

UV-based imaging systems can be used for low-altitude rockets detection or biological agents identification (for instance weapons containing ANTHRAX). Compared to conventional CCD technology, CMOS-based active pixel sensors provide several advantages, including excellent electro-optical performances, high integration, low voltage operation, low power consumption, low cost, long lifetime, and robustness against environment. The monolithic integration of UV, visible and infrared detectors on the same uncooled CMOS smart system would therefore represent a major advance in the combat field, for characterization and representation of targets and backgrounds. In this approach, we have recently developped a novel technology using polymorphous silicon. This new material, fully compatible with above-IC silicon technology, is made of nanometric size ordered domains embedded in an amorphous matrix. The typical quantum efficiency of detectors made of this nano-material reach up to 80 % at 550 nm and 30 % in the UV range, depending of the design and the growth parameters. Furthermore, a record dark current of 20 pA/cm2 at -3 V has been reached. In addition, this new generation of sensors is significantly faster and more stable than their amorphous silicon counterparts. In this paper, we will present the relationship between the sensor technology and the overall performances.

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, H.; Benoit, M.; Chen, H.

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE PAGES

Liu, H.; Benoit, M.; Chen, H.; ...

2017-01-11

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

PubMed

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

Subpixel mapping and test beam studies with a HV2FEI4v2 CMOS-Sensor-Hybrid Module for the ATLAS inner detector upgrade

NASA Astrophysics Data System (ADS)

Bisanz, T.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.

2017-08-01

The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33× 125 μm2, while the pixels of the read-out chip have a pitch of 50× 250 μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Preliminary performances measured on a CMOS long linear array for space application

NASA Astrophysics Data System (ADS)

Renard, Christophe; Artinian, Armand; Dantes, Didier; Lepage, Gérald; Diels, Wim

2017-11-01

This paper presents the design and the preliminary performances of a CMOS linear array, resulting from collaboration between Alcatel Alenia Space and Cypress Semiconductor BVBA, which takes advantage of emerging potentialities of CMOS technologies. The design of the sensor is presented: it includes 8000 panchromatic pixels with up to 25 rows used in TDI mode, and 4 lines of 2000 pixels for multispectral imaging. Main system requirements and detector tradeoffs are recalled, and the preliminary test results obtained with a first generation prototype are summarized and compared with predicted performances.

Finding a roadmap to achieve large neuromorphic hardware systems

PubMed Central

Hasler, Jennifer; Marr, Bo

2013-01-01

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time. PMID:24058330

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents

PubMed Central

Din, Amad Ud; Chandrathna, Seneke Chamith; Lee, Jong-Wook

2017-01-01

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power POUT of 564 μW and a rectifier output voltage VRECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a POUT of 288 μW and a VRECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier. PMID:28422085

Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents.

PubMed

Din, Amad Ud; Chandrathna, Seneke Chamith; Lee, Jong-Wook

2017-04-19

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power P OUT of 564 μW and a rectifier output voltage V RECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a P OUT of 288 μW and a V RECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

MT3250BA: a 320×256-50µm snapshot microbolometer ROIC for high-resistance detector arrays

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Akin, Tayfun

2013-06-01

This paper reports the development of a new microbolometer readout integrated circuit (MT3250BA) designed for high-resistance detector arrays. MT3250BA is the first microbolometer readout integrated circuit (ROIC) product from Mikro-Tasarim Ltd., which is a fabless IC design house specialized in the development of monolithic CMOS imaging sensors and ROICs for hybrid photonic imaging sensors and microbolometers. MT3250BA has a format of 320 × 256 and a pixel pitch of 50 µm, developed with a system-on-chip architecture in mind, where all the timing and biasing for this ROIC are generated on-chip without requiring any external inputs. MT3250BA is a highly configurable ROIC, where many of its features can be programmed through a 3-wire serial interface allowing on-the-fly configuration of many ROIC features. MT3250BA has 2 analog video outputs and 1 analog reference output for pseudo-differential operation, and the ROIC can be programmed to operate in the 1 or 2-output modes. A unique feature of MT3250BA is that it performs snapshot readout operation; therefore, the image quality will only be limited by the thermal time constant of the detector pixels, but not by the scanning speed of the ROIC, as commonly found in the conventional microbolometer ROICs performing line-by-line (rolling-line) readout operation. The signal integration is performed at the pixel level in parallel for the whole array, and signal integration time can be programmed from 0.1 µs up to 100 ms in steps of 0.1 µs. The ROIC is designed to work with high-resistance detector arrays with pixel resistance values higher than 250 kΩ. The detector bias voltage can be programmed on-chip over a 2 V range with a resolution of 1 mV. The ROIC has a measured input referred noise of 260 µV rms at 300 K. The ROIC can be used to build a microbolometer infrared sensor with an NETD value below 100 mK using a microbolometer detector array fabrication technology with a high detector resistance value (≥ 250 KΩ), a high TCR value (≥ 2.5 % / K), and a sufficiently low pixel thermal conductance (Gth ≤ 20 nW / K). The ROIC uses a single 3.3 V supply voltage and dissipates less than 75 mW in the 1-output mode at 60 fps. MT3250BA is fabricated using a mixed-signal CMOS process on 200 mm CMOS wafers, and tested wafers are available with test data and wafer map. A USB based compact test electronics and software are available for quick evaluation of this new microbolometer ROIC.

Product assurance technology for custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seco, Joao; Depauw, Nicolas

2011-02-15

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissuemore » contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.« less

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

Defect-sensitivity analysis of an SEU immune CMOS logic family

NASA Technical Reports Server (NTRS)

Ingermann, Erik H.; Frenzel, James F.

1992-01-01

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Magnan, Pierre; Bernard, Frédéric; Rolland, Guy; Saint-Pé, Olivier; Huger, Nicolas; Corbière, Franck

2008-02-01

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 μm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed.

Reliability evaluation of CMOS RAMs

NASA Astrophysics Data System (ADS)

Salvo, C. J.; Sasaki, A. T.

The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure rates at 100 C were 0.54 x 10 to the -5th failures/hour for the 1K RAM and 0.21 x 10 to the -5th failures/hour for the 4K RAM. Only minimal electrostatic discharge damage was noted in the devices when they were subjected to multiple pulses at 1000 Vdc, and redesign of the 7 Vdc quiescent parameter of the 4K RAM is expected to raise its field threshold voltage.

Tracking Detectors in the STAR Experiment at RHIC

NASA Astrophysics Data System (ADS)

Wieman, Howard

2015-04-01

The STAR experiment at RHIC is designed to measure and identify the thousands of particles produced in 200 Gev/nucleon Au on Au collisions. This talk will focus on the design and construction of two of the main tracking detectors in the experiment, the TPC and the Heavy Flavor Tracker (HFT) pixel detector. The TPC is a solenoidal gas filled detector 4 meters in diameter and 4.2 meters long. It provides precise, continuous tracking and rate of energy loss in the gas (dE/dx) for particles at + - 1 units of pseudo rapidity. The tracking in a half Tesla magnetic field measures momentum and dE/dX provides particle ID. To detect short lived particles tracking close to the point of interaction is required. The HFT pixel detector is a two-layered, high resolution vertex detector located at a few centimeters radius from the collision point. It determines origins of the tracks to a few tens of microns for the purpose of extracting displaced vertices, allowing the identification of D mesons and other short-lived particles. The HFT pixel detector uses detector chips developed by the IPHC group at Strasbourg that are based on standard IC Complementary Metal-Oxide-Semiconductor (CMOS) technology. This is the first time that CMOS pixel chips have been incorporated in a collider application.

Attentional gating models of object substitution masking.

PubMed

Põder, Endel

2013-11-01

Di Lollo, Enns, and Rensink (2000) proposed the computational model of object substitution (CMOS) to explain their experimental results with sparse visual maskers. This model supposedly is based on reentrant hypotheses testing in the visual system, and the modeled experiments are believed to demonstrate these reentrant processes in human vision. In this study, I analyze the main assumptions of this model. I argue that CMOS is a version of the attentional gating model and that its relationship with reentrant processing is rather illusory. The fit of this model to the data indicates that reentrant hypotheses testing is not necessary for the explanation of object substitution masking (OSM). Further, the original CMOS cannot predict some important aspects of the experimental data. I test 2 new models incorporating an unselective processing (divided attention) stage; these models are more consistent with data from OSM experiments. My modeling shows that the apparent complexity of OSM can be reduced to a few simple and well-known mechanisms of perception and memory. PsycINFO Database Record (c) 2013 APA, all rights reserved.

A 41 ps ASIC time-to-digital converter for physics experiments

NASA Astrophysics Data System (ADS)

Russo, Stefano; Petra, Nicola; De Caro, Davide; Barbarino, Giancarlo; Strollo, Antonio G. M.

2011-12-01

We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on a synchronous counter and an asynchronous fine interpolator. The fine part of the measurement is obtained using NORA inverters that provide improved resolution. A prototype IC was fabricated in 180 nm CMOS technology. Experimental measurements show that proposed TDC features 41 ps resolution associated with 0.35LSB differential non-linearity, 0.77LSB integral non-linearity and a negligible single shot precision. The whole dynamic range is equal to 18 μs. The proposed TDC is designed using a flash architecture that reduces dead time. Data reported in the paper show that our design is well suited for present and future particle physics experiments.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Overview of CMOS process and design options for image sensor dedicated to space applications

NASA Astrophysics Data System (ADS)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

NASA Astrophysics Data System (ADS)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier injection modulators and light-emitting diodes (LED) with drive voltage requirements below 1.5V. Measurement results show an optical link based on a 70MHz red LED work well at 300Mbps by using the pre-emphasis driver module. A traveling wave electrode (TWE) modulator structure is presented, including a novel design methodology to address process limitations imposed by a commercial silicon fabrication technology. Results from 3D full wave EM simulation demonstrate the application of the design methodology to achieve specifications, including phase velocity matching, insertion loss, and impedance matching. Results show the HBT-based TWE-EAM system has the bandwidth higher than 60GHz.

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be recovered using several methods; for example, using tunable transmission line lengths in the amplifier or using a variable supply voltage. This concept of estimating process variation has been demonstrated in Agilent Design System (ADS).

Cargo Movement Operations System (CMOS) Preliminary Software Test Description, Increment II

DTIC Science & Technology

1991-06-26

occurred within this shall statement. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS...COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED ( ] ORIGINATOR CONTROL NUMBER: STD1-0004 PROGRAM OFFICE CONTROL NUMBER...ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] SYSTEM ENVIRONMENT STD The following comment is related

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

PubMed

Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

2017-02-01

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

Dynamical Competition of IC-Industry Clustering from Taiwan to China

NASA Astrophysics Data System (ADS)

Tsai, Bi-Huei; Tsai, Kuo-Hui

2009-08-01

Most studies employ qualitative approach to explore the industrial clusters; however, few research has objectively quantified the evolutions of industry clustering. The purpose of this paper is to quantitatively analyze clustering among IC design, IC manufacturing as well as IC packaging and testing industries by using the foreign direct investment (FDI) data. The Lotka-Volterra system equations are first adopted here to capture the competition or cooperation among such three industries, thus explaining their clustering inclinations. The results indicate that the evolution of FDI into China for IC design industry significantly inspire the subsequent FDI of IC manufacturing as well as IC packaging and testing industries. Since IC design industry lie in the upstream stage of IC production, the middle-stream IC manufacturing and downstream IC packing and testing enterprises tend to cluster together with IC design firms, in order to sustain a steady business. Finally, Taiwan IC industry's FDI amount into China is predicted to cumulatively increase, which supports the industrial clustering tendency for Taiwan IC industry. Particularly, the FDI prediction of Lotka-Volterra model performs superior to that of the conventional Bass model after the forecast accuracy of these two models are compared. The prediction ability is dramatically improved as the industrial mutualism among each IC production stage is taken into account.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

A miniature batteryless health and usage monitoring system based on hybrid energy harvesting

NASA Astrophysics Data System (ADS)

Huang, Chenling; Chakrabartty, Shantanu

2011-04-01

The cost and size of the state-of-the-art health and usage monitoring systems (HUMS) are determined by capacity of on-board energy storage which limits their large scale deployment. In this paper, we present a miniature low-cost mechanical HUMS integrated circuit (IC) based on the concept of hybrid energy harvesting where continuous monitoring is achieved by self-powering, where as the programming, localization and communication with the sensor is achieved using remote RF powering. The self-powered component of the proposed HUMS is based on our previous result which used a controllable hot electron injection on floatinggate transistor as an ultra-low power signal processor. We show that the HUMS IC can seamlessly switch between different energy harvesting modes based on the availability of ambient RF power and that the configuration, programming and communication functions can be remotely performed without physically accessing the HUMS device. All the measured results presented in this paper have been obtained from prototypes fabricated in a 0.5 micron standard CMOS process and the entire system has been successfully integrated on a 1.5cm x 1.5cm package.

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

PubMed Central

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-01-01

With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field. PMID:27879789

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

NASA Astrophysics Data System (ADS)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

NASA Astrophysics Data System (ADS)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

New generation QuIC assays for prion seeding activity.

PubMed

Orrù, Christina D; Wilham, Jason M; Vascellari, Sarah; Hughson, Andrew G; Caughey, Byron

2012-01-01

The ability of abnormal TSE-associated forms of PrP to seed the formation of amyloid fibrils from recombinant PrP(Sen) has served as the basis for several relatively rapid and highly sensitive tests for prion diseases. These tests include rPrP-PMCA (rPMCA), standard quaking-induced conversion (S-QuIC), amyloid seeding assay (ASA), real-time QuIC (RT-QuIC) and enhanced QuIC (eQuIC). Here, we summarize recent improvements in the RT-QuIC-based assays that enhance the practicality, sensitivity and quantitative attributes of assays QuIC and promote the detection of prion seeding activity in dilute, inhibitor-laden fluids such as blood plasma.

SIERRA - A 3-D device simulator for reliability modeling

NASA Astrophysics Data System (ADS)

Chern, Jue-Hsien; Arledge, Lawrence A., Jr.; Yang, Ping; Maeda, John T.

1989-05-01

SIERRA is a three-dimensional general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under dc, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5x to 7x speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and dynamic random-access memory single-event-upset studies is described.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

Laboratory and Sky Testing Results for the TIS H4RG-10 4k x 4k, 10 micron Visible CMOS-Hybrid Detector

DTIC Science & Technology

2007-01-01

extremely important. In this paper we discuss Teledyne Imaging Sensor’s (TIS)# H4RG-10 CMOS-Hybrid Focal Plane Assembly (FPA)@. The H4RG-10 is a...receipt of a loaned engineering grade unit ( EGU ) that was used initially for electronics set up and testing. We plan on irradiating the EGU at a later...persistence, since exposure to high energy proton flux that is typical of the space environment results in the generation of new traps in the detector

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1980-01-01

The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

Surface-modified CMOS IC electrochemical sensor array targeting single chromaffin cells for highly parallel amperometry measurements.

PubMed

Huang, Meng; Delacruz, Joannalyn B; Ruelas, John C; Rathore, Shailendra S; Lindau, Manfred

2018-01-01

Amperometry is a powerful method to record quantal release events from chromaffin cells and is widely used to assess how specific drugs modify quantal size, kinetics of release, and early fusion pore properties. Surface-modified CMOS-based electrochemical sensor arrays allow simultaneous recordings from multiple cells. A reliable, low-cost technique is presented here for efficient targeting of single cells specifically to the electrode sites. An SU-8 microwell structure is patterned on the chip surface to provide insulation for the circuitry as well as cell trapping at the electrode sites. A shifted electrode design is also incorporated to increase the flexibility of the dimension and shape of the microwells. The sensitivity of the electrodes is validated by a dopamine injection experiment. Microwells with dimensions slightly larger than the cells to be trapped ensure excellent single-cell targeting efficiency, increasing the reliability and efficiency for on-chip single-cell amperometry measurements. The surface-modified device was validated with parallel recordings of live chromaffin cells trapped in the microwells. Rapid amperometric spikes with no diffusional broadening were observed, indicating that the trapped and recorded cells were in very close contact with the electrodes. The live cell recording confirms in a single experiment that spike parameters vary significantly from cell to cell but the large number of cells recorded simultaneously provides the statistical significance.

SEM contour based metrology for microlens process studies in CMOS image sensor technologies

NASA Astrophysics Data System (ADS)

Lakcher, Amine; Ostrovsky, Alain; Le-Gratiet, Bertrand; Berthier, Ludovic; Bidault, Laurent; Ducoté, Julien; Jamin-Mornet, Clémence; Mortini, Etienne; Besacier, Maxime

2018-03-01

From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow). Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product. The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Ma, Wuying; Huang, Shaoyan

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a {sup 60}Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo responsemore » non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.« less

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Wang, Zujun; Ma, Wuying; Huang, Shaoyan; Yao, Zhibin; Liu, Minbo; He, Baoping; Liu, Jing; Sheng, Jiangkun; Xue, Yuan

2016-03-01

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

Fully Integrated Biopotential Acquisition Analog Front-End IC

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

2015-01-01

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

CMOS output buffer wave shaper

NASA Technical Reports Server (NTRS)

Albertson, L.; Whitaker, S.; Merrell, R.

1990-01-01

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

NASA Astrophysics Data System (ADS)

Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

2012-04-01

In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

Modeling and evaluation of a high-resolution CMOS detector for cone-beam CT of the extremities.

PubMed

Cao, Qian; Sisniega, Alejandro; Brehler, Michael; Stayman, J Webster; Yorkston, John; Siewerdsen, Jeffrey H; Zbijewski, Wojciech

2018-01-01

Quantitative assessment of trabecular bone microarchitecture in extremity cone-beam CT (CBCT) would benefit from the high spatial resolution, low electronic noise, and fast scan time provided by complementary metal-oxide semiconductor (CMOS) x-ray detectors. We investigate the performance of CMOS sensors in extremity CBCT, in particular with respect to potential advantages of thin (<0.7 mm) scintillators offering higher spatial resolution. A cascaded systems model of a CMOS x-ray detector incorporating the effects of CsI:Tl scintillator thickness was developed. Simulation studies were performed using nominal extremity CBCT acquisition protocols (90 kVp, 0.126 mAs/projection). A range of scintillator thickness (0.35-0.75 mm), pixel size (0.05-0.4 mm), focal spot size (0.05-0.7 mm), magnification (1.1-2.1), and dose (15-40 mGy) was considered. The detectability index was evaluated for both CMOS and a-Si:H flat-panel detector (FPD) configurations for a range of imaging tasks emphasizing spatial frequencies associated with feature size aobj. Experimental validation was performed on a CBCT test bench in the geometry of a compact orthopedic CBCT system (SAD = 43.1 cm, SDD = 56.0 cm, matching that of the Carestream OnSight 3D system). The test-bench studies involved a 0.3 mm focal spot x-ray source and two CMOS detectors (Dalsa Xineos-3030HR, 0.099 mm pixel pitch) - one with the standard CsI:Tl thickness of 0.7 mm (C700) and one with a custom 0.4 mm thick scintillator (C400). Measurements of modulation transfer function (MTF), detective quantum efficiency (DQE), and CBCT scans of a cadaveric knee (15 mGy) were obtained for each detector. Optimal detectability for high-frequency tasks (feature size of ~0.06 mm, consistent with the size of trabeculae) was ~4× for the C700 CMOS detector compared to the a-Si:H FPD at nominal system geometry of extremity CBCT. This is due to ~5× lower electronic noise of a CMOS sensor, which enables input quantum-limited imaging at smaller pixel size. Optimal pixel size for high-frequency tasks was <0.1 mm for a CMOS, compared to ~0.14 mm for an a-Si:H FPD. For this fine pixel pitch, detectability of fine features could be improved by using a thinner scintillator to reduce light spread blur. A 22% increase in detectability of 0.06 mm features was found for the C400 configuration compared to C700. An improvement in the frequency at 50% modulation (f 50 ) of MTF was measured, increasing from 1.8 lp/mm for C700 to 2.5 lp/mm for C400. The C400 configuration also achieved equivalent or better DQE as C700 for frequencies above ~2 mm -1 . Images of cadaver specimens confirmed improved visualization of trabeculae with the C400 sensor. The small pixel size of CMOS detectors yields improved performance in high-resolution extremity CBCT compared to a-Si:H FPDs, particularly when coupled with a custom 0.4 mm thick scintillator. The results indicate that adoption of a CMOS detector in extremity CBCT can benefit applications in quantitative imaging of trabecular microstructure in humans. © 2017 American Association of Physicists in Medicine.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

A 400 MHz Wireless Neural Signal Processing IC With 625 $\\times$ On-Chip Data Reduction and Reconfigurable BFSK/QPSK Transmitter Based on Sequential Injection Locking.

PubMed

Teng, Kok-Hin; Wu, Tong; Liu, Xiayun; Yang, Zhi; Heng, Chun-Huat

2017-06-01

An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, and feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK transmitter (TX) at MICS/MedRadio band is incorporated to support different data rate requirement. By using an Exponential Component-Polynomial Component (EC-PC) spike processing unit with an incremental principal component analysis (IPCA) engine, the detection of neural spikes with poor SNR is possible while achieving 625× data reduction. For the TX, a dual-channel at 401 MHz and 403.8 MHz are supported by applying sequential injection locked techniques while attaining phase noise of -102 dBc/Hz at 100 kHz offset. From the measurement, error vector magnitude (EVM) of 4.60%/9.55% with power amplifier (PA) output power of -15 dBm is achieved for the QPSK at 8 Mbps and the BFSK at 12.5 kbps. Fabricated in 65 nm CMOS with an active area of 1 mm 2 , the design consumes a total current of 5  ∼ 5.6 mA with a maximum energy efficiency of 0.7 nJ/b.

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

NASA Technical Reports Server (NTRS)

White, Mark; Vu, Duc; Nguyen, Duc; Ruiz, Ron; Chen, Yuan; Bernstein, Joseph B.

2006-01-01

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Standardizing Imperata cylindrica--source material for quality allergen preparations.

PubMed

Bijli, Kaiser M; Singh, B P; Sridhara, Susheela; Gaur, S N; Arora, Naveen

2002-02-01

Tropical countries experience wide variations in daytime temperature and relative humidity. This affects the quality of the source material used for allergen extracts. The present study was undertaken to standardize the processing and preservation conditions of Imperata cylindrica grass pollen. I. cylindrica (Ic) inflorescence were freeze-dried, pollens sieved out and stored at -70 degrees C (IcA). Alternatively, the inflorescence were dried at room temperature and then at 37 degrees C, pollens sieved out and stored at 4 degrees C (IcB). The extracts prepared in PBS were analyzed in vivo by skin tests and in vitro by immunochemical methods. Reduced SDS-PAGE revealed 37 protein bands in IcA extract and 23 in IcB extract. IgE immunoblot with a pool of sera from Ic hypersensitive patients showed 30 allergenic bands in IcA and 14 in IcB. Immunoblot using anti-Ic rabbit sera revealed 33 antigenic bands in IcA and 22 in IcB. In both blots, the IcA extract exhibited sharp bands and the IcB extract exhibited diffuse bands. ELISA, ELISA inhibition and skin test procedures showed that IcA extracts had a higher potency than IcB extracts. Extracts prepared from -70 degrees C processed and preserved pollens (IcA) are allergenically more potent and contain a greater number of major and minor allergens than IcB extracts.

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Soli, G. A.; Buehler, M. G.

1991-01-01

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

ERIC Educational Resources Information Center

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

Effects of a 6-month exercise program pilot study on walking economy, peak physiological characteristics, and walking performance in patients with peripheral arterial disease.

PubMed

Crowther, Robert G; Leicht, Anthony S; Spinks, Warwick L; Sangla, Kunwarjit; Quigley, Frank; Golledge, Jonathan

2012-01-01

The purpose of this study was to examine the effects of a 6-month exercise program on submaximal walking economy in individuals with peripheral arterial disease and intermittent claudication (PAD-IC). Participants (n = 16) were randomly allocated to either a control PAD-IC group (CPAD-IC, n = 6) which received standard medical therapy, or a treatment PAD-IC group (TPAD-IC; n = 10) which took part in a supervised exercise program. During a graded treadmill test, physiological responses, including oxygen consumption, were assessed to calculate walking economy during submaximal and maximal walking performance. Differences between groups at baseline and post-intervention were analyzed via Kruskal-Wallis tests. At baseline, CPAD-IC and TPAD-IC groups demonstrated similar walking performance and physiological responses. Postintervention, TPAD-IC patients demonstrated significantly lower oxygen consumption during the graded exercise test, and greater maximal walking performance compared to CPAD-IC. These preliminary results indicate that 6 months of regular exercise improves both submaximal walking economy and maximal walking performance, without significant changes in maximal walking economy. Enhanced walking economy may contribute to physiological efficiency, which in turn may improve walking performance as demonstrated by PAD-IC patients following regular exercise programs.

Sensitive albuminuria analysis using dye-binding based test strips.

PubMed

Delanghe, Joris R; Himpe, Jonas; De Cock, Naomi; Delanghe, Sigurd; De Herde, Kevin; Stove, Veronique; Speeckaert, Marijn M

2017-08-01

Populations at increased risk for chronic kidney disease should be screened for albuminuria. Possibilities of advanced urine strip readers based on complementary metal oxide semiconductor (CMOS) sensor technology were investigated for obtaining quantitative albuminuria results. Reflectance data of test strips (Sysmex UFC 3500 reader+CMOS) were compared with albuminuria (BNII) and with proteinuria (Cobas 8000). Urinary creatinine was assayed using a Jaffe-based creatinine assay (Cobas 8000). Calibration curve was made between 11.5 and 121.5mg/L with detection limit of 5.5mg/L. Within-run CV values of reflectance data were 0.21% (UC-Control L; 10mg/L) and 0.37% (UC-Control H; >150mg/L) for albumin, and 0.71%/3.97% for creatinine. Between-run CV values were 0.24%/0.42% for albumin and 0.93%/5.13% for creatinine. A strong correlation (r=0.92) was obtained between albuminuria (BNII) and protein strip reflectance data. Creatinine reflectance data correlated well with Jaffe-based urinary creatinine data (r=0.90). Albumin:creatinine ratio obtained by test strip and by wet chemistry showed a good correlation (r=0.59). Carbamylated, glycated and partially hydrolyzed isoforms of albumin could be detected by test strip. Dye-binding based albumin test strip assay in combination with a CMOS based reader would potentially allow quantitative analysis of albuminuria and determination of albumin:creatinine ratio. Copyright © 2017 Elsevier B.V. All rights reserved.

Infection control and prevention practices implemented to reduce transmission risk of Middle East respiratory syndrome-coronavirus in a tertiary care institution in Saudi Arabia.

PubMed

Butt, Taimur S; Koutlakis-Barron, Irene; AlJumaah, Suliman; AlThawadi, Sahar; AlMofada, Saleh

2016-05-01

Transmission of Middle East respiratory syndrome-coronavirus (MERS-CoV) among health care workers (HCWs) and patients has been documented with mortality rate approximating 36%. We propose advanced infection control measures (A-IC) used in conjunction with basic infection control measures (B-IC) help reduce pathogen transmission. B-IC include standard and transmission-based precautions. A-IC are initiatives implemented within our center to enhance effectiveness of B-IC. Study effectiveness of combining B-IC and A-IC to prevent transmission of MERS-CoV to HCWs. A retrospective observational study was undertaken. A-IC measures include administrative support with daily rounds; infection control risk assessment; timely screening, isolation, and specimen analysis; collaboration; epidemic planning; stockpiling; implementation of contingency plans; full personal protective equipment use for advanced airway management; use of a real-time electronic isolation flagging system; infection prevention and control team on-call protocols; pretransfer MERS-CoV testing; and education. A total of 874 real-time polymerase chain reaction MERS-CoV tests were performed during the period beginning July 1, 2013, and ending January 31, 2015. Six hundred ninety-four non-HCWs were tested, of these 16 tested positive for MERS-CoV and their infection was community acquired. Sixty-nine percent of the confirmed MERS-CoV-positive cases were men, with an average age of 56 years (range, 19-84 years). Of the total tested for MERS-CoV, 180 individuals were HCWs with zero positivity. Adhering to a combination of B-IC and A-IC reduces the risk of MERS-CoV transmission to HCWs. Copyright © 2016 Association for Professionals in Infection Control and Epidemiology, Inc. Published by Elsevier Inc. All rights reserved.

Emergency Department Management of Suspected Calf-Vein Deep Venous Thrombosis: A Diagnostic Algorithm

PubMed Central

Kitchen, Levi; Lawrence, Matthew; Speicher, Matthew; Frumkin, Kenneth

2016-01-01

Introduction Unilateral leg swelling with suspicion of deep venous thrombosis (DVT) is a common emergency department (ED) presentation. Proximal DVT (thrombus in the popliteal or femoral veins) can usually be diagnosed and treated at the initial ED encounter. When proximal DVT has been ruled out, isolated calf-vein deep venous thrombosis (IC-DVT) often remains a consideration. The current standard for the diagnosis of IC-DVT is whole-leg vascular duplex ultrasonography (WLUS), a test that is unavailable in many hospitals outside normal business hours. When WLUS is not available from the ED, recommendations for managing suspected IC-DVT vary. The objectives of the study is to use current evidence and recommendations to (1) propose a diagnostic algorithm for IC-DVT when definitive testing (WLUS) is unavailable; and (2) summarize the controversy surrounding IC-DVT treatment. Discussion The Figure combines D-dimer testing with serial CUS or a single deferred FLUS for the diagnosis of IC-DVT. Such an algorithm has the potential to safely direct the management of suspected IC-DVT when definitive testing is unavailable. Whether or not to treat diagnosed IC-DVT remains widely debated and awaiting further evidence. Conclusion When IC-DVT is not ruled out in the ED, the suggested algorithm, although not prospectively validated by a controlled study, offers an approach to diagnosis that is consistent with current data and recommendations. When IC-DVT is diagnosed, current references suggest that a decision between anticoagulation and continued follow-up outpatient testing can be based on shared decision-making. The risks of proximal progression and life-threatening embolization should be balanced against the generally more benign natural history of such thrombi, and an individual patient’s risk factors for both thrombus propagation and complications of anticoagulation. PMID:27429688

Emergency Department Management of Suspected Calf-Vein Deep Venous Thrombosis: A Diagnostic Algorithm.

PubMed

Kitchen, Levi; Lawrence, Matthew; Speicher, Matthew; Frumkin, Kenneth

2016-07-01

Unilateral leg swelling with suspicion of deep venous thrombosis (DVT) is a common emergency department (ED) presentation. Proximal DVT (thrombus in the popliteal or femoral veins) can usually be diagnosed and treated at the initial ED encounter. When proximal DVT has been ruled out, isolated calf-vein deep venous thrombosis (IC-DVT) often remains a consideration. The current standard for the diagnosis of IC-DVT is whole-leg vascular duplex ultrasonography (WLUS), a test that is unavailable in many hospitals outside normal business hours. When WLUS is not available from the ED, recommendations for managing suspected IC-DVT vary. The objectives of the study is to use current evidence and recommendations to (1) propose a diagnostic algorithm for IC-DVT when definitive testing (WLUS) is unavailable; and (2) summarize the controversy surrounding IC-DVT treatment. The Figure combines D-dimer testing with serial CUS or a single deferred FLUS for the diagnosis of IC-DVT. Such an algorithm has the potential to safely direct the management of suspected IC-DVT when definitive testing is unavailable. Whether or not to treat diagnosed IC-DVT remains widely debated and awaiting further evidence. When IC-DVT is not ruled out in the ED, the suggested algorithm, although not prospectively validated by a controlled study, offers an approach to diagnosis that is consistent with current data and recommendations. When IC-DVT is diagnosed, current references suggest that a decision between anticoagulation and continued follow-up outpatient testing can be based on shared decision-making. The risks of proximal progression and life-threatening embolization should be balanced against the generally more benign natural history of such thrombi, and an individual patient's risk factors for both thrombus propagation and complications of anticoagulation.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Diagnostic reliability of an immunochromatographic test for Chagas disease screening at a primary health care centre in a rural endemic area

PubMed Central

Mendicino, Diego; Stafuza, Mariana; Colussi, Carlina; del Barco, Mónica; Streiger, Mirtha; Moretti, Edgardo

2014-01-01

Many patients with Chagas disease live in remote communities that lack both equipment and trained personnel to perform a diagnosis by conventional serology (CS). Thus, reliable tests suitable for use under difficult conditions are required. In this study, we evaluated the ability of personnel with and without laboratory skills to perform immunochromatographic (IC) tests to detect Chagas disease at a primary health care centre (PHCC). We examined whole blood samples from 241 patients and serum samples from 238 patients. Then, we calculated the percentage of overall agreement (POA) between the two groups of operators for the sensitivity (S), specificity (Sp) and positive (PPV) and negative (NPV) predictive values of IC tests compared to CS tests. We also evaluated the level of agreement between ELISAs and indirect haemagglutination (IHA) tests. The readings of the IC test results showed 100% agreement (POA = 1). The IC test on whole blood showed the following values: S = 87.3%; Sp = 98.8%; PPV = 96.9% and NPV = 95.9%. Additionally, the IC test on serum displayed the following results: S = 95.7%; Sp = 100%; PPV = 100% and NPV = 98.2%. Using whole blood, the agreement with ELISA was 96.3% and the agreement with IHA was 94.1%. Using serum, the agreement with ELISA was 97.8% and the agreement with IHA was 96.6%. The IC test performance with serum samples was excellent and demonstrated its usefulness in a PHCC with minimal equipment. If the IC test S value and NPV with whole blood are improved, then this test could also be used in areas lacking laboratories or specialised personnel. PMID:25466624

Electron trapping in rad-hard RCA IC's irradiated with electrons and gamma rays

NASA Technical Reports Server (NTRS)

Danchenko, V.; Brashears, S. S.; Fang, P. H.

1984-01-01

Enhanced electron trapping has been observed in n-channels of rad-hard CMOS devices due to electron and gamma-ray irradiation. Room-temperature annealing results in a positive shift in the threshold potential far beyond its initial value. The slope of the annealing curve immediately after irradiation was found to depend strongly on the gate bias applied during irradiation. Some dependence was also observed on the electron dose rate. No clear dependence on energy and shielding over a delidded device was observed. The threshold shift is probably due to electron trapping at the radiation-induced interface states and tunneling of electrons through the oxide-silicon energy barrier to fill the radiation-induced electron traps. A mathematical analysis, based on two parallel annealing kinetics, hole annealing and electron trapping, is applied to the data for various electron dose rates.

Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

PubMed

Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

2015-07-16

We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.

PubMed

Massengill, L W; Mundie, D B

1992-01-01

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

NASA Astrophysics Data System (ADS)

Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

2011-01-01

In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

Hyperspectral CMOS imager

NASA Astrophysics Data System (ADS)

Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

2017-11-01

CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

Detection of pointing errors with CMOS-based camera in intersatellite optical communications

NASA Astrophysics Data System (ADS)

Yu, Si-yuan; Ma, Jing; Tan, Li-ying

2005-01-01

For very high data rates, intersatellite optical communications hold a potential performance edge over microwave communications. Acquisition and Tracking problem is critical because of the narrow transmit beam. A single array detector in some systems performs both spatial acquisition and tracking functions to detect pointing errors, so both wide field of view and high update rate is required. The past systems tend to employ CCD-based camera with complex readout arrangements, but the additional complexity reduces the applicability of the array based tracking concept. With the development of CMOS array, CMOS-based cameras can employ the single array detector concept. The area of interest feature of the CMOS-based camera allows a PAT system to specify portion of the array. The maximum allowed frame rate increases as the size of the area of interest decreases under certain conditions. A commercially available CMOS camera with 105 fps @ 640×480 is employed in our PAT simulation system, in which only part pixels are used in fact. Beams angle varying in the field of view can be detected after getting across a Cassegrain telescope and an optical focus system. Spot pixel values (8 bits per pixel) reading out from CMOS are transmitted to a DSP subsystem via IEEE 1394 bus, and pointing errors can be computed by the centroid equation. It was shown in test that: (1) 500 fps @ 100×100 is available in acquisition when the field of view is 1mrad; (2)3k fps @ 10×10 is available in tracking when the field of view is 0.1mrad.

RF upset susceptibilities of CMOS and low power Schottky D-type flip-flops

NASA Astrophysics Data System (ADS)

Kenneally, Daniel J.; Koellen, Daniel S.; Epshtein, Stan

A description is given of measurements of RF upset levels on two D-type flip-flops, the CD4013B and 54ALS74A, which are functionally identical but fabricated from different technologies: CMOS and low-power Schottky. Continuous-wave electromagnetic interference (CW EMI) from 1 MHz to 200 MHz was coupled into the clock, data, and collector bias, Vcc, ports of each device type while test vectors were used to verify normal operation and subsequent upsets. Both the CMOS and the Schottky devices show decreasing RF susceptibility with increasing frequencies from 1 to 200 MHz. The CMOS device roll-off is almost 18 dB/decade as compared to about 12 dB/decade for the Schottky device. The differences in the Vcc ports' susceptibilities are also apparent. The CMOS device's upset levels decrease steeply with increasing frequency at approximate roll-offs of 60 dB/decade up to 5 MHz and 15 dB/decade from 5 to 100 MHz. Over the same bands, the Schottky device susceptibility at the Vcc port remains strikingly constant at a 6-dBm upset level. Measurements on the clock and data ports seem to suggest that: (1) the CMOS device is `RF harder' than the Schottky device by 3 to 18 dB at least above the 5 to 10 MHz range and out to 100 MHz; and (2) below that range, the Schottky device may be `RF harder' by 3 to 6 dB, but there are not enough measurement data to confirm this performance below 5 MHz.

Immunochromatographic Strip Test for Rapid Detection of Diphtheria Toxin: Description and Multicenter Evaluation in Areas of Low and High Prevalence of Diphtheria

PubMed Central

Engler, K. H.; Efstratiou, A.; Norn, D.; Kozlov, R. S.; Selga, I.; Glushkevich, T. G.; Tam, M.; Melnikov, V. G.; Mazurova, I. K.; Kim, V. E.; Tseneva, G. Y.; Titov, L. P.; George, R. C.

2002-01-01

An immunochromatographic strip (ICS) test was developed for the detection of diphtheria toxin by using an equine polyclonal antibody as the capture antibody and colloidal gold-labeled monoclonal antibodies specific for fragment A of the diphtheria toxin molecule as the detection antibody. The ICS test has been fully optimized for the detection of toxin from bacterial cultures; the limit of detection was approximately 0.5 ng of diphtheria toxin per ml within 10 min. In a comparative study with 915 pure clinical isolates of Corynebacterium spp., the results of the ICS test were in complete agreement with those of the conventional Elek test. The ICS test was also evaluated for its ability to detect toxigenicity from clinical specimens (throat swabs) in two field studies conducted within areas of the former USSR where diphtheria is epidemic. Eight hundred fifty throat swabs were examined by conventional culture and by use of directly inoculated broth cultures for the ICS test. The results showed 99% concordance (848 of 850 specimens), and the sensitivity and specificity of the ICS test were 98% (95% confidence interval, 91 to 99%) and 99% (95% confidence interval, 99 to 100%), respectively. PMID:11773096

Edwards nXDS15iC Vacuum Scroll Pump Pressure Testing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sessions, H.; Morgan, G. A.

2013-07-17

The SRNL High Pressure Laboratory performed testing on an Edwards Model nXDS15iC Vacuum Scroll Pump on July 10th and 11th of 2013 at 723-A. This testing was done in an attempt to obtain initial compression ratio information for the nXDS15iC pump, with compression ratio defined as discharge pressure of the pump divided by suction pressure. Pressure burst testing was also done on the pump to determine its design pressure for pressure safety reasons. The Edwards nXDS15iC pump is being evaluated by SRNL for use part of the SHINE project being executed by SRNL.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Cytotoxic activity of quassinoids from Eurycoma longifolia.

PubMed

Miyake, Katsunori; Li, Feng; Tezuka, Yasuhiro; Awale, Suresh; Kadota, Shigetoshi

2010-07-01

Twenty-four quassinoids isolated from Eurycoma longifolia Jack were investigated for their cytotoxicity against a panel of four different cancer cell lines, which includes three murine cell lines [colon 26-L5 carcinoma (colon 26-L5), B16-BL6 melanoma (B16-BL6), Lewis lung carcinoma (LLC)] and a human lung A549 adenocarcinoma (A549) cell line. Among the tested compounds, eurycomalactone (9) displayed the most potent activity against all the tested cell lines; colon 26-L5 (IC50 = 0.70 microM), B16-BL6 (IC50 = 0.59 microM), LLC (IC50 = 0.78 microM), and A549 (IC50 = 0.73 microM). These activities were comparable to clinically used anticancer agent doxorubicin (colon 26-L5, IC50 = 0.76 microM; B16-BL6, IC50 = 0.86 microM; LLC, IC50 = 0.80 microM; A549, IC50 = 0.66 microM).

Electromigration failures under bidirectional current stress

NASA Astrophysics Data System (ADS)

Tao, Jiang; Cheung, Nathan W.; Hu, Chenming

1998-01-01

Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed-DC (local VCC and VSS lines) and bidirectional AC current (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. Failure mechanisms of different metallization systems (Al-Si, Al-Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under AC current stress in a wide frequency range (from mHz to 500 MHz) has been study in this paper. Based on these experimental results, a damage healing model is developed, and electromigration design rules are proposed. It shows that in the circuit operating frequency range, the "design-rule current" is the time-average current. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal-migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.

Ultrahigh sensitivity endoscopic camera using a new CMOS image sensor: providing with clear images under low illumination in addition to fluorescent images.

PubMed

Aoki, Hisae; Yamashita, Hiromasa; Mori, Toshiyuki; Fukuyo, Tsuneo; Chiba, Toshio

2014-11-01

We developed a new ultrahigh-sensitive CMOS camera using a specific sensor that has a wide range of spectral sensitivity characteristics. The objective of this study is to present our updated endoscopic technology that has successfully integrated two innovative functions; ultrasensitive imaging as well as advanced fluorescent viewing. Two different experiments were conducted. One was carried out to evaluate the function of the ultrahigh-sensitive camera. The other was to test the availability of the newly developed sensor and its performance as a fluorescence endoscope. In both studies, the distance from the endoscopic tip to the target was varied and those endoscopic images in each setting were taken for further comparison. In the first experiment, the 3-CCD camera failed to display the clear images under low illumination, and the target was hardly seen. In contrast, the CMOS camera was able to display the targets regardless of the camera-target distance under low illumination. Under high illumination, imaging quality given by both cameras was quite alike. In the second experiment as a fluorescence endoscope, the CMOS camera was capable of clearly showing the fluorescent-activated organs. The ultrahigh sensitivity CMOS HD endoscopic camera is expected to provide us with clear images under low illumination in addition to the fluorescent images under high illumination in the field of laparoscopic surgery.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

The Role of a Physical Analysis Laboratory in a 300 mm IC Development and Manufacturing Centre

NASA Astrophysics Data System (ADS)

Kwakman, L. F. Tz.; Bicais-Lepinay, N.; Courtas, S.; Delille, D.; Juhel, M.; Trouiller, C.; Wyon, C.; de la Bardonnie, M.; Lorut, F.; Ross, R.

2005-09-01

To remain competitive IC manufacturers have to accelerate the development of most advanced (CMOS) technology and to deliver high yielding products with best cycle times and at a competitive pricing. With the increase of technology complexity, also the need for physical characterization support increases, however many of the existing techniques are no longer adequate to effectively support the 65-45 nm technology node developments. New and improved techniques are definitely needed to better characterize the often marginal processes, but these should not significantly impact fabrication costs or cycle time. Hence, characterization and metrology challenges in state-of-the-art IC manufacturing are both of technical and economical nature. TEM microscopy is needed for high quality, high volume analytical support but several physical and practical hurdles have to be taken. The success rate of FIB-SEM based failure analysis drops as defects often are too small to be detected and fault isolation becomes more difficult in the nano-scale device structures. To remain effective and efficient, SEM and OBIRCH techniques have to be improved or complemented with other more effective methods. Chemical analysis of novel materials and critical interfaces requires improvements in the field of e.g. SIMS, ToF-SIMS. Techniques that previously were only used sporadically, like EBSD and XRD, have become a `must' to properly support backend process development. At the bright side, thanks to major technical advances, techniques that previously were practiced at laboratory level only now can be used effectively for at-line fab metrology: Voltage Contrast based defectivity control, XPS based gate dielectric metrology and XRD based control of copper metallization processes are practical examples. In this paper capabilities and shortcomings of several techniques and corresponding equipment are presented with practical illustrations of use in our Crolles facilities.

Evaluation of the Field Performance of ImmunoCard STAT!® Rapid Diagnostic Test for Rotavirus in Dadaab Refugee Camp and at the Kenya–Somalia Border

PubMed Central

Ope, Maurice; Nyoka, Raymond; Unshur, Ahmed; Oyier, Fredrick O.; Mowlid, Shafe A.; Owino, Brian; Ochieng, Steve B.; Okello, Charles I.; Montgomery, Joel M.; Wagacha, Burton; Galev, Aleksandar; Abdow, Abdikadir; Esona, Mathew D.; Tate, Jacqueline; Fitter, David; Cookson, Susan T.; Arunmozhi, Balajee; Marano, Nina

2017-01-01

Rotavirus commonly causes diarrhea in children, leading to hospitalization and even death. Rapid diagnostic tests are feasible alternatives for determining rotavirus outbreaks in refugee camps that have inadequate laboratory capacity. We evaluated the field performance of ImmunoCard STAT!® Rotavirus (ICS-RV) in Dadaab Refugee Camp and at the Kenya–Somalia border. From May to December 2014, we prospectively enrolled children aged < 5 years hospitalized with acute diarrhea, defined as ≥ 3 episodes of loose stool in 24 hours for < 7 days. Stool samples were collected and tested by trained surveillance clerks using ICS-RV per manufacturer's instructions. The field performance characteristics of ICS-RV were evaluated against the gold standard test, Premier™ Rotaclone® enzyme immunoassay. The operational characteristics were evaluated using World Health Organization (WHO) ASSURED criteria to determine whether ICS-RV is appropriate as a point-of-care test by administering a standard questionnaire and observing surveillance clerks performing the test. We enrolled 213 patients with a median age of 10 months (range = 1–48); 58.2% were male. A total of 71 (33.3%) and 60 (28.2%) patients tested positive for rotavirus infection by immunoassay and ICS-RV, respectively. The sensitivity, specificity, and positive and negative predictive values of ICS-RV compared with the immunoassay were 83.1% (95% confidence interval [CI] = 72.3–91.0), 99.3% (95% CI = 96.1–100), 98.3% (95% CI = 91.1–100), and 92.1% (95% CI = 86.6–95.5), respectively. The ICS-RV fulfilled the WHO ASSURED criteria for point-of-care testing. ICS-RV is a field-ready point-of-care test with good field performance and operational characteristics. It can be useful in determining rotavirus outbreaks in resource-limited settings. PMID:28719278

Evaluation of the Field Performance of ImmunoCard STAT!® Rapid Diagnostic Test for Rotavirus in Dadaab Refugee Camp and at the Kenya-Somalia Border.

PubMed

Ope, Maurice; Nyoka, Raymond; Unshur, Ahmed; Oyier, Fredrick O; Mowlid, Shafe A; Owino, Brian; Ochieng, Steve B; Okello, Charles I; Montgomery, Joel M; Wagacha, Burton; Galev, Aleksandar; Abdow, Abdikadir; Esona, Mathew D; Tate, Jacqueline; Fitter, David; Cookson, Susan T; Arunmozhi, Balajee; Marano, Nina

2017-06-01

AbstractRotavirus commonly causes diarrhea in children, leading to hospitalization and even death. Rapid diagnostic tests are feasible alternatives for determining rotavirus outbreaks in refugee camps that have inadequate laboratory capacity. We evaluated the field performance of ImmunoCard STAT! ® Rotavirus (ICS-RV) in Dadaab Refugee Camp and at the Kenya-Somalia border. From May to December 2014, we prospectively enrolled children aged < 5 years hospitalized with acute diarrhea, defined as ≥ 3 episodes of loose stool in 24 hours for < 7 days. Stool samples were collected and tested by trained surveillance clerks using ICS-RV per manufacturer's instructions. The field performance characteristics of ICS-RV were evaluated against the gold standard test, Premier ™ Rotaclone ® enzyme immunoassay. The operational characteristics were evaluated using World Health Organization (WHO) ASSURED criteria to determine whether ICS-RV is appropriate as a point-of-care test by administering a standard questionnaire and observing surveillance clerks performing the test. We enrolled 213 patients with a median age of 10 months (range = 1-48); 58.2% were male. A total of 71 (33.3%) and 60 (28.2%) patients tested positive for rotavirus infection by immunoassay and ICS-RV, respectively. The sensitivity, specificity, and positive and negative predictive values of ICS-RV compared with the immunoassay were 83.1% (95% confidence interval [CI] = 72.3-91.0), 99.3% (95% CI = 96.1-100), 98.3% (95% CI = 91.1-100), and 92.1% (95% CI = 86.6-95.5), respectively. The ICS-RV fulfilled the WHO ASSURED criteria for point-of-care testing. ICS-RV is a field-ready point-of-care test with good field performance and operational characteristics. It can be useful in determining rotavirus outbreaks in resource-limited settings.

Saturn Apollo Program

NASA Image and Video Library

1964-12-01

At the Marshall Space Flight Center (MSFC), the fuel tank assembly for the Saturn V S-IC-T (static test stage) fuel tank assembly is mated to the liquid oxygen (LOX) tank in building 4705. This stage underwent numerous static firings at the newly-built S-IC Static Test Stand at the MSFC west test area. The S-IC (first) stage used five F-1 engines that produced a total thrust of 7,500,000 pounds as each engine produced 1,500,000 pounds of thrust. The S-IC stage lifted the Saturn V vehicle and Apollo spacecraft from the launch pad.

Time-Domain Fluorescence Lifetime Imaging Techniques Suitable for Solid-State Imaging Sensor Arrays

PubMed Central

Li, David Day-Uei; Ameer-Beg, Simon; Arlt, Jochen; Tyndall, David; Walker, Richard; Matthews, Daniel R.; Visitkul, Viput; Richardson, Justin; Henderson, Robert K.

2012-01-01

We have successfully demonstrated video-rate CMOS single-photon avalanche diode (SPAD)-based cameras for fluorescence lifetime imaging microscopy (FLIM) by applying innovative FLIM algorithms. We also review and compare several time-domain techniques and solid-state FLIM systems, and adapt the proposed algorithms for massive CMOS SPAD-based arrays and hardware implementations. The theoretical error equations are derived and their performances are demonstrated on the data obtained from 0.13 μm CMOS SPAD arrays and the multiple-decay data obtained from scanning PMT systems. In vivo two photon fluorescence lifetime imaging data of FITC-albumin labeled vasculature of a P22 rat carcinosarcoma (BD9 rat window chamber) are used to test how different algorithms perform on bi-decay data. The proposed techniques are capable of producing lifetime images with enough contrast. PMID:22778606

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

PubMed

Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

2013-01-01

One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

An integrated conceptual framework for evaluating and improving 'understanding' in informed consent.

PubMed

Bossert, Sabine; Strech, Daniel

2017-10-17

The development of understandable informed consent (IC) documents has proven to be one of the most important challenges in research with humans as well as in healthcare settings. Therefore, evaluating and improving understanding has been of increasing interest for empirical research on IC. However, several conceptual and practical challenges for the development of understandable IC documents remain unresolved. In this paper, we will outline and systematize some of these challenges. On the basis of our own experiences in empirical user testing of IC documents as well as the relevant literature on understanding in IC, we propose an integrated conceptual model for the development of understandable IC documents. The proposed conceptual model integrates different methods for the participatory improvement of written information, including IC, as well as quantitative methods for measuring understanding in IC. In most IC processes, understandable written information is an important prerequisite for valid IC. To improve the quality of IC documents, a conceptual model for participatory procedures of testing, revising, and retesting can be applied. However, the model presented in this paper needs further theoretical and empirical elaboration and clarification of several conceptual and practical challenges.

Monolithic CMOS imaging x-ray spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

NASA Astrophysics Data System (ADS)

Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

2009-05-01

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

NASA Astrophysics Data System (ADS)

Torres, Erick Omar

Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

MT6415CA: a 640×512-15µm CTIA ROIC for SWIR InGaAs detector arrays

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Isikhan, Murat; Bayhan, Nusret; Gulden, M. Ali; Incedere, O. Samet; Soyer, S. Tuncer; Kocak, Serhat; Yilmaz, Gokhan S.; Akin, Tayfun

2013-06-01

This paper reports the development of a new low-noise CTIA ROIC (MT6415CA) suitable for SWIR InGaAs detector arrays for low-light imaging applications. MT6415CA is the second product in the MT6400 series ROICs from Mikro-Tasarim Ltd., which is a fabless IC design house specialized in the development of monolithic imaging sensors and ROICs for hybrid imaging sensors. MT6415CA is a low-noise snapshot CTIA ROIC, has a format of 640 × 512 and pixel pitch of 15 µm, and has been developed with the system-on-chip architecture in mind, where all the timing and biasing for this ROIC are generated on-chip without requiring any external inputs. MT6415CA is a highly configurable ROIC, where many of its features can be programmed through a 3-wire serial interface allowing on-the-fly configuration of many ROIC features. It performs snapshot operation both using Integrate-Then-Read (ITR) and Integrate-While-Read (IWR) modes. The CTIA type pixel input circuitry has three gain modes with programmable full-well-capacity (FWC) values of 10.000 e-, 20.000 e-, and 350.000 e- in the very high gain (VHG), high-gain (HG), and low-gain (LG) modes, respectively. MT6415CA has an input referred noise level of less than 5 e- in the very high gain (VHG) mode, suitable for very low-noise SWIR imaging applications. MT6415CA has 8 analog video outputs that can be programmed in 8, 4, or 2-output modes with a selectable analog reference for pseudo-differential operation. The ROIC runs at 10 MHz and supports frame rate values up to 200 fps in the 8-output mode. The integration time can be programmed up to 1s in steps of 0.1 µs. The ROIC uses 3.3 V and 1.8V supply voltages and dissipates less than 150 mW in the 4-output mode. MT6415CA is fabricated using a modern mixed-signal CMOS process on 200 mm CMOS wafers, and tested parts are available at wafer or die levels with test reports and wafer maps. A compact USB 3.0 camera and imaging software have been developed to demonstrate the imaging performance of SWIR sensors built with MT6415CA ROIC

Construction Progress of the S-IC Test Stand Complex Bunker House

NASA Technical Reports Server (NTRS)

1963-01-01

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army's Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the S-IC stand, additional related facilities were built during this time frame. Built to the east of the S-IC stand, the block house served as the control room. To the south of the blockhouse was a newly constructed pump house used for delivering water to the S-IC stand during testing. North of the massive test stand, the F-1 Engine test stand was built for testing a single F-1 engine. Just southeast of the S-IC stand a concrete bunker house was constructed. The bunker housed an emergency crew clad in fire proof gear, who were close at hand should any emergencies arise during testing. This photo of the completed bunker house was taken on May 7, 1963.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

The need to scale up HIV indicator condition-guided testing for early case-finding: a case-control study in primary care.

PubMed

Joore, Ivo K; Twisk, Denise E; Vanrolleghem, Ann M; de Ridder, Maria; Geerlings, Suzanne E; van Bergen, Jan E A M; van den Broek, Ingrid V

2016-11-17

European guidelines recommend offering an HIV test to individuals who display HIV indicator conditions (ICs). We aimed to investigate the incidence of ICs in primary care reported in medical records prior to HIV diagnosis. We did a cross-sectional search in an electronic general practice database using a matched case-control design to identify which predefined ICs registered by Dutch GPs were most associated with an HIV-positive status prior to the time of diagnosis. We included 224 HIV cases diagnosed from 2009 to 2013, which were matched with 2,193 controls. Almost two thirds (n = 136, 60.7%) of cases were diagnosed with one or more ICs in the period up to five years prior to the index date compared to 18.7% (n = 411) of controls. Cases were more likely to have an IC than controls: in the one year prior to the index date, the odds ratio (OR) for at least one condition was 11.7 (95% CI: 8.3 to 16.4). No significant differences were seen in the strength of the association between HIV diagnosis and ICs when comparing genders, age groups or urbanisation levels. There is no indication that subgroups require a different testing strategy. Our study shows that there are opportunities for IC-guided testing in primary care. We recommend that IC-guided testing be more integrated in GPs' future guidelines and that education strategies be used to facilitate its implementation in daily practice.

Purification and partial characterization ofa 67-kD cross-react ive allergen from Imperata cylindrica pollen extract.

PubMed

Verma, J; Singh, B P; Gangal, S V; Arora, N; Sridhara, S

2000-08-01

Grass pollens are known to induce type I allergic reactions in a large number of genetically predisposed individuals. Earlier studies have recognized Imperata cylindrica (Ic) pollen as an important source of aeroallergen which contained 7 IgE binding proteins in the MW range of 85-16 kD. To isolate, purify and characterize a cross-reactive allergenic protein from Ic pollen extract for diagnosis and therapy of grass pollen allergy. Ic pollen extract was fractionated using DEAE Sephadex A-50, Sephadex G-200 and Mono Q column. Allergenic activity of the fractions was checked by ELISA, skin tests, ELISA inhibition and immunoblot using sera of Ic-sensitive patients. A 67-kD protein was purified to homogeneity from Ic-VIII. The allergenic determinants of this protein were identified by SDS-PAGE and immunoblot after CNBr treatment. Among Ic fractions, Ic-VIII was highly potent by ELISA, skin tests and showed cross-reactivity with 4 other tropical grasses by immunoblot and ELISA inhibition. The subfraction Ic-VIIIe1 of Ic-VIII showed a band at 67 kD on SDS-PAGE. On CNBr treatment, it gave 7 peptides, 3 of which were found to be allergenic. A 67-kD protein (Ic-VIIIe1) was isolated, purified to homogeneity and partially characterized. It showed cross-reactivity with tropical grasses tested and contained at least three allergenic determinants. Copyright 2000 S. Karger AG, Basel.

Saturn Apollo Program

NASA Image and Video Library

1967-01-01

This photograph is a view of the Saturn V S-IC (first) test stage being hoisted into the S-IC-B1 test stand at the Mississippi Test Facility (MTF), Bay St. Louis, Mississippi. This stage was used to prove the operational readiness of the stand. Begirning operations in 1966, the MTF has two test stands; a dual-position structure for running the S-IC stage at full throttle, and two separate stands for the S-II (Saturn V third) stage. It became the focus of the static test firing program. The completed S-IC stage was shipped from the Michoud Assembly Facility (MAF) to the MTF. The stage was then installed into the 124-meter-high test stand for static firing tests before shipment to the Kennedy Space Center for final assembly of the Saturn V vehicle. The MTF was renamed to the National Space Technology Laboratory (NSTL) in 1974 and later to the Stennis Space Center (SSC) in May 1988.

Saturn Apollo Program

NASA Image and Video Library

1967-08-01

This photograph is a view of the Saturn V S-IC-5 (first) flight stage static test firing at the S-IC-B1 test stand at the Mississippi Test Facility (MTF), Bay St. Louis, Mississippi. Begirning operations in 1966, the MTF has two test stands, a dual-position structure for running the S-IC stage at full throttle, and two separate stands for the S-II (Saturn V third) stage. It became the focus of the static test firing program. The completed S-IC stage was shipped from Michoud Assembly Facility (MAF) to the MTF. The stage was then installed into the 407-foot-high test stand for the static firing tests before shipment to the Kennedy Space Center for final assembly of the Saturn V vehicle. The MTF was renamed to the National Space Technology Laboratory (NSTL) in 1974 and later to the Stennis Space Center (SSC) in May 1988.

Acute Stress Impairs Inhibitory Control based on Individual Differences in Parasympathetic Nervous System Activity

PubMed Central

Roos, Leslie E.; Knight, Erik L.; Beauchamp, Kathryn G.; Berkman, Elliot T.; Faraday, Kelsie; Hyslop, Katie; Fisher, Philip A.

2017-01-01

Identifying environmental influences on inhibitory control (IC) may help promote positive behavioral and social adjustment. Although chronic stress is known to predict lower IC, the immediate effects of acute stress are unknown. The parasympathetic nervous system (PNS) may be a mechanism of the stress-IC link, given its psychophysiological regulatory role and connections to prefrontal brain regions critical to IC. We used a focused assessment of IC (the stop-signal task) to test whether an acute social stressor (the Trier Social Stress Test) affected participants’ pre- to post-IC performance (n = 58), compared to a control manipulation (n = 31). High frequency heart-rate variability was used as an index of PNS activity in response to the manipulation. Results indicated that stress impaired IC performance, blocking the practice effects observed in control participants. We also investigated the associations between PNS activity and IC; higher resting PNS activity predicted better pre-manipulation IC, and greater PNS stressor reactivity protected against the negative effects of stress on IC. Together, these results are the first to document the immediate effects of acute stress on IC and a phenotypic marker (PNS reactivity to stressors) of susceptibility to stress-induced IC impairment. This study suggests a new way to identify situations in which individuals are likely to exhibit IC vulnerability and related consequences such as impulsivity and risk taking behavior. Targeting PNS regulation may represent a novel target for IC-focused interventions. PMID:28268165

Increasing the Institutional Commitment of College Students: Enhanced Measurement and Test of a Nomological Model

ERIC Educational Resources Information Center

Davidson, William B.; Beck, Hall P.; Grisaffe, Douglas B.

2015-01-01

Measurement shortcomings have hampered the understanding of institutional commitment (IC) in college students. Therefore, this study sought to (a) develop validated indices of IC and associated psychosocial attributes and (b) use these indices to test a nomological network of variables and their direct and indirect relationships to IC. Exploratory…

Variation and Defect Tolerance for Nano Crossbars

NASA Astrophysics Data System (ADS)

Tunc, Cihan

With the extreme shrinking in CMOS technology, quantum effects and manufacturing issues are getting more crucial. Hence, additional shrinking in CMOS feature size seems becoming more challenging, difficult, and costly. On the other hand, emerging nanotechnology has attracted many researchers since additional scaling down has been demonstrated by manufacturing nanowires, Carbon nanotubes as well as molecular switches using bottom-up manufacturing techniques. In addition to the progress in manufacturing, developments in architecture show that emerging nanoelectronic devices will be promising for the future system designs. Using nano crossbars, which are composed of two sets of perpendicular nanowires with programmable intersections, it is possible to implement logic functions. In addition, nano crossbars present some important features as regularity, reprogrammability, and interchangeability. Combining these features, researchers have presented different effective architectures. Although bottom-up nanofabrication can greatly reduce manufacturing costs, due to low controllability in the manufacturing process, some critical issues occur. Bottom- up nanofabrication process results in high variation compared to conventional top- down lithography used in CMOS technology. In addition, an increased failure rate is expected. Variation and defect tolerance methods used for conventional CMOS technology seem inadequate for adapting to emerging nano technology because the variation and the defect rate for emerging nano technology is much more than current CMOS technology. Therefore, variations and defect tolerance methods for emerging nano technology are necessary for a successful transition. In this work, in order to tolerate variations for crossbars, we introduce a framework that is established based on reprogrammability and interchangeability features of nano crossbars. This framework is shown to be applicable for both FET-based and diode-based nano crossbars. We present a characterization testing method which requires minimal number of test vectors. We formulate the variation optimization problem using Simulated Annealing with different optimization goals. Furthermore, we extend the framework for defect tolerance. Experimental results and comparison of proposed framework with exhaustive methods confirm its effectiveness for both variation and defect tolerance.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Maximization of DRAM yield by control of surface charge and particle addition during high dose implantation

NASA Astrophysics Data System (ADS)

Horvath, J.; Moffatt, S.

1991-04-01

Ion implantation processing exposes semiconductor devices to an energetic ion beam in order to deposit dopant ions in shallow layers. In addition to this primary process, foreign materials are deposited as particles and surface films. The deposition of particles is a major cause of IC yield loss and becomes even more significant as device dimensions are decreased. Control of particle addition in a high-volume production environment requires procedures to limit beamline and endstation sources, control of particle transport, cleaning procedures and a well grounded preventative maintenance philosophy. Control of surface charge by optimization of the ion beam and electron shower conditions and measurement with a real-time charge sensor has been effective in improving the yield of NMOS and CMOS DRAMs. Control of surface voltages to a range between 0 and -20 V was correlated with good implant yield with PI9200 implanters for p + and n + source-drain implants.

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

The FE-I4 Pixel Readout Chip and the IBL Module

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barbero, Marlon; Arutinov, David; Backhaus, Malte

2012-05-01

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on testmore » results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.« less

Design and simulation analysis of a novel pressure sensor based on graphene film

NASA Astrophysics Data System (ADS)

Nie, M.; Xia, Y. H.; Guo, A. Q.

2018-02-01

A novel pressure sensor structure based on graphene film as the sensitive membrane was proposed in this paper, which solved the problem to measure low and minor pressure with high sensitivity. Moreover, the fabrication process was designed which can be compatible with CMOS IC fabrication technology. Finite element analysis has been used to simulate the displacement distribution of the thin movable graphene film of the designed pressure sensor under the different pressures with different dimensions. From the simulation results, the optimized structure has been obtained which can be applied in the low measurement range from 10hPa to 60hPa. The length and thickness of the graphene film could be designed as 100μm and 0.2μm, respectively. The maximum mechanical stress on the edge of the sensitive membrane was 1.84kPa, which was far below the breaking strength of the silicon nitride and graphene film.

C-MOS bulk metal design handbook. [LSI standard cell (circuits)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

Around Marshall

NASA Image and Video Library

1976-01-06

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was originally designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage. Modifications to the S-IC Test Stand began in 1975 to accommodate space shuttle external tank testing. This photo is of the horizontal liquid oxygen tanks.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness.

PubMed

Cao, Q; Brehler, M; Sisniega, A; Stayman, J W; Yorkston, J; Siewerdsen, J H; Zbijewski, W

2017-03-01

CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μ m, ~80 μ m and ~40 μ m, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μ m pixels) with CsI scintillator thicknesses of 400 μ m and 700 μ m, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6-5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μ m scintillator compared to the standard nominal CsI thickness of 700 μ m. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index ( d' 2 ) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μ m CsI compared to 700 μ m CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μ m panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μ m scinitllator. Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μ m CsI onto the clinical prototype of CMOS-based extremity CBCT.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness

PubMed Central

Cao, Q.; Brehler, M.; Sisniega, A.; Stayman, J. W.; Yorkston, J.; Siewerdsen, J. H.; Zbijewski, W.

2017-01-01

Purpose CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. Methods A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μm, ~80 μm and ~40 μm, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μm pixels) with CsI scintillator thicknesses of 400 μm and 700 μm, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6–5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Results Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μm scintillator compared to the standard nominal CsI thickness of 700 μm. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index (d′2) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μm CsI compared to 700 μm CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μm panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μm scinitllator. Conclusion Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μm CsI onto the clinical prototype of CMOS-based extremity CBCT. PMID:28989220

WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Q; Brehler, M; Sisniega, A

Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection)more » using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high-frequency imaging tasks through adoption of the CMOS detector and small FS x-ray source, motivating the use of these components in a new system for quantitative in-vivo imaging of trabecular bone. Financial Support: US NIH grant R01EB018896. Qian Cao is a Howard Hughes Medical Institute International Student Research Fellow. Disclosures: W Zbijewski, J Siewerdsen and A Sisniega receive research funding from Carestream Health.« less

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

Smart CMOS image sensor for lightning detection and imaging.

PubMed

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

Innovative monolithic detector for tri-spectral (THz, IR, Vis) imaging

NASA Astrophysics Data System (ADS)

Pocas, S.; Perenzoni, M.; Massari, N.; Simoens, F.; Meilhan, J.; Rabaud, W.; Martin, S.; Delplanque, B.; Imperinetti, P.; Goudon, V.; Vialle, C.; Arnaud, A.

2012-10-01

Fusion of multispectral images has been explored for many years for security and used in a number of commercial products. CEA-Leti and FBK have developed an innovative sensor technology that gathers monolithically on a unique focal plane arrays, pixels sensitive to radiation in three spectral ranges that are terahertz (THz), infrared (IR) and visible. This technology benefits of many assets for volume market: compactness, full CMOS compatibility on 200mm wafers, advanced functions of the CMOS read-out integrated circuit (ROIC), and operation at room temperature. The ROIC houses visible APS diodes while IR and THz detections are carried out by microbolometers collectively processed above the CMOS substrate. Standard IR bolometric microbridges (160x160 pixels) are surrounding antenna-coupled bolometers (32X32 pixels) built on a resonant cavity customized to THz sensing. This paper presents the different technological challenges achieved in this development and first electrical and sensitivity experimental tests.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Affordable Wide-field Optical Space Surveillance using sCMOS and GPUs

NASA Astrophysics Data System (ADS)

Zimmer, P.; McGraw, J.; Ackermann, M.

2016-09-01

Recent improvements in sCMOS technology allow for affordable, wide-field, and rapid cadence surveillance from LEO to out past GEO using largely off-the-shelf hardware. sCMOS sensors, until very recently, suffered from several shortcomings when compared to CCD sensors - lower sensitivity, smaller physical size and less predictable noise characteristics. Sensors that overcome the first two of these are now available commercially and the principals at J.T. McGraw and Associates (JTMA) have developed observing strategies that minimize the impact of the third, while leveraging the key features of sCMOS, fast readout and low average readout noise. JTMA has integrated a new generation sCMOS sensor into an existing COTS telescope system in order to develop and test new detection techniques designed for uncued optical surveillance across a wide range of apparent object angular rates - from degree per second scale of LEO objects to a few arcseconds per second for objects out past GEO. One further complication arises from this: increased useful frame rate means increased data volume. Fortunately, GPU technology continues to advance at a breakneck pace and we report on the results and performance of our new detection techniques implemented on new generation GPUs. Early results show significance within 20% of the expected theoretical limiting signal-to-noise using commodity GPUs in near real time across a wide range of object parameters, closing the gap in detectivity between moving objects and tracked objects.

Saturn Apollo Program

NASA Image and Video Library

1967-01-01

This photograph is a view of the Saturn V S-IC-5 (first) flight stage being hoisted into the S-IC-B1 test stand at the Mississippi Test Facility (MTF), Bay St. Louis, Mississippi. Begirning operations in 1966, the MTF has two test stands, a dual-position structure for running the S-IC stage at full throttle, and two separate stands for the S-II (Saturn V third) stage. It became the focus of the static test firing program. The completed S-IC stage was shipped from Michoud Assembly Facility (MAF) to the MTF. The stage was then installed into the 124-meter-high test stand for static firing tests before shipment to the Kennedy Space Center for final assembly of the Saturn V vehicle. The MTF was renamed to the National Space Technology Laboratory (NSTL) in 1974 and later to the Stennis Space Center (SSC) in May 1988.

A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique

PubMed Central

Kim, SangYun; Samadpoor Rikan, Behnam; Pu, YoungGun; Yoo, Sang-Sun; Lee, Minjae; Yang, Youngoo; Lee, Kang-Yoon

2018-01-01

In this paper, a high noise immunity, 28 × 16-channel finger touch sensing IC for an orthogonal frequency division multiplexing (OFDM) touch sensing scheme is presented. In order to increase the signal-to-noise ratio (SNR), the OFDM sensing scheme is proposed. The transmitter (TX) transmits the orthogonal signal to each channels of the panel. The receiver (RX) detects the magnitude of the orthogonal frequency to be transmitted from the TX. Due to the orthogonal characteristics, it is robust to narrowband interference and noise. Therefore, the SNR can be improved. In order to reduce the noise effect of low frequencies, a mixer and high-pass filter are proposed as well. After the noise is filtered, the touch SNR attained is 60 dB, from 20 dB before the noise is filtered. The advantage of the proposed OFDM sensing scheme is its ability to detect channels of the panel simultaneously with the use of multiple carriers. To satisfy the linearity of the signal in the OFDM system, a high-linearity mixer and a rail-to-rail amplifier in the TX driver are designed. The proposed design is implemented in 90 nm CMOS process. The SNR is approximately 60 dB. The area is 13.6 mm2, and the power consumption is 62.4 mW. PMID:29883435

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Comparison of the diagnostic accuracy of a rapid immunochromatographic test and the rapid plasma reagin test for antenatal syphilis screening in Mozambique.

PubMed Central

Montoya, Pablo J.; Lukehart, Sheila A.; Brentlinger, Paula E.; Blanco, Ana J.; Floriano, Florencia; Sairosse, Josefa; Gloyd, Stephen

2006-01-01

OBJECTIVE: Programmes to control syphilis in developing countries are hampered by a lack of laboratory services, delayed diagnosis, and doubts about current screening methods. We aimed to compare the diagnostic accuracy of an immunochromatographic strip (ICS) test and the rapid plasma reagin (RPR) test with the combined gold standard (RPR, Treponema pallidum haemagglutination assay and direct immunofluorescence stain done at a reference laboratory) for the detection of syphilis in pregnancy. METHODS: We included test results from 4789 women attending their first antenatal visit at one of six health facilities in Sofala Province, central Mozambique. We compared diagnostic accuracy (sensitivity, specificity, and positive and negative predictive values) of ICS and RPR done at the health facilities and ICS performed at the reference laboratory. We also made subgroup comparisons by human immunodeficiency virus (HIV) and malaria status. FINDINGS: For active syphilis, the sensitivity of the ICS was 95.3% at the reference laboratory, and 84.1% at the health facility. The sensitivity of the RPR at the health facility was 70.7%. Specificity and positive and negative predictive values showed a similar pattern. The ICS outperformed RPR in all comparisons (P<0.001). CONCLUSION: The diagnostic accuracy of the ICS compared favourably with that of the gold standard. The use of the ICS in Mozambique and similar settings may improve the diagnosis of syphilis in health facilities, both with and without laboratories. PMID:16501726

Scoring Systems to Estimate Intracerebral Control and Survival Rates of Patients Irradiated for Brain Metastases;Brain metastases; Radiation therapy; Local control; Survival; Prognostic scores

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rades, Dirk, E-mail: Rades.Dirk@gmx.net; Dziggel, Liesa; Haatanen, Tiina

2011-07-15

Purpose: To create and validate scoring systems for intracerebral control (IC) and overall survival (OS) of patients irradiated for brain metastases. Methods and Materials: In this study, 1,797 patients were randomly assigned to the test (n = 1,198) or the validation group (n = 599). Two scoring systems were developed, one for IC and another for OS. The scores included prognostic factors found significant on multivariate analyses. Age, performance status, extracerebral metastases, interval tumor diagnosis to RT, and number of brain metastases were associated with OS. Tumor type, performance status, interval, and number of brain metastases were associated with IC.more » The score for each factor was determined by dividing the 6-month IC or OS rate (given in percent) by 10. The total score represented the sum of the scores for each factor. The score groups of the test group were compared with the corresponding score groups of the validation group. Results: In the test group, 6-month IC rates were 17% for 14-18 points, 49% for 19-23 points, and 77% for 24-27 points (p < 0.0001). IC rates in the validation group were 19%, 52%, and 77%, respectively (p < 0.0001). In the test group, 6-month OS rates were 9% for 15-19 points, 41% for 20-25 points, and 78% for 26-30 points (p < 0.0001). OS rates in the validation group were 7%, 39%, and 79%, respectively (p < 0.0001). Conclusions: Patients irradiated for brain metastases can be given scores to estimate OS and IC. IC and OS rates of the validation group were similar to the test group demonstrating the validity and reproducibility of both scores.« less

Development and Validation of an HIV Risk Exposure and Indicator Conditions Questionnaire to Support Targeted HIV Screening.

PubMed

Elías, María Jesús Pérez; Gómez-Ayerbe, Cristina; Elías, Pilar Pérez; Muriel, Alfonso; de Santiago, Alberto Diaz; Martinez-Colubi, María; Moreno, Ana; Santos, Cristina; Polo, Lidia; Barea, Rafa; Robledillo, Gema; Uranga, Almudena; Espín, Agustina Cano; Quereda, Carmen; Dronda, Fernando; Casado, Jose Luis; Moreno, Santiago

2016-02-01

The aim of our study was to develop a Spanish-structured HIV risk of exposure and indicator conditions (RE&IC) questionnaire. People attending to an emergency room or to a primary clinical care center were offered to participate in a prospective, 1 arm, open label study, in which all enrolled patients filled out our developed questionnaire and were HIV tested. Questionnaire accuracy, feasibility, and reliability were evaluated.Valid paired 5329 HIV RE&IC questionnaire and rapid HIV tests were performed, 69.3% in the primary clinical care center, 49.6% women, median age 37 years old, 74.9% Spaniards, 20.1% Latin-Americans. Confirmed hidden HIV infection was detected in 4.1%, while HIV RE&IC questionnaire was positive in 51.2%. HIV RE&IC questionnaire sensitivity was 100% to predict HIV infection, with a 100% negative predictive value. When considered separately, RE or IC items sensitivity decreases to 86.4% or 91%, and similarly their negative predictive value to 99.9% for both of them. The majority of people studied, 90.8% self-completed HIV RE&IC questionnaire. Median time to complete was 3 minutes. Overall HIV RE&IC questionnaire test-retest Kappa agreement was 0.82 (almost perfect), likewise for IC items 0.89, while for RE items was lower 0.78 (substantial).A feasible and reliable Spanish HIV RE&IC self questionnaire accurately discriminated all non-HIV-infected people without missing any HIV diagnoses, in a low prevalence HIV infection area. The best accuracy and reliability were obtained when combining HIV RE&IC items.

Development and Validation of an HIV Risk Exposure and Indicator Conditions Questionnaire to Support Targeted HIV Screening

PubMed Central

Elías, María Jesús Pérez; Gómez-Ayerbe, Cristina; Elías, Pilar Pérez; Muriel, Alfonso; de Santiago, Alberto Diaz; Martinez-Colubi, María; Moreno, Ana; Santos, Cristina; Polo, Lidia; Barea, Rafa; Robledillo, Gema; Uranga, Almudena; Espín, Agustina Cano; Quereda, Carmen; Dronda, Fernando; Casado, Jose Luis; Moreno, Santiago

2016-01-01

Abstract The aim of our study was to develop a Spanish-structured HIV risk of exposure and indicator conditions (RE&IC) questionnaire. People attending to an emergency room or to a primary clinical care center were offered to participate in a prospective, 1 arm, open label study, in which all enrolled patients filled out our developed questionnaire and were HIV tested. Questionnaire accuracy, feasibility, and reliability were evaluated. Valid paired 5329 HIV RE&IC questionnaire and rapid HIV tests were performed, 69.3% in the primary clinical care center, 49.6% women, median age 37 years old, 74.9% Spaniards, 20.1% Latin-Americans. Confirmed hidden HIV infection was detected in 4.1%, while HIV RE&IC questionnaire was positive in 51.2%. HIV RE&IC questionnaire sensitivity was 100% to predict HIV infection, with a 100% negative predictive value. When considered separately, RE or IC items sensitivity decreases to 86.4% or 91%, and similarly their negative predictive value to 99.9% for both of them. The majority of people studied, 90.8% self-completed HIV RE&IC questionnaire. Median time to complete was 3 minutes. Overall HIV RE&IC questionnaire test-retest Kappa agreement was 0.82 (almost perfect), likewise for IC items 0.89, while for RE items was lower 0.78 (substantial). A feasible and reliable Spanish HIV RE&IC self questionnaire accurately discriminated all non–HIV-infected people without missing any HIV diagnoses, in a low prevalence HIV infection area. The best accuracy and reliability were obtained when combining HIV RE&IC items. PMID:26844471

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

NASA Technical Reports Server (NTRS)

Kolasinski, W. A.; Koga, R.; Blake, J. B.; Brucker, G.; Pandya, P.; Petersen, E.; Price, W.

1982-01-01

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection.

PubMed

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N

2017-08-23

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

PubMed Central

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N.

2017-01-01

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW. PMID:28832523

Detection of CMOS bridging faults using minimal stuck-at fault test sets

NASA Technical Reports Server (NTRS)

Ijaz, Nabeel; Frenzel, James F.

1993-01-01

The performance of minimal stuck-at fault test sets at detecting bridging faults are evaluated. New functional models of circuit primitives are presented which allow accurate representation of bridging faults under switch-level simulation. The effectiveness of the patterns is evaluated using both voltage and current testing.

Electrical characterization of standard and radiation-hardened RCA CDP1856D 4-BIT, CMOS, bus buffer/separator

NASA Technical Reports Server (NTRS)

Stokes, R. L.

1979-01-01

Tests performed to determine accuracy and efficiency of bus separators used in microprocessors are presented. Functional, AC parametric, and DC parametric tests were performed in a Tektronix S-3260 automated test system. All the devices passed the functional tests and yielded nominal values in the parametric test.

30 CFR 57.22227 - Approved testing devices (I-A, I-B, I-C, II-A, II-B, III, IV, V-A, and V-B mines).

Code of Federal Regulations, 2011 CFR

2011-07-01

... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Approved testing devices (I-A, I-B, I-C, II-A, II-B, III, IV, V-A, and V-B mines). 57.22227 Section 57.22227 Mineral Resources MINE SAFETY AND... Ventilation § 57.22227 Approved testing devices (I-A, I-B, I-C, II-A, II-B, III, IV, V-A, and V-B mines). (a...

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

SEM probe of IC radiation sensitivity

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Stanley, A. G.

1979-01-01

Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.

Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

NASA Astrophysics Data System (ADS)

Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

2010-01-01

Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

Bladder pain syndrome/interstitial cystitis as a functional somatic syndrome.

PubMed

Warren, John W

2014-12-01

To determine whether bladder pain syndrome/interstitial cystitis (BPS/IC) has the characteristics of a functional somatic syndrome (FSS). There is no accepted definition of an FSS. Consequently, this paper reviewed the literature for common FSS characteristics and for reports that BPS/IC has these characteristics. Eleven articles met inclusion and exclusion criteria and yielded 18 FSS characteristics. BPS/IC patients manifest all but two: the exceptions were normal light microscopic anatomy (after hydrodistention under anesthesia, some BPS/IC bladders have Hunner's lesions and most have petechial hemorrhages) and normal laboratory tests (many BPS/IC patients have hematuria). Petechial hemorrhages and hematuria are probably related and may appear during naturally-occurring bladder distention. Without such distention, then, the 90% of BPS/IC patients without a Hunner's lesion have all the characteristics of an FSS. Comparisons in the opposite direction were consistent: several additional features of BPS/IC were found in FSSs. This systematic but untested method is consistent with but does not test the hypothesis that BPS/IC in some patients might best be understood as an FSS. Like most conditions, BPS/IC is probably heterogeneous; hence only a proportion of BPS/IC cases are likely to be manifestations of an FSS. This hypothesis has several implications. Explorations of processes that connect the FSSs might contribute to understanding the pathogenesis of BPS/IC. Patients with FSSs are at risk for BPS/IC and may benefit from future preventive strategies. Therapies that are useful in FSSs also may be useful in some cases of BPS/IC. Copyright © 2014 Elsevier Inc. All rights reserved.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

Association Between Macrominerals Intake and Changes in Internal Carotid Artery-Intima Media Thickness in POST Ischemic Stroke Patients

NASA Astrophysics Data System (ADS)

Pudjonarko, Dwi; Tugasworo, Dodik; Silaen, Rumintang

2017-02-01

Carotid Intima Media Thickness (C-IMT) has been widely used as marker for atherosclerosis. Previous studies on minerals intake and its association with C-IMT revealed various. Most of the studies showed inconsistent results. The aim of this study is to determine wether macro minerals intake is related to internal carotid-intima media thickness (IC-IMT). This is a longitudinal study, pre test post test design conducted in Neurology clinic, Kariadi hospital, Semarang from June to December 2014. Subjects were 22 post ischemic stroke patients. Minerals intake and IC-IMT was measured using Food Frequency Questionnaire and Duplex Carotid Ultrasonography. Statistical analysis was performed using Chi-Square, Fisher Exact and Logistic Regression test. Subjects included in this study were 17 male subjects (77.3%) and 5 female subjects (22.7%). Mean of IC-IMT in female subjects was found to be higher than in male. Mean of total IC-IMT was increased after a period of six months (0.96±0.80 to 0.97±0.21 mm). There were significant association between calcium as well as sodium intakes and IC-IMT. In contrast, there were no association between magnesium as well as potassium intake and IC-IMT. Multivariate analysis suggest that sodium intake (OR=26.828) was the most influencing factor for IC-IMT, followed by calcium intake (OR=0.042). Calcium as well as potassium intake were independently associated with IC-IMT. Magnecium as well as sodium intake were not independently associated with IC-IMT changes. Sodium intake was the most influencing variable to IC-IMT changes, followed by calcium intake.

Feasibility and Acceptability of Implementing Indirect Calorimetry Into Routine Clinical Care of Patients With Spinal Cord Injury

PubMed Central

Mayr, Hannah; Atresh, Sridhar; Kemp, Irene; Simmons, Joshua; Vivanti, Angela; Hickman, Ingrid J.

2016-01-01

Background: In the absence of reliable predictive equations, indirect calorimetry (IC) remains the gold standard for assessing energy requirements after spinal cord injury (SCI), but it is typically confined to a research setting. The purpose of this study is to assess the feasibility and acceptability of implementing IC into routine clinical care in an Australian SCI rehabilitation facility. Methods: Bedside IC (canopy hood) was performed, and patients completed an IC acceptability questionnaire (open-ended; yes/no; 5-point Likert scale). Fasted resting energy expenditure (REE) steady-state criteria were applied to assess data quality, and adherence to a test ≥20 minutes was recorded. Staff were surveyed to assess impact of IC on usual care. Results: Of 35 eligible patients, 9 declined (7 reported claustrophobia). One patient could not be tested before discharge and 25 underwent IC (84% male, injury level C2-L2, AIS A-D). Anxiety prevented one patient from completing IC, while another failed to fast. The remaining 23 patients achieved a steady-state REE (≥5 consecutive minutes with ≤10% coefficient of variation for VO2 and VCO2). Test-retest (n = 5) showed <10% variation in REE. Patients deemed the procedure acceptable, with 88% reporting a willingness to repeat IC. Eighty percent of patients and 90% of staff agreed it was acceptable for IC to be integrated into usual care. Conclusion: This study found that IC is a feasible and acceptable addition to the routine clinical care of patients recovering from SCI and may serve to improve accuracy of nutrition interventions for this patient population. PMID:29339868

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

NASA Astrophysics Data System (ADS)

Moradi, Behzad; Mirzaei, Abdolreza

2016-11-01

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

2013-12-01

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Multiplane and Spectrally-Resolved Single Molecule Localization Microscopy with Industrial Grade CMOS cameras.

PubMed

Babcock, Hazen P

2018-01-29

This work explores the use of industrial grade CMOS cameras for single molecule localization microscopy (SMLM). We show that industrial grade CMOS cameras approach the performance of scientific grade CMOS cameras at a fraction of the cost. This makes it more economically feasible to construct high-performance imaging systems with multiple cameras that are capable of a diversity of applications. In particular we demonstrate the use of industrial CMOS cameras for biplane, multiplane and spectrally resolved SMLM. We also provide open-source software for simultaneous control of multiple CMOS cameras and for the reduction of the movies that are acquired to super-resolution images.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

Elements in the murine c-mos messenger RNA 5'-untranslated region repress translation of downstream coding sequences.

PubMed

Steel, L F; Telly, D L; Leonard, J; Rice, B A; Monks, B; Sawicki, J A

1996-10-01

Murine c-mos transcripts isolated from testes have 5'-untranslated regions (5'UTRs) of approximately 300 nucleotides with a series of four overlapping open reading frames (ORFs) upstream of the AUG codon that initiates the Mos ORF. Ovarian c-mos transcripts have shorter 5'UTRs (70-80 nucleotides) and contain only 1-2 of the upstream ORFs (uORFs). To test whether these 5'UTRs affect translational efficiency, we have constructed plasmids for the expression of chimeric transcripts with a mos-derived 5'UTR fused to the Escherichia coli beta-galactosidase coding region. Translational efficiency has been evaluated by measuring beta-galactosidase activity NIH3T3 cells transiently transfected with these plasmids and with plasmids where various mutations have been introduced into the 5'UTR. We show that the 5'UTR characteristic of testis-specific c-mos mRNA strongly represses translation relative to the translation of transcripts that contain a 5'UTR derived from beta-globin mRNA, and this is mainly due to the four uORFs. Each of the four upstream AUG triplets can be recognized as a start site for translation, and no single uAUG dominates the repressive effect. The uORFs repress translation by a mechanism that is not affected by the amino acid sequence in the COOH-terminal region of the uORF-encoded peptides. The very short uORF (AUGUGA) present in ovary-specific transcripts does not repress translation. Staining of testis sections from transgenic mice carrying chimeric beta-galactosidase transgene constructs, which contain a mos 5'UTR with or without the uATGs, suggests that the uORFs can dramatically change the pattern of expression in spermatogenic cells.

The antioxidant activity test by using DPPH method from the white tea using different solvents

NASA Astrophysics Data System (ADS)

Darmajana, Doddy A.; Hadiansyah, Firman; Desnilasari, Dewi

2017-11-01

The solvents used in this study are: aquades, ethanol and glacial acetic acid. The raw material as the source of antioxidants is white tea. Pure Quercetin is used as a comparing antioxidant. The treatment design was the solvent type for extraction, while the antioxidant activity was tested using DPPH method, with IC50 as the reference of antioxidant activity value. The results of antioxidant activity tests with three different solvent types are IC50 of 22,499 µg/mL for aquades, IC50 of 13,317 µg/mL for Ethanol and IC50 of 60,555 µg/mL for Glacial Acetic Acid. As a control of the standard antioxidant activity value of Quercetin is 4,313 µg/mL.

Design trade-off between spatial resolution and power consumption in CMOS biosensor circuit based on millimeter-wave LC oscillator array

NASA Astrophysics Data System (ADS)

Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

In this paper, we describe a trade-off between spatial resolution and power consumption in an LC oscillator-based CMOS biosensor, which can detect biomolecules by observing the resonance frequency shift due to changes in the complex permittivity of the biomolecules. The optimal operating frequency and improvement in the image resolution of the sensor output require a reduction in the size of the inductor. However, it is necessary to increase the transconductance of the cross-coupling transistor to achieve the oscillation condition, although the power consumption increases. We confirmed the trade-off between the spatial resolution and the power consumption of this sensor using SPICE simulation. A test chip was fabricated using a 65 nm CMOS process, and the transition in the peak frequency and the power consumption were measured. When the outer diameter of the inductor was 46 µm, the power consumption was 31.2 mW, which matched well with the simulation results.

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE PAGES

Kanisauskas, K.; Affolder, A.; Arndt, K.; ...

2017-02-15

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE PAGES

An, Mangmang; Chen, Chufeng; Gao, Chaosong; ...

2015-12-12

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanisauskas, K.; Affolder, A.; Arndt, K.

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Mangmang; Chen, Chufeng; Gao, Chaosong

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

n/a

NASA Image and Video Library

1962-10-26

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the S-IC test stand, related facilities were built during this time. Built to the north of the massive S-IC test stand, was the F-1 Engine test stand. The F-1 test stand, a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, was designed to assist in the development of the F-1 Engine. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo, taken October 26, 1962, depicts the excavation process of the single engine F-1 stand.

n/a

NASA Image and Video Library

1962-11-15

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the S-IC test stand, related facilities were built during this time. Built to the north of the massive S-IC test stand, was the F-1 Engine test stand. The F-1 test stand, a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, was designed to assist in the development of the F-1 Engine. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo, taken November 15, 1962, depicts the excavation process of the single engine F-1 stand site.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Compact characterization of liquid absorption and emission spectra using linear variable filters integrated with a CMOS imaging camera.

PubMed

Wan, Yuhang; Carlson, John A; Kesler, Benjamin A; Peng, Wang; Su, Patrick; Al-Mulla, Saoud A; Lim, Sung Jun; Smith, Andrew M; Dallesasse, John M; Cunningham, Brian T

2016-07-08

A compact analysis platform for detecting liquid absorption and emission spectra using a set of optical linear variable filters atop a CMOS image sensor is presented. The working spectral range of the analysis platform can be extended without a reduction in spectral resolution by utilizing multiple linear variable filters with different wavelength ranges on the same CMOS sensor. With optical setup reconfiguration, its capability to measure both absorption and fluorescence emission is demonstrated. Quantitative detection of fluorescence emission down to 0.28 nM for quantum dot dispersions and 32 ng/mL for near-infrared dyes has been demonstrated on a single platform over a wide spectral range, as well as an absorption-based water quality test, showing the versatility of the system across liquid solutions for different emission and absorption bands. Comparison with a commercially available portable spectrometer and an optical spectrum analyzer shows our system has an improved signal-to-noise ratio and acceptable spectral resolution for discrimination of emission spectra, and characterization of colored liquid's absorption characteristics generated by common biomolecular assays. This simple, compact, and versatile analysis platform demonstrates a path towards an integrated optical device that can be utilized for a wide variety of applications in point-of-use testing and point-of-care diagnostics.

Design and Characterization of a Built-In CMOS TID Smart Sensor

NASA Astrophysics Data System (ADS)

Agustin, Javier; Gil, Carlos; Lopez-Vallejo, Marisa; Ituero, Pablo

2015-04-01

This paper describes a total ionization dose (TID) sensor that presents the following advantages: it is a digital sensor able to be integrated in CMOS circuits; it has a configurable sensitivity that allows radiation doses ranging from very low to high levels; its interface helps to integrate this design in a multidisciplinary sensor network; and it is self-timed, hence it does not need a clock signal. We designed, implemented and manufactured the sensor in a 0.35 μm CMOS commercial technology. It was irradiated with a 60Co source. This test was used to characterize the sensor in terms of the radiation response up to 575 krad. After irradiation, we monitored the sensor to control charge redistribution and annealing effects for 80 hours. We also exposed our design to meticulous temperature analysis from 0 to 50°C and we studied the acceleration on the annealing phenomena due to high temperatures. Sensor calibration takes into account the results of all tests. Finally we propose to use this sensor in a self-recovery system. The sensor manufactured in this work has an area of 0.047 mm 2, of which 22% is dedicated to measuring radiation. Its energy per conversion is 463 pJ.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Optical scanning tests of complex CMOS microcircuits

NASA Technical Reports Server (NTRS)

Levy, M. E.; Erickson, J. J.

1977-01-01

The new test method was based on the use of a raster-scanned optical stimulus in combination with special electrical test procedures. The raster-scanned optical stimulus was provided by an optical spot scanner, an instrument that combines a scanning optical microscope with electronic instrumentation to process and display the electric photoresponse signal induced in a device that is being tested.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Incentive memory: evidence the basolateral amygdala encodes and the insular cortex retrieves outcome values to guide choice between goal-directed actions.

PubMed

Parkes, Shauna L; Balleine, Bernard W

2013-05-15

Choice between goal-directed actions is determined by the relative value of their consequences. Such values are encoded during incentive learning and later retrieved to guide performance. Although the basolateral amygdala (BLA) and the gustatory region of insular cortex (IC) have been implicated in these processes, their relative contribution is still a matter of debate. Here we assessed whether these structures interact during incentive learning and retrieval to guide choice. In these experiments, rats were trained on two actions for distinct outcomes after which one of the two outcomes was devalued by specific satiety immediately before a choice extinction test. We first confirmed that, relative to appropriate controls, outcome devaluation recruited both the BLA and IC based on activation of the immediate early gene Arc; however, we found that infusion of the NMDAr antagonist ifenprodil into the BLA only abolished outcome devaluation when given before devaluation. In contrast, ifenprodil infusion into the IC was effective whether made before devaluation or test. We hypothesized that the BLA encodes and the IC retrieves incentive value for choice and, to test this, developed a novel sequential disconnection procedure. Blocking NMDAr activation unilaterally in the BLA before devaluation and then contralaterally in the IC before test abolished selective devaluation. In contrast, reversing the order of these infusions left devaluation intact. These results confirm that the BLA and IC form a circuit mediating the encoding and retrieval of outcome values, with the BLA encoding and the IC retrieving such values to guide choice.

A 2-year step-down withdrawal from inhaled corticosteroids in asthmatic children receiving immunotherapy.

PubMed

He, Chun-Hui; Li, Xing; Lin, Jun-Hong; Xiao, Qiang; Yu, Jia-Lu; Liu, Ying-Fen; Jiang, Wen-Hui; Chen, Chen; Deng, Li; Zhou, Jie

2017-12-01

Inhaled corticosteroids (ICSs) for treating asthma are controversial because of their negative effects on the growth of asthmatic children and without clearly defined withdrawal strategy. A 2-year ICS step-down and withdrawal strategy has been developed for asthmatic children receiving 3-year subcutaneous immunotherapy (SCIT). Eleven children were included into the SCIT group and 13 children into the ICS group. ICSs were discontinued when children met the following criteria: requiring only 1 puffper day, with good control, for at least 6 months; having a forced expiratory volume in 1 second (FEV 1 )/forced vital capacity ≥80%; and SCIT discontinued for ≥24 months. The main endpoints were the results of both the childhood asthma control test (C-CAT) and the methacholine bronchial provocation test. In the SCIT group, all the 11 children had ICS discontinued, with one child developed asthma attack after pneumonia and received ICS again after completion of SCIT. In the ICS group, five children discontinued ICS and developed asthma attacks later and received ICS again; the other eight children developed severe symptoms during ICS step-down. Thus, the discontinuation of ICS was only achieved in the SCIT group. The dose of methacholine that caused a decrease of 20% in FEV 1 continued to improve after discontinuation of ICS for the SCIT group and presented better results than the ICS group (P=0.050). After completion of SCIT, the C-CAT had improved significantly after 30 months of treatment compared with the ICS group (P<0.05). In the present study, we developed a 2-year step-down and withdrawal strategy from ICSs strategy for allergic asthma children receiving SCIT; the strategy was efficacious and safe.

Radiation Testing on State-of-the-Art CMOS: Challenges, Plans, and Preliminary Results

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2009-01-01

At GOMAC 2007 and 2008, we discussed a variety of challenges for radiation testing of modern semiconductor devices and technologies [1, 2]. In this presentation, we provide more specific details in this on-going investigation focusing on out-of-the-box lessons observed for providing radiation effects assurances as well as preliminary test results.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

NASA Astrophysics Data System (ADS)

Pan, Xiaoyu; Guo, Hongxia; Luo, Yinhong; Zhang, Fengqi; Ding, Lili

2018-03-01

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up (SEL) sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset (MCU) is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM’s MCU sensitivity. After the neutron experiment, we test the devices’ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices’ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge (ESD) testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

n/a

NASA Image and Video Library

1963-01-15

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. Built directly east of the test stand was the Block House, which served as the control center for the test stand. The two were connected by a narrow access tunnel which housed the cables for the controls. The F-1 Engine test stand was built north of the massive S-IC test stand. The F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, and was designed to assist in the development of the F-1 Engine. Capability is provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This aerial photograph, taken January 15, 1963, gives a close overall view of the newly developed test complex. Depicted in the forefront center is the S-IC test stand with towers prominent, the Block House is seen in the center just above the S-IC test stand, and the large hole to the left, located midway between the two is the F-1 test stand site.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

The DUV Stability of Superlattice-Doped CMOS Detector Arrays

NASA Technical Reports Server (NTRS)

Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

2013-01-01

JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

NASA Astrophysics Data System (ADS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-02-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Effect of Annealing Process on the Properties of Ni(55%)Cr(40%)Si(5%) Thin-Film Resistors.

PubMed

Cheng, Huan-Yi; Chen, Ying-Chung; Li, Pei-Jou; Yang, Cheng-Fu; Huang, Hong-Hsin

2015-10-02

Resistors in integrated circuits (ICs) are implemented using diffused methods fabricated in the base and emitter regions of bipolar transistor or in source/drain regions of CMOS. Deposition of thin films on the wafer surface is another choice to fabricate the thin-film resistors in ICs' applications. In this study, Ni(55%)Cr(40%)Si(5%) (abbreviated as NiCrSi) in wt % was used as the target and the sputtering method was used to deposit the thin-film resistors on Al2O3 substrates. NiCrSi thin-film resistors with different thicknesses of 30.8 nm~334.7 nm were obtained by controlling deposition time. After deposition, the thin-film resistors were annealed at 400 °C under different durations in N₂ atmosphere using the rapid thermal annealing (RTA) process. The sheet resistance of NiCrSi thin-film resistors was measured using the four-point-probe method from 25 °C to 125 °C, then the temperature coefficient of resistance could be obtained. We aim to show that resistivity of NiCrSi thin-film resistors decreased with increasing deposition time (thickness) and the annealing process had apparent effect on the sheet resistance and temperature coefficient of resistance. We also aim to show that the annealed NiCrSi thin-film resistors had a low temperature coefficient of resistance (TCR) between 0 ppm/°C and +50 ppm/°C.

A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

2010-11-07

We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems

PubMed Central

Chang, Sun-Il

2018-01-01

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm2 and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW. PMID:29342103

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.

PubMed

Chang, Sun-Il; Park, Sung-Yun; Yoon, Euisik

2018-01-17

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm² and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µV rms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

Characterization of cogon grass (Imperata cylindrica) pollen extract and preliminary analysis of grass group 1, 4 and 5 homologues using monoclonal antibodies to Phleum pratense.

PubMed

Kumar, L; Sridhara, S; Singh, B P; Gangal, S V

1998-11-01

Previous studies have established the role of Imperata cylindrica (Ic) pollen in type I allergic disorders. However, no systematic information is available on the allergen composition of Ic pollen extract. To characterize the IgE-binding proteins of Ic pollen extract and to detect the presence of grass group 1, 4 and 5 allergen homologues, if any. Pollen extract of Ic was analyzed by in vivo and in vitro procedures such as intradermal tests (ID), enzyme-linked immunosorbent assay (ELISA), ELISA-inhibition, thin-layer isoelectric focusing (TLIEF), sodium dodecylsulfate polyacrylamide gel electrophoresis (SDS-PAGE) and immunoblotting. Dot blot assay was carried out to check the presence of well-known group 1, 4, and 5 allergen homologues in Ic pollen extract. Out of 303 respiratory allergies patients skin-tested, 27 showed sensitivity to Ic pollen extract. Specific IgE levels were elevated in all 15 serum samples tested. The extract prepared for this study was found to be highly potent since it required only 400 ng of homologous proteins for 50% inhibition of binding in ELISA inhibition assays. TLIEF of Ic pollen extract showed 44 silver-stained bands (pI 3.5-7.0) while SDS-PAGE resolved it into 24 Coomassie-Brilliant-Blue-stained bands (MW 100-10 kD). Immunoblotting with individual patient sera recognized 7 major IgE-binding bands (MW 85, 62, 57, 43, 40, 28 and 16 kD) in Ic pollen extract. A panel of monoclonal antibodies, specific to group 1, 4 and 5 allergens from Phleum pratense pollen extract identified group 5 and group 4 homologues in Ic pollen extract. Ic pollen extract was characterized for the protein profile by TLIEF and SDS-PAGE. IgE reactivity was determined by ELISA and immunoblot. Monoclonal antibodies to group 5 and group 4 allergens reacted weakly showing that this pollen contains group 5 and group 4 homologous allergens.

Variability in P-Glycoprotein Inhibitory Potency (IC50) Using Various in Vitro Experimental Systems: Implications for Universal Digoxin Drug-Drug Interaction Risk Assessment Decision Criteria

PubMed Central

Bentz, Joe; O’Connor, Michael P.; Bednarczyk, Dallas; Coleman, JoAnn; Lee, Caroline; Palm, Johan; Pak, Y. Anne; Perloff, Elke S.; Reyner, Eric; Balimane, Praveen; Brännström, Marie; Chu, Xiaoyan; Funk, Christoph; Guo, Ailan; Hanna, Imad; Herédi-Szabó, Krisztina; Hillgren, Kate; Li, Libin; Hollnack-Pusch, Evelyn; Jamei, Masoud; Lin, Xuena; Mason, Andrew K.; Neuhoff, Sibylle; Patel, Aarti; Podila, Lalitha; Plise, Emile; Rajaraman, Ganesh; Salphati, Laurent; Sands, Eric; Taub, Mitchell E.; Taur, Jan-Shiang; Weitz, Dietmar; Wortelboer, Heleen M.; Xia, Cindy Q.; Xiao, Guangqing; Yabut, Jocelyn; Yamagata, Tetsuo; Zhang, Lei

2013-01-01

A P-glycoprotein (P-gp) IC50 working group was established with 23 participating pharmaceutical and contract research laboratories and one academic institution to assess interlaboratory variability in P-gp IC50 determinations. Each laboratory followed its in-house protocol to determine in vitro IC50 values for 16 inhibitors using four different test systems: human colon adenocarcinoma cells (Caco-2; eleven laboratories), Madin-Darby canine kidney cells transfected with MDR1 cDNA (MDCKII-MDR1; six laboratories), and Lilly Laboratories Cells—Porcine Kidney Nr. 1 cells transfected with MDR1 cDNA (LLC-PK1-MDR1; four laboratories), and membrane vesicles containing human P-glycoprotein (P-gp; five laboratories). For cell models, various equations to calculate remaining transport activity (e.g., efflux ratio, unidirectional flux, net-secretory-flux) were also evaluated. The difference in IC50 values for each of the inhibitors across all test systems and equations ranged from a minimum of 20- and 24-fold between lowest and highest IC50 values for sertraline and isradipine, to a maximum of 407- and 796-fold for telmisartan and verapamil, respectively. For telmisartan and verapamil, variability was greatly influenced by data from one laboratory in each case. Excluding these two data sets brings the range in IC50 values for telmisartan and verapamil down to 69- and 159-fold. The efflux ratio-based equation generally resulted in severalfold lower IC50 values compared with unidirectional or net-secretory-flux equations. Statistical analysis indicated that variability in IC50 values was mainly due to interlaboratory variability, rather than an implicit systematic difference between test systems. Potential reasons for variability are discussed and the simplest, most robust experimental design for P-gp IC50 determination proposed. The impact of these findings on drug-drug interaction risk assessment is discussed in the companion article (Ellens et al., 2013) and recommendations are provided. PMID:23620485

Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop (Poster)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lundstrom, B.; Shirazi, M.; Coddington, M.

2013-02-01

This poster describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1TM. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through themore » use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.« less

Saturn Apollo Program

NASA Image and Video Library

1965-04-16

This photograph depicts a dramatic view of the first test firing of all five F-1 engines for the Saturn V S-IC stage at the Marshall Space Flight Center. The testing lasted a full duration of 6.5 seconds. It also marked the first test performed in the new S-IC static test stand and the first test using the new control blockhouse. The S-IC stage is the first stage, or booster, of a 364-foot long rocket that ultimately took astronauts to the Moon. Operating at maximum power, all five of the engines produced 7,500,000 pounds of thrust. Required to hold down the brute force of a 7,500,000-pound thrust, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and cement, planted down to bedrock 40 feet below ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the up position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. When the Saturn V S-IC first stage was placed upright in the stand , the five F-1 engine nozzles pointed downward on a 1,900 ton, water-cooled deflector. To prevent melting damage, water was sprayed through small holes in the deflector at the rate 320,000 gallons per minute.

n/a

NASA Image and Video Library

1963-01-15

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. Built directly east of the test stand was the Block House, which served as the control center for the test stand. The two were connected by a narrow access tunnel which housed the cables for the controls. The F-1 Engine test stand was built north of the massive S-IC test stand. The F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, and was designed to assist in the development of the F-1 Engine. Capability is provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This aerial photograph, taken January 15, 1963 gives an overall view of the construction progress of the newly developed test complex. The large white building located in the center is the Block House. Just below and to the right of it is the S-IC test stand. The large hole to the left of the S-IC stand is the F-1 test stand site.

Posterior insular cortex is necessary for conditioned inhibition of fear

PubMed Central

Foilb, Allison R.; Flyer-Adams, Johanna G.; Maier, Steven F.; Christianson, John P.

2016-01-01

Veridical detection of safety versus danger is critical to survival. Learned signals for safety inhibit fear, and so when presented, reduce fear responses produced by danger signals. This phenomenon is termed conditioned inhibition of fear. Here, we report that CS+/CS− fear discrimination conditioning over 5 days in rats leads the CS− to become a conditioned inhibitor of fear, as measured by the classic tests of conditioned inhibition: summation and retardation of subsequent fear acquisition. We then show that NMDA-receptor antagonist AP5 injected to posterior insular cortex (IC) before training completely prevented the acquisition of a conditioned fear inhibitor, while intra-AP5 to anterior and medial IC had no effect. To determine if the IC contributes to the recall of learned fear inhibition, injections of the GABAA agonist muscimol were made to posterior IC before a summation test. This resulted in fear inhibition per se, which obscured inference to the effect of IC inactivation with recall of the safety cue. Control experiments sought to determine if the role of the IC in conditioned inhibition learning could be reduced to simpler fear discrimination function, but fear discrimination and recall were unaffected by AP5 or muscmiol, respectively, in the posterior IC. These data implicate a role of posterior IC in the learning of conditioned fear inhibitors. PMID:27523750

The Comfort Measures Order Set at a Tertiary Care Academic Hospital: Is There a Comparable Difference in End-of-Life Care Between Patients Dying in Acute Care When CMOS Is Utilized?

PubMed

Lau, Christine; Stilos, Kalli; Nowell, Allyson; Lau, Fanchea; Moore, Jennifer; Wynnychuk, Lesia

2018-04-01

Standardized protocols have been previously shown to be helpful in managing end-of-life (EOL) care in hospital. The comfort measures order set (CMOS), a standardized framework for assessing imminently dying patients' symptoms and needs, was implemented at a tertiary academic hospital. We assessed whether there were comparable differences in the care of a dying patient when the CMOS was utilized and when it was not. A retrospective chart review was completed on patients admitted under oncology and general internal medicine, who were referred to the inpatient palliative care team for "EOL care" between February 2015 and March 2016. Of 83 patients, 56 (67%) received intiation of the CMOS and 27 (33%) did not for EOL care. There was significant involvement of spiritual care with the CMOS (66%), as compared to the group without CMOS (19%), P < .05. The use of CMOS resulted in 1.7 adjustments to symptom management per patient by palliative care, which was significantly less than the number of symptom management adjustments per patient when CMOS was not used (3.3), P < .05. However, initiating CMOS did not result in a signficant difference in patient distress around the time of death ( P = .11). Dyspnea was the most frequently identified symptom causing distress in actively dying patients. Implementation of the CMOS is helpful in providing a foundation to a comfort approach in imminently dying patients. However, more education on its utility as a framework for EOL care and assessment across the organization is still required.

Immunogenicity testing of therapeutic antibodies in ocular fluids after intravitreal injection.

PubMed

Wessels, Uwe; Zadak, Markus; Reiser, Astrid; Brockhaus, Janis; Ritter, Mirko; Abdolzade-Bavil, Afsaneh; Heinrich, Julia; Stubenrauch, Kay

2018-04-11

High drug concentrations in ocular fluids after intravitreal administration preclude the use of drug-sensitive immunoassays. A drug-tolerant immunoassay is therefore desirable for immunogenicity testing in ophthalmology. Immune complex (IC) antidrug antibody (ADA) assays were established for two species. The assays were compared with the bridging assay in ocular and plasma samples from two preclinical studies. The IC assays showed high drug tolerance, which enabled a reliable ADA detection in ocular fluids after intravitreal administration. The IC assays were superior to the bridging assay in the analysis of ocular fluids with high drug concentrations. The IC assay allows a reliable ADA detection in matrices with high drug concentrations, such as ocular fluids.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

PubMed

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel

PubMed Central

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel. PMID:23112588

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Y.; Hu-Guo, C.; Husson, D.

2011-07-01

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial pointsmore » of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)« less

All-digital pulse-expansion-based CMOS digital-to-time converter.

PubMed

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm 2 . Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

All-digital pulse-expansion-based CMOS digital-to-time converter

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Around Marshall

NASA Image and Video Library

1963-01-14

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the S-IC test stand, related facilities were constructed during this time frame. Built just north of the massive S-IC test stand was the F-1 Engine test stand. The F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, and was designed to assist in the development of the F-1 Engine. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo, taken January 14, 1963 depicts the F-1 test stand site with hoses pumping excess water from the site.

Collimation testing using slit Fresnel diffraction

NASA Astrophysics Data System (ADS)

Luo, Xiaohe; Hui, Mei; Wang, Shanshan; Hou, Yinlong; Zhou, Siyu; Zhu, Qiudong

2018-03-01

A simple collimation testing method based on slit Fresnel diffraction is proposed. The method needs only a CMOS and a slit with no requirement in dimensional accuracy. The light beam to be tested diffracts across the slit and forms a Fresnel diffraction pattern received by CMOS. After analysis, the defocusing amount and the distance between the primary peak point and secondary peak point of diffraction pattern fulfill an expression relationship and then the defocusing amount can be deduced from the expression. The method is applied to both the coherent beam and partially coherent beam, and these two beams are emitted from a laser and light-emitting diode (LED) with a spectrum width of about 50 nm in this paper. Simulations show that the wide spectrum of LED has the effect of smooth filtering to provide higher accuracy. Experiments show that the LED with a spectrum width of about 50 nm has a lower limitation error than the laser and can achieve up to 58.1601 μm with focal length 200 mm and slit width 15 mm.

CMOS image sensors: State-of-the-art

NASA Astrophysics Data System (ADS)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

Influence of core thickness and artificial aging on the biaxial flexural strength of different all-ceramic materials: An in-vitro study.

PubMed

Dikicier, Sibel; Ayyildiz, Simel; Ozen, Julide; Sipahi, Cumhur

2017-05-31

The purpose of this study was to investigate the flexural strength of all-ceramics with varying core thicknesses submitted to aging. In-Ceram Alumina (IC), IPS e.max Press (EM) and Katana (K) (n=40), were selected. Each group contained two core groups based on the core thickness as follows: IC/0.5, IC/0.8, EM/0.5, EM/0.8, K/0.5 and K/0.8 mm in thickness (n=20 each). Ten specimens from each group were subjected to aging and all specimens were tested for strength in a testing machine either with or without being subjected aging. The mean strength of the K were higher (873.05 MPa) than that of the IC (548.28 MPa) and EM (374.32 MPa) regardless of core thickness. Strength values increased with increasing core thickness for all IC, EM and K regardless of aging. Results of this study concluded that strength was not significantly affected by aging. Different core thicknesses affected strength of the all-ceramic materials tested (p<0.05).

Interpersonal Callousness and Co-Occurring Anxiety: Developmental Validity of an Adolescent Taxonomy

PubMed Central

2016-01-01

Growing evidence suggests heterogeneity within interpersonal-callous (IC) youth based on co-occurring anxiety. The developmental validity of this proposed taxonomy remains unclear however, as most previous research is cross-sectional and/or limited to adolescence. We aimed to identify low-anxiety (IC/ANX−) and high-anxiety (IC/ANX+) IC variants, and compare these groups on (a) early risk exposures, (b) psychiatric symptoms from midchildhood to early adolescence, and (c) school-based functioning. Using the Avon Longitudinal Study of Parents and Children (ALSPAC), a prospective epidemiological birth cohort, model-based cluster analysis was performed on children with complete age-13 IC and anxiety scores (n = 6,791). Analysis of variance was used to compare resulting clusters on (a) prenatal and postnatal family adversity and maternal psychopathology, and harsh parenting; (b) developmental differences in attention-deficit/hyperactivity disorder (ADHD), conduct disorder (CD), oppositional defiant disorder (ODD), emotional difficulties, and low pro-social behavior at 7, 10, and 13 years; and (c) teacher-reported discipline problems, along with standardized test performance. We identified a 4-cluster solution: “typical,” “low,” “IC/ANX−”, and “IC/ANX+.” IC/ANX+ youth showed the highest prenatal and postnatal levels of family adversity and maternal psychopathology, highest levels of ADHD, CD, ODD, and emotional difficulties, greatest discipline problems, and lowest national test scores (all p < .001). IC/ANX+ also showed a distinct pattern of increasing psychopathology from age 7 to 13 years. Adolescent IC subtypes were successfully validated in ALSPAC across multiple raters using prenatal and early postnatal risk, repeated measures of psychopathology, and school-based outcomes. Greater prenatal environmental risk among IC/ANX+ youth suggests an important target for early intervention. PMID:27977232

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

NASA Astrophysics Data System (ADS)

Arslan, Emre; Yıldız, Merih; Minaei, Shahram

2015-06-01

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push-pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

Development of UItra-Low Temperature Motor Controllers: Ultra Low Temperatures Evaluation and Characterization of Semiconductor Technologies For The Next Generation Space Telescope

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.

2003-01-01

Electronics designed for low temperature operation will result in more efficient systems than room temperature. This improvement is a result of better electronic, electrical, and thermal properties of materials at low temperatures. In particular, the performance of certain semiconductor devices improves with decreasing temperature down to ultra-low temperature (-273 'C). The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components and systems suitable for applications in deep space missions. Research is being conducted on devices and systems for use down to liquid helium temperatures (-273 'C). Some of the components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. The work performed this summer has focused on the evaluation of silicon-, silicon-germanium- and gallium-Arsenide-based (GaAs) bipolar, MOS and CMOS discrete components and integrated circuits (ICs), from room temperature (23 'C) down to ultra low temperatures (-263 'C).

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

PubMed

Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

2012-01-01

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

NASA Astrophysics Data System (ADS)

Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

2011-08-01

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

Screening of (-SEA) α-thalassaemia using an immunochromatographic strip assay for the ζ-globin chain in a population with a high prevalence and heterogeneity of haemoglobinopathies.

PubMed

Jomoui, Wittaya; Fucharoen, Goonnapa; Sanchaisuriya, Kanokwan; Fucharoen, Supan

2017-01-01

The presence of the ζ-globin chain is a good marker of (-- SEA ) α 0 -thalassaemia. We evaluated an immunochromatographic (IC) strip assay for ζ-globin in screening for (-- SEA ) α 0 -thalassaemia in a population with a high prevalence and heterogeneity of haemoglobinopathies. The study was carried out on 300 screen positive blood samples of Thai individuals. The IC strip assay for the ζ-globin chain was performed on all samples. The results were interpreted with thalassaemia genotyping using standard haemoglobin and DNA analyses. Several thalassaemia genotypes were noted. Among the 300 subjects investigated, 79 had a positive IC strip assay for ζ-globin and (-- SEA ) α 0 -thalassaemia was identified in 40 of them. No (-- SEA ) α 0 -thalassaemia was detected in the remaining 39 samples with a positive IC strip test result or in the 221 samples with a negative IC strip test result. Further DNA analysis identified α + -thalassaemia in 25 of the 39 (-- SEA ) α 0 -thalassaemia negative samples. Using this IC strip assay in combination with a conventional screening protocol for (-- SEA ) α 0 -thalassaemia could provide sensitivity and specificity of 100% and 90.4%, respectively. IC strip assay for ζ-globin is simple, rapid and does not require sophisticated equipment. Use of this test in addition to the existing screening protocol could detect potential (-- SEA ) α 0 -thalassaemia leading to a significant reduction in the workload of DNA analysis. This could be used in areas where haemoglobinopathies are prevalent and heterogeneous but molecular testing is not available. Published by the BMJ Publishing Group Limited. For permission to use (where not already granted under a licence) please go to http://www.bmj.com/company/products-services/rights-and-licensing/.

Diagnostic and prognostic value of human prion detection in cerebrospinal fluid.

PubMed

Foutz, Aaron; Appleby, Brian S; Hamlin, Clive; Liu, Xiaoqin; Yang, Sheng; Cohen, Yvonne; Chen, Wei; Blevins, Janis; Fausett, Cameron; Wang, Han; Gambetti, Pierluigi; Zhang, Shulin; Hughson, Andrew; Tatsuoka, Curtis; Schonberger, Lawrence B; Cohen, Mark L; Caughey, Byron; Safar, Jiri G

2017-01-01

Several prion amplification systems have been proposed for detection of prions in cerebrospinal fluid (CSF), most recently, the measurements of prion seeding activity with second-generation real-time quaking-induced conversion (RT-QuIC). The objective of this study was to investigate the diagnostic performance of the RT-QuIC prion test in the broad phenotypic spectrum of prion diseases. We performed CSF RT-QuIC testing in 2,141 patients who had rapidly progressive neurological disorders, determined diagnostic sensitivity and specificity in 272 cases that were autopsied, and evaluated the impact of mutations and polymorphisms in the PRNP gene, and type 1 or type 2 human prions on diagnostic performance. The 98.5% diagnostic specificity and 92% sensitivity of CSF RT-QuIC in a blinded retrospective analysis matched the 100% specificity and 95% sensitivity of a blind prospective study. The CSF RT-QuIC differentiated 94% of cases of sporadic Creutzfeldt-Jakob disease (sCJD) MM1 from the sCJD MM2 phenotype, and 80% of sCJD VV2 from sCJD VV1. The mixed prion type 1-2 and cases heterozygous for codon 129 generated intermediate CSF RT-QuIC patterns, whereas genetic prion diseases revealed distinct profiles for each PRNP gene mutation. The diagnostic performance of the improved CSF RT-QuIC is superior to surrogate marker tests for prion diseases such as 14-3-3 and tau proteins, and together with PRNP gene sequencing the test allows the major prion subtypes to be differentiated in vivo. This differentiation facilitates prediction of the clinicopathological phenotype and duration of the disease-two important considerations for envisioned therapeutic interventions. ANN NEUROL 2017;81:79-92. © 2016 American Neurological Association.

Diagnostic and Prognostic Value of Human Prion Detection in Cerebrospinal Fluid

PubMed Central

Foutz, Aaron; Appleby, Brian S.; Hamlin, Clive; Liu, Xiaoqin; Yang, Sheng; Cohen, Yvonne; Chen, Wei; Blevins, Janis; Fausett, Cameron; Wang, Han; Gambetti, Pierluigi; Zhang, Shulin; Hughson, Andrew; Tatsuoka, Curtis; Schonberger, Lawrence B.; Cohen, Mark L.; Caughey, Byron; Safar, Jiri G.

2016-01-01

Objective Several prion amplification systems have been proposed for detection of prions in cerebrospinal fluid (CSF), most recently, the measurements of prion seeding activity with second-generation real-time quaking-induced conversion (RT-QuIC). The objective of this study was to investigate the diagnostic performance of the RT-QuIC prion test in the broad phenotypic spectrum of prion diseases. Methods We performed CSF RT-QuIC testing in 2,141 patients who had rapidly progressive neurological disorders, determined diagnostic sensitivity and specificity in 272 cases which were autopsied, and evaluated the impact of mutations and polymorphisms in the PRNP gene, and Type 1 or Type 2 of human prions on diagnostic performance. Results The 98.5% diagnostic specificity and 92% sensitivity of CSF RT-QuIC in a blinded retrospective analysis matched the 100% specificity and 95% sensitivity of a blind prospective study. The CSF RT-QuIC differentiated 94% of cases of sporadic Creutzfeldt-Jakob disease (sCJD) MM1 from the sCJD MM2 phenotype, and 80% of sCJD VV2 from sCJD VV1. The mixed prion type 1–2 and cases heterozygous for codon 129 generated intermediate CSF RT-QuIC patterns, while genetic prion diseases revealed distinct profiles for each PRNP gene mutation. Interpretation The diagnostic performance of the improved CSF RT-QuIC is superior to surrogate marker tests for prion diseases such as 14-3-3 and Tau proteins and together with PRNP gene sequencing, the test allows the major prion subtypes to be differentiated in vivo. This differentiation facilitates prediction of the clinicopathological phenotype and duration of the disease—two important considerations for envisioned therapeutic interventions. PMID:27893164

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Cargo Movement Operations System (CMOS) System Segment Design Document (Draft) Increment II

DTIC Science & Technology

1990-05-02

and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR

Validation of the Intelligibility in Context Scale for Jamaican Creole-Speaking Preschoolers.

PubMed

Washington, Karla N; McDonald, Megan M; McLeod, Sharynne; Crowe, Kathryn; Devonish, Hubert

2017-08-15

To describe validation of the Intelligibility in Context Scale (ICS; McLeod, Harrison, & McCormack, 2012a) and ICS-Jamaican Creole (ICS-JC; McLeod, Harrison, & McCormack, 2012b) in a sample of typically developing 3- to 6-year-old Jamaicans. One-hundred and forty-five preschooler-parent dyads participated in the study. Parents completed the 7-item ICS (n = 145) and ICS-JC (n = 98) to rate children's speech intelligibility (5-point scale) across communication partners (parents, immediate family, extended family, friends, acquaintances, strangers). Preschoolers completed the Diagnostic Evaluation of Articulation and Phonology (DEAP; Dodd, Hua, Crosbie, Holm, & Ozanne, 2006) in English and Jamaican Creole to establish speech-sound competency. For this sample, we examined validity and reliability (interrater, test-rest, internal consistency) evidence using measures of speech-sound production: (a) percentage of consonants correct, (b) percentage of vowels correct, and (c) percentage of phonemes correct. ICS and ICS-JC ratings showed preschoolers were always (5) to usually (4) understood across communication partners (ICS, M = 4.43; ICS-JC, M = 4.50). Both tools demonstrated excellent internal consistency (α = .91), high interrater, and test-retest reliability. Significant correlations between the two tools and between each measure and language-specific percentage of consonants correct, percentage of vowels correct, and percentage of phonemes correct provided criterion-validity evidence. A positive correlation between the ICS and age further strengthened validity evidence for that measure. Both tools show promising evidence of reliability and validity in describing functional speech intelligibility for this group of typically developing Jamaican preschoolers.

Comparsion of an immunochromatographic strip with ELISA for simultaneous detection of thiamphenicol, florfenicol and chloramphenicol in food samples.

PubMed

Guo, Lingling; Song, Shanshan; Liu, Liqiang; Peng, Juan; Kuang, Hua; Xu, Chuanlai

2015-09-01

Rapid and sensitive indirect competitive enzyme-linked immunosorbent assays (ic-ELISA) and gold nanoparticle immunochromatographic strip tests were developed to detect thiamphenicol (TAP), florfenicol (FF) and chloramphenicol (CAP) in milk and honey samples. The generic monoclonal antibody for TAP, FF and CAP was prepared based on a hapten [D-threo-1-(4-aminophenyl)-2- dichloroacetylamino-1,3-propanediol], and the haptenwas linked to a carrier protein using the diazotization method. After the optimization of several parameters (coating, pH, sodium chloride content and methanol content), the ic-ELISA was established. The quantitative working range for TAP was 0.11-1.36 ng/mL, with an IC50 of 0.39 ng/mL. The optimized ELISA showed cross-reactivity to CAP (300%) and FF (15.6%), with IC50 values of 0.13 and 2.5 ng/mL, respectively. The analytical recovery of TAP, FF and CAP in milk and honey samples in the ic-ELISA ranged from 81.2 to 112.9%. Based on this monoclonal antibody, a rapid and sensitive immunochromatographic test strip was also developed. This strip had a detection limit of 1 ng/mL for TAP, FF and CAP in milk and honey samples. Moreover, the test was completed within 10 min. Our results showed that the proposed ic-ELISA and immunochromatographic test strip method are highly useful screening tools for TAP, FF and CAP detection in milk and honey samples. Copyright © 2015 John Wiley & Sons, Ltd.

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

PubMed

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III - Grid Interconnection System Evaluator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lundstrom, B.; Shirazi, M.; Coddington, M.

2013-01-01

This paper describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through themore » use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.« less

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

A high speed and high gain CMOS receiver chip for a pulsed time-of-flight laser rangefinder

NASA Astrophysics Data System (ADS)

Yu, Jin-jin; Deng, Ruo-han; Yuan, Hong-hui; Chen, Yong-ping

2011-06-01

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed. Pulsed TOF laser range finding devices using a laser diode transmitter can achieve millimeter-level distance measurement accuracy in a measurement range of several tens of meters to non-cooperative targets. The amplifier exploits the regulated cascade (RGC) configuration as the input-stage, thus achieving as large effective input trans-conductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. To enlarge the bandwidth, inductive peaking technology has been adopted. An active inductor (MOS-L) is used instead of spiral inductor in CMOS process. An R-2R resistor ladder is inserting between per-amplifier and post-amplifier as the variable attenuator for digital gain control purpose. The gain-bandwidth of a basic differential pair with resistive load is not large enough for broad band operation. A circuit solution to improve both gain and bandwidth of an amplifying stage is proposed. Traditional and modified Cherry-Hooper amplifiers are discussed and the cascading of several stages to constitute the post-amplifier is designed. The fully integrated one-chip solution is designed with Cadence IC design platform. The simulation result shows the bandwidth of the trans-impedance amplifier is 215MHz with the presence of a 2pF input capacitor and 5pF load capacitor. And the maximum trans-impedance gain is 136dB. The walk error is less than 1ns in 1:1000 dynamic range. The responsive time is less than 2.2ns.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Synthesis of High Symmetry Phase of Hafnium Dioxide Thin Films and Nickel Ferrite's Effect on Microstructure in Composite Heterostructure

NASA Astrophysics Data System (ADS)

Straka, Weston J.

Hafnium dioxide has attracted a great deal of attention recently due to its potential use in two different electronic applications: CMOS and FeRAM. In CMOS, the usefulness of hafnia comes in due to its high dielectric constant and compatibility with current IC processing parameters. For FeRAM, hafnia's recent discovery to exhibit ferroelectricity in an orthorhombic phase makes this material attractive for replacement of the ferroelectric material in FeRAM. This study shows the feasibility of depositing thin films of hafnium oxide via chemical solution deposition for integration into these devices. The processing parameters necessary to produce this phase show how non-equilibrium processing plays a role in its synthesis. The temperature necessary to achieve the high symmetry phase was at 725 °C for 3 minutes on sapphire, silicon, and coated silicon substrates. The thermal conductivity of each was viewed as the property that allowed the hafnia formation. The dielectric constant of the hafnia films were between 30 and 32 with low dissipation factors and up to 47 with a poor dissipation factor all at 1 kHz. The formation of this phase was shown to be thickness independent with the high symmetry phase existing up to 300 nm film thickness. Interfacing the hafnia film with nickel ferrite was also studied to identify the possibility of using this composite for non-destructive reading of FeRAM. The magnetic properties showed an unchanged nickel ferrite film but the interface between the two was poor leading to the conclusion that more work must be done to successfully integrate these two films.

Comparative study of various pixel photodiodes for digital radiography: Junction structure, corner shape and noble window opening

NASA Astrophysics Data System (ADS)

Kang, Dong-Uk; Cho, Minsik; Lee, Dae Hee; Yoo, Hyunjun; Kim, Myung Soo; Bae, Jun Hyung; Kim, Hyoungtaek; Kim, Jongyul; Kim, Hyunduk; Cho, Gyuseong

2012-05-01

Recently, large-size 3-transistors (3-Tr) active pixel complementary metal-oxide silicon (CMOS) image sensors have been being used for medium-size digital X-ray radiography, such as dental computed tomography (CT), mammography and nondestructive testing (NDT) for consumer products. We designed and fabricated 50 µm × 50 µm 3-Tr test pixels having a pixel photodiode with various structures and shapes by using the TSMC 0.25-m standard CMOS process to compare their optical characteristics. The pixel photodiode output was continuously sampled while a test pixel was continuously illuminated by using 550-nm light at a constant intensity. The measurement was repeated 300 times for each test pixel to obtain reliable results on the mean and the variance of the pixel output at each sampling time. The sampling rate was 50 kHz, and the reset period was 200 msec. To estimate the conversion gain, we used the mean-variance method. From the measured results, the n-well/p-substrate photodiode, among 3 photodiode structures available in a standard CMOS process, showed the best performance at a low illumination equivalent to the typical X-ray signal range. The quantum efficiencies of the n+/p-well, n-well/p-substrate, and n+/p-substrate photodiodes were 18.5%, 62.1%, and 51.5%, respectively. From a comparison of pixels with rounded and rectangular corners, we found that a rounded corner structure could reduce the dark current in large-size pixels. A pixel with four rounded corners showed a reduced dark current of about 200fA compared to a pixel with four rectangular corners in our pixel sample size. Photodiodes with round p-implant openings showed about 5% higher dark current, but about 34% higher sensitivities, than the conventional photodiodes.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Laser as a Tool to Study Radiation Effects in CMOS

NASA Astrophysics Data System (ADS)

Ajdari, Bahar

Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam testing. In this thesis, I propose a methodology of correlating laser soft error rate (SER) to particle beam gathered data. Additionally, results are presented showing a temperature dependence of SER and the "neighbor effect" phenomenon where due to the close proximity of devices a "weakening effect" in the ON state can be observed.

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix, Version 3 Increment II

DTIC Science & Technology

1990-12-17

above SCs should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...These two documents should be in agreement with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...completeness, they should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

This ECSCRM 2016 submission presents further electrical testing and microscopic post-failure studies aimed at more comprehensive understanding of the durability limits of this extreme temperature IC technology. The results summarized represent an unprecedented combination of T 500 C semiconductor IC durability and functionality.

Posterior insular cortex is necessary for conditioned inhibition of fear.

PubMed

Foilb, Allison R; Flyer-Adams, Johanna G; Maier, Steven F; Christianson, John P

2016-10-01

Veridical detection of safety versus danger is critical to survival. Learned signals for safety inhibit fear, and so when presented, reduce fear responses produced by danger signals. This phenomenon is termed conditioned inhibition of fear. Here, we report that CS+/CS- fear discrimination conditioning over 5 days in rats leads the CS- to become a conditioned inhibitor of fear, as measured by the classic tests of conditioned inhibition: summation and retardation of subsequent fear acquisition. We then show that NMDA-receptor antagonist AP5 injected to posterior insular cortex (IC) before training completely prevented the acquisition of a conditioned fear inhibitor, while intra-AP5 to anterior and medial IC had no effect. To determine if the IC contributes to the recall of learned fear inhibition, injections of the GABAA agonist muscimol were made to posterior IC before a summation test. This resulted in fear inhibition per se, which obscured inference to the effect of IC inactivation with recall of the safety cue. Control experiments sought to determine if the role of the IC in conditioned inhibition learning could be reduced to simpler fear discrimination function, but fear discrimination and recall were unaffected by AP5 or muscimol, respectively, in the posterior IC. These data implicate a role of posterior IC in the learning of conditioned fear inhibitors. Copyright © 2016 Elsevier Inc. All rights reserved.

Using the Climbing Drum Peel (CDP) Test to Obtain a G(sub IC) value for Core/Facesheet Bonds

NASA Technical Reports Server (NTRS)

Nettles, A. T.; Gregory, Elizabeth D.; Jackson, Justin R.

2006-01-01

A method of measuring the Mode I fracture toughness of core/facesheet bonds in sandwich Structures is desired, particularly with the widespread use of models that need this data as input. This study examined if a critical strain energy release rate, G(sub IC), can be obtained from the climbing drum peel (CDP) test. The CDP test is relatively simple to perform and does not rely on measuring small crack lengths such as required by the double cantilever beam (DCB) test. Simple energy methods were used to calculate G(sub IC) from CDP test data on composite facesheets bonded to a honeycomb core. Facesheet thicknesses from 2 to 5 plies were tested to examine the upper and lower bounds on facesheet thickness requirements. Results from the study suggest that the CDP test, with certain provisions, can be used to find the GIG value of a core/facesheet bond.

Compact characterization of liquid absorption and emission spectra using linear variable filters integrated with a CMOS imaging camera

PubMed Central

Wan, Yuhang; Carlson, John A.; Kesler, Benjamin A.; Peng, Wang; Su, Patrick; Al-Mulla, Saoud A.; Lim, Sung Jun; Smith, Andrew M.; Dallesasse, John M.; Cunningham, Brian T.

2016-01-01

A compact analysis platform for detecting liquid absorption and emission spectra using a set of optical linear variable filters atop a CMOS image sensor is presented. The working spectral range of the analysis platform can be extended without a reduction in spectral resolution by utilizing multiple linear variable filters with different wavelength ranges on the same CMOS sensor. With optical setup reconfiguration, its capability to measure both absorption and fluorescence emission is demonstrated. Quantitative detection of fluorescence emission down to 0.28 nM for quantum dot dispersions and 32 ng/mL for near-infrared dyes has been demonstrated on a single platform over a wide spectral range, as well as an absorption-based water quality test, showing the versatility of the system across liquid solutions for different emission and absorption bands. Comparison with a commercially available portable spectrometer and an optical spectrum analyzer shows our system has an improved signal-to-noise ratio and acceptable spectral resolution for discrimination of emission spectra, and characterization of colored liquid’s absorption characteristics generated by common biomolecular assays. This simple, compact, and versatile analysis platform demonstrates a path towards an integrated optical device that can be utilized for a wide variety of applications in point-of-use testing and point-of-care diagnostics. PMID:27389070

Compact characterization of liquid absorption and emission spectra using linear variable filters integrated with a CMOS imaging camera

NASA Astrophysics Data System (ADS)

Wan, Yuhang; Carlson, John A.; Kesler, Benjamin A.; Peng, Wang; Su, Patrick; Al-Mulla, Saoud A.; Lim, Sung Jun; Smith, Andrew M.; Dallesasse, John M.; Cunningham, Brian T.

2016-07-01

A compact analysis platform for detecting liquid absorption and emission spectra using a set of optical linear variable filters atop a CMOS image sensor is presented. The working spectral range of the analysis platform can be extended without a reduction in spectral resolution by utilizing multiple linear variable filters with different wavelength ranges on the same CMOS sensor. With optical setup reconfiguration, its capability to measure both absorption and fluorescence emission is demonstrated. Quantitative detection of fluorescence emission down to 0.28 nM for quantum dot dispersions and 32 ng/mL for near-infrared dyes has been demonstrated on a single platform over a wide spectral range, as well as an absorption-based water quality test, showing the versatility of the system across liquid solutions for different emission and absorption bands. Comparison with a commercially available portable spectrometer and an optical spectrum analyzer shows our system has an improved signal-to-noise ratio and acceptable spectral resolution for discrimination of emission spectra, and characterization of colored liquid’s absorption characteristics generated by common biomolecular assays. This simple, compact, and versatile analysis platform demonstrates a path towards an integrated optical device that can be utilized for a wide variety of applications in point-of-use testing and point-of-care diagnostics.

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

Around Marshall

NASA Image and Video Library

1963-01-15

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. Built directly east of the test stand was the Block House, which served as the control center for the test stand. The two were connected by a narrow access tunnel which housed the cables for the controls. The F-1 Engine test stand was built north of the massive S-IC test stand. The F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, and was designed to assist in the development of the F-1 Engine. Capability is provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. Looking North, this aerial taken January 15, 1963, gives a closer view of the deep hole for the F-1 test stand site in the forefront. The S-IC test stand with towers prominent is to the right of center, and the Block House is seen left of center.

Around Marshall

NASA Image and Video Library

1963-04-17

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photograph taken April 17, 1963, gives a look at the four tower legs of the S-IC test stand at their completed height.

Around Marshall

NASA Image and Video Library

1963-11-20

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo shows the progress of the S-IC test stand as of November 20, 1963.

Around Marshall

NASA Image and Video Library

1963-02-25

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photograph taken February 25, 1963, gives a close up look at two of the ever-growing four towers of the S-IC Test Stand.

Around Marshall

NASA Image and Video Library

1963-05-07

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photograph, taken from ground level on May 7, 1963, gives a close look at one of the four towers legs of the S-IC test stand nearing its completed height.

Around Marshall

NASA Image and Video Library

1963-05-07

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photograph, taken May 7, 1963, gives a close look at the four concrete tower legs of the S-IC test stand at their completed height.

Around Marshall

NASA Image and Video Library

1963-09-18

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. This photograph taken September 18, 1963 shows a spherical hydrogen tank being constructed next to the S-IC test stand.

Around Marshall

NASA Image and Video Library

1963-10-10

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo shows the progress of the S-IC test stand as of October 10, 1963. Kerosene storage tanks can be seen to the left.

Around Marshall

NASA Image and Video Library

1961-09-07

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo shows the construction progress of the S-IC test stand as of September 7, 1961.

Construction Progress of the S-IC Test Stand-Steel Reinforcements

NASA Technical Reports Server (NTRS)

1961-01-01

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army's Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo, taken September 15, 1961, shows the installation of the reinforcing steel prior to the pouring of the concrete foundation walls.

Around Marshall

NASA Image and Video Library

1961-07-10

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In this photo, taken July 10, 1961, actual ground breaking has occurred for the S-IC test stand site.

A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

NASA Astrophysics Data System (ADS)

Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

2015-01-01

The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.

2018-05-01

This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included papers on advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.).

The effects of transistor source-to-gate bridging faults in complex CMOS gates

NASA Astrophysics Data System (ADS)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Design automation techniques for custom LSI arrays

NASA Technical Reports Server (NTRS)

Feller, A.

1975-01-01

The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

NASA Astrophysics Data System (ADS)

Kim, D.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Lattuca, A.; Mager, M.; Sielewicz, K. M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Pham, T. H.; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. W.; Yang, P.

2016-02-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

Performance and Transient Behavior of Vertically Integrated Thin-film Silicon Sensors

PubMed Central

Wyrsch, Nicolas; Choong, Gregory; Miazza, Clément; Ballif, Christophe

2008-01-01

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode. PMID:27873778

Identification of epitopes within integrin β4 for binding of auto-antibodies in ocular cicatricial and mucous membrane pemphigoid: preliminary report.

PubMed

Rashid, Khwaja Aftab; Foster, C Stephen; Ahmed, A Razzaque

2013-11-19

To identify the epitopes on human β4 integrin to which the sera of patients with ocular cicatricial pemphigoid (OCP) and mucous membrane pemphigoid (MMP) without ocular involvement bind. Fragments of the intracellular domain of the β4 molecule were cloned, expressed, purified and peptides were synthesized. Antibodies to various fragments and peptides were produced in rabbits. Binding specificity was determined via Western blot and blocking experiments. Test sera and controls were injected into neonatal BALB/c mice for in vivo passive transfer. Sera from patients with OCP, MMP, and both OCP and MMP were bound to cloned fragments of IC3.0. Its subcloned fragments IC3.4 (1489 aa-1572 aa) and IC3.4.1 (1489 aa-1510 aa) were bound with the sera from patients with OCP only. Subcloned fragments IC3.6 (1573 aa-1822 aa) and IC3.6.1 (1689 aa-1702 aa) were bound with MMP sera only. No cross-reactivity in binding was observed. Immuno-affinity-purified sera from patients with OCP, MMP, and rabbit antibodies to IC3.0, IC3.4, IC3.4.1, IC3.6, and IC3.6.1, when injected in neonatal BALB/c mice, produced subepidermal blisters in their skin. These preliminary observations identified IC3.4.1 as the possible epitope for the binding of OCP auto-antibody and IC3.6.1 as the possible epitope for the binding of MMP auto-antibody without ocular disease. Antibodies specific to these peptides produced blisters when injected in mice. Still-unidentified epitopes may exist. These observations may enhance our understanding of the role of β4 integrin in the pathobiology of OCP and MMP. Early diagnosis may be possible if serologic tests with specificity and sensitivity can be developed.

Construction Progress of the S-IC Test Stand-Pumps

NASA Technical Reports Server (NTRS)

1962-01-01

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army's Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo, taken April 4, 1961, shows the S-IC test stand dry once again when workers resumed construction after a 6 month delay due to booster size reconfiguration back in September of 1961. The disturbance of a natural spring during the excavation of the site required water to be pumped from the site continuously. The site was completely flooded after the pumps were shut down during the construction delay.

Performance test and image correction of CMOS image sensor in radiation environment

NASA Astrophysics Data System (ADS)

Wang, Congzheng; Hu, Song; Gao, Chunming; Feng, Chang

2016-09-01

CMOS image sensors rival CCDs in domains that include strong radiation resistance as well as simple drive signals, so it is widely applied in the high-energy radiation environment, such as space optical imaging application and video monitoring of nuclear power equipment. However, the silicon material of CMOS image sensors has the ionizing dose effect in the high-energy rays, and then the indicators of image sensors, such as signal noise ratio (SNR), non-uniformity (NU) and bad point (BP) are degraded because of the radiation. The radiation environment of test experiments was generated by the 60Co γ-rays source. The camera module based on image sensor CMV2000 from CMOSIS Inc. was chosen as the research object. The ray dose used for the experiments was with a dose rate of 20krad/h. In the test experiences, the output signals of the pixels of image sensor were measured on the different total dose. The results of data analysis showed that with the accumulation of irradiation dose, SNR of image sensors decreased, NU of sensors was enhanced, and the number of BP increased. The indicators correction of image sensors was necessary, as it was the main factors to image quality. The image processing arithmetic was adopt to the data from the experiences in the work, which combined local threshold method with NU correction based on non-local means (NLM) method. The results from image processing showed that image correction can effectively inhibit the BP, improve the SNR, and reduce the NU.

Cargo Movement Operations System (CMOS) Final Software User’s Manual

DTIC Science & Technology

1990-12-20

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ I COMMENT STATUS: OPEN...is correct. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS CO1MENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...RATIONALE: .."DA001041" is in the SUM but not in the SDD. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1980-01-01

This report covers the time period from May 1976 to December 1979 and encompasses the three phases of accelerated testing: Phase 1, the 250 C testing; Phase 2, the 200 C testing; and Phase 3, the 125 C testing. The duration of the test in Phase 1 and Phase 2 was sufficient to take the devices into the wear out region. The wear out distributions were used to estimate the activation energy between the 250 C and the 200 C test temperatures. The duration of the 125 C test, 20,000 hours, was not sufficient to bring the test devices into the wear out region; consequently the third data point at 125 C for determining the consistency of activation energy could not be obtained. It was estimated that, for the most complex of the three device types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment was assessed. Guidelines for the development of accelerated life test conditions were proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life test characteristics of CMOS microcircuits was explored in Phase 4 of this study and is attached as an appendix to this report.

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

6-Nitrobenzimidazole derivatives: potential phosphodiesterase inhibitors: synthesis and structure-activity relationship.

PubMed

Khan, K M; Shah, Zarbad; Ahmad, V U; Ambreen, N; Khan, M; Taha, M; Rahim, F; Noreen, S; Perveen, S; Choudhary, M I; Voelter, W

2012-02-15

6-Nitrobenzimidazole derivatives (1-30) synthesized and their phosphodiesterase inhibitory activities determined. Out of thirty tested compounds, ten showed a varying degrees of phosphodiesterase inhibition with IC(50) values between 1.5±0.043 and 294.0±16.7 μM. Compounds 30 (IC(50)=1.5±0.043 μM), 1 (IC(50)=2.4±0.049 μM), 11 (IC(50)=5.7±0.113 μM), 13 (IC(50)=6.4±0.148 μM), 14 (IC(50)=10.5±0.51 μM), 9 (IC(50)=11.49±0.08 μM), 3 (IC(50)=63.1±1.48 μM), 10 (IC(50)=120.0±4.47 μM), and 6 (IC(50)=153.2±5.6 μM) showed excellent phosphodiesterase inhibitory activity, much superior to the standard EDTA (IC(50)=274±0.007 μM), and thus are potential molecules for the development of a new class of phosphodiesterase inhibitors. A structure-activity relationship is evaluated. All compounds are characterized by spectroscopic parameters. Copyright © 2011 Elsevier Ltd. All rights reserved.

Saturn Apollo Program

NASA Image and Video Library

1964-11-01

This image shows the Saturn V S-IC-T stage (S-IC static test article) fuel tank being attached to the thrust structure in the vehicle assembly building at the Marshall Space Flight Center (MSFC). The S-IC stage utilized five F-1 engines that used liquid oxygen and kerosene as propellant and provided a combined thrust of 7,500,000 pounds.

Reliability, Validity, and Factor Structure of the Imaginative Capability Scale

ERIC Educational Resources Information Center

Liang, Chaoyun; Chia, Tsorng-Lin

2014-01-01

Three studies were combined to test the reliability, validity, and factor structure of the imaginative capability scale (ICS). The ICS was a new self-report measure, which was developed to be empirically valid and easy to administer. Study 1 consisted in an exploratory factor analysis to determine the most appropriate structure of the ICS in a…

The challenge of sCMOS image sensor technology to EMCCD

NASA Astrophysics Data System (ADS)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Around Marshall

NASA Image and Video Library

1963-11-20

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo shows the progress of the F-1 Test Stand as of November 20, 1963.

Around Marshall

NASA Image and Video Library

1962-07-03

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo depicts the construction of the F-1 test stand as of July 3, 1963. All four of its tower legs are well underway.

Around Marshall

NASA Image and Video Library

1963-04-04

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo, taken April 4, 1963 depicts the construction of the F-1 test stand foundation walls.

Around Marshall

NASA Image and Video Library

1963-04-17

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo, taken April 17, 1963 depicts the construction of the F-1 test stand foundation walls.

Around Marshall

NASA Image and Video Library

1963-09-05

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo depicts the construction of the F-1 test stand as of September 5, 1963.

Around Marshall

NASA Image and Video Library

1963-09-30

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo depicts the construction of the F-1 test stand as of September 30, 1963.

Around Marshall

NASA Image and Video Library

1963-06-24

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. North of the massive S-IC test stand, the F-1 Engine test stand was built. Designed to assist in the development of the F-1 Engine, the F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo depicts the construction of the F-1 test stand as of June 24, 1963. Two if its four tower legs are underway.

Around Marshall

NASA Image and Video Library

1963-10-22

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. Northeast of the massive S-IC test stand, the F-1 Engine test stand was built. The F-1 test stand is a vertical engine firing test stand, 239 feet in elevation and 4,600 square feet in area at the base, and was designed to assist in the development of the F-1 Engine. Capability was provided for static firing of 1.5 million pounds of thrust using liquid oxygen and kerosene. Like the S-IC stand, the foundation of the F-1 stand is keyed into the bedrock approximately 40 feet below grade. This photo depicts the fuel tanks that housed kerosene and just beyond those is the F-1 test stand.

A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

PubMed

Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

2014-12-01

A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. Copyright © 2014 Elsevier B.V. All rights reserved.

Heavy Ion and Proton Tests for Subsystem Upset.

DTIC Science & Technology

1988-03-21

R. Kennerud, P. Measel , and K. Wahlin, "Transient And Total Dose Radiation Properties Of The CMOS/SOS EPIC Chip Set", IEEE Trans. on Nucl. Sci., Vol...NS-30, No. 6, Dec. 1983 .(3) T. L. Criswell, P. R. Measel , and K. L. Wahlin, "Single Event Upset P Testing With Relativistic Heavy Ions", IEEE Trans

Backside imaging of a microcontroller with common-path digital holography

NASA Astrophysics Data System (ADS)

Finkeldey, Markus; Göring, Lena; Schellenberg, Falk; Gerhardt, Nils C.; Hofmann, Martin

2017-03-01

The investigation of integrated circuits (ICs), such as microcontrollers (MCUs) and system on a chip (SoCs) devices is a topic with growing interests. The need for fast and non-destructive imaging methods is given by the increasing importance of hardware Trojans, reverse engineering and further security related analysis of integrated cryptographic devices. In the field of side-channel attacks, for instance, the precise spot for laser fault attacks is important and could be determined by using modern high resolution microscopy methods. Digital holographic microscopy (DHM) is a promising technique to achieve high resolution phase images of surface structures. These phase images provide information about the change of the refractive index in the media and the topography. For enabling a high phase stability, we use the common-path geometry to create the interference pattern. The interference pattern, or hologram, is captured with a water cooled sCMOS camera. This provides a fast readout while maintaining a low level of noise. A challenge for these types of holograms is the interference of the reflected waves from the different interfaces inside the media. To distinguish between the phase signals from the buried layer and the surface reflection we use specific numeric filters. For demonstrating the performance of our setup we show results with devices under test (DUT), using a 1064 nm laser diode as light source. The DUTs are modern microcontrollers thinned to different levels of thickness of the Si-substrate. The effect of the numeric filter compared to unfiltered images is analyzed.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Pupal productivity in rainy and dry seasons: findings from the impact survey of a randomised controlled trial of dengue prevention in Guerrero, Mexico.

PubMed

Jiménez-Alejo, Abel; Morales-Pérez, Arcadio; Nava-Aguilera, Elizabeth; Flores-Moreno, Miguel; Apreza-Aguilar, Sinahí; Carranza-Alcaraz, Wilhelm; Cortés-Guzmán, Antonio Juan; Fernández-Salas, Ildefonso; Ledogar, Robert J; Cockcroft, Anne; Andersson, Neil

2017-05-30

The follow-up survey of a cluster-randomised controlled trial of evidence-based community mobilisation for dengue control in Nicaragua and Mexico included entomological information from the 2012 rainy and dry seasons. We used data from the Mexican arm of the trial to assess the impact of the community action on pupal production of the dengue vector Aedes aegypti in both rainy and dry seasons. Trained field workers inspected household water containers in 90 clusters and collected any pupae or larvae present for entomological examination. We calculated indices of pupae per person and pupae per household, and traditional entomological indices of container index, household index and Breteau index, and compared these between rainy and dry seasons and between intervention and control clusters, using a cluster t-test to test significance of differences. In 11,933 houses in the rainy season, we inspected 40,323 containers and found 7070 Aedes aegypti pupae. In the dry season, we inspected 43,461 containers and counted 6552 pupae. All pupae and entomological indices were lower in the intervention clusters (IC) than in control clusters (CC) in both the rainy season (RS) and the dry season (DS): pupae per container 0.12 IC and 0.24 CC in RS, and 0.10 IC and 0.20 CC in DS; pupae per household 0.46 IC and 0.82 CC in RS, and 0.41 IC and 0.83 CC in DS; pupae per person 0.11 IC and 0.19 CC in RS, and 0.10 IC and 0.20 CC in DS; household index 16% IC and 21% CC in RS, and 12.1% IC and 17.9% CC in DS; container index 7.5% IC and 11.5% CC in RS, and 4.6% IC and 7.1% CC in DS; Breteau index 27% IC and 36% CC in RS, and 19% IC and 29% CC in DS. All differences between the intervention and control clusters were statistically significant, taking into account clustering. The trial intervention led to significant decreases in pupal and conventional entomological indices in both rainy and dry seasons. ISRCTN27581154 .

Urchin-like gold nanoparticle-based immunochromatographic strip test for rapid detection of fumonisin B1 in grains.

PubMed

Ren, Wenjie; Huang, Zhibing; Xu, Yang; Li, Yanping; Ji, Yanwei; Su, Baowei

2015-09-01

An immunochromatographic strip (ICS) using urchin-like gold nanoparticles (UGNs) for sensitive detection of fumonisin B1 (FB1) was developed to meet the requirement for rapidly monitoring FB1 in grain samples. The sensitivity of the ICS was 5.0 ng/mL, which represents a fourfold increase in sensitivity over conventional strip preparation using colloidal gold as the antibody-labeled probe. Analysis of FB1 in grain samples showed that data obtained from the strip tests were in a good agreement with those obtained from HPLC and enzyme-linked immunosorbent assays (ELISAs). This qualitative test did not require any specialized equipment, and the detection time was less than 5 min, which is suitable for on-site testing of FB1 in grain samples. Overall, to our knowledge, this is the first report of using a UGN as the antibody-labeled probe for sensitive detection of FB1 in grains using an ICS. Graphical Abstract Preparation of ICS using conventional colloidal gold and urchin-like gold nanoparticle, respectively.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

NASA Technical Reports Server (NTRS)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

Analyzing CMOS/SOS fabrication for LSI arrays

NASA Technical Reports Server (NTRS)

Ipri, A. C.

1978-01-01

Report discusses set of design rules that have been developed as result of work with test arrays. Set of optimum dimensions is given that would maximize process output and would correspondingly minimize costs in fabrication of large-scale integration (LSI) arrays.

Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

NASA Technical Reports Server (NTRS)

Lee, C.; Johnston, A.

1998-01-01

This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

The effects of iris-ciliary complex on the organ cultured rabbit ocular lens.

PubMed

Niyogi, T K; Emanuel, K; Parafina, J; Bagchi, M

1991-01-01

Freshly isolated rabbit lenses were cultured with and without attached iris-ciliary (IC)-complex for 24 hours in TC-199 medium. Subsequent morphological analysis revealed that the IC-complex cannot be maintained in serum-free medium. In addition an observed effect of the IC-complex on the co-cultured lenses could not be due only because of the cellular degeneration of the IC-complex. To test this possibility lenses with attached IC-complexes were incubated in 20% serum-containing TC-199 medium. The IC-complex cultured in 20% serum containing medium retained its normal morphology. However co-cultured lens cells displayed vacuoles and other signs of degeneration. The protein synthetic and Na+/K+ pump activities of these lenses were also significantly depressed. These data indicated that the observed effects of IC-complex on the lens were not due to its cellular degradation. Preliminary experiments showed that the IC-complex contains water soluble factor(s) which could effectively inhibit lens protein synthesis and Na+/K+ pump.

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

NASA Technical Reports Server (NTRS)

Cole, Edward H.; Smeins, Larry G.

1991-01-01

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

A wirelessly powered electro-acupuncture based on adaptive pulsewidth monophase stimulation.

PubMed

Kiseok Song; Long Yan; Seulki Lee; Yoo, Jerald; Hoi-Jun Yoo

2011-04-01

A wirelessly powered electro-acupuncture (EA) system with adaptive-pulsewidth (APW) monophase stimulation is presented for convenient invasive medicine. The proposed system removes cumbersome wires connected between EA nodes and an EA controller in order to realize both patients' convenience and remedial values simultaneously. An ultra-low-power stimulator integrated circuit (IC) that is integrated on the flexible-printed-circuit board (F-PCB) is attached to the tip of a needle electrode. Combined with a conductive yarn helical antenna wound around the needle electrode, the EA node receives wireless power from the EA controller using 433 MHz with the maximum loss of 6 dB. A zero-Vth nMOS rectifier harvests a supply voltage of 1.0 V from a -16-dBm incoming power signal with 32% efficiency. To deal with a body impedance variation (BIV) in the range of 100-200 kΩ , the proposed APW stimulator IC, fabricated in a 0.18-μm 1P6M complementary metal-oxide semiconductor CMOS process and occupying 1.56 mm(2), enables constant charge injection of 80-nC/stimulation. To ensure the patients' safety, the EA node (a pair of EAs) shares ground and clock wires to operate in alternate monophase (AMP) fashion for neutralizing the injected charge. The proposed wirelessly powered EA node was verified by applying it to a chunk of pork as a body model with the wireless power supplied from an RF signal generator (output power of 10 dBm and located 30 cm away).

Interfacial Fracture Toughness of Adhesive Resin Cement-Lithium-Disilicate/Resin-Composite Blocks.

PubMed

Mesmar, Samer; Ruse, N Dorin

2017-09-15

Resin composite blocks (RCB) are advocated as alternative to ceramic blocks (CB). Prior to use, adherence to these materials should characterized. This study aimed to test the null hypothesis (H 0 ) that material and surface treatment combinations do not influence interfacial fracture toughness (K IC ) of a self-cured adhesive resin cement [RelyX Ultimate (RXU)] to RCB or CB, under nonaged and aged conditions. Two RCB, Lava Ultimate (LU) and Enamic (EN), and one CB, IPS e.max Press (EMP) were used. Half-size [(6 × 6 × 6 × 6 mm)] specimens were prepared for EMP (n = 30), EN (n = 30), and LU (n = 60). RCB specimens were prepared by wet cutting/grinding, while CB specimens were pressed. Surfaces of EMP and EN were preconditioned with hydrofluoric acid (5%); surfaces of LU were sandblasted with either 27 μm alumina (LUS) or 30 μm silica-modified alumina Rocatec soft (LUR). All specimens were bonded with Scotchbond Universal adhesive and RXU. Additionally, twenty (4 × 4 × 4 × 8 mm) RXU specimens were prepared. All specimens were stored in water at 37°C and tested after 1 and 60 days. Interfacial K IC was determined with the notchless triangular prism specimen K IC test. Results were analyzed with two-way ANOVA and Scheffé multiple means comparisons (α = 0.05). Preconditioned and selected fractured surfaces were characterized with scanning electron microscopy. At 24 hours, LUS-RXU and LUR-RXU had significantly higher interfacial K IC than EN-RXU and EMP-RXU and were not different from K IC of RXU. Aging lead to a significant decrease in K IC of RXU and interfacial K IC of LUS-RXU, LUR-RXU, and EMP-RXU; interfacial K IC of EN-RXU was not affected. Based on the results, H 0 was rejected. Under the conditions of this study, at 24 hours, interfacial K IC of LUS-RXU and LUR-RXU was superior to EMP-RXU and EN-RXU. Aging in water at 37°C did not affect interfacial K IC of EN-RXU but adversely affected K IC of RXU and the other interfacial K IC . The results suggest that RXU and its adherence to LU and EMP deteriorates upon exposure to water at 37°C. In making clinical decisions related to material selection, practitioners should consider in vitro results. © 2017 by the American College of Prosthodontists.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T = 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Comparison of isolated-check visual evoked potential and standard automated perimetry in early glaucoma and high-risk ocular hypertension

PubMed Central

Chen, Xiang-Wu; Zhao, Ying-Xi

2017-01-01

AIM To compare the diagnostic performance of isolated-check visual evoked potential (icVEP) and standard automated perimetry (SAP), for evaluating the application values of icVEP in the detection of early glaucoma. METHODS Totally 144 subjects (288 eyes) were enrolled in this study. icVEP testing was performed with the Neucodia visual electrophysiological diagnostic system. A 15% positive-contrast (bright) condition pattern was used in this device to differentiate between glaucoma patients and healthy control subjects. Signal-to-noise ratios (SNR) were derived based on a multivariate statistic. The eyes were judged as abnormal if the test yielded an SNR≤1. SAP testing was performed with the Humphrey Field Analyzer II. The visual fields were deemed as abnormality if the glaucoma hemifield test results outside normal limits; or the pattern standard deviation with P<0.05; or the cluster of three or more non-edge points on the pattern deviation plot in a single hemifield with P<0.05, one of which must have a P<0.01. Disc photographs were graded as either glaucomatous optic neuropathy or normal by two experts who were masked to all other patient information. Moorfields regression analysis (MRA) used as a separate diagnostic classification was performed by Heidelberg retina tomograph (HRT). RESULTS When the disc photograph grader was used as diagnostic standard, the sensitivity for SAP and icVEP was 32.3% and 38.5% respectively and specificity was 82.3% and 77.8% respectively. When the MRA Classifier was used as the diagnostic standard, the sensitivity for SAP and icVEP was 48.6% and 51.4% respectively and specificity was 84.1% and 78.0% respectively. When the combined structural assessment was used as the diagnostic standard, the sensitivity for SAP and icVEP was 59.2% and 53.1% respectively and specificity was 84.2% and 84.6% respectivlely. There was no statistical significance between the sensitivity or specificity of SAP and icVEP, regardless of which diagnostic standard was based on. CONCLUSION The diagnostic performance of icVEP is not better than that of SAP in the detection of early glaucoma. PMID:28503434

Piper aduncum against Haemonchus contortus isolates: cross resistance and the research of natural bioactive compounds.

PubMed

Gaínza, Yousmel Alemán; Fantatto, Rafaela Regina; Chaves, Francisco Celio Maia; Bizzo, Humberto Ribeiro; Esteves, Sérgio Novita; Chagas, Ana Carolina de Souza

2016-01-01

The anthelminthic activity of the essential oil (EO) of Piper aduncum L. was tested in vitro on eggs and larvae of resistant (Embrapa2010) and susceptible (McMaster) isolates of Haemonchus contortus. The EO was obtained by steam distillation and its components identified by chromatography. EO concentrations of 12.5 to 0.02 mg/mL were used in the egg hatch test (EHT) and concentrations of 3.12 to 0.01 mg/mL in the larval development test (LDT). Inhibition concentrations (IC) were determined by the SAS Probit procedure, and significant differences assessed by ANOVA followed by Tukey's test. In the EHT, the IC50 for the susceptible isolate was 5.72 mg/mL. In the LDT, the IC50 and IC90 were, respectively, 0.10 mg/mL and 0.34 mg/mL for the susceptible isolate, and 0.22 mg/mL and 0.51 mg/mL for the resistant isolate. The EO (dillapiole 76.2%) was highly efficacious on phase L1. Due to the higher ICs obtained for the resistant isolate, it was raised the hypothesis that dillapiole may have a mechanism of action that resembles those of other anthelmintic compounds. We further review and discuss studies, especially those conducted in Brazil, that quantified the major constituents of P. aduncum-derived EO.

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Characterization and development of an event-driven hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher

2015-06-01

Hybrid CMOS detectors (HCD) have provided great benefit to the infrared and optical fields of astronomy, and they are poised to do the same for X-ray astronomy. Infrared HCDs have already flown on the Hubble Space Telescope and the Wide-Field Infrared Survey Explorer (WISE) mission and are slated to fly on the James Webb Space Telescope (JWST). Hybrid CMOS X-ray detectors offer low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up. The fast readout time is necessary for future high throughput X-ray missions. The Speedster-EXD X-ray HCD presented in this dissertation offers new in-pixel features and reduces known noise sources seen on previous generation HCDs. The Speedster-EXD detector makes a great step forward in the development of these detectors for future space missions. This dissertation begins with an overview of future X-ray space mission concepts and their detector requirements. The background on the physics of semiconductor devices and an explanation of the detection of X-rays with these devices will be discussed followed by a discussion on CCDs and CMOS detectors. Next, hybrid CMOS X-ray detectors will be explained including their advantages and disadvantages. The Speedster-EXD detector and its new features will be outlined including its ability to only read out pixels which contain X-ray events. Test stand design and construction for the Speedster-EXD detector is outlined and the characterization of each parameter on two Speedster-EXD detectors is detailed including read noise, dark current, interpixel capacitance crosstalk (IPC), and energy resolution. Gain variation is also characterized, and a Monte Carlo simulation of its impact on energy resolution is described. This analysis shows that its effect can be successfully nullified with proper calibration, which would be important for a flight mission. Appendix B contains a study of the extreme tidal disruption event, Swift J1644+57, to search for periodicities in its X-ray light curve. iii.

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At an earlier conference we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art CMOS technologies. In this presentation, we extend this discussion focusing on the following areas: (1) Device packaging, (2) Evolving physical single even upset mechanisms, (3) Device complexity, and (4) the goal of understanding the limitations and interpretation of radiation testing results.

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

NASA Astrophysics Data System (ADS)

Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

2018-03-01

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaria, N.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. Lastly, the collaborationmore » is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.« less

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

HEMATOPOIETIC PROGENITOR CELL CONTENT OF VERTEBRAL BODY MARROW USED FOR COMBINED SOLID ORGAN AND BONE MARROW TRANSPLANTATION

PubMed Central

Rybka, Witold B.; Fontes, Paulo A.; Rao, Abdul S.; Winkelstein, Alan; Ricordi, Camillo; Ball, Edward D.; Starzl, Thomas E.

2010-01-01

While cadaveric vertebral bodies (VB) have long been proposed as a suitable source of bone marrow (BM) for transplantation (BMT), they have rarely been used for this purpose. We have infused VB BM immediately following whole organ (WO) transplantation to augment donor cell chimerism. We quantified the hematopoietic progenitor cell (HPC) content of VB BM as well as BM obtained from the iliac crests (IC) of normal allogeneic donors (ALLO) and from patients with malignancy undergoing autologous marrow harvest (AUTO). Patients undergoing WOIBM transplantation also had AUTO BM harvested in the event that subsequent lymphohematopoietic reconstitution was required. Twenty-four VB BM, 24 IC BM-ALLO, 31 IC AUTO, and 24 IC WO-AUTO were harvested. VB BM was tested 12 to 72 hr after procurement and infused after completion ofWO grafting. IC BM was tested and then used or cryopreserved immediately. HPC were quantified by clonal assay measuring CFU-GM, BFU-E, and CFU-GEMM, and by flow cytometry for CD34+ progenitor cells. On an average, 9 VB were processed during each harvest, and despite an extended processing time the number of viable nucleated cells obtained was significantly higher than that from IC. Furthermore, by HPC content, VB BM was equivalent to IC BM, which is routinely used for BMT. We conclude that VB BM is a clinically valuable source of BM for allogeneic transplantation. PMID:7701582

Predictors of dynamic hyperinflation during the 6-minute walk test in stable chronic obstructive pulmonary disease patients

PubMed Central

Chen, Rui; Lin, Lin; Tian, Jing-Wei; Zeng, Bin; Zhang, Lei

2015-01-01

Background Dynamic hyperinflation (DH) is a major contributor to exercise limitation in chronic obstructive pulmonary disease (COPD). Therefore, we aimed to elucidate the physiological factors responsible for DH development during the 6-minute walk test (6MWT) in COPD patients and compare ventilatory response to the 6MWT in hyperinflators and non-hyperinflators. Methods A total of 105 consecutive subjects with stable COPD underwent a 6MWT, and the Borg dyspnea scale, oxygen saturation (SpO2), breathing pattern, and inspiratory capacity (IC) were recorded before and immediately after walking. The change in IC was measured, and subjects were divided into hyperinflators (ΔIC >0.0 L) and non-hyperinflators (ΔIC ≤0.0 L). Spirometry, the Modified Medical Research Council (MMRC) dyspnea scale and St George’s Respiratory Questionnaire (SGRQ) were also assessed. Results DH was present in 66.67% of subjects. ΔIC/IC was significantly and negatively correlated with the small airway function. On multiple stepwise regression analysis forced expiratory flow after exhaling 50% of the forced vital capacity (FEF50%) was the only predictor of ΔIC/IC. Non-hyperinflators had a higher post-walking VT (t=2.419, P=0.017) and post-walking VE (t=2.599, P=0.011) than the hyperinflators did. Age and resting IC were independent predictors of the 6-minute walk distance (6MWD) in hyperinflators. Conclusions DH was considerably common in subjects with COPD. Small airway function may partly contribute to the DH severity during walking. The ventilator response to the 6MWT differed between hyperinflators and non-hyperinflators. Resting hyperinflation is an important predictor of functional exercise capacity in hyperinflators. PMID:26380729

Persistence of Circulating Hepatitis C Virus Antigens-Specific Immune Complexes in Patients with Resolved HCV Infection.

PubMed

Hu, Ke-Qin; Cui, Wei

2018-05-01

Our recent study indicated the possible presence of detectable hepatitis C virus antigens (HCV-Ags) after denaturation of sera with resolved HCV (R-HCV) infection. The present study determined and characterized persistent HCV-Ags-specific immune complexes (ICs) in these patients. Sixty-eight sera with R-HCV and 34 with viremic HCV (V-HCV) infection were tested for free and IC-bound HCV-Ags using HCV-Ags enzyme immunoassay (EIA), the presence of HCV-Ags-specific ICs by immunoprecipitation and Western blot (IP-WB), HCV ICs containing HCV virions using IP and HCV RNA RT-PCR, and correlation of HCV ICs with clinical presentation in these patients. Using HCV-Ags EIA, we found 57.4% of sera with R-HCV infection were tested positive for bound, but not free HCV-Ags. Using pooled or individual anti-HCV E1/E2, cAg, NS3, NS4b, and/or NS5a to precipitate HCV-specific-Ags, we confirmed persistent HCV-Ags ICs specific to various HCV structural and non-structural proteins not only in V-HCV infection, but also in R-HCV infection. Using IP and HCV RNA PCR, we then confirmed the presence of HCV virions within circulating ICs in V-HCV, but not in R-HCV sera. Multivariable analysis indicated significant and independent associations of persistent circulating HCV-Ags-specific ICs with both age and the presence of cirrhosis in patients with R-HCV infection. Various HCV-Ag-specific ICs, but not virions, persist in 57.4% of patients who had spontaneous or treatment-induced HCV clearance for 6 months to 20 years. These findings enriched our knowledge on HCV pathogenesis and support further study on its long-term clinical relevance, such as extrahepatic manifestation, transfusion medicine, and hepatocarcinogenesis.

Importance of ion energy on SEU in CMOS SRAMs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dodd, P.E.; Shaneyfelt, M.R.; Sexton, F.W.

1998-03-01

The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... credit union may invest in and hold exchangeable collateralized mortgage obligations (exchangeable CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio of the market...

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Cargo Movement Operations System (CMOS). Final Software Requirements Specification, (Applications CSCI), Increment II

DTIC Science & Technology

1991-01-29

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL Nt3MBFR: SRS1-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...floppy diskette interface with CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES ( 3 NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

NASA Astrophysics Data System (ADS)

de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

2008-05-01

CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

Contrast sensitivity measured by two different test methods in healthy, young adults with normal visual acuity.

PubMed

Koefoed, Vilhelm F; Baste, Valborg; Roumes, Corinne; Høvding, Gunnar

2015-03-01

This study reports contrast sensitivity (CS) reference values obtained by two different test methods in a strictly selected population of healthy, young adults with normal uncorrected visual acuity. Based on these results, the index of contrast sensitivity (ICS) is calculated, aiming to establish ICS reference values for this population and to evaluate the possible usefulness of ICS as a tool to compare the degree of agreement between different CS test methods. Military recruits with best eye uncorrected visual acuity 0.00 LogMAR or better, normal colour vision and age 18-25 years were included in a study to record contrast sensitivity using Optec 6500 (FACT) at spatial frequencies of 1.5, 3, 6, 12 and 18 cpd in photopic and mesopic light and CSV-1000E at spatial frequencies of 3, 6, 12 and 18 cpd in photopic light. Index of contrast sensitivity was calculated based on data from the three tests, and the Bland-Altman technique was used to analyse the agreement between ICS obtained by the different test methods. A total of 180 recruits were included. Contrast sensitivity frequency data for all tests were highly skewed with a marked ceiling effect for the photopic tests. The median ICS for Optec 6500 at 85 cd/m2 was -0.15 (95% percentile 0.45), compared with -0.00 (95% percentile 1.62) for Optec at 3 cd/m2 and 0.30 (95% percentile 1.20) FOR CSV-1000E. The mean difference between ICSFACT 85 and ICSCSV was -0.43 (95% CI -0.56 to -0.30, p<0.00) with limits of agreement (LoA) within -2.10 and 1.22. The regression line on the difference of average was near to zero (R2=0.03). The results provide reference CS and ICS values in a young, adult population with normal visual acuity. The agreement between the photopic tests indicated that they may be used interchangeably. There was little agreement between the mesopic and photopic tests. The mesopic test seemed best suited to differentiate between candidates and may therefore possibly be useful for medical selection purposes. © 2014 Acta Ophthalmologica Scandinavica Foundation. Published by John Wiley & Sons Ltd.

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

NASA Technical Reports Server (NTRS)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Yu-Qian; Modjaz, Maryam; Bianco, Federica B., E-mail: YL1260@nyu.edu, E-mail: mmodjaz@nyu.edu

Super-luminous supernovae (SLSNe) are tremendously luminous explosions whose power sources and progenitors are highly debated. Broad-lined SNe Ic (SNe Ic-bl) are the only type of SNe that are connected with long-duration gamma-ray bursts (GRBs). Studying the spectral similarity and difference between the populations of hydrogen-poor SLSNe (SLSNe Ic) and of hydrogen-poor stripped-envelope core-collapse SNe, in particular SNe Ic and SNe Ic-bl, can provide crucial observations to test predictions of theories based on various power source models and progenitor models. In this paper, we collected all of the published optical spectra of 32 SLSNe Ic, 21 SNe Ic-bl, as well asmore » 17 SNe Ic, quantified their spectral features, constructed average spectra, and compared them in a systematic way using new tools we have developed. We find that SLSNe Ic and SNe Ic-bl, including those connected with GRBs, have comparable widths for their spectral features and average absorption velocities at all phases. Thus, our findings strengthen the connection between SLSNe Ic and GRBs. In particular, SLSNe Ic have average Fe ii λ 5169 absorption velocities of −15,000 ± 2600 km s{sup −1} at 10 days after peak, which are higher than those of SNe Ic by ∼7000 km s{sup −1} on average. SLSNe Ic also have significantly broader Fe ii λ 5169 lines than SNe Ic. Moreover, we find that such high absorption and width velocities of SLSNe Ic may be hard to explain with the interaction model, and none of the 13 SLSNe Ic with measured absorption velocities spanning over 10 days has a convincing flat velocity evolution, which is inconsistent with the magnetar model in one dimension. Lastly, we compare SN 2011kl, the first SN connected with an ultra-long GRB, with the mean spectrum of SLSNe Ic and of SNe Ic-bl.« less

Saturn Apollo Program

NASA Image and Video Library

1965-02-01

This photograph shows a fuel tank lower half for the Saturn V S-IC-T stage (the S-IC stage for static testing) on a C-frame transporter inside the vertical assembly building at the Marshall Space Flight Center.

Around Marshall

NASA Image and Video Library

1963-10-22

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. This photo shows the progress of the S-IC test stand as of October 22, 1963. Spherical liquid hydrogen tanks can be seen to the left. Just to the lower front of those are the cylindrical liquid oxygen (LOX) tanks.

Around Marshall

NASA Image and Video Library

1963-09-05

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In addition to the stand itself, related facilities were constructed during this time. In the center portion of this photograph, taken September 5, 1963, the spherical hydrogen storage tanks are being constructed. One of the massive tower legs of the S-IC test stand is visible to the far right.

Around Marshall

NASA Image and Video Library

1961-06-01

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In this photo, taken July 13, 1961, progress is being made with the excavation of the S-IC test stand site. During the digging, a natural spring was disturbed which caused a constant flooding problem. Pumps were used to remove the water all through the construction process and the site is still pumped today.

Around Marshall

NASA Image and Video Library

1963-03-29

At its founding, the Marshall Space Flight Center (MSFC) inherited the Army’s Jupiter and Redstone test stands, but much larger facilities were needed for the giant stages of the Saturn V. From 1960 to 1964, the existing stands were remodeled and a sizable new test area was developed. The new comprehensive test complex for propulsion and structural dynamics was unique within the nation and the free world, and they remain so today because they were constructed with foresight to meet the future as well as on going needs. Construction of the S-IC Static test stand complex began in 1961 in the west test area of MSFC, and was completed in 1964. The S-IC static test stand was designed to develop and test the 138-ft long and 33-ft diameter Saturn V S-IC first stage, or booster stage, weighing in at 280,000 pounds. Required to hold down the brute force of a 7,500,000-pound thrust produced by 5 F-1 engines, the S-IC static test stand was designed and constructed with the strength of hundreds of tons of steel and 12,000,000 pounds of cement, planted down to bedrock 40 feet below ground level. The foundation walls, constructed with concrete and steel, are 4 feet thick. The base structure consists of four towers with 40-foot-thick walls extending upward 144 feet above ground level. The structure was topped by a crane with a 135-foot boom. With the boom in the upright position, the stand was given an overall height of 405 feet, placing it among the highest structures in Alabama at the time. In the early stages of excavation, a natural spring was disturbed that caused a water problem which required constant pumping from the site and is even pumped to this day. Behind this reservoir of pumped water is the S-IC test stand boasting its ever-growing four towers as of March 29, 1963.