A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

PubMed

Zhou, Zhijun; Warr, Paul A

2016-12-01

Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

PubMed

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Matched wideband low-noise amplifiers for radio astronomy.

PubMed

Weinreb, S; Bardin, J; Mani, H; Jones, G

2009-04-01

Two packaged low noise amplifiers for the 0.3-4 GHz frequency range are described. The amplifiers can be operated at temperatures of 300-4 K and achieve noise temperatures in the 5 K range (<0.1 dB noise figure) at 15 K physical temperature. One amplifier utilizes commercially available, plastic-packaged SiGe transistors for first and second stages; the second amplifier is identical except it utilizes an experimental chip transistor as the first stage. Both amplifiers use resistive feedback to provide input reflection coefficient S11<-10 dB over a decade bandwidth with gain over 30 dB. The amplifiers can be used as rf amplifiers in very low noise radio astronomy systems or as i.f. amplifiers following superconducting mixers operating in the millimeter and submillimeter frequency range.

Cryogenic ultra-low-noise SiGe transistor amplifier.

PubMed

Ivanov, B I; Trgala, M; Grajcar, M; Il'ichev, E; Meyer, H-G

2011-10-01

An ultra-low-noise one-stage SiGe heterojunction bipolar transistor amplifier was designed for cryogenic temperatures and a frequency range of 10 kHz-100 MHz. A noise temperature T(N) ≈ 1.4 K was measured at an ambient temperature of 4.2 K at frequencies between 100 kHz and 100 MHz for a source resistance of ~50 Ω. The voltage gain of the amplifier was 25 dB at a power consumption of 720 μW. The input voltage noise spectral density of the amplifier is about 35 pV/√Hz. The low noise resistance and power consumption makes the amplifier suitable for readout of resistively shunted DC SQUID magnetometers and amplifiers.

Ku band low noise parametric amplifier

NASA Technical Reports Server (NTRS)

1976-01-01

A low noise, K sub u-band, parametric amplifier (paramp) was developed. The unit is a spacecraft-qualifiable, prototype, parametric amplifier for eventual application in the shuttle orbiter. The amplifier was required to have a noise temperature of less than 150 K. A noise temperature of less than 120 K at a gain level of 17 db was achieved. A 3-db bandwidth in excess of 350 MHz was attained, while deviation from phase linearity of about + or - 1 degree over 50 MHz was achieved. The paramp operates within specification over an ambient temperature range of -5 C to +50 C. The performance requirements and the operation of the K sub u-band parametric amplifier system are described. The final test results are also given.

External Peltier Cooler For Low-Noise Amplifier

NASA Technical Reports Server (NTRS)

Soper, Terry A.

1990-01-01

Inexpensive Peltier-effect cooling module made of few commercially available parts used to reduce thermal noise in microwave amplifier. Retrofitted to almost any microwave low-noise amplifier or receiver preamplifier used in communication, telemetry, or radar. Includes copper or aluminum cold plate held tightly against unit to be cooled by strap-type worm-gear clamps.

Design of ultra-low power biopotential amplifiers for biosignal acquisition applications.

PubMed

Zhang, Fan; Holleman, Jeremy; Otis, Brian P

2012-08-01

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

An integrated CMOS bio-potential amplifier with a feed-forward DC cancellation topology.

PubMed

Parthasarathy, Jayant; Erdman, Arthur G; Redish, Aaron D; Ziaie, Babak

2006-01-01

This paper describes a novel technique to realize an integrated CMOS bio-potential amplifier with a feedforward DC cancellation topology. The amplifier is designed to provide substantial DC cancellation even while amplifying very low frequency signals. More than 80 dB offset rejection ratio is achieved without any external capacitors. The cancellation scheme is robust against process and temperature variations. The amplifier is fabricated through MOSIS AMI 1.5 microm technology (0.05 mm2 area). Measurement results show a gain of 43.5 dB in the pass band (<1 mHz-5 KHz), an input referred noise of 3.66 microVrms, and a current consumption of 22 microA.

Low-Noise Amplifier for 100 to 180 GHz

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka; Pukala, David; Fung, King Man; Gaier, Todd; Mei, Xiaobing; Lai, Richard; Deal, William

2009-01-01

A three-stage monolithic millimeter-wave integrated-circuit (MMIC) amplifier designed to exhibit low noise in operation at frequencies from about 100 to somewhat above 180 GHz has been built and tested. This is a prototype of broadband amplifiers that have potential utility in diverse applications, including measurement of atmospheric temperature and humidity and millimeter-wave imaging for inspecting contents of opaque containers. Figure 1 depicts the amplifier as it appears before packaging. Figure 2 presents data from measurements of the performance of the amplifier as packaged in a WR-05 waveguide and tested in the frequency range from about 150 to about 190 GHz. The amplifier exhibited substantial gain throughout this frequency range. Especially notable is the fact that at 165 GHz, the noise figure was found to be 3.7 dB, and the noise temperature was found to be 370 K: This is less than half the noise temperature of the prior state of the art.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

A low-noise current-sensitive amplifier-discriminator system for beta particle counting.

PubMed

Sephton, J P; Johansson, L C; Williams, J M

2008-01-01

NPL has developed a low-noise current amplifier/discriminator system for radionuclides that emit low-energy electrons and X-rays. The new beta amplifier is based on the low-noise Amptek A-250 operational amplifier. The design has been configured for optimum signal to noise ratio. The new amplifier is described and results obtained using primarily electron-capture decaying radionuclides are presented. The new amplifier gives rise to higher particle detection efficiency than the previously used Atomic Energy of Canada Limited-designed amplifier. This is shown by measurements of (54)Mn and (65)Zn. The counting plateaux are significantly longer and have reduced gradients.

Ultra-low noise miniaturized neural amplifier with hardware averaging.

PubMed

Dweiri, Yazan M; Eggers, Thomas; McCallum, Grant; Durand, Dominique M

2015-08-01

Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (<3 μVrms 700 Hz-7 kHz), thereby requiring a baseline noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating <1.5 μVrms total recording baseline noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the presence of high source impedances that are

Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor.

PubMed

Majidzadeh, V; Schmid, A; Leblebici, Y

2011-06-01

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

PubMed Central

Chang, Sheng-Ren; Chen, Hsin

2009-01-01

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times. PMID:22408508

Low Noise Amplifiers for 140 Ghz Wide-Band Cryogenic Receivers

NASA Technical Reports Server (NTRS)

Larkoski, Patricia V.; Kangaslahti, Pekka; Samoska, Lorene; Lai, Richard; Sarkozy, Stephen

2013-01-01

We report S-parameter and noise measurements for three different Indium Phosphide 35-nanometer-gate-length High Electron Mobility Transistor (HEMT) Low Noise Amplifier (LNA) designs operating in the frequency range centered on 140 gigahertz. When packaged in a Waveguide Rectangular-6.1 waveguide housing, the LNAs have an average measured noise figure of 3.0 decibels - 3.6 decibels over the 122-170 gigahertz band. One LNA was cooled to 20 degrees Kelvin and a record low noise temperature of 46 Kelvin, or 0.64 decibels noise figure, was measured at 152 gigahertz. These amplifiers can be used to develop receivers for instruments that operate in the 130-170 gigahertz atmospheric window, which is an important frequency band for ground-based astronomy and millimeter-wave imaging applications.

Note: A temperature-stable low-noise transimpedance amplifier for microcurrent measurement.

PubMed

Xie, Kai; Shi, Xueyou; Zhao, Kai; Guo, Lixin; Zhang, Hanlu

2017-02-01

Temperature stability and noise characteristics often run contradictory in microcurrent (e.g., pA-scale) measurement instruments because low-noise performance requires high-value resistors with relatively poor temperature coefficients. A low-noise transimpedance amplifier with high-temperature stability, which involves an active compensation mechanism to overcome the temperature drift mainly caused by high-value resistors, is presented. The implementation uses a specially designed R-2R compensating network to provide programmable current gain with extra-fine trimming resolution. The temperature drifts of all components (e.g., feedback resistors, operational amplifiers, and the R-2R network itself) are compensated simultaneously. Therefore, both low-temperature drift and ultra-low-noise performance can be achieved. With a current gain of 10 11 V/A, the internal current noise density was about 0.4 fA/√Hz, and the average temperature coefficient was 4.3 ppm/K at 0-50 °C. The amplifier module maintains accuracy across a wide temperature range without additional thermal stabilization, and its compact size makes it especially suitable for high-precision, low-current measurement in outdoor environments for applications such as electrochemical emission supervision, air pollution particles analysis, radiation monitoring, and bioelectricity.

Note: A temperature-stable low-noise transimpedance amplifier for microcurrent measurement

NASA Astrophysics Data System (ADS)

Xie, Kai; Shi, Xueyou; Zhao, Kai; Guo, Lixin; Zhang, Hanlu

2017-02-01

Temperature stability and noise characteristics often run contradictory in microcurrent (e.g., pA-scale) measurement instruments because low-noise performance requires high-value resistors with relatively poor temperature coefficients. A low-noise transimpedance amplifier with high-temperature stability, which involves an active compensation mechanism to overcome the temperature drift mainly caused by high-value resistors, is presented. The implementation uses a specially designed R-2R compensating network to provide programmable current gain with extra-fine trimming resolution. The temperature drifts of all components (e.g., feedback resistors, operational amplifiers, and the R-2R network itself) are compensated simultaneously. Therefore, both low-temperature drift and ultra-low-noise performance can be achieved. With a current gain of 1011 V/A, the internal current noise density was about 0.4 fA/√Hz, and the average temperature coefficient was 4.3 ppm/K at 0-50 °C. The amplifier module maintains accuracy across a wide temperature range without additional thermal stabilization, and its compact size makes it especially suitable for high-precision, low-current measurement in outdoor environments for applications such as electrochemical emission supervision, air pollution particles analysis, radiation monitoring, and bioelectricity.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Problems of the design of low-noise input devices. [parametric amplifiers

NASA Technical Reports Server (NTRS)

Manokhin, V. M.; Nemlikher, Y. A.; Strukov, I. A.; Sharfov, Y. A.

1974-01-01

An analysis is given of the requirements placed on the elements of parametric centimeter waveband amplifiers for achievement of minimal noise temperatures. A low-noise semiconductor parametric amplifier using germanium parametric diodes for a receiver operating in the 4 GHz band was developed and tested confirming the possibility of satisfying all requirements.

A compact nanopower low output impedance CMOS operational amplifier for wireless intraocular pressure recordings.

PubMed

Dresher, Russell P; Irazoqui, Pedro P

2007-01-01

Wireless sensing has shown potential benefits for the continuous-time measurement of physiological data. One such application is the recording of intraocular pressure (IOP) for patients with glaucoma. Ultra-low-power circuits facilitate the use of inductively-coupled power for implantable wireless systems. Compact circuit size is also desirable for implantable systems. As a first step towards the realization of such circuits, we have designed a compact, ultra-low-power operational amplifier which can be used to record IOP. This paper presents the measured results of a CMOS operational amplifier that can be incorporated with a wireless IOP monitoring system or other low-power application. It has a power consumption of 736 nW, chip area of 0.023 mm2, and output impedance of 69 Omega to drive low-impedance loads.

S-band low noise amplifier and 40 kW high power amplifier subsystems of Japanese Deep Space Earth Station

NASA Astrophysics Data System (ADS)

Honma, K.; Handa, K.; Akinaga, W.; Doi, M.; Matsuzaki, O.

This paper describes the design and the performance of the S-band low noise amplifier and the S-band high power amplifier that have been developed for the Usuda Deep Space Station of the Institute of Space and Astronautical Science (ISAS), Japan. The S-band low noise amplifier consists of a helium gas-cooled parametric amplifier followed by three-stage FET amplifiers and has a noise temperature of 8 K. The high power amplifier is composed of two 28 kW klystrons, capable of transmitting 40 kW continuously when two klystrons are combined. Both subsystems are operating quite satisfactorily in the tracking of Sakigake and Suisei, the Japanese interplanetary probes for Halley's comet exploration, launched by ISAS in 1985.

Ultrasensitive low noise voltage amplifier for spectral analysis.

PubMed

Giusi, G; Crupi, F; Pace, C

2008-08-01

Recently we have proposed several voltage noise measurement methods that allow, at least in principle, the complete elimination of the noise introduced by the measurement amplifier. The most severe drawback of these methods is that they require a multistep measurement procedure. Since environmental conditions may change in the different measurement steps, the final result could be affected by these changes. This problem is solved by the one-step voltage noise measurement methodology based on a novel amplifier topology proposed in this paper. Circuit implementations for the amplifier building blocks based on operational amplifiers are critically discussed. The proposed approach is validated through measurements performed on a prototype circuit.

Cross-talk free, low-noise optical amplifier

DOEpatents

Dijaili, Sol P.; Patterson, Frank G.; Deri, Robert J.

1995-01-01

A low-noise optical amplifier solves crosstalk problems in optical amplifiers by using an optical cavity oriented off-axis (e.g. perpendicular) to the direction of a signal amplified by the gain medium of the optical amplifier. Several devices are used to suppress parasitic lasing of these types of structures. The parasitic lasing causes the gain of these structures to be practically unusable. The lasing cavity is operated above threshold and the gain of the laser is clamped to overcome the losses of the cavity. Any increase in pumping causes the lasing power to increase. The clamping action of the gain greatly reduces crosstalk due to gain saturation for the amplified signal beam. It also reduces other nonlinearities associated with the gain medium such as four-wave mixing induced crosstalk. This clamping action can occur for a bandwidth defined by the speed of the laser cavity. The lasing field also reduces the response time of the gain medium. By having the lasing field off-axis, no special coatings are needed. Other advantages are that the lasing field is easily separated from the amplified signal and the carrier grating fluctuations induced by four-wave mixing are decreased. Two related methods reduce the amplified spontaneous emission power without sacrificing the gain of the optical amplifier.

Cross-talk free, low-noise optical amplifier

DOEpatents

Dijaili, S.P.; Patterson, F.G.; Deri, R.J.

1995-07-25

A low-noise optical amplifier solves crosstalk problems in optical amplifiers by using an optical cavity oriented off-axis (e.g. perpendicular) to the direction of a signal amplified by the gain medium of the optical amplifier. Several devices are used to suppress parasitic lasing of these types of structures. The parasitic lasing causes the gain of these structures to be practically unusable. The lasing cavity is operated above threshold and the gain of the laser is clamped to overcome the losses of the cavity. Any increase in pumping causes the lasing power to increase. The clamping action of the gain greatly reduces crosstalk due to gain saturation for the amplified signal beam. It also reduces other nonlinearities associated with the gain medium such as four-wave mixing induced crosstalk. This clamping action can occur for a bandwidth defined by the speed of the laser cavity. The lasing field also reduces the response time of the gain medium. By having the lasing field off-axis, no special coatings are needed. Other advantages are that the lasing field is easily separated from the amplified signal and the carrier grating fluctuations induced by four-wave mixing are decreased. Two related methods reduce the amplified spontaneous emission power without sacrificing the gain of the optical amplifier. 11 figs.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

PubMed Central

Kawahito, Shoji; Seo, Min-Woong

2016-01-01

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e−rms) when compared with the CMS gain of two (2.4 e−rms), or 16 (1.1 e−rms). PMID:27827972

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

PubMed

Kawahito, Shoji; Seo, Min-Woong

2016-11-06

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e - rms ) when compared with the CMS gain of two (2.4 e - rms ), or 16 (1.1 e - rms ).

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE PAGES

An, Mangmang; Chen, Chufeng; Gao, Chaosong; ...

2015-12-12

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Mangmang; Chen, Chufeng; Gao, Chaosong

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

NASA Astrophysics Data System (ADS)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

Tests of Low-Noise MMIC Amplifier Module at 290 to 340 GHz

NASA Technical Reports Server (NTRS)

Gaier, Todd; Samoska, Lorene; Fung, King Man; Deal, William; Mei, Xiaobing; Lai, Richard

2009-01-01

A document presents data from tests of a low-noise amplifier module operating in the frequency range from 290 to 340 GHz said to be the highest-frequency low-noise, solid-state amplifier ever developed. The module comprised a three-stage monolithic microwave integrated circuit (MMIC) amplifier integrated with radial probe MMIC/waveguide transitions and contained in a compact waveguide package, all according to the concepts described in the immediately preceding article and in the referenced prior article, "Integrated Radial Probe Transition From MMIC to Waveguide" (NPO-43957), NASA Tech Briefs Vol. 31, No. 5 (May 2007), page 38. The tests included measurements by the Y-factor method, in which noise figures are measured repeatedly with an input noise source alternating between an "on" (hot-load) condition and an "off" (cold-load) condition. (The Y factor is defined as the ratio between the "on" and "off" noise power levels.) The test results showed that, among other things, the module exhibited a minimum noise figure of about 8.7 dB at 325 GHz and that the gain at that frequency under the bias conditions that produced the minimum noise figure was between about 9 and 10 dB.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Ultra-Low-Power Cryogenic SiGe Low-Noise Amplifiers: Theory and Demonstration

NASA Astrophysics Data System (ADS)

Montazeri, Shirin; Wong, Wei-Ting; Coskun, Ahmet H.; Bardin, Joseph C.

2016-01-01

Low-power cryogenic low-noise amplifiers (LNAs) are desired to ease the cooling requirements of ultra-sensitive cryogenically cooled instrumentation. In this paper, the tradeoff between power and noise performance in silicon-germanium LNAs is explored to study the possibility of operating these devices from low supply voltages. A new small-signal heterojunction bipolar transistor noise model applicable to both the forward-active and saturation regimes is developed from first principles. Experimental measurements of a device across a wide range of temperatures are then presented and the dependence of the noise parameters on collector-emitter voltage is described. This paper concludes with the demonstration of a high-gain 1.8-3.6-GHz cryogenic LNA achieving a noise temperature of 3.4-5 K while consuming just 290 μW when operating at 15-K physical temperature.

Low-noise current amplifier based on mesoscopic Josephson junction.

PubMed

Delahaye, J; Hassel, J; Lindell, R; Sillanpää, M; Paalanen, M; Seppä, H; Hakonen, P

2003-02-14

We used the band structure of a mesoscopic Josephson junction to construct low-noise amplifiers. By taking advantage of the quantum dynamics of a Josephson junction, i.e., the interplay of interlevel transitions and the Coulomb blockade of Cooper pairs, we created transistor-like devices, Bloch oscillating transistors, with considerable current gain and high-input impedance. In these transistors, the correlated supercurrent of Cooper pairs is controlled by a small base current made up of single electrons. Our devices reached current and power gains on the order of 30 and 5, respectively. The noise temperature was estimated to be around 1 kelvin, but noise temperatures of less than 0.1 kelvin can be realistically achieved. These devices provide quantum-electronic building blocks that will be useful at low temperatures in low-noise circuit applications with an intermediate impedance level.

A 256×256 low-light-level CMOS imaging sensor with digital CDS

NASA Astrophysics Data System (ADS)

Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

2016-10-01

In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

PubMed

Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

2016-04-13

A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2017-04-01

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

High-quality recording of bioelectric events. Part 2. Low-noise, low-power multichannel amplifier design.

PubMed

Metting van Rijn, A C; Peper, A; Grimbergen, C A

1991-07-01

A multichannel instrumentation amplifier, developed to be used in a miniature universal eight-channel amplifier module, is described. After discussing the specific properties of a bioelectric recording, the difficulties of meeting the demanded specifications with a design based on operational amplifiers are reviewed. Because it proved impossible to achieve the demanded combination of low noise and low power consumption using commercially available operational amplifiers, an amplifier equipped with an input stage with discrete transistors was developed. A new design concept was used to expand the design to a multichannel version with an equivalent input noise voltage of 0.35 microV RMS in a bandwidth of 0.1-100 Hz and a power consumption of 0.6 mW per channel. The results of this study are applied to miniature, universal, eight-channel amplifier modules, manufactured with thick-film production techniques. The modules can be coupled to satisfy the demand for a multiple of eight channels. The low power consumption enables the modules to be used in all kinds of portable and telemetry measurement systems and simplifies the power supply in stationary measurement systems.

Note: cryogenic low-noise dc-coupled wideband differential amplifier based on SiGe heterojunction bipolar transistors.

PubMed

Beev, Nikolai; Kiviranta, Mikko

2012-06-01

Silicon-germanium heterojunction bipolar transistors can be used to construct low-noise cryogenic amplifiers. We present a dc-coupled differential amplifier capable of operating down to 10 K. In this temperature regime it has bandwidth of 15 MHz and noise temperature as low as 1.3 K. When operated at liquid nitrogen temperature of 77 K, the measured noise temperature is lower than 3 K. The amplifier is based on the commercially available transistors NESG3031 and operational amplifier OPA836 and is capable of standalone operation without any additional stages at room temperature.

W-band InP based HEMT MMIC low noise amplifiers

NASA Technical Reports Server (NTRS)

Lin, K. Y.; Tang, Y. L.; Wang, H.; Gaier, T.; Gough, R. G.; Sinclair, M.

2002-01-01

This paper presents the designs and measurement results of a three-stage and a four-stage W-band monolithic microwave integrated circuits (MMIC) including a three-stage and a four-stage low noise amplifiers.

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor.

PubMed

Song, Shuang; Rooijakkers, Michael; Harpe, Pieter; Rabotti, Chiara; Mischi, Massimo; van Roermund, Arthur H M; Cantatore, Eugenio

2015-04-01

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

Low-Noise MMIC Amplifiers for 120 to 180 GHz

NASA Technical Reports Server (NTRS)

Pukala, David; Samoska, Lorene; Peralta, Alejandro; Bayuk, Brian; Grundbacher, Ron; Oliver, Patricia; Cavus, Abdullah; Liu, Po-Hsin

2009-01-01

Three-stage monolithic millimeter-wave integrated-circuit (MMIC) amplifiers capable of providing useful amounts of gain over the frequency range from 120 to 180 GHz have been developed as prototype low-noise amplifiers (LNAs) to be incorporated into instruments for sensing cosmic microwave background radiation. There are also potential uses for such LNAs in electronic test equipment, passive millimeter- wave imaging systems, radar receivers, communication receivers, and systems for detecting hidden weapons. The main advantage afforded by these MMIC LNAs, relative to prior MMIC LNAs, is that their coverage of the 120-to-180-GHz frequency band makes them suitable for reuse in a wider variety of applications without need to redesign them. Each of these MMIC amplifiers includes InP transistors and coplanar waveguide circuitry on a 50- mthick chip (see Figure 1). Coplanar waveguide transmission lines are used for both applying DC bias and matching of input and output impedances of each transistor stage. Via holes are incorporated between top and bottom ground planes to suppress propagation of electromagnetic modes in the substrate. On the basis of computational simulations, each of these amplifiers was expected to operate with a small-signal gain of 14 dB and a noise figure of 4.3 dB. At the time of writing this article, measurements of noise figures had not been reported, but on-chip measurements had shown gains approaching their simulated values (see Figure 2).

A Cryogenic SiGe Low-noise Amplifier Optimized for Phased-array Feeds

NASA Astrophysics Data System (ADS)

Groves, Wavley M., III; Morgan, Matthew A.

2017-08-01

The growing number of phased-array feeds (PAF) being built for radio astronomy demonstrates an increasing need for low-noise amplifiers (LNA), which are designed for repeatability, low noise, and ease of manufacture. Specific design features that help to achieve these goals include the use of unpackaged transistors (for cryogenic operation); single-polarity biasing; straight plug-in radio frequency (RF) interfaces to facilitate installation and re-work; and the use of off-the-shelf components. The focal L-band array for the Green Bank Telescope (FLAG) is a cooperative effort by Brigham Young University and the National Radio Astronomy Observatory using warm dipole antennae and cryogenic Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) LNAs. These LNAs have an in band gain average of 38 dB and 4.85 Kelvin average noise temperature. Although the FLAG instrument was the driving instrument behind this development, most of the key features of the design and the advantages they offer apply broadly to other array feeds, including independent-beam and phased, and for many antenna types such as horn, dipole, Vivaldi, connected-bowtie, etc. This paper focuses on the unique requirements array feeds have for low-noise amplifiers and how amplifier manufacturing can accommodate these needs.

160-190 GHz Monolithic Low Noise Amplifiers

NASA Technical Reports Server (NTRS)

Kok, Y. L.; Wang, H.; Huang, T. W.; Lai, R.; Chen, Y. C.; Sholley, M.; Block, T.; Streit, D. C.; Liu, P. H.; Allen, B. R.;

Two-Stage, 90-GHz, Low-Noise Amplifier

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Gaier, Todd C.; Xenos, Stephanie; Soria, Mary M.; Kangaslahti, Pekka P.; Cleary, Kieran A.; Ferreira, Linda; Lai, Richard; Mei, Xiaobing

2010-01-01

A device has been developed for coherent detection of the polarization of the cosmic microwave background (CMB). A two-stage amplifier has been designed that covers 75-110 GHz. The device uses the emerging 35-nm InP HEMT technology recently developed at Northrop Grumman Corporation primarily for use at higher frequencies. The amplifier has more than 18 dB gain and less than 35 K noise figure across the band. These devices have noise less than 30 K at 100 GHz. The development started with design activities at JPL, as well as characterization of multichip modules using existing InP. Following processing, a test campaign was carried out using single-chip modules at 100 GHz. Successful development of the chips will lead to development of multichip modules, with simultaneous Q and U Stokes parameter detection. This MMIC (monolithic microwave integrated circuit) amplifier takes advantage of performance improvements intended for higher frequencies, but in this innovation are applied at 90 GHz. The large amount of available gain ultimately leads to lower possible noise performance at 90 GHz.

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

PubMed Central

Mollazadeh, Mohsen; Murari, Kartikeya; Cauwenberghs, Gert; Thakor, Nitish

2009-01-01

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental ΔΣ analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 μVrms while drawing 12.2 μA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 μW power. Time-modulation feedback in the ADC offers programmable digital gain (1–4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject. PMID:20046962

Cryogenic, low-noise high electron mobility transistor amplifiers for the Deep Space Network

NASA Technical Reports Server (NTRS)

Bautista, J. J.

1993-01-01

The rapid advances recently achieved by cryogenically cooled high electron mobility transistor (HEMT) low-noise amplifiers (LNA's) in the 1- to 10-GHz range are making them extremely competitive with maser amplifiers. In order to address future spacecraft navigation, telemetry, radar, and radio science needs, the Deep Space Network is investing both maser and HEMT amplifiers for its Ka-band (32-GHz) downlink capability. This article describes the current state cryogenic HEMT LNA development at Ka-band for the DSN. Noise performance results at S-band (2.3 GHz) and X-band (8.5 GHz) for HEMT's and masers are included for completeness.

A microwave cryogenic low-noise amplifier based on sige heterostructures

NASA Astrophysics Data System (ADS)

Ivanov, B. I.; Grajcar, M.; Novikov, I. L.; Vostretsov, A. G.; Il'ichev, E.

2016-04-01

A low-noise cryogenic amplifier for the measurement of weak microwave signals at sub-Kelvin temperatures is constructed. The amplifier has five stages based on SiGe bipolar heterostructure transistors and has a gain factor of 35 dB in the frequency band from 100 MHz to 4 GHz at an operating temperature of 800 mK. The parameters of a superconducting quantum bit measured with this amplifier in the ultralow-power mode are presented as an application example. The amplitude-frequency response of the "supercon-ducting qubit-coplanar cavity" structure is demonstrated. The ground state of the qubit is characterized in the quasi-dispersive measurement mode.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

PubMed

Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

2013-01-01

One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

PubMed

Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

2015-01-01

In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

PubMed Central

Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

2017-01-01

A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µVrms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter. PMID:28394289

A fully integrated neural recording amplifier with DC input stabilization.

PubMed

Mohseni, Pedram; Najafi, Khalil

2004-05-01

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

Radio astronomy ultra-low-noise amplifier for operation at 91 cm wavelength in high RFI environment

NASA Astrophysics Data System (ADS)

Korolev, A. M.; Zakharenko, V. V.; Ulyanov, O. M.

2016-02-01

An ultra-low-noise input amplifier intended for a use in a radio telescope operating at 91 cm wavelength is presented. The amplifier noise temperatures are 12.8 ± 1.5 and 10.0 ± 1.5 K at ambient temperatures of 293 and 263 K respectively. The amplifier does not require cryogenic cooling. It can be quickly put in operation thus shortening losses in the telescope observation time. High linearity of the amplifier (output power at 1 dB gain compression P1dB ≥ 22 dBm, output third order intercept point OIP3 ≥ 37 dBm) enables the telescope operation in highly urbanized and industrialized regions. To obtain low noise characteristics along with high linearity, high-electron-mobility field-effect transistors were used in parallel in the circuit developed. The transistors used in the amplifier are cost-effective and commercially available. The circuit solution is recommended for similar devices working in ultra-high frequency band.

A low-power CMOS trans-impedance amplifier for FM/cw ladar imaging system

NASA Astrophysics Data System (ADS)

Hu, Kai; Zhao, Yi-qiang; Sheng, Yun; Zhao, Hong-liang; Yu, Hai-xia

2013-09-01

A scannerless ladar imaging system based on a unique frequency modulation/continuous wave (FM/cw) technique is able to entirely capture the target environment, using a focal plane array to construct a 3D picture of the target. This paper presents a low power trans-impedance amplifier (TIA) designed and implemented by 0.18 μm CMOS technology, which is used in the FM/cw imaging ladar with a 64×64 metal-semiconductor-metal(MSM) self-mixing detector array. The input stage of the operational amplifier (op amp) in TIA is realized with folded cascade structure to achieve large open loop gain and low offset. The simulation and test results of TIA with MSM detectors indicate that the single-end trans-impedance gain is beyond 100 kΩ, and the -3 dB bandwidth of Op Amp is beyond 60 MHz. The input common mode voltage ranges from 0.2 V to 1.5 V, and the power dissipation is reduced to 1.8 mW with a supply voltage of 3.3 V. The performance test results show that the TIA is a candidate for preamplifier of the read-out integrated circuit (ROIC) in the FM/cw scannerless ladar imaging system.

Low Voltage Current-Reused Pseudo-Differential Programmable Gain Amplifier

NASA Astrophysics Data System (ADS)

Nguyen, Huy-Hieu; Lee, Jeong-Seon; Lee, Sang-Gug

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3dB with gain error of less than ±0.38dB. The IIP3, P1dB, and smallest 3-dB bandwidth are 10.5 to 27dBm, -9 to 9.5dBm, and 250MHz, respectively. The PGA occupies the chip area of 0.04mm2 and consumes only 460 µA from a 1.2V supply.

Noise and noise figure of vertical-cavity semiconductor optical amplifiers (VCSOAs) operated in reflection mode

NASA Astrophysics Data System (ADS)

Wen, Pengyue; Sanchez, Michael; Gross, Matthias; Esener, Sadik C.

2003-05-01

In this paper, the noise properties of vertical cavity semiconductor optical amplifiers (VCSOAs) operated in reflection mode are studied. Expressions for noise sources contributing to the total noise detected at amplifier output are derived, based on the photon statistics master equations. The noise figure, defined as the degradation of signal-to-noise ratio (SNR), is analyzed using the assumption that spontaneous emission-signal beat noise dominates. The analysis shows that the noise figure of reflection mode VCSOAs has the same values as that in transmission mode as long as amplifier gain is high (G>>1). Furthermore, simulations depict the dependence of noise figure on device parameters and bias conditions, as well as reveal the importance of the low reflectivity front mirror and the high reflectivity rear mirror for low noise operation. In addition, the noise figure analysis results are compared with experimental measurements, in which amplified spontaneous emission (ASE) power is measured by an optical spectrum analyzer and the noise figure is obtained from the ASE power and the amplifier gain. The measured data are in good agreement with the theoretical predictions.

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

NASA Astrophysics Data System (ADS)

Edward, Alexander; Chan, Pak Kwong

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

A high efficiency PWM CMOS class-D audio power amplifier

NASA Astrophysics Data System (ADS)

Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

2009-02-01

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

High-gain cryogenic amplifier assembly employing a commercial CMOS operational amplifier.

PubMed

Proctor, J E; Smith, A W; Jung, T M; Woods, S I

2015-07-01

We have developed a cryogenic amplifier for the measurement of small current signals (10 fA-100 nA) from cryogenic optical detectors. Typically operated with gain near 10(7) V/A, the amplifier performs well from DC to greater than 30 kHz and exhibits noise level near the Johnson limit. Care has been taken in the design and materials to control heat flow and temperatures throughout the entire detector-amplifier assembly. A simple one-board version of the amplifier assembly dissipates 8 mW to our detector cryostat cold stage, and a two-board version can dissipate as little as 17 μW to the detector cold stage. With current noise baseline of about 10 fA/(Hz)(1/2), the cryogenic amplifier is generally useful for cooled infrared detectors, and using blocked impurity band detectors operated at 10 K, the amplifier enables noise power levels of 2.5 fW/(Hz)(1/2) for detection of optical wavelengths near 10 μm.

Low phase noise oscillator using two parallel connected amplifiers

NASA Technical Reports Server (NTRS)

Kleinberg, Leonard L.

1987-01-01

A high frequency oscillator is provided by connecting two amplifier circuits in parallel where each amplifier circuit provides the other amplifier circuit with the conditions necessary for oscillation. The inherent noise present in both amplifier circuits causes the quiescent current, and in turn, the generated frequency, to change. The changes in quiescent current cause the transconductance and the load impedance of each amplifier circuit to vary, and this in turn results in opposing changes in the input susceptance of each amplifier circuit. Because the changes in input susceptance oppose each other, the changes in quiescent current also oppose each other. The net result is that frequency stability is enhanced.

Concentric Parallel Combining Balun for Millimeter-Wave Power Amplifier in Low-Power CMOS with High-Power Density

NASA Astrophysics Data System (ADS)

Han, Jiang-An; Kong, Zhi-Hui; Ma, Kaixue; Yeo, Kiat Seng; Lim, Wei Meng

2016-11-01

This paper presents a novel balun for a millimeter-wave power amplifier (PA) design to achieve high-power density in a 65-nm low-power (LP) CMOS process. By using a concentric winding technique, the proposed parallel combining balun with compact size accomplishes power combining and unbalance-balance conversion concurrently. For calculating its power combination efficiency in the condition of various amplitude and phase wave components, a method basing on S-parameters is derived. Based on the proposed parallel combining balun, a fabricated 60-GHz industrial, scientific, and medical (ISM) band PA with single-ended I/O achieves an 18.9-dB gain and an 8.8-dBm output power at 1-dB compression and 14.3-dBm saturated output power ( P sat) at 62 GHz. This PA occupying only a 0.10-mm2 core area has demonstrated a high-power density of 269.15 mW/mm2 in 65 nm LP CMOS.

Phase noise in RF and microwave amplifiers.

PubMed

Boudot, Rodolphe; Rubiola, Enrico

2012-12-01

Understanding amplifier phase noise is a critical issue in many fields of engineering and physics, such as oscillators, frequency synthesis, telecommunication, radar, and spectroscopy; in the emerging domain of microwave photonics; and in exotic fields, such as radio astronomy, particle accelerators, etc. Focusing on the two main types of base noise in amplifiers, white and flicker, the power spectral density of the random phase φ(t) is Sφ(f) = b(0) + b(-1)/f. White phase noise results from adding white noise to the RF spectrum in the carrier region. For a given RF noise level, b(0) is proportional to the reciprocal of the carrier power P(0). By contrast, flicker results from a near-dc 1/f noise-present in all electronic devices-which modulates the carrier through some parametric effect in the semiconductor. Thus, b(-1) is a parameter of the amplifier, constant in a wide range of P(0). The consequences are the following: Connecting m equal amplifiers in parallel, b(-1) is 1/m times that of one device. Cascading m equal amplifiers, b(-1) is m times that of one amplifier. Recirculating the signal in an amplifier so that the gain increases by a power of m (a factor of m in decibels) as a result of positive feedback (regeneration), we find that b(-1) is m(2) times that of the amplifier alone. The feedforward amplifier exhibits extremely low b(-1) because the carrier is ideally nulled at the input of its internal error amplifier. Starting with an extensive review of the literature, this article introduces a system-oriented model which describes the phase flickering. Several amplifier architectures (cascaded, parallel, etc.) are analyzed systematically, deriving the phase noise from the general model. There follow numerous measurements of amplifiers using different technologies, including some old samples, and in a wide frequency range (HF to microwaves), which validate the theory. In turn, theory and results provide design guidelines and give suggestions for CAD and

Low-noise kinetic inductance traveling-wave amplifier using three-wave mixing

NASA Astrophysics Data System (ADS)

Vissers, M. R.; Erickson, R. P.; Ku, H.-S.; Vale, Leila; Wu, Xian; Hilton, G. C.; Pappas, D. P.

2016-01-01

We have fabricated a wide-bandwidth, high dynamic range, low-noise cryogenic amplifier based on a superconducting kinetic inductance traveling-wave device. The device was made from NbTiN and consisted of a long, coplanar waveguide on a silicon chip. By adding a DC current and an RF pump tone, we are able to generate parametric amplification using three-wave mixing (3WM). The devices exhibit gain of more than 15 dB across an instantaneous bandwidth from 4 to 8 GHz. The total usable gain bandwidth, including both sides of the signal-idler gain region, is more than 6 GHz. The noise referred to the input of the devices approaches the quantum limit, with less than 1 photon excess noise. We compare these results directly to the four-wave mixing amplification mode, i.e., without DC-biasing. We find that the 3WM mode allows operation with the pump at lower RF power and at frequencies far from the signal. We have used this knowledge to redesign the amplifiers to utilize primarily 3WM amplification, thereby allowing for direct integration into large scale qubit and detector applications.

Low-noise kinetic inductance traveling-wave amplifier using three-wave mixing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vissers, M. R.; Erickson, R. P.; Ku, H.-S.

We have fabricated a wide-bandwidth, high dynamic range, low-noise cryogenic amplifier based on a superconducting kinetic inductance traveling-wave device. The device was made from NbTiN and consisted of a long, coplanar waveguide on a silicon chip. By adding a DC current and an RF pump tone, we are able to generate parametric amplification using three-wave mixing (3WM). The devices exhibit gain of more than 15 dB across an instantaneous bandwidth from 4 to 8 GHz. The total usable gain bandwidth, including both sides of the signal-idler gain region, is more than 6 GHz. The noise referred to the input of the devices approachesmore » the quantum limit, with less than 1 photon excess noise. We compare these results directly to the four-wave mixing amplification mode, i.e., without DC-biasing. We find that the 3WM mode allows operation with the pump at lower RF power and at frequencies far from the signal. We have used this knowledge to redesign the amplifiers to utilize primarily 3WM amplification, thereby allowing for direct integration into large scale qubit and detector applications.« less

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers

PubMed Central

Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

2016-01-01

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/Hz at 50 kHz, which corresponds to 100 μg/Hz. PMID:28042830

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

PubMed

Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

2016-12-30

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ Hz at 50 kHz, which corresponds to 100 μg/ Hz .

Design of Low-Noise Output Amplifiers for P-channel Charge-Coupled Devices Fabricated on High-Resistivity Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haque, S; Frost, F Dion R.; Groulx, R

2011-12-22

We describe the design and optimization of low-noise, single-stage output amplifiers for p-channel charge-coupled devices (CCDs) used for scientific applications in astronomy and other fields. The CCDs are fabricated on high-resistivity, 4000–5000 -cm, n-type silicon substrates. Single-stage amplifiers with different output structure designs and technologies have been characterized. The standard output amplifier is designed with an n{sup +} polysilicon gate that has a metal connection to the sense node. In an effort to lower the output amplifier readout noise by minimizing the capacitance seen at the sense node, buried-contact technology has been investigated. In this case, the output transistor hasmore » a p{sup +} polysilicon gate that connects directly to the p{sup +} sense node. Output structures with buried-contact areas as small as 2 μm × 2 μm are characterized. In addition, the geometry of the source-follower transistor was varied, and we report test results on the conversion gain and noise of the various amplifier structures. By use of buried-contact technology, better amplifier geometry, optimization of the amplifier biases and improvements in the test electronics design, we obtain a 45% reduction in noise, corresponding to 1.7 e{sup -} rms at 70 kpixels/sec.« less

Reset noise suppression in two-dimensional CMOS photodiode pixels through column-based feedback-reset

NASA Technical Reports Server (NTRS)

Pain, B.; Cunningham, T. J.; Hancock, B.; Yang, G.; Seshadri, S.; Ortiz, M.

2002-01-01

We present new CMOS photodiode imager pixel with ultra-low read noise through on-chip suppression of reset noise via column-based feedback circuitry. The noise reduction is achieved without introducing any image lag, and with insignificant reduction in quantum efficiency and full well.

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

NASA Astrophysics Data System (ADS)

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

NASA Astrophysics Data System (ADS)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

Transimpedance Amplifier for MEMS SAW Oscillator in 1.4GHz

NASA Astrophysics Data System (ADS)

Kamarudin, N.; Karim, J.; Hussin, H.

2018-03-01

This work is to design a transimpedance amplifier for MEMS SAW resonator to achieve low power consumption at desired frequency. A transimpedance amplifier is designed and characterized for MEMS SAW resonator in 0.18μm CMOS process. The transimpedance amplifier achieves gain is 31 dBΩ at 176°. The power consume by oscillator is 0.6mW at VDD 1.8V while phase noise at -133.97dBc/Hz at 10kHz.

Low noise tuned amplifier

NASA Technical Reports Server (NTRS)

Kleinberg, L. L. (Inventor)

1984-01-01

A bandpass amplifier employing a field effect transistor amplifier first stage is described with a resistive load either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load of the field effect transistor.

Small Pixel Hybrid CMOS X-ray Detectors

NASA Astrophysics Data System (ADS)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

Novel matched amplifiers with low noise positive feedback. Part II: Resistive-capacitive feedback

NASA Astrophysics Data System (ADS)

Bruck, Y.; Zakharenko, V.

2010-02-01

This article is a continuation of consideration for an amplifier with resistive positive feedback (RPF) (Bruck (2008), 'Novel Matched LNA with Low Noise Positive Feedback. Part 1: General Features and Resistive Feedback', International Journal of Electronics, 95, 441-456). We propose here new configuration schematics of a transformer-less selective LNA with resistive-capacitive positive feedback (RCPF). A circuit of an amplifier with a transistor connected into a circuit with a common base (CB) configuration is analysed in detail. RCPF and RPF circuits are compared. It is shown that the LNA RCPF provides any pass-band, a good level of input and output matching, a minimum noise temperature which is significantly lower than that of the LNA RPF, a rather high linearity, and stability of amplification. The simulation results and some experimental data for the amplifiers intended for use in the LOFAR radiotelescope (Konovalenko et al. (2003), 'Thirty Element Array Antenna as a Prototype of a Huge Low-Frequency Radio Telescope,' Experimental Astronomy, 16, 149-164; Konovalenko (2007), 'Ukrainian Contribution to LOFAR', A scientific workshop, organised by LOFAR/ASTRON' Emmen, Netherlands, 23-27. http://www.lofar.org/workshop) are given. It is assumed that such devices are of a special interest for high-frequency integral circuits (IC).

New low-level a-c amplifier provides adjustable noise cancellation and automatic temperature compensation

NASA Technical Reports Server (NTRS)

Smith, J. R., Jr.

1964-01-01

Circuit utilizing a transistorized differential amplifier is developed for biomedical use. This low voltage operating circuit provides adjustable cancellation at the input for unbalanced noise signals, and automatic temperature compensation is accomplished by a single active element across the input-output ends.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

Development of a cryogenic DC-low noise amplifier for SQuID-based readout electronics

NASA Astrophysics Data System (ADS)

Macculi, C.; Torrioli, G.; Di Giorgio, A.; Spinoglio, L.; Piro, Luigi

2014-07-01

We present the preliminary results of the design and test activities for a DC cryogenic low noise amplifier for the SAFARI imaging spectrometer, planned to be onboard the SPICA mission, necessary not only to drive, as usual, the voltage signal produced by the SQuID but also to boost such signals over about 7 meter of path towards the warm feedback electronics. This development has been done in the framework of the mission preparation studies, within the European Consortium for the development of the SAFARI instrument. The actual configuration of the SAFARI focal plane assembly (FPA), indeed, foresees a long distance to the warm back end electronics. It is therefore mandatory to boost the faint electric signal coming from the SQuID device by keeping under control both power dissipation and noise: this is the main role of the designed Cryogenic Low Noise Amplifier (LNA). Working at 136K, it has a differential input gain-stage, and a differential balanced voltage buffer output stage, running at few mW target overall power. At present the design is based on the use of Heterojunction Si:Ge transistors, the required bandwidth is DC-4MHz and the required noise lower than 1 nV/rtHz.

Low-noise cryogenic transmission line

NASA Technical Reports Server (NTRS)

Norris, D.

1987-01-01

New low-noise cryogenic input transmission lines have been developed for the Deep Space Network (DSN) at 1.668 GHz for cryogenically cooled Field Effect Transistors (FET) and High Electron Mobility Transistor (HEMT) amplifiers. These amplifiers exhibit very low noise temperatures of 5 K to 15 K, making the requirements for a low-noise input transmission line critical. Noise contribution to the total amplifier system from the low-noise line is less than 0.5 K for both the 1.668-GHz and 2.25-GHz FET systems. The 1.668-GHz input line was installed in six FET systems which were implemented in the DSN for the Venus Balloon Experiment. The 2.25-GHz input line has been implemented in three FET systems for the DSN 34-m HEF antennas, and the design is currently being considered for use at higher frequencies.

Low-power G m-C filter employing current-reuse differential difference amplifiers

DOE PAGES

Mincey, John S.; Briseno-Vidrios, Carlos; Silva-Martinez, Jose; ...

2016-08-10

This study deals with the design of low-power, high performance, continuous-time filters. The proposed OTA architecture employs current-reuse differential difference amplifiers in order to produce more power efficient Gm-C filter solutions. To demonstrate this, a 6th order low-pass Butterworth filter was designed in 0.18 m CMOS achieving a 65-MHz -3-dB frequency, an in-band input-referred third-order intercept point of 12.0 dBm, and an input referred noise density of 40 nV/Hz1=2, while only consuming 8.07 mW from a 1.8 V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

Low-power G m-C filter employing current-reuse differential difference amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mincey, John S.; Briseno-Vidrios, Carlos; Silva-Martinez, Jose

This study deals with the design of low-power, high performance, continuous-time filters. The proposed OTA architecture employs current-reuse differential difference amplifiers in order to produce more power efficient Gm-C filter solutions. To demonstrate this, a 6th order low-pass Butterworth filter was designed in 0.18 m CMOS achieving a 65-MHz -3-dB frequency, an in-band input-referred third-order intercept point of 12.0 dBm, and an input referred noise density of 40 nV/Hz1=2, while only consuming 8.07 mW from a 1.8 V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

Optimization of noise in non-integrated instrumentation amplifier for the amplification of very low electrophysiological [corrected] signals. Case of electro cardio graphic signals (ECG).

PubMed

Ngounou, Guy Merlin; Kom, Martin

2014-12-01

In this paper we present an instrumentation amplifier with discrete elements and optimized noise for the amplification of very low signals. In amplifying signals of very weak amplitude, the noise can completely absorb these signals if the used amplifier does not present the optimal guarantee to minimize the noise. Based on related research and re-viewing of recent patents Journal of Medical Systems, 30:205-209, 2006, we suggest an approach of noise reduction in amplification much more thoroughly than re-viewing of recent patents and we deduce from it the general criteria necessary and essential to achieve this optimization. The comparison of these criteria with the provisions adopted in practice leads to the inadequacy of conventional amplifiers for effective noise reduction. The amplifier we propose is an instrumentation amplifier with active negative feedback and optimized noise for the amplification of signals with very low amplitude. The application of this method in the case of electro cardio graphic signals (ECG) provides simulation results fully in line with forecasts.

An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

NASA Astrophysics Data System (ADS)

Chen, Hsin-Han; Hsieh, Chih-Cheng

2013-09-01

This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

Bandwidth tunable amplifier for recording biopotential signals.

PubMed

Hwang, Sungkil; Aninakwa, Kofi; Sonkusale, Sameer

2010-01-01

This paper presents a low noise, low power, bandwidth tunable amplifier for bio-potential signal recording applications. By employing depletion-mode pMOS transistor in diode configuration as a tunable sub pA current source to adjust the resistivity of MOS-Bipolar pseudo-resistor, the bandwidth is adjusted without any need for a separate band-pass filter stage. For high CMRR, PSRR and dynamic range, a fully differential structure is used in the design of the amplifier. The amplifier achieves a midband gain of 39.8dB with a tunable high-pass cutoff frequency ranging from 0.1Hz to 300Hz. The amplifier is fabricated in 0.18εm CMOS process and occupies 0.14mm(2) of chip area. A three electrode ECG measurement is performed using the proposed amplifier to show its feasibility for low power, compact wearable ECG monitoring application.

Phase-Noise and Amplitude-Noise Measurement of Low-Power Signals

NASA Technical Reports Server (NTRS)

Rubiola, Enrico; Salik, Ertan; Yu, Nan; Maleki, Lute

2004-01-01

Measuring the phase fluctuation between a pair of low-power microwave signals, the signals must be amplified before detection. In such cases the phase noise of the amplifier pair is the main cause of 1/f background noise of the instrument. this article proposes a scheme that makes amplification possible while rejecting the close in 1/f (flicker) noise of the two amplifiers. Noise rejection, which relies upon the understanding of the amplifier noise mechanism does not require averaging. Therefore, our scheme can also be the detector of a closed loop noise reduction system. the first prototype, compared to a traditional saturated mixer system under the same condition, show a 24 dB noise reduction of the 1/f region.

Development of a Low-Noise High Common-Mode-Rejection Instrumentation Amplifier. M.S. Thesis

NASA Technical Reports Server (NTRS)

Rush, Kenneth; Blalock, T. V.; Kennedy, E. J.

1975-01-01

Several previously used instrumentation amplifier circuits were examined to find limitations and possibilities for improvement. One general configuration is analyzed in detail, and methods for improvement are enumerated. An improved amplifier circuit is described and analyzed with respect to common mode rejection and noise. Experimental data are presented showing good agreement between calculated and measured common mode rejection ratio and equivalent noise resistance. The amplifier is shown to be capable of common mode rejection in excess of 140 db for a trimmed circuit at frequencies below 100 Hz and equivalent white noise below 3.0 nv/square root of Hz above 1000 Hz.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

Low noise buffer amplifiers and buffered phase comparators for precise time and frequency measurement and distribution

NASA Technical Reports Server (NTRS)

Eichinger, R. A.; Dachel, P.; Miller, W. H.; Ingold, J. S.

1982-01-01

Extremely low noise, high performance, wideband buffer amplifiers and buffered phase comparators were developed. These buffer amplifiers are designed to distribute reference frequencies from 30 KHz to 45 MHz from a hydrogen maser without degrading the hydrogen maser's performance. The buffered phase comparators are designed to intercompare the phase of state of the art hydrogen masers without adding any significant measurement system noise. These devices have a 27 femtosecond phase stability floor and are stable to better than one picosecond for long periods of time. Their temperature coefficient is less than one picosecond per degree C, and they have shown virtually no voltage coefficients.

Up-converted 1/f PM and AM noise in linear HBT amplifiers.

PubMed

Ferre-Pikal, Eva S; Savage, Frederick H

2008-08-01

In this paper we describe a technique to predict the 1/f phase modulation (PM) and 1/f amplitude modulation (AM) noise due to up-conversion of 1/f baseband current noise in microwave heterojunction bipolar transistor (HBT) amplifiers. We obtain an accurate model for the amplifier and find the expression for voltage gain in terms of DC bias, transistor parameters, and circuit components. Theoretical 1/f PM and AM noise sensitivities to 1/f baseband current noise are then found by applying the definitions of PM and AM noise to the gain expression of the amplifier. Measurements of PM and AM sensitivities at 500 MHz and 1 GHz were in good agreement with the values predicted by theory, verifying the validity of this technique. This method can be used to optimize amplifier design for low PM and AM noise. We show that the amplifier PM noise can be reduced by 9 dB by adjusting the value of the input coupling capacitor.

Design and implementation of a low-power SOI CMOS receiver

NASA Astrophysics Data System (ADS)

Zencir, Ertan

There is a strong demand for wireless communications in civilian and military applications, and space explorations. This work attempts to implement a low-power, high-performance fully-integrated receiver for deep space communications using Silicon on Insulator (SOI) CMOS technology. Design and implementation of a UHF low-IF receiver front-end in a 0.35-mum SOI CMOS technology are presented. Problems and challenges in implementing a highly integrated receiver at UHF are identified. Low-IF architecture, suitable for low-power design, has been adopted to mitigate the noise at the baseband. Design issues of the receiver building blocks including single-ended and differential LNA's, passive and active mixers, and variable gain/bandwidth complex filters are discussed. The receiver is designed to have a variable conversion gain of more than 100 dB with a 70 dB image rejection and a power dissipation of 45 mW from a 2.5-V supply. Design and measured performance of the LNA's, and the mixer are presented. Measurement results of RF front-end blocks including a single-ended LNA, a differential LNA, and a double-balanced mixer demonstrate the low power realizability of RF front-end circuits in SOI CMOS technology. We also report on the design and simulation of the image-rejecting complex IF filter and the full receiver circuit. Gain, noise, and linearity performance of the receiver components prove the viability of fully integrated low-power receivers in SOI CMOS technology.

2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

PubMed

Lee, Changhyun; Park, Changkun

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2).

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

PubMed Central

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-01-01

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

PubMed

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-12-26

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

NASA Astrophysics Data System (ADS)

Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

2016-07-01

In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

Recent progress and development of a speedster-EXD: a new event-triggered hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2015-08-01

We present the characterization of a new event-driven X-ray hybrid CMOS detector developed by Penn State University in collaboration with Teledyne Imaging Sensors. Along with its low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up, the Speedster-EXD has been designed with the capability to limit its readout to only those pixels containing charge, thus enabling even faster effective frame rates. The threshold for the comparator in each pixel can be set by the user so that only pixels with signal above the set threshold are read out. The Speedster-EXD hybrid CMOS detector also has two new in-pixel features that reduce noise from known noise sources: (1) a low-noise, high-gain CTIA amplifier to eliminate crosstalk from interpixel capacitance (IPC) and (2) in-pixel CDS subtraction to reduce kTC noise. We present the read noise, dark current, IPC, energy resolution, and gain variation measurements of one Speedster-EXD detector.

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

CMOS SiPM with integrated amplifier

NASA Astrophysics Data System (ADS)

Schwinger, Alexander; Brockherde, Werner; Hosticka, Bedrich J.; Vogt, Holger

2017-02-01

The integration of silicon photomultiplier (SiPM) and frontend electronics in a suitable optoelectronic CMOS process is a promising approach to increase the versatility of single-photon avalanche diode (SPAD)-based singlephoton detectors. By integrating readout amplifiers, the device output capacitance can be reduced to minimize the waveform tail, which is especially important for large area detectors (>10 × 10mm2). Possible architectures include a single readout amplifier for the whole detector, which reduces the output capacitance to 1:1 pF at minimal reduction in detector active area. On the other hand, including a readout amplifier in every SiPM cell would greatly improve the total output capacitance by minimizing the influence of metal routing parasitic capacitance, but requiring a prohibitive amount of detector area. As tradeoff, the proposed detector features one readout amplifier for each column of the detector matrix to allow for a moderate reduction in output capacitance while allowing the electronics to be placed in the periphery of the active detector area. The presented detector with a total size of 1.7 ♢ 1.0mm2 features 400 cells with a 50 μm pitch, where the signal of each column of 20 SiPM cells is summed in a readout channel. The 20 readout channels are subsequently summed into one output channel, to allow the device to be used as a drop-in replacement for commonly used analog SiPMs.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

A monolithic patch-clamping amplifier with capacitive feedback.

PubMed

Prakash, J; Paulos, J J; Jensen, D N

1989-03-01

Patch-clamping is an established method for directly measuring ionic transport through cellular membranes with sufficient resolution to observe open/close transitions of individual channel molecules. This paper describes an alternative technique for patch-clamping which uses a capacitor as the transimpedance element. This approach eliminates bandwidth and saturation limitations experienced with resistive patch-clamping amplifiers. A complete monolithic design featuring an on-chip operational amplifier, a capacitor array with gain-ranging from 30 pF down to 0.03 pF, and reset and gain ranging switches has been fabricated using 5 microns CMOS technology. It is shown that the voltage noise of the CMOS operational amplifier limits the overall noise performance, but that performance competitive with conventional instruments can be achieved over a 10 kHz bandwidth, at least for small input capacitances (less than or equal to 5 pF). Results are presented along with an analysis and comparison of noise performance using both resistive and capacitive elements.

Simple nonlinearity evaluation and modeling of low-noise amplifiers with application to radio astronomy receivers.

PubMed

Casas, F J; Pascual, J P; de la Fuente, M L; Artal, E; Portilla, J

2010-07-01

This paper describes a comparative nonlinear analysis of low-noise amplifiers (LNAs) under different stimuli for use in astronomical applications. Wide-band Gaussian-noise input signals, together with the high values of gain required, make that figures of merit, such as the 1 dB compression (1 dBc) point of amplifiers, become crucial in the design process of radiometric receivers in order to guarantee the linearity in their nominal operation. The typical method to obtain the 1 dBc point is by using single-tone excitation signals to get the nonlinear amplitude to amplitude (AM-AM) characteristic but, as will be shown in the paper, in radiometers, the nature of the wide-band Gaussian-noise excitation signals makes the amplifiers present higher nonlinearity than when using single tone excitation signals. Therefore, in order to analyze the suitability of the LNA's nominal operation, the 1 dBc point has to be obtained, but using realistic excitation signals. In this work, an analytical study of compression effects in amplifiers due to excitation signals composed of several tones is reported. Moreover, LNA nonlinear characteristics, as AM-AM, total distortion, and power to distortion ratio, have been obtained by simulation and measurement with wide-band Gaussian-noise excitation signals. This kind of signal can be considered as a limit case of a multitone signal, when the number of tones is very high. The work is illustrated by means of the extraction of realistic nonlinear characteristics, through simulation and measurement, of a 31 GHz back-end module LNA used in the radiometer of the QUIJOTE (Q U I JOint TEnerife) CMB experiment.

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

PubMed Central

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

Low energy CMOS for space applications

NASA Technical Reports Server (NTRS)

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors.

PubMed

Ge, Xiaoliang; Theuwissen, Albert J P

2018-02-27

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

Noise reduction in plasmonic amplifiers

NASA Astrophysics Data System (ADS)

Vyshnevyy, Andrey A.; Fedyanin, Dmitry Yu.

2018-06-01

Surface plasmon polaritons amplification give the possibility to overcome strong absorption in metals and design truly nanoscale devices for on-chip photonic circuits. However, the process of stimulated emission in the gain medium is inevitably accompanied by spontaneous emission, which greatly increases the noise power. Herein we present an efficient strategy for noise reduction in plasmonic amplifiers,which is based on gain redistribution along the amplifier. We show that even a very small gain redistribution (∼3%) makes it possible to increase the signal-to-noise ratio by ∼100% and improve the bit error ratio by orders of magnitude.

Cross-correlation measurement of quantum shot noise using homemade transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Hashisaka, Masayuki; Ota, Tomoaki; Yamagishi, Masakazu; Fujisawa, Toshimasa; Muraki, Koji

2014-05-01

We report a cross-correlation measurement system, based on a new approach, which can be used to measure shot noise in a mesoscopic conductor at milliKelvin temperatures. In contrast to other measurement systems in which high-speed low-noise voltage amplifiers are commonly used, our system employs homemade transimpedance amplifiers (TAs). The low input impedance of the TAs significantly reduces the crosstalk caused by unavoidable parasitic capacitance between wires. The TAs are designed to have a flat gain over a frequency band from 2 kHz to 1 MHz. Low-noise performance is attained by installing the TAs at a 4 K stage of a dilution refrigerator. Our system thus fulfills the technical requirements for cross-correlation measurements: low noise floor, high frequency band, and negligible crosstalk between two signal lines. Using our system, shot noise generated at a quantum point contact embedded in a quantum Hall system is measured. The good agreement between the obtained shot-noise data and theoretical predictions demonstrates the accuracy of the measurements.

Cross-correlation measurement of quantum shot noise using homemade transimpedance amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hashisaka, Masayuki, E-mail: hashisaka@phys.titech.ac.jp; Ota, Tomoaki; Yamagishi, Masakazu

We report a cross-correlation measurement system, based on a new approach, which can be used to measure shot noise in a mesoscopic conductor at milliKelvin temperatures. In contrast to other measurement systems in which high-speed low-noise voltage amplifiers are commonly used, our system employs homemade transimpedance amplifiers (TAs). The low input impedance of the TAs significantly reduces the crosstalk caused by unavoidable parasitic capacitance between wires. The TAs are designed to have a flat gain over a frequency band from 2 kHz to 1 MHz. Low-noise performance is attained by installing the TAs at a 4 K stage of amore » dilution refrigerator. Our system thus fulfills the technical requirements for cross-correlation measurements: low noise floor, high frequency band, and negligible crosstalk between two signal lines. Using our system, shot noise generated at a quantum point contact embedded in a quantum Hall system is measured. The good agreement between the obtained shot-noise data and theoretical predictions demonstrates the accuracy of the measurements.« less

Low-noise two-wired buffer electrodes for bioelectric amplifiers.

PubMed

Degen, Thomas; Torrent, Simon; Jäckel, Heinz

2007-07-01

Active buffer electrodes are known to improve the immunity of bioelectric recordings against power line interferences. A survey of published work reveals that buffer electrodes are almost exclusively designed using operational amplifiers (opamps). In this paper, we discuss the advantage of utilizing a single transistor instead. This allows for a simple electrode, which is small and requires only two wires. In addition, a single transistor adds considerably less noise when compared to an opamp with the same power consumption. We then discuss output resistance and gain as well as their respective effect on the common mode rejection ratio (CMRR). Finally, we demonstrate the use of two-wired buffer electrodes for a bioelectric amplifier.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

NASA Astrophysics Data System (ADS)

Riyan, Wang; Jiwei, Huang; Zhengping, Li; Weifeng, Zhang; Longyue, Zeng

2012-03-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35 μm CMOS

NASA Astrophysics Data System (ADS)

Hui, Xu; Jun, Feng; Quan, Liu; Wei, Li

2011-10-01

A 3.125-Gb/s transimpedance amplifier (TIA) for an optical communication system is realized in 0.35 μm CMOS technology. The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point. In addition, noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩ and -3 dB bandwidth of 2.31 GHz. The measured average input referred noise current spectral density is about . The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS. Under a single 3.3-V supply voltage, the TIA consumes only 58.08 mW, including 20 mW from the output buffer. The whole die area is 465 × 435 μm2.

A low-noise transimpedance amplifier for the detection of "Violin-Mode" resonances in Advanced Laser Interferometer Gravitational wave Observatory suspensions.

PubMed

Lockerbie, N A; Tokmakov, K V

2014-11-01

This paper describes the design and performance of an extremely low-noise differential transimpedance amplifier, which takes its two inputs from separate photodiodes. The amplifier was planned to serve as the front-end electronics for a highly sensitive shadow-displacement sensing system, aimed at detecting very low-level "Violin-Mode" (VM) oscillations in 0.4 mm diameter by 600 mm long fused-silica suspension fibres. Four such highly tensioned fibres support the 40 kg test-masses/mirrors of the Advanced Laser Interferometer Gravitational wave Observatory interferometers. This novel design of amplifier incorporates features which prevent "noise-gain peaking" arising from large area photodiode (and cable) capacitances, and which also usefully separate the DC and AC photocurrents coming from the photodiodes. In consequence, the differential amplifier was able to generate straightforwardly two DC outputs, one per photodiode, as well as a single high-gain output for monitoring the VM oscillations-this output being derived from the difference of the photodiodes' two, naturally anti-phase, AC photocurrents. Following a displacement calibration, the amplifier's final VM signal output was found to have an AC displacement responsivity at 500 Hz of (9.43 ± 1.20) MV(rms) m(-1)(rms), and, therefore, a shot-noise limited sensitivity to such AC shadow- (i.e., fibre-) displacements of (69 ± 13) picometres/√Hz at this frequency, over a measuring span of ±0.1 mm.

A low-noise transimpedance amplifier for the detection of "Violin-Mode" resonances in advanced Laser Interferometer Gravitational wave Observatory suspensions

NASA Astrophysics Data System (ADS)

Lockerbie, N. A.; Tokmakov, K. V.

2014-11-01

This paper describes the design and performance of an extremely low-noise differential transimpedance amplifier, which takes its two inputs from separate photodiodes. The amplifier was planned to serve as the front-end electronics for a highly sensitive shadow-displacement sensing system, aimed at detecting very low-level "Violin-Mode" (VM) oscillations in 0.4 mm diameter by 600 mm long fused-silica suspension fibres. Four such highly tensioned fibres support the 40 kg test-masses/mirrors of the Advanced Laser Interferometer Gravitational wave Observatory interferometers. This novel design of amplifier incorporates features which prevent "noise-gain peaking" arising from large area photodiode (and cable) capacitances, and which also usefully separate the DC and AC photocurrents coming from the photodiodes. In consequence, the differential amplifier was able to generate straightforwardly two DC outputs, one per photodiode, as well as a single high-gain output for monitoring the VM oscillations—this output being derived from the difference of the photodiodes' two, naturally anti-phase, AC photocurrents. Following a displacement calibration, the amplifier's final VM signal output was found to have an AC displacement responsivity at 500 Hz of (9.43 ± 1.20) MV(rms) m-1(rms), and, therefore, a shot-noise limited sensitivity to such AC shadow- (i.e., fibre-) displacements of (69 ± 13) picometres/√Hz at this frequency, over a measuring span of ±0.1 mm.

Raman-noise-induced noise-figure limit for chi (3) parametric amplifiers

NASA Astrophysics Data System (ADS)

Voss, Paul L.; Kumar, Prem

2004-03-01

The nonzero response time of the Kerr [chi (3)] nonlinearity determines the quantum-limited noise figure of c3 parametric amplifiers. This nonzero response time of the nonlinearity requires coupling of the parametric amplification process to a molecular-vibration phonon bath, causing the addition of excess noise through Raman gain or loss at temperatures above 0 K. The effect of this excess noise on the noise figure can be surprisingly significant. We derive analytical expressions for this quantum-limited noise figure for phase-insensitive operation of a chi (3) amplifier and show good agreement with published noise-figure measurements.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors †

PubMed Central

Theuwissen, Albert J. P.

2018-01-01

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models. PMID:29495496

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Comotti, Daniele; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio

2015-10-01

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

Ultrastable low-noise current amplifier: a novel device for measuring small electric currents with high accuracy.

PubMed

Drung, D; Krause, C; Becker, U; Scherer, H; Ahlers, F J

2015-02-01

An ultrastable low-noise current amplifier (ULCA) is presented. The ULCA is a non-cryogenic instrument based on specially designed operational amplifiers and resistor networks. It involves two stages, the first providing a 1000-fold current gain and the second performing a current-to-voltage conversion via an internal 1 MΩ reference resistor or, optionally, an external standard resistor. The ULCA's transfer coefficient is highly stable versus time, temperature, and current amplitude within the full dynamic range of ±5 nA. The low noise level of 2.4 fA/√Hz helps to keep averaging times short at small input currents. A cryogenic current comparator is used to calibrate both input current gain and output transresistance, providing traceability to the quantum Hall effect. Within one week after calibration, the uncertainty contribution from short-term fluctuations and drift of the transresistance is about 0.1 parts per million (ppm). The long-term drift is typically 5 ppm/yr. A high-accuracy variant is available that shows improved stability of the input gain at the expense of a higher noise level of 7.5 fA/√Hz. The ULCA also allows the traceable generation of small electric currents or the calibration of high-ohmic resistors.

Ultrastable low-noise current amplifier: A novel device for measuring small electric currents with high accuracy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drung, D.; Krause, C.; Becker, U.

2015-02-15

An ultrastable low-noise current amplifier (ULCA) is presented. The ULCA is a non-cryogenic instrument based on specially designed operational amplifiers and resistor networks. It involves two stages, the first providing a 1000-fold current gain and the second performing a current-to-voltage conversion via an internal 1 MΩ reference resistor or, optionally, an external standard resistor. The ULCA’s transfer coefficient is highly stable versus time, temperature, and current amplitude within the full dynamic range of ±5 nA. The low noise level of 2.4 fA/√Hz helps to keep averaging times short at small input currents. A cryogenic current comparator is used to calibratemore » both input current gain and output transresistance, providing traceability to the quantum Hall effect. Within one week after calibration, the uncertainty contribution from short-term fluctuations and drift of the transresistance is about 0.1 parts per million (ppm). The long-term drift is typically 5 ppm/yr. A high-accuracy variant is available that shows improved stability of the input gain at the expense of a higher noise level of 7.5 fA/√Hz. The ULCA also allows the traceable generation of small electric currents or the calibration of high-ohmic resistors.« less

Ultrastable low-noise current amplifier: A novel device for measuring small electric currents with high accuracy

NASA Astrophysics Data System (ADS)

Drung, D.; Krause, C.; Becker, U.; Scherer, H.; Ahlers, F. J.

2015-02-01

An ultrastable low-noise current amplifier (ULCA) is presented. The ULCA is a non-cryogenic instrument based on specially designed operational amplifiers and resistor networks. It involves two stages, the first providing a 1000-fold current gain and the second performing a current-to-voltage conversion via an internal 1 MΩ reference resistor or, optionally, an external standard resistor. The ULCA's transfer coefficient is highly stable versus time, temperature, and current amplitude within the full dynamic range of ±5 nA. The low noise level of 2.4 fA/√Hz helps to keep averaging times short at small input currents. A cryogenic current comparator is used to calibrate both input current gain and output transresistance, providing traceability to the quantum Hall effect. Within one week after calibration, the uncertainty contribution from short-term fluctuations and drift of the transresistance is about 0.1 parts per million (ppm). The long-term drift is typically 5 ppm/yr. A high-accuracy variant is available that shows improved stability of the input gain at the expense of a higher noise level of 7.5 fA/√Hz. The ULCA also allows the traceable generation of small electric currents or the calibration of high-ohmic resistors.

Cryogenically cooled low-noise amplifier for radio-astronomical observations and centimeter-wave deep-space communications systems

NASA Astrophysics Data System (ADS)

Vdovin, V. F.; Grachev, V. G.; Dryagin, S. Yu.; Eliseev, A. I.; Kamaletdinov, R. K.; Korotaev, D. V.; Lesnov, I. V.; Mansfeld, M. A.; Pevzner, E. L.; Perminov, V. G.; Pilipenko, A. M.; Sapozhnikov, B. D.; Saurin, V. P.

2016-01-01

We report a design solution for a highly reliable, low-noise and extremely efficient cryogenically cooled transmit/receive unit for a large antenna system meant for radio-astronomical observations and deep-space communications in the X band. We describe our design solution and the results of a series of laboratory and antenna tests carried out in order to investigate the properties of the cryogenically cooled low-noise amplifier developed. The transmit/receive unit designed for deep-space communications (Mars missions, radio observatories located at Lagrangian point L2, etc.) was used in practice for communication with live satellites including "Radioastron" observatory, which moves in a highly elliptical orbit.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Common source cascode amplifiers for integrating IR-FPA applications

NASA Technical Reports Server (NTRS)

Woolaway, James T.; Young, Erick T.

1989-01-01

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Response of a lock-in amplifier to noise

NASA Astrophysics Data System (ADS)

Van Baak, D. A.; Herold, George

2014-08-01

The "lock-in" detection technique can extract, from a possibly noisy waveform, the amplitude of a signal that is synchronous with a known reference signal. This paper examines the effects of input noise on the output of a lock-in amplifier. We present quantitative predictions for the root-mean-square size of the resulting fluctuations and for the spectral density of the noise at the output of a lock-in amplifier. Our results show how a lock-in amplifier can be used to measure the spectral density of noise in the case of a noise-only input signal. Some implications of the theory, familiar and surprising, are tested against experimental data.

X-band ultralow-noise maser amplifier performance

NASA Technical Reports Server (NTRS)

Glass, G. W.; Ortiz, G. G.; Johnson, D. L.

1994-01-01

Noise temperature measurements of an 8440-MHz ultralow noise maser amplifier (ULNA) have been performed at subatmospheric, liquid-helium temperatures. The traveling-wave maser was operated while immersed in a liquid helium bath. The lowest input noise temperature measured was 1.43 +/- 0.16 K at a physical temperature of 1.60 K. At this physical temperature, the observed gain per centimeter of ruby was 4.9 dB/cm. The amplifier had a 3-dB bandwidth of 76 MHz.

A low-noise transimpedance amplifier for the detection of “Violin-Mode” resonances in advanced Laser Interferometer Gravitational wave Observatory suspensions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lockerbie, N. A.; Tokmakov, K. V.

2014-11-15

This paper describes the design and performance of an extremely low-noise differential transimpedance amplifier, which takes its two inputs from separate photodiodes. The amplifier was planned to serve as the front-end electronics for a highly sensitive shadow-displacement sensing system, aimed at detecting very low-level “Violin-Mode” (VM) oscillations in 0.4 mm diameter by 600 mm long fused-silica suspension fibres. Four such highly tensioned fibres support the 40 kg test-masses/mirrors of the Advanced Laser Interferometer Gravitational wave Observatory interferometers. This novel design of amplifier incorporates features which prevent “noise-gain peaking” arising from large area photodiode (and cable) capacitances, and which also usefullymore » separate the DC and AC photocurrents coming from the photodiodes. In consequence, the differential amplifier was able to generate straightforwardly two DC outputs, one per photodiode, as well as a single high-gain output for monitoring the VM oscillations—this output being derived from the difference of the photodiodes’ two, naturally anti-phase, AC photocurrents. Following a displacement calibration, the amplifier's final VM signal output was found to have an AC displacement responsivity at 500 Hz of (9.43 ± 1.20) MV(rms) m{sup −1}(rms), and, therefore, a shot-noise limited sensitivity to such AC shadow- (i.e., fibre-) displacements of (69 ± 13) picometres/√Hz at this frequency, over a measuring span of ±0.1 mm.« less

A model for phase noise generation in amplifiers.

PubMed

Tomlin, T D; Fynn, K; Cantoni, A

2001-11-01

In this paper, a model is presented for predicting the phase modulation (PM) and amplitude modulation (AM) noise in bipolar junction transistor (BJT) amplifiers. The model correctly predicts the dependence of phase noise on the signal frequency (at a particular carrier offset frequency), explains the noise shaping of the phase noise about the signal frequency, and shows the functional dependence on the transistor parameters and the circuit parameters. Experimental studies on common emitter (CE) amplifiers have been used to validate the PM noise model at carrier frequencies between 10 and 100 MHz.

A 205GHz Amplifier in 90nm CMOS Technology

DTIC Science & Technology

2017-03-01

San Jose State University San Jose, CA, USA       Abstract: This paper presents a 205GHz amplifier drawing 43.4mA from a 0.9V power supply with...10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...reported in [2]. In this paper, two neutralization techniques, internal and external approaches, have been implemented to achieve higher power

Gain dynamics of clad-pumped Yb-fiber amplifier and intensity noise control.

PubMed

Zhao, Jian; Guiraud, Germain; Floissat, Florian; Gouhier, Benoit; Rota-Rodrigo, Sergio; Traynor, Nicholas; Santarelli, Giorgio

2017-01-09

Gain dynamics study provides an attractive method to understand the intensity noise behavior in fiber amplifiers. Here, the gain dynamics of a medium power (5 W) clad-pumped Yb-fiber amplifier is experimentally evaluated by measuring the frequency domain transfer functions for the input seed and pump lasers from 10 Hz to 1 MHz. We study gain dynamic behavior of the fiber amplifier in the presence of significant residual pump power (compared to the seed power), showing that the seed transfer function is strongly saturated at low Fourier frequencies while the pump power modulation transfer function is nearly unaffected. The characterization of relative intensity noise (RIN) of the fiber amplifier is well explained by the gain dynamics analysis. Finally, a 600 kHz bandwidth feedback loop using an acoustic-optical modulator (AOM) controlling the seed intensity is successfully demonstrated to suppress the broadband laser intensity noise. A maximum noise reduction of about 30 dB is achieved leading to a RIN of -152 dBc/Hz (~1 kHz-10 MHz) at 2.5 W output power.

Josephson junction microwave amplifier in self-organized noise compression mode

PubMed Central

Lähteenmäki, Pasi; Vesterinen, Visa; Hassel, Juha; Seppä, Heikki; Hakonen, Pertti

2012-01-01

The fundamental noise limit of a phase-preserving amplifier at frequency is the standard quantum limit . In the microwave range, the best candidates have been amplifiers based on superconducting quantum interference devices (reaching the noise temperature at 700 MHz), and non-degenerate parametric amplifiers (reaching noise levels close to the quantum limit at 8 GHz). We introduce a new type of an amplifier based on the negative resistance of a selectively damped Josephson junction. Noise performance of our amplifier is limited by mixing of quantum noise from Josephson oscillation regime down to the signal frequency. Measurements yield nearly quantum-limited operation, at 2.8 GHz, owing to self-organization of the working point. Simulations describe the characteristics of our device well and indicate potential for wide bandwidth operation. PMID:22355788

Large CMOS imager using hadamard transform based multiplexing

NASA Technical Reports Server (NTRS)

Karasik, Boris S.; Wadsworth, Mark V.

2005-01-01

We have developed a concept design for a large (10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be 100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Excess noise in gain-guided amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deutsch, I.H.; Garrison, J.C.; Wright, E.M.

1991-06-01

A second-quantized theory of the radiation field is used to study the origin of the excess noise observed in gain-guided amplifiers. We find that the reduction of the signal-to-noise ratio is a function of the length of the amplifier, and thus the enhancement of the noise is a propagation effect arising from longitudinally inhomogeneous gain of the noise rather than from an excess of local spontaneous emission. We confirm this conclusion by showing that the microscopic rate of spontaneous emission into a given non-power-orthogonal cavity mode is not enhanced by the Petermann factor. In addition, we illustrate the difficulties associatedmore » with photon statistics for this and other open systems by showing that no acceptable family of photon-number operators corresponds to a set of non-power-orthogonal cavity modes.« less

Enhancing the noise performance of monolithic microwave integrated circuit-based low noise amplifiers through the use of a discrete preamplifying transistor

NASA Astrophysics Data System (ADS)

McCulloch, Mark A.; Melhuish, Simon J.; Piccirillo, Lucio

2015-01-01

An approach to enhancing the noise performance of an InP monolithic microwave integrated circuit (MMIC)-based low noise amplifiers (LNA) through the use of a discrete 100-nm gate length InP high electron mobility transistor is outlined. This LNA, known as a transistor in front of MMIC (T + MMIC) LNA, possesses a gain in excess of 40 dB and an average noise temperature of 9.4 K across the band 27 to 33 GHz at a physical temperature of 8 K. This compares favorably with 14.5 K for an LNA containing an equivalent MMIC. A simple advanced design system model offering further insights into the operation of the LNA is also presented and the LNA is compared with the current state-of-the-art Planck LFI LNAs.

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

NASA Astrophysics Data System (ADS)

Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

2017-06-01

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

Low noise InP-based MMIC receivers for W-band

NASA Technical Reports Server (NTRS)

Leonard, Regis F.

1991-01-01

A program to develop a monolithic W-band low noise amplifier (a critical element in any W-band communications, sensors, or radar application) is described. Goals of the program include a completely monolithic low noise amplifier, less than a 3.5 dB noise figure, and a monolithic mixer suitable for integration with the LNA.

A low power and low phase-noise 91 96 GHz VCO in 90 nm CMOS

NASA Astrophysics Data System (ADS)

Lin, Yo-Sheng; Lan, Kai-Siang; Chuang, Ming-Yuan; Lin, Yu-Ching

2018-06-01

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91 96 GHz, close to the simulated (92.1 96.7 GHz) and the calculated one (92.2 98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of - 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of -188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2.

Noise behavior of microwave amplifiers operating under nonlinear conditions

NASA Astrophysics Data System (ADS)

Escotte, L.; Gonneau, E.; Chambon, C.; Graffeuil, J.

2005-12-01

B The noise behavior of microwave amplifiers operating under a large-signal condition has been studied in this paper. A Gaussian noise is added to a microwave signal and they are applied at the input of several amplifying devices. Experimental data show a decrease of the output noise spectral density when the power of the microwave signal at the input of the devices increases due to the compression of the amplifiers. A distortion component due to the interaction of the signal and its harmonics with the noise is also demonstrated from a simplified theoretical model. The statistical properties of the signal and the noise have also been investigated in order to verify the Gaussianity of the noise at the output of the nonlinear circuits. We have also observed that the majority of the measured devices show some variations of their additive noise versus the input power level.

Amplification and noise properties of an erbium-doped multicore fiber amplifier.

PubMed

Abedin, K S; Taunay, T F; Fishteyn, M; Yan, M F; Zhu, B; Fini, J M; Monberg, E M; Dimarcello, F V; Wisk, P W

2011-08-15

A multicore erbium-doped fiber (MC-EDF) amplifier for simultaneous amplification in the 7-cores has been developed, and the gain and noise properties of individual cores have been studied. The pump and signal radiation were coupled to individual cores of MC-EDF using two tapered fiber bundled (TFB) couplers with low insertion loss. For a pump power of 146 mW, the average gain achieved in the MC-EDF fiber was 30 dB, and noise figure was less than 4 dB. The net useful gain from the multicore-amplifier, after taking into consideration of all the passive losses, was about 23-27 dB. Pump induced ASE noise transfer between the neighboring channel was negligible. © 2011 Optical Society of America

Fixed Pattern Noise pixel-wise linear correction for crime scene imaging CMOS sensor

NASA Astrophysics Data System (ADS)

Yang, Jie; Messinger, David W.; Dube, Roger R.; Ientilucci, Emmett J.

2017-05-01

Filtered multispectral imaging technique might be a potential method for crime scene documentation and evidence detection due to its abundant spectral information as well as non-contact and non-destructive nature. Low-cost and portable multispectral crime scene imaging device would be highly useful and efficient. The second generation crime scene imaging system uses CMOS imaging sensor to capture spatial scene and bandpass Interference Filters (IFs) to capture spectral information. Unfortunately CMOS sensors suffer from severe spatial non-uniformity compared to CCD sensors and the major cause is Fixed Pattern Noise (FPN). IFs suffer from "blue shift" effect and introduce spatial-spectral correlated errors. Therefore, Fixed Pattern Noise (FPN) correction is critical to enhance crime scene image quality and is also helpful for spatial-spectral noise de-correlation. In this paper, a pixel-wise linear radiance to Digital Count (DC) conversion model is constructed for crime scene imaging CMOS sensor. Pixel-wise conversion gain Gi,j and Dark Signal Non-Uniformity (DSNU) Zi,j are calculated. Also, conversion gain is divided into four components: FPN row component, FPN column component, defects component and effective photo response signal component. Conversion gain is then corrected to average FPN column and row components and defects component so that the sensor conversion gain is uniform. Based on corrected conversion gain and estimated image incident radiance from the reverse of pixel-wise linear radiance to DC model, corrected image spatial uniformity can be enhanced to 7 times as raw image, and the bigger the image DC value within its dynamic range, the better the enhancement.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.

PubMed

Adimulam, Mahesh Kumar; Divya, A; Tejaswi, K; Srinivas, M B

2017-07-01

A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31-70 dB, input referred noise of 1.15 μVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 μW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm 2 .

The challenge of sCMOS image sensor technology to EMCCD

NASA Astrophysics Data System (ADS)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Noise characteristics of a plasma relativistic microwave amplifier

DOE Office of Scientific and Technical Information (OSTI.GOV)

Strelkov, P. S., E-mail: strelkov@fpl.gpi.ru; Ivanov, I. E.; Shumeiko, D. V.

2016-07-15

Reasons for the occurrence of microwave noise at the output of a plasma relativistic amplifier have been analyzed. It is found that, in the absence of an input signal, the emission spectrum of the plasma relativistic microwave amplifier is similar to that of an electron beam in vacuum. It is concluded that microwave noise at the output of the amplifier appears as a result of amplification of the intrinsic noise of the electron beam. The emission characteristics of a relativistic electron beam formed in a magnetically insulated diode with an explosive emission cathode in vacuum have been studied experimentally formore » the first time. An important point is that, in this case, there is no virtual cathode in the drift space.« less

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Development of a low-noise amplifier for neutron detection in harsh environment

NASA Astrophysics Data System (ADS)

Angelone, M.; Cardarelli, R.; Paolozzi, L.; Pillon, M.

2014-10-01

A fast matching charge amplifier for neutron spectroscopy in harsh environment has been developed and tested at the JET Tokamak. This front-end circuit is capable to operate at a distance up to 100 meters from a sensor without increasing its equivalent noise charge. Further improvements are possible by exploiting the intrinsic performance of silicon-germanium bipolar junction transistors.

Low Noise Optical Amplifiers

DTIC Science & Technology

2010-05-01

Karsten Rottwitt DTU Fotonik Department of Photonics Engineering, Technical University of Denmark - 2 - TABLE OF...at DTU Fotonik, has intensified through two new ph.d positions within parametric amplifiers, one partly funded through a research program on phase...Activities: As indicated in the above DTU Fotonik now has significant activities on using parametric processes in optical fibers. This includes

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

PubMed Central

Boukhayma, Assim; Peizerat, Arnaud; Enz, Christian

2016-01-01

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

Nanosecond-laser induced crosstalk of CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.

PubMed

Wong, A K Y; Kong-Pang Pun; Yuan-Ting Zhang; Ka Nang Leung

2008-12-01

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

A 2385 MHz, 2-stage low noise amplifier design

NASA Technical Reports Server (NTRS)

Sifri, Jack D.

1986-01-01

This article shows the design aspects of a 2.385 GHz low noise preamplifier with a .7 dB noise figure and 16.5 dB gain using the NE 67383 FET. The design uses a unique method in matching the input which achieves optimum noise figure and unconditional stability.

Relative intensity noise transfer of large-bandwidth pump lasers in Raman fiber amplifiers

NASA Astrophysics Data System (ADS)

Keita, Kafing; Delaye, Philippe; Frey, Robert; Roosen, Gérald

2006-12-01

A theoretical analysis of the Raman amplification in optical fibers and the pump-to-signal relative intensity noise (RIN) transfer has been performed in the spectral domain. An efficient Raman amplification of a monochromatic signal beam by a large-bandwidth pump beam has been demonstrated for a pump bandwidth much smaller than the Raman linewidth. Under the same approximation the pump-to-signal RIN transfer has been calculated in both cases of copropagating and counterpropagating beams in the two limiting cases of modulated monochromatic and smooth-profile large-bandwidth pump beams. At low frequencies the excess of noise evidenced in the case of a modulated monochromatic pump beam did not exist in the case of large-bandwidth pseudoincoherent sources. As this noise reduction can be as large as 13 dB for a 40 dB net gain of the amplifier, such incoherent pumping sources must be considered for the purpose of low-noise Raman amplifiers.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

NASA Astrophysics Data System (ADS)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

Novel design of low noise preamplifier for medical ultrasound transducers.

PubMed

Amer, Mashhour Bani

2011-02-01

A novel design of low noise amplifier for medical ultrasound transducers is described in this paper. Unlike conventional low noise preamplifiers, this design proposes a new circuit configuration which has electronically adjustable matching resistance that allows the preamplifier to be compatible with a variety of medical ultrasound transducers. The design employs current feedback operational amplifier to enhance the gain-bandwidth independence and improve the design slew rate. Simulation results show that the proposed design has very low output noise voltage spectral density and the level of this noise does not increase when its tunable matching resistance is increased or decreased.

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

PubMed

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

Digital Lock-In Detector for Ultra-Low Level Noise Spectrum Analysis

DTIC Science & Technology

1988-08-01

Noise measurements,’ digital lockAn detector; 1 / f noise ; P...lower than the internal amplifier noise . Especially at low frequencies, amplifier noises become overwhelming, due to the 1 / f noise generated by the...shows the set-up. vm is the modulating signal generated by the computer. The two lOOk’s are metal film resistors, whose 1 / f noise is negligible. Ri’s

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Origin of 1/f PM and AM noise in bipolar junction transistor amplifiers.

PubMed

Walls, F L; Ferre-Pikal, E S; Jefferts, S R

1997-01-01

In this paper we report the results of extensive research on phase modulation (PM) and amplitude modulation (AM) noise in linear bipolar junction transistor (BJT) amplifiers. BJT amplifiers exhibit 1/f PM and AM noise about a carrier signal that is much larger than the amplifiers thermal noise at those frequencies in the absence of the carrier signal. Our work shows that the 1/f PM noise of a BJT based amplifier is accompanied by 1/f AM noise which can be higher, lower, or nearly equal, depending on the circuit implementation. The 1/f AM and PM noise in BJTs is primarily the result of 1/f fluctuations in transistor current, transistor capacitance, circuit supply voltages, circuit impedances, and circuit configuration. We discuss the theory and present experimental data in reference to common emitter amplifiers, but the analysis can be applied to other configurations as well. This study provides the functional dependence of 1/f AM and PM noise on transistor parameters, circuit parameters, and signal frequency, thereby laying the groundwork for a comprehensive theory of 1/f AM and PM noise in BJT amplifiers. We show that in many cases the 1/f PM and AM noise can be reduced below the thermal noise of the amplifier.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

A CMOS-MEMS clamped–clamped beam displacement amplifier for resonant switch applications

NASA Astrophysics Data System (ADS)

Liu, Jia-Ren; Lu, Shih-Chuan; Tsai, Chun-Pu; Li, Wei-Chang

2018-06-01

This paper presents a micromechanical clamped–clamped beam (CC-beam) displacement amplifier based on a CMOS-MEMS fabrication process platform. In particular, a 2.0 MHz resonant displacement amplifier composed of two identical CC-beams coupled by a mechanical beam at locations where the two beams have mismatched velocities exhibits a larger displacement, up to 9.96×, on one beam than that of the other. The displacement amplification prevents unwanted input impacting—the structure switches only to the output but not the input—required by resonant switch-based mechanical circuits (Kim et al 2009 22nd IEEE Int. Conf. on Micro Electro Mechanical Systems; Lin et al 2009 15th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’09) Li et al 2013 17th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’13)). Compared to a single CC-beam displacement amplifier, theory predicts that the displacement amplifying CC-beam array yields a larger overall output displacement for displacement gain beyond 1.13 thanks to the preserved input driving force. A complete analytical model predicts the resultant stiffness and displacement gain of the coupled CC-beam displacement amplifier that match well with finite element analysis (FEA) prediction and measured results.

Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs

NASA Astrophysics Data System (ADS)

Ibrahim, Mohamed Farhat

Silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) have the properties of producing very low noise and high gain over a wide bandwidth. Because of these properties, SiGe HBTs have continually improved and now compete with InP and GaAs HEMTs for low-noise amplification. This thesis investigates the theoretical characterizations and optimizations of SiGe HBT low noise amplifiers (LNAs) for low-noise low-power applications, using SiGe BiCMOS (bipolar complementary metal-oxide-semiconductor) technology. The theoretical characterization of SiGe HBT transistors is investigated by a comprehensive study of the DC and small-signal transistor modeling. Based on a selected small-signal model, a noise model for the SiGe HBT transistor is produced. This noise model is used to build a cascode inductively degenerated SiGe HBT LNA circuit. The noise figure (NF) equation for this LNA is derived. This NF equation shows better than 94.4% agreement with the simulation results. With the small-signal model verification, a new analytical method for optimizing the noise figure of the SiGe HBT LNA circuits is presented. The novelty feature of this optimization is the inclusion of the noise contributions of the base inductor parasitic resistance, the emitter inductor parasitic resistance and the bond-wire inductor parasitic resistances. The optimization is performed by reducing the number of design variables as possible. This improved theoretical optimization results in LNA designs that achieve better noise figure performance compared to previously published results in bipolar and BiCMOS technologies. Different design constraints are discussed for the LNA optimization techniques. Three different LNAs are designed. The three designs are fully integrated and fabricated in a single chip to achieve a fully monolithic realization. The LNA designs are experimentally verified. The low noise design produced a NF of 1.5dB, S21 of 15dB, and power consumption of 15mW. The three LNA

A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

PubMed

Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

2012-01-01

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Matching technique yields optimum LNA performance. [Low Noise Amplifiers

NASA Technical Reports Server (NTRS)

Sifri, J. D.

1986-01-01

The present article is concerned with a case in which an optimum noise figure and unconditional stability have been designed into a 2.385-GHz low-noise preamplifier via an unusual method for matching the input with a suspended line. The results obtained with several conventional line-matching techniques were not satisfactory. Attention is given to the minimization of thermal noise, the design procedure, requirements for a high-impedance line, a sampling of four matching networks, the noise figure of the single-line matching network as a function of frequency, and the approaches used to achieve unconditional stability.

Low-noise readout circuit for SWIR focal plane arrays

NASA Astrophysics Data System (ADS)

Altun, Oguz; Tasdemir, Ferhat; Nuzumlali, Omer Lutfi; Kepenek, Reha; Inceturkmen, Ercihan; Akyurek, Fatih; Tunca, Can; Akbulut, Mehmet

2017-02-01

This paper reports a 640x512 SWIR ROIC with 15um pixel pitch that is designed and fabricated using 0.18um CMOS process. Main challenge of SWIR ROIC design is related to input circuit due to pixel area and noise limitations. In this design, CTIA with single stage amplifier is utilized as input stage. The pixel design has three pixel gain options; High Gain (HG), Medium Gain (MG), and Low Gain (LG) with corresponding Full-Well-Capacities of 18.7ké, 190ké and 1.56Mé, respectively. According to extracted simulation results, 5.9é noise is achieved at HG mode and 200é is achieved at LG mode of operation. The ROIC can be programmed through an SPI interface. It supports 1, 2 and 4 output modes which enables the user to configure the detector to work at 30, 60 and 120fps frame rates. In the 4 output mode, the total power consumption of the ROIC is less than 120mW. The ROIC is powered from a 3.3V analog supply and allows for an output swing range in excess of 2V. Anti-blooming feature is added to prevent any unwanted blooming effect during readout.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting.

PubMed

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-04-09

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e(-) read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting

PubMed Central

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-01-01

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e− read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor. PMID:27070625

Gain and noise figure enhancement of Er+3/Yb+3 co-doped fiber/Raman hybrid amplifier

NASA Astrophysics Data System (ADS)

Mahran, O.

2016-02-01

An Er/Yb co-doped fiber/Raman hybrid amplifier (HA) is proposed and studied theoretically and analytically to improve the gain and noise figure of optical amplifiers. The calculations are performed under a uniform dopant and steady-state conditions. The initial energy transfer efficiency for Er/Yb co-doped fiber amplifier (EYDFA) is introduced, while the amplified spontaneous emission (ASE) is neglected. The glass fiber used for both Er/Yb and Raman amplifiers is phosphate. Different pump powers are used for both EYDFA and RA with 1 μW input signal power, 1 m length of Er/Yb amplifier and 25 km length of Raman amplifier (RA). The proposed model is validated for Er/Yb co-doped amplifier and Raman amplifier separately by comparing the calculating results with the experimental data. A high gain and low noise figure at 200 mW Raman pump power and 500 mW Er/Yb pump power are obtained for the proposed HA as compared with the experimental results of EYDFA, Raman amplifier and the EDFA/Raman hybrid amplifier.

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

NASA Astrophysics Data System (ADS)

Hamaizia, Z.; Sengouga, N.; Yagoub, M. C. E.; Missous, M.

2012-02-01

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S11 < -10 dB, S22 < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

A two-step A/D conversion and column self-calibration technique for low noise CMOS image sensors.

PubMed

Bae, Jaeyoung; Kim, Daeyun; Ham, Seokheon; Chae, Youngcheol; Song, Minkyu

2014-07-04

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

NASA Astrophysics Data System (ADS)

Verma, Bipin Kumar; Akashe, Shyam; Sharma, Sanjay

2015-09-01

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes - sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Effective amplifier noise for an optical receiver based on linear mode avalanche photodiodes

NASA Technical Reports Server (NTRS)

Chen, C.-C.

1989-01-01

The rms noise charge induced by the amplifier for an optical receiver based on the linear-mode avalanche photodiode (APD) was analyzed. It is shown that for an amplifier with a 1-pF capacitor and a noise temperature of 100 K, the rms noise charge due to the amplifier is about 300. Since the noise charge must be small compared to the signal gain, APD gains on the order of 1000 will be required to operate the receiver in the linear mode.

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

NASA Astrophysics Data System (ADS)

Utagawa, Akira; Asai, Tetsuya; Hirose, Tetsuya; Amemiya, Yoshihito

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1], [2]. We regard neural oscillators as independent clock sources on LSIs; i. e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (<1GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

Centroid measurement error of CMOS detector in the presence of detector noise for inter-satellite optical communications

NASA Astrophysics Data System (ADS)

Li, Xin; Zhou, Shihong; Ma, Jing; Tan, Liying; Shen, Tao

2013-08-01

CMOS is a good candidate tracking detector for satellite optical communications systems with outstanding feature of sub-window for the development of APS (Active Pixel Sensor) technology. For inter-satellite optical communications it is critical to estimate the direction of incident laser beam precisely by measuring the centroid position of incident beam spot. The presence of detector noise results in measurement error, which degrades the tracking performance of systems. In this research, the measurement error of CMOS is derived taking consideration of detector noise. It is shown that the measurement error depends on pixel noise, size of the tracking sub-window (pixels number), intensity of incident laser beam, relative size of beam spot. The influences of these factors are analyzed by numerical simulation. We hope the results obtained in this research will be helpful in the design of CMOS detector satellite optical communications systems.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

DTIC Science & Technology

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

NASA Astrophysics Data System (ADS)

Bourree, Loig E.

2014-05-01

Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

In-circuit-measurement of parasitic elements in high gain high bandwidth low noise transimpedance amplifiers.

PubMed

Cochems, P; Kirk, A; Zimmermann, S

2014-12-01

Parasitic elements play an important role in the development of every high performance circuit. In the case of high gain, high bandwidth transimpedance amplifiers, the most important parasitic elements are parasitic capacitances at the input and in the feedback path, which significantly influence the stability, the frequency response, and the noise of the amplifier. As these parasitic capacitances range from a few picofarads down to only a few femtofarads, it is nearly impossible to measure them accurately using traditional LCR meters. Unfortunately, they also cannot be easily determined from the transfer function of the transimpedance amplifier, as it contains several overlapping effects and its measurement is only possible when the circuit is already stable. Therefore, we developed an in-circuit measurement method utilizing minimal modifications to the input stage in order to measure its parasitic capacitances directly and with unconditional stability. Furthermore, using the data acquired with this measurement technique, we both proposed a model for the complicated frequency response of high value thick film resistors as they are used in high gain transimpedance amplifiers and optimized our transimpedance amplifier design.

Noise-figure limit of fiber-optical parametric amplifiers and wavelength converters: experimental investigation

NASA Astrophysics Data System (ADS)

Tang, Renyong; Voss, Paul L.; Lasri, Jacob; Devgan, Preetpaul; Kumar, Prem

2004-10-01

Recent theoretical work predicts that the quantum-limited noise figure of a chi(3)-based fiber-optical parametric amplifier operating as a phase-insensitive in-line amplifier or as a wavelength converter exceeds the standard 3-dB limit at high gain. The degradation of the noise figure is caused by the excess noise added by the unavoidable Raman gain and loss occurring at the signal and the converted wavelengths. We present detailed experimental evidence in support of this theory through measurements of the gain and noise-figure spectra for phase-insensitive parametric amplification and wavelength conversion in a continuous-wave amplifier made from 4.4 km of dispersion-shifted fiber. The theory is also extended to include the effect of distributed linear loss on the noise figure of such a long-length parametric amplifier and wavelength converter.

Fundamental performance differences between CMOS and CCD imagers: Part II

NASA Astrophysics Data System (ADS)

Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

2007-09-01

A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

Dedicated power supply subsystem for ultra-low noise preamplifiers and biophotonic sensors

NASA Astrophysics Data System (ADS)

SuraŻyński, Łukasz; Wierzba, Paweł; Zienkiewicz, Aleksandra

2013-11-01

It is very common for noise to have an influence on analog circuits. In order to preserve the quality of measurements taken by specific sensors and any noise dependent amplifiers which are correlated to them, all of these devices must be powered by low-noise power supplies. Therefore a necessity exists to develop new ultra-low noise power supplies which can cooperate with specified amplifiers and preamplifiers. Many well-known power supplies are particularly expensive and yet still have their disadvantages. This paper proposes a simple and inexpensive solution, which fulfills a specific criteria and can be treated as a base for improvement.

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

PubMed

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

Ultra-low-noise preamplifier for condenser microphones.

PubMed

Starecki, Tomasz

2010-12-01

The paper presents the design of a low-noise preamplifier dedicated for condenser measurement microphones used in high sensitivity applications, in which amplifier noise is the main factor limiting sensitivity of the measurements. In measurement microphone preamplifiers, the dominant source of noise at lower frequencies is the bias resistance of the input stage. In the presented solution, resistors were connected to the input stage by means of switches. The switches are opened during measurements, which disconnects the resistors from the input stage and results in noise reduction. Closing the switches allows for fast charging of the microphone capacitance. At low frequencies the noise of the designed preamplifier is a few times lower in comparison to similar, commercially available instruments.

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

Self-amplified CMOS image sensor using a current-mode readout circuit

NASA Astrophysics Data System (ADS)

Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

2014-05-01

The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

NASA Astrophysics Data System (ADS)

Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

2017-05-01

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

A Low Cost Bluetooth Low Energy Transceiver for Wireless Sensor Network Applications with a Front-end Receiver-Matching Network-Reusing Power Amplifier Load Inductor.

PubMed

Liang, Zhen; Li, Bin; Huang, Mo; Zheng, Yanqi; Ye, Hui; Xu, Ken; Deng, Fangming

2017-04-19

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX)-matching network-reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of -93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm². The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications.

Noise spectra in balanced optical detectors based on transimpedance amplifiers.

PubMed

Masalov, A V; Kuzhamuratov, A; Lvovsky, A I

2017-11-01

We present a thorough theoretical analysis and experimental study of the shot and electronic noise spectra of a balanced optical detector based on an operational amplifier connected in a transimpedance scheme. We identify and quantify the primary parameters responsible for the limitations of the circuit, in particular, the bandwidth and shot-to-electronic noise clearance. We find that the shot noise spectrum can be made consistent with the second-order Butterworth filter, while the electronic noise grows linearly with the second power of the frequency. Good agreement between the theory and experiment is observed; however, the capacitances of the operational amplifier input and the photodiodes appear significantly higher than those specified in manufacturers' datasheets. This observation is confirmed by independent tests.

Noise spectra in balanced optical detectors based on transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Masalov, A. V.; Kuzhamuratov, A.; Lvovsky, A. I.

2017-11-01

We present a thorough theoretical analysis and experimental study of the shot and electronic noise spectra of a balanced optical detector based on an operational amplifier connected in a transimpedance scheme. We identify and quantify the primary parameters responsible for the limitations of the circuit, in particular, the bandwidth and shot-to-electronic noise clearance. We find that the shot noise spectrum can be made consistent with the second-order Butterworth filter, while the electronic noise grows linearly with the second power of the frequency. Good agreement between the theory and experiment is observed; however, the capacitances of the operational amplifier input and the photodiodes appear significantly higher than those specified in manufacturers' datasheets. This observation is confirmed by independent tests.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Y.; Hu-Guo, C.; Husson, D.

2011-07-01

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial pointsmore » of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)« less

Experiments with synchronized sCMOS cameras

NASA Astrophysics Data System (ADS)

Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

2016-07-01

Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Simultaneous monitoring technique for ASE and MPI noises in distributed Raman Amplified Systems.

PubMed

Choi, H Y; Jun, S B; Shin, S K; Chung, Y C

2007-07-09

We develop a new technique for simultaneously monitoring the amplified spontaneous emission (ASE) and multi-path interference (MPI) noises in distributed Raman amplified (DRA) systems. This technique utilizes the facts that the degree-of polarization (DOP) of the MPI noise is 1/9, while the ASE noise is unpolarized. The results show that the proposed technique can accurately monitor both of these noises regardless of the bit rates, modulation formats, and optical signal-to-noise ratio (OSNR) levels of the signals.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and γ-Ray Spectrum Analyzer

NASA Astrophysics Data System (ADS)

Gan, B.; Wei, T.; Gao, W.; Zheng, R.; Hu, Y.

2015-10-01

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 mm ×4.8 mm. At room temperature, the equivalent noise level of a typical channel reaches 133 e- (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than ±2% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 1.8% at the 662-keV line of 137Cs source.

Note: Broadband low-noise photodetector for Pound-Drever-Hall laser stabilization

NASA Astrophysics Data System (ADS)

Potnis, Shreyas; Vutha, Amar C.

2016-07-01

The Pound-Drever-Hall laser stabilization technique requires a fast, low-noise photodetector. We present a simple photodetector design that uses a transformer as an intermediary between a photodiode and cascaded low-noise radio-frequency amplifiers. Our implementation using a silicon photodiode yields a detector with 50 MHz bandwidth, gain >105 V/A, and input current noise <4 pA/ √{ Hz } , allowing us to obtain shot-noise-limited performance with low optical power.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

A very low noise, high accuracy, programmable voltage source for low frequency noise measurements

NASA Astrophysics Data System (ADS)

Scandurra, Graziella; Giusi, Gino; Ciofi, Carmine

2014-04-01

In this paper an approach for designing a programmable, very low noise, high accuracy voltage source for biasing devices under test in low frequency noise measurements is proposed. The core of the system is a supercapacitor based two pole low pass filter used for filtering out the noise produced by a standard DA converter down to 100 mHz with an attenuation in excess of 40 dB. The high leakage current of the supercapacitors, however, introduces large DC errors that need to be compensated in order to obtain high accuracy as well as very low output noise. To this end, a proper circuit topology has been developed that allows to considerably reduce the effect of the supercapacitor leakage current on the DC response of the system while maintaining a very low level of output noise. With a proper design an output noise as low as the equivalent input voltage noise of the OP27 operational amplifier, used as the output buffer of the system, can be obtained with DC accuracies better that 0.05% up to the maximum output of 8 V. The expected performances of the proposed voltage source have been confirmed both by means of SPICE simulations and by means of measurements on actual prototypes. Turn on and stabilization times for the system are of the order of a few hundred seconds. These times are fully compatible with noise measurements down to 100 mHz, since measurement times of the order of several tens of minutes are required in any case in order to reduce the statistical error in the measured spectra down to an acceptable level.

A very low noise, high accuracy, programmable voltage source for low frequency noise measurements.

PubMed

Scandurra, Graziella; Giusi, Gino; Ciofi, Carmine

2014-04-01

In this paper an approach for designing a programmable, very low noise, high accuracy voltage source for biasing devices under test in low frequency noise measurements is proposed. The core of the system is a supercapacitor based two pole low pass filter used for filtering out the noise produced by a standard DA converter down to 100 mHz with an attenuation in excess of 40 dB. The high leakage current of the supercapacitors, however, introduces large DC errors that need to be compensated in order to obtain high accuracy as well as very low output noise. To this end, a proper circuit topology has been developed that allows to considerably reduce the effect of the supercapacitor leakage current on the DC response of the system while maintaining a very low level of output noise. With a proper design an output noise as low as the equivalent input voltage noise of the OP27 operational amplifier, used as the output buffer of the system, can be obtained with DC accuracies better that 0.05% up to the maximum output of 8 V. The expected performances of the proposed voltage source have been confirmed both by means of SPICE simulations and by means of measurements on actual prototypes. Turn on and stabilization times for the system are of the order of a few hundred seconds. These times are fully compatible with noise measurements down to 100 mHz, since measurement times of the order of several tens of minutes are required in any case in order to reduce the statistical error in the measured spectra down to an acceptable level.

Prospects for charge sensitive amplifiers in scaled CMOS

NASA Astrophysics Data System (ADS)

O'Connor, Paul; De Geronimo, Gianluigi

2002-03-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

Development of an ultra low noise, miniature signal conditioning device for vestibular evoked response recordings

PubMed Central

2014-01-01

Background Inner ear evoked potentials are small amplitude (<1 μVpk) signals that require a low noise signal acquisition protocol for successful extraction; an existing such technique is Electrocochleography (ECOG). A novel variant of ECOG called Electrovestibulography (EVestG) is currently investigated by our group, which captures vestibular responses to a whole body tilt. The objective is to design and implement a bio-signal amplifier optimized for ECOG and EVestG, which will be superior in noise performance compared to low noise, general purpose devices available commercially. Method A high gain configuration is required (>85 dB) for such small signal recordings; thus, background power line interference (PLI) can have adverse effects. Active electrode shielding and driven-right-leg circuitry optimized for EVestG/ECOG recordings were investigated for PLI suppression. A parallel pre-amplifier design approach was investigated to realize low voltage, and current noise figures for the bio-signal amplifier. Results In comparison to the currently used device, PLI is significantly suppressed by the designed prototype (by >20 dB in specific test scenarios), and the prototype amplifier generated noise was measured to be 4.8 nV/Hz @ 1 kHz (0.45 μVRMS with bandwidth 10 Hz-10 kHz), which is lower than the currently used device generated noise of 7.8 nV/Hz @ 1 kHz (0.76 μVRMS). A low noise (<1 nV/Hz) radio frequency interference filter was realized to minimize noise contribution from the pre-amplifier, while maintaining the required bandwidth in high impedance measurements. Validation of the prototype device was conducted for actual ECOG recordings on humans that showed an increase (p < 0.05) of ~5 dB in Signal-to-Noise ratio (SNR), and for EVestG recordings using a synthetic ear model that showed a ~4% improvement (p < 0.01) over the currently used amplifier. Conclusion This paper presents the design and evaluation of an ultra-low noise and miniaturized bio

Improved Signal Chains for Readout of CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Measurement of the photon statistics and the noise figure of a fiber-optic parametric amplifier.

PubMed

Voss, Paul L; Tang, Renyong; Kumar, Prem

2003-04-01

We report measurement of the noise statistics of spontaneous parametric fluorescence in a fiber parametric amplifier with single-mode, single-photon resolution. We employ optical homodyne tomography for this purpose, which also provides a self-calibrating measurement of the noise figure of the amplifier. The measured photon statistics agree with quantum-mechanical predictions, and the amplifier's noise figure is found to be almost quantum limited.

A high gain wide dynamic range transimpedance amplifier for optical receivers

NASA Astrophysics Data System (ADS)

Lianxi, Liu; Jiao, Zou; Yunfei, En; Shubin, Liu; Yue, Niu; Zhangming, Zhu; Yintang, Yang

2014-01-01

As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.

Coplanar monolithic integrated circuits for low-noise communication and radar systems

NASA Astrophysics Data System (ADS)

Bessemoulin, Alexandre; Verweyen, Ludger; Marsetz, Waldemar; Massler, Hermann; Neumann, Markus; Hulsmann, Axel; Schlechtweg, Michael

1999-12-01

This paper presents coplanar millimeter-wave monolithic integrated circuits with high performance and small size for use in low noise communication and radar system applications. Technology and modeling issues with respect to active and passive elements are discussed first. In a second step, the potential of coplanar waveguides to realize compact ICs is illustrated through various design examples, such as low noise amplifiers, mixers and power amplifiers. The performance of multifunctional ICs is also presented by comparing simulated and measured results for a complete 77 GHz Transceive MMIC.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

PubMed Central

Kim, Sungho; Lepkowski, William; Wilk, Seth J.; Thornton, Trevor J.; Bakkaloglu, Bertan

2014-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of −70dBm and −98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10−3 at the input powers of −70dBm at 1.2V and −98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Measurement of spectral phase noise in a cryogenically cooled Ti:Sa amplifier (Conference Presentation)

NASA Astrophysics Data System (ADS)

Nagymihaly, Roland S.; Jójárt, Péter; Börzsönyi, Ádám.; Osvay, Károly

2017-05-01

In most of cases the drift of the carrier envelope phase (CEP) of a chirped pulse amplifier (CPA) system is determined only [1], being the relevant parameter at laser-matter interactions. The need of coherent combination of multiple amplifier channels to further increase the peak power of pulses requires interferometric precision [2]. For this purpose, the stability of the group delay of the pulses may become equally important. Further development of amplifier systems requires the investigation of phase noise contributions of individual subsystems, like amplifier stages. Spectrally resolved interferometry (SRI), which is a completely linear optical method, makes the measurement of spectral phase noise possible of basically any part of a laser system [3]. By utilizing this method, the CEP stability of water-cooled Ti:Sa based amplifiers was investigated just recently, where the effects of seed and pump energy, repetition rate, and the cooling crystal mounts were thoroughly measured [4]. We present a systematic investigation on the noise of the spectral phase, including CEP, of laser pulses amplified in a cryogenically-cooled Ti:Sa amplifier of a CPA chain. The double-pass amplifier was built in the sample arm of a compact Michelson interferometer. The Ti:Sa crystal was cooled below 30 °K. The inherent phase noise was measured for different operation modes, as at various repetition rates, and pump depletion. Noise contributions of the vacuum pumps and the cryogenic refrigerator were found to be 43 and 47 mrad, respectively. We have also identified CEP noise having thermal as well as mechanical origin. Both showed a monotonically decreasing tendency towards higher repetition rates. We found that the widths of the noise distributions are getting broader towards lower repetition rates. Spectral phase noise with and without amplification was measured, and we found no significant difference in the phase noise distributions. The mechanical vibration was also measured in

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology

PubMed Central

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator’s high motion losses due to the possibility of their ‘system-on-chip’ integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design’s applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications. PMID:27391136

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

PubMed

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be

A digitally assisted, signal folding neural recording amplifier.

PubMed

Chen, Yi; Basu, Arindam; Liu, Lei; Zou, Xiaodan; Rajkumar, Ramamoorthy; Dawe, Gavin Stewart; Je, Minkyu

2014-08-01

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

Photon statistics of shot noise measured using a Josephson parametric amplifier

NASA Astrophysics Data System (ADS)

Simoneau, Jean Olivier; Virally, Stéphane; Lupien, Christian; Reulet, Bertrand

2015-03-01

Quantum measurements are very sensitive to external noise sources. Such measurements require careful amplification chain design so as not to overwhelm the signal with extraneous noise. A quantum-limited amplifier, like the Josephson parametric amplifier (paramp), is thus an ideal candidate for this purpose. We used a paramp to investigate the quantum noise of a tunnel junction. This measurement scheme allowed us to improve upon previous observations of shot noise by an order of magnitude in terms of noise temperature. With this setup, we have measured the second and fourth cumulants of current fluctuations generated by the tunnel junction within a 40 MHz bandwidth around 6 GHz. From theses measurements, we deduce the variance of the photon number fluctuations for various bias schemes of the junction. In particular, we investigate the regime where the junction emits pairs of photons.

Simulation and evaluation of phase noise for optical amplification using semiconductor optical amplifiers in DPSK applications

NASA Astrophysics Data System (ADS)

Hong, Wei; Huang, Dexiu; Zhang, Xinliang; Zhu, Guangxi

2008-01-01

A thorough simulation and evaluation of phase noise for optical amplification using semiconductor optical amplifier (SOA) is very important for predicting its performance in differential phase-shift keyed (DPSK) applications. In this paper, standard deviation and probability distribution of differential phase noise at the SOA output are obtained from the statistics of simulated differential phase noise. By using a full-wave model of SOA, the noise performance in the entire operation range can be investigated. It is shown that nonlinear phase noise substantially contributes to the total phase noise in case of a noisy signal amplified by a saturated SOA and the nonlinear contribution is larger with shorter SOA carrier lifetime. It is also shown that Gaussian distribution can be useful as a good approximation of the total differential phase noise statistics in the whole operation range. Power penalty due to differential phase noise is evaluated using a semi-analytical probability density function (PDF) of receiver noise. Obvious increase of power penalty at high signal input powers can be found for low input OSNR, which is due to both the large nonlinear differential phase noise and the dependence of BER vs. receiving power curvature on differential phase noise standard deviation.

The 30 GHz communications satellite low noise receiver

NASA Technical Reports Server (NTRS)

Steffek, L. J.; Smith, D. W.

1983-01-01

A Ka-band low noise front end in proof of concept (POC) model form for ultimate spaceborne communications receiver deployment was developed. The low noise receiver consists of a 27.5 to 30.0 GHz image enhanced mixer integrated with a 3.7 to 6.2 GHz FET low noise IF amplifier and driven by a self contained 23.8 GHz phase locked local oscillator source. The measured level of receiver performance over the 27.3 to 30.0 GHz RF/3.7 to 6.2 GHz IF band includes 5.5 to 6.5 dB (typ) SSB noise figure, 20.5 + or - 1.5 dB conversion gain and +23 dBm minimum third order two tone intermodulation output intercept point.

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

Large-area, low-noise, high-speed, photodiode-based fluorescence detectors with fast overdrive recovery

NASA Astrophysics Data System (ADS)

Bickman, S.; DeMille, D.

2005-11-01

Two large-area, low-noise, high-speed fluorescence detectors have been built. One detector consists of a photodiode with an area of 28mm×28mm and a low-noise transimpedance amplifier. This detector has a input light-equivalent spectral noise density of less than 3pW/√Hz , can recover from a large scattered light pulse within 10μs, and has a bandwidth of at least 900 kHz. The second detector consists of a 16-mm-diam avalanche photodiode and a low-noise transimpedance amplifier. This detector has an input light-equivalent spectral noise density of 0.08pW/√Hz , also can recover from a large scattered light pulse within 10μs, and has a bandwidth of 1 MHz.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Intensity and temporal noise characteristics in femtosecond optical parametric amplifiers.

PubMed

Chen, Wei; Fan, Jintao; Ge, Aichen; Song, Huanyu; Song, Youjian; Liu, Bowen; Chai, Lu; Wang, Chingyue; Hu, Minglie

2017-12-11

We characterize the relative intensity noise (RIN) and relative timing jitter (RTJ) between the signal and pump pulses of optical parametric amplifiers (OPAs) seeded by three different seed sources. Compared to a white-light continuum (WLC) seeded- and an optical parametric generator (OPG) seeded OPA, the narrowband CW seeded OPA exhibits the lowest root-mean-square (RMS) RIN and RTJ of 0.79% and 0.32 fs, respectively, integrated from 1 kHz to the Nyquist frequency of 1.25 MHz. An improved numerical model based on a forward Maxwell equation (FME) is built to investigate the transfers of the pump and seed's noise to the resulting OPAs' intensity and temporal fluctuation. Both the experimental and numerical study indicate that the low level of noise from the narrowband CW seeded OPA is attributed to the elimination of the RIN and RTJ coupled from the noise of seed source, being one of the important contributions to RIN and timing jitter in the other two OPAs. The approach to achieve lower level of noise from this CW seeded OPA by driving it close to saturation is also discussed with the same numerical model.

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Monolithic CMOS imaging x-ray spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors.

PubMed

Dutton, Neale A W; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K

2016-07-20

SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed.

Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors

PubMed Central

Dutton, Neale A. W.; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K.

2016-01-01

SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed. PMID:27447643

Large-area, low-noise, high-speed, photodiode-based fluorescence detectors with fast overdrive recovery

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bickman, S.; DeMille, D.

2005-11-15

Two large-area, low-noise, high-speed fluorescence detectors have been built. One detector consists of a photodiode with an area of 28 mmx28 mm and a low-noise transimpedance amplifier. This detector has a input light-equivalent spectral noise density of less than 3 pW/{radical}(Hz), can recover from a large scattered light pulse within 10 {mu}s, and has a bandwidth of at least 900 kHz. The second detector consists of a 16-mm-diam avalanche photodiode and a low-noise transimpedance amplifier. This detector has an input light-equivalent spectral noise density of 0.08 pW/{radical}(Hz), also can recover from a large scattered light pulse within 10 {mu}s, andmore » has a bandwidth of 1 MHz.« less

A Low Power Low Phase Noise Oscillator for MICS Transceivers

PubMed Central

Li, Dawei; Liu, Dongsheng; Kang, Chaojian; Zou, Xuecheng

2017-01-01

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm2 area. The measured phase noise is −108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage. PMID:28085107

A Low Power Low Phase Noise Oscillator for MICS Transceivers.

PubMed

Li, Dawei; Liu, Dongsheng; Kang, Chaojian; Zou, Xuecheng

2017-01-12

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm² area. The measured phase noise is -108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

SQUID amplifiers for axion search experiments

NASA Astrophysics Data System (ADS)

Matlashov, Andrei; Schmelz, Matthias; Zakosarenko, Vyacheslav; Stolz, Ronny; Semertzidis, Yannis K.

2018-04-01

In the experiments for dark-matter QCD-axion searches, very weak microwave signals from a low-temperature High-Q resonant cavity should be detected using the highest sensitivity. The best commercial low-noise cryogenic semiconductor amplifiers based on high electron mobility transistors have a lowest noise temperature above 1.0 K, even if they are cooled well below 1 K. Superconducting quantum interference devices can work as microwave amplifiers with temperature noise close to the standard quantum limit. Previous SQUID-based RF amplifiers designed for axion search experiments have a microstrip resonant input coil and are thus called micro-strip SQUID amplifiers or MSAs. Due to the resonant input coupling they usually have narrow bandwidth. In this paper we report on a SQUID-based wideband microwave amplifier fabricated using sub-micron size Josephson junctions with very low capacitance. A single amplifier can be used in a frequency range of approximately 1-5 GHz.

Method and apparatus for linear low-frequency feedback in monolithic low-noise charge amplifiers

DOEpatents

DeGeronimo, Gianluigi

2006-02-14

A charge amplifier includes an amplifier, feedback circuit, and cancellation circuit. The feedback circuit includes a capacitor, inverter, and current mirror. The capacitor is coupled across the signal amplifier, the inverter is coupled to the output of the signal amplifier, and the current mirror is coupled to the input of the signal amplifier. The cancellation circuit is coupled to the output of the signal amplifier. A method of charge amplification includes providing a signal amplifier; coupling a first capacitor across the signal amplifier; coupling an inverter to the output of the signal amplifier; coupling a current mirror to the input of the signal amplifier; and coupling a cancellation circuit to the output of the signal amplifier. A front-end system for use with radiation sensors includes a charge amplifier and a current amplifier, shaping amplifier, baseline stabilizer, discriminator, peak detector, timing detector, and logic circuit coupled to the charge amplifier.

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor.

PubMed

Lee, Jieun; Jang, Jaeman; Choi, Bongsik; Yoon, Jinsu; Kim, Jee-Yeon; Choi, Yang-Kyu; Kim, Dong Myong; Kim, Dae Hwan; Choi, Sung-Jin

2015-07-21

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 10(5) times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 10(5) with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density.

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

PubMed Central

Lee, Jieun; Jang, Jaeman; Choi, Bongsik; Yoon, Jinsu; Kim, Jee-Yeon; Choi, Yang-Kyu; Myong Kim, Dong; Hwan Kim, Dae; Choi, Sung-Jin

2015-01-01

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 105 times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 105 with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density. PMID:26197105

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

NASA Astrophysics Data System (ADS)

Arslan, Emre; Yıldız, Merih; Minaei, Shahram

2015-06-01

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push-pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

FM notch filter in front - and - behind the low noise amplifier of a Callisto Radio Spectrometer in Gauribidanur, India

NASA Astrophysics Data System (ADS)

Monstein, C.

2014-03-01

In the framework of IHY2007 a Callisto spectrometer [Benz(2004)] was installed and set into operation at the location of the solar heliograph in Gauribidanur, India. At that time the level of radio frequency interference (RFI) was amazingly low. In recent years more and more FM broadcast transmitters were installed with high power compared to the requirements of radio astronomical observations. So, the spectral observations with Callisto experienced more and more interference by these FM transmitters. Recently an FM-notch filter was installed between the low noise amplifier and Callisto, but it did not work out. The notch filter was then moved to the input of the LNA and the result was much better, as expected from theoretical concepts.

Dual-Polarized Antenna Arrays with CMOS Power Amplifiers for SiP Integration at W-Band

NASA Astrophysics Data System (ADS)

Giese, Malte; Vehring, Sönke; Böck, Georg; Jacob, Arne F.

2017-09-01

This paper presents requirements and front-end solutions for low-cost communication systems with data rates of 100 Gbit/s. Link budget analyses in different mass-market applications are conducted for that purpose. It proposes an implementation of the front-end as an active antenna array with support for beam steering and polarization multiplexing over the full W-band. The critical system components are investigated and presented. This applies to a transformer coupled power amplifier (PA) in 40 nm bulk CMOS. It shows saturated output power of more than 10 dBm and power-added-efficiency of more than 10 % over the full W-band. Furthermore, the performance of microstrip-to-waveguide transitions is shown exemplarily as an important part of the active antenna as it interfaces active circuitry and antenna in a polymer-and-metal process. The transition test design shows less than 0.9 dB insertion loss and more than 12 dB return loss for the differential transition over the full W-band.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, James H.; Lavietes, Anthony D.

1998-05-29

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, J.H.; Lavietes, A.D.

1998-05-26

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

A low power on-chip class-E power amplifier for remotely powered implantable sensor systems

NASA Astrophysics Data System (ADS)

Ture, Kerim; Kilinc, Enver G.; Dehollain, Catherine

2015-06-01

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the required high inductance values which make the on-chip integration of the power amplifier difficult. The designed power amplifier is fully integrated in the remotely powered sensor system and fabricated in 0.18 μm CMOS process. The power is transferred to the implantable sensor system at 13.56 MHz by using an inductively coupled remote powering link. The induced AC voltage on the implant coil is converted into a DC voltage by a passive full-wave rectifier. A voltage regulator is used to suppress the ripples and create a clean and stable 1.8 V supply voltage for the sensor and communication blocks. The data collected from the sensors is transmitted by on-off keying modulated low-power transmitter at 1.2 GHz frequency. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. An additional output network is used for the power amplifier which makes the integration of the power amplifier fully on-chip. The integrated power amplifier with 0.2 V supply voltage has a drain efficiency of 31.5% at -10 dBm output power for 50 Ω load. The measurement results verify the functionality of the power amplifier and the remotely powered implantable sensor system. The data communication is also verified by using a commercial 50 Ω chip antenna and has 600 kbps data rate at 1 m communication distance.

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

NASA Astrophysics Data System (ADS)

Pal, Dipankar; Goswami, Manish

2010-05-01

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ∼83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.

Precision limits of lock-in amplifiers below unity signal-to-noise ratios

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gillies, G.T.; Allison, S.W.

1986-02-01

An investigation of noise-related performance limits of commercial-grade lock-in amplifiers has been carried out. The dependence of the output measurement error on the input signal-to-noise ratio was established in each case and measurements of noise-related gain variations were made.

CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

PubMed

An Hu; Chodavarapu, Vamsy P

2010-10-01

We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

A Distributed Amplifier System for Bilayer Lipid Membrane (BLM) Arrays With Noise and Individual Offset Cancellation.

PubMed

Crescentini, Marco; Thei, Frederico; Bennati, Marco; Saha, Shimul; de Planque, Maurits R R; Morgan, Hywel; Tartagni, Marco

2015-06-01

Lipid bilayer membrane (BLM) arrays are required for high throughput analysis, for example drug screening or advanced DNA sequencing. Complex microfluidic devices are being developed but these are restricted in terms of array size and structure or have integrated electronic sensing with limited noise performance. We present a compact and scalable multichannel electrophysiology platform based on a hybrid approach that combines integrated state-of-the-art microelectronics with low-cost disposable fluidics providing a platform for high-quality parallel single ion channel recording. Specifically, we have developed a new integrated circuit amplifier based on a novel noise cancellation scheme that eliminates flicker noise derived from devices under test and amplifiers. The system is demonstrated through the simultaneous recording of ion channel activity from eight bilayer membranes. The platform is scalable and could be extended to much larger array sizes, limited only by electronic data decimation and communication capabilities.

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

Cross correlation measurement of low frequency conductivity noise

NASA Astrophysics Data System (ADS)

Jain, Aditya Kumar; Nigudkar, Himanshu; Chakraborti, Himadri; Udupa, Aditi; Gupta, Kantimay Das

2018-04-01

In order to study the low frequency noise(1/f noise)an experimental technique based on cross correlation of two channels is presented. In this method the device under test (DUT)is connected to the two independently powered preamplifiers in parallel. The amplified signals from the two preamplifiers are fed to two channels of a digitizer. Subsequent data processing largelyeliminates the uncorrelated noise of the two channels. This method is tested for various commercial carbon/metal film resistors by measuring equilibrium thermal noise (4kBTR). The method is then modified to study the non-equilibrium low frequency noise of heterostructure samples using fiveprobe configuration. Five contact probes allow two parts of the sample to become two arms of a balanced bridge. This configuration helps in suppressing the effect of power supply fluctuations, bath temperature fluctuations and contact resistances.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

The effect of pumping noise on the characteristics of a single-stage parametric amplifier

NASA Astrophysics Data System (ADS)

Medvedev, S. Iu.; Muzychuk, O. V.

1983-10-01

An analysis is made of the operation of a single-stage parametric amplifier based on a varactor with a sharp transition. Analytical expressions are obtained for the statistical moments of the output signal, the signal-noise ratio, and other characteristics in the case when the output signal and the pump are a mixture of harmonic oscillation and Gaussian noise. It is shown that, when a noise component is present in the pump, an increase of its harmonic component to values close to the threshold leads to a sharp decrease in the signal-noise ratio at the amplifier output.

High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

PubMed

Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

2012-07-30

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

Numerical investigation of differential phase noise and its power penalty for optical amplification using semiconductor optical amplifiers in DPSK applications

NASA Astrophysics Data System (ADS)

Hong, Wei; Huang, Dexiu; Zhang, Xinliang; Zhu, Guangxi

2007-11-01

A thorough simulation and evaluation of phase noise for optical amplification using semiconductor optical amplifier (SOA) is very important for predicting its performance in differential phase shift keyed (DPSK) applications. In this paper, standard deviation and probability distribution of differential phase noise are obtained from the statistics of simulated differential phase noise. By using a full-wave model of SOA, the noise performance in the entire operation range can be investigated. It is shown that nonlinear phase noise substantially contributes to the total phase noise in case of a noisy signal amplified by a saturated SOA and the nonlinear contribution is larger with shorter SOA carrier lifetime. Power penalty due to differential phase noise is evaluated using a semi-analytical probability density function (PDF) of receiver noise. Obvious increase of power penalty at high signal input powers can be found for low input OSNR, which is due to both the large nonlinear differential phase noise and the dependence of BER vs. receiving power curvature on differential phase noise standard deviation.

Analysis on frequency response of trans-impedance amplifier (TIA) for signal-to-noise ratio (SNR) enhancement in optical signal detection system using lock-in amplifier (LIA)

NASA Astrophysics Data System (ADS)

Kim, Ji-Hoon; Jeon, Su-Jin; Ji, Myung-Gi; Park, Jun-Hee; Choi, Young-Wan

2017-02-01

Lock-in amplifier (LIA) has been widely used in optical signal detection systems because it can measure small signal under high noise level. Generally, The LIA used in optical signal detection system is composed of transimpedance amplifier (TIA), phase sensitive detector (PSD) and low pass filter (LPF). But commercial LIA using LPF is affected by flicker noise. To avoid flicker noise, there is 2ω detection LIA using BPF. To improve the dynamic reserve (DR) of the 2ω LIA, the signal to noise ratio (SNR) of the TIA should be improved. According to the analysis of frequency response of the TIA, the noise gain can be minimized by proper choices of input capacitor (Ci) and feed-back network in the TIA in a specific frequency range. In this work, we have studied how the SNR of the TIA can be improved by a proper choice of frequency range. We have analyzed the way to control this frequency range through the change of passive component in the TIA. The result shows that the variance of the passive component in the TIA can change the specific frequency range where the noise gain is minimized in the uniform gain region of the TIA.

A Low-Noise, Wideband Preamplifier for a Fourier-Transform Ion Cyclotron Resonance Mass Spectrometer

PubMed Central

Mathur, Raman; Knepper, Ronald W.; O'Connor, Peter B.

2009-01-01

FTMS performance parameters such as limits of detection, dynamic range, sensitivity, and even mass accuracy and resolution can be greatly improved by enhancing its detection circuit. An extended investigation of significant design considerations for optimal signal-to-noise ratio in an FTMS detection circuit are presented. A low noise amplifier for an FTMS is developed based on the discussed design rules. The amplifier has a gain of ≈ 3500 and a bandwidth of 10 kHz - 1 MHz corresponding to m/z range of 100 Da to 10 kDa (at 7 Tesla). The performance of the amplifier was tested on a MALDI-FTMS, and has demonstrated a 25-fold reduction in noise in a mass spectrum of C60 compared to that of a commercial amplifier. PMID:18029195

An implantable integrated low-power amplifier-microelectrode array for Brain-Machine Interfaces.

PubMed

Patrick, Erin; Sankar, Viswanath; Rowe, William; Sanchez, Justin C; Nishida, Toshikazu

2010-01-01

One of the important challenges in designing Brain-Machine Interfaces (BMI) is to build implantable systems that have the ability to reliably process the activity of large ensembles of cortical neurons. In this paper, we report the design, fabrication, and testing of a polyimide-based microelectrode array integrated with a low-power amplifier as part of the Florida Wireless Integrated Recording Electrode (FWIRE) project at the University of Florida developing a fully implantable neural recording system for BMI applications. The electrode array was fabricated using planar micromachining MEMS processes and hybrid packaged with the amplifier die using a flip-chip bonding technique. The system was tested both on bench and in-vivo. Acute and chronic neural recordings were obtained from a rodent for a period of 42 days. The electrode-amplifier performance was analyzed over the chronic recording period with the observation of a noise floor of 4.5 microVrms, and an average signal-to-noise ratio of 3.8.

A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

NASA Astrophysics Data System (ADS)

Shrestha, Sumeet; Kamehama, Hiroki; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2015-08-01

This paper presents a low-noise wide-dynamic-range pixel design for a high-energy particle detector in astronomical applications. A silicon on insulator (SOI) based detector is used for the detection of wide energy range of high energy particles (mainly for X-ray). The sensor has a thin layer of SOI CMOS readout circuitry and a thick layer of high-resistivity detector vertically stacked in a single chip. Pixel circuits are divided into two parts; signal sensing circuit and event detection circuit. The event detection circuit consisting of a comparator and logic circuits which detect the incidence of high energy particle categorizes the incident photon it into two energy groups using an appropriate energy threshold and generate a two-bit code for an event and energy level. The code for energy level is then used for selection of the gain of the in-pixel amplifier for the detected signal, providing a function of high-dynamic-range signal measurement. The two-bit code for the event and energy level is scanned in the event scanning block and the signals from the hit pixels only are read out. The variable-gain in-pixel amplifier uses a continuous integrator and integration-time control for the variable gain. The proposed design allows the small signal detection and wide dynamic range due to the adaptive gain technique and capability of correlated double sampling (CDS) technique of kTC noise canceling of the charge detector.

Enhanced performance CCD output amplifier

DOEpatents

Dunham, Mark E.; Morley, David W.

1996-01-01

A low-noise FET amplifier is connected to amplify output charge from a che coupled device (CCD). The FET has its gate connected to the CCD in common source configuration for receiving the output charge signal from the CCD and output an intermediate signal at a drain of the FET. An intermediate amplifier is connected to the drain of the FET for receiving the intermediate signal and outputting a low-noise signal functionally related to the output charge signal from the CCD. The amplifier is preferably connected as a virtual ground to the FET drain. The inherent shunt capacitance of the FET is selected to be at least equal to the sum of the remaining capacitances.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Noise and frequency response of silicon photodiode operational amplifier combination.

PubMed

Hamstra, R H; Wendland, P

1972-07-01

The noise in dark and illuminated Schottky barrier and diffused PIN non-guard-ring photodiodes has been measured between 0.1 Hz and 10 kHz and compared to theory with an excellent fit. It is shown that diodes used photovoltaically are free of 1/f noise in the dark. It is also demonstrated that there is an optimum bias (ca. 100 mV) for minimum noise equivalent power. When only a resistive load is used with a detector, it often determines the frequency response and noise of the detector circuit. We develop and demonstrate equations for the major improvements in both noise and frequency response that can be obtained using a current mode (inverting) operational amplifier.

High-power all-fiber ultra-low noise laser

NASA Astrophysics Data System (ADS)

Zhao, Jian; Guiraud, Germain; Pierre, Christophe; Floissat, Florian; Casanova, Alexis; Hreibi, Ali; Chaibi, Walid; Traynor, Nicholas; Boullet, Johan; Santarelli, Giorgio

2018-06-01

High-power ultra-low noise single-mode single-frequency lasers are in great demand for interferometric metrology. Robust, compact all-fiber lasers represent one of the most promising technologies to replace the current laser sources in use based on injection-locked ring resonators or multi-stage solid-state amplifiers. Here, a linearly polarized high-power ultra-low noise all-fiber laser is demonstrated at a power level of 100 W. Special care has been taken in the study of relative intensity noise (RIN) and its reduction. Using an optimized servo actuator to directly control the driving current of the pump laser diode, we obtain a large feedback bandwidth of up to 1.3 MHz. The RIN reaches - 160 dBc/Hz between 3 and 20 kHz.

Circuit Models and Experimental Noise Measurements of Micropipette Amplifiers for Extracellular Neural Recordings from Live Animals

PubMed Central

Chen, Chang Hao; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Klug, Achim; Lei, Tim C.

2014-01-01

Glass micropipettes are widely used to record neural activity from single neurons or clusters of neurons extracellularly in live animals. However, to date, there has been no comprehensive study of noise in extracellular recordings with glass micropipettes. The purpose of this work was to assess various noise sources that affect extracellular recordings and to create model systems in which novel micropipette neural amplifier designs can be tested. An equivalent circuit of the glass micropipette and the noise model of this circuit, which accurately describe the various noise sources involved in extracellular recordings, have been developed. Measurement schemes using dead brain tissue as well as extracellular recordings from neurons in the inferior colliculus, an auditory brain nucleus of an anesthetized gerbil, were used to characterize noise performance and amplification efficacy of the proposed micropipette neural amplifier. According to our model, the major noise sources which influence the signal to noise ratio are the intrinsic noise of the neural amplifier and the thermal noise from distributed pipette resistance. These two types of noise were calculated and measured and were shown to be the dominating sources of background noise for in vivo experiments. PMID:25133158

Noise Characterization of Erbium-Doped Fiber Amplifiers and Avalanche Photodiodes in Optical Communication Systems.

NASA Astrophysics Data System (ADS)

Kahraman, Gokalp

We examine the performance of optical communication systems using erbium-doped fiber amplifiers (OFAs) and avalanche photodiodes (APDs) including nonlinear and transient effects in the former and transient effects in the latter. Transient effects become important as these amplifiers are operated at very high data rates. Nonlinear effects are important for high gain amplifiers. In most studies of noise in these devices, the temporal and nonlinear effects have been ignored. We present a quantum theory of noise in OFAs including the saturation of the atomic population inversion and the pump depletion. We study the quantum-statistical properties of pulse amplification. The generating function of the output photon number distribution (PND) is determined as a function of time during the course of the pulse with an arbitrary input PND assumed. Under stationary conditions, we determine the Kolmogorov equation obeyed by the PND. The PND at the output is determined for arbitrary input distributions. The effect of the counting time and the filter bandwidth used by the detection circuit is determined. We determine the gain, the noise figure, and the sensitivity of receivers using OFAs as preamplifiers, including the effect of backward amplified spontaneous emission (ASE). Backward ASE degrades the noise figure and the sensitivity by depleting the population inversion at the input side of the fiber and thus increasing the noise during signal amplification. We show that the sensitivity improves with the bit rate at low rates but degrades at high rates. We provide a stochastic model that describes the time dynamics in a double-carrier multiplication (DCM) APD. A discrete stochastic model for the electron/hole motion and multiplication is defined on a spatio-temporal lattice and used to derive recursive equations for the mean, the variance, and the autocorrelation of the impulse response as functions of time. The power spectral density of the photocurrent produced in response to a

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

PubMed

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

A Hybrid Semi-Digital Transimpedance Amplifier With Noise Cancellation Technique for Nanopore-Based DNA Sequencing.

PubMed

Hsu, Chung-Lun; Jiang, Haowei; Venkatesh, A G; Hall, Drew A

2015-10-01

Over the past two decades, nanopores have been a promising technology for next generation deoxyribonucleic acid (DNA) sequencing. Here, we present a hybrid semi-digital transimpedance amplifier (HSD-TIA) to sense the minute current signatures introduced by single-stranded DNA (ssDNA) translocating through a nanopore, while discharging the baseline current using a semi-digital feedback loop. The amplifier achieves fast settling by adaptively tuning a DC compensation current when a step input is detected. A noise cancellation technique reduces the total input-referred current noise caused by the parasitic input capacitance. Measurement results show the performance of the amplifier with 31.6 M Ω mid-band gain, 950 kHz bandwidth, and 8.5 fA/ √Hz input-referred current noise, a 2× noise reduction due to the noise cancellation technique. The settling response is demonstrated by observing the insertion of a protein nanopore in a lipid bilayer. Using the nanopore, the HSD-TIA was able to measure ssDNA translocation events.

Compact low-noise preamplifier for noise spectroscopy with biased photodiodes in cargo inspection systems

NASA Astrophysics Data System (ADS)

Benetti, Bob; Langeveld, Willem G. J.

2013-09-01

Noise Spectroscopy, a.k.a. Z-determination by Statistical Count-rate ANalysis (Z-SCAN), is a statistical technique to determine a quantity called the "noise figure" from digitized waveforms of pulses of transmitted x-rays in cargo inspection systems. Depending only on quantities related to the x-ray energies, it measures a characteristic of the transmitted x-ray spectrum, which depends on the atomic number, Z, of the material penetrated. The noise figure can thus be used for material separation. In an 80-detector prototype, scintillators are used with large-area photodiodes biased at 80V and digitized using 50-MSPS 12-bit ADC boards. We present an ultra-compact low-noise preamplifier design, with one high-gain and one low-gain channel per detector for improved dynamic range. To achieve adequate detection sensitivity and spatial resolution each dual-gain preamplifier channel must fit within a 12.7 mm wide circuit board footprint and maintain adequate noise immunity to conducted and radiated interference from adjacent channels. The novel design included iterative SPICE analysis of transient response, dynamic range, frequency response, and noise analysis to optimize the selection and configuration of amplifiers and filter response. We discuss low-noise active and passive components and low-noise techniques for circuit board layout that are essential to achieving the design goals, and how the completed circuit board performed in comparison to the predicted responses.

A low-noise delta-sigma phase modulator for polar transmitters.

PubMed

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μ m CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of -104 dBc/Hz and -120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

2015-04-01

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

Low-noise front-end electronics for detection of intermediate-frequency weak light signals

NASA Astrophysics Data System (ADS)

Lin, Cunbao; Yan, Shuhua; Du, Zhiguang; Wei, Chunhua; Wang, Guochao

2015-02-01

A novel low-noise front-end electronics was proposed for detection of light signals with intensity about 10 μW and frequency above 2.7 MHz. The direct current (DC) power supply, pre-amplifier and main-amplifier were first designed, simulated and then realized. Small-size components were used to make the power supply small, and the pre-amplifier and main-amplifier were the least capacitors to avoid the phase shift of the signals. The performance of the developed front-end electronics was verified in cross-grating diffraction experiments. The results indicated that the output peak-topeak noise of the +/-5 V DC power supply was about 2 mV, and the total output current was 1.25 A. The signal-to-noise ratio (SNR) of the output signal of the pre-amplifier was about 50 dB, and it increased to nearly 60 dB after the mainamplifier, which means this front-end electronics was especially suitable for using in the phase-sensitive and integrated precision measurement systems.

Saturation of the right-leg drive amplifier in low-voltage ECG monitors.

PubMed

Freeman, Daniel K; Gatzke, Ronald D; Mallas, Georgios; Chen, Yu; Brouse, Chris J

2015-01-01

Electrocardiogram (ECG) monitoring is a critical tool in patient care, but its utility is often balanced with frustration from clinicians who are constantly distracted by false alarms. This has motivated the need to readdress the major factors that contribute to ECG noise with the goal of reducing false alarms. In this study, we describe a previously unreported phenomenon in which ECG noise can result from an unintended interaction between two systems: 1) the dc lead-off circuitry that is used to detect whether electrodes fall off the patient; and 2) the right-leg drive (RLD) system that is responsible for reducing ac common-mode noise that couples into the body. Using a circuit model to study this interaction, we found that in the presence of a dc lead-off system, even moderate increases in the right-leg skin-electrode resistance can cause the RLD amplifier to saturate. Such saturation can produce ECG noise because the RLD amplifier will no longer be capable of attenuating ac common-mode noise on the body. RLD saturation is particularly a problem for modern ECG monitors that use low-voltage supply levels. For example, for a 12-lead ECG and a 2 V power supply, saturation will occur when the right-leg electrode resistance reaches only 2 MΩ. We discuss several design solutions that can be used in low-voltage monitors to avoid RLD saturation.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Wide-Temperature-Range Integrated Operational Amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

2007-01-01

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Reduced transposed flicker noise in microwave oscillators using gaas-based feedforward amplifiers.

PubMed

Everard, Jeremy K A; Broomfield, Carl D

2007-06-01

Transposed flicker noise reduction and removal is demonstrated in 7.6 GHz microwave oscillators for offsets greater than 10 kHz. This is achieved by using a GaAs-based feedforward power amplifier as the oscillation-sustaining stage and incorporating a limiter and resonator elsewhere in the loop. 20 dB noise suppression is demonstrated at 12.5 kHz offset when the error correcting amplifier is switched on. Three oscillator pairs have been built. A transmission line feedback oscillator with a Qo of 180 and two sapphire-based, dielectric resonator oscillators (DROs) with a Qo of 44,500. The difference between the two DROs is a change in the limiter threshold power level of 10 dB. The phase noise rolls-off at (1/f)(2) for offsets greater than 10 kHz for the transmission line oscillator and is set by the thermal noise to within 0-1 dB of the theoretical minimum. The noise performance of the DROs is within 6-12 dB of the theory. Possible reasons for this discrepancy are presented.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

Low-noise correlation measurements based on software-defined-radio receivers and cooled microwave amplifiers.

PubMed

Nieminen, Teemu; Lähteenmäki, Pasi; Tan, Zhenbing; Cox, Daniel; Hakonen, Pertti J

2016-11-01

We present a microwave correlation measurement system based on two low-cost USB-connected software defined radio dongles modified to operate as coherent receivers by using a common local oscillator. Existing software is used to obtain I/Q samples from both dongles simultaneously at a software tunable frequency. To achieve low noise, we introduce an easy low-noise solution for cryogenic amplification at 600-900 MHz based on single discrete HEMT with 21 dB gain and 7 K noise temperature. In addition, we discuss the quantization effects in a digital correlation measurement and determination of optimal integration time by applying Allan deviation analysis.

A low noise interface circuit design of micro-machined gyroscope

NASA Astrophysics Data System (ADS)

Fu, Qiang; Di, Xipeng; Yin, Liang; Liu, Xiaowei

2017-07-01

The analyses of MEMS gyroscope interface circuit on thermal noise, 1/f noise and phase noise are made in this paper. A closed-loop differential driving circuit and a low-noise differential detecting circuit based on the high frequency modulation are designed to limit the noise. The interface chip is implemented in a standard 0.5 μm CMOS process. The test results show that the resolution of sensitive capacity can reach to 6.47 × 10-20 F at the bandwidth of 60 Hz. The measuring range is ± 200°/s and the nonlinearity is 310 ppm. The output noise density is 5.8^\\circ/({{h}}\\cdot \\sqrt{{Hz}}). The angular random walk (allen-variance) is 0.092^\\circ/\\sqrt{{{h}}} and the bias instability is 2.63°/h. Project supported by the National Natural Science Foundation of China (No. 61204121), the National Hi-Tech Research and Development Program of China (No. 2013AA041107), and the Fundamental Research Funds for the Central Universities (No. HIT.NSRIF.2013040).

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Measurements of the Low Frequency Gain Fluctuations of a 30 GHz High-Electron-Mobility-Transistor Cryogenic Amplifier

NASA Technical Reports Server (NTRS)

Jarosik, Norman

1994-01-01

Low frequency gain fluctuations of a 30 GHz cryogenic HEMT amplifier have been measured with the input of the amplifier connected to a 15 K load. Effects of fluctuations of other components of the test set-up were eliminated by use of a power-power correlation technique. Strong correlation between output power fluctuations of the amplifier and drain current fluctuations of the transistors comprising the amplifier are observed. The existence of these correlations introduces the possibility of regressing some of the excess noise from the HEMT amplifier's output using the measured drain currents.

Noise-driven neuromorphic tuned amplifier.

PubMed

Fanelli, Duccio; Ginelli, Francesco; Livi, Roberto; Zagli, Niccoló; Zankoc, Clement

2017-12-01

We study a simple stochastic model of neuronal excitatory and inhibitory interactions. The model is defined on a directed lattice and internodes couplings are modulated by a nonlinear function that mimics the process of synaptic activation. We prove that such a system behaves as a fully tunable amplifier: the endogenous component of noise, stemming from finite size effects, seeds a coherent (exponential) amplification across the chain generating giant oscillations with tunable frequencies, a process that the brain could exploit to enhance, and eventually encode, different signals. On a wider perspective, the characterized amplification process could provide a reliable pacemaking mechanism for biological systems. The device extracts energy from the finite size bath and operates as an out of equilibrium thermal machine, under stationary conditions.

Single-Event Effects in High-Frequency Linear Amplifiers: Experiment and Analysis

NASA Astrophysics Data System (ADS)

Zeinolabedinzadeh, Saeed; Ying, Hanbin; Fleetwood, Zachary E.; Roche, Nicolas J.-H.; Khachatrian, Ani; McMorrow, Dale; Buchner, Stephen P.; Warner, Jeffrey H.; Paki-Amouzou, Pauline; Cressler, John D.

2017-01-01

The single-event transient (SET) response of two different silicon-germanium (SiGe) X-band (8-12 GHz) low noise amplifier (LNA) topologies is fully investigated in this paper. The two LNAs were designed and implemented in 130nm SiGe HBT BiCMOS process technology. Two-photon absorption (TPA) laser pulses were utilized to induce transients within various devices in these LNAs. Impulse response theory is identified as a useful tool for predicting the settling behavior of the LNAs subjected to heavy ion strikes. Comprehensive device and circuit level modeling and simulations were performed to accurately simulate the behavior of the circuits under ion strikes. The simulations agree well with TPA measurements. The simulation, modeling and analysis presented in this paper can be applied for any other circuit topologies for SET modeling and prediction.

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

PubMed Central

Zhou, Bo

2014-01-01

A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively. PMID:24719578

Computer-Aided Design of Low-Noise Microwave Circuits

NASA Astrophysics Data System (ADS)

Wedge, Scott William

1991-02-01

Devoid of most natural and manmade noise, microwave frequencies have detection sensitivities limited by internally generated receiver noise. Low-noise amplifiers are therefore critical components in radio astronomical antennas, communications links, radar systems, and even home satellite dishes. A general technique to accurately predict the noise performance of microwave circuits has been lacking. Current noise analysis methods have been limited to specific circuit topologies or neglect correlation, a strong effect in microwave devices. Presented here are generalized methods, developed for computer-aided design implementation, for the analysis of linear noisy microwave circuits comprised of arbitrarily interconnected components. Included are descriptions of efficient algorithms for the simultaneous analysis of noisy and deterministic circuit parameters based on a wave variable approach. The methods are therefore particularly suited to microwave and millimeter-wave circuits. Noise contributions from lossy passive components and active components with electronic noise are considered. Also presented is a new technique for the measurement of device noise characteristics that offers several advantages over current measurement methods.

Hybrid matrix amplifier

DOEpatents

Martens, J.S.; Hietala, V.M.; Plut, T.A.

1995-01-03

The present invention comprises a novel matrix amplifier. The matrix amplifier includes an active superconducting power divider (ASPD) having N output ports; N distributed amplifiers each operatively connected to one of the N output ports of the ASPD; and a power combiner having N input ports each operatively connected to one of the N distributed amplifiers. The distributed amplifier can included M stages of amplification by cascading superconducting active devices. The power combiner can include N active elements. The resulting (N[times]M) matrix amplifier can produce signals of high output power, large bandwidth, and low noise. 6 figures.

Hybrid matrix amplifier

DOEpatents

Martens, Jon S.; Hietala, Vincent M.; Plut, Thomas A.

1995-01-01

The present invention comprises a novel matrix amplifier. The matrix amplifier includes an active superconducting power divider (ASPD) having N output ports; N distributed amplifiers each operatively connected to one of the N output ports of the ASPD; and a power combiner having N input ports each operatively connected to one of the N distributed amplifiers. The distributed amplifier can included M stages of amplification by cascading superconducting active devices. The power combiner can include N active elements. The resulting (N.times.M) matrix amplifier can produce signals of high output power, large bandwidth, and low noise.

A low-noise 15-μm pixel-pitch 640×512 hybrid InGaAs image sensor for night vision

NASA Astrophysics Data System (ADS)

Guellec, Fabrice; Dubois, Sébastien; de Borniol, Eric; Castelein, Pierre; Martin, Sébastien; Guiguet, Romain; Tchagaspanian, Micha"l.; Rouvié, Anne; Bois, Philippe

2012-03-01

Hybrid InGaAs focal plane arrays are very interesting for night vision because they can benefit from the nightglow emission in the Short Wave Infrared band. Through a collaboration between III-V Lab and CEA-Léti, a 640x512 InGaAs image sensor with 15μm pixel pitch has been developed. The good crystalline quality of the InGaAs detectors opens the door to low dark current (around 20nA/cm2 at room temperature and -0.1V bias) as required for low light level imaging. In addition, the InP substrate can be removed to extend the detection range towards the visible spectrum. A custom readout IC (ROIC) has been designed in a standard CMOS 0.18μm technology. The pixel circuit is based on a capacitive transimpedance amplifier (CTIA) with two selectable charge-to-voltage conversion gains. Relying on a thorough noise analysis, this input stage has been optimized to deliver low-noise performance in high-gain mode with a reasonable concession on dynamic range. The exposure time can be maximized up to the frame period thanks to a rolling shutter approach. The frame rate can be up to 120fps or 60fps if the Correlated Double Sampling (CDS) capability of the circuit is enabled. The first results show that the CDS is effective at removing the very low frequency noise present on the reference voltage in our test setup. In this way, the measured total dark noise is around 90 electrons in high-gain mode for 8.3ms exposure time. It is mainly dominated by the dark shot noise for a detector temperature settling around 30°C when not cooled. The readout noise measured with shorter exposure time is around 30 electrons for a dynamic range of 71dB in high-gain mode and 108 electrons for 79dB in low-gain mode.

CMOS VLSI Active-Pixel Sensor for Tracking

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

PubMed

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel

PubMed Central

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel. PMID:23112588

Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

PubMed

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-10-16

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

Using Polynomials to Simplify Fixed Pattern Noise and Photometric Correction of Logarithmic CMOS Image Sensors

PubMed Central

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-01-01

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. PMID:26501287

A Low Power 2.4 GHz CMOS Mixer Using Forward Body Bias Technique for Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Yin, C. J.; Murad, S. A. Z.; Harun, A.; Ramli, M. M.; Zulkifli, T. Z. A.; Karim, J.

2018-03-01

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

Fast and Precise Emulation of Stochastic Biochemical Reaction Networks With Amplified Thermal Noise in Silicon Chips.

PubMed

Kim, Jaewook; Woo, Sung Sik; Sarpeshkar, Rahul

2018-04-01

The analysis and simulation of complex interacting biochemical reaction pathways in cells is important in all of systems biology and medicine. Yet, the dynamics of even a modest number of noisy or stochastic coupled biochemical reactions is extremely time consuming to simulate. In large part, this is because of the expensive cost of random number and Poisson process generation and the presence of stiff, coupled, nonlinear differential equations. Here, we demonstrate that we can amplify inherent thermal noise in chips to emulate randomness physically, thus alleviating these costs significantly. Concurrently, molecular flux in thermodynamic biochemical reactions maps to thermodynamic electronic current in a transistor such that stiff nonlinear biochemical differential equations are emulated exactly in compact, digitally programmable, highly parallel analog "cytomorphic" transistor circuits. For even small-scale systems involving just 80 stochastic reactions, our 0.35-μm BiCMOS chips yield a 311× speedup in the simulation time of Gillespie's stochastic algorithm over COPASI, a fast biochemical-reaction software simulator that is widely used in computational biology; they yield a 15 500× speedup over equivalent MATLAB stochastic simulations. The chip emulation results are consistent with these software simulations over a large range of signal-to-noise ratios. Most importantly, our physical emulation of Poisson chemical dynamics does not involve any inherently sequential processes and updates such that, unlike prior exact simulation approaches, they are parallelizable, asynchronous, and enable even more speedup for larger-size networks.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

NASA Astrophysics Data System (ADS)

Paik, Daehwa; Miyahara, Masaya; Matsuzawa, Akira

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

NASA Technical Reports Server (NTRS)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

2016-06-01

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

Low noise WDR ROIC for InGaAs SWIR image sensor

NASA Astrophysics Data System (ADS)

Ni, Yang

2017-11-01

Hybridized image sensors are actually the only solution for image sensing beyond the spectral response of silicon devices. By hybridization, we can combine the best sensing material and photo-detector design with high performance CMOS readout circuitry. In the infrared band, we are facing typically 2 configurations: high background situation and low background situation. The performance of high background sensors are conditioned mainly by the integration capacity in each pixel which is the case for mid-wave and long-wave infrared detectors. For low background situation, the detector's performance is mainly limited by the pixel's noise performance which is conditioned by dark signal and readout noise. In the case of reflection based imaging condition, the pixel's dynamic range is also an important parameter. This is the case for SWIR band imaging. We are particularly interested by InGaAs based SWIR image sensors.

Noise thermometry at ultra-low temperatures.

PubMed

Rothfuss, D; Reiser, A; Fleischmann, A; Enss, C

2016-03-28

The options for primary thermometry at ultra-low temperatures are rather limited. In practice, most laboratories are using (195)Pt NMR thermometers in the microkelvin range. In recent years, current sensing direct current superconducting quantum interference devices (DC-SQUIDs) have enabled the use of noise thermometry in this temperature range. Such devices have also demonstrated the potential for primary thermometry. One major advantage of noise thermometry is the fact that no driving current is needed to operate the device and thus the heat dissipation within the thermometer can be reduced to a minimum. Ultimately, the intrinsic power dissipation is given by the negligible back action of the readout SQUID. For thermometry in low-temperature experiments, current noise thermometers and magnetic flux fluctuation thermometers have proved to be most suitable. To make use of such thermometers at ultra-low temperatures, we have developed a cross-correlation technique that reduces the amplifier noise contribution to a negligible value. For this, the magnetic flux fluctuations caused by the Brownian motion of the electrons in our noise source are measured inductively by two DC-SQUID magnetometers simultaneously and the signals from these two channels are cross-correlated. Experimentally, we have characterized a thermometer made of a cold-worked high-purity copper cylinder with a diameter of 5 mm and a length of 20 mm for temperatures between 42 μK and 0.8 K. For a given temperature, a measuring time below 1 min is sufficient to reach a precision of better than 1%. The extremely low power dissipation in the thermometer allows continuous operation without heating effects. © 2016 The Author(s).

Analysis and Enhancement of Low-Light-Level Performance of Photodiode-Type CMOS Active Pixel Images Operated with Sub-Threshold Reset

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Yang, Guang; Ortiz, Monico; Wrigley, Christopher; Hancock, Bruce; Cunningham, Thomas

2000-01-01

Noise in photodiode-type CMOS active pixel sensors (APS) is primarily due to the reset (kTC) noise at the sense node, since it is difficult to implement in-pixel correlated double sampling for a 2-D array. Signal integrated on the photodiode sense node (SENSE) is calculated by measuring difference between the voltage on the column bus (COL) - before and after the reset (RST) is pulsed. Lower than kTC noise can be achieved with photodiode-type pixels by employing "softreset" technique. Soft-reset refers to resetting with both drain and gate of the n-channel reset transistor kept at the same potential, causing the sense node to be reset using sub-threshold MOSFET current. However, lowering of noise is achieved only at the expense higher image lag and low-light-level non-linearity. In this paper, we present an analysis to explain the noise behavior, show evidence of degraded performance under low-light levels, and describe new pixels that eliminate non-linearity and lag without compromising noise.

Integrated-circuit balanced parametric amplifier

NASA Technical Reports Server (NTRS)

Dickens, L. E.

1975-01-01

Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost.

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Radiation Performance of Commercial SiGe HBT BiCMOS-High Speed Operational Amplifiers

NASA Technical Reports Server (NTRS)

Chen, Dakai; Pellish, Jonathan; Phan, Anthony; Kim, Hak; Burns, Sam; Albarian, Rafi; Holcombe, Bruce; Little, Bradley; Salzman, James; LaBel, Kenneth

2010-01-01

We present results on heavy-ion and proton irradiations for commercial SiGe BiCMOS operational amplifiers: LTC6400-20 from Linear Technology and THS4304 from Texas Instruments. We found that the devices are susceptible to heavy-ion-induced SETs. The SET cross-sections increase with increasing operating frequency. The LTC6400 exhibits a LET(sub th) < 7.4 MeV·sq cm/mg for frequencies ranging from 10 to 1000 MHz. The THS4304 exhibits a LET(sub th) < 4.4 MeV·sq cm/mg at 200 MHz; the LET(sub th) decreases with increasing frequency. The significance of the SETs also increases with frequency. The SETs at 1000 MHz can erase several signal cycles. We al.so found that the LTC6400 is relatively robust against 198 and 54 MeV protons. We did not observe angular sensitivity from the proton irradiations.

A low-power CMOS readout IC design for bolometer applications

NASA Astrophysics Data System (ADS)

Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

2017-02-01

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

Shot noise limit of chemically amplified resists with photodecomposable quenchers used for extreme ultraviolet lithography

NASA Astrophysics Data System (ADS)

Kozawa, Takahiro; Santillan, Julius Joseph; Itani, Toshiro

2017-06-01

In lithography using high-energy photons such as an extreme ultraviolet (EUV) radiation, the shot noise of photons is a critical issue. The shot noise is a cause of line edge/width roughness (LER/LWR) and stochastic defect generation and limits the resist performance. In this study, the effects of photodecomposable quenchers were investigated from the viewpoint of the shot noise limit. The latent images of line-and-space patterns with 11 nm half-pitch were calculated using a Monte Carlo method. In the simulation, the effect of secondary electron blur was eliminated to clarify the shot noise limits regarding stochastic phenomena such as LER. The shot noise limit for chemically amplified resists with acid generators and photodecomposable quenchers was approximately the same as that for chemically amplified resists with acid generators and conventional quenchers when the total sensitizer concentration was the same. The effect of photodecomposable quenchers on the shot noise limit was essentially the same as that of acid generators.

A low-cost, ultra-fast and ultra-low noise preamplifier for silicon avalanche photodiodes

NASA Astrophysics Data System (ADS)

Gasmi, Khaled

2018-02-01

An ultra-fast and ultra-low noise preamplifier for amplifying the fast and weak electrical signals generated by silicon avalanche photodiodes has been designed and developed. It is characterized by its simplicity, compactness, reliability and low cost of construction. A very wide bandwidth of 300 MHz, a very good linearity from 1 kHz to 280 MHz, an ultra-low noise level at the input of only 1.7 nV Hz-1/2 and a very good stability are its key features. The compact size (70 mm  ×  90 mm) and light weight (45 g), as well as its excellent characteristics, make this preamplifier very competitive compared to any commercial preamplifier. The preamplifier, which is a main part of the detection system of a homemade laser remote sensing system, has been successfully tested. In addition, it is versatile and can be used in any optical detection system requiring high speed and very low noise electronics.

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

Low noise charge ramp electrometer

DOEpatents

Morgan, John P.; Piper, Thomas C.

1992-01-01

An electrometer capable of measuring small currents without the use of a feedback resistor which tends to contribute a large noise factor to the measured data. The electrometer eliminates the feedback resistor through the use of a feedback capacitor located across the electrometer amplifier. The signal from the electrometer amplifier is transferred to a electrometer buffer amplifier which serves to transfer the signal to several receptors. If the electrometer amplifier is approaching saturation, the buffer amplifier signals a reset discriminator which energizes a coil whose magnetic field closes a magnetic relay switch which in turn resets or zeros the feedback capacitor. In turn, a reset complete discriminator restarts the measurement process when the electrometer amplifier approaches its initial condition. The buffer amplifier also transmits the voltage signal from the electrometer amplifier to a voltage-to-frequency converter. The signals from the voltage-to-frequency converter are counted over a fixed period of time and the information is relayed to a data processor. The timing and sequencing of the small current measuring system is under the control of a sequence control logic unit.

Advanced Concepts in Josephson Junction Reflection Amplifiers

NASA Astrophysics Data System (ADS)

Lähteenmäki, Pasi; Vesterinen, Visa; Hassel, Juha; Paraoanu, G. S.; Seppä, Heikki; Hakonen, Pertti

2014-06-01

Low-noise amplification at microwave frequencies has become increasingly important for the research related to superconducting qubits and nanoelectromechanical systems. The fundamental limit of added noise by a phase-preserving amplifier is the standard quantum limit, often expressed as noise temperature . Towards the goal of the quantum limit, we have developed an amplifier based on intrinsic negative resistance of a selectively damped Josephson junction. Here we present measurement results on previously proposed wide-band microwave amplification and discuss the challenges for improvements on the existing designs. We have also studied flux-pumped metamaterial-based parametric amplifiers, whose operating frequency can be widely tuned by external DC-flux, and demonstrate operation at pumping, in contrast to the typical metamaterial amplifiers pumped via signal lines at.

Intensity noise reduction of a high-power nonlinear femtosecond fiber amplifier based on spectral-breathing self-similar parabolic pulse evolution

NASA Astrophysics Data System (ADS)

Wang, Sijia; Liu, Bowen; Song, Youjian; Hu, Minglie

2016-04-01

We report on a simple passive scheme to reduce the intensity noise of high-power nonlinear fiber amplifiers by use of the spectral-breathing parabolic evolution of the pulse amplification with an optimized negative initial chirp. In this way, the influences of amplified spontaneous emission (ASE) on the amplifier intensity noise can be efficiently suppressed, owing to the lower overall pulse chirp, shorter spectral broadening distance, as well as the asymptotic attractive nature of self-similar pulse amplification. Systematic characterizations of the relative intensity noise (RIN) of a free-running nonlinear Yb-doped fiber amplifier are performed over a series of initial pulse parameters. Experiments show that the measured amplifier RIN increases respect to the decreased input pulse energy, due to the increased amount of ASE noise. For pulse amplification with a proper negative initial chirp, the increase of RIN is found to be smaller than with a positive initial chirp, confirming the ASE noise tolerance of the proposed spectral-breathing parabolic amplification scheme. At the maximum output average power of 27W (25-dB amplification gain), the incorporation of an optimum negative initial chirp (-0.84 chirp parameter) leads to a considerable amplifier root-mean-square (rms) RIN reduction of ~20.5% (integrated from 10 Hz to 10 MHz Fourier frequency). The minimum amplifier rms RIN of 0.025% (integrated from 1 kHz to 5 MHz Fourier frequency) is obtained along with the transform-limited compressed pulse duration of 55fs. To our knowledge, the demonstrated intensity noise performance is the lowest RIN level measured from highpower free-running femtosecond fiber amplifiers.

Low-frequency noise measurements: applications, methodologies and instrumentation

NASA Astrophysics Data System (ADS)

Ciofi, Carmine; Neri, Bruno

2003-05-01

Low frequency noise measurements (f<10Hz) are a powerful tool for the investigation of the quality and reliability of electron devices and material. In most cases, however, the application of this technique is made quite difficult both because of the effect of external interferences (temperature fluctuations, EMI, mechanical vibrations, etc.) and because of the high level of flicker noise of the commercial instrumentation. In this paper the most remarkable results we obtained by using low frequency noise measurements for the characterization of the reliability of VLSI metallic interconnections and thin oxides are resumed. Moreover, we discuss the effects of the several sources of noise and interferences which contribute to reduce the sensitivity of the measurement chain. In particular, we demonstrate that by means of a proper design, dedicated instrumentation can be built which allows for a considerable reduction of the overall background noise. Examples will be given with reference to voltage and transresistance amplifiers (both AC and DC coupled), to programmable biasing systems (both current and voltage sources), to thermal stabilization systems and to data acquisition systems. Finally, we will discuss methods which may allow, in proper conditions, to accurately measure noise levels well below the background noise of the input preamplifiers coupled to the device under test. As the systems we discuss are characterized by moderate complexity and employ components readily available on the market, we trust that this paper may also serve as a simple guideline to anyone interested in exploiting the possibility of using very low frequency noise measurements by building his own instrumentation.

Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

NASA Astrophysics Data System (ADS)

Ying, Yutong; Lin, Fujiang; Bai, Xuefei

2018-03-01

This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology, including a transmitter, receiver, and fractional synthesizer. The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology, which are energy- and hardware-efficient, to enhance the data rate for a given spectrum. A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption. For the receiver, a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied. The LNA adopts a CCC boost common-gate amplifier as the input stage, and its current is reused for the second stage to save power. The mixer uses a shared amplification stage for the following passive IQ mixer. Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design. The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver, respectively. The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz. Project supported by the National Science and Technology Major Project of China (No. 2011ZX03004-002-01).

The Speedster-EXD- A New Event-Driven Hybrid CMOS X-ray Detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2016-01-01

The Speedster-EXD is a new 64×64 pixel, 40-μm pixel pitch, 100-μm depletion depth hybrid CMOS x-ray detector with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain capacitive transimpedance amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel correlated double sampling subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5%) at 5.89 keV and 172 eV (10.0%) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25%±0.2% (i.e., consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80%±0.03%, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

Noise temperature and noise figure concepts: DC to light

NASA Technical Reports Server (NTRS)

Stelzried, C. T.

1982-01-01

The Deep Space Network is investigating the use of higher operational frequencies for improved performance. Noise temperature and noise figure concepts are used to describe the noise performance of these receiving systems. It is proposed to modify present noise temperature definitions for linear amplifiers so they will be valid over the range (hf/kT) 1 (hf/kT). This is important for systems operating at high frequencies and low noise temperatures, or systems requiring very accurate calibrations. The suggested definitions are such that for an ideal amplifier, T sub e = (hg/k) = T sub q and F = 1. These definitions revert to the present definition for (hf/kT) 1. Noise temperature calibrations are illustrated with a detailed example. These concepts are applied to system signal-to-noise analysis. The fundamental limit to a receiving system sensitivity is determined by the thermal noise of the source and the quantum noise limit of the receiver. The sensitivity of a receiving system consisting of an ideal linear amplifier with a 2.7 K source, degrades significantly at higher frequencies.

Low noise charge ramp electrometer

DOEpatents

Morgan, J.P.; Piper, T.C.

1992-10-06

An electrometer capable of measuring small currents without the use of a feedback resistor which tends to contribute a large noise factor to the measured data. The electrometer eliminates the feedback resistor through the use of a feedback capacitor located across the electrometer amplifier. The signal from the electrometer amplifier is transferred to a electrometer buffer amplifier which serves to transfer the signal to several receptors. If the electrometer amplifier is approaching saturation, the buffer amplifier signals a reset discriminator which energizes a coil whose magnetic field closes a magnetic relay switch which in turn resets or zeros the feedback capacitor. In turn, a reset complete discriminator restarts the measurement process when the electrometer amplifier approaches its initial condition. The buffer amplifier also transmits the voltage signal from the electrometer amplifier to a voltage-to-frequency converter. The signals from the voltage-to-frequency converter are counted over a fixed period of time and the information is relayed to a data processor. The timing and sequencing of the small current measuring system is under the control of a sequence control logic unit. 2 figs.

Cryogenetically Cooled Field Effect Transistors for Low-Noise Systems

NASA Technical Reports Server (NTRS)

Wollack, Edward J.; Rabin, Douglas M. (Technical Monitor)

2002-01-01

Recent tends in the design, fabrication and use of High-Electron-Mobility-Transistors (HEMT) in low noise amplifiers are reviewed. Systems employing these devices have achieved the lowest system noise for wavelengths greater than three millimeters with relatively modest cryogenic cooling requirements in a variety of ground and space based applications. System requirements which arise in employing such devices in imaging applications are contrasted with other leading coherent detector candidates at microwave wavelengths. Fundamental and practical limitations which arise in the context of microwave application of field effect devices at cryogenic temperatures will be discussed from a component and systems point of view.

Cryogenically Cooled Field Effect Transistors for Low-Noise Systems

NASA Technical Reports Server (NTRS)

Wollack, Edward J.

2002-01-01

Recent tends in the design, fabrication and use of High-Electron-Mobility-Transistors (HEMT) in low noise amplifiers are reviewed. Systems employing these devices have achieved the lowest system noise for wavelengths greater than three millimeters with relatively modest cryogenic cooling requirements in a variety of ground and space based applications. System requirements which arise in employing such devices in imaging applications are contrasted with other leading coherent detector candidates at microwave wavelengths. Fundamental and practical limitations which arise in the context of microwave application of field effect devices at cryogenic temperatures will be discussed from a component and systems point of view.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

NASA Astrophysics Data System (ADS)

Gómez-Galán, J. A.; Sánchez-Rodríguez, T.; Sánchez-Raya, M.; Martel, I.; López-Martín, A.; Carvajal, R. G.; Ramírez-Angulo, J.

2014-06-01

This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

A 1V low power second-order delta-sigma modulator for biomedical signal application.

PubMed

Hsu, Chih-Han; Tang, Kea-Tiong

2013-01-01

This paper presents the design and implementation of a low-power delta-sigma modulator for biomedical application with a standard 90 nm CMOS technology. The delta-sigma architecture is implemented as 2nd order feedforward architecture. A low quiescent current operational transconductance amplifier (OTA) is utilized to reduce power consumption. This delta-sigma modulator operated in 1V power supply, and achieved 64.87 dB signal to noise distortion ratio (SNDR) at 10 KHz bandwidth with an oversampling ratio (OSR) of 64. The power consumption is 17.14 µW, and the figure-of-merit (FOM) is 0.60 pJ/conv.

An Integrated Low-Power Lock-In Amplifier and Its Application to Gas Detection

PubMed Central

Maya-Hernández, Paulina M.; Álvarez-Simón, Luis C.; Sanz-Pascual, María Teresa; Calvo-López, Belén

2014-01-01

This paper presents a new micropower analog lock-in amplifier (LIA) suitable for battery-operated applications thanks to its reduced size and power consumption as well as its operation with single-supply voltage. The proposed LIA was designed in a 0.18 μm CMOS process with a single supply voltage of 1.8 V. Experimental results show a variable DC gain ranging from 24.7 to 42 dB, power consumption of 417 μW and integration area of 0.013 mm2. The LIA performance was demonstrated by measuring carbon monoxide concentrations as low as 1 ppm in dry N2. The experimental results show that the response to CO of the sensing system can be considerably improved by means of the proposed LIA. PMID:25166501

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Affordable Wide-field Optical Space Surveillance using sCMOS and GPUs

NASA Astrophysics Data System (ADS)

Zimmer, P.; McGraw, J.; Ackermann, M.

2016-09-01

Recent improvements in sCMOS technology allow for affordable, wide-field, and rapid cadence surveillance from LEO to out past GEO using largely off-the-shelf hardware. sCMOS sensors, until very recently, suffered from several shortcomings when compared to CCD sensors - lower sensitivity, smaller physical size and less predictable noise characteristics. Sensors that overcome the first two of these are now available commercially and the principals at J.T. McGraw and Associates (JTMA) have developed observing strategies that minimize the impact of the third, while leveraging the key features of sCMOS, fast readout and low average readout noise. JTMA has integrated a new generation sCMOS sensor into an existing COTS telescope system in order to develop and test new detection techniques designed for uncued optical surveillance across a wide range of apparent object angular rates - from degree per second scale of LEO objects to a few arcseconds per second for objects out past GEO. One further complication arises from this: increased useful frame rate means increased data volume. Fortunately, GPU technology continues to advance at a breakneck pace and we report on the results and performance of our new detection techniques implemented on new generation GPUs. Early results show significance within 20% of the expected theoretical limiting signal-to-noise using commodity GPUs in near real time across a wide range of object parameters, closing the gap in detectivity between moving objects and tracked objects.

On-Chip Integrated Distributed Amplifier and Antenna Systems in SiGe BiCMOS for Transceivers with Ultra-Large Bandwidth

NASA Astrophysics Data System (ADS)

Valerio Testa, Paolo; Klein, Bernhard; Hahnel, Ronny; Plettemeier, Dirk; Carta, Corrado; Ellinger, Frank

2017-09-01

This paper presents an overview of the research work currently being performed within the frame of project DAAB and its successor DAAB-TX towards the integration of ultra-wideband transceivers operating at mm-wave frequencies and capable of data rates up to 100 Gbits-1. Two basic system architectures are being considered: integrating a broadband antenna with a distributed amplifier and integrate antennas centered at adjacent frequencies with broadband active combiners or dividers. The paper discusses in detail the design of such systems and their components, from the distributed amplifiers and combiners, to the broadband silicon antennas and their single-chip integration. All components are designed for fabrication in a commercially available SiGe:C BiCMOS technology. The presented results represent the state of the art in their respective areas: 170 GHz is the highest reported bandwidth for distributed amplifiers integrated in Silicon; 89 GHz is the widest reported bandwidth for integrated-system antennas; the simulated performance of the two antenna integrated receiver spans 105 GHz centered at 148GHz, which would improve the state of the art by a factor in excess of 4 even against III-V implementations, if confirmed by measurements.

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gan, Bo; Wei, Tingcun; Gao, Wu

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of themore » whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for

High dynamic range CMOS-based mammography detector for FFDM and DBT

NASA Astrophysics Data System (ADS)

Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

2016-03-01

Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Note: Expanding the bandwidth of the ultra-low current amplifier using an artificial negative capacitor.

PubMed

Xie, Kai; Liu, Yan; Li, XiaoPing; Guo, Lixin; Zhang, Hanlu

2016-04-01

The bandwidth and low noise characteristics are often contradictory in ultra-low current amplifier, because an inevitable parasitic capacitance is paralleled with the high value feedback resistor. In order to expand the amplifier's bandwidth, a novel approach was proposed by introducing an artificial negative capacitor to cancel the parasitic capacitance. The theory of the negative capacitance and the performance of the improved amplifier circuit with the negative capacitor are presented in this manuscript. The test was conducted by modifying an ultra-low current amplifier with a trans-impedance gain of 50 GΩ. The results show that the maximum bandwidth was expanded from 18.7 Hz to 3.3 kHz with more than 150 times of increase when the parasitic capacitance (∼0.17 pF) was cancelled. Meanwhile, the rise time decreased from 18.7 ms to 0.26 ms with no overshot. Any desired bandwidth or rise time within these ranges can be obtained by adjusting the ratio of cancellation of the parasitic and negative capacitance. This approach is especially suitable for the demand of rapid response to weak current, such as transient ion-beam detector, mass spectrometry analysis, and fast scanning microscope.

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

PubMed

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

NASA Astrophysics Data System (ADS)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

Non-Gaussian statistics of soliton timing jitter induced by amplifier noise.

PubMed

Ho, Keang-Po

2003-11-15

Based on first-order perturbation theory of the soliton, the Gordon-Haus timing jitter induced by amplifier noise is found to be non-Gaussian distributed. Both frequency and timing jitter have larger tail probabilities than Gaussian distribution given by the linearized perturbation theory. The timing jitter has a larger discrepancy from Gaussian distribution than does the frequency jitter.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

NASA Astrophysics Data System (ADS)

Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

2017-01-01

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Low light CMOS contact imager with an integrated poly-acrylic emission filter for fluorescence detection.

PubMed

Dattner, Yonathan; Yadid-Pecht, Orly

2010-01-01

This study presents the fabrication of a low cost poly-acrylic acid (PAA) based emission filter integrated with a low light CMOS contact imager for fluorescence detection. The process involves the use of PAA as an adhesive for the emission filter. The poly-acrylic solution was chosen due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment. The emission filter, also known as an absorption filter, involves dissolving an absorbing specimen in a polar protic solvent and mixing it with the PAA to uniformly bond the absorbing specimen and harden the filter. The PAA is optically transparent in solid form and therefore does not contribute to the absorbance of light in the visible spectrum. Many combinations of absorbing specimen and polar protic solvents can be derived, yielding different filter characteristics in different parts of the spectrum. We report a specific combination as a first example of implementation of our technology. The filter reported has excitation in the green spectrum and emission in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. The thickness of the filter (20 μm) was chosen by calculating the desired SNR using Beer-Lambert's law for liquids, Quantum Yield of the fluorophore and the Quantum Efficiency of the sensor array. The filters promising characteristics make it suitable for low light fluorescence detection. The filter was integrated with a fully functional low noise, low light CMOS contact imager and experimental results using fluorescence polystyrene micro-spheres are presented.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Low noise parametric amplifiers for radio astronomy observations at 18-21 cm wavelength

NASA Technical Reports Server (NTRS)

Kanevskiy, B. Z.; Veselov, V. M.; Strukov, I. A.; Etkin, V. S.

1974-01-01

The principle characteristics and use of SHF parametric amplifiers for radiometer input devices are explored. Balanced parametric amplifiers (BPA) are considered as the SHF signal amplifiers allowing production of the amplifier circuit without a special filter to achieve decoupling. Formulas to calculate the basic parameters of a BPA are given. A modulator based on coaxial lines is discussed as the input element of the SHF. Results of laboratory tests of the receiver section and long-term stability studies of the SHF sector are presented.

Tests of commercial colour CMOS cameras for astronomical applications

NASA Astrophysics Data System (ADS)

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

NASA Astrophysics Data System (ADS)

Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

2014-12-01

The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

The front-end electronics of the LSPE-SWIPE experiment