A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

NASA Astrophysics Data System (ADS)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

A neuromorphic circuit mimicking biological short-term memory.

PubMed

Barzegarjalali, Saeid; Parker, Alice C

2016-08-01

Research shows that the way we remember things for a few seconds is a different mechanism from the way we remember things for a longer time. Short-term memory is based on persistently firing neurons, whereas storing information for a longer time is based on strengthening the synapses or even forming new neural connections. Information about location and appearance of an object is segregated and processed by separate neurons. Furthermore neurons can continue firing using different mechanisms. Here, we have designed a biomimetic neuromorphic circuit that mimics short-term memory by firing neurons, using biological mechanisms to remember location and shape of an object. Our neuromorphic circuit has a hybrid architecture. Neurons are designed with CMOS 45nm technology and synapses are designed with carbon nanotubes (CNT).

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

DTIC Science & Technology

2016-04-01

with Al top electrodes and Cu bottom electrodes. ................... 9 Figure 4. SPICE netlist structure...memory elements play a part in logic gate. 4.4.2 Simulation SPICE Simulation Program for Integrated Circuits Emphasis ( SPICE ) is a general-purpose...analog circuit simulator that was developed at the Electronics Research Laboratory of the University of California, Berkeley [6]. In 1975, SPICE

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

CMOS VLSI Active-Pixel Sensor for Tracking

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

SEU hardened memory cells for a CCSDS Reed Solomon encoder

DOE Office of Scientific and Technical Information (OSTI.GOV)

Whitaker, S.; Canaris, J.; Liu, K.

This paper reports on design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. The design technique provides a recovery mechanism which is independent of the shape of the upsetting event. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station and Explorer platforms.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition.

PubMed

James, Alex Pappachen; Fedorova, Irina; Ibrayev, Timur; Kudithipudi, Dhireesha

2017-06-01

Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.

Si-based optical I/O for optical memory interface

NASA Astrophysics Data System (ADS)

Ha, Kyoungho; Shin, Dongjae; Byun, Hyunil; Cho, Kwansik; Na, Kyoungwon; Ji, Hochul; Pyo, Junghyung; Hong, Seokyong; Lee, Kwanghyun; Lee, Beomseok; Shin, Yong-hwack; Kim, Junghye; Kim, Seong-gu; Joe, Insung; Suh, Sungdong; Choi, Sanghoon; Han, Sangdeok; Park, Yoondong; Choi, Hanmei; Kuh, Bongjin; Kim, Kichul; Choi, Jinwoo; Park, Sujin; Kim, Hyeunsu; Kim, Kiho; Choi, Jinyong; Lee, Hyunjoo; Yang, Sujin; Park, Sungho; Lee, Minwoo; Cho, Minchang; Kim, Saebyeol; Jeong, Taejin; Hyun, Seokhun; Cho, Cheongryong; Kim, Jeong-kyoum; Yoon, Hong-gu; Nam, Jeongsik; Kwon, Hyukjoon; Lee, Hocheol; Choi, Junghwan; Jang, Sungjin; Choi, Joosun; Chung, Chilhee

2012-01-01

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

Optical waveguides with memory effect using photochromic material for neural network

NASA Astrophysics Data System (ADS)

Tanimoto, Keisuke; Amemiya, Yoshiteru; Yokoyama, Shin

2018-04-01

An optical neural network using a waveguide with a memory effect, a photodiode, CMOS circuits and LEDs was proposed. To realize the neural network, optical waveguides with a memory effect were fabricated using a cladding layer containing the photochromic material “diarylethene”. The transmittance of green light was decreased by UV light irradiation and recovered by the passage of green light through the waveguide. It was confirmed that the transmittance versus total energy of the green light that passed through the waveguide well fit the universal exponential curve.

Josephson-CMOS Hybrid Memories

DTIC Science & Technology

2007-04-25

threshold voltage. The subthreshold behavior is critical for dynamic circuits since it determines the static power and retention time of a dynamic memory...results of subthreshold behaviors for different temperatures are shown in Fig. 2.9, the simulated results con- firm the analysis above. Also, experimental...0.5-26.5 GHz 25 dB gain), but they are not on-chip because they comsume so much power (9 W) that you cannot afford to build them on chip. [52] Another

RAD hard PROM design study

NASA Technical Reports Server (NTRS)

1981-01-01

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

SODR Memory Control Buffer Control ASIC

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1994-01-01

The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Nanoelectronics from the bottom up.

PubMed

Lu, Wei; Lieber, Charles M

2007-11-01

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

NASA Astrophysics Data System (ADS)

Sadoghifar, Ali; Heikalabad, Saeed Rasouli

2018-05-01

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

Integrated, nonvolatile, high-speed analog random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

1994-01-01

This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Magnetic Random Access Memory for Embedded Computing

DTIC Science & Technology

2007-10-29

layer, w he free layer hose resistan .  ce  2. Develop and model  data  storage circuits  based  on the MTJ cells. 3. Integrated the MTJ cells into a CMOS...suggested the two methods shown in Fig. 4.5 [95]. The circuit shown at the top of the figure uses NMOS pass transistors to load data , which is the simplest... method but requires careful design to avoid charge sharing and accommodate the data -dependent loading seen at the DATA input. With additional

Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

NASA Astrophysics Data System (ADS)

You, Y.; Huang, D.; Chen, J.; Gong, D.; Liu, T.; Ye, J.

2014-01-01

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

NASA Astrophysics Data System (ADS)

Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Computer-Aided Fabrication of Integrated Circuits

DTIC Science & Technology

1989-09-30

baseline CMOS process. One result of this effort was the identification of several residual bugs in the PATRAN graphics processor . The vendor promises...virtual memory. The internal Nubus architecture uses a 32-bit LISP processor running at 10 megahertz (100 ns clock period). An ethernet controller is...For different patterns, we need different masks for the photo step, and for dif- ferent micro -structures of the wafers, we need different etching

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

NASA Astrophysics Data System (ADS)

Di Pendina, G.; Zianbetov, E.; Beigne, E.

2015-05-01

Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Solid-state image sensor with focal-plane digital photon-counting pixel array

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Pain, Bedabrata (Inventor)

1995-01-01

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Complimentary Metal Oxide Semiconductor (CMOS)-Memristor Hybrid Nanoelectronics

DTIC Science & Technology

2011-06-01

and testing. The major accomplishments of this effort were, 1) a Verilog-A model of a memristor and co-simulation with SPICE for one transistor one...4  4.2  Development of Verilog-A model / SPICE for 1T1R ........................................... 4  4.3 Simulation and...co-simulation with SPICE for one transistor one memristor (1T1R) circuits/memory cell, and a memristor-FPGA routing switch were developed; 2

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Modeling and Implementation of HfO2-based Ferroelectric Tunnel Junctions

NASA Astrophysics Data System (ADS)

Pringle, Spencer Allen

HfO2-based ferroelectric tunnel junctions (FTJs) represent a unique opportunity as both a next-generation digital non-volatile memory and as synapse devices in braininspired logic systems, owing to their higher reliability compared to filamentary resistive random-access memory (ReRAM) and higher speed and lower power consumption compared to competing devices, including phase-change memory (PCM) and state-of-the-art FTJ. Ferroelectrics are often easier to deposit and have simpler material structure than films for magnetic tunnel junctions (MTJs). Ferroelectric HfO2 also enables complementary metal-oxide-semiconductor (CMOS) compatibility, since lead zirconate titanate (PZT) and BaTiO3-based FTJs often are not. No other groups have yet demonstrated a HfO2-based FTJ (to best of the author's knowledge) or applied it to a suitable system. For such devices to be useful, system designers require models based on both theoretical physical analysis and experimental results of fabricated devices in order to confidently design control systems. Both the CMOS circuitry and FTJs must then be designed in layout and fabricated on the same die. This work includes modeling of proposed device structures using a custom python script, which calculates theoretical potential barrier heights as a function of material properties and corresponding current densities (ranging from 8x103 to 3x10-2 A/cm 2 with RHRS/RLRS ranging from 5x105 to 6, depending on ferroelectric thickness). These equations were then combined with polynomial fits of experimental timing data and implemented in a Verilog-A behavioral analog model in Cadence Virtuoso. The author proposes tristate CMOS control systems, and circuits, for implementation of FTJ devices as digital memory and presents simulated performance. Finally, a process flow for fabrication of FTJ devices with CMOS is presented. This work has therefore enabled the fabrication of FTJ devices at RIT and the continued investigation of them as applied to any appropriate systems.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

NASA Astrophysics Data System (ADS)

Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

NASA Astrophysics Data System (ADS)

Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

2018-04-01

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Product assurance technology for custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Pendina, G., E-mail: gregory.dipendina@cea.fr, E-mail: eldar.zianbetov@cea.fr, E-mail: edith.beigne@cea.fr; Zianbetov, E., E-mail: gregory.dipendina@cea.fr, E-mail: eldar.zianbetov@cea.fr, E-mail: edith.beigne@cea.fr; CNRS, SPINTEC, F-38000 Grenoble

2015-05-07

Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remainingmore » in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.« less

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Simple BiCMOS CCCTA design and resistorless analog function realization.

PubMed

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

VLSI 'smart' I/O module development

NASA Astrophysics Data System (ADS)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Wafer-scale development and experimental verification of 0.36 mm2 228 mV open-circuit-voltage solid-state CMOS-compatible glucose fuel cell

NASA Astrophysics Data System (ADS)

Arata, Shigeki; Hayashi, Kenya; Nishio, Yuya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-04-01

The world’s smallest (0.36 mm2) solid-state CMOS-compatible glucose fuel cell, which exhibits an open-circuit voltage (OCV) of 228 mV and a power generation density of 1.32 µW/cm2 with a 30 mM glucose solution, is reported in this paper. Compared with conventional wet etching, dry etching (reactive ion etching) for patterning minimizes damage to the anode and cathode, resulting in a cell with a small size and a high OCV, sufficient for CMOS circuit operation.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

New ultraportable display technology and applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Lewis, Nancy D.

1998-08-01

MicroDisplay devices are based on a combination of technologies rooted in the extreme integration capability of conventionally fabricated CMOS active-matrix liquid crystal display substrates. Customized diffraction grating and optical distortion correction technology for lens-system compensation allow the elimination of many lenses and systems-level components. The MicroDisplay Corporation's miniature integrated information display technology is rapidly leading to many new defense and commercial applications. There are no moving parts in MicroDisplay substrates, and the fabrication of the color generating gratings, already part of the CMOS circuit fabrication process, is effectively cost and manufacturing process-free. The entire suite of the MicroDisplay Corporation's technologies was devised to create a line of application- specific integrated circuit single-chip display systems with integrated computing, memory, and communication circuitry. Next-generation portable communication, computer, and consumer electronic devices such as truly portable monitor and TV projectors, eyeglass and head mounted displays, pagers and Personal Communication Services hand-sets, and wristwatch-mounted video phones are among the may target commercial markets for MicroDisplay technology. Defense applications range from Maintenance and Repair support, to night-vision systems, to portable projectors for mobile command and control centers.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

NASA Astrophysics Data System (ADS)

Moradi, Behzad; Mirzaei, Abdolreza

2016-11-01

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

RC64, a Rad-Hard Many-Core High- Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Gellis, Hagay; Liran, Tuvia; Israeli, Tsvika; Nesher, Roy; Lange, Fredy; Dobkin, Reuven; Meirov, Henri; Reznik, Dror

2015-09-01

RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

RC64, a Rad-Hard Many-Core High-Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Mandler, Alberto; Lange, Fredy; Dobkin, Reuven; Goldberg, Miki

2014-08-01

RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 20 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 2.5 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

CMOS output buffer wave shaper

NASA Technical Reports Server (NTRS)

Albertson, L.; Whitaker, S.; Merrell, R.

1990-01-01

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

Differential wide temperature range CMOS interface circuit for capacitive MEMS pressure sensors.

PubMed

Wang, Yucai; Chodavarapu, Vamsy P

2015-02-12

We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between -55 °C and 225 °C. The circuit is implemented using IBM 0.13 μm CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%.

Differential Wide Temperature Range CMOS Interface Circuit for Capacitive MEMS Pressure Sensors

PubMed Central

Wang, Yucai; Chodavarapu, Vamsy P.

2015-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between −55 °C and 225 °C. The circuit is implemented using IBM 0.13 μm CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%. PMID:25686312

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

PubMed

Aull, Brian

2016-04-08

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

CMOL: A New Concept for Nanoelectronics

NASA Astrophysics Data System (ADS)

Likharev, Konstantin

2005-03-01

I will review the recent work on devices and architectures for future hybrid semiconductor/molecular integrated circuits, in particular those of ``CMOL'' variety [1]. Such circuits would combine an advanced CMOS subsystem fabricated by the usual lithographic patterning, two layers of parallel metallic nanowires formed, e.g., by nanoimprint, and two-terminal molecular devices self-assembled on the nanowire crosspoints. Estimates show that this powerful combination may allow CMOL circuits to reach an unparalleled density (up to 10^12 functions per cm^2) and ultrahigh rate of information processing (up to 10^20 operations per second on a single chip), at acceptable power dissipation. The main challenges on the way toward practical CMOL technology are: (i) reliable chemically-directed self-assembly of mid-size organic molecules, and (ii) the development of efficient defect-tolerant architectures for CMOL circuits. Our recent work has shown that such architectures may be developed not only for terabit-scale memories and naturally defect-tolerant mixed-signal neuromorphic networks, but (rather unexpectedly) also for FPGA-style digital Boolean circuits. [1] For details, see http://rsfq1.physics.sunysb.edu/˜likharev/nano/Springer04.pdf

Energy-efficient STDP-based learning circuits with memristor synapses

NASA Astrophysics Data System (ADS)

Wu, Xinyu; Saxena, Vishal; Campbell, Kristy A.

2014-05-01

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (<1 pJ/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.

An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Khosroshahy, Milad Bagherian; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

Nanotechnologies, notably quantum-dot cellular automata, have achieved major attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, high switching speed and ultra-low energy consumption, is considered as a potential alternative for the CMOS technology. As the memory unit is one of the most essential components in a digital system, designing a well-optimized QCA random access memory (RAM) cell is an important area of research. In this paper, a new five-input majority gate is presented which is suitable for implementing efficient single-layer QCA circuits. In addition, a new RAM cell with set and reset capabilities is designed based on the proposed majority gate, which has an efficient and low-energy structure. The functionality, performance and energy consumption of the proposed designs are evaluated based on the QCADesigner and QCAPro tools. According to the simulation results, the proposed RAM design leads to on average 38% lower total energy dissipation, 25% smaller area, 20% lower cell count, 28% lower delay and 60% lower QCA cost as compared to its previous counterparts.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

Filamentary model in resistive switching materials

NASA Astrophysics Data System (ADS)

Jasmin, Alladin C.

2017-12-01

The need for next generation computer devices is increasing as the demand for efficient data processing increases. The amount of data generated every second also increases which requires large data storage devices. Oxide-based memory devices are being studied to explore new research frontiers thanks to modern advances in nanofabrication. Various oxide materials are studied as active layers for non-volatile memory. This technology has potential application in resistive random-access-memory (ReRAM) and can be easily integrated in CMOS technologies. The long term perspective of this research field is to develop devices which mimic how the brain processes information. To realize such application, a thorough understanding of the charge transport and switching mechanism is important. A new perspective in the multistate resistive switching based on current-induced filament dynamics will be discussed. A simple equivalent circuit of the device gives quantitative information about the nature of the conducting filament at different resistance states.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

PubMed Central

Chang, Ming-Hui; Huang, Han-Pang

2013-01-01

This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement. PMID:23493122

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Sensing circuits for multiwire proportional chambers

NASA Technical Reports Server (NTRS)

Peterson, H. T.; Worley, E. R.

1977-01-01

Integrated sensing circuits were designed, fabricated, and packaged for use in determining the direction and fluence of ionizing radiation passing through a multiwire proportional chamber. CMOS on sapphire was selected because of its high speed and low power capabilities. The design of the proposed circuits is described and the results of computer simulations are presented. The fabrication processes for the CMOS on sapphire sensing circuits and hybrid substrates are outlined. Several design options are described and the cost implications of each discussed. To be most effective, each chip should handle not more than 32 inputs, and should be mounted on its own hybrid substrate.

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

SIERRA - A 3-D device simulator for reliability modeling

NASA Astrophysics Data System (ADS)

Chern, Jue-Hsien; Arledge, Lawrence A., Jr.; Yang, Ping; Maeda, John T.

1989-05-01

SIERRA is a three-dimensional general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under dc, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5x to 7x speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and dynamic random-access memory single-event-upset studies is described.

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1993-01-01

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

NASA Astrophysics Data System (ADS)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

DEAL annual report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Misra, Shashank

2017-11-01

The digital electronics at the atomic limit (DEAL) project seeks to leverage Sandia's atomic-precision fabrication capability to realize the theorized orders-of-magnitude improvement in operating voltage for tunnel field effect transistors (TFETs) compared to CMOS. Not only are low-power digital circuits a critical element of many national security systems (e.g. satellites), TFETs can perform circuit functions inaccessible to CMOS (e.g. polymorphism).

Twenty-four-micrometer-pitch microelectrode array with 6912-channel readout at 12 kHz via highly scalable implementation for high-spatial-resolution mapping of action potentials.

PubMed

Ogi, Jun; Kato, Yuri; Matoba, Yoshihisa; Yamane, Chigusa; Nagahata, Kazunori; Nakashima, Yusaku; Kishimoto, Takuya; Hashimoto, Shigeki; Maari, Koichi; Oike, Yusuke; Ezaki, Takayuki

2017-12-19

A 24-μm-pitch microelectrode array (MEA) with 6912 readout channels at 12 kHz and 23.2-μV rms random noise is presented. The aim is to reduce noise in a "highly scalable" MEA with a complementary metal-oxide-semiconductor integration circuit (CMOS-MEA), in which a large number of readout channels and a high electrode density can be expected. Despite the small dimension and the simplicity of the in-pixel circuit for the high electrode-density and the relatively large number of readout channels of the prototype CMOS-MEA chip developed in this work, the noise within the chip is successfully reduced to less than half that reported in a previous work, for a device with similar in-pixel circuit simplicity and a large number of readout channels. Further, the action potential was clearly observed on cardiomyocytes using the CMOS-MEA. These results indicate the high-scalability of the CMOS-MEA. The highly scalable CMOS-MEA provides high-spatial-resolution mapping of cell action potentials, and the mapping can aid understanding of complex activities in cells, including neuron network activities.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

PubMed

Li, Haitao; Boling, C Sam; Mason, Andrew J

2016-08-01

Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Fukuda, Koichi; Liu, Yongxun; Mori, Takahiro; Mizubayashi, Wataru; O'uchi, Shin-ichi; Fuketa, Hiroshi; Otsuka, Shintaro; Migita, Shinji; Masahara, Meishoku; Endo, Kazuhiko; Ota, Hiroyuki; Matsukawa, Takashi

2017-04-01

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

LDRD report: Smoke effects on electrical equipment

DOE Office of Scientific and Technical Information (OSTI.GOV)

TANAKA,TINA J.; BAYNES JR.,EDWARD E.; NOWLEN,STEVEN P.

2000-03-01

Smoke is known to cause electrical equipment failure, but the likelihood of immediate failure during a fire is unknown. Traditional failure assessment techniques measure the density of ionic contaminants deposited on surfaces to determine the need for cleaning or replacement of electronic equipment exposed to smoke. Such techniques focus on long-term effects, such as corrosion, but do not address the immediate effects of the fire. This document reports the results of tests on the immediate effects of smoke on electronic equipment. Various circuits and components were exposed to smoke from different fields in a static smoke exposure chamber and weremore » monitored throughout the exposure. Electrically, the loss of insulation resistance was the most important change caused by smoke. For direct current circuits, soot collected on high-voltage surfaces sometimes formed semi-conductive soot bridges that shorted the circuit. For high voltage alternating current circuits, the smoke also tended to increase the likelihood of arcing, but did not accumulate on the surfaces. Static random access memory chips failed for high levels of smoke, but hard disk drives did not. High humidity increased the conductive properties of the smoke. The conductivity does not increase linearly with smoke density as first proposed; however, it does increase with quantity. The data can be used to give a rough estimate of the amount of smoke that will cause failures in CMOS memory chips, dc and ac circuits. Comparisons of this data to other fire tests can be made through the optical and mass density measurements of the smoke.« less

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor)

2015-01-01

A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

NASA Technical Reports Server (NTRS)

Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

2002-01-01

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

NASA Astrophysics Data System (ADS)

Fulkerson, David E.

2010-02-01

This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

PubMed Central

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

PubMed

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

An efficient current-based logic cell model for crosstalk delay analysis

NASA Astrophysics Data System (ADS)

Nazarian, Shahin; Das, Debasish

2013-04-01

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.

Qualitative-Modeling-Based Silicon Neurons and Their Networks

PubMed Central

Kohno, Takashi; Sekikawa, Munehisa; Li, Jing; Nanami, Takuya; Aihara, Kazuyuki

2016-01-01

The ionic conductance models of neuronal cells can finely reproduce a wide variety of complex neuronal activities. However, the complexity of these models has prompted the development of qualitative neuron models. They are described by differential equations with a reduced number of variables and their low-dimensional polynomials, which retain the core mathematical structures. Such simple models form the foundation of a bottom-up approach in computational and theoretical neuroscience. We proposed a qualitative-modeling-based approach for designing silicon neuron circuits, in which the mathematical structures in the polynomial-based qualitative models are reproduced by differential equations with silicon-native expressions. This approach can realize low-power-consuming circuits that can be configured to realize various classes of neuronal cells. In this article, our qualitative-modeling-based silicon neuron circuits for analog and digital implementations are quickly reviewed. One of our CMOS analog silicon neuron circuits can realize a variety of neuronal activities with a power consumption less than 72 nW. The square-wave bursting mode of this circuit is explained. Another circuit can realize Class I and II neuronal activities with about 3 nW. Our digital silicon neuron circuit can also realize these classes. An auto-associative memory realized on an all-to-all connected network of these silicon neurons is also reviewed, in which the neuron class plays important roles in its performance. PMID:27378842

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Moharrami, Elham; Navimipour, Nima Jafari

2018-04-01

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.

A Low Cost Rad-Tolerant Standard Cell Library

NASA Technical Reports Server (NTRS)

Gambles, Jody W.; Maki, Gary K.

1997-01-01

This paper describes circuit design techniques developed at the NASA Institute of Advanced Microelectronics that have been shown to protect CMOS circuits from the deleterious effects of the natural space radiation environment. The IAuE is leading a program to incorporate these radiation-tolerance providing design techniques into a commercial standard cell library that will be used in conjunction with available Electronic Design Automation tools to produce space flight qualified microelectronics fabricated at modern commercial CMOS foundries.

Facile fabrication of efficient organic CMOS circuits.

PubMed

Dzwilewski, Andrzej; Matyba, Piotr; Edman, Ludvig

2010-01-14

Organic electronic circuits based on a combination of n- and p-type transistors (so-called CMOS circuits) are attractive, since they promise the realization of a manifold of versatile and low-cost electronic devices. Here, we report a novel photoinduced transformation method, which allows for a particularly straightforward fabrication of highly functional organic CMOS circuits. A solution-deposited single-layer film, comprising a mixture of the n-type semiconductor [6,6]-phenyl-C(61)-butyric acid methyl ester (PCBM) and the p-type semiconductor poly-3-hexylthiophene (P3HT) in a 3:1 mass ratio, was utilized as the common active material in an array of transistors. Selected film areas were exposed to laser light, with the result that the irradiated PCBM monomers were photochemically transformed into a low-solubility and high-mobility dimeric state. Thereafter, the entire film was developed via immersion into a developer solution, which selectively removed the nonexposed, and monomeric, PCBM component. The end result was that the transistors in the exposed film areas are n-type, as dimeric PCBM is the majority component in the active material, while the transistors in the nonexposed film areas are p-type, as P3HT is the sole remaining material. We demonstrate the merit of the method by utilizing the resulting combination of n-type and p-type transistors for the realization of CMOS inverters with a high gain of approximately 35.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Design of replica bit line control circuit to optimize power for SRAM

NASA Astrophysics Data System (ADS)

Pengjun, Wang; Keji, Zhou; Huihong, Zhang; Daohui, Gong

2016-12-01

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002, 61474068), and the K. C. Wong Magna Fund in Ningbo University.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

Organic-on-silicon complementary metal–oxide–semiconductor colour image sensors

PubMed Central

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-01

Complementary metal–oxide–semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor. PMID:25578322

Proton Tolerance of SiGe Precision Voltage References for Extreme Temperature Range Electronics

NASA Astrophysics Data System (ADS)

Najafizadeh, Laleh; Bellini, Marco; Prakash, A. P. Gnana; Espinel, Gustavo A.; Cressler, John D.; Marshall, Paul W.; Marshall, Cheryl J.

2006-12-01

A comprehensive investigation of the effects of proton irradiation on the performance of SiGe BiCMOS precision voltage references intended for extreme environment operational conditions is presented. The voltage reference circuits were designed in two distinct SiGe BiCMOS technology platforms (first generation (50 GHz) and third generation (200 GHz)) in order to investigate the effect of technology scaling. The circuits were irradiated at both room temperature and at 77 K. Measurement results from the experiments indicate that the proton-induced changes in the SiGe bandgap references are minor, even down to cryogenic temperatures, clearly good news for the potential application of SiGe mixed-signal circuits in emerging extreme environments

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

A novel wireless power and data transmission AC to DC converter for an implantable device.

PubMed

Liu, Jhao-Yan; Tang, Kea-Tiong

2013-01-01

This article presents a novel AC to DC converter implemented by standard CMOS technology, applied for wireless power transmission. This circuit combines the functions of the rectifier and DC to DC converter, rather than using the rectifier to convert AC to DC and then supplying the required voltage with regulator as in the transitional method. This modification can reduce the power consumption and the area of the circuit. This circuit also transfers the loading condition back to the external circuit by the load shift keying(LSK), determining if the input power is not enough or excessive, which increases the efficiency of the total system. The AC to DC converter is fabricated with the TSMC 90nm CMOS process. The circuit area is 0.071mm(2). The circuit can produce a 1V DC voltage with maximum output current of 10mA from an AC input ranging from 1.5V to 2V, at 1MHz to 10MHz.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

PubMed Central

Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

2016-01-01

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

NASA Astrophysics Data System (ADS)

Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

2017-06-01

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

NASA Astrophysics Data System (ADS)

Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

2009-05-01

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

NASA Astrophysics Data System (ADS)

Hayakawa, Hitoshi; Ogawa, Makoto; Shibata, Tadashi

2005-04-01

A very large scale integrated circuit (VLSI) architecture for a multiple-instruction-stream multiple-data-stream (MIMD) associative processor has been proposed. The processor employs an architecture that enables seamless switching from associative operations to arithmetic operations. The MIMD element is convertible to a regular central processing unit (CPU) while maintaining its high performance as an associative processor. Therefore, the MIMD associative processor can perform not only on-chip perception, i.e., searching for the vector most similar to an input vector throughout the on-chip cache memory, but also arithmetic and logic operations similar to those in ordinary CPUs, both simultaneously in parallel processing. Three key technologies have been developed to generate the MIMD element: associative-operation-and-arithmetic-operation switchable calculation units, a versatile register control scheme within the MIMD element for flexible operations, and a short instruction set for minimizing the memory size for program storage. Key circuit blocks were designed and fabricated using 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. As a result, the full-featured MIMD element is estimated to be 3 mm2, showing the feasibility of an 8-parallel-MIMD-element associative processor in a single chip of 5 mm× 5 mm.

Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

PubMed Central

Dutta, Sourav; Chang, Sou-Chi; Kani, Nickvash; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Naeemi, Azad

2015-01-01

The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations. PMID:25955353

The use of light emission in failure analysis of CMOS ICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hawkins, C.F.; Soden, J.M.; Cole, E.I. Jr.

1990-01-01

The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

NASA Technical Reports Server (NTRS)

Yeh, Penshu; Maki, Gary

2007-01-01

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

NASA Astrophysics Data System (ADS)

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo; Steyaert, Michiel; Leroux, Paul

2018-04-01

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

Energy efficient hybrid computing systems using spin devices

NASA Astrophysics Data System (ADS)

Sharad, Mrigank

Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

NASA Astrophysics Data System (ADS)

Mitić, Darko B.; Jovanović, Goran S.; Stojčev, Mile K.; Antić, Dragan S.

2015-03-01

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

NASA Astrophysics Data System (ADS)

Aloulou, R.; De Peslouan, P.-O. Lucas; Mnif, H.; Alicalapa, F.; Luk, J. D. Lan Sun; Loulou, M.

2016-05-01

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.

CMOS Camera Array With Onboard Memory

NASA Technical Reports Server (NTRS)

Gat, Nahum

2009-01-01

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

NASA Astrophysics Data System (ADS)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Full analogue electronic realisation of the Hodgkin-Huxley neuronal dynamics in weak-inversion CMOS.

PubMed

Lazaridis, E; Drakakis, E M; Barahona, M

2007-01-01

This paper presents a non-linear analog synthesis path towards the modeling and full implementation of the Hodgkin-Huxley neuronal dynamics in silicon. The proposed circuits have been realized in weak-inversion CMOS technology and take advantage of both log-domain and translinear transistor-level techniques.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Wideband low-noise variable-gain BiCMOS transimpedance amplifier

NASA Astrophysics Data System (ADS)

Meyer, Robert G.; Mack, William D.

1994-06-01

A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kilo ohms, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/square root of Hz and input signal-current handling capability of 3 mA.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Development of CMOS Imager Block for Capsule Endoscope

NASA Astrophysics Data System (ADS)

Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

2014-04-01

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

High density submicron magnetoresistive random access memory (invited)

NASA Astrophysics Data System (ADS)

Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

1999-04-01

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

PubMed

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

NASA Astrophysics Data System (ADS)

Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

2017-02-01

This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Nanopore-CMOS Interfaces for DNA Sequencing

PubMed Central

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-01-01

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

Nanopore-CMOS Interfaces for DNA Sequencing.

PubMed

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-08-06

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

Nanomagnet Logic: Architectures, design, and benchmarking

NASA Astrophysics Data System (ADS)

Kurtz, Steven J.

Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to project what advancements are required for NML to realize performance improvements over scaled-CMOS hardware equivalents at the functional unit and/or application-level.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Signal to Noise Ratio SPICE Simulation Program with Integrated Circuit Emphasis TIFF Tagged Image File Format USC University of Southern California xvii...sources can create errors in digital circuits. These effects can be simulated using Simulation Program with Integrated Circuit Emphasis ( SPICE ) or...compute summary statistics. 4.1 Circuit Simulations Noisy analog circuits can be simulated in SPICE or Cadence SpectreTM software via noisy voltage

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Multi-purpose CMOS sensor interface for low-power applications

NASA Astrophysics Data System (ADS)

Wouters, P.; de Cooman, M.; Puers, R.

1994-08-01

A dedicated low-power CMOS transponder microchip is presented as part of a novel telemetry implant for biomedical applications. This mixed analog-digital circuit contains an identification code and collects information on physiological parameters, i.e., body temperature and physical activity, and on the status of the battery. To minimize the amount of data to be transmitted, a dedicated signal processing algorithm is embedded within its circuitry. All telemetry functions (encoding, modulation, generation of the carrier) are implemented on the integrated circuit. Emphasis is on a high degree of flexibility towards sensor inputs and internal data management, extreme miniaturization, and low-power consumption to allow a long implantation lifetime.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

NASA Astrophysics Data System (ADS)

Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

2017-01-01

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Flow sensor based on monolithic integration of organic light-emitting diodes (OLEDs) and CMOS circuits

NASA Astrophysics Data System (ADS)

Reckziegel, S.; Kreye, D.; Puegner, T.; Vogel, U.; Scholles, M.; Grillberger, C.; Fehse, K.

2009-02-01

In this paper we present an optoelectronic integrated circuit (OEIC) based on monolithic integration of organic lightemitting diodes (OLEDs) and CMOS technology. By the use of integrated circuits, photodetectors and highly efficient OLEDs on the same silicon chip, novel OEICs with combined sensors and actuating elements can be realized. The OLEDs are directly deposited on the CMOS top metal. The metal layer serves as OLED bottom electrode and determines the bright area. Furthermore, the area below the OLED electrodes can be used for integrated circuits. The monolithic integration of actuators, sensors and electronics on a common silicon substrate brings significant advantages in most sensory applications. The developed OEIC combines three different types of sensors: a reflective sensor, a color sensor and a particle flow sensor and is configured with an orange (597nm) emitting p-i-n OLED. We describe the architecture of such a monolithic OEIC and demonstrate a method to determine the velocity of a fluid being conveyed pneumatically in a transparent capillary. The integrated OLEDs illuminate the capillary with the flowing fluid. The fluid has a random reflection profile. Depending on the velocity and a random contrast difference, more or less light is reflected back to the substrate. The integrated photodiodes located at different fixed points detect the reflected light and using crosscorrelation, the velocity is calculated from the time in which contrast differences move over a fixed distance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

PubMed

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

FinFET memory cell improvements for higher immunity against single event upsets

NASA Astrophysics Data System (ADS)

Sajit, Ahmed Sattar

The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high likelihood of SEUs. Consequently, FinFET DICE memory can be a good candidate due to its high ability to tolerate SEUs of different amplitudes and long periods for both read and hold operations.

A compact nanopower low output impedance CMOS operational amplifier for wireless intraocular pressure recordings.

PubMed

Dresher, Russell P; Irazoqui, Pedro P

2007-01-01

Wireless sensing has shown potential benefits for the continuous-time measurement of physiological data. One such application is the recording of intraocular pressure (IOP) for patients with glaucoma. Ultra-low-power circuits facilitate the use of inductively-coupled power for implantable wireless systems. Compact circuit size is also desirable for implantable systems. As a first step towards the realization of such circuits, we have designed a compact, ultra-low-power operational amplifier which can be used to record IOP. This paper presents the measured results of a CMOS operational amplifier that can be incorporated with a wireless IOP monitoring system or other low-power application. It has a power consumption of 736 nW, chip area of 0.023 mm2, and output impedance of 69 Omega to drive low-impedance loads.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

CMOS sensor as charged particles and ionizing radiation detector

NASA Astrophysics Data System (ADS)

Cruz-Zaragoza, E.; Piña López, I.

2015-01-01

This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Built-in self-repair of VLSI memories employing neural nets

NASA Astrophysics Data System (ADS)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

NASA Astrophysics Data System (ADS)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

Power control electronics for cryogenic instrumentation

NASA Technical Reports Server (NTRS)

Ray, Biswajit; Gerber, Scott S.; Patterson, Richard L.; Myers, Ira T.

1995-01-01

In order to achieve a high-efficiency high-density cryogenic instrumentation system, the power processing electronics should be placed in the cold environment along with the sensors and signal-processing electronics. The typical instrumentation system requires low voltage dc usually obtained from processing line frequency ac power. Switch-mode power conversion topologies such as forward, flyback, push-pull, and half-bridge are used for high-efficiency power processing using pulse-width modulation (PWM) or resonant control. This paper presents several PWM and multiresonant power control circuits, implemented using commercially available CMOS and BiCMOS integrated circuits, and their performance at liquid-nitrogen temperature (77 K) as compared to their room temperature (300 K) performance. The operation of integrated circuits at cryogenic temperatures results in an improved performance in terms of increased speed, reduced latch-up susceptibility, reduced leakage current, and reduced thermal noise. However, the switching noise increased at 77 K compared to 300 K. The power control circuits tested in the laboratory did successfully restart at 77 K.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

PubMed Central

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Investigation of noise insensitive electronic circuits for automotive applications with particular regard to MOS circuits

NASA Astrophysics Data System (ADS)

Gorille, I.

1980-11-01

The application of MOS switching circuits of high complexity in essential automobile systems, such as ignition and injection, was investigated. A bipolar circuit technology, current hogging logic (CHL), was compared to MOS technologies for its competitiveness. The functional requirements of digital automotive systems can only be met by technologies allowing large packing densities and medium speeds. The properties of n-MOS and CMOS are promising whereas the electrical power needed by p-MOS circuits is in general prohibitively large.

C-MOS bulk metal design handbook. [LSI standard cell (circuits)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

PubMed

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

A Hybrid CMOS-Memristor Neuromorphic Synapse.

PubMed

Azghadi, Mostafa Rahimi; Linares-Barranco, Bernabe; Abbott, Derek; Leong, Philip H W

2017-04-01

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as [Formula: see text] in a [Formula: see text] process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

A 1.1nW Energy Harvesting System with 544pW Quiescent Power for Next Generation Implants

PubMed Central

Mercier, Patrick P.; Lysaght, Andrew C.; Stankovic, Konstantina M.; Chandrakasan, Anantha P.

2015-01-01

This paper presents a nW power management unit (PMU) for an autonomous wireless sensor that sustains itself by harvesting energy from the endocochlear potential (EP), the 70–100 mV electrochemical bio-potential inside the mammalian ear. Due to the anatomical constraints inside the inner ear, the total extractable power from the EP is limited to 1.1–6.25 nW. A nW boost converter is used to increase the input voltage (30–55 mV) to a higher voltage (0.8 to 1.1 V) usable by CMOS circuits in the sensor. A pW Charge Pump circuit is used to minimize the leakage in the boost converter. Further, ultra-low-power control circuits consisting of digital implementations of input impedance adjustment circuits and Zero Current Switching circuits along with Timer and Reference circuits keep the quiescent power of the PMU down to 544 pW. The designed boost converter achieves a peak power conversion efficiency of 56%. The PMU can sustain itself and a duty-cyled ultra-low power load while extracting power from the EP of a live guinea pig. The PMU circuits have been implemented on a 0.18µm CMOS process. PMID:25983340

Variability of multilevel switching in scaled hybrid RS/CMOS nanoelectronic circuits: theory

NASA Astrophysics Data System (ADS)

Heittmann, Arne; Noll, Tobias G.

2013-07-01

A theory is presented which describes the variability of multilevel switching in scaled hybrid resistive-switching/CMOS nanoelectronic circuits. Variability is quantified in terms of conductance variation using the first two moments derived from the probability density function (PDF) of the RS conductance. For RS, which are based on the electrochemical metallization effect (ECM), this variability is - to some extent - caused by discrete events such as electrochemical reactions, which occur on atomic scale and are at random. The theory shows that the conductance variation depends on the joint interaction between the programming circuit and the resistive switch (RS), and explicitly quantifies the impact of RS device parameters and parameters of the programming circuit on the conductance variance. Using a current mirror as an exemplary programming circuit an upper limit of 2-4 bits (dependent on the filament surface area) is estimated as the storage capacity exploiting the multilevel capabilities of an ECM cell. The theoretical results were verified by Monte Carlo circuit simulations on a standard circuit simulation environment using an ECM device model which models the filament growth by a Poisson process. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

A 1.1nW Energy Harvesting System with 544pW Quiescent Power for Next Generation Implants.

PubMed

Bandyopadhyay, Saurav; Mercier, Patrick P; Lysaght, Andrew C; Stankovic, Konstantina M; Chandrakasan, Anantha P

2014-12-01

This paper presents a nW power management unit (PMU) for an autonomous wireless sensor that sustains itself by harvesting energy from the endocochlear potential (EP), the 70-100 mV electrochemical bio-potential inside the mammalian ear. Due to the anatomical constraints inside the inner ear, the total extractable power from the EP is limited to 1.1-6.25 nW. A nW boost converter is used to increase the input voltage (30-55 mV) to a higher voltage (0.8 to 1.1 V) usable by CMOS circuits in the sensor. A pW Charge Pump circuit is used to minimize the leakage in the boost converter. Further, ultra-low-power control circuits consisting of digital implementations of input impedance adjustment circuits and Zero Current Switching circuits along with Timer and Reference circuits keep the quiescent power of the PMU down to 544 pW. The designed boost converter achieves a peak power conversion efficiency of 56%. The PMU can sustain itself and a duty-cyled ultra-low power load while extracting power from the EP of a live guinea pig. The PMU circuits have been implemented on a 0.18µm CMOS process.

Assessing Design Activity in Complex CMOS Circuit Design.

ERIC Educational Resources Information Center

Biswas, Gautam; And Others

This report characterizes human problem solving in digital circuit design. Protocols of 11 different designers with varying degrees of training were analyzed by identifying the designers' problem solving strategies and discussing activity patterns that differentiate the designers. These methods are proposed as a tentative basis for assessing…

Inverter Matrix for the Clementine Mission

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Tardio, G.; Soli, G. A.

1994-01-01

An inverter matrix test circuit was designed for the Clementine space mission and is built into the RRELAX (Radiation and Reliability Assurance Experiment). The objective is to develop a circuit that will allow the evaluation of the CMOS FETs using a lean data set in the noisy spacecraft environment.

Multi-physics modelling contributions to investigate the atmospheric cosmic rays on the single event upset sensitivity along the scaling trend of CMOS technologies.

PubMed

Hubert, G; Regis, D; Cheminet, A; Gatti, M; Lacoste, V

2014-10-01

Particles originating from primary cosmic radiation, which hit the Earth's atmosphere give rise to a complex field of secondary particles. These particles include neutrons, protons, muons, pions, etc. Since the 1980s it has been known that terrestrial cosmic rays can penetrate the natural shielding of buildings, equipment and circuit package and induce soft errors in integrated circuits. Recently, research has shown that commercial static random access memories are now so small and sufficiently sensitive that single event upsets (SEUs) may be induced from the electronic stopping of a proton. With continued advancements in process size, this downward trend in sensitivity is expected to continue. Then, muon soft errors have been predicted for nano-electronics. This paper describes the effects in the specific cases such as neutron-, proton- and muon-induced SEU observed in complementary metal-oxide semiconductor. The results will allow investigating the technology node sensitivity along the scaling trend. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Memory technology survey

NASA Technical Reports Server (NTRS)

1981-01-01

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

EDITORIAL: Synaptic electronics Synaptic electronics

NASA Astrophysics Data System (ADS)

Demming, Anna; Gimzewski, James K.; Vuillaume, Dominique

2013-09-01

Conventional computers excel in logic and accurate scientific calculations but make hard work of open ended problems that human brains handle easily. Even von Neumann—the mathematician and polymath who first developed the programming architecture that forms the basis of today's computers—was already looking to the brain for future developments before his death in 1957 [1]. Neuromorphic computing uses approaches that better mimic the working of the human brain. Recent developments in nanotechnology are now providing structures with very accommodating properties for neuromorphic approaches. This special issue, with guest editors James K Gimzewski and Dominique Vuillaume, is devoted to research at the serendipitous interface between the two disciplines. 'Synaptic electronics', looks at artificial devices with connections that demonstrate behaviour similar to synapses in the nervous system allowing a new and more powerful approach to computing. Synapses and connecting neurons respond differently to incident signals depending on the history of signals previously experienced, ultimately leading to short term and long term memory behaviour. The basic characteristics of a synapse can be replicated with around ten simple transistors. However with the human brain having around 1011 neurons and 1015 synapses, artificial neurons and synapses from basic transistors are unlikely to accommodate the scalability required. The discovery of nanoscale elements that function as 'memristors' has provided a key tool for the implementation of synaptic connections [2]. Leon Chua first developed the concept of the 'The memristor—the missing circuit element' in 1971 [3]. In this special issue he presents a tutorial describing how memristor research has fed into our understanding of synaptic behaviour and how they can be applied in information processing [4]. He also describes, 'The new principle of local activity, which uncovers a minuscule life-enabling "Goldilocks zone", dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge'. Also in this issue R Stanley Williams and colleagues report results from simulations that demonstrate the potential for using Mott transistors as building blocks for scalable neuristor-based integrated circuits without transistors [5]. The scalability of neural chip designs is also tackled in the design reported by Narayan Srinivasa and colleagues in the US [6]. Meanwhile Carsten Timm and Massimiliano Di Ventra describe simulations of a molecular transistor in which electrons strongly coupled to a vibrational mode lead to a Franck-Condon (FC) blockade that mimics the spiking action potentials in synaptic memory behaviour [7]. The 'atomic switches' used to demonstrate synaptic behaviour by a collaboration of researchers in California and Japan also come under further scrutiny in this issue. James K Gimzewski and colleagues consider the difference between the behaviour of an atomic switch in isolation and in a network [8]. As the authors point out, 'The work presented represents steps in a unified approach of experimentation and theory of complex systems to make atomic switch networks a uniquely scalable platform for neuromorphic computing'. Researchers in Germany [9] and Sweden [10] also report on theoretical approaches to modelling networks of memristive elements and complementary resistive switches for synaptic devices. As Vincent Derycke and colleagues in France point out, 'Actual experimental demonstrations of neural network type circuits based on non-conventional/non-CMOS memory devices and displaying function learning capabilities remain very scarce'. They describe how their work using carbon nanotubes provides a rare demonstration of actual function learning with synapses based on nanoscale building blocks [11]. However, this is far from the only experimental work reported in this issue, others include: short-term memory of TiO2-based electrochemical capacitors [12]; a neuromorphic circuit composed of a nanoscale 1-kbit resistive random-access memory (RRAM) cross-point array of synapses and complementary metal-oxide-semiconductor (CMOS) neuron circuits [13]; a WO3-x-based nanoionics device from Masakazu Aono's group with a wide scale of reprogrammable memorization functions [14]; a new spike-timing dependent plasticity scheme based on a MOS transistor as a selector and a RRAM as a variable resistance device [15]; a new hybrid memristor-CMOS neuromorphic circuit [16]; and a photo-assisted atomic switch [17]. Synaptic electronics evidently has many emerging facets, and Duygu Kuzum, Shimeng Yu, and H-S Philip Wong in the US provide a review of the field, including the materials, devices and applications [18]. In embracing the expertise acquired over thousands of years of evolution, biomimetics and bio-inspired design is a common, smart approach to technological innovation. Yet in successfully mimicking the physiological mechanisms of the human mind synaptic electronics research has a potential impact that is arguably unprecedented. That the quirks and eccentricities recently unearthed in the behaviour of nanomaterials should lend themselves so accommodatingly to emulating synaptic functions promises some very exciting developments in the field, as the articles in this special issue emphasize. References [1] von Neumann J (ed) 2012 The Computer and the Brain 3rd edn (Yale: Yale University Press) [2] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 The missing memristor found Nature 453 80-3 [3] Chua L O 1971 Memristor—the missing circuit element IEEE Trans. Circuit Theory 18 507-19 [4] Chua L O 2013 Memristor, Hodgkin-Huxley, and Edge of Chaos Nanotechnology 24 383001 [5] Pickett M D and Williams R S 2013 Phase transitions enable computational universality in neuristor-based cellular automata Nanotechnology 24 384002 [6] Cruz-Albrecht J M, Derosier T and Srinivasa N 2013 Scalable neural chip with synaptic electronics using CMOS integrated memristors Nanotechnology 24 384011 [7] Timm C and Di Ventra M 2013 Molecular neuron based on the Franck-Condon blockade Nanotechnology 24 384001 [8] Sillin H O, Aguilera R, Shieh H-H, Avizienis A V, Aono M, Stieg A Z and Gimzewski J K 2013 A theoretical and experimental study of neuromorphic atomic switch networks for reservoir computing Nanotechnology 24 384004 [9] Linn E, Menzel S, Ferch S and Waser R 2013 Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications Nanotechnology 24 384008 [10] Konkoli Z and Wendin G 2013 A generic simulator for large networks of memristive elements Nanotechnology 24 384007 [11] Gacem K, Retrouvey J-M, Chabi D, Filoramo A, Zhao W, Klein J-O and Derycke V 2013 Neuromorphic function learning with carbon nanotube-based synapses Nanotechnology 24 384013 [12] Lim H, Kim I, Kim J-S, Hwang C S and Jeong D S 2013 Short-term memory of TiO2-based electrochemical capacitors: empirical analysis with adoption of a sliding threshold Nanotechnology 24 384005 [13] Park S, Noh J, Choo M-L, Sheri A M, Chang M, Kim Y-B, Kim C J, Jeon M, Lee B-G, Lee B H and Hwang H 2013 Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device Nanotechnology 24 384009 [14] Yang R, Terabe K, Yao Y, Tsuruoka T, Hasegawa T, Gimzewski J K and Aono M 2013 Synaptic plasticity and memory functions achieved in WO3-x-based nanoionics device by using principle of atomic switch operation Nanotechnology 24 384002 [15] Ambrogio S, Balatti S, Nardi F, Facchinetti S and Ielmini D 2013 Spike-timing dependent plasticity in a transistor-selected resistive switching memory Nanotechnology 24 384012 [16] Indiveria G, Linares-Barranco B, Legenstein R, Deligeorgis G and Prodromakise T 2013 Integration of nanoscale memristor synapses in neuromorphic computing architectures Nanotechnology 24 384010 [17] Hino T, Hasegawa T, Tanaka H, Tsuruoka T, Terabe K, Ogawa T and Aono M 2013 Volatile and nonvolatile selective switching of a photo-assited initialized atomic switch Nanotechnology 24 384006 [18] Kuzum D, Yu S and Wong H-S P 2013 Synaptic electronics: materials, devices and applications Nanotechnology 24 382001

CMOS compatible electrode materials selection in oxide-based memory devices

NASA Astrophysics Data System (ADS)

Zhuo, V. Y.-Q.; Li, M.; Guo, Y.; Wang, W.; Yang, Y.; Jiang, Y.; Robertson, J.

2016-07-01

Electrode materials selection guidelines for oxide-based memory devices are constructed from the combined knowledge of observed device operation characteristics, ab-initio calculations, and nano-material characterization. It is demonstrated that changing the top electrode material from Ge to Cr to Ta in the Ta2O5-based memory devices resulted in a reduction of the operation voltages and current. Energy Dispersed X-ray (EDX) Spectrometer analysis clearly shows that the different top electrode materials scavenge oxygen ions from the Ta2O5 memory layer at various degrees, leading to different oxygen vacancy concentrations within the Ta2O5, thus the observed trends in the device performance. Replacing the Pt bottom electrode material with CMOS compatible materials (Ru and Ir) further reduces the power consumption and can be attributed to the modification of the Schottky barrier height and oxygen vacancy concentration at the electrode/oxide interface. Both trends in the device performance and EDX results are corroborated by the ab-initio calculations which reveal that the electrode material tunes the oxygen vacancy concentration via the oxygen chemical potential and defect formation energy. This experimental-theoretical approach strongly suggests that the proper selection of CMOS compatible electrode materials will create the critical oxygen vacancy concentration to attain low power memory performance.

Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits

NASA Technical Reports Server (NTRS)

Beagles, Grant; Winters, Kel; Eldin, A. G.

1992-01-01

A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Implementation of a spike-based perceptron learning rule using TiO2-x memristors.

PubMed

Mostafa, Hesham; Khiat, Ali; Serb, Alexander; Mayr, Christian G; Indiveri, Giacomo; Prodromakis, Themis

2015-01-01

Synaptic plasticity plays a crucial role in allowing neural networks to learn and adapt to various input environments. Neuromorphic systems need to implement plastic synapses to obtain basic "cognitive" capabilities such as learning. One promising and scalable approach for implementing neuromorphic synapses is to use nano-scale memristors as synaptic elements. In this paper we propose a hybrid CMOS-memristor system comprising CMOS neurons interconnected through TiO2-x memristors, and spike-based learning circuits that modulate the conductance of the memristive synapse elements according to a spike-based Perceptron plasticity rule. We highlight a number of advantages for using this spike-based plasticity rule as compared to other forms of spike timing dependent plasticity (STDP) rules. We provide experimental proof-of-concept results with two silicon neurons connected through a memristive synapse that show how the CMOS plasticity circuits can induce stable changes in memristor conductances, giving rise to increased synaptic strength after a potentiation episode and to decreased strength after a depression episode.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

Memristor-based cellular nonlinear/neural network: design, analysis, and applications.

PubMed

Duan, Shukai; Hu, Xiaofang; Dong, Zhekang; Wang, Lidan; Mazumder, Pinaki

2015-06-01

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Dickson, T. O.; Lacroix, M.-A.; Boret, S.; Gloria, D.; Beerkens, R.; Voinigescu, S. P.

2005-01-01

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S21 of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 μm × 30 μm) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.

Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-01

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro-mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm. PMID:25594598

Mechanically and electrically robust metal-mask design for organic CMOS circuits

NASA Astrophysics Data System (ADS)

Shintani, Michihiro; Qin, Zhaoxing; Kuribara, Kazunori; Ogasahara, Yasuhiro; Hiromoto, Masayuki; Sato, Takashi

2018-04-01

The design of metal masks for fabricating organic CMOS circuits requires the consideration of not only the electrical property of the circuits, but also the mechanical strength of the masks. In this paper, we propose a new design flow for metal masks that realizes coanalysis of the mechanical and electrical properties and enables design exploration considering the trade-off between the two properties. As a case study, we apply a “stitching technique” to the mask design of a ring oscillator and explore the best design. With this technique, mask patterns are divided into separate parts using multiple mask layers to improve the mechanical strength at the cost of high resistance of the vias. By a numerical experiment, the design trade-off of the stitching technique is quantitatively analyzed, and it is demonstrated that the proposed flow is useful for the exploration of the designs of metal masks.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

Ethanol microsensors with a readout circuit manufactured using the CMOS-MEMS technique.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-14

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro -mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

PubMed Central

Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

2014-01-01

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

NASA Astrophysics Data System (ADS)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-07-17

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Linear dynamic range enhancement in a CMOS imager

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Dynamically re-configurable CMOS imagers for an active vision system

NASA Technical Reports Server (NTRS)

Yang, Guang (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors.

PubMed

Zhang, Xiang; Zhao, Jianwen; Dou, Junyan; Tange, Masayoshi; Xu, Weiwei; Mo, Lixin; Xie, Jianjun; Xu, Wenya; Ma, Changqi; Okazaki, Toshiya; Cui, Zheng

2016-09-01

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO 2 thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10 5 , mobility of ≈15 cm 2 V -1 s -1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V dd = 1.5 V) and maximum voltage gain of 30 at V dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V dd of 1 V is achieved. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and implementation of a low-power SOI CMOS receiver

NASA Astrophysics Data System (ADS)

Zencir, Ertan

There is a strong demand for wireless communications in civilian and military applications, and space explorations. This work attempts to implement a low-power, high-performance fully-integrated receiver for deep space communications using Silicon on Insulator (SOI) CMOS technology. Design and implementation of a UHF low-IF receiver front-end in a 0.35-mum SOI CMOS technology are presented. Problems and challenges in implementing a highly integrated receiver at UHF are identified. Low-IF architecture, suitable for low-power design, has been adopted to mitigate the noise at the baseband. Design issues of the receiver building blocks including single-ended and differential LNA's, passive and active mixers, and variable gain/bandwidth complex filters are discussed. The receiver is designed to have a variable conversion gain of more than 100 dB with a 70 dB image rejection and a power dissipation of 45 mW from a 2.5-V supply. Design and measured performance of the LNA's, and the mixer are presented. Measurement results of RF front-end blocks including a single-ended LNA, a differential LNA, and a double-balanced mixer demonstrate the low power realizability of RF front-end circuits in SOI CMOS technology. We also report on the design and simulation of the image-rejecting complex IF filter and the full receiver circuit. Gain, noise, and linearity performance of the receiver components prove the viability of fully integrated low-power receivers in SOI CMOS technology.

Monolithic 3D CMOS Using Layered Semiconductors.

PubMed

Sachid, Angada B; Tosun, Mahmut; Desai, Sujay B; Hsu, Ching-Yi; Lien, Der-Hsien; Madhvapathy, Surabhi R; Chen, Yu-Ze; Hettick, Mark; Kang, Jeong Seuk; Zeng, Yuping; He, Jr-Hau; Chang, Edward Yi; Chueh, Yu-Lun; Javey, Ali; Hu, Chenming

2016-04-06

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

PubMed Central

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

Nanosecond-laser induced crosstalk of CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Fully Digital Arrays of Silicon Photomultipliers (dSiPM) - a Scalable Alternative to Vacuum Photomultiplier Tubes (PMT)

NASA Astrophysics Data System (ADS)

Haemisch, York; Frach, Thomas; Degenhardt, Carsten; Thon, Andreas

Silicon Photomultipliers (SiPMs) have emerged as promising alternative to fast vacuum photomultiplier tubes (PMT). A fully digital implementation of the Silicon Photomultiplier (dSiPM) has been developed in order to overcome the deficiencies and limitations of the so far only analog SiPMs (aSiPMs). Our sensor is based on arrays of single photon avalanche photodiodes (SPADs) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter. In consequence, photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic provides the added benefit of low power consumption and possible integration of data post-processing directly in the sensor. In this overview paper, we discuss the sensor architecture together with its characteristics with a focus on scalability and practicability aspects for applications in medical imaging, high energy- and astrophysics.

CMOS array design automation techniques. [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Ramondetta, P.; Feller, A.; Noto, R.; Lombardi, T.

1975-01-01

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

CMOS based capacitance to digital converter circuit for MEMS sensor

NASA Astrophysics Data System (ADS)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

PubMed

Kawahito, Shoji; Seo, Min-Woong

2016-11-06

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e - rms ) when compared with the CMS gain of two (2.4 e - rms ), or 16 (1.1 e - rms ).

Microelectromechanical accelerometer with resonance-cancelling control circuit including an idle state

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.; Campbell, David V.

2001-01-01

A digital feedback control circuit is disclosed for use in an accelerometer (e.g. a microelectromechanical accelerometer). The digital feedback control circuit, which periodically re-centers a proof mass in response to a sensed acceleration, is based on a sigma-delta (.SIGMA..DELTA.) configuration that includes a notch filter (e.g. a digital switched-capacitor filter) for rejecting signals due to mechanical resonances of the proof mass and further includes a comparator (e.g. a three-level comparator). The comparator generates one of three possible feedback states, with two of the feedback states acting to re-center the proof mass when that is needed, and with a third feedback state being an "idle" state which does not act to move the proof mass when no re-centering is needed. Additionally, the digital feedback control system includes an auto-zero trim capability for calibration of the accelerometer for accurate sensing of acceleration. The digital feedback control circuit can be fabricated using complementary metal-oxide semiconductor (CMOS) technology, bi-CMOS technology or bipolar technology and used in single- and dual-proof-mass accelerometers.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

PubMed Central

Kawahito, Shoji; Seo, Min-Woong

2016-01-01

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e−rms) when compared with the CMS gain of two (2.4 e−rms), or 16 (1.1 e−rms). PMID:27827972

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

The design of high dynamic range ROIC for IRFPAs

NASA Astrophysics Data System (ADS)

Jiang, Dazhao; Liang, Qinghua; Zhang, Qiwen; Chen, Honglei; Ding, Ruijun

2015-10-01

The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

NASA Astrophysics Data System (ADS)

Balali, Moslem; Rezai, Abdalhossein

2018-07-01

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

NASA Astrophysics Data System (ADS)

Balali, Moslem; Rezai, Abdalhossein

2018-03-01

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.

A Coherent VLSI Design Environment.

DTIC Science & Technology

1986-03-31

Schema were a CMOS sorter and a TTL PC board for gathering statistics from a Multibus. Neither design was completed using Schema, but at least in the...technique for automatically adjusting signal delays in an MOS system has been developed. The Dynamic Delay Adjustment (DDA) technique provides...34Synchronization Reliability in CMOS Technology," IEEE J. of Solid - State Circuits, Vol. SC-20, No. 4, pp. 880-883, 1985. * [8] J. Hohl, W. Larsen and L. Schooley

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Demonstration of the Potential of Magnetic Tunnel Junctions for a Universal RAM Technology

NASA Astrophysics Data System (ADS)

Gallagher, William J.

2000-03-01

Over the past four years, tunnel junctions with magnetic electrodes have emerged as promising devices for future magnetoresistive sensing and for information storage. This talk will review advances in these devices, focusing particularly on the use of magnetic tunnel junctions for magnetic random access memory (MRAM). Exchange-biased versions of magnetic tunnel junctions (MTJs) in particular will be shown to have useful properties for forming magnetic memory storage elements in a novel cross-point architecture. Exchange-biased MTJ elements have been made with areas as small as 0.1 square microns and have shown magnetoresistance values exceeding 40 The potential of exchange-biased MTJs for MRAM has been most seriously explored in a demonstration experiment involving the integration of 0.25 micron CMOS technology with a special magnetic tunnel junction "back end." The magnetic back end is based upon multi-layer magnetic tunnel junction growth technology which was developed using research-scale equipment and one-inch size substrates. For the demonstration, the CMOS wafers processed through two metal layers were cut into one-inch squares for depositions of bottom-pinned exchange-biased magnetic tunnel junctions. The samples were then processed through four additional lithographic levels to complete the circuits. The demonstration focused attention on a number of processing and device issues that were addressed successfully enough that key performance aspects of MTJ MRAM were demonstrated in 1 K bit arrays, including reads and writes in less than 10 ns and nonvolatility. While other key issues remain to be addressed, these results suggest that MTJ MRAM might simultaneously provide much of the functionality now provided separately by SRAM, DRAM, and NVRAM.

A High Performance 50% Clock Duty Cycle Regulator

NASA Astrophysics Data System (ADS)

Huang, Peng; Deng, Hong-Hui; Yin, Yong-Sheng

A low-jitter clock duty cycle corrector circuit applied in high performance ADC is presented in the paper, such circuits can change low accuracy input signals with different frequencies into 50% pulse width clock. The result have show that the circuit could lock duty cycle rapidly with an accuracy of 50% ± 1% in 200ns. This circuit have 10%-90% of duty cycle input, and clock jitter could be suppressed to less than 5ps. The method used in the circuit, which provides little relationship with the noise and process mismatch, is widely used Implemented in 0.18μm CMOS process.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

A miniaturized neuroprosthesis suitable for implantation into the brain

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Binkley, David; Blalock, Benjamin; Andersen, Richard; Ulshoefer, Norbert; Johnson, Travis; Del Castillo, Linda

2003-01-01

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Toward Three Dimensional Circuits Formed by Molten-Alloy Driven Self-Assembly

DTIC Science & Technology

2008-12-01

layers. Next, we deposited a lead-free, eutectic Bi-Sn alloy with a 138°C melting point shown in Fig. 2D). First, we evaporated 100nm of Au to...IEEE, 427-429. Chan, V. W. C., P. C. H. Chan, and M. Chan, 2001: Multiple layers of CMOS integrated circuits using recrystallized silicon film

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

PubMed Central

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique.

PubMed

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-01-01

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90 %RH. PMID:25353984

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Siemens, Philips megaproject to yield superchip in 5 years

NASA Astrophysics Data System (ADS)

1985-02-01

The development of computer chips using complementary metal oxide semiconductor (CMOS) memory technology is described. The management planning and marketing strategy of the Philips and Siemens corporations with regard to the memory chip are discussed.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

NASA Astrophysics Data System (ADS)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Design of high-throughput and low-power true random number generator utilizing perpendicularly magnetized voltage-controlled magnetic tunnel junction

NASA Astrophysics Data System (ADS)

Lee, Hochul; Ebrahimi, Farbod; Amiri, Pedram Khalili; Wang, Kang L.

2017-05-01

A true random number generator based on perpendicularly magnetized voltage-controlled magnetic tunnel junction devices (MRNG) is presented. Unlike MTJs used in memory applications where a stable bit is needed to store information, in this work, the MTJ is intentionally designed with small perpendicular magnetic anisotropy (PMA). This allows one to take advantage of the thermally activated fluctuations of its free layer as a stochastic noise source. Furthermore, we take advantage of the voltage dependence of anisotropy to temporarily change the MTJ state into an unstable state when a voltage is applied. Since the MTJ has two energetically stable states, the final state is randomly chosen by thermal fluctuation. The voltage controlled magnetic anisotropy (VCMA) effect is used to generate the metastable state of the MTJ by lowering its energy barrier. The proposed MRNG achieves a high throughput (32 Gbps) by implementing a 64 ×64 MTJ array into CMOS circuits and executing operations in a parallel manner. Furthermore, the circuit consumes very low energy to generate a random bit (31.5 fJ/bit) due to the high energy efficiency of the voltage-controlled MTJ switching.

Fault tolerant system based on IDDQ testing

NASA Astrophysics Data System (ADS)

Guibane, Badi; Hamdi, Belgacem; Mtibaa, Abdellatif; Bensalem, Brahim

2018-06-01

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

NASA Astrophysics Data System (ADS)

Kim, Y.; Pham, C.; Chang, J. P.

2015-02-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal-oxide-semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the materials’ full potential.

Moving Beyond 3D Hetero-Integration and Towards Monolithic Integration of Phase-Change RF Switches with SiGe BiCMOS

DTIC Science & Technology

2016-03-31

Corporation, Linthicum, Maryland *Corresponding author: Pavel.Borodulin@ngc.com Abstract: A chip -scale, highly-reconfigurable transmitter and...the technology has been used in a chip -scale, reconfigurable receiver demonstration and ongoing efforts to increase the level of performance and...circuit (RF-FPGA). It consists of a heterogeneous assembly of a SiGe BiCMOS chip with multiple 3D-integrated, low-loss, phase-change switch chiplets

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Atomic memory access hardware implementations

DOEpatents

Ahn, Jung Ho; Erez, Mattan; Dally, William J

2015-02-17

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

Driver-receiver combined optical transceiver modules for bidirectional optical interconnection

NASA Astrophysics Data System (ADS)

Park, Hyo-Hoon; Kang, Sae-Kyoung; Kim, Do-Won; Nga, Nguyen T. H.; Hwang, Sung-Hwan; Lee, Tae-Woo

2008-02-01

We review a bidirectional optical link scheme for memory-interface applications. A driver-receiver combined optical transceiver (TRx) modules was demonstrated on an optical printed-circuit board (OPCB) platform. To select the bidirectional electric input/output signals, a driver-receiver combined TRx IC with a switching function was designed in 0.18-μm CMOS technology. The TRx IC was integrated with VCSEL/PD chips for optical link in the TRx module. The optical TRx module was assembled on a fiber-embedded OPCB, employing a 90°-bent fiber connector for 90° deflection of light beams between the TRx module and the OPCB. The TRx module and the 90° connector were passively assembled on the OPCB, using ferrule-type guide pins/ holes. Employing these constituent components, the bidirectional optical link between a pair of TRx modules has been successfully demonstrated up to 1.25 Gb/s on the OPCB.

Interface engineering of semiconductor/dielectric heterojunctions toward functional organic thin-film transistors.

PubMed

Zhang, Hongtao; Guo, Xuefeng; Hui, Jingshu; Hu, Shuxin; Xu, Wei; Zhu, Daoben

2011-11-09

Interface modification is an effective and promising route for developing functional organic field-effect transistors (OFETs). In this context, however, researchers have not created a reliable method of functionalizing the interfaces existing in OFETs, although this has been crucial for the technological development of high-performance CMOS circuits. Here, we demonstrate a novel approach that enables us to reversibly photocontrol the carrier density at the interface by using photochromic spiropyran (SP) self-assembled monolayers (SAMs) sandwiched between active semiconductors and gate insulators. Reversible changes in dipole moment of SPs in SAMs triggered by lights with different wavelengths produce two distinct built-in electric fields on the OFET that can modulate the channel conductance and consequently threshold voltage values, thus leading to a low-cost noninvasive memory device. This concept of interface functionalization offers attractive new prospects for the development of organic electronic devices with tailored electronic and other properties.

Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Roy, Kaushik

2018-03-01

“Spintronics” refers to the understanding of the physics of electron spin-related phenomena. While most of the significant advancements in this field has been driven primarily by memory, recent research has demonstrated that various facets of the underlying physics of spin transport and manipulation can directly mimic the functionalities of the computational primitives in neuromorphic computation, i.e., the neurons and synapses. Given the potential of these spintronic devices to implement bio-mimetic computations at very low terminal voltages, several spin-device structures have been proposed as the core building blocks of neuromorphic circuits and systems to implement brain-inspired computing. Such an approach is expected to play a key role in circumventing the problems of ever-increasing power dissipation and hardware requirements for implementing neuro-inspired algorithms in conventional digital CMOS technology. Perspectives on spin-enabled neuromorphic computing, its status, and challenges and future prospects are outlined in this review article.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

CMOS single-stage input-powered bridge rectifier with boost switch and duty cycle control

NASA Astrophysics Data System (ADS)

Radzuan, Roskhatijah; Mohd Salleh, Mohd Khairul; Hamzah, Mustafar Kamal; Ab Wahab, Norfishah

2017-06-01

This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement.

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

NASA Astrophysics Data System (ADS)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

NASA Astrophysics Data System (ADS)

Li, Y.-Q.; Wang, H.-B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S.-T.; He, A.-L.; Guo, G.; Baeg, S. H.; Wen, S.-J.; Wong, R.; Chen, M.; Wu, Q.

2017-06-01

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

Superconductor Digital Electronics: -- Current Status, Future Prospects

NASA Astrophysics Data System (ADS)

Mukhanov, Oleg

2011-03-01

Two major applications of superconductor electronics: communications and supercomputing will be presented. These areas hold a significant promise of a large impact on electronics state-of-the-art for the defense and commercial markets stemming from the fundamental advantages of superconductivity: simultaneous high speed and low power, lossless interconnect, natural quantization, and high sensitivity. The availability of relatively small cryocoolers lowered the foremost market barrier for cryogenically-cooled superconductor electronic systems. These fundamental advantages enabled a novel Digital-RF architecture - a disruptive technological approach changing wireless communications, radar, and surveillance system architectures dramatically. Practical results were achieved for Digital-RF systems in which wide-band, multi-band radio frequency signals are directly digitized and digital domain is expanded throughout the entire system. Digital-RF systems combine digital and mixed signal integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology, superconductor analog filter circuits, and semiconductor post-processing circuits. The demonstrated cryocooled Digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals, enabling multi-net data links, and performing signal acquisition from HF to L-band with 30 GHz clock frequencies. In supercomputing, superconductivity leads to the highest energy efficiencies per operation. Superconductor technology based on manipulation and ballistic transfer of magnetic flux quanta provides a superior low-power alternative to CMOS and other charge-transfer based device technologies. The fundamental energy consumption in SFQ circuits defined by flux quanta energy 2 x 10-19 J. Recently, a novel energy-efficient zero-static-power SFQ technology, eSFQ/ERSFQ was invented, which retains all advantages of standard RSFQ circuits: high-speed, dc power, internal memory. The voltage bias regulation, determined by SFQ clock, enables the zero-power at zero-activity regimes, indispensable for sensor and quantum bit readout.

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

NASA Astrophysics Data System (ADS)

Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan

2018-01-01

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V. He received 2016 International Low Power Design Contest Award from ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from Univ. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008, 2001, and 1999 Samsung Humantec Thesis Award and, 2005 ETRI Journal Paper of the Year Award. He is an author/co-author of +100 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed- mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an associate editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.

Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMs

NASA Astrophysics Data System (ADS)

Diehl, S. E.; Ochoa, A., Jr.; Dressendorfer, P. V.; Koga, P.; Kolasinski, W. A.

1982-12-01

Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Similarity between the response of memristive and memcapacitive circuits subjected to ramped voltage

NASA Astrophysics Data System (ADS)

Kanygin, Mikhail A.; Katkov, Mikhail V.; Pershin, Yuriy V.

2017-07-01

We report a similar feature in the response of resistor-memristor and capacitor-memcapacitor circuits with threshold-type memory devices driven by triangular waveform voltage. In both cases, the voltage across the memory device is stabilized during the switching of the memory device state. While in the memristive circuit this feature is observed when the applied voltage changes in one direction, the memcapacitive circuit with a ferroelectric memcapacitor demonstrates the voltage stabilization effect at both sweep directions. The discovered behavior of capacitor-memcapacitor circuit is also demonstrated experimentally. We anticipate that our observation can be used in the design of electronic circuits with emergent memory devices as well as in the identification and characterization of memory effects in threshold-type memory devices.

Design for low-power and reliable flexible electronics

NASA Astrophysics Data System (ADS)

Huang, Tsung-Ching (Jim)

Flexible electronics are emerging as an alternative to conventional Si electronics for large-area low-cost applications such as e-paper, smart sensors, and disposable RFID tags. By utilizing inexpensive manufacturing methods such as ink-jet printing and roll-to-roll imprinting, flexible electronics can be made on low-cost plastics just like printing a newspaper. However, the key elements of exible electronics, thin-film transistors (TFTs), have slower operating speeds and less reliability than their Si electronics counterparts. Furthermore, depending on the material property, TFTs are usually mono-type -- either p- or n-type -- devices. Making air-stable complementary TFT circuits is very challenging and not applicable to most TFT technologies. Existing design methodologies for Si electronics, therefore, cannot be directly applied to exible electronics. Other inhibiting factors such as high supply voltage, large process variation, and lack of trustworthy device modeling also make designing larger-scale and robust TFT circuits a significant challenge. The major goal of this dissertation is to provide a viable solution for robust circuit design in exible electronics. I will first introduce a reliability simulation framework that can predict the degraded TFT circuits' performance under bias-stress. This framework has been validated using the amorphous-silicon (a-Si) TFT scan driver for TFT-LCD displays. To reuse the existing CMOS design ow for exible electronics, I propose a Pseudo-CMOS cell library that can make TFT circuits operable under low supply voltage and which has post-fabrication tunability for reliability and performance enhancement. This cell library has been validated using 2V self-assembly-monolayer (SAM) organic TFTs with a low-cost shadow-mask deposition process. I will also demonstrate a 3-bit 1.25KS/s Flash ADC in a-Si TFTs, which is based on the proposed Pseudo-CMOS cell library, and explore more possibilities in display, energy, and sensing applications.

Physics Notes.

ERIC Educational Resources Information Center

School Science Review, 1981

1981-01-01

Presents activities, experiments, demonstrations, and equipment for physics instruction, including computer applications of sports biomechanics, vibrating magnetometer, alternative uses for an environmental comparator, CMOS integrated circuit logic tutor, and an activity demonstrating positive and negative leakage. (JN)

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

2012-06-01

Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

Optimized Signaling Method for High-Speed Transmission Channels with Higher Order Transfer Function

NASA Astrophysics Data System (ADS)

Ševčík, Břetislav; Brančík, Lubomír; Kubíček, Michal

2017-08-01

In this paper, the selected results from testing of optimized CMOS friendly signaling method for high-speed communications over cables and printed circuit boards (PCBs) are presented and discussed. The proposed signaling scheme uses modified concept of pulse width modulated (PWM) signal which enables to better equalize significant channel losses during data high-speed transmission. Thus, the very effective signaling method to overcome losses in transmission channels with higher order transfer function, typical for long cables and multilayer PCBs, is clearly analyzed in the time and frequency domain. Experimental results of the measurements include the performance comparison of conventional PWM scheme and clearly show the great potential of the modified signaling method for use in low power CMOS friendly equalization circuits, commonly considered in modern communication standards as PCI-Express, SATA or in Multi-gigabit SerDes interconnects.

Subwavelength InSb-based Slot wavguides for THz transport: concept and practical implementations.

PubMed

Ma, Youqiao; Zhou, Jun; Pištora, Jaromír; Eldlio, Mohamed; Nguyen-Huu, Nghia; Maeda, Hiroshi; Wu, Qiang; Cada, Michael

2016-12-07

Seeking better surface plasmon polariton (SPP) waveguides is of critical importance to construct the frequency-agile terahertz (THz) front-end circuits. We propose and investigate here a new class of semiconductor-based slot plasmonic waveguides for subwavelength THz transport. Optimizations of the key geometrical parameters demonstrate its better guiding properties for simultaneous realization of long propagation lengths (up to several millimeters) and ultra-tight mode confinement (~λ 2 /530) in the THz spectral range. The feasibility of the waveguide for compact THz components is also studied to lay the foundations for its practical implementations. Importantly, the waveguide is compatible with the current complementary metal-oxide-semiconductor (CMOS) fabrication technique. We believe the proposed waveguide configuration could offer a potential for developing a CMOS plasmonic platform and can be designed into various components for future integrated THz circuits (ITCs).

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

PubMed

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

Integration of nanoscale memristor synapses in neuromorphic computing architectures

NASA Astrophysics Data System (ADS)

Indiveri, Giacomo; Linares-Barranco, Bernabé; Legenstein, Robert; Deligeorgis, George; Prodromakis, Themistoklis

2013-09-01

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

PubMed

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-10-16

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

PubMed

Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

2017-07-01

Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

A novel CMOS transducer for giant magnetoresistance sensors.

PubMed

Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

2017-02-01

In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μm CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Recent Trends in Spintronics-Based Nanomagnetic Logic

NASA Astrophysics Data System (ADS)

Das, Jayita; Alam, Syed M.; Bhanja, Sanjukta

2014-09-01

With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.

A 0.2 V Micro-Electromechanical Switch Enabled by a Phase Transition.

PubMed

Dong, Kaichen; Choe, Hwan Sung; Wang, Xi; Liu, Huili; Saha, Bivas; Ko, Changhyun; Deng, Yang; Tom, Kyle B; Lou, Shuai; Wang, Letian; Grigoropoulos, Costas P; You, Zheng; Yao, Jie; Wu, Junqiao

2018-04-01

Micro-electromechanical (MEM) switches, with advantages such as quasi-zero leakage current, emerge as attractive candidates for overcoming the physical limits of complementary metal-oxide semiconductor (CMOS) devices. To practically integrate MEM switches into CMOS circuits, two major challenges must be addressed: sub 1 V operating voltage to match the voltage levels in current circuit systems and being able to deliver at least millions of operating cycles. However, existing sub 1 V mechanical switches are mostly subject to significant body bias and/or limited lifetimes, thus failing to meet both limitations simultaneously. Here 0.2 V MEM switching devices with ≳10 6 safe operating cycles in ambient air are reported, which achieve the lowest operating voltage in mechanical switches without body bias reported to date. The ultralow operating voltage is mainly enabled by the abrupt phase transition of nanolayered vanadium dioxide (VO 2 ) slightly above room temperature. The phase-transition MEM switches open possibilities for sub 1 V hybrid integrated devices/circuits/systems, as well as ultralow power consumption sensors for Internet of Things applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

NASA Astrophysics Data System (ADS)

Hande, Vinayak; Shojaei Baghini, Maryam

2015-08-01

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/°C is achieved over -25 to 125 °C temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm2

A 0.7 V 6.66-9.36 GHz wide tuning range CMOS LC VCO with small chip size

NASA Astrophysics Data System (ADS)

Chen, Jun-Da; Zhang, Jie

2017-10-01

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is -110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about -1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about -180.7 and -191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1982-01-01

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

From Contextual Fear to a Dynamic View of Memory Systems

PubMed Central

Fanselow, Michael S

2009-01-01

The brain does not learn and remember in a unitary fashion. Rather, different circuits specialize in certain classes of problems and encode different types of information. Damage to one of these systems typically results in amnesia only for the form of memory that is the affected region's specialty. How does the brain allocate a specific category of memory to a particular circuit? This question has received little attention. The currently dominant view, Multiple Memory Systems Theory, assumes that such abilities are hard-wired. Using fear conditioning as a paradigmatic case, I propose an alternative model in which mnemonic processing is allocated to specific circuits through a dynamic process. Potential circuits compete to form memories with the most efficient circuits emerging as winners. However, alternate circuits compensate when these “primary” circuits are compromised. PMID:19939724

An Autonomous Circuit for the Measurement of Photovoltaic Devices Parameters.

DTIC Science & Technology

1986-09-01

Comparison Data, Gallium Arsenide ................ 80 A 7 A,. TABLE OF SYMBOLS A Curve Fitting Constant ADC Analog to Digital Converter AMO Air-Mass-Zero...in Radiation Fluence in the Logarithmic Region CMOS Complementary Metal-Oxide Semiconductor DAC Digital to Analog Converter DC Direct Current Dp Hole...characteristics of individual solar cells. A novel circuit is developed that uses a microprocessor controlled Digital to Analog Converter (DAC) to obtain

Adaptive neuro fuzzy inference system-based power estimation method for CMOS VLSI circuits

NASA Astrophysics Data System (ADS)

Vellingiri, Govindaraj; Jayabalan, Ramesh

2018-03-01

Recent advancements in very large scale integration (VLSI) technologies have made it feasible to integrate millions of transistors on a single chip. This greatly increases the circuit complexity and hence there is a growing need for less-tedious and low-cost power estimation techniques. The proposed work employs Back-Propagation Neural Network (BPNN) and Adaptive Neuro Fuzzy Inference System (ANFIS), which are capable of estimating the power precisely for the complementary metal oxide semiconductor (CMOS) VLSI circuits, without requiring any knowledge on circuit structure and interconnections. The ANFIS to power estimation application is relatively new. Power estimation using ANFIS is carried out by creating initial FIS modes using hybrid optimisation and back-propagation (BP) techniques employing constant and linear methods. It is inferred that ANFIS with the hybrid optimisation technique employing the linear method produces better results in terms of testing error that varies from 0% to 0.86% when compared to BPNN as it takes the initial fuzzy model and tunes it by means of a hybrid technique combining gradient descent BP and mean least-squares optimisation algorithms. ANFIS is the best suited for power estimation application with a low RMSE of 0.0002075 and a high coefficient of determination (R) of 0.99961.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

NASA Technical Reports Server (NTRS)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

Modeling of SONOS Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

2011-01-01

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective

NASA Astrophysics Data System (ADS)

Das, Kushal; Lehmann, Torsten

2014-07-01

The effect of ultra low operating temperature on mismatch among identically designed Silicon-on-Sapphire CMOS devices is investigated in detail from a circuit design view point. The evolution of transistor matching properties for different operating conditions at both room and 4.2 K temperature are presented. The statistical analysis reveals that mismatch at low temperature is effectively unrelated to that at room temperature, which disagrees with previously published literature. The measurement data was used to extract key transistor parameters and the consequence of temperature lowering on their respective variance is estimated. We find that standard deviation of the threshold-voltage mismatch deteriorates by a factor ∼2 at 4.2 K temperature. Similar to room temperature operation, mismatch at 4.2 K is bias point dependent and the degradation of matching at very low temperature depends to some extent on how the bias point shifts upon cooling.

New readout integrated circuit using continuous time fixed pattern noise correction

NASA Astrophysics Data System (ADS)

Dupont, Bertrand; Chammings, G.; Rapellin, G.; Mandier, C.; Tchagaspanian, M.; Dupont, Benoit; Peizerat, A.; Yon, J. J.

2008-04-01

LETI has been involved in IRFPA development since 1978; the design department (LETI/DCIS) has focused its work on new ROIC architecture since many years. The trend is to integrate advanced functions into the CMOS design to achieve cost efficient sensors production. Thermal imaging market is today more and more demanding of systems with instant ON capability and low power consumption. The purpose of this paper is to present the latest developments of fixed pattern noise continuous time correction. Several architectures are proposed, some are based on hardwired digital processing and some are purely analog. Both are using scene based algorithms. Moreover a new method is proposed for simultaneous correction of pixel offsets and sensitivities. In this scope, a new architecture of readout integrated circuit has been implemented; this architecture is developed with 0.18μm CMOS technology. The specification and the application of the ROIC are discussed in details.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

CMOS image sensor with organic photoconductive layer having narrow absorption band and proposal of stack type solid-state image sensors

NASA Astrophysics Data System (ADS)

Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi

2006-02-01

Digital still cameras overtook film cameras in Japanese market in 2000 in terms of sales volume owing to their versatile functions. However, the image-capturing capabilities such as sensitivity and latitude of color films are still superior to those of digital image sensors. In this paper, we attribute the cause for the high performance of color films to their multi-layered structure, and propose the solid-state image sensors with stacked organic photoconductive layers having narrow absorption bands on CMOS read-out circuits.

Application specific serial arithmetic arrays

NASA Technical Reports Server (NTRS)

Winters, K.; Mathews, D.; Thompson, T.

1990-01-01

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braiman, Yehuda; Neschke, Brendan; Nair, Niketh S.

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Design and development of cell queuing, processing, and scheduling modules for the iPOINT input-buffered ATM testbed

NASA Astrophysics Data System (ADS)

Duan, Haoran

1997-12-01

This dissertation presents the concepts, principles, performance, and implementation of input queuing and cell-scheduling modules for the Illinois Pulsar-based Optical INTerconnect (iPOINT) input-buffered Asynchronous Transfer Mode (ATM) testbed. Input queuing (IQ) ATM switches are well suited to meet the requirements of current and future ultra-broadband ATM networks. The IQ structure imposes minimum memory bandwidth requirements for cell buffering, tolerates bursty traffic, and utilizes memory efficiently for multicast traffic. The lack of efficient cell queuing and scheduling solutions has been a major barrier to build high-performance, scalable IQ-based ATM switches. This dissertation proposes a new Three-Dimensional Queue (3DQ) and a novel Matrix Unit Cell Scheduler (MUCS) to remove this barrier. 3DQ uses a linked-list architecture based on Synchronous Random Access Memory (SRAM) to combine the individual advantages of per-virtual-circuit (per-VC) queuing, priority queuing, and N-destination queuing. It avoids Head of Line (HOL) blocking and provides per-VC Quality of Service (QoS) enforcement mechanisms. Computer simulation results verify the QoS capabilities of 3DQ. For multicast traffic, 3DQ provides efficient usage of cell buffering memory by storing multicast cells only once. Further, the multicast mechanism of 3DQ prevents a congested destination port from blocking other less- loaded ports. The 3DQ principle has been prototyped in the Illinois Input Queue (iiQueue) module. Using Field Programmable Gate Array (FPGA) devices, SRAM modules, and integrated on a Printed Circuit Board (PCB), iiQueue can process incoming traffic at 800 Mb/s. Using faster circuit technology, the same design is expected to operate at the OC-48 rate (2.5 Gb/s). MUCS resolves the output contention by evaluating the weight index of each candidate and selecting the heaviest. It achieves near-optimal scheduling and has a very short response time. The algorithm originates from a heuristic strategy that leads to 'socially optimal' solutions, yielding a maximum number of contention-free cells being scheduled. A novel mixed digital-analog circuit has been designed to implement the MUCS core functionality. The MUCS circuit maps the cell scheduling computation to the capacitor charging and discharging procedures that are conducted fully in parallel. The design has a uniform circuit structure, low interconnect counts, and low chip I/O counts. Using 2 μm CMOS technology, the design operates on a 100 MHz clock and finds a near-optimal solution within a linear processing time. The circuit has been verified at the transistor level by HSPICE simulation. During this research, a five-port IQ-based optoelectronic iPOINT ATM switch has been developed and demonstrated. It has been fully functional with an aggregate throughput of 800 Mb/s. The second-generation IQ-based switch is currently under development. Equipped with iiQueue modules and MUCS module, the new switch system will deliver a multi-gigabit aggregate throughput, eliminate HOL blocking, provide per-VC QoS, and achieve near-100% link bandwidth utilization. Complete documentation of input modules and trunk module for the existing testbed, and complete documentation of 3DQ, iiQueue, and MUCS for the second-generation testbed are given in this dissertation.

Implementation of Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

2000-01-01

Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

NASA Technical Reports Server (NTRS)

Cable, J. S.; Carter, J. R.; Witteles, A. A.

1986-01-01

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Ultralow-Loss CMOS Copper Plasmonic Waveguides.

PubMed

Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

2016-01-13

Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.

PubMed

Zhang, Deming; Zeng, Lang; Cao, Kaihua; Wang, Mengxing; Peng, Shouzhong; Zhang, Yue; Zhang, Youguang; Klein, Jacques-Olivier; Wang, Yu; Zhao, Weisheng

2016-08-01

Artificial synaptic devices implemented by emerging post-CMOS non-volatile memory technologies such as Resistive RAM (RRAM) have made great progress recently. However, it is still a big challenge to fabricate stable and controllable multilevel RRAM. Benefitting from the control of electron spin instead of electron charge, spintronic devices, e.g., magnetic tunnel junction (MTJ) as a binary device, have been explored for neuromorphic computing with low power dissipation. In this paper, a compound spintronic device consisting of multiple vertically stacked MTJs is proposed to jointly behave as a synaptic device, termed as compound spintronic synapse (CSS). Based on our theoretical and experimental work, it has been demonstrated that the proposed compound spintronic device can achieve designable and stable multiple resistance states by interfacial and materials engineering of its components. Additionally, a compound spintronic neuron (CSN) circuit based on the proposed compound spintronic device is presented, enabling a multi-step transfer function. Then, an All Spin Artificial Neural Network (ASANN) is constructed with the CSS and CSN circuit. By conducting system-level simulations on the MNIST database for handwritten digital recognition, the performance of such ASANN has been investigated. Moreover, the impact of the resolution of both the CSS and CSN and device variation on the system performance are discussed in this work.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Efficient design of CMOS TSC checkers

NASA Technical Reports Server (NTRS)

Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

1990-01-01

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications

NASA Astrophysics Data System (ADS)

Jackson, Suzy A.

2004-06-01

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 μm RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

NASA Astrophysics Data System (ADS)

Chen, R. M.; Mahatme, N. N.; Diggins, Z. J.; Wang, L.; Zhang, E. X.; Chen, Y. P.; Liu, Y. N.; Narasimham, B.; Witulski, A. F.; Bhuva, B. L.; Fleetwood, D. M.

2017-08-01

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

NASA Technical Reports Server (NTRS)

Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

1979-01-01

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

Using multiple-accumulator CMACs to improve efficiency of the X part of an input-buffered FX correlator

NASA Astrophysics Data System (ADS)

Lapshev, Stepan; Hasan, S. M. Rezaul

2017-04-01

This paper presents the approach of using complex multiplier-accumulators (CMACs) with multiple accumulators to reduce the total number of memory operations in an input-buffered architecture for the X part of an FX correlator. A processing unit of this architecture uses an array of CMACs that are reused for different groups of baselines. The disadvantage of processing correlations in this way is that each input data sample has to be read multiple times from the memory because each input signal is used in many of these baseline groups. While a one-accumulator CMAC cannot switch to a different baseline until it is finished integrating the current one, a multiple-accumulator CMAC can. Thus, the array of multiple-accumulator CMACs can switch between processing different baselines that share some input signals at any moment to reuse the current data in the processing buffers. In this way significant reductions in the number of memory read operations are achieved with only a few accumulators per CMAC. For example, for a large number of input signals three-accumulator CMACs reduce the total number of memory operations by more than a third. Simulated energy measurements of four VLSI designs in a high-performance 28 nm CMOS technology are presented in this paper to demonstrate that using multiple accumulators can also lead to reduced power dissipation of the processing array. Using three accumulators as opposed to one has been found to reduce the overall energy of 8-bit CMACs by 1.4% through the reduction of the switching activity within their circuits, which is in addition to a more than 30% reduction in the memory.

Persistent activity in a recurrent circuit underlies courtship memory in Drosophila.

PubMed

Zhao, Xiaoliang; Lenek, Daniela; Dag, Ugur; Dickson, Barry J; Keleman, Krystyna

2018-01-11

Recurrent connections are thought to be a common feature of the neural circuits that encode memories, but how memories are laid down in such circuits is not fully understood. Here we present evidence that courtship memory in Drosophila relies on the recurrent circuit between mushroom body gamma (MBγ), M6 output, and aSP13 dopaminergic neurons. We demonstrate persistent neuronal activity of aSP13 neurons and show that it transiently potentiates synaptic transmission from MBγ>M6 neurons. M6 neurons in turn provide input to aSP13 neurons, prolonging potentiation of MB γ >M6 synapses over time periods that match short-term memory. These data support a model in which persistent aSP13 activity within a recurrent circuit lays the foundation for a short-term memory. © 2018, Zhao et al.

Persistent activity in a recurrent circuit underlies courtship memory in Drosophila

PubMed Central

Zhao, Xiaoliang; Lenek, Daniela; Dag, Ugur; Dickson, Barry J

2018-01-01

Recurrent connections are thought to be a common feature of the neural circuits that encode memories, but how memories are laid down in such circuits is not fully understood. Here we present evidence that courtship memory in Drosophila relies on the recurrent circuit between mushroom body gamma (MBγ), M6 output, and aSP13 dopaminergic neurons. We demonstrate persistent neuronal activity of aSP13 neurons and show that it transiently potentiates synaptic transmission from MBγ>M6 neurons. M6 neurons in turn provide input to aSP13 neurons, prolonging potentiation of MBγ>M6 synapses over time periods that match short-term memory. These data support a model in which persistent aSP13 activity within a recurrent circuit lays the foundation for a short-term memory. PMID:29322941

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Possible Circuit Architectures for Molecular Nanoelectronics

NASA Astrophysics Data System (ADS)

Likharev, Konstantin

2003-03-01

Chemically-directed self-assembly of molecular devices is apparently the only feasible way to continue the fast progress of microelectronics after its Moore-Laws-based development runs into the wall of physical and economic limitations [1]. The architectures of VLSI circuits using such devices should be substantially fault-tolerant and accommodate other their features including low transconductance. The most significant feature of all promising suggested architectures is the hybridization of three technologies: advanced CMOS, simple nanowire arrays, and molecular devices self-assembling on these wires. Molecular memory arrays may have a simple structure, and their simple prototypes have already been implemented experimentally [2]. In contrast, the logic circuit development is just starting. I will describe a family of neuromorphic networks based on so-called CrossNet arrays [3] that look promising for advanced information processing, starting from fast image recognition and beyond. This architecture may combine very high density (above 10^12 functions per cm^2) and relatively high speed (100-ns-scale latency of cell-to-cell communications) at acceptable power consumption. In future, these features may allow to put an artificial analog of the human cerebral cortex, capable of processing information and (hopefully) self-evolution at 4 to 5 orders of magnitude faster than its biological prototype, on a 20x20 cm^2 silicon wafer. [1] K. Likharev, "Electronics Below 20-nm", see http://rsfq1.physics.sunysb.edu/ likharev/nano/ForMorkoc.pdf. [2] See, e.g, http://nanotechweb.org/articles/news/1/9/8/1. [3] O. Turel and K. Likharev, Int. J. of Circuit Theory and Applications 31, No.1 (2003); see http://rsfq1.physics.sunysb.edu/ likharev/nano/Preprint070102.pdf.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Photodiode area effect on performance of X-ray CMOS active pixel sensors

NASA Astrophysics Data System (ADS)

Kim, M. S.; Kim, Y.; Kim, G.; Lim, K. T.; Cho, G.; Kim, D.

2018-02-01

Compared to conventional TFT-based X-ray imaging devices, CMOS-based X-ray imaging sensors are considered next generation because they can be manufactured in very small pixel pitches and can acquire high-speed images. In addition, CMOS-based sensors have the advantage of integration of various functional circuits within the sensor. The image quality can also be improved by the high fill-factor in large pixels. If the size of the subject is small, the size of the pixel must be reduced as a consequence. In addition, the fill factor must be reduced to aggregate various functional circuits within the pixel. In this study, 3T-APS (active pixel sensor) with photodiodes of four different sizes were fabricated and evaluated. It is well known that a larger photodiode leads to improved overall performance. Nonetheless, if the size of the photodiode is > 1000 μm2, the degree to which the sensor performance increases as the photodiode size increases, is reduced. As a result, considering the fill factor, pixel-pitch > 32 μm is not necessary to achieve high-efficiency image quality. In addition, poor image quality is to be expected unless special sensor-design techniques are included for sensors with a pixel pitch of 25 μm or less.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors.

PubMed

Ge, Xiaoliang; Theuwissen, Albert J P

2018-02-27

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

A low power and low phase-noise 91 96 GHz VCO in 90 nm CMOS

NASA Astrophysics Data System (ADS)

Lin, Yo-Sheng; Lan, Kai-Siang; Chuang, Ming-Yuan; Lin, Yu-Ching

2018-06-01

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91 96 GHz, close to the simulated (92.1 96.7 GHz) and the calculated one (92.2 98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of - 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of -188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors †

PubMed Central

Theuwissen, Albert J. P.

2018-01-01

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models. PMID:29495496

Using Polynomials to Simplify Fixed Pattern Noise and Photometric Correction of Logarithmic CMOS Image Sensors

PubMed Central

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-01-01

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. PMID:26501287

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

PubMed

Oh, Sungjin; Ahn, Jae-Hyun; Lee, Sangmin; Ko, Hyoungho; Seo, Jong Mo; Goo, Yong-Sook; Cho, Dong-il Dan

2015-01-01

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 μm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 μ m × 55 μm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 μA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection.

PubMed

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N

2017-08-23

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

PubMed Central

Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N.

2017-01-01

This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW. PMID:28832523

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Low-temperature crack-free Si3N4 nonlinear photonic circuits for CMOS-compatible optoelectronic co-integration

NASA Astrophysics Data System (ADS)

Casale, Marco; Kerdiles, Sebastien; Brianceau, Pierre; Hugues, Vincent; El Dirani, Houssein; Sciancalepore, Corrado

2017-02-01

In this communication, authors report for the first time on the fabrication and testing of Si3N4 non-linear photonic circuits for CMOS-compatible monolithic co-integration with silicon-based optoelectronics. In particular, a novel process has been developed to fabricate low-loss crack-free Si3N4 750-nm-thick films for Kerr-based nonlinear functions featuring full thermal budget compatibility with existing Silicon photonics and front-end Si optoelectronics. Briefly, differently from previous and state-of-the-art works, our nonlinear nitride-based platform has been realized without resorting to commonly-used high-temperature annealing ( 1200°C) of the film and its silica upper-cladding used to break N-H bonds otherwise causing absorption in the C-band and destroying its nonlinear functionality. Furthermore, no complex and fabrication-intolerant Damascene process - as recently reported earlier this year - aimed at controlling cracks generated in thick tensile-strained Si3N4 films has been used as well. Instead, a tailored Si3N4 multiple-step film deposition in 200-mm LPCVD-based reactor and subsequent low-temperature (400°C) PECVD oxide encapsulation have been used to fabricate the nonlinear micro-resonant circuits aiming at generating optical frequency combs via optical parametric oscillators (OPOs), thus allowing the monolithic co-integration of such nonlinear functions on existing CMOS-compatible optoelectronics, for both active and passive components such as, for instance, silicon modulators and wavelength (de-)multiplexers. Experimental evidence based on wafer-level statistics show nitride-based 112-μm-radius ring resonators using such low-temperature crack-free nitride film exhibiting quality factors exceeding Q >3 x 105, thus paving the way to low-threshold power-efficient Kerr-based comb sources and dissipative temporal solitons in the C-band featuring full thermal processing compatibility with Si photonic integrated circuits (Si-PICs).

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Resistive switching phenomena of tungsten nitride thin films with excellent CMOS compatibility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Seok Man; Kim, Hee-Dong; An, Ho-Myoung

2013-12-15

Graphical abstract: - Highlights: • The resistive switching characteristics of WN{sub x} thin films. • Excellent CMOS compatibility WN{sub x} films as a resistive switching material. • Resistive switching mechanism revealed trap-controlled space charge limited conduction. • Good endurance and retention properties over 10{sup 5} cycles, and 10{sup 5} s, respectively - Abstract: We report the resistive switching (RS) characteristics of tungsten nitride (WN{sub x}) thin films with excellent complementary metal-oxide-semiconductor (CMOS) compatibility. A Ti/WN{sub x}/Pt memory cell clearly shows bipolar RS behaviors at a low voltage of approximately ±2.2 V. The dominant conduction mechanisms at low and high resistancemore » states were verified by Ohmic behavior and trap-controlled space-charge-limited conduction, respectively. A conducting filament model by a redox reaction explains the RS behavior in WN{sub x} films. We also demonstrate the memory characteristics during pulse operation, including a high endurance over >10{sup 5} cycles and a long retention time of >10{sup 5} s.« less

A high sensitivity 20Mfps CMOS image sensor with readout speed of 1Tpixel/sec for visualization of ultra-high speed phenomena

NASA Astrophysics Data System (ADS)

Kuroda, R.; Sugawa, S.

2017-02-01

Ultra-high speed (UHS) CMOS image sensors with on-chop analog memories placed on the periphery of pixel array for the visualization of UHS phenomena are overviewed in this paper. The developed UHS CMOS image sensors consist of 400H×256V pixels and 128 memories/pixel, and the readout speed of 1Tpixel/sec is obtained, leading to 10 Mfps full resolution video capturing with consecutive 128 frames, and 20 Mfps half resolution video capturing with consecutive 256 frames. The first development model has been employed in the high speed video camera and put in practical use in 2012. By the development of dedicated process technologies, photosensitivity improvement and power consumption reduction were simultaneously achieved, and the performance improved version has been utilized in the commercialized high-speed video camera since 2015 that offers 10 Mfps with ISO16,000 photosensitivity. Due to the improved photosensitivity, clear images can be captured and analyzed even under low light condition, such as under a microscope as well as capturing of UHS light emission phenomena.

Method for Evaluating the Corrosion Resistance of Aluminum Metallization of Integrated Circuits under Multifactorial Influence

NASA Astrophysics Data System (ADS)

Kolomiets, V. I.

2018-03-01

The influence of complex influence of climatic factors (temperature, humidity) and electric mode (supply voltage) on the corrosion resistance of metallization of integrated circuits has been considered. The regression dependence of the average time of trouble-free operation t on the mentioned factors has been established in the form of a modified Arrhenius equation that is adequate in a wide range of factor values and is suitable for selecting accelerated test modes. A technique for evaluating the corrosion resistance of aluminum metallization of depressurized CMOS integrated circuits has been proposed.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

PubMed

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

A fast-locking PLL with all-digital locked-aid circuit

NASA Astrophysics Data System (ADS)

Kao, Shao-Ku; Hsieh, Fu-Jen

2013-02-01

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

Integrated Circuit Design of 3 Electrode Sensing System Using Two-Stage Operational Amplifier

NASA Astrophysics Data System (ADS)

Rani, S.; Abdullah, W. F. H.; Zain, Z. M.; N, Aqmar N. Z.

2018-03-01

This paper presents the design of a two-stage operational amplifier(op amp) for 3-electrode sensing system readout circuits. The designs have been simulated using 0.13μm CMOS technology from Silterra (Malaysia) with Mentor graphics tools. The purpose of this projects is mainly to design a miniature interfacing circuit to detect the redox reaction in the form of current using standard analog modules. The potentiostat consists of several op amps combined together in order to analyse the signal coming from the 3-electrode sensing system. This op amp design will be used in potentiostat circuit device and to analyse the functionality for each module of the system.

Post-Training Reversible Disconnection of the Ventral Hippocampal-Basolateral Amygdaloid Circuits Impairs Consolidation of Inhibitory Avoidance Memory in Rats

ERIC Educational Resources Information Center

Wang, Gong-Wu; Liu, Jian; Wang, Xiao-Qin

2017-01-01

The ventral hippocampus (VH) and the basolateral amygdala (BLA) are both crucial in inhibitory avoidance (IA) memory. However, the exact role of the VH-BLA circuit in IA memory consolidation is unclear. This study investigated the effect of post-training reversible disconnection of the VH-BLA circuit in IA memory consolidation. Male Wistar rats…

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Automated ILA design for synchronous sequential circuits

NASA Technical Reports Server (NTRS)

Liu, M. N.; Liu, K. Z.; Maki, G. K.; Whitaker, S. R.

1991-01-01

An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.

Design and Implementation of a CMOS Chip for a Prolog

DTIC Science & Technology

1988-03-01

generation scheme . We use the P -circuit [9] with pre-conditioning and post- conditioning 12,3] circuits to generate the carry. The implementation of...system generates vertical microcode for a general purpose processor, the NCR 9300 sys- S tem, from W- code [7]. Three significant pieces of software are...calculation block generating the pro- pagate ( P ) and generate (G) signals needed for carry calculation, and a sum block supplying the final result. The top

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

CMOS nanoelectrode array for all-electrical intracellular electrophysiological imaging

NASA Astrophysics Data System (ADS)

Abbott, Jeffrey; Ye, Tianyang; Qin, Ling; Jorgolli, Marsela; Gertner, Rona S.; Ham, Donhee; Park, Hongkun

2017-05-01

Developing a new tool capable of high-precision electrophysiological recording of a large network of electrogenic cells has long been an outstanding challenge in neurobiology and cardiology. Here, we combine nanoscale intracellular electrodes with complementary metal-oxide-semiconductor (CMOS) integrated circuits to realize a high-fidelity all-electrical electrophysiological imager for parallel intracellular recording at the network level. Our CMOS nanoelectrode array has 1,024 recording/stimulation 'pixels' equipped with vertical nanoelectrodes, and can simultaneously record intracellular membrane potentials from hundreds of connected in vitro neonatal rat ventricular cardiomyocytes. We demonstrate that this network-level intracellular recording capability can be used to examine the effect of pharmaceuticals on the delicate dynamics of a cardiomyocyte network, thus opening up new opportunities in tissue-based pharmacological screening for cardiac and neuronal diseases as well as fundamental studies of electrogenic cells and their networks.

VLSI circuits implementing computational models of neocortical circuits.

PubMed

Wijekoon, Jayawan H B; Dudek, Piotr

2012-09-15

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

NASA Technical Reports Server (NTRS)

Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

2006-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Spintronic Nanodevices for Bioinspired Computing

PubMed Central

Grollier, Julie; Querlioz, Damien; Stiles, Mark D.

2016-01-01

Bioinspired hardware holds the promise of low-energy, intelligent, and highly adaptable computing systems. Applications span from automatic classification for big data management, through unmanned vehicle control, to control for biomedical prosthesis. However, one of the major challenges of fabricating bioinspired hardware is building ultra-high-density networks out of complex processing units interlinked by tunable connections. Nanometer-scale devices exploiting spin electronics (or spintronics) can be a key technology in this context. In particular, magnetic tunnel junctions (MTJs) are well suited for this purpose because of their multiple tunable functionalities. One such functionality, non-volatile memory, can provide massive embedded memory in unconventional circuits, thus escaping the von-Neumann bottleneck arising when memory and processors are located separately. Other features of spintronic devices that could be beneficial for bioinspired computing include tunable fast nonlinear dynamics, controlled stochasticity, and the ability of single devices to change functions in different operating conditions. Large networks of interacting spintronic nanodevices can have their interactions tuned to induce complex dynamics such as synchronization, chaos, soliton diffusion, phase transitions, criticality, and convergence to multiple metastable states. A number of groups have recently proposed bioinspired architectures that include one or several types of spintronic nanodevices. In this paper, we show how spintronics can be used for bioinspired computing. We review the different approaches that have been proposed, the recent advances in this direction, and the challenges toward fully integrated spintronics complementary metal–oxide–semiconductor (CMOS) bioinspired hardware. PMID:27881881

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Single-Chip T/R Module for 1.2 GHz

NASA Technical Reports Server (NTRS)

Moussessian, Alina; Mojarradi, Mohammad; Johnson, Travis; Davis, John; Grigorian, Edwin; Hoffman, James; Caro, Edward; Kuhn, William

2006-01-01

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Interference and memory capacity effects in memristive systems

NASA Astrophysics Data System (ADS)

Hermiz, John; Chang, Ting; Du, Chao; Lu, Wei

2013-02-01

Short-term memory implies the existence of a capacity limit beyond which memory cannot be securely formed and retained. The underlying mechanisms are believed to be two primary factors: decay and interference. Here, we demonstrate through both simulation and experiment that the memory capacity effect can be implemented in a parallel memristor circuit, where decay and interference are achieved by the inherent ion diffusion in the device and the competition for current supply in the circuit, respectively. This study suggests it is possible to emulate high-level biological behaviors with memristor circuits and will stimulate continued studies on memristor-based neuromorphic circuits.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

PubMed

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

PubMed Central

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

2014-01-01

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

Implementation of a wireless ECG acquisition SoC for IEEE 802.15.4 (ZigBee) applications.

PubMed

Wang, Liang-Hung; Chen, Tsung-Yen; Lin, Kuang-Hao; Fang, Qiang; Lee, Shuenn-Yuh

2015-01-01

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effectively acquire ECG signals.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-12-01

rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

Combined Effects of Radio Frequency and Electron Radiation on CMOS Inverters

DTIC Science & Technology

2011-03-01

equipment that comes from taking real- time , in-situ measurements. To overcome this, a test circuit was designed and built to allow for real- time in...situ measurement of the output voltage, current and the inverter power. This test circuit provides real– time measurement of the inverter’s...now. To the “Operator of the Dynamitron at WSU”, thank you for your time , advice, and patience with all of my “why and how” questions. LTC McClory

Single photon detection using Geiger mode CMOS avalanche photodiodes

NASA Astrophysics Data System (ADS)

Lawrence, William G.; Stapels, Christopher; Augustine, Frank L.; Christian, James F.

2005-10-01

Geiger mode Avalanche Photodiodes fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication technology combine high sensitivity detectors with pixel-level auxiliary circuitry. Radiation Monitoring Devices has successfully implemented CMOS manufacturing techniques to develop prototype detectors with active diameters ranging from 5 to 60 microns and measured detection efficiencies of up to 60%. CMOS active quenching circuits are included in the pixel layout. The actively quenched pixels have a quenching time less than 30 ns and a maximum count rate greater than 10 MHz. The actively quenched Geiger mode avalanche photodiode (GPD) has linear response at room temperature over six orders of magnitude. When operating in Geiger mode, these GPDs act as single photon-counting detectors that produce a digital output pulse for each photon with no associated read noise. Thermoelectrically cooled detectors have less than 1 Hz dark counts. The detection efficiency, dark count rate, and after-pulsing of two different pixel designs are measured and demonstrate the differences in the device operation. Additional applications for these devices include nuclear imaging and replacement of photomultiplier tubes in dosimeters.

An all-silicon optical PC-to-PC link utilizing USB

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Alberts, Antonie C.; Venter, Petrus J.; du Plessis, Monuko; Rademeyer, Pieter

2013-02-01

An integrated silicon light source still remains the Holy Grail for integrated optical communication systems. Hot carrier luminescent light sources provide a way to create light in a standard CMOS process, potentially enabling cost effective optical communication between CMOS integrated circuits. In this paper we present a 1 Mb/s integrated silicon optical link for information transfer, targeting a real-world integrated solution by connecting two PCs via a USB port while transferring data optically between the devices. This realization represents the first optical communication product prototype utilizing a CMOS light emitter. The silicon light sources which are implemented in a standard 0.35 μm CMOS technology are electrically modulated and detected using a commercial silicon avalanche photodiode. Data rates exceeding 10 Mb/s using silicon light sources have previously been demonstrated using raw bit streams. In this work data is sent in two half duplex streams accompanied with the separate transmission of a clock. Such an optical communication system could find application in high noise environments where data fidelity, range and cost are a determining factor.

A digital output piezoelectric accelerometer using a Pb(Zr, Ti)O3 thin film array electrically connected in series

NASA Astrophysics Data System (ADS)

Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

2010-10-01

A digital output piezoelectric accelerometer is proposed to realize an ultra-low power consumption wireless sensor node. The accelerometer has patterned piezoelectric thin films (piezoelectric plates) electrically connected in series accompanied by CMOS switches at the end of some of the piezoelectric plates. The connected piezoelectric plates amplify the output voltage without the use of amplifiers. The CMOS switches turn on when the output voltage of the piezoelectric plates is higher than the CMOS threshold voltage. The piezoelectric accelerometer converts the acceleration into a number of on-state CMOS switches, which can be called the digital output. The proposed digital output piezoelectric accelerometer, using Pb(Zr, Ti)O3 (PZT) thin films as the piezoelectric material, was fabricated through a microelectromechanical system (MEMS) microfabrication process. The output voltage was found to be amplified by the number of connected piezoelectric plates. The DC output voltage obtained by using an AC to DC conversion circuit is proportional to the number of connections. The results show the potential for realizing the proposed digital output piezoelectric accelerometer.

Post-training reversible disconnection of the ventral hippocampal-basolateral amygdaloid circuits impairs consolidation of inhibitory avoidance memory in rats.

PubMed

Wang, Gong-Wu; Liu, Jian; Wang, Xiao-Qin

2017-11-01

The ventral hippocampus (VH) and the basolateral amygdala (BLA) are both crucial in inhibitory avoidance (IA) memory. However, the exact role of the VH-BLA circuit in IA memory consolidation is unclear. This study investigated the effect of post-training reversible disconnection of the VH-BLA circuit in IA memory consolidation. Male Wistar rats with implanted guide cannulae were trained with a one-trial IA task, then received immediate intracerebral injections of muscimol or saline, and were tested 24 h later. Muscimol injection into the bilateral BLA, or the unilateral VH and contralateral BLA, but not the unilateral VH and ipsilateral BLA, significantly decreased the retention latencies (versus saline treatment). The results suggest that the VH-BLA circuit could be an important circuit to modulate consolidation of IA memory in rats. © 2017 Wang et al.; Published by Cold Spring Harbor Laboratory Press.

A modeling framework for deriving the structural and functional architecture of a short-term memory microcircuit.

PubMed

Fisher, Dimitry; Olasagasti, Itsaso; Tank, David W; Aksay, Emre R F; Goldman, Mark S

2013-09-04

Although many studies have identified neural correlates of memory, relatively little is known about the circuit properties connecting single-neuron physiology to behavior. Here we developed a modeling framework to bridge this gap and identify circuit interactions capable of maintaining short-term memory. Unlike typical studies that construct a phenomenological model and test whether it reproduces select aspects of neuronal data, we directly fit the synaptic connectivity of an oculomotor memory circuit to a broad range of anatomical, electrophysiological, and behavioral data. Simultaneous fits to all data, combined with sensitivity analyses, revealed complementary roles of synaptic and neuronal recruitment thresholds in providing the nonlinear interactions required to generate the observed circuit behavior. This work provides a methodology for identifying the cellular and synaptic mechanisms underlying short-term memory and demonstrates how the anatomical structure of a circuit may belie its functional organization. Copyright © 2013 Elsevier Inc. All rights reserved.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

PubMed Central

Jeong, Gyu-Seob

2017-01-01

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies. PMID:28841154

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

PubMed

Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

2017-08-25

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Design of Efficient Mirror Adder in Quantum- Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Mishra, Prashant Kumar; Chattopadhyay, Manju K.

2018-03-01

Lower power consumption is an essential demand for portable multimedia system using digital signal processing algorithms and architectures. Quantum dot cellular automata (QCA) is a rising nano technology for the development of high performance ultra-dense low power digital circuits. QCA based several efficient binary and decimal arithmetic circuits are implemented, however important improvements are still possible. This paper demonstrate Mirror Adder circuit design in QCA. We present comparative study of mirror adder cells designed using conventional CMOS technique and mirror adder cells designed using quantum-dot cellular automata. QCA based mirror adders are better in terms of area by order of three.

Associative Pattern Recognition In Analog VLSI Circuits

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1995-01-01

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

Dual redundant core memory systems

NASA Technical Reports Server (NTRS)

Hull, F. E.

1972-01-01

Electronic memory system consisting of series redundant drive switch circuits, triple redundant majority voted memory timing functions, and two data registers to provide functional dual redundancy is described. Signal flow through the circuits is illustrated and equence of events which occur within the memory system is explained.

Memory and cognitive control circuits in mathematical cognition and learning.

PubMed

Menon, V

2016-01-01

Numerical cognition relies on interactions within and between multiple functional brain systems, including those subserving quantity processing, working memory, declarative memory, and cognitive control. This chapter describes recent advances in our understanding of memory and control circuits in mathematical cognition and learning. The working memory system involves multiple parietal-frontal circuits which create short-term representations that allow manipulation of discrete quantities over several seconds. In contrast, hippocampal-frontal circuits underlying the declarative memory system play an important role in formation of associative memories and binding of new and old information, leading to the formation of long-term memories that allow generalization beyond individual problem attributes. The flow of information across these systems is regulated by flexible cognitive control systems which facilitate the integration and manipulation of quantity and mnemonic information. The implications of recent research for formulating a more comprehensive systems neuroscience view of the neural basis of mathematical learning and knowledge acquisition in both children and adults are discussed. © 2016 Elsevier B.V. All rights reserved.

Memory and cognitive control circuits in mathematical cognition and learning

PubMed Central

Menon, V.

2018-01-01

Numerical cognition relies on interactions within and between multiple functional brain systems, including those subserving quantity processing, working memory, declarative memory, and cognitive control. This chapter describes recent advances in our understanding of memory and control circuits in mathematical cognition and learning. The working memory system involves multiple parietal–frontal circuits which create short-term representations that allow manipulation of discrete quantities over several seconds. In contrast, hippocampal–frontal circuits underlying the declarative memory system play an important role in formation of associative memories and binding of new and old information, leading to the formation of long-term memories that allow generalization beyond individual problem attributes. The flow of information across these systems is regulated by flexible cognitive control systems which facilitate the integration and manipulation of quantity and mnemonic information. The implications of recent research for formulating a more comprehensive systems neuroscience view of the neural basis of mathematical learning and knowledge acquisition in both children and adults are discussed. PMID:27339012

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439