Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

NASA Astrophysics Data System (ADS)

Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

2017-06-01

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

Design of ultra-low power biopotential amplifiers for biosignal acquisition applications.

PubMed

Zhang, Fan; Holleman, Jeremy; Otis, Brian P

2012-08-01

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

NASA Astrophysics Data System (ADS)

Riyan, Wang; Jiwei, Huang; Zhengping, Li; Weifeng, Zhang; Longyue, Zeng

2012-03-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

PubMed

Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

2012-07-30

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

PubMed Central

Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

2017-01-01

A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µVrms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter. PMID:28394289

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

NASA Astrophysics Data System (ADS)

Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

2009-05-01

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

A fully integrated neural recording amplifier with DC input stabilization.

PubMed

Mohseni, Pedram; Najafi, Khalil

2004-05-01

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.

Wideband pulse amplifiers for the NECTAr chip

NASA Astrophysics Data System (ADS)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

A Compact Operational Amplifier with Load-Insensitive Stability Compensation for High-Precision Transducer Interface.

PubMed

Yu, Zhanghao; Yang, Xi; Chung, SungWon

2018-01-29

High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation capacitor size is insensitive to the load capacitance and also orders of magnitude smaller compared to the conventional Miller-compensation capacitor that often dominates chip area. By exploiting pole-zero cancellation between a gain-boosting stage and the main amplifier stage, the compensation capacitor of the proposed operational amplifier becomes less dependent of load capacitance, so that it can also operate with a wide range of load capacitance. A prototype operational amplifier designed in 0.13-μm complementary metal-oxide-semiconductor (CMOS) with a 400-fF compensation capacitor occupies 900- μ m 2 chip area and achieves 0.022-2.78-MHz unity gain bandwidth and over 65 ∘ phase margin with a load capacitance of 0.1-15 nF. The prototype amplifier consumes 7.6 μ W from a single 1.0-V supply. For a given compensation capacitor size and a chip area, the prototype design demonstrates the best reported performance trade-off on unity gain bandwidth, maximum stable load capacitance, and power consumption.

A high efficiency PWM CMOS class-D audio power amplifier

NASA Astrophysics Data System (ADS)

Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

2009-02-01

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

On-Chip Integrated Distributed Amplifier and Antenna Systems in SiGe BiCMOS for Transceivers with Ultra-Large Bandwidth

NASA Astrophysics Data System (ADS)

Valerio Testa, Paolo; Klein, Bernhard; Hahnel, Ronny; Plettemeier, Dirk; Carta, Corrado; Ellinger, Frank

2017-09-01

This paper presents an overview of the research work currently being performed within the frame of project DAAB and its successor DAAB-TX towards the integration of ultra-wideband transceivers operating at mm-wave frequencies and capable of data rates up to 100 Gbits-1. Two basic system architectures are being considered: integrating a broadband antenna with a distributed amplifier and integrate antennas centered at adjacent frequencies with broadband active combiners or dividers. The paper discusses in detail the design of such systems and their components, from the distributed amplifiers and combiners, to the broadband silicon antennas and their single-chip integration. All components are designed for fabrication in a commercially available SiGe:C BiCMOS technology. The presented results represent the state of the art in their respective areas: 170 GHz is the highest reported bandwidth for distributed amplifiers integrated in Silicon; 89 GHz is the widest reported bandwidth for integrated-system antennas; the simulated performance of the two antenna integrated receiver spans 105 GHz centered at 148GHz, which would improve the state of the art by a factor in excess of 4 even against III-V implementations, if confirmed by measurements.

2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

PubMed

Lee, Changhyun; Park, Changkun

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2).

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

PubMed Central

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

Wideband low-noise variable-gain BiCMOS transimpedance amplifier

NASA Astrophysics Data System (ADS)

Meyer, Robert G.; Mack, William D.

1994-06-01

A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kilo ohms, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/square root of Hz and input signal-current handling capability of 3 mA.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

A Compact Operational Amplifier with Load-Insensitive Stability Compensation for High-Precision Transducer Interface

PubMed Central

Yang, Xi

2018-01-01

High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation capacitor size is insensitive to the load capacitance and also orders of magnitude smaller compared to the conventional Miller-compensation capacitor that often dominates chip area. By exploiting pole-zero cancellation between a gain-boosting stage and the main amplifier stage, the compensation capacitor of the proposed operational amplifier becomes less dependent of load capacitance, so that it can also operate with a wide range of load capacitance. A prototype operational amplifier designed in 0.13-μm complementary metal–oxide–semiconductor (CMOS) with a 400-fF compensation capacitor occupies 900-μm2 chip area and achieves 0.022–2.78-MHz unity gain bandwidth and over 65∘ phase margin with a load capacitance of 0.1–15 nF. The prototype amplifier consumes 7.6 μW from a single 1.0-V supply. For a given compensation capacitor size and a chip area, the prototype design demonstrates the best reported performance trade-off on unity gain bandwidth, maximum stable load capacitance, and power consumption. PMID:29382183

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35 μm CMOS

NASA Astrophysics Data System (ADS)

Hui, Xu; Jun, Feng; Quan, Liu; Wei, Li

2011-10-01

A 3.125-Gb/s transimpedance amplifier (TIA) for an optical communication system is realized in 0.35 μm CMOS technology. The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point. In addition, noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩ and -3 dB bandwidth of 2.31 GHz. The measured average input referred noise current spectral density is about . The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS. Under a single 3.3-V supply voltage, the TIA consumes only 58.08 mW, including 20 mW from the output buffer. The whole die area is 465 × 435 μm2.

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

NASA Astrophysics Data System (ADS)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Preamplifiers for non-contact capacitive biopotential measurements.

PubMed

Peng, GuoChen; Ignjatovic, Zeljko; Bocko, Mark F

2013-01-01

Non-contact biopotential sensing is an attractive measurement strategy for a number of health monitoring applications, primarily the ECG and the EEG. In all such applications a key technical challenge is the design of a low-noise trans-impedance preamplifier for the typically low-capacitance, high source impedance sensing electrodes. In this paper, we compare voltage and charge amplifier designs in terms of their common mode rejection ratio, noise performance, and frequency response. Both amplifier types employ the same operational-transconductance amplifier (OTA), which was fabricated in a 0.35 um CMOS process. The results show that a charge amplifier configuration has advantages for small electrode-to-subject coupling capacitance values (less than 10 pF--typical of noncontact electrodes) and that the voltage amplifier configuration has advantages for electrode capacitances above 10 pF.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

An integrated CMOS bio-potential amplifier with a feed-forward DC cancellation topology.

PubMed

Parthasarathy, Jayant; Erdman, Arthur G; Redish, Aaron D; Ziaie, Babak

2006-01-01

This paper describes a novel technique to realize an integrated CMOS bio-potential amplifier with a feedforward DC cancellation topology. The amplifier is designed to provide substantial DC cancellation even while amplifying very low frequency signals. More than 80 dB offset rejection ratio is achieved without any external capacitors. The cancellation scheme is robust against process and temperature variations. The amplifier is fabricated through MOSIS AMI 1.5 microm technology (0.05 mm2 area). Measurement results show a gain of 43.5 dB in the pass band (<1 mHz-5 KHz), an input referred noise of 3.66 microVrms, and a current consumption of 22 microA.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

NASA Astrophysics Data System (ADS)

Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

2017-01-01

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Design, simulation and comparative analysis of CNT based cascode operational transconductance amplifiers

NASA Astrophysics Data System (ADS)

Nizamuddin, M.; Loan, Sajad A.; Alamoud, Abdul R.; Abbassi, Shuja A.

2015-10-01

In this work, design and calibrated simulation of carbon nanotube field effect transistor (CNTFET)-based cascode operational transconductance amplifiers (COTA) have been performed. Three structures of CNTFET-based COTAs have been designed using HSPICE and have been compared with the conventional CMOS-based COTAs. The proposed COTAs include one using pure CNTFETs and two others that employ CNTFETs, as well as the conventional MOSFETs. The simulation study has revealed that the CNTFET-based COTAs have significantly outperformed the conventional MOSFET-based COTAs. A significant increase in dc gain, output resistance and slew rate of 81.4%, 25% and 13.2%, respectively, have been achieved in the proposed pure CNT-based COTA in comparison to the conventional CMOS-based COTA. The power consumption in the pure CNT-COTA is 324 times less in comparison to the conventional CMOS-COTA. Further, the phase margin (PM), gain margin (GM), common mode and power supply rejection ratios have been significantly increased in the proposed CNT-based COTAs in comparison to the conventional CMOS-based COTAs. Furthermore, to see the advantage of cascoding, the proposed CNT-based cascode OTAs have been compared with the CNT-based OTAs. It has been observed that by incorporating the concept of cascode in the CNTFET-based OTAs, significant increases in gain (12.5%) and output resistance (13.07%) have been achieved. The performance of the proposed COTAs has been further observed by changing the number of CNTs (N), CNT pitch (S) and CNT diameter (DCNT) in the CNTFETs used. It has been observed that the performance of the proposed COTAs can be significantly improved by using optimum values of N, S and DCNT.

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

NASA Technical Reports Server (NTRS)

Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Solid-state image sensor with focal-plane digital photon-counting pixel array

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Pain, Bedabrata (Inventor)

1995-01-01

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

A digitally assisted, signal folding neural recording amplifier.

PubMed

Chen, Yi; Basu, Arindam; Liu, Lei; Zou, Xiaodan; Rajkumar, Ramamoorthy; Dawe, Gavin Stewart; Je, Minkyu

2014-08-01

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

Preamplifiers for non-contact capacitive biopotential measurements*

PubMed Central

Peng, GuoChen; Ignjatovic, Zeljko; Bocko, Mark F.

2014-01-01

Non-contact biopotential sensing is an attractive measurement strategy for a number of health monitoring applications, primarily the ECG and the EEG. In all such applications a key technical challenge is the design of a low-noise trans-impedance preamplifier for the typically low-capacitance, high source impedance sensing electrodes. In this paper, we compare voltage and charge amplifier designs in terms of their common mode rejection ratio, noise performance, and frequency response. Both amplifier types employ the same operational-transconductance amplifier (OTA), which was fabricated in a 0.35um CMOS process. The results show that a charge amplifier configuration has advantages for small electrode-to-subject coupling capacitance values (less than 10 pF - typical of noncontact electrodes) and that the voltage amplifier configuration has advantages for electrode capacitances above 10 pF. PMID:24109979

Integrated Circuit Design of 3 Electrode Sensing System Using Two-Stage Operational Amplifier

NASA Astrophysics Data System (ADS)

Rani, S.; Abdullah, W. F. H.; Zain, Z. M.; N, Aqmar N. Z.

2018-03-01

This paper presents the design of a two-stage operational amplifier(op amp) for 3-electrode sensing system readout circuits. The designs have been simulated using 0.13μm CMOS technology from Silterra (Malaysia) with Mentor graphics tools. The purpose of this projects is mainly to design a miniature interfacing circuit to detect the redox reaction in the form of current using standard analog modules. The potentiostat consists of several op amps combined together in order to analyse the signal coming from the 3-electrode sensing system. This op amp design will be used in potentiostat circuit device and to analyse the functionality for each module of the system.

OFCC based voltage and transadmittance mode instrumentation amplifier

NASA Astrophysics Data System (ADS)

Nand, Deva; Pandey, Neeta; Pandey, Rajeshwari; Tripathi, Prateek; Gola, Prashant

2017-07-01

The operational floating current conveyor (OFCC) is a versatile active block due to the availability of both low and high input and output impedance terminals. This paper addresses the realization of OFCC based voltage and transadmittance mode instrumentation amplifiers (VMIA and TAM IA). It employs three OFCCs and seven resistors. The transadmittance mode operation can easily be obtained by simply connecting an OFCC based voltage to current converter at the output. The effect of non-idealities of OFCC, in particular finite transimpedance and tracking error, on system performance is also dealt with and corresponding mathematical expressions are derived. The functional verification is performed through SPICE simulation using CMOS based implementation of OFCC.

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

The front-end electronics of the LSPE-SWIPE experiment

NASA Astrophysics Data System (ADS)

Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

2016-07-01

The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

A digital output piezoelectric accelerometer using a Pb(Zr, Ti)O3 thin film array electrically connected in series

NASA Astrophysics Data System (ADS)

Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

2010-10-01

A digital output piezoelectric accelerometer is proposed to realize an ultra-low power consumption wireless sensor node. The accelerometer has patterned piezoelectric thin films (piezoelectric plates) electrically connected in series accompanied by CMOS switches at the end of some of the piezoelectric plates. The connected piezoelectric plates amplify the output voltage without the use of amplifiers. The CMOS switches turn on when the output voltage of the piezoelectric plates is higher than the CMOS threshold voltage. The piezoelectric accelerometer converts the acceleration into a number of on-state CMOS switches, which can be called the digital output. The proposed digital output piezoelectric accelerometer, using Pb(Zr, Ti)O3 (PZT) thin films as the piezoelectric material, was fabricated through a microelectromechanical system (MEMS) microfabrication process. The output voltage was found to be amplified by the number of connected piezoelectric plates. The DC output voltage obtained by using an AC to DC conversion circuit is proportional to the number of connections. The results show the potential for realizing the proposed digital output piezoelectric accelerometer.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

NASA Astrophysics Data System (ADS)

Edward, Alexander; Chan, Pak Kwong

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

Self-amplified CMOS image sensor using a current-mode readout circuit

NASA Astrophysics Data System (ADS)

Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

2014-05-01

The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

Design of analog pixels front-end active feedback

NASA Astrophysics Data System (ADS)

Kmon, P.; Kadlubowski, L. A.; Kaczmarczyk, P.

2018-01-01

The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

A high speed and high gain CMOS receiver chip for a pulsed time-of-flight laser rangefinder

NASA Astrophysics Data System (ADS)

Yu, Jin-jin; Deng, Ruo-han; Yuan, Hong-hui; Chen, Yong-ping

2011-06-01

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed. Pulsed TOF laser range finding devices using a laser diode transmitter can achieve millimeter-level distance measurement accuracy in a measurement range of several tens of meters to non-cooperative targets. The amplifier exploits the regulated cascade (RGC) configuration as the input-stage, thus achieving as large effective input trans-conductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. To enlarge the bandwidth, inductive peaking technology has been adopted. An active inductor (MOS-L) is used instead of spiral inductor in CMOS process. An R-2R resistor ladder is inserting between per-amplifier and post-amplifier as the variable attenuator for digital gain control purpose. The gain-bandwidth of a basic differential pair with resistive load is not large enough for broad band operation. A circuit solution to improve both gain and bandwidth of an amplifying stage is proposed. Traditional and modified Cherry-Hooper amplifiers are discussed and the cascading of several stages to constitute the post-amplifier is designed. The fully integrated one-chip solution is designed with Cadence IC design platform. The simulation result shows the bandwidth of the trans-impedance amplifier is 215MHz with the presence of a 2pF input capacitor and 5pF load capacitor. And the maximum trans-impedance gain is 136dB. The walk error is less than 1ns in 1:1000 dynamic range. The responsive time is less than 2.2ns.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

Pushing the limits of CMOS optical parametric amplifiers with USRN:Si7N3 above the two-photon absorption edge

PubMed Central

Ooi, K. J. A.; Ng, D. K. T.; Wang, T.; Chee, A. K. L.; Ng, S. K.; Wang, Q.; Ang, L. K.; Agarwal, A. M.; Kimerling, L. C.; Tan, D. T. H.

2017-01-01

CMOS platforms operating at the telecommunications wavelength either reside within the highly dissipative two-photon regime in silicon-based optical devices, or possess small nonlinearities. Bandgap engineering of non-stoichiometric silicon nitride using state-of-the-art fabrication techniques has led to our development of USRN (ultra-silicon-rich nitride) in the form of Si7N3, that possesses a high Kerr nonlinearity (2.8 × 10−13 cm2 W−1), an order of magnitude larger than that in stoichiometric silicon nitride. Here we experimentally demonstrate high-gain optical parametric amplification using USRN, which is compositionally tailored such that the 1,550 nm wavelength resides above the two-photon absorption edge, while still possessing large nonlinearities. Optical parametric gain of 42.5 dB, as well as cascaded four-wave mixing with gain down to the third idler is observed and attributed to the high photon efficiency achieved through operating above the two-photon absorption edge, representing one of the largest optical parametric gains to date on a CMOS platform. PMID:28051064

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

1997-01-01

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

A low-power CMOS trans-impedance amplifier for FM/cw ladar imaging system

NASA Astrophysics Data System (ADS)

Hu, Kai; Zhao, Yi-qiang; Sheng, Yun; Zhao, Hong-liang; Yu, Hai-xia

2013-09-01

A scannerless ladar imaging system based on a unique frequency modulation/continuous wave (FM/cw) technique is able to entirely capture the target environment, using a focal plane array to construct a 3D picture of the target. This paper presents a low power trans-impedance amplifier (TIA) designed and implemented by 0.18 μm CMOS technology, which is used in the FM/cw imaging ladar with a 64×64 metal-semiconductor-metal(MSM) self-mixing detector array. The input stage of the operational amplifier (op amp) in TIA is realized with folded cascade structure to achieve large open loop gain and low offset. The simulation and test results of TIA with MSM detectors indicate that the single-end trans-impedance gain is beyond 100 kΩ, and the -3 dB bandwidth of Op Amp is beyond 60 MHz. The input common mode voltage ranges from 0.2 V to 1.5 V, and the power dissipation is reduced to 1.8 mW with a supply voltage of 3.3 V. The performance test results show that the TIA is a candidate for preamplifier of the read-out integrated circuit (ROIC) in the FM/cw scannerless ladar imaging system.

An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

NASA Astrophysics Data System (ADS)

Chen, Hsin-Han; Hsieh, Chih-Cheng

2013-09-01

This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

1997-11-04

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

PubMed

Zhou, Zhijun; Warr, Paul A

2016-12-01

Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

Design and assessment of a robust voltage amplifier with 2.5 GHz GBW and >100 kGy total dose tolerance

NASA Astrophysics Data System (ADS)

Verbeeck, J.; Leroux, P.; Steyaert, M.

2011-01-01

A differential voltage amplifier with a gain-bandwidth product of 2.5Ghz and using adaptive biasing has been designed in a standard CMOS technology and assessed under radiation and temperature variations. The principle used in this ASIC will be employed in the design of a Gbps TIA with improved tolerance for γ-irradiation and temperature for an optical instrumentation (LIDAR) receiver aiming at operation in harsh environments. The voltage amplifier was tested under gamma radiation and features a gain degradation of merely 4.5% up to a total dose of 100kGy. In order to verify the radiation effects on the IC, the threshold voltage shift of the separate transistors has been investigated. Temperature characterization has shown that the amplifier features a reduction of the voltage gain by only 5.6% for a temperature range of -40 till 130 °C.

An Integrated Low-Power Lock-In Amplifier and Its Application to Gas Detection

PubMed Central

Maya-Hernández, Paulina M.; Álvarez-Simón, Luis C.; Sanz-Pascual, María Teresa; Calvo-López, Belén

2014-01-01

This paper presents a new micropower analog lock-in amplifier (LIA) suitable for battery-operated applications thanks to its reduced size and power consumption as well as its operation with single-supply voltage. The proposed LIA was designed in a 0.18 μm CMOS process with a single supply voltage of 1.8 V. Experimental results show a variable DC gain ranging from 24.7 to 42 dB, power consumption of 417 μW and integration area of 0.013 mm2. The LIA performance was demonstrated by measuring carbon monoxide concentrations as low as 1 ppm in dry N2. The experimental results show that the response to CO of the sensing system can be considerably improved by means of the proposed LIA. PMID:25166501

A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

PubMed

Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

2016-04-13

A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

A Current-Mode Common-Mode Feedback Circuit (CMFB) with Rail-to-Rail Operation

NASA Astrophysics Data System (ADS)

Suadet, Apirak; Kasemsuwan, Varakorn

2011-03-01

This paper presents a current-mode common-mode feedback (CMFB) circuit with rail-to-rail operation. The CMFB is a stand-alone circuit, which can be connected to any low voltage transconductor without changing or upsetting the existing circuit. The proposed CMFB employs current mirrors, operating as common-mode detector and current amplifier to enhance the loop gain of the CMFB. The circuit employs positive feedback to enhance the output impedance and gain. The circuit has been designed using a 0.18 μm CMOS technology under 1V supply and analyzed using HSPICE with BSIM3V3 device models. A pseudo-differential amplifier using two common sources and the proposed CMFB shows rail to rail output swing (± 0.7 V) with low common-mode gain (-36 dB) and power dissipation of 390 μW.

A multi-channel instrumentation system for biosignal recording.

PubMed

Yu, Hong; Li, Pengfei; Xiao, Zhiming; Peng, Chung-Ching; Bashirullah, Rizwan

2008-01-01

This paper reports a highly integrated battery operated multi-channel instrumentation system intended for physiological signal recording. The mixed signal IC has been fabricated in standard 0.5microm 5V 3M-2P CMOS process and features 32 instrumentation amplifiers, four 8b SAR ADCs, a wireless power interface with Li-ion battery charger, low power bidirectional telemetry and FSM controller with power gating control for improved energy efficiency. The chip measures 3.2mm by 4.8mm and dissipates approximately 2.1mW when fully operational.

A 205GHz Amplifier in 90nm CMOS Technology

DTIC Science & Technology

2017-03-01

San Jose State University San Jose, CA, USA       Abstract: This paper presents a 205GHz amplifier drawing 43.4mA from a 0.9V power supply with...10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...reported in [2]. In this paper, two neutralization techniques, internal and external approaches, have been implemented to achieve higher power

Large CMOS imager using hadamard transform based multiplexing

NASA Technical Reports Server (NTRS)

Karasik, Boris S.; Wadsworth, Mark V.

2005-01-01

We have developed a concept design for a large (10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be 100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

NASA Astrophysics Data System (ADS)

Sordo-Ibáñez, Samuel; Piñero-García, Blanca; Muñoz-Díaz, Manuel; Ragel-Morales, Antonio; Ceballos-Cáceres, Joaquín; Carranza-González, Luis; Espejo-Meana, Servando; Arias-Drake, Alberto; Ramos-Martos, Juan; Mora-Gutiérrez, José Miguel; Lagos-Florido, Miguel Angel

2016-08-01

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

Prospects for charge sensitive amplifiers in scaled CMOS

NASA Astrophysics Data System (ADS)

O'Connor, Paul; De Geronimo, Gianluigi

2002-03-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

NASA Astrophysics Data System (ADS)

Huang, Zhangcai; Jiang, Minglu; Inoue, Yasuaki

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for ±2.5V power supply voltages, respectively.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

PubMed

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

Low Voltage Current-Reused Pseudo-Differential Programmable Gain Amplifier

NASA Astrophysics Data System (ADS)

Nguyen, Huy-Hieu; Lee, Jeong-Seon; Lee, Sang-Gug

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3dB with gain error of less than ±0.38dB. The IIP3, P1dB, and smallest 3-dB bandwidth are 10.5 to 27dBm, -9 to 9.5dBm, and 250MHz, respectively. The PGA occupies the chip area of 0.04mm2 and consumes only 460 µA from a 1.2V supply.

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

NASA Astrophysics Data System (ADS)

Ma, Rui; Zheng, Hao; Zhu, Zhangming

2017-08-01

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 k {{Ω }}, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/\\sqrt{{Hz}} (rms), resulting in a very low detectable input current of 1 μA with SNR = 5.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

NASA Astrophysics Data System (ADS)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

PubMed

An Hu; Chodavarapu, Vamsy P

2010-10-01

We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

CMOS VLSI Active-Pixel Sensor for Tracking

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

BICMOS power detector for pulsed Rf power amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bridge, Clayton D.

2016-10-01

A BiCMOS power detector for pulsed radio-frequency power amplifiers is proposed. Given the pulse waveform and a fraction of the power amplifier's input or output signal, the detector utilizes a low-frequency feedback loop to perform a successive approximation of the amplitude of the input signal. Upon completion of the successive approximation, the detector returns 9-bits representing the amplitude of the RF input signal. Using the pulse waveform from the power amplifier, the detector can dynamically adjust the rate of the binary search operation in order to return the updated amplitude information of the RF input signal at least every 1ms.more » The detector can handle pulse waveform frequencies from 50kHz to 10MHz with duty cycles in the range of 5- 50% and peak power levels of -10 to 10dBm. The signal amplitude measurement can be converted to a peak power measurement accurate to within ±0.6dB of the input RF power.« less

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

NASA Technical Reports Server (NTRS)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

NASA Astrophysics Data System (ADS)

Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.

PubMed

Wong, A K Y; Kong-Pang Pun; Yuan-Ting Zhang; Ka Nang Leung

2008-12-01

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Hongpeng; Wang, Xuebing; Chen, Jun; Li, Yueyue; Jin, Haiyan; Yang, Yongjun

2018-02-01

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 μm CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2-3 GHz. The in-band noise figure of 3.4-4.7 dB is obtained while the IIP3 of 5.3-6.8 dBm and IIP2 of 12.5-17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

A CMOS-MEMS clamped–clamped beam displacement amplifier for resonant switch applications

NASA Astrophysics Data System (ADS)

Liu, Jia-Ren; Lu, Shih-Chuan; Tsai, Chun-Pu; Li, Wei-Chang

2018-06-01

This paper presents a micromechanical clamped–clamped beam (CC-beam) displacement amplifier based on a CMOS-MEMS fabrication process platform. In particular, a 2.0 MHz resonant displacement amplifier composed of two identical CC-beams coupled by a mechanical beam at locations where the two beams have mismatched velocities exhibits a larger displacement, up to 9.96×, on one beam than that of the other. The displacement amplification prevents unwanted input impacting—the structure switches only to the output but not the input—required by resonant switch-based mechanical circuits (Kim et al 2009 22nd IEEE Int. Conf. on Micro Electro Mechanical Systems; Lin et al 2009 15th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’09) Li et al 2013 17th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’13)). Compared to a single CC-beam displacement amplifier, theory predicts that the displacement amplifying CC-beam array yields a larger overall output displacement for displacement gain beyond 1.13 thanks to the preserved input driving force. A complete analytical model predicts the resultant stiffness and displacement gain of the coupled CC-beam displacement amplifier that match well with finite element analysis (FEA) prediction and measured results.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

PubMed

Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

2017-09-09

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

PubMed Central

Han, Seong-Tae; Baek, Donghyun

2017-01-01

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB. PMID:28891927

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

NASA Astrophysics Data System (ADS)

Moradi, Behzad; Mirzaei, Abdolreza

2016-11-01

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

PubMed Central

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be recovered using several methods; for example, using tunable transmission line lengths in the amplifier or using a variable supply voltage. This concept of estimating process variation has been demonstrated in Agilent Design System (ADS).

High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches

NASA Astrophysics Data System (ADS)

Lee, Jaejun; Lee, Sungho; Song, Yonghoon; Nam, Sangwook

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13µm standard CMOS technology and the experimental results agree well with the theory.

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

NASA Astrophysics Data System (ADS)

Zheng, Hao; Zhu, Zhangming; Ma, Rui

2017-07-01

This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35 μm digital technology achieves a THD+N of 0.02% when delivering 400 mW to an 8 {{Ω }} load from {V}{DD}=3.6 {{V}}. The PSRR of the prototype class D amplifier is 80 dB at 217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V DD range from 2.5 to 4.2 V in mobile application. The total area of the amplifier is 1.7 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044).

A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

PubMed

Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

2013-04-01

In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

A 1V low power second-order delta-sigma modulator for biomedical signal application.

PubMed

Hsu, Chih-Han; Tang, Kea-Tiong

2013-01-01

This paper presents the design and implementation of a low-power delta-sigma modulator for biomedical application with a standard 90 nm CMOS technology. The delta-sigma architecture is implemented as 2nd order feedforward architecture. A low quiescent current operational transconductance amplifier (OTA) is utilized to reduce power consumption. This delta-sigma modulator operated in 1V power supply, and achieved 64.87 dB signal to noise distortion ratio (SNDR) at 10 KHz bandwidth with an oversampling ratio (OSR) of 64. The power consumption is 17.14 µW, and the figure-of-merit (FOM) is 0.60 pJ/conv.

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

NASA Astrophysics Data System (ADS)

Gómez-Galán, J. A.; Sánchez-Rodríguez, T.; Sánchez-Raya, M.; Martel, I.; López-Martín, A.; Carvajal, R. G.; Ramírez-Angulo, J.

2014-06-01

This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

Transimpedance Amplifier for MEMS SAW Oscillator in 1.4GHz

NASA Astrophysics Data System (ADS)

Kamarudin, N.; Karim, J.; Hussin, H.

2018-03-01

This work is to design a transimpedance amplifier for MEMS SAW resonator to achieve low power consumption at desired frequency. A transimpedance amplifier is designed and characterized for MEMS SAW resonator in 0.18μm CMOS process. The transimpedance amplifier achieves gain is 31 dBΩ at 176°. The power consume by oscillator is 0.6mW at VDD 1.8V while phase noise at -133.97dBc/Hz at 10kHz.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

A Design Methodology for Optoelectronic VLSI

DTIC Science & Technology

2007-01-01

current gets converted to a CMOS voltage level through a transimpedance amplifier circuit called a receiver. The output of the receiver is then...change the current flowing from the diode to a voltage that the logic inputs can use. That circuit is called a receiver. It is a transimpedance amplifier ...incorpo- rate random access memory circuits, SRAM or dynamic RAM (DRAM). These circuits use weak internal analog signals that are amplified by sense

A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

Concentric Parallel Combining Balun for Millimeter-Wave Power Amplifier in Low-Power CMOS with High-Power Density

NASA Astrophysics Data System (ADS)

Han, Jiang-An; Kong, Zhi-Hui; Ma, Kaixue; Yeo, Kiat Seng; Lim, Wei Meng

2016-11-01

This paper presents a novel balun for a millimeter-wave power amplifier (PA) design to achieve high-power density in a 65-nm low-power (LP) CMOS process. By using a concentric winding technique, the proposed parallel combining balun with compact size accomplishes power combining and unbalance-balance conversion concurrently. For calculating its power combination efficiency in the condition of various amplitude and phase wave components, a method basing on S-parameters is derived. Based on the proposed parallel combining balun, a fabricated 60-GHz industrial, scientific, and medical (ISM) band PA with single-ended I/O achieves an 18.9-dB gain and an 8.8-dBm output power at 1-dB compression and 14.3-dBm saturated output power ( P sat) at 62 GHz. This PA occupying only a 0.10-mm2 core area has demonstrated a high-power density of 269.15 mW/mm2 in 65 nm LP CMOS.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers

NASA Astrophysics Data System (ADS)

Ito, Tomohiko; Itakura, Tetsuro

A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40MS/s, the measured SNDR is 59.3dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.

Small Pixel Hybrid CMOS X-ray Detectors

NASA Astrophysics Data System (ADS)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

Simple BiCMOS CCCTA design and resistorless analog function realization.

PubMed

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Specification and Design of the SBRC-190: A Cryogenic Multiplexer for Far Infrared Photoconductor Detectors

NASA Technical Reports Server (NTRS)

Erickson, E. F.; Young, E. T.; Wolf, J.; Asbrock, J. F.; Lum, N.; DeVincenzi, D. (Technical Monitor)

2002-01-01

Arrays of far-infrared photoconductor detectors operate at a few degrees Kelvin and require electronic amplifiers in close proximity. For the electronics, a cryogenic multiplexer is ideal to avoid the large number of wires associated with individual amplifiers for each pixel, and to avoid adverse effects of thermal and radiative heat loads from the circuitry. For low background applications, the 32 channel CRC 696 CMOS device was previously developed for SIRTF, the cryogenic Space Infrared Telescope Facility. For higher background applications, we have developed a similar circuit, featuring several modifications: (a) an AC coupled, capacitive feedback transimpedence unit cell, to minimize input offset effects, thereby enabling low detector biases, (b) selectable feedback capacitors to enable operation over a wide range of backgrounds, and (c) clamp and sample & hold output circuits to improve sampling efficiency, which is a concern at the high readout rates required. We describe the requirements for and design of the new device.

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

NASA Astrophysics Data System (ADS)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce; Hall, David; Niaz, Iftikhar Ahmad; Zhou, Yuchun; Sham, L. J.; Lo, Yu-Hwa

2015-08-01

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanism based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.

Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

NASA Astrophysics Data System (ADS)

Cansizoglu, Hilal; Gao, Yang; Ghandiparsi, Soroush; Kaya, Ahmet; Perez, Cesar Bartolo; Mayet, Ahmed; Ponizovskaya Devine, Ekaterina; Cansizoglu, Mehmet F.; Yamada, Toshishige; Elrefaie, Aly F.; Wang, Shih-Yuan; Islam, M. Saif

2017-08-01

Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

Experimental study of the spatially-modulated light detector

NASA Astrophysics Data System (ADS)

Coppée, Daniël; Pan, Wei; Stiens, Johan; Vounckx, Roger; Kuijk, Maarten

1999-03-01

Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm 2).

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording.

PubMed

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-05-19

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

PubMed Central

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-01-01

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter. PMID:27213382

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

NASA Astrophysics Data System (ADS)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

DTIC Science & Technology

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

A linearization time-domain CMOS smart temperature sensor using a curvature compensation oscillator.

PubMed

Chen, Chun-Chi; Chen, Hao-Wen

2013-08-28

This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a -40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of -1.2 to 0.2 °C is achieved in an operation range of -40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

A new high dynamic range ROIC with smart light intensity control unit

NASA Astrophysics Data System (ADS)

Yazici, Melik; Ceylan, Omer; Shafique, Atia; Abbasi, Shahbaz; Galioglu, Arman; Gurbuz, Yasar

2017-05-01

This journal presents a new high dynamic range ROIC with smart pixel which consists of two pre-amplifiers that are controlled by a circuit inside the pixel. Each pixel automatically decides which pre-amplifier is used according to the incoming illumination level. Instead of using single pre-amplifier, two input pre-amplifiers, which are optimized for different signal levels, are placed inside each pixel. The smart circuit mechanism, which decides the best input circuit according to the incoming light level, is also designed for each pixel. In short, an individual pixel has the ability to select the best input amplifier circuit that performs the best/highest SNR for the incoming signal level. A 32 × 32 ROIC prototype chip is designed to demonstrate the concept in 0.18 μ m CMOS technology. The prototype is optimized for NIR and SWIR bands. Instead of a detector, process variation optimized current sources are placed inside the ROIC. The chip achieves minimum 8.6 e- input referred noise and 98.9 dB dynamic range. It has the highest dynamic range in the literature in terms of analog ROICs for SWIR band. It is operating in room temperature and power consumption is 2.8 μ W per pixel.

High linearity current communicating passive mixer employing a simple resistor bias

NASA Astrophysics Data System (ADS)

Rongjiang, Liu; Guiliang, Guo; Yuepeng, Yan

2013-03-01

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier (TIA) is introduced. It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell. The optimum linearity and the maximum symmetric switching operation are obtained at the same time. The mixer is implemented in a 0.25 μm CMOS process. The test shows that it achieves an input third-order intercept point of 13.32 dBm, conversion gain of 5.52 dB, and a single sideband noise figure of 20 dB.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

A Comparative Analysis of CMUT Receiving Architectures for the Design Optimization of Integrated Transceiver Front Ends.

PubMed

Sautto, Marco; Savoia, Alessandro Stuart; Quaglia, Fabio; Caliano, Giosue; Mazzanti, Andrea

2017-05-01

A formal comparison between fundamental RX amplifier configurations for capacitive micromachined ultrasonic transducers (CMUTs) is proposed in this paper. The impact on both RX and the pulse-echo frequency response and on the output SNR is thoroughly analyzed and discussed. It is shown that the resistive-feedback amplifier yields a bandpass RX frequency response, while both open-loop voltage and capacitive-feedback amplifiers exhibit a low-pass frequency response. For a given power dissipation, it is formally proved that a capacitive-feedback amplifier provides a remarkable SNR improvement against the commonly adopted resistive feedback stage, achieved at the expense of a reduced pulse-echo center frequency, making its use convenient in low-frequency and midfrequency ultrasound imaging applications. The advantage mostly comes from a much lower noise contributed by the active devices, especially with low- Q , broadband transducers. The results of the analysis are applied to the design of a CMUT front end in BIPOLAR-CMOS-DMOS Silicon-on-Insulator technology operating at 10-MHz center frequency. It comprises a low-power RX amplifier, a high-voltage Transmission/Reception switch, and a 100-V TX driver. Extensive electrical characterization, pulse-echo measurements, and imaging results are shown. Compared with previously reported CMUT front ends, this transceiver demonstrates the highest dynamic range and state-of-the-art noise performance with an RX amplifier power dissipation of 1 mW.

High Efficiency mm-Wave Transmitter Array

DTIC Science & Technology

2016-09-01

SECURITY CLASSIFICATION OF: High efficiency, high power transmitters integrated in silicon at 45, 94 and 138 GHz were developed. Our approach...employs CMOS-SOI and SiGe HBT unit amplifiers, power -combined in free-space using antenna arrays to attain high power levels. In the baseline approach...the-art were made. At 45GHz, a single CMOS chip produced an RF power of 630mW, which yielded an EIRP of 1. REPORT DATE (DD-MM-YYYY) 4. TITLE AND

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

CMOS SiPM with integrated amplifier

NASA Astrophysics Data System (ADS)

Schwinger, Alexander; Brockherde, Werner; Hosticka, Bedrich J.; Vogt, Holger

2017-02-01

The integration of silicon photomultiplier (SiPM) and frontend electronics in a suitable optoelectronic CMOS process is a promising approach to increase the versatility of single-photon avalanche diode (SPAD)-based singlephoton detectors. By integrating readout amplifiers, the device output capacitance can be reduced to minimize the waveform tail, which is especially important for large area detectors (>10 × 10mm2). Possible architectures include a single readout amplifier for the whole detector, which reduces the output capacitance to 1:1 pF at minimal reduction in detector active area. On the other hand, including a readout amplifier in every SiPM cell would greatly improve the total output capacitance by minimizing the influence of metal routing parasitic capacitance, but requiring a prohibitive amount of detector area. As tradeoff, the proposed detector features one readout amplifier for each column of the detector matrix to allow for a moderate reduction in output capacitance while allowing the electronics to be placed in the periphery of the active detector area. The presented detector with a total size of 1.7 ♢ 1.0mm2 features 400 cells with a 50 μm pitch, where the signal of each column of 20 SiPM cells is summed in a readout channel. The 20 readout channels are subsequently summed into one output channel, to allow the device to be used as a drop-in replacement for commonly used analog SiPMs.

A High Performance LIA-Based Interface for Battery Powered Sensing Devices

PubMed Central

García-Romeo, Daniel; Valero, María R.; Medrano, Nicolás; Calvo, Belén; Celma, Santiago

2015-01-01

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to −39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment. PMID:26437408

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce

2015-08-03

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanismmore » based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.« less

A High Performance LIA-Based Interface for Battery Powered Sensing Devices.

PubMed

García-Romeo, Daniel; Valero, María R; Medrano, Nicolás; Calvo, Belén; Celma, Santiago

2015-09-30

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to -39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment.

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

PubMed

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

Sensitivity-Enhanced CMOS Phase Luminometry System Using Xerogel-Based Sensors.

PubMed

Lei Yao; Khan, R; Chodavarapu, V P; Tripathi, V S; Bright, F V

2009-10-01

We present the design and implementation of a phase luminometry sensor system with improved and tunable detection sensitivity achieved using a complementary metal-oxide semiconductor (CMOS) integrated circuit. We use sol-gel derived xerogel thin films as an immobilization media to house oxygen (O2) responsive luminescent molecules. The sensor operates on the principal of phase luminometry wherein a sinusoidal modulation signal is used to excite the luminophores encapsulated in the porous xerogel films and the corresponding phase shift of the emission signals is monitored. The phase shift is directly related to excited state lifetimes of the luminophores which in turn are related to the concentration of the target analyte species present in the vicinity of the luminophores. The CMOS IC, which consists of a 16 times 16 high-gain phototransistor array, current-to-voltage converter, amplifier and tunable phase shift detector, consumes an average power of 14 mW with 5-V power supply operating at a 38-kHz modulation frequency. The output of the IC is a dc voltage that corresponds to the detected luminescence phase shift with respect to the excitation signal. As a prototype, we demonstrate an oxygen sensor system by encapsulating the luminophore tris(4,7-diphenyl-1,10-phenanthroline)ruthenium(II) within the xerogel matrices. The sensor system showed a fast response on the order of few seconds and we obtained a detection sensitivity of 118 mV per 1% change in O2 concentration. The system demonstrates a novel concept to tune and improve the detection sensitivity for specific concentrations of the target analyte in many biomedical monitoring applications.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Improvements of low-detection-limit filter-free fluorescence sensor developed by charge accumulation operation

NASA Astrophysics Data System (ADS)

Tanaka, Kiyotsugu; Choi, Yong Joon; Moriwaki, Yu; Hizawa, Takeshi; Iwata, Tatsuya; Dasai, Fumihiro; Kimura, Yasuyuki; Takahashi, Kazuhiro; Sawada, Kazuaki

2017-04-01

We developed a low-detection-limit filter-free fluorescence sensor by a charge accumulation technique. For charge accumulation, a floating diffusion amplifier (FDA), which included a floating diffusion capacitor, a transfer gate, and a source follower circuit, was used. To integrate CMOS circuits with the filter-free fluorescence sensor, we adopted a triple-well process to isolate transistors from the sensor on a single chip. We detected 0.1 nW fluorescence under the illumination of excitation light by 1.5 ms accumulation, which was one order of magnitude greater than that of a previous current detection sensor.

CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

PubMed

Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

2016-06-01

Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2012-12-17

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

NASA Astrophysics Data System (ADS)

Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Moreno-Cadenas, J. A.; Escobosa-Echavarría, A.

2011-03-01

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

Time Difference Amplifier with Robust Gain Using Closed-Loop Control

NASA Astrophysics Data System (ADS)

Nakura, Toru; Mandai, Shingo; Ikeda, Makoto; Asada, Kunihiro

This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

PubMed Central

Kim, Sungho; Lepkowski, William; Wilk, Seth J.; Thornton, Trevor J.; Bakkaloglu, Bertan

2014-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of −70dBm and −98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10−3 at the input powers of −70dBm at 1.2V and −98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers

PubMed Central

Anabtawi, Nijad; Ferzli, Rony; Harmanani, Haidar M.

2017-01-01

This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that can be configured to operate with either 1st, 2nd, 3rd or 4th order loop filters, eliminating the need for a bulky passive output filter. Output ripple, sideband noise and spectral emission requirements of different wireless standards can be met by configuring the modulator’s filter order and converter’s sampling frequency. The proposed converter is entirely digital and is implemented in 14nm bulk CMOS process for post layout verification. For an input voltage of 3.3V, the converter’s output can be regulated to any voltage level from 0.5V to 2.5V, at a nominal switching frequency of 150MHz. It achieves a maximum efficiency of 94% at 1.5 W output power. PMID:28919657

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Bandwidth tunable amplifier for recording biopotential signals.

PubMed

Hwang, Sungkil; Aninakwa, Kofi; Sonkusale, Sameer

2010-01-01

This paper presents a low noise, low power, bandwidth tunable amplifier for bio-potential signal recording applications. By employing depletion-mode pMOS transistor in diode configuration as a tunable sub pA current source to adjust the resistivity of MOS-Bipolar pseudo-resistor, the bandwidth is adjusted without any need for a separate band-pass filter stage. For high CMRR, PSRR and dynamic range, a fully differential structure is used in the design of the amplifier. The amplifier achieves a midband gain of 39.8dB with a tunable high-pass cutoff frequency ranging from 0.1Hz to 300Hz. The amplifier is fabricated in 0.18εm CMOS process and occupies 0.14mm(2) of chip area. A three electrode ECG measurement is performed using the proposed amplifier to show its feasibility for low power, compact wearable ECG monitoring application.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2017-04-01

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

A low-power CMOS readout IC design for bolometer applications

NASA Astrophysics Data System (ADS)

Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

2017-02-01

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

Dual-Polarized Antenna Arrays with CMOS Power Amplifiers for SiP Integration at W-Band

NASA Astrophysics Data System (ADS)

Giese, Malte; Vehring, Sönke; Böck, Georg; Jacob, Arne F.

2017-09-01

This paper presents requirements and front-end solutions for low-cost communication systems with data rates of 100 Gbit/s. Link budget analyses in different mass-market applications are conducted for that purpose. It proposes an implementation of the front-end as an active antenna array with support for beam steering and polarization multiplexing over the full W-band. The critical system components are investigated and presented. This applies to a transformer coupled power amplifier (PA) in 40 nm bulk CMOS. It shows saturated output power of more than 10 dBm and power-added-efficiency of more than 10 % over the full W-band. Furthermore, the performance of microstrip-to-waveguide transitions is shown exemplarily as an important part of the active antenna as it interfaces active circuitry and antenna in a polymer-and-metal process. The transition test design shows less than 0.9 dB insertion loss and more than 12 dB return loss for the differential transition over the full W-band.

A 5 Gb/s CMOS adaptive equalizer for serial link

NASA Astrophysics Data System (ADS)

Wu, Hongbing; Wang, Jingyu; Liu, Hongxia

2018-04-01

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter. Project supported by the National Natural Science Foundation of China (No. 61376099), the Foundation for Fundamental Research of China (No. JSZL2016110B003), and the Major Fundamental Research Program of Shaanxi (No. 2017ZDJC-26).

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

PubMed

Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2012-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems

PubMed Central

Dey, Samrat; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2013-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs). PMID:24301987

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

NASA Astrophysics Data System (ADS)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

1.2V, 24mW/ch, 10bit, 80MSample/s Pipelined A/D Converters

NASA Astrophysics Data System (ADS)

Ueno, Takeshi; Ito, Tomohiko; Kurose, Daisuke; Yamaji, Takafumi; Itakura, Tetsuro

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24mW/ch from a 1.2V power supply. The measured SNR and SNDR are 58.6dB and 52.2dB, respectively.

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

NASA Astrophysics Data System (ADS)

Paik, Daehwa; Miyahara, Masaya; Matsuzawa, Akira

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

NASA Astrophysics Data System (ADS)

Yoshida, Takeshi; Sueishi, Katsuya; Iwata, Atsushi; Matsushita, Kojiro; Hirata, Masayuki; Suzuki, Takafumi

2011-04-01

This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal-oxide-silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process and occupies 0.09 mm2 on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1-100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.

Common source cascode amplifiers for integrating IR-FPA applications

NASA Technical Reports Server (NTRS)

Woolaway, James T.; Young, Erick T.

1989-01-01

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

Note: Characterization and test of a high input impedance RF amplifier for series nanowire detector

NASA Astrophysics Data System (ADS)

Wan, Chao; Pei, Yufeng; Jiang, Zhou; Kang, Lin; Wu, Peiheng

2016-09-01

We designed a high input impedance RF amplifier based on Tower Jazz's 0.18 μm SiGe BiCMOS process for series nanowire detector. The characterization of its gain and input impedance with a vector network analyzer is described in detail for its specificity. The actual 15 dB gain should be the measured value subtracts 6 dB, which is easy to be ignored. Its input impedance can be equivalent to 6.7 kΩ ∥ 3.4 pF though fitting the measurement, whose accuracy is verified. The process of measurement provides a good reference to characterize the similar special amplifier with unmatched impedance.

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Kuan, Bao; Xiangning, Fan; Wei, Li; Zhigong, Wang

2013-01-01

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a -1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Nanosecond monolithic CMOS readout cell

DOEpatents

Souchkov, Vitali V.

2004-08-24

A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

A 4MP high-dynamic-range, low-noise CMOS image sensor

NASA Astrophysics Data System (ADS)

Ma, Cheng; Liu, Yang; Li, Jing; Zhou, Quan; Chang, Yuchun; Wang, Xinyang

2015-03-01

In this paper we present a 4 Megapixel high dynamic range, low dark noise and dark current CMOS image sensor, which is ideal for high-end scientific and surveillance applications. The pixel design is based on a 4-T PPD structure. During the readout of the pixel array, signals are first amplified, and then feed to a low- power column-parallel ADC array which is already presented in [1]. Measurement results show that the sensor achieves a dynamic range of 96dB, a dark noise of 1.47e- at 24fps speed. The dark current is 0.15e-/pixel/s at -20oC.

Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

NASA Technical Reports Server (NTRS)

Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

2006-01-01

The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

2003-04-01

This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

NASA Astrophysics Data System (ADS)

Ito, Tomohiko; Kurose, Daisuke; Ueno, Takeshi; Yamaji, Takafumi; Itakura, Tetsuro

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90dB with low power. The measured SNR of the 100-MSPS ADC is 66.7dB at 1.2-V supply. Under that condition, each ADC dissipates only 55mW.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Improved Space Object Orbit Determination Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

CMOS integrated avalanche photodiodes and frequency-mixing optical sensor front end for portable NIR spectroscopy instruments.

PubMed

Yun, Ruida; Sthalekar, Chirag; Joyner, Valencia M

2011-01-01

This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \\im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.

Cargo Movement Operations System (CMOS). Software Requirements Specification (Applications CSCI) Increment 1, Update

DTIC Science & Technology

1990-05-31

12. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SRS1-0004 PROGRAM OFFICE...operational state of the SBSS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Comotti, Daniele; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio

2015-10-01

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor.

PubMed

Song, Shuang; Rooijakkers, Michael; Harpe, Pieter; Rabotti, Chiara; Mischi, Massimo; van Roermund, Arthur H M; Cantatore, Eugenio

2015-04-01

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

On the Application of Inverse-Mode SiGe HBTs in RF Receivers for the Mitigation of Single-Event Transients

NASA Astrophysics Data System (ADS)

Song, Ickhyun; Cho, Moon-Kyu; Oakley, Michael A.; Ildefonso, Adrian; Ju, Inchan; Buchner, Stephen P.; McMorrow, Dale; Paki, Pauline; Cressler, John. D.

2017-05-01

Best practice in mitigation strategies for single-event transients (SETs) in radio-frequency (RF) receiver modules is investigated using a variety of integrated receivers utilizing inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The receivers were designed and implemented in a 130-nm SiGe BiCMOS technology platform. In general, RF switches, low-noise amplifiers (LNAs), and downconversion mixers utilizing inverse-mode SiGe HBTs exhibit less susceptibility to SETs than conventional RF designs, in terms of transient peaks and duration, at the cost of RF performance. Under normal RF operation, the SET-hardened switch is mainly effective in peak reduction, while the LNA and the mixer exhibit reductions in transient peaks as well as transient duration.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Cargo Movement Operations System (CMOS). Software Test Description

DTIC Science & Technology

1990-10-28

resulting in errors in paragraph numbers and titles. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...location to test the update of the truck manifest. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Recent progress and development of a speedster-EXD: a new event-triggered hybrid CMOS x-ray detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2015-08-01

We present the characterization of a new event-driven X-ray hybrid CMOS detector developed by Penn State University in collaboration with Teledyne Imaging Sensors. Along with its low susceptibility to radiation damage, low power consumption, and fast readout time to avoid pile-up, the Speedster-EXD has been designed with the capability to limit its readout to only those pixels containing charge, thus enabling even faster effective frame rates. The threshold for the comparator in each pixel can be set by the user so that only pixels with signal above the set threshold are read out. The Speedster-EXD hybrid CMOS detector also has two new in-pixel features that reduce noise from known noise sources: (1) a low-noise, high-gain CTIA amplifier to eliminate crosstalk from interpixel capacitance (IPC) and (2) in-pixel CDS subtraction to reduce kTC noise. We present the read noise, dark current, IPC, energy resolution, and gain variation measurements of one Speedster-EXD detector.

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-03-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-06-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

Cargo Movement Operations System (CMOS) System Segment Design Document (Draft) Increment II

DTIC Science & Technology

1990-05-02

and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications

DOE PAGES

Zhang, T.; Tavernier, F.; Moreira, P.; ...

2015-02-19

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system at the transmitter side. We have developed a 10 Gb/s GBLD (GBLD10) in a 130 nm CMOS technology, as part of the design efforts towards the upgrade of the electrical components of the LHC experiments. The GBLD10 is based on the distributed-amplifier (DA) architecture and achieves data rates up to 10 Gb/s. It is capable of driving VCSELs with modulation currents up to 12 mA. Furthermore, a pre-emphasis function has been included in the proposed laser driver in order to compensate for the capacitivemore » load and channel losses.« less

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

PubMed

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix, Version 3 Increment II

DTIC Science & Technology

1990-12-17

above SCs should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...These two documents should be in agreement with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...completeness, they should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

NASA Astrophysics Data System (ADS)

Pal, Dipankar; Goswami, Manish

2010-05-01

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ∼83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.

A new physical unclonable function architecture

NASA Astrophysics Data System (ADS)

Chuang, Bai; Xuecheng, Zou; Kui, Dai

2015-03-01

This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 °C, and supply voltage variation from 1.7 to 1.9 V. Project supported by the National Natural Science Foundation of China (No. 61376031).

Embedded neural recording with TinyOS-based wireless-enabled processor modules.

PubMed

Farshchi, Shahin; Pesterev, Aleksey; Nuyujukian, Paul; Guenterberg, Eric; Mody, Istvan; Judy, Jack W

2010-04-01

To create a wireless neural recording system that can benefit from the continuous advancements being made in embedded microcontroller and communications technologies, an embedded-system-based architecture for wireless neural recording has been designed, fabricated, and tested. The system consists of commercial-off-the-shelf wireless-enabled processor modules (motes) for communicating the neural signals, and a back-end database server and client application for archiving and browsing the neural signals. A neural-signal-acquisition application has been developed to enable the mote to either acquire neural signals at a rate of 4000 12-bit samples per second, or detect and transmit spike heights and widths sampled at a rate of 16670 12-bit samples per second on a single channel. The motes acquire neural signals via a custom low-noise neural-signal amplifier with adjustable gain and high-pass corner frequency that has been designed, and fabricated in a 1.5-microm CMOS process. In addition to browsing acquired neural data, the client application enables the user to remotely toggle modes of operation (real-time or spike-only), as well as amplifier gain and high-pass corner frequency.

Cargo Movement Operations System (CMOS). Final Software Requirements Specification, (Applications CSCI), Increment II

DTIC Science & Technology

1991-01-29

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL Nt3MBFR: SRS1-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...floppy diskette interface with CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES ( 3 NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

NASA Astrophysics Data System (ADS)

1981-12-01

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

NASA Technical Reports Server (NTRS)

1981-01-01

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Cargo Movement Operations System (CMOS) Final Software User’s Manual

DTIC Science & Technology

1990-12-20

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ I COMMENT STATUS: OPEN...is correct. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS CO1MENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...RATIONALE: .."DA001041" is in the SUM but not in the SDD. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Fukuda, Koichi; Liu, Yongxun; Mori, Takahiro; Mizubayashi, Wataru; O'uchi, Shin-ichi; Fuketa, Hiroshi; Otsuka, Shintaro; Migita, Shinji; Masahara, Meishoku; Endo, Kazuhiko; Ota, Hiroyuki; Matsukawa, Takashi

2017-04-01

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Nanosecond-laser induced crosstalk of CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

PubMed

Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

2015-11-06

This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

A Printed Organic Amplification System for Wearable Potentiometric Electrochemical Sensors.

PubMed

Shiwaku, Rei; Matsui, Hiroyuki; Nagamine, Kuniaki; Uematsu, Mayu; Mano, Taisei; Maruyama, Yuki; Nomura, Ayako; Tsuchiya, Kazuhiko; Hayasaka, Kazuma; Takeda, Yasunori; Fukuda, Takashi; Kumaki, Daisuke; Tokito, Shizuo

2018-03-02

Electrochemical sensor systems with integrated amplifier circuits play an important role in measuring physiological signals via in situ human perspiration analysis. Signal processing circuitry based on organic thin-film transistors (OTFTs) have significant potential in realizing wearable sensor devices due to their superior mechanical flexibility and biocompatibility. Here, we demonstrate a novel potentiometric electrochemical sensing system comprised of a potassium ion (K + ) sensor and amplifier circuits employing OTFT-based pseudo-CMOS inverters, which have a highly controllable switching voltage and closed-loop gain. The ion concentration sensitivity of the fabricated K + sensor was 34 mV/dec, which was amplified to 160 mV/dec (by a factor of 4.6) with high linearity. The developed system is expected to help further the realization of ultra-thin and flexible wearable sensor devices for healthcare applications.

Single-Chip T/R Module for 1.2 GHz

NASA Technical Reports Server (NTRS)

Moussessian, Alina; Mojarradi, Mohammad; Johnson, Travis; Davis, John; Grigorian, Edwin; Hoffman, James; Caro, Edward; Kuhn, William

2006-01-01

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Fabricating a hybrid imaging device

NASA Technical Reports Server (NTRS)

Wadsworth, Mark (Inventor); Atlas, Gene (Inventor)

2003-01-01

A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

Radiation Response of Emerging FeRAM Technology

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Scheick, L. Z.

2001-01-01

The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.

High-density CMOS Microelectrode Array System for Impedance Spectroscopy and Imaging of Biological Cells.

PubMed

Vijay, Viswam; Raziyeh, Bounik; Amir, Shadmani; Jelena, Dragas; Alicia, Boos Julia; Axel, Birchler; Jan, Müller; Yihui, Chen; Andreas, Hierlemann

2017-01-26

A monolithic measurement platform was implemented to enable label-free in-vitro electrical impedance spectroscopy measurements of cells on multi-functional CMOS microelectrode array. The array includes 59,760 platinum microelectrodes, densely packed within a 4.5 mm × 2.5 mm sensing region at a pitch of 13.5 μm. The 32 on-chip lock-in amplifiers can be used to measure the impedance of any arbitrarily chosen electrodes on the array by applying a sinusoidal voltage, generated by an on-chip waveform generator with a frequency range from 1 Hz to 1 MHz, and measuring the respective current. Proof-of-concept measurements of impedance sensing and imaging are shown in this paper. Correlations between cell detection through optical microscopy and electrochemical impedance scanning were established.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Cargo Movement Operations System (CMOS). Software Requirements Specification

DTIC Science & Technology

1990-03-12

was erroneously deleted. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...previous SRS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] 0 ORIGINATOR CONTROL NUMBER

Cargo Movement Operations System (CMOS). System Segment Specification, Updated, Increment II

DTIC Science & Technology

1990-05-02

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ 3 COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL...the LAN. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology

PubMed Central

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator’s high motion losses due to the possibility of their ‘system-on-chip’ integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design’s applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications. PMID:27391136

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Low-power low-voltage superior-order curvature corrected voltage reference

NASA Astrophysics Data System (ADS)

Popa, Cosmin

2010-06-01

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

A 1microW 85nV/ radicalHz pseudo open-loop preamplifier with programmable band-pass filter for neural interface system.

PubMed

Chang, Sun-Il; Yoon, Euisik

2009-01-01

We report an energy efficient pseudo open-loop amplifier with programmable band-pass filter developed for neural interface systems. The proposed amplifier consumes 400nA at 2.5V power supply. The measured thermal noise level is 85nV/ radicalHz and input-referred noise is 1.69microV(rms) from 0.3Hz to 1 kHz. The amplifier has a noise efficiency factor of 2.43, the lowest in the differential topologies reported up to date to our knowledge. By programming the switched-capacitor frequency and bias current, we could control the bandwidth of the preamplifier from 138 mHz to 2.2 kHz to meet various application requirements. The entire preamplifier including band-pass filters has been realized in a small area of 0.043mm(2) using a 0.25microm CMOS technology.

Cargo Movement Operations System (CMOS). Software User’s Manual

DTIC Science & Technology

1990-06-27

RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SUM-0003 PROGRAM...3.1.11. RATIONALE: Clarity. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS). Software Design Document

DTIC Science & Technology

1990-04-29

order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT...inadvertently omitted from the table. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDDI-0005 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

Fabricating a hybrid imaging device having non-destructive sense nodes

NASA Technical Reports Server (NTRS)

Wadsworth, Mark (Inventor); Atlas, Gene (Inventor)

2001-01-01

A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Third-Order Elliptic Lowpass Filter for Multi-Standard Baseband Chain Using Highly Linear Digitally Programmable OTA

NASA Astrophysics Data System (ADS)

Elamien, Mohamed B.; Mahmoud, Soliman A.

2018-03-01

In this paper, a third-order elliptic lowpass filter is designed using highly linear digital programmable balanced OTA. The filter exhibits a cutoff frequency tuning range from 2.2 MHz to 7.1 MHz, thus, it covers W-CDMA, UMTS, and DVB-H standards. The programmability concept in the filter is achieved by using digitally programmable operational transconductors amplifier (DPOTA). The DPOTA employs three linearization techniques which are the source degeneration, double differential pair and the adaptive biasing. Two current division networks (CDNs) are used to control the value of the transconductance. For the DPOTA, the third-order harmonic distortion (HD3) remains below -65 dB up to 0.4 V differential input voltage at 1.2 V supply voltage. The DPOTA and the filter are designed and simulated in 90 nm CMOS technology with LTspice simulator.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

PubMed Central

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-01-01

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors. PMID:28368355

Spin switches for compact implementation of neuron and synapse

NASA Astrophysics Data System (ADS)

Quang Diep, Vinh; Sutton, Brian; Behin-Aein, Behtash; Datta, Supriyo

2014-06-01

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltages that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems.

PubMed

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-04-03

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

PubMed

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

PubMed

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

NASA Astrophysics Data System (ADS)

O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

2016-02-01

CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

PubMed Central

Mollazadeh, Mohsen; Murari, Kartikeya; Cauwenberghs, Gert; Thakor, Nitish

2009-01-01

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental ΔΣ analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 μVrms while drawing 12.2 μA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 μW power. Time-modulation feedback in the ADC offers programmable digital gain (1–4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject. PMID:20046962

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

NASA Astrophysics Data System (ADS)

Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

2017-06-01

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

Cargo Movement Operations System (CMOS) System Segment Design Document. Revision. Increment 2

DTIC Science & Technology

1990-06-14

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ J CLOSED [ ] Cmnt Page Paragraph No. No. Number...provided (SSDDII-0004). CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ 3 ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...but not in paragraph 10.1. CMOS PMO ACCEPTS COMMENT: YES [ ) NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] * COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS): Revised Preliminary Software Design Document (Applications CSCI), Increment II

DTIC Science & Technology

1991-05-23

background color does not change. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: CONMENT STATUS: OPEN...NO ( ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ) CLOSED [ ] ,$ ...collected on this worksheet and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO

Cargo Movement Operations System (CMOS) Draft Software User’s Manual Increment II

DTIC Science & Technology

1991-06-26

the user. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...indicated. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN r I CLOSED [ ] ORIGINATOR CONTROL NUMBER: SUM-0006 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

On the design and assessment of a 2.45 GHz radio telecommand system for remote patient monitoring.

PubMed

Crumley, G C; Evans, N E; Burns, J B; Trouton, T G

1998-12-01

This paper discusses the design and operational assessment of a minimum-power, 2.45 GHz portable pulse receiver and associated base transmitter comprising the interrogation link in a duplex, cross-band RF transponder designed for short-range, remote patient monitoring. A tangential receiver sensitivity of - 53 dBm was achieved using a 50 ohms microstrip stub-matched zero-bias diode detector and a CMOS baseband amplifier consuming 20 microA from + 3 V. The base transmitter generated an on-off keyed peak output of 0.5 W into 50 ohms. Both linear and right-hand circularly-polarised antennas were employed in system evaluations carried out within an operational Coronary Care Unit ward. For transmitting antenna heights of between 0.3 and 2.2 m above floor level. transponder interrogations were 95% reliable within the 82 m2 area of the ward, falling to an average of 46% in the surrounding rooms and corridors. Separating the polarisation modes, using the circular antenna set gave the higher overall reliability.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems.

PubMed

Al-Ashmouny, Khaled M; Chang, Sun-Il; Yoon, Euisik

2012-10-01

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

Programmable differential capacitance-to-voltage converter for MEMS accelerometers

NASA Astrophysics Data System (ADS)

Royo, G.; Sánchez-Azqueta, C.; Gimeno, C.; Aldea, C.; Celma, S.

2017-05-01

Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.

Low power, highly linear output buffer. [for infrared focal plane arrays

NASA Technical Reports Server (NTRS)

Foley, D.; Butler, N.; Stobie, J.

1992-01-01

A class AB CMOS output buffer has been designed for use on an IR focal plane array. Given the requirements for power dissipation and load capacitance a class A output, such as a source follower, would be unsuitable. The approach taken uses a class AB amplifier configured as a charge integrator. Thus it converts a charge packet in the focal plane multiplexer to a voltage which is then the output of the focal plane. With a quiescent current of 18 micro-a and a load capacitance of 100 pf, the amplifier has an open loop unity gain bandwidth of 900 khz. Integral nonlinearity is better than .03 percent over 5.5 volts when run with VDD-VSS = 6v.

Cargo Movement Operations System (CMOS). Final Software Design Document. Increment III. (PC Unix - Air Force Configuration)

DTIC Science & Technology

1991-07-03

required changes to this matrix. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...this appendix should be updated to include all necessary changes. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDD3-0004 PROGRAM OFFICE

Cargo Movement Operations System (CMOS) Interface Requirements Specification (Draft). Increment II

DTIC Science & Technology

1990-05-17

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ 3 CLOSED [ ] ORIGINATOR CONTROL NUMBER: IRS1-0003 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM DISCREPANCY WORKSHEET CDRL NUMBER: A004-05 DATE: 05/17/90 ORIGINATOR NAME: Ronald J. Lacour OFFICE SYMBOL: SAIC TELEPHONE NUMBER: 272-2999 SUBSTANTIVE: X EDITORIAL: PAGE NUMBER: 9 PARA NUMBER: 3.2 c. COMMENT OR RECOMMENDED CHANGE: Change line 2 to read, "CMOS IRD/SBSS-01 and SBSS-03." Move "CMOS IRD/SBSS-02" to paragraph 3.3 c. RATIONALE: The CMOS IRD/SBSS-02 covers the Shipment Suspense

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

A 256×256 low-light-level CMOS imaging sensor with digital CDS

NASA Astrophysics Data System (ADS)

Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

2016-10-01

In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Cargo Movement Operations System (CMOS) Computer System Operator’s Manual. Draft

DTIC Science & Technology

1990-06-27

are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMEN7 STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: CSOM-0003 PROGRAM OFFICE CONTROL...ACCEPTS COMMENT: YES [ ] NO ( 3 ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

PubMed

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis.

Cargo Movement Operations (CMOS) Increment I Installation and Checkout Plan for Langley AFB

DTIC Science & Technology

1990-10-28

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No...document. CMOS PMO ACCEPTS COMMENT: YES [ ) NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, John D.; Patel, Jagdish; Liu, S. T.; Reed, Robert A.; Mojarradi, Mohammad M.; Blalock, Benjamin J.

2003-06-01

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Recent X-ray hybrid CMOS detector developments and measurements

NASA Astrophysics Data System (ADS)

Hull, Samuel V.; Falcone, Abraham D.; Burrows, David N.; Wages, Mitchell; Chattopadhyay, Tanmoy; McQuaide, Maria; Bray, Evan; Kern, Matthew

2017-08-01

The Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors (TIS), have progressed their efforts to improve soft X-ray Hybrid CMOS detector (HCD) technology on multiple fronts. Having newly acquired a Teledyne cryogenic SIDECARTM ASIC for use with HxRG devices, measurements were performed with an H2RG HCD and the cooled SIDECARTM. We report new energy resolution and read noise measurements, which show a significant improvement over room temperature SIDECARTM operation. Further, in order to meet the demands of future high-throughput and high spatial resolution X-ray observatories, detectors with fast readout and small pixel sizes are being developed. We report on characteristics of new X-ray HCDs with 12.5 micron pitch that include in-pixel CDS circuitry and crosstalk-eliminating CTIA amplifiers. In addition, PSU and TIS are developing a new large-scale array Speedster-EXD device. The original 64 × 64 pixel Speedster-EXD prototype used comparators in each pixel to enable event driven readout with order of magnitude higher effective readout rates, which will now be implemented in a 550 × 550 pixel device. Finally, the detector lab is involved in a sounding rocket mission that is slated to fly in 2018 with an off-plane reflection grating array and an H2RG X-ray HCD. We report on the planned detector configuration for this mission, which will increase the NASA technology readiness level of X-ray HCDs to TRL 9.

Transceiver Design for CMUT-Based Super-Resolution Ultrasound Imaging.

PubMed

Behnamfar, Parisa; Molavi, Reza; Mirabbasi, Shahriar

2016-04-01

A recently introduced structure for the capacitive micromachined ultrasonic transducers (CMUTs) has focused on the applications of the asymmetric mode of vibration and has shown promising results in construction of super-resolution ultrasound images. This paper presents the first implementation and experimental results of a transceiver circuit to interface such CMUT structures. The multiple input/multiple output receiver in this work supports both fundamental and asymmetric modes of operation and includes transimpedance amplifiers and low-power variable-gain stages. These circuit blocks are designed considering the trade-offs between gain, input impedance, noise, linearity and power consumption. The high-voltage transmitter can generate pulse voltages up to 60 V while occupying a considerably small area. The overall circuit is designed and laid out in a 0.35 μm CMOS process and a four-channel transceiver occupies 0.86 × 0.38 mm(2). The prototype chip is characterized in both electrical and mechanical domains. Measurement results show that each receiver channel has a nominal gain of 110 dBΩ with a 3 dB bandwidth of 9 MHz while consuming 1.02 mW from a 3.3 V supply. The receiver is also highly linear, with 1 dB compression point of minimum 1.05 V which is considerably higher than the previously reported designs. The transmitter consumes 98.1 mW from a 30 V supply while generating 1.38 MHz, 30 V pulses. The CMOS-CMUT system is tested in the transmit mode and shows full functionality in air medium.

The iQID Camera: An Ionizing-Radiation Quantum Imaging Detector

DOE PAGES

Miller, Brian W.; Gregory, Stephanie J.; Fuller, Erin S.; ...

2014-06-11

We have developed and tested a novel, ionizing-radiation Quantum Imaging Detector (iQID). This scintillation-based detector was originally developed as a high-resolution gamma-ray imager, called BazookaSPECT, for use in single-photon emission computed tomography (SPECT). Recently, we have investigated the detectors response and imaging potential with other forms of ionizing radiation including alpha, neutron, beta, and fission fragment particles. The detector’s response to a broad range of ionizing radiation has prompted its new title. The principle operation of the iQID camera involves coupling a scintillator to an image intensifier. The scintillation light generated particle interactions is optically amplified by the intensifier andmore » then re-imaged onto a CCD/CMOS camera sensor. The intensifier provides sufficient optical gain that practically any CCD/CMOS camera can be used to image ionizing radiation. Individual particles are identified and their spatial position (to sub-pixel accuracy) and energy are estimated on an event-by-event basis in real time using image analysis algorithms on high-performance graphics processing hardware. Distinguishing features of the iQID camera include portability, large active areas, high sensitivity, and high spatial resolution (tens of microns). Although modest, iQID has energy resolution that is sufficient to discrimate between particles. Additionally, spatial features of individual events can be used for particle discrimination. An important iQID imaging application that has recently been developed is single-particle, real-time digital autoradiography. In conclusion, we present the latest results and discuss potential applications.« less

Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering

PubMed Central

Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro

2017-01-01

Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system. PMID:29120358

Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering.

PubMed

Mars, Kamel; Lioe, De Xing; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

2017-11-09

Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

A low power on-chip class-E power amplifier for remotely powered implantable sensor systems

NASA Astrophysics Data System (ADS)

Ture, Kerim; Kilinc, Enver G.; Dehollain, Catherine

2015-06-01

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the required high inductance values which make the on-chip integration of the power amplifier difficult. The designed power amplifier is fully integrated in the remotely powered sensor system and fabricated in 0.18 μm CMOS process. The power is transferred to the implantable sensor system at 13.56 MHz by using an inductively coupled remote powering link. The induced AC voltage on the implant coil is converted into a DC voltage by a passive full-wave rectifier. A voltage regulator is used to suppress the ripples and create a clean and stable 1.8 V supply voltage for the sensor and communication blocks. The data collected from the sensors is transmitted by on-off keying modulated low-power transmitter at 1.2 GHz frequency. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. An additional output network is used for the power amplifier which makes the integration of the power amplifier fully on-chip. The integrated power amplifier with 0.2 V supply voltage has a drain efficiency of 31.5% at -10 dBm output power for 50 Ω load. The measurement results verify the functionality of the power amplifier and the remotely powered implantable sensor system. The data communication is also verified by using a commercial 50 Ω chip antenna and has 600 kbps data rate at 1 m communication distance.

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

NASA Astrophysics Data System (ADS)

Arslan, Emre; Yıldız, Merih; Minaei, Shahram

2015-06-01

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push-pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.

Field programmable analog array based on current differencing transconductance amplifiers and its application to high-order filter

NASA Astrophysics Data System (ADS)

He, Haizhen; Luo, Rongming; Hu, Zhenhua; Wen, Lei

2017-07-01

A current-mode field programmable analog array(FPAA) is presented in this paper. The proposed FPAA consists of 9 configurable analog blocks(CABs) which are based on current differencing transconductance amplifiers (CDTA) and trans-impedance amplifier (TIA). The proposed CABs interconnect through global lines. These global lines contain some bridge switches, which used to reduce the parasitic capacitance effectively. High-order current-mode low-pass and band-pass filter with transmission zeros based on the simulation of general passive RLC ladder prototypes is proposed and mapped into the FPAA structure in order to demonstrate the versatility of the FPAA. These filters exhibit good performance on bandwidth. Filter's cutoff frequency can be tuned from 1.2MHz to 40MHz.The proposed FPAA is simulated in a standard Charted 0.18μm CMOS process with +/-1.2V power supply to confirm the presented theory, and the results have good agreement with the theoretical analysis.

Ways to suppress click and pop for class D amplifiers

NASA Astrophysics Data System (ADS)

Haishi, Wang; Bo, Zhang; Jiang, Sun

2012-08-01

Undesirable audio click and pop may be generated in a speaker or headphone. Compared to linear (class A/B/AB) amplifiers, class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop. This article analyzes sources that generate click and pop in class D amplifiers, and corresponding ways to suppress them. For a class D amplifier with a single-ended input, click and pop is likely to be due to two factors. One is from a voltage difference (VDIF) between the voltage of an input capacitance (VCIN) and a reference voltage (VREF) of the input stage, and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage. In this article, a fast charging loop is introduced into the input stage to charge VCIN to roughly near VREF. Then a correction loop further charges or discharges VCIN, substantially equalizing it with VREF. Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC, and the power switches are disabled until the BFVC are set up successfully. A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process. Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

NASA Astrophysics Data System (ADS)

Suganthi, K.; Malarvizhi, S.

2018-03-01

A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier

PubMed Central

Tangsrirat, Worapong

2013-01-01

This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (G m s) as core circuits. The advantage of this element is that the current transfer ratios (i z/i p and i x/i z) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated. PMID:24381513

Low-power G m-C filter employing current-reuse differential difference amplifiers

DOE PAGES

Mincey, John S.; Briseno-Vidrios, Carlos; Silva-Martinez, Jose; ...

2016-08-10

This study deals with the design of low-power, high performance, continuous-time filters. The proposed OTA architecture employs current-reuse differential difference amplifiers in order to produce more power efficient Gm-C filter solutions. To demonstrate this, a 6th order low-pass Butterworth filter was designed in 0.18 m CMOS achieving a 65-MHz -3-dB frequency, an in-band input-referred third-order intercept point of 12.0 dBm, and an input referred noise density of 40 nV/Hz1=2, while only consuming 8.07 mW from a 1.8 V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

Low-power G m-C filter employing current-reuse differential difference amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mincey, John S.; Briseno-Vidrios, Carlos; Silva-Martinez, Jose

This study deals with the design of low-power, high performance, continuous-time filters. The proposed OTA architecture employs current-reuse differential difference amplifiers in order to produce more power efficient Gm-C filter solutions. To demonstrate this, a 6th order low-pass Butterworth filter was designed in 0.18 m CMOS achieving a 65-MHz -3-dB frequency, an in-band input-referred third-order intercept point of 12.0 dBm, and an input referred noise density of 40 nV/Hz1=2, while only consuming 8.07 mW from a 1.8 V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Cronus: A Distributed Operating System.

DTIC Science & Technology

1983-11-01

general, support movement of arbitrary objects from one host to another; some specific object tye will give rise to mobile objects, however. -34...File hierarchy is achieved by binding file identifiers to symbolic names in a hierarchical name space. Cronus CMos Aplications Since CMOS is the GCE

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Design of a 0.13 µm SiGe Limiting Amplifier with 14.6 THz Gain-Bandwidth-Product

NASA Astrophysics Data System (ADS)

Park, Sehoon; Du, Xuan-Quang; Grözing, Markus; Berroth, Manfred

2017-09-01

This paper presents the design of a limiting amplifier with 1-to-3 fan-out implementation in a 0.13 µm SiGe BiCMOS technology and gives a detailed guideline to determine the circuit parameters of the amplifier for optimum high-frequency performance based on simplified gain estimations. The proposed design uses a Cherry-Hooper topology for bandwidth enhancement and is optimized for maximum group delay flatness to minimize phase distortion of the input signal. With regard to a high integration density and a small chip area, the design employs no passive inductors which might be used to boost the circuit bandwidth with inductive peaking. On a RLC-extracted post-layout simulation level, the limiting amplifier exhibits a gain-bandwidth-product of 14.6 THz with 56.6 dB voltage gain and 21.5 GHz 3 dB bandwidth at a peak-to-peak input voltage of 1.5 mV. The group delay variation within the 3 dB bandwidth is less than 0.5 ps and the power dissipation at a power supply voltage of 3 V including output drivers is 837 mW.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Testing methodologies and systems for semiconductor optical amplifiers

NASA Astrophysics Data System (ADS)

Wieckowski, Michael

Semiconductor optical amplifiers (SOA's) are gaining increased prominence in both optical communication systems and high-speed optical processing systems, due primarily to their unique nonlinear characteristics. This in turn, has raised questions regarding their lifetime performance reliability and has generated a demand for effective testing techniques. This is especially critical for industries utilizing SOA's as components for system-in-package products. It is important to note that very little research to date has been conducted in this area, even though production volume and market demand has continued to increase. In this thesis, the reliability of dilute-mode InP semiconductor optical amplifiers is studied experimentally and theoretically. The aging characteristics of the production level devices are demonstrated and the necessary techniques to accurately characterize them are presented. In addition, this work proposes a new methodology for characterizing the optical performance of these devices using measurements in the electrical domain. It is shown that optical performance degradation, specifically with respect to gain, can be directly qualified through measurements of electrical subthreshold differential resistance. This metric exhibits a linear proportionality to the defect concentration in the active region, and as such, can be used for prescreening devices before employing traditional optical testing methods. A complete theoretical analysis is developed in this work to explain this relationship based upon the device's current-voltage curve and its associated leakage and recombination currents. These results are then extended to realize new techniques for testing semiconductor optical amplifiers and other similarly structured devices. These techniques can be employed after fabrication and during packaged operation through the use of a proposed stand-alone testing system, or using a proposed integrated CMOS self-testing circuit. Both methods are capable of ascertaining SOA performance based solely on the subthreshold differential resistance signature, and are a first step toward the inevitable integration of self-testing circuits into complex optoelectronic systems.

Multi-mode multi-band power amplifier module with high low-power efficiency

NASA Astrophysics Data System (ADS)

Xuguang, Zhang; Jie, Jin

2015-10-01

Increasingly, mobile communications standards require high power efficiency and low currents in the low power mode. This paper proposes a fully-integrated multi-mode and multi-band power amplifier module (PAM) to meet these requirements. A dual-path PAM is designed for high-power mode (HPM), medium-power mode (MPM), and low-power mode (LPM) operations without any series switches for different mode selection. Good performance and significant current saving can be achieved by using an optimized load impedance design for each power mode. The PAM is tapeout with the InGaP/GaAs heterojunction bipolar transistor (HBT) process and the 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The test results show that the PAM achieves a very low quiescent current of 3 mA in LPM. Meanwhile, across the 1.7-2.0 GHz frequency, the PAM performs well. In HPM, the output power is 28 dBm with at least 39.4% PAE and -40 dBc adjacent channel leakage ratio 1 (ACLR1). In MPM, the output power is 17 dBm, with at least 21.3% PAE and -43 dBc ACLR1. In LPM, the output power is 8 dBm, with at least 18.2% PAE and -40 dBc ACLR1. Project supported by the National Natural Science Foundation of China (No. 61201244).

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Modeling Single-Event Transient Propagation in a SiGe BiCMOS Direct-Conversion Receiver

NASA Astrophysics Data System (ADS)

Ildefonso, Adrian; Song, Ickhyun; Tzintzarov, George N.; Fleetwood, Zachary E.; Lourenco, Nelson E.; Wachter, Mason T.; Cressler, John D.

2017-08-01

The propagation of single-event transient (SET) signals in a silicon-germanium direct-conversion receiver carrying modulated data is explored. A theoretical analysis of transient propagation, verified by simulation, is presented. A new methodology to characterize and quantify the impact of SETs in communication systems carrying modulated data is proposed. The proposed methodology uses a pulsed radiation source to induce distortions in the signal constellation. The error vector magnitude due to SETs can then be calculated to quantify errors. Two different modulation schemes were simulated: QPSK and 16-QAM. The distortions in the constellation diagram agree with the presented circuit theory. Furthermore, the proposed methodology was applied to evaluate the improvements in the SET response due to a known radiation-hardening-by-design (RHBD) technique, where the common-base device of the low-noise amplifier was operated in inverse mode. The proposed methodology can be a valid technique to determine the most sensitive parts of a system carrying modulated data.

Spin switches for compact implementation of neuron and synapse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quang Diep, Vinh, E-mail: vdiep@purdue.edu; Sutton, Brian; Datta, Supriyo

2014-06-02

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltagesmore » that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.« less

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

A three channel telemetry system

NASA Technical Reports Server (NTRS)

Lesho, Jeffery C.; Eaton, Harry A. C.

1993-01-01

A three channel telemetry system intended for biomedical applications is described. The transmitter is implemented in a single chip using a 2 micron BiCMOS processes. The operation of the system and the test results from the latest chip are discussed. One channel is always dedicated to temperature measurement while the other two channels are generic. The generic channels carry information from transducers that are interfaced to the system through on-chip general purpose operational amplifiers. The generic channels have different bandwidths: one from dc to 250 Hz and the other from dc to 1300 Hz. Each generic channel modulates a current controlled oscillator to produce a frequency modulated signal. The two frequency modulated signals are summed and used to amplitude modulate the temperature signal which acts as a carrier. A near-field inductive link telemeters the combined signals over a short distance. The chip operates on a supply voltage anywhere from 2.5 to 3.6 Volts and draws less than 1 mA when transmitting a signal. The chip can be incorporated into ingestible, implantable and other configurations. The device can free the patient from tethered data collection systems and reduces the possibility of infection from subcutaneous leads. Data telemetry can increase patient comfort leading to a greater acceptance of monitoring.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Integrated imaging sensor systems with CMOS active pixel sensor technology

NASA Technical Reports Server (NTRS)

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Low energy CMOS for space applications

NASA Technical Reports Server (NTRS)

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Multi-band infrared camera systems

NASA Astrophysics Data System (ADS)

Davis, Tim; Lang, Frank; Sinneger, Joe; Stabile, Paul; Tower, John

1994-12-01

The program resulted in an IR camera system that utilizes a unique MOS addressable focal plane array (FPA) with full TV resolution, electronic control capability, and windowing capability. Two systems were delivered, each with two different camera heads: a Stirling-cooled 3-5 micron band head and a liquid nitrogen-cooled, filter-wheel-based, 1.5-5 micron band head. Signal processing features include averaging up to 16 frames, flexible compensation modes, gain and offset control, and real-time dither. The primary digital interface is a Hewlett-Packard standard GPID (IEEE-488) port that is used to upload and download data. The FPA employs an X-Y addressed PtSi photodiode array, CMOS horizontal and vertical scan registers, horizontal signal line (HSL) buffers followed by a high-gain preamplifier and a depletion NMOS output amplifier. The 640 x 480 MOS X-Y addressed FPA has a high degree of flexibility in operational modes. By changing the digital data pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or noninterlaced format. The thermal sensitivity performance of the second system's Stirling-cooled head was the best of the systems produced.

Bio-isolated dc operational amplifier. [for bioelectric measurements

NASA Technical Reports Server (NTRS)

Lee, R. D. (Inventor)

1974-01-01

A bio-isolated dc operational amplifier is described for use in making bioelectrical measurements of a patient while providing isolation of the patient from electrical shocks. The circuit contains a first operational amplifier coupled to the patient with its output coupled in a forward loop through a first optic coupler to a second operational amplifier. The output of the second operational amplifier is coupled to suitable monitoring circuitry via a feedback circuit including a second optic coupler to the input of the first operational amplifier.

Single-Event Effects in High-Frequency Linear Amplifiers: Experiment and Analysis

NASA Astrophysics Data System (ADS)

Zeinolabedinzadeh, Saeed; Ying, Hanbin; Fleetwood, Zachary E.; Roche, Nicolas J.-H.; Khachatrian, Ani; McMorrow, Dale; Buchner, Stephen P.; Warner, Jeffrey H.; Paki-Amouzou, Pauline; Cressler, John D.

2017-01-01

The single-event transient (SET) response of two different silicon-germanium (SiGe) X-band (8-12 GHz) low noise amplifier (LNA) topologies is fully investigated in this paper. The two LNAs were designed and implemented in 130nm SiGe HBT BiCMOS process technology. Two-photon absorption (TPA) laser pulses were utilized to induce transients within various devices in these LNAs. Impulse response theory is identified as a useful tool for predicting the settling behavior of the LNAs subjected to heavy ion strikes. Comprehensive device and circuit level modeling and simulations were performed to accurately simulate the behavior of the circuits under ion strikes. The simulations agree well with TPA measurements. The simulation, modeling and analysis presented in this paper can be applied for any other circuit topologies for SET modeling and prediction.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

PubMed

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, G.; Garcia-Scivres, M.; Paramonov, A.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Charter Management Organizations: An Emerging Approach to Scaling up What Works

ERIC Educational Resources Information Center

Farrell, Caitlin; Wohlstetter, Priscilla; Smith, Joanna

2012-01-01

Policymakers have shown increasing interest in replicating high-quality education models as a way to improve chronically underperforming schools. Charter management organizations (CMOs) have been touted as one organizational model poised to be such a vehicle for reform. CMOs are nonprofit organizations that operate a network of charter schools…

Review of "Charter-School Management Organizations: Diverse Strategies and Diverse Student Impacts"

ERIC Educational Resources Information Center

Fuller, Bruce

2012-01-01

This report details how charter schools are increasingly run by private, nonprofit management organizations called charter school management organizations (CMOs). The researchers find that most CMOs serve urban students from low-income families, operate small schools that offer more instructional time, and attract teachers loyal to each school's…

Cargo Movement Operations System (CMOS) Final System Segment Specification (Change 04), Increment II

DTIC Science & Technology

1991-11-14

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSS-002 PROGRAM OFFICE...only used for air cargo, does not alter the requirement for a surface cargo checklist. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Single photon detection using Geiger mode CMOS avalanche photodiodes

NASA Astrophysics Data System (ADS)

Lawrence, William G.; Stapels, Christopher; Augustine, Frank L.; Christian, James F.

2005-10-01

Geiger mode Avalanche Photodiodes fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication technology combine high sensitivity detectors with pixel-level auxiliary circuitry. Radiation Monitoring Devices has successfully implemented CMOS manufacturing techniques to develop prototype detectors with active diameters ranging from 5 to 60 microns and measured detection efficiencies of up to 60%. CMOS active quenching circuits are included in the pixel layout. The actively quenched pixels have a quenching time less than 30 ns and a maximum count rate greater than 10 MHz. The actively quenched Geiger mode avalanche photodiode (GPD) has linear response at room temperature over six orders of magnitude. When operating in Geiger mode, these GPDs act as single photon-counting detectors that produce a digital output pulse for each photon with no associated read noise. Thermoelectrically cooled detectors have less than 1 Hz dark counts. The detection efficiency, dark count rate, and after-pulsing of two different pixel designs are measured and demonstrate the differences in the device operation. Additional applications for these devices include nuclear imaging and replacement of photomultiplier tubes in dosimeters.

Low noise tuned amplifier

NASA Technical Reports Server (NTRS)

Kleinberg, L. L. (Inventor)

1984-01-01

A bandpass amplifier employing a field effect transistor amplifier first stage is described with a resistive load either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load of the field effect transistor.

Miniature atomic scalar magnetometer for space based on the rubidium isotope 87Rb.

PubMed

Korth, Haje; Strohbehn, Kim; Tejada, Francisco; Andreou, Andreas G; Kitching, John; Knappe, Svenja; Lehtonen, S John; London, Shaughn M; Kafel, Matiwos

2016-08-01

A miniature atomic scalar magnetometer based on the rubidium isotope 87 Rb was developed for operation in space. The instrument design implements both M x and M z mode operation and leverages a novel microelectromechanical system (MEMS) fabricated vapor cell and a custom silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS) integrated circuit. The vapor cell has a volume of only 1 mm 3 so that it can be efficiently heated to its operating temperature by a specially designed, low-magnetic-field-generating resistive heater implemented in multiple metal layers of the transparent sapphire substrate of the SOS-CMOS chips. The SOS-CMOS chip also hosts the Helmholtz coil and associated circuitry to stimulate the magnetically sensitive atomic resonance and temperature sensors. The prototype instrument has a total mass of fewer than 500 g and uses less than 1 W of power, while maintaining a sensitivity of 15 pT/√Hz at 1 Hz, comparable to present state-of-the-art absolute magnetometers.

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

PubMed

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

2012-04-10

A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188more » ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.« less

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

High-speed detection of DNA translocation in nanopipettes

NASA Astrophysics Data System (ADS)

Fraccari, Raquel L.; Ciccarella, Pietro; Bahrami, Azadeh; Carminati, Marco; Ferrari, Giorgio; Albrecht, Tim

2016-03-01

We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface.We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface. Electronic supplementary information (ESI) available: Gel electrophoresis confirming lengths and purity of DNA samples, comparison between Axopatch 200B and custom-built setup, comprehensive low-noise amplifier characterization, representative I-V curves of nanopipettes used, typical scatter plots of τ vs. peak amplitude for the four LDNA's used, table of most probable τ values, a comparison between different fitting models for the DNA translocation time distribution, further details on the stochastic numerical simulation of the scaling statistics and the derivation of the extended model for the length dependence of τ. See DOI: 10.1039/c5nr08634e

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

NASA Astrophysics Data System (ADS)

Zhu, Tiezhu; Mo, Taishan; Ye, Tianchun

2017-12-01

An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor's transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of -28 dBm for a bit error rate of 10-10 at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm2 and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Student Achievement in New York City Middle Schools Affiliated with Achievement First and Uncommon Schools. Final Report

ERIC Educational Resources Information Center

Teh, Bing-ru; McCullough, Moira; Gill, Brian P.

2010-01-01

In recent years, some of the most ambitious charter school operators, with the support of philanthropic investors, have sought to increase the scale and scope of their work by creating charter management organizations (CMOs) that aim to replicate effective charter school models across multiple campuses. CMOs are nonprofit organizations with…

"It's Just Really Not Me": How Pre-Service English Teachers from a Traditional Teacher Education Program Experience Student-Teaching in Charter-School Networks

ERIC Educational Resources Information Center

Salerno, April S.; Heny, Natasha A.

2016-01-01

Though teacher educators nationwide are considering ways to provide urban placements for pre-service teachers (PSTs), little research has examined how PSTs experience placements in schools operated by charter management organizations (CMOs). This study considers CMOs--which often hold particular instructional and classroom management…

A high gain wide dynamic range transimpedance amplifier for optical receivers

NASA Astrophysics Data System (ADS)

Lianxi, Liu; Jiao, Zou; Yunfei, En; Shubin, Liu; Yue, Niu; Zhangming, Zhu; Yintang, Yang

2014-01-01

As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.

Cargo Movement Operations System (CMOS). Interface Requirements Specification. Revised Draft. Increment 2

DTIC Science & Technology

1990-08-02

NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment ------------ ---- --------- -------------------------------------------- 1. 12 Table 3.1.2 Add "(On-Base)" to CC0205 - ADAM III to CMOS. 2. 28 3.10.2 c. Add reference to Table 3.11.21. 3. 30 3.12.1 b.(2) Change "Conformation of Listed Manifest" to "Confirmation of Lifted Manifest". 4. 50 3.34 d. Change this paragraph ref 2rence to 3.33 d. 5. 58 Table 6.3 Change the second "CMOS to ADAM III

Wafer-scale development and experimental verification of 0.36 mm2 228 mV open-circuit-voltage solid-state CMOS-compatible glucose fuel cell

NASA Astrophysics Data System (ADS)

Arata, Shigeki; Hayashi, Kenya; Nishio, Yuya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-04-01

The world’s smallest (0.36 mm2) solid-state CMOS-compatible glucose fuel cell, which exhibits an open-circuit voltage (OCV) of 228 mV and a power generation density of 1.32 µW/cm2 with a 30 mM glucose solution, is reported in this paper. Compared with conventional wet etching, dry etching (reactive ion etching) for patterning minimizes damage to the anode and cathode, resulting in a cell with a small size and a high OCV, sufficient for CMOS circuit operation.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Llamas: Large-area microphone arrays and sensing systems

NASA Astrophysics Data System (ADS)

Sanz-Robinson, Josue

Large-area electronics (LAE) provides a platform to build sensing systems, based on distributing large numbers of densely spaced sensors over a physically-expansive space. Due to their flexible, "wallpaper-like" form factor, these systems can be seamlessly deployed in everyday spaces. They go beyond just supplying sensor readings, but rather they aim to transform the wealth of data from these sensors into actionable inferences about our physical environment. This requires vertically integrated systems that span the entirety of the signal processing chain, including transducers and devices, circuits, and signal processing algorithms. To this end we develop hybrid LAE / CMOS systems, which exploit the complementary strengths of LAE, enabling spatially distributed sensors, and CMOS ICs, providing computational capacity for signal processing. To explore the development of hybrid sensing systems, based on vertical integration across the signal processing chain, we focus on two main drivers: (1) thin-film diodes, and (2) microphone arrays for blind source separation: 1) Thin-film diodes are a key building block for many applications, such as RFID tags or power transfer over non-contact inductive links, which require rectifiers for AC-to-DC conversion. We developed hybrid amorphous / nanocrystalline silicon diodes, which are fabricated at low temperatures (<200 °C) to be compatible with processing on plastic, and have high current densities (5 A/cm2 at 1 V) and high frequency operation (cutoff frequency of 110 MHz). 2) We designed a system for separating the voices of multiple simultaneous speakers, which can ultimately be fed to a voice-command recognition engine for controlling electronic systems. On a device level, we developed flexible PVDF microphones, which were used to create a large-area microphone array. On a circuit level we developed localized a-Si TFT amplifiers, and a custom CMOS IC, for system control, sensor readout and digitization. On a signal processing level we developed an algorithm for blind source separation in a real, reverberant room, based on beamforming and binary masking. It requires no knowledge about the location of the speakers or microphones. Instead, it uses cluster analysis techniques to determine the time delays for beamforming; thus, adapting to the unique acoustic environment of the room.

Two multichannel integrated circuits for neural recording and signal processing.

PubMed

Obeid, Iyad; Morizio, James C; Moxon, Karen A; Nicolelis, Miguel A L; Wolf, Patrick D

2003-02-01

We have developed, manufactured, and tested two analog CMOS integrated circuit "neurochips" for recording from arrays of densely packed neural electrodes. Device A is a 16-channel buffer consisting of parallel noninverting amplifiers with a gain of 2 V/V. Device B is a 16-channel two-stage analog signal processor with differential amplification and high-pass filtering. It features selectable gains of 250 and 500 V/V as well as reference channel selection. The resulting amplifiers on Device A had a mean gain of 1.99 V/V with an equivalent input noise of 10 microV(rms). Those on Device B had mean gains of 53.4 and 47.4 dB with a high-pass filter pole at 211 Hz and an equivalent input noise of 4.4 microV(rms). Both devices were tested in vivo with electrode arrays implanted in the somatosensory cortex.

A Low Noise Amplifier for Neural Spike Recording Interfaces

PubMed Central

Ruiz-Amaya, Jesus; Rodriguez-Perez, Alberto; Delgado-Restituto, Manuel

2015-01-01

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models. PMID:26437411

A Low Noise Amplifier for Neural Spike Recording Interfaces.

PubMed

Ruiz-Amaya, Jesus; Rodriguez-Perez, Alberto; Delgado-Restituto, Manuel

2015-09-30

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz-7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

Novel pre-equalization transimpedance amplifier for 10 Gb/s optical interconnects

NASA Astrophysics Data System (ADS)

Qiwei, Song; Luhong, Mao; Sheng, Xie; Yuzhuo, Kang

2015-07-01

This paper presents a modified regulated cascode (RGC) transimpedance amplifier (TIA) with a novel pre-equalized technique. The pre-equalized circuit employed the broadband series inductive π-network and Gm-boosting technique. The introduction of this technique compensates the transferred signal at the input port of the TIA without an increase in power dissipation. Furthermore, a novel miller capacitance degeneration method is designed in the gain stage for further bandwidth improvement. The TIA is realized in UMC 0.18 πm CMOS technology and tested with an on-chip 0.3 pF capacitor to emulate a photodetector (PD). The measured transimpedance gain amounts to 57 dBΩ with a -3 dB bandwidth of about 8.2 GHz and consumes only 22 mW power from a single 1.8 V supply. Project supported by the National Natural Science Foundation of China (Nos. 61036002, 61474081).

Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

PubMed

Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

2015-08-01

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Noise and linearity optimization methods for a 1.9GHz low noise amplifier.

PubMed

Guo, Wei; Huang, Da-Quan

2003-01-01

Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

Gain drift compensation with no-feedback-loop developed for the X-IFU/ATHENA readout chain

NASA Astrophysics Data System (ADS)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Goldwurm, A.

2016-07-01

The focal plane of the X-ray Integral Field Unit (X-IFU) instrument of the Athena observatory is composed of about 4000 micro-calorimeters. These sensors, based on superconducting Transition Edge Sensors, are read out through a frequency multiplexer and a base-band feedback to linearize SQUIDs. However, the loop gain of this feedback is lower than 10 in the modulated TES signal bandwidth, which is not enough to fix the gain of the full readout chain. Calibration of the instrument is planned to be done at a time scale larger than a dozen minutes and the challenging energy resolution goal of 2.5 eV at 6 keV will probably require a gain stability larger than 10-4 over a long duration. A large part of this gain is provided by a Low-Noise Amplifier (LNA) in the Warm Front-End Electronics (WFEE). To reach such gain stability over more than a dozen minutes, this non-cooled amplifier has to cope with the temperature and supply voltage variations. Moreover, mainly for noise reasons, common large loop gain with feedback can not be used. We propose a new amplifier topology using diodes as loads of a differential amplifier to provide a fixed voltage gain, independent of the temperature and of the bias fluctuations. This amplifier is designed using a 350 nm SiGe BiCMOS technology and is part of an integrated circuit developed for the WFEE. Our simulations provide the expected gain drift and noise performances of such structure. Comparison with standard resistive loaded differential pair clearly shows the advantages of the proposed amplifier topology with a gain drift decreasing by more than an order of magnitude. Performances of this diode loaded amplifier are discussed in the context of the X-IFU requirements.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

PubMed

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Wobbly strings: calculating the capture rate of a webcam using the rolling shutter effect in a guitar

NASA Astrophysics Data System (ADS)

Cunnah, David

2014-07-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

Wobbly Strings: Calculating the Capture Rate of a Webcam Using the Rolling Shutter Effect in a Guitar

ERIC Educational Resources Information Center

Cunnah, David

2014-01-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

DEAL annual report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Misra, Shashank

2017-11-01

The digital electronics at the atomic limit (DEAL) project seeks to leverage Sandia's atomic-precision fabrication capability to realize the theorized orders-of-magnitude improvement in operating voltage for tunnel field effect transistors (TFETs) compared to CMOS. Not only are low-power digital circuits a critical element of many national security systems (e.g. satellites), TFETs can perform circuit functions inaccessible to CMOS (e.g. polymorphism).

Cargo Movement Operations System (CMOS). Draft Software Programmer’s Manual

DTIC Science & Technology

1990-07-12

NO ( ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment 1. 3-4 3.2 Change...reader in locating pertinent information. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: COMMENT...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SPM-0006 PROGRAM

Cargo Movement Operation Systems (CMOS) Interface Design Document (Preliminary)

DTIC Science & Technology

1990-04-29

between these versions, each must be individually numbered. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: IDDl-0004 PROGRAM OFFICE CONTROL NUMBER...COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: IDDl-0006

Cargo Movement Operations System (CMOS) Preliminary Software Test Description, Increment II

DTIC Science & Technology

1991-06-26

occurred within this shall statement. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS...COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED ( ] ORIGINATOR CONTROL NUMBER: STD1-0004 PROGRAM OFFICE CONTROL NUMBER...ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] SYSTEM ENVIRONMENT STD The following comment is related

Cargo Movement Operations System (CMOS). Updated Draft Software User’s Manual. Increment I

DTIC Science & Technology

1991-03-22

ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ...shall be combined. Therefore, the menu structure should reflect that change. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ... COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SUM-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM DISCREPANCY

NV-CMOS HD camera for day/night imaging

NASA Astrophysics Data System (ADS)

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation †

PubMed Central

Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

2017-01-01

Infrared imaging technology, used both to study deep-space bodies’ radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a 2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW. PMID:28574466

A noiseless, kHz frame rate imaging detector for AO wavefront sensors based on MCPs read out with the Medipix2 CMOS pixel chip

NASA Astrophysics Data System (ADS)

Vallerga, J. V.; McPhate, J. B.; Tremsin, A. S.; Siegmund, O. H. W.; Mikulec, B.; Clark, A. G.

2004-12-01

Future wavefront sensors in adaptive optics (AO) systems for the next generation of large telescopes (> 30 m diameter) will require large formats (512x512) , kHz frame rates, low readout noise (<3 electrons) and high optical QE. The current generation of CCDs cannot achieve the first three of these specifications simultaneously. We present a detector scheme that can meet the first three requirements with an optical QE > 40%. This detector consists of a vacuum tube with a proximity focused GaAs photocathode whose photoelectrons are amplified by microchannel plates and the resulting output charge cloud counted by a pixelated CMOS application specific integrated circuit (ASIC) called the Medipix2 (http://medipix.web.cern.ch/MEDIPIX/). Each 55 micron square pixel of the Medipix2 chip has an amplifier, discriminator and 14 bit counter and the 256x256 array can be read out in 287 microseconds. The chip is 3 side abuttable so a 512x512 array is feasible in one vacuum tube. We will present the first results with an open-faced, demountable version of the detector where we have mounted a pair of MCPs 500 microns above a Medipix2 readout inside a vacuum chamber and illuminated it with UV light. The results include: flat field response, spatial resolution, spatial linearity on the sub-pixel level and global event counting rate. We will also discuss the vacuum tube design and the fabrication issues associated with the Medipix2 surviving the tube making process.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, James D.

1997-01-01

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controled switching and effecting a direction of rectification.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, J.D.

1997-09-02

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controlled switching and effecting a direction of rectification. 89 figs.

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Multi-pass amplifier architecture for high power laser systems

DOEpatents

Manes, Kenneth R; Spaeth, Mary L; Erlandson, Alvin C

2014-04-01

A main amplifier system includes a first reflector operable to receive input light through a first aperture and direct the input light along an optical path. The input light is characterized by a first polarization. The main amplifier system also includes a first polarizer operable to reflect light characterized by the first polarization state. The main amplifier system further includes a first and second set of amplifier modules. Each of the first and second set of amplifier modules includes an entrance window, a quarter wave plate, a plurality of amplifier slablets arrayed substantially parallel to each other, and an exit window. The main amplifier system additionally includes a set of mirrors operable to reflect light exiting the first set of amplifier modules to enter the second set of amplifier modules and a second polarizer operable to reflect light characterized by a second polarization state.

Cargo Movement Operations System (CMOS). Updated Software Requirements Specifications, Increment 2, (Communications CSCI)

DTIC Science & Technology

1990-11-14

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SRS2-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...e. (1st and 3rd sentence), 3.2.7.21, and 3.2.8 b. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ COMMENT DISPOSITION...3rd 3.2.7.6 4th 3.2.7.22 4th 3.2.7.7 4th 3.2.8 d. 2nd & 3rd 3.2.7.9 4th 3.2.8 e. 2nd CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [

Bio-isolated DC operational amplifier

NASA Technical Reports Server (NTRS)

Lee, R. D.

1974-01-01

Possibility of shocks from leakage currents can be reduced by use of isolated preamplifiers. Amplifier consists of battery-powered operational amplifier coupled by means of light-emitting diodes to another amplifier which may be grounded and operated from ac power mains or separate battery supply.

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

NASA Technical Reports Server (NTRS)

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Cargo Movement Operations System (CMOS) Final Software Design Document, Change 01, Increment I

DTIC Science & Technology

1991-03-22

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDDl-0002 PROGRAM OFFICE...COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDDl-0003 PROGRAM OFFICE CONTROL NUMBER: DATA...CARMODE and SURRTG. RATIONALE: Request clarification of these deletions. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Cargo Movement Operations System (CMOS) Final System Segment Design Document Increment II, (ChaNge 02)

DTIC Science & Technology

1990-11-07

present, the documents are in conflict with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] p ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [1 ORIGINATOR CONTROL NUMBER: SSDD-0005 PROGRAM OFFICE

640 X 480 MOS PtSi IR sensor

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1991-12-01

The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

An OTA-C filter for ECG acquisition systems with highly linear range and less passband attenuation

NASA Astrophysics Data System (ADS)

Jihai, Duan; Chuang, Lan; Weilin, Xu; Baolin, Wei

2015-05-01

A fifth order operational transconductance amplifier-C (OTA-C) Butterworth type low-pass filter with highly linear range and less passband attenuation is presented for wearable bio-telemetry monitoring applications in a UWB wireless body area network. The source degeneration structure applied in typical small transconductance circuit is improved to provide a highly linear range for the OTA-C filter. Moreover, to reduce the passband attenuation of the filter, a cascode structure is employed as the output stage of the OTA. The OTA-based circuit is operated in weak inversion due to strict power limitation in the biomedical chip. The filter is fabricated in a SMIC 0.18-μm CMOS process. The measured results for the filter have shown a passband gain of -6.2 dB, while the -3-dB frequency is around 276 Hz. For the 0.8 VPP sinusoidal input at 100 Hz, a total harmonic distortion (THD) of -56.8 dB is obtained. An electrocardiogram signal with noise interference is fed into this chip to validate the function of the designed filter. Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Natural Science Foundation (No. 2013GXNSFAA019333).

The design and performance of a 2.5-GHz telecommand link for wireless biomedical monitoring.

PubMed

Crumley, G C; Evans, N E; Scanlon, W G; Burns, J B; Trouton, T G

2000-12-01

This paper details the implementation and operational performance of a minimum-power 2.45-GHz pulse receiver and a companion on-off keyed transmitter for use in a semi-active, duplex RF biomedical transponder. A 50-ohm microstrip stub-matched zero-bias diode detector forms the heart of a body-worn receiver that has a (CMOS baseband amplifier consuming 20 microA from +3 V and achieves a tangential sensitivity of -53 dBm. The base transmitter generates 0.5 W of peak RF output power into 50 ohms. Both linear and right-hand circularly polarized Tx-Rx antenna sets were employed in system reliability trials carried out in a hospital Coronary Care Unit. For transmitting antenna heights between 0.3 and 2.2 m above floor level, transponder interrogations were 95% reliable within the 67-m2 area of the ward, falling to an average of 46% in the surrounding rooms and corridors. Overall, the circular antenna set gave the higher reliability and lower propagation power decay index.

Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

PubMed

Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

2014-05-01

This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka; Schlecht, Erich; Samoska, Lorene

2009-01-01

Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have prohibitively low impedances. Yet another advantage afforded by the virtual ground of the differential configuration is elimination of the need for a ground plane and, hence, elimination of the need for back-side metallization of the MMIC chip. In turn, elimination of the back-side metallization simplifies fabrication, reduces parasitic capacitances, and enables mounting of the MMIC in the electric-field plane ("E-plane") of a waveguide. E-plane mounting is consistent with (and essential for the utility of) the finline configuration, in which transmission lines lie on a dielectric sheet in the middle of a broad side of the waveguide. E-plane mounting offers a combination of low loss and ease of assembly because no millimeter-wave wire bonds or transition substrates are required. Moreover, because there is no ground plane behind the MMIC, the impedance for the detrimental even (single-ended) mode is high, suppressing coupling to that mode. Still another advantage of E-plane mounting is that the fundamental waveguide mode is inherently differential, eliminating the need for a balun to excite the differential mode.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Design and fabrication of a CMOS-compatible MHP gas sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao

2014-03-15

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperaturemore » in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.« less

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

A CMOS Humidity Sensor for Passive RFID Sensing Applications

PubMed Central

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

PubMed

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Limit circuit prevents overdriving of operational amplifier

NASA Technical Reports Server (NTRS)

Openshaw, F. L.

1967-01-01

Cutoff-type high gain amplifier coupled by a diode prevents overdriving of operational amplifier. An amplified feedback signal offsets the excess input signal that tends to cause the amplifier to exceed its preset limit. The output is, therfore, held to the set clamp level.

A novel pseudo resistor structure for biomedical front-end amplifiers.

PubMed

Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

2015-08-01

This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

Low-Power Low-Noise Amplifier Using Attenuation-Adaptive Noise Control for Ultrasound Imaging Systems.

PubMed

Jung, Sung-Jin; Hong, Seong-Kwan; Kwon, Oh-Kyong

2017-02-01

This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

NASA Astrophysics Data System (ADS)

Gang, Jin; Yiqi, Zhuang; Yue, Yin; Miao, Cui

2015-03-01

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from -4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

CMOS Camera Array With Onboard Memory

NASA Technical Reports Server (NTRS)

Gat, Nahum

2009-01-01

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Cargo Movement Operations System (CMOS) Updated Draft Software Requirements Specification (Applications CSCI) Increment II

DTIC Science & Technology

1990-11-29

appropriate to combine them into one paragraph. CMOS PMO ACCEPTS COY24ENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT...COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SRS1-0004...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SRS1-0005 PROGRAM OFFICE

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

NASA Astrophysics Data System (ADS)

Varlamava, Volha; De Amicis, Giovanni; Del Monte, Andrea; Perticaroli, Stefano; Rao, Rosario; Palma, Fabrizio

2016-08-01

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

PubMed

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

PubMed Central

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

2015-01-01

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

A CMOS smart temperature and humidity sensor with combined readout.

PubMed

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

NASA Astrophysics Data System (ADS)

Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

2017-02-01

The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

PubMed

Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

2015-08-01

This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Papapolymerou, John

2003-01-01

180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

PubMed

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

NASA Astrophysics Data System (ADS)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

Crystal oscillators using negative voltage gain, single pole response amplifiers

NASA Technical Reports Server (NTRS)

Kleinberg, Leonard L. (Inventor)

1989-01-01

A simple and inexpensive crystal oscillator is provided which employs negative voltage gain, single pole response amplifiers. The amplifiers may include such configurations as gate inverters, operational amplifiers and conventional bipolar transistor amplifiers, all of which operate at a frequency which is on the roll-off portion of their gain versus frequency curve. Several amplifier feedback circuit variations are employed to set desired bias levels and to allow the oscillator to operate at the crystal's fundamental frequency or at an overtone of the fundamental frequency. The oscillator is made less expensive than comparable oscillators by employing relatively low frequency amplifiers and operating them at roll-off, at frequencies beyond which they are customarily used. Simplicity is provided because operation at roll-off eliminates components ordinarily required in similar circuits to provide sufficient phase-shift in the feedback circuitry for oscillation to occur.

Log amplifier with pole-zero compensation

DOEpatents

Brookshier, William

1987-01-01

A logarithmic amplifier circuit provides pole-zero compensation for improved stability and response time over 6-8 decades of input signal frequency. The amplifier circuit includes a first operational amplifier with a first feedback loop which includes a second, inverting operational amplifier in a second feedback loop. The compensated output signal is provided by the second operational amplifier with the log elements, i.e., resistors, and the compensating capacitors in each of the feedback loops having equal values so that each break point or pole is offset by a compensating break point or zero.

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

A 12b 200kS/s 0.52mA 0.47mm2 Algorithmic A/D Converter for MEMS Applications

NASA Astrophysics Data System (ADS)

Kim, Young-Ju; Choi, Hee-Cheol; Lee, Seung-Hoon; Cho, Dongil “Dan”

This work describes a 12b 200kS/s 0.52mA 0.47mm2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200kS/s and 10kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18μm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200kS/s, respectively. The ADC occupies an active die area of 0.47mm2 and consumes 0.94mW at 200kS/s and 0.63mW at 10kS/s with a 1.8V supply.

Note: cryogenic low-noise dc-coupled wideband differential amplifier based on SiGe heterojunction bipolar transistors.

PubMed

Beev, Nikolai; Kiviranta, Mikko

2012-06-01

Silicon-germanium heterojunction bipolar transistors can be used to construct low-noise cryogenic amplifiers. We present a dc-coupled differential amplifier capable of operating down to 10 K. In this temperature regime it has bandwidth of 15 MHz and noise temperature as low as 1.3 K. When operated at liquid nitrogen temperature of 77 K, the measured noise temperature is lower than 3 K. The amplifier is based on the commercially available transistors NESG3031 and operational amplifier OPA836 and is capable of standalone operation without any additional stages at room temperature.

A portable electronic system for radiation dosimetry using electrets

NASA Astrophysics Data System (ADS)

Cruvinel, P. E.; Mascarenhas, S.; Cameron, J.

1990-02-01

An electret dosimeter with a cylindrical active volume has been introduced by Mascarenhas and collaborators [Proc. 10th Anniversary Conf. 1969-1979, Associacâo Brasileira de Fisicos em Medicina, p. 488; Topics Appl. Phys. 33 (1987) 321] for possible use in personnel and area monitoring. The full energy response curve as well as the degree of reproducibility and accuracy of the dosimeter are reported in a previous report [O. Guerrini, Master Science Thesis, São Carlos, USP-IFQSC (1982)]. For dimensions similar to those of the common pen dosimeter, the electret has a total surface charge of the order of 10 -9 C and it has a readout sensitivity of the order of 10 -5 Gy with a useful range of 5 × 10 -2 Gy. In this paper we describe a portable electronic system to measure X and γ-rays using a cylindrical electret ionization chamber. It uses commercially available operational amplifiers, and charge measurements can also be made by connecting a suitable capacitor in the feedback loop. With this system it is possible to measure equivalent surface charges up to (19.99±0.01) on the dosimeter. The readout doses are shown on a 3 {1}/{2} digit liquid crystal display (LCD). We have used complementary metal oxide semiconductor (CMOS) and bipolar metal oxide semiconductor (BiMOS) operatonal amplifier devices in the system's design. This choice provides small power consumption and is ideal for battery powered instruments. Furthermore the instrument is ideally suited for in situ measurements of X and γ radiation using a cylindrical electret ionization chamber.

Operational Amplifiers.

ERIC Educational Resources Information Center

Foxcroft, G. E.

1986-01-01

Addresses the introduction of low cost equipment into high school and college physical science classes. Examines the properties of an "ideal" operational amplifier and discusses how it might be used under saturated and non-saturated conditions. Notes the action of a "real" operational amplifier. (TW)

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor.

PubMed

Lee, Jieun; Jang, Jaeman; Choi, Bongsik; Yoon, Jinsu; Kim, Jee-Yeon; Choi, Yang-Kyu; Kim, Dong Myong; Kim, Dae Hwan; Choi, Sung-Jin

2015-07-21

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 10(5) times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 10(5) with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density.

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

PubMed Central

Lee, Jieun; Jang, Jaeman; Choi, Bongsik; Yoon, Jinsu; Kim, Jee-Yeon; Choi, Yang-Kyu; Myong Kim, Dong; Hwan Kim, Dae; Choi, Sung-Jin

2015-01-01

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 105 times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 105 with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density. PMID:26197105

Design of high-linear CMOS circuit using a constant transconductance method for gamma-ray spectroscopy system

NASA Astrophysics Data System (ADS)

Jung, I. I.; Lee, J. H.; Lee, C. S.; Choi, Y.-W.

2011-02-01

We propose a novel circuit to be applied to the front-end integrated circuits of gamma-ray spectroscopy systems. Our circuit is designed as a type of current conveyor (ICON) employing a constant- gm (transconductance) method which can significantly improve the linearity in the amplified signals by using a large time constant and the time-invariant characteristics of an amplifier. The constant- gm method is obtained by a feedback control which keeps the transconductance of the input transistor constant. To verify the performance of the propose circuit, the time constant variations for the channel resistances are simulated with the TSMC 0.18 μm transistor parameters using HSPICE, and then compared with those of a conventional ICON. As a result, the proposed ICON shows only 0.02% output linearity variation and 0.19% time constant variation for the input amplitude up to 100 mV. These are significantly small values compared to a conventional ICON's 1.39% and 19.43%, respectively, for the same conditions.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Coherent white light amplification

DOEpatents

Jovanovic, Igor; Barty, Christopher P.

2004-05-25

A system for coherent simultaneous amplification of a broad spectral range of light that includes an optical parametric amplifier and a source of a seed pulse is described. A first angular dispersive element is operatively connected to the source of a seed pulse. A first imaging telescope is operatively connected to the first angular dispersive element and operatively connected to the optical parametric amplifier. A source of a pump pulse is operatively connected to the optical parametric amplifier. A second imaging telescope is operatively connected to the optical parametric amplifier and a second angular dispersive element is operatively connected to the second imaging telescope.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

PubMed

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Gurbuz, Yasar

2013-06-01

Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring

PubMed Central

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-01-01

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO2 detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO2 sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO2/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations. PMID:28353680

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring.

PubMed

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-03-29

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO₂ detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO₂ sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO₂/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations.

Gain drift compensation with no feedback-loop developed for the X-Ray Integral Field Unit/ATHENA readout chain

NASA Astrophysics Data System (ADS)

Prêle, Damien; Voisin, Fabrice; Beillimaz, Cyril; Chen, Si; Goldwurm, Andrea

2016-10-01

The focal plane of the X-Ray Integral Field Unit (X-IFU) instrument of the Advanced Telescope for High-Energy Astrophysics observatory is composed of 3840 microcalorimeters. These sensors, based on superconducting transition edge sensors (TES), are read out through a frequency multiplexer. A "base-band feedback" suppresses all the carriers of the multiplexed signal in the superconducting quantum interference devices input coil (cryogenic readout). However, the loop gain of this feedback is too small (less than 10 in the present baseline of the phase A mission) to strongly compensate the readout gain drifts. An onboard x-ray source is considered to calibrate the gain of the full instrument. However, in-flight calibration time must be minimized, which leads to a requirement on the gain stability larger than 10-4 over a long duration (between each calibration) to reach the challenging energy resolution goal of 2.5 eV at 6 keV of the X-IFU. A significant part of this gain is provided by a low-noise amplifier in the warm front-end electronics (WFEE). To reach such gain stability over more than a dozen minutes, this noncooled amplifier has to cope with the temperature and supply voltage variations. Moreover, mainly for noise reasons, a common large loop gain with feedback cannot be used. We propose a new amplifier topology using diodes as loads of a differential amplifier to provide a fixed voltage gain, independent of the temperature and of the bias fluctuations. This amplifier is designed using 350-nm SiGe BiCMOS technology and is part of an integrated circuit developed for the WFEE. Our simulations provide the expected gain and noise performances. Comparison with standard resistive loaded differential pair clearly shows the advantages of the proposed amplifier topology with a gain drift decreased by more than an order of magnitude. Performances of this diode loaded amplifier are discussed in the context of the X-IFU requirements.

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

NASA Astrophysics Data System (ADS)

Wu, Chang-Hsi; You, Hong-Cheng; Huang, Shun-Zhao

2018-02-01

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of -9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

Isolated thermocouple amplifier system for stirred fixed-bed gasifier

DOEpatents

Fasching, George E.

1992-01-01

A sensing system is provided for determining the bed temperature profile of the bed of a stirred, fixed-bed gasifier including a plurality of temperature sensors for sensing the bed temperature at different levels, a transmitter for transmitting data based on the outputs of the sensors to a remote operator's station, and a battery-based power supply. The system includes an isolation amplifier system comprising a plurality of isolation amplifier circuits for amplifying the outputs of the individual sensors. The isolation amplifier circuits each comprise an isolation operational amplifier connected to a sensor; a first "flying capacitor" circuit for, in operation, controlling the application of power from the power supply to the isolation amplifier; an output sample and hold circuit connected to the transmitter; a second "flying capacitor" circuit for, in operation, controlling the transfer of the output of the isolation amplifier to the sample and hold circuit; and a timing and control circuit for activating the first and second capacitor circuits in a predetermined timed sequence.

Active pixel image sensor with a winner-take-all mode of operation

NASA Technical Reports Server (NTRS)

Yadid-Pecht, Orly (Inventor); Mead, Carver (Inventor); Fossum, Eric R. (Inventor)

2003-01-01

An integrated CMOS semiconductor imaging device having two modes of operation that can be performed simultaneously to produce an output image and provide information of a brightest or darkest pixel in the image.

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Laser line scan underwater imaging by complementary metal-oxide-semiconductor camera

NASA Astrophysics Data System (ADS)

He, Zhiyi; Luo, Meixing; Song, Xiyu; Wang, Dundong; He, Ning

2017-12-01

This work employs the complementary metal-oxide-semiconductor (CMOS) camera to acquire images in a scanning manner for laser line scan (LLS) underwater imaging to alleviate backscatter impact of seawater. Two operating features of the CMOS camera, namely the region of interest (ROI) and rolling shutter, can be utilized to perform image scan without the difficulty of translating the receiver above the target as the traditional LLS imaging systems have. By the dynamically reconfigurable ROI of an industrial CMOS camera, we evenly divided the image into five subareas along the pixel rows and then scanned them by changing the ROI region automatically under the synchronous illumination by the fun beams of the lasers. Another scanning method was explored by the rolling shutter operation of the CMOS camera. The fun beam lasers were turned on/off to illuminate the narrow zones on the target in a good correspondence to the exposure lines during the rolling procedure of the camera's electronic shutter. The frame synchronization between the image scan and the laser beam sweep may be achieved by either the strobe lighting output pulse or the external triggering pulse of the industrial camera. Comparison between the scanning and nonscanning images shows that contrast of the underwater image can be improved by our LLS imaging techniques, with higher stability and feasibility than the mechanically controlled scanning method.

High-speed detection of DNA translocation in nanopipettes.

PubMed

Fraccari, Raquel L; Ciccarella, Pietro; Bahrami, Azadeh; Carminati, Marco; Ferrari, Giorgio; Albrecht, Tim

2016-04-14

We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface.

Log amplifier with pole-zero compensation

DOEpatents

Brookshier, W.

1985-02-08

A logarithmic amplifier circuit provides pole-zero compensation for improved stability and response time over 6-8 decades of input signal frequency. The amplifer circuit includes a first operational amplifier with a first feedback loop which includes a second, inverting operational amplifier in a second feedstock loop. The compensated output signal is provided by the second operational amplifier with the log elements, i.e., resistors, and the compensating capacitors in each of the feedback loops having equal values so that each break point is offset by a compensating break point or zero.

Hybrid matrix amplifier

DOEpatents

Martens, J.S.; Hietala, V.M.; Plut, T.A.

1995-01-03

The present invention comprises a novel matrix amplifier. The matrix amplifier includes an active superconducting power divider (ASPD) having N output ports; N distributed amplifiers each operatively connected to one of the N output ports of the ASPD; and a power combiner having N input ports each operatively connected to one of the N distributed amplifiers. The distributed amplifier can included M stages of amplification by cascading superconducting active devices. The power combiner can include N active elements. The resulting (N[times]M) matrix amplifier can produce signals of high output power, large bandwidth, and low noise. 6 figures.

Hybrid matrix amplifier

DOEpatents

Martens, Jon S.; Hietala, Vincent M.; Plut, Thomas A.

1995-01-01

The present invention comprises a novel matrix amplifier. The matrix amplifier includes an active superconducting power divider (ASPD) having N output ports; N distributed amplifiers each operatively connected to one of the N output ports of the ASPD; and a power combiner having N input ports each operatively connected to one of the N distributed amplifiers. The distributed amplifier can included M stages of amplification by cascading superconducting active devices. The power combiner can include N active elements. The resulting (N.times.M) matrix amplifier can produce signals of high output power, large bandwidth, and low noise.

Amplifiers in the radio-electronic equipment of aircraft

NASA Astrophysics Data System (ADS)

Khol'Nyi, Vladimir Ia.

The applications, classification, and technical specifications of airborne electronic amplifiers are discussed. Particular attention is given to the general design and principles of operation of single amplification cascades and multicascade amplifiers, including dc, audio, and video amplifiers used as part of the radio-electronic equipment of modern aircraft. The discussion also covers the principal technical and performance characteristics of various amplifiers, their operating conditions, service, and repair.

640 X 480 PtSi MOS infrared imager

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1992-09-01

The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 10(superscript 6) electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

A CMOS merged CDR and continuous-time adaptive equalizer

NASA Astrophysics Data System (ADS)

Sánchez-Azqueta, C.; Aguirre, J.; Gimeno, C.; Aldea, C.; Celma, S.

2015-06-01

We present a low-voltage merged CDR and cntinuous-time adaptive equalizer capable to compensate the attenu- ation of a SI-POF channel while at the same time synchronizing and regenerating the incoming signal in a single stage. The system operates at 1.25 Gbps for NRZ modulation through a 50-m SI-POF channel and it is designed in standard 0.18-μm CMOS fed at 1 V with a power consumption of 43.4 mW.

Performance Analysis of Visible Light Communication Using CMOS Sensors.

PubMed

Do, Trong-Hop; Yoo, Myungsik

2016-02-29

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

Performance Analysis of Visible Light Communication Using CMOS Sensors

PubMed Central

Do, Trong-Hop; Yoo, Myungsik

2016-01-01

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix

DTIC Science & Technology

1990-04-29

this worksheet and are arranged in page number order. I Comnt Page SS No. No. No . Comment 1. C-10 SS0804 Delete this shall statement. 2. C-29 SS0810...correspond with each other. I CMOS PMO ACCEPTS COM1*ENT: YES [ ] NO [ ] i ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: I COMMENT STATUS: OPEN...ACCEPTS COMMENT: YES [ ] NO [ ] I ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: II COMMENT STATUS: OPEN [(] CLOSED [1] I U I I I I I I I

Ultrananocrystalline diamond films with optimized dielectric properties for advanced RF MEMS capacitive switches

DOEpatents

Sumant, Anirudha V.; Auciello, Orlando H.; Mancini, Derrick C.

2013-01-15

An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

NASA Astrophysics Data System (ADS)

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

A low jitter PLL clock used for phase change memory

NASA Astrophysics Data System (ADS)

Xiao, Hong; Houpeng, Chen; Zhitang, Song; Daolin, Cai; Xi, Li

2013-02-01

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

PubMed

Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

2016-12-21

One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

The Speedster-EXD- A New Event-Driven Hybrid CMOS X-ray Detector

NASA Astrophysics Data System (ADS)

Griffith, Christopher V.; Falcone, Abraham D.; Prieskorn, Zachary R.; Burrows, David N.

2016-01-01

The Speedster-EXD is a new 64×64 pixel, 40-μm pixel pitch, 100-μm depletion depth hybrid CMOS x-ray detector with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain capacitive transimpedance amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel correlated double sampling subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5%) at 5.89 keV and 172 eV (10.0%) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25%±0.2% (i.e., consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80%±0.03%, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

Novel pH sensing semiconductor for point-of-care detection of HIV-1 viremia

PubMed Central

Gurrala, R.; Lang, Z.; Shepherd, L.; Davidson, D.; Harrison, E.; McClure, M.; Kaye, S.; Toumazou, C.; Cooke, G. S.

2016-01-01

The timely detection of viremia in HIV-infected patients receiving antiviral treatment is key to ensuring effective therapy and preventing the emergence of drug resistance. In high HIV burden settings, the cost and complexity of diagnostics limit their availability. We have developed a novel complementary metal-oxide semiconductor (CMOS) chip based, pH-mediated, point-of-care HIV-1 viral load monitoring assay that simultaneously amplifies and detects HIV-1 RNA. A novel low-buffer HIV-1 pH-LAMP (loop-mediated isothermal amplification) assay was optimised and incorporated into a pH sensitive CMOS chip. Screening of 991 clinical samples (164 on the chip) yielded a sensitivity of 95% (in vitro) and 88.8% (on-chip) at >1000 RNA copies/reaction across a broad spectrum of HIV-1 viral clades. Median time to detection was 20.8 minutes in samples with >1000 copies RNA. The sensitivity, specificity and reproducibility are close to that required to produce a point-of-care device which would be of benefit in resource poor regions, and could be performed on an USB stick or similar low power device. PMID:27829667

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

NASA Astrophysics Data System (ADS)

Lu, Y.; Tang, H.; Fung, S.; Wang, Q.; Tsai, J. M.; Daneman, M.; Boser, B. E.; Horsley, D. A.

2015-06-01

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ˜14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

PubMed

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

Development of the hard x-ray monitor onboard WF-MAXI

NASA Astrophysics Data System (ADS)

Arimoto, Makoto; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Harayama, Atsushi; Takeda, Shin'ichiro; Takahashi, Tadayuki; Tomida, Hiroshi; Ueno, Shiro; Kimura, Masashi; Mihara, Tatehiro; Serino, Motoko; Tsunemi, Hiroshi; Yoshida, Atsumasa; Sakamoto, Takanori; Kohmura, Tadayoshi; Negoro, Hitoshi; Ueda, Yoshihiro

2014-07-01

WF-MAXI is a mission to detect and localize X-ray transients with short-term variability as gravitational-wave (GW) candidates including gamma-ray bursts, supernovae etc. We are planning on starting observations by WF-MAXI to be ready for the initial operation of the next generation GW telescopes (e.g., KAGRA, Advanced LIGO etc.). WF-MAXI consists of two main instruments, Soft X-ray Large Solid Angle Camera (SLC) and Hard X-ray Monitor (HXM) which totally cover 0.7 keV to 1 MeV band. HXM is a multi-channel array of crystal scintillators coupled with APDs observing photons in the hard X-ray band with an effective area of above 100 cm2. We have developed an analog application specific integrated circuit (ASIC) dedicated for the readout of 32-channel APDs' signals using 0.35 μm CMOS technology based on Open IP project and an analog amplifier was designed to achieve a low-noise readout. The developed ASIC showed a low-noise performance of 2080 e- + 2.3 e-/pF at root mean square and with a reverse-type APD coupled to a Ce:GAGG crystal a good FWHM energy resolution of 6.9% for 662 keV -rays.

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging.

PubMed

Attarzadeh, Hourieh; Xu, Ye; Ytterdal, Trond

2017-10-01

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

Low-noise readout circuit for SWIR focal plane arrays

NASA Astrophysics Data System (ADS)

Altun, Oguz; Tasdemir, Ferhat; Nuzumlali, Omer Lutfi; Kepenek, Reha; Inceturkmen, Ercihan; Akyurek, Fatih; Tunca, Can; Akbulut, Mehmet

2017-02-01

This paper reports a 640x512 SWIR ROIC with 15um pixel pitch that is designed and fabricated using 0.18um CMOS process. Main challenge of SWIR ROIC design is related to input circuit due to pixel area and noise limitations. In this design, CTIA with single stage amplifier is utilized as input stage. The pixel design has three pixel gain options; High Gain (HG), Medium Gain (MG), and Low Gain (LG) with corresponding Full-Well-Capacities of 18.7ké, 190ké and 1.56Mé, respectively. According to extracted simulation results, 5.9é noise is achieved at HG mode and 200é is achieved at LG mode of operation. The ROIC can be programmed through an SPI interface. It supports 1, 2 and 4 output modes which enables the user to configure the detector to work at 30, 60 and 120fps frame rates. In the 4 output mode, the total power consumption of the ROIC is less than 120mW. The ROIC is powered from a 3.3V analog supply and allows for an output swing range in excess of 2V. Anti-blooming feature is added to prevent any unwanted blooming effect during readout.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

NASA Astrophysics Data System (ADS)

Guo, Jiarong

2017-04-01

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 °C. Project supported by the National Natural Science Fundation of China (No. 61376028).

Chaotic behaviors of operational amplifiers.

PubMed

Yim, Geo-Su; Ryu, Jung-Wan; Park, Young-Jai; Rim, Sunghwan; Lee, Soo-Young; Kye, Won-Ho; Kim, Chil-Min

2004-04-01

We investigate nonlinear dynamical behaviors of operational amplifiers. When the output terminal of an operational amplifier is connected to the inverting input terminal, the circuit exhibits period-doubling bifurcation, chaos, and periodic windows, depending on the voltages of the positive and the negative power supplies. We study these nonlinear dynamical characteristics of this electronic circuit experimentally.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective

NASA Astrophysics Data System (ADS)

Das, Kushal; Lehmann, Torsten

2014-07-01

The effect of ultra low operating temperature on mismatch among identically designed Silicon-on-Sapphire CMOS devices is investigated in detail from a circuit design view point. The evolution of transistor matching properties for different operating conditions at both room and 4.2 K temperature are presented. The statistical analysis reveals that mismatch at low temperature is effectively unrelated to that at room temperature, which disagrees with previously published literature. The measurement data was used to extract key transistor parameters and the consequence of temperature lowering on their respective variance is estimated. We find that standard deviation of the threshold-voltage mismatch deteriorates by a factor ∼2 at 4.2 K temperature. Similar to room temperature operation, mismatch at 4.2 K is bias point dependent and the degradation of matching at very low temperature depends to some extent on how the bias point shifts upon cooling.

Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

DOEpatents

Welch, James D.

2003-09-23

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

CMOS plasmonics in WDM data transmission: 200 Gb/s (8 × 25Gb/s) transmission over aluminum plasmonic waveguides.

PubMed

Dabos, G; Manolis, A; Papaioannou, S; Tsiokos, D; Markey, L; Weeber, J-C; Dereux, A; Giesecke, A L; Porschatis, C; Chmielak, B; Pleros, N

2018-05-14

We demonstrate wavelength-division-multiplexed (WDM) 200 Gb/s (8 × 25 Gb/s) data transmission over 100 μm long aluminum (Al) surface-plasmon-polariton (SPP) waveguides on a Si 3 N 4 waveguide platform at telecom wavelengths. The Al SPP waveguide was evaluated in terms of signal integrity by performing bit-error-rate (BER) measurements that revealed error-free operation for all eight 25 Gb/s non-return-to-zero (NRZ) modulated data channels with power penalties not exceeding 0.2 dB at 10 -9 . To the best of our knowledge, this is the first demonstration of WDM enabled data transmission over complementary-metal-oxide-semiconductor (CMOS) SPP waveguides fueling future development of CMOS compatible plasmo-photonic devices for on-chip optical interconnections.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Matched wideband low-noise amplifiers for radio astronomy.

PubMed

Weinreb, S; Bardin, J; Mani, H; Jones, G

2009-04-01

Two packaged low noise amplifiers for the 0.3-4 GHz frequency range are described. The amplifiers can be operated at temperatures of 300-4 K and achieve noise temperatures in the 5 K range (<0.1 dB noise figure) at 15 K physical temperature. One amplifier utilizes commercially available, plastic-packaged SiGe transistors for first and second stages; the second amplifier is identical except it utilizes an experimental chip transistor as the first stage. Both amplifiers use resistive feedback to provide input reflection coefficient S11<-10 dB over a decade bandwidth with gain over 30 dB. The amplifiers can be used as rf amplifiers in very low noise radio astronomy systems or as i.f. amplifiers following superconducting mixers operating in the millimeter and submillimeter frequency range.

Hyperspectral CMOS imager

NASA Astrophysics Data System (ADS)

Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

2017-11-01

CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

RF upset susceptibilities of CMOS and low power Schottky D-type flip-flops

NASA Astrophysics Data System (ADS)

Kenneally, Daniel J.; Koellen, Daniel S.; Epshtein, Stan

A description is given of measurements of RF upset levels on two D-type flip-flops, the CD4013B and 54ALS74A, which are functionally identical but fabricated from different technologies: CMOS and low-power Schottky. Continuous-wave electromagnetic interference (CW EMI) from 1 MHz to 200 MHz was coupled into the clock, data, and collector bias, Vcc, ports of each device type while test vectors were used to verify normal operation and subsequent upsets. Both the CMOS and the Schottky devices show decreasing RF susceptibility with increasing frequencies from 1 to 200 MHz. The CMOS device roll-off is almost 18 dB/decade as compared to about 12 dB/decade for the Schottky device. The differences in the Vcc ports' susceptibilities are also apparent. The CMOS device's upset levels decrease steeply with increasing frequency at approximate roll-offs of 60 dB/decade up to 5 MHz and 15 dB/decade from 5 to 100 MHz. Over the same bands, the Schottky device susceptibility at the Vcc port remains strikingly constant at a 6-dBm upset level. Measurements on the clock and data ports seem to suggest that: (1) the CMOS device is `RF harder' than the Schottky device by 3 to 18 dB at least above the 5 to 10 MHz range and out to 100 MHz; and (2) below that range, the Schottky device may be `RF harder' by 3 to 6 dB, but there are not enough measurement data to confirm this performance below 5 MHz.

Photonic-band-gap gyrotron amplifier with picosecond pulses.

PubMed

Nanni, Emilio A; Jawla, Sudheer; Lewis, Samantha M; Shapiro, Michael A; Temkin, Richard J

2017-12-04

We report the amplification of 250 GHz pulses as short as 260 ps without observation of pulse broadening using a photonic-band-gap circuit gyrotron traveling-wave-amplifier. The gyrotron amplifier operates with a device gain of 38 dB and an instantaneous bandwidth of 8 GHz. The operational bandwidth of the amplifier can be tuned over 16 GHz by adjusting the operating voltage of the electron beam and the magnetic field. The amplifier uses a 30 cm long photonic-band-gap interaction circuit to confine the desired TE 03 -like operating mode while suppressing lower order modes which can result in undesired oscillations. The circuit gain is >55 dB for a beam voltage of 23 kV and a current of 700 mA. These results demonstrate the wide bandwidths and a high gain achievable with gyrotron amplifiers. The amplification of picosecond pulses of variable lengths, 260-800 ps, shows good agreement with the theory using the coupled dispersion relation and the gain-spectrum of the amplifier as measured with quasi-CW input pulses.

High-efficiency S-band harmonic tuning GaN amplifier

NASA Astrophysics Data System (ADS)

Cao, Meng-Yi; Zhang, Kai; Chen, Yong-He; Zhang, Jin-Cheng; Ma, Xiao-Hua; Hao, Yue

2014-03-01

In this paper, we present a high-efficiency S-band gallium nitride (GaN) power amplifier (PA). This amplifier is fabricated based on a self-developed GaN high-electron-mobility transistor (HEMT) with 10 mm gate width on SiC substrate. Harmonic manipulation circuits are presented in the amplifier. The matching networks consist of microstrip lines and discrete components. Open-circuited stub lines in both input and output are used to tune the 2nd harmonic wave and match the GaN HEMT to the highest efficiency condition. The developed amplifier delivers an output power of 48.5 dBm (~70 W) with a power-added efficiency (PAE) of 72.2% at 2 GHz in pulse condition. When operating at 1.8-2.2 GHz (20% relative bandwidth), the amplifier provides an output power higher than 48 dBm (~ 65 W), with a PAE over 70% and a power gain above 15 dB. When operating in continuous-wave (CW) operating conditions, the amplifier gives an output power over 46 dBm (40 W) with PAE beyond 60% over the whole operation frequency range.

Photonic-band-gap gyrotron amplifier with picosecond pulses

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nanni, Emilio A.; Jawla, Sudheer; Lewis, Samantha M.

Here, we report the amplification of 250 GHz pulses as short as 260 ps without observation of pulse broadening using a photonic-band-gap circuit gyrotron traveling-wave-amplifier. The gyrotron amplifier operates with a device gain of 38 dB and an instantaneous bandwidth of 8 GHz. The operational bandwidth of the amplifier can be tuned over 16 GHz by adjusting the operating voltage of the electron beam and the magnetic field. The amplifier uses a 30 cm long photonic-band-gap interaction circuit to confine the desired TE 03-like operating mode while suppressing lower order modes which can result in undesired oscillations. The circuit gainmore » is >55 dB for a beam voltage of 23 kV and a current of 700 mA. These results demonstrate the wide bandwidths and a high gain achievable with gyrotron amplifiers. The amplification of picosecond pulses of variable lengths, 260–800 ps, shows good agreement with the theory using the coupled dispersion relation and the gain-spectrum of the amplifier as measured with quasi-CW input pulses.« less

Photonic-band-gap gyrotron amplifier with picosecond pulses

DOE PAGES

Nanni, Emilio A.; Jawla, Sudheer; Lewis, Samantha M.; ...

2017-12-05

Here, we report the amplification of 250 GHz pulses as short as 260 ps without observation of pulse broadening using a photonic-band-gap circuit gyrotron traveling-wave-amplifier. The gyrotron amplifier operates with a device gain of 38 dB and an instantaneous bandwidth of 8 GHz. The operational bandwidth of the amplifier can be tuned over 16 GHz by adjusting the operating voltage of the electron beam and the magnetic field. The amplifier uses a 30 cm long photonic-band-gap interaction circuit to confine the desired TE 03-like operating mode while suppressing lower order modes which can result in undesired oscillations. The circuit gainmore » is >55 dB for a beam voltage of 23 kV and a current of 700 mA. These results demonstrate the wide bandwidths and a high gain achievable with gyrotron amplifiers. The amplification of picosecond pulses of variable lengths, 260–800 ps, shows good agreement with the theory using the coupled dispersion relation and the gain-spectrum of the amplifier as measured with quasi-CW input pulses.« less

Selective photon counter for digital x-ray mammography tomosynthesis

NASA Astrophysics Data System (ADS)

Goldan, Amir H.; Karim, Karim S.; Rowlands, J. A.

2006-03-01

Photon counting is an emerging detection technique that is promising for mammography tomosynthesis imagers. In photon counting systems, the value of each image pixel is equal to the number of photons that interact with the detector. In this research, we introduce the design and implementation of a low noise, novel selective photon counting pixel for digital mammography tomosynthesis in crystalline silicon CMOS (complementary metal oxide semiconductor) 0.18 micron technology. The design comprises of a low noise charge amplifier (CA), two low offset voltage comparators, a decision-making unit (DMU), a mode selector, and a pseudo-random counter. Theoretical calculations and simulation results of linearity, gain, and noise of the photon counting pixel are presented.

A power-efficient analog integrated circuit for amplification and detection of neural signals.

PubMed

Borghi, T; Bonfanti, A; Gusmeroli, R; Zambra, G; Spinelli, A S

2008-01-01

We present a neural amplifier that optimizes the trade-off between power consumption and noise performance down to the best so far reported. In the perspective of realizing a fully autonomous implantable system we also address the problem of spike detection by using a new simple algorithm and we discuss the implementation with analog integrated circuits. Implemented in 0.35-microm CMOS technology and with total current consumption of about 20 microA, the whole circuit occupies an area of 0.18 mm(2). Reduced power consumption and small area make it suited to be used in chronic multichannel recording systems for neural prosthetics and neuroscience experiments.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers

PubMed Central

Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

2016-01-01

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/Hz at 50 kHz, which corresponds to 100 μg/Hz. PMID:28042830

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

PubMed

Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

2016-12-30

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ Hz at 50 kHz, which corresponds to 100 μg/ Hz .

Waveguide Power-Amplifier Module for 80 to 150 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Weinreb, Sander; Peralta, Alejandro

2006-01-01

A waveguide power-amplifier module capable of operating over the frequency range from 80 to 150 GHz has been constructed. The module comprises a previously reported power amplifier packaged in a waveguide housing that is compatible with WR-8 waveguides. (WR- 8 is a standard waveguide size for the nominal frequency range from 90 to 140 GHz.) The waveguide power-amplifier module is robust and can be bolted to test equipment and to other electronic circuits with which the amplifier must be connected for normal operation.

A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

NASA Technical Reports Server (NTRS)

Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

2013-01-01

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.