A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

PubMed

Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

2012-08-01

An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

A CMOS matrix for extracting MOSFET parameters before and after irradiation

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Buehler, M. G.; Lin, Y.-S.; Hicks, K. A.

1988-01-01

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

A m-ary linear feedback shift register with binary logic

NASA Technical Reports Server (NTRS)

Perlman, M. (Inventor)

1973-01-01

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers.

Selective data segment monitoring system. [using shift registers

NASA Technical Reports Server (NTRS)

Wirth, M. N. (Inventor)

1976-01-01

High speed data monitoring apparatus is described for displaying the bit pattern of a selected portion of a block of transmitted data comprising a shift register for receiving the transmitted data and for temporarily containing the consecutive data bits. A programmable sync detector for monitoring the contents of the shift register and for generating a sync signal when the shift register contains a predetermined sync code is included. A counter is described for counting the data bits input to the shift register after the sync signal is generated and for generating a count complete signal when a selected number of data bits have been input to the register. A data storage device is used for storing the contents of the shift register at the time the count complete signal is generated.

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

A 20 MHz CMOS reorder buffer for a superscalar microprocessor

NASA Technical Reports Server (NTRS)

Lenell, John; Wallace, Steve; Bagherzadeh, Nader

1992-01-01

Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

A high speed CCSDS encoder for space applications

NASA Technical Reports Server (NTRS)

Whitaker, S.; Liu, K.

1990-01-01

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Sensitivity-Enhanced CMOS Phase Luminometry System Using Xerogel-Based Sensors.

PubMed

Lei Yao; Khan, R; Chodavarapu, V P; Tripathi, V S; Bright, F V

2009-10-01

We present the design and implementation of a phase luminometry sensor system with improved and tunable detection sensitivity achieved using a complementary metal-oxide semiconductor (CMOS) integrated circuit. We use sol-gel derived xerogel thin films as an immobilization media to house oxygen (O2) responsive luminescent molecules. The sensor operates on the principal of phase luminometry wherein a sinusoidal modulation signal is used to excite the luminophores encapsulated in the porous xerogel films and the corresponding phase shift of the emission signals is monitored. The phase shift is directly related to excited state lifetimes of the luminophores which in turn are related to the concentration of the target analyte species present in the vicinity of the luminophores. The CMOS IC, which consists of a 16 times 16 high-gain phototransistor array, current-to-voltage converter, amplifier and tunable phase shift detector, consumes an average power of 14 mW with 5-V power supply operating at a 38-kHz modulation frequency. The output of the IC is a dc voltage that corresponds to the detected luminescence phase shift with respect to the excitation signal. As a prototype, we demonstrate an oxygen sensor system by encapsulating the luminophore tris(4,7-diphenyl-1,10-phenanthroline)ruthenium(II) within the xerogel matrices. The sensor system showed a fast response on the order of few seconds and we obtained a detection sensitivity of 118 mV per 1% change in O2 concentration. The system demonstrates a novel concept to tune and improve the detection sensitivity for specific concentrations of the target analyte in many biomedical monitoring applications.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Two-step single slope/SAR ADC with error correction for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Amira, Abbes; Amor Benammar, Mohieddine; He, Debiao; Zhao, Xiaojin

2014-01-01

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μ m CMOS technology. The chip area of the proposed ADC is 7 μ m × 500 μ m. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k  μ m(2) · cycles/sample.

A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

PubMed

Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

2016-09-23

In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

A study of charged particles/radiation damage to VLSI device materials

NASA Technical Reports Server (NTRS)

Okyere, John G.

1987-01-01

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

CMOS micromachined capacitive cantilevers for mass sensing

NASA Astrophysics Data System (ADS)

Li, Ying-Chung; Ho, Meng-Han; Hung, Shi-Jie; Chen, Meng-Huei; S-C Lu, Michael

2006-12-01

In this paper, we present the design, fabrication and characterization of the CMOS micromachined cantilevers for mass sensing in the femtogram range. The cantilevers consisting of multiple metal and dielectric layers are fabricated after completion of a conventional CMOS process by dry etching steps. The cantilevers are electrostatically actuated to resonance by in-plane electrodes. The mechanical resonant frequency is detected capacitively with on-chip circuitry, where the modulation technique is applied to eliminate capacitive feedthrough from the driving port and to lessen the effect of flicker noise. The highest resonant frequency of the cantilevers is measured at 396.46 kHz with a quality factor of 2600 at 10 mTorr. The resonant frequency shift after deposition of a 0.1 µm SiO2 layer is 140 Hz, averaging 353 fg Hz-1.

Vocal-fold collision mass as a differentiator between registers in the low-pitch range.

PubMed

Vilkman, E; Alku, P; Laukkanen, A M

1995-03-01

Register shift between the chest and falsetto register is generally studied in the higher-than-speaking pitch range. However, a similar difference can also be produced at speaking pitch level. The shift from breathy "falsetto" phonation to normal chest voice phonation was studied in normal female (pitch range 170-180 Hz) and male (pitch range 94-110 Hz) subjects. The phonations gliding from falsetto to normal chest voice were analyzed using iterative adaptive inverse filtering and electroglottography. Both trained and untrained, as well as female and male subjects, were able to produce an abrupt register shift from soft falsetto to soft chest register phonation. The differences between male and female speakers in the glottal flow waveforms were smaller than expected. The register shift is interpreted in terms of a "critical mass" concept of chest register phonation.

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

NASA Astrophysics Data System (ADS)

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, John D.; Patel, Jagdish; Liu, S. T.; Reed, Robert A.; Mojarradi, Mohammad M.; Blalock, Benjamin J.

2003-06-01

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Molecular Electronic Shift Registers

NASA Technical Reports Server (NTRS)

Beratan, David N.; Onuchic, Jose N.

1990-01-01

Molecular-scale shift registers eventually constructed as parts of high-density integrated memory circuits. In principle, variety of organic molecules makes possible large number of different configurations and modes of operation for such shift-register devices. Several classes of devices and implementations in some specific types of molecules proposed. All based on transfer of electrons or holes along chains of repeating molecular units.

Staff perceptions of leadership during implementation of task-shifting in three surgical units.

PubMed

Henderson, Amanda; Paterson, Karyn; Burmeister, Liz; Thomson, Bernadette; Young, Louise

2013-03-01

Registered nurses are difficult to recruit and retain. Task shifting, which involves reallocation of delegation, can reduce demand for registered nurses. Effective leadership is needed for successful task shifting. This study explored leadership styles of three surgical nurse unit managers. Staff completed surveys before and after the implementation of task shifting. Task shifting involved the introduction of endorsed enrolled nurses (licensed nurses who must practise under registered nurse supervision) to better utilize registered nurses. Implementation of task shifting occurred over 4 months in a 700-bed tertiary hospital, in southeast Queensland, Australia. A facilitator assisted nurse unit managers during implementation. The impact was assessed by comparison of data before (n = 49) and after (n = 72) task shifting from registered nurses and endorsed enrolled nurses (n = 121) who completed the Ward Organization Features Survey. Significant differences in leadership and staff organization subscales across the settings suggest that how change involving task shifting is implemented influences nurses' opinions of leadership. Leadership behaviours of nurse unit managers is a key consideration in managing change such as task shifting. Consistent and clear messages from leaders about practice change are viewed positively by nursing staff. In the short term, incremental change possibly results in staff maintaining confidence in leadership. © 2012 Blackwell Publishing Ltd.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

NASA Astrophysics Data System (ADS)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

A goggle navigation system for cancer resection surgery

NASA Astrophysics Data System (ADS)

Xu, Junbin; Shao, Pengfei; Yue, Ting; Zhang, Shiwu; Ding, Houzhu; Wang, Jinkun; Xu, Ronald

2014-02-01

We describe a portable fluorescence goggle navigation system for cancer margin assessment during oncologic surgeries. The system consists of a computer, a head mount display (HMD) device, a near infrared (NIR) CCD camera, a miniature CMOS camera, and a 780 nm laser diode excitation light source. The fluorescence and the background images of the surgical scene are acquired by the CCD camera and the CMOS camera respectively, co-registered, and displayed on the HMD device in real-time. The spatial resolution and the co-registration deviation of the goggle navigation system are evaluated quantitatively. The technical feasibility of the proposed goggle system is tested in an ex vivo tumor model. Our experiments demonstrate the feasibility of using a goggle navigation system for intraoperative margin detection and surgical guidance.

Information storage at the molecular level - The design of a molecular shift register memory

NASA Technical Reports Server (NTRS)

Beratan, David N.; Onuchic, Jose Nelson; Hopfield, J. J.

1989-01-01

The control of electron transfer rates is discussed and a molecular shift register memory at the molecular level is described. The memory elements are made up of molecules which can exist in either an oxidized or reduced state and the bits can be shifted between the cells with photoinduced electron transfer reactions. The device integrates designed molecules onto a VLSI substrate. A control structure to modify the flow of information along a shift register is indicated schematically.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Beyond CMOS computing with spin and polarization

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2018-04-01

Spintronic and multiferroic systems are leading candidates for achieving attojoule-class logic gates for computing, thereby enabling the continuation of Moore's law for transistor scaling. However, shifting the materials focus of computing towards oxides and topological materials requires a holistic approach addressing energy, stochasticity and complexity.

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be recovered using several methods; for example, using tunable transmission line lengths in the amplifier or using a variable supply voltage. This concept of estimating process variation has been demonstrated in Agilent Design System (ADS).

Design of a Molecular Memory Device: The Electron Transfer Shift Register Memory

NASA Technical Reports Server (NTRS)

Beratan, D.

1993-01-01

A molecular shift register memory at the molecular level is described. The memory elements consist of molecules can exit in either an oxidized or reduced state and the bits are shifted between the cells with photoinduced electron transfer reactions.

Periodic binary sequence generators: VLSI circuits considerations

NASA Technical Reports Server (NTRS)

Perlman, M.

1984-01-01

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

Counting digital filters

NASA Technical Reports Server (NTRS)

Zohar, S. (Inventor)

1973-01-01

Several embodiments of a counting digital filter of the non-recursive type are disclosed. In each embodiment two registers, at least one of which is a shift register, are included. The shift register received j sub x-bit data input words bit by bit. The kth data word is represented by the integer.

Design trade-off between spatial resolution and power consumption in CMOS biosensor circuit based on millimeter-wave LC oscillator array

NASA Astrophysics Data System (ADS)

Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

In this paper, we describe a trade-off between spatial resolution and power consumption in an LC oscillator-based CMOS biosensor, which can detect biomolecules by observing the resonance frequency shift due to changes in the complex permittivity of the biomolecules. The optimal operating frequency and improvement in the image resolution of the sensor output require a reduction in the size of the inductor. However, it is necessary to increase the transconductance of the cross-coupling transistor to achieve the oscillation condition, although the power consumption increases. We confirmed the trade-off between the spatial resolution and the power consumption of this sensor using SPICE simulation. A test chip was fabricated using a 65 nm CMOS process, and the transition in the peak frequency and the power consumption were measured. When the outer diameter of the inductor was 46 µm, the power consumption was 31.2 mW, which matched well with the simulation results.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

NASA Astrophysics Data System (ADS)

Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

2008-09-01

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.

Simulating interfering fringe displacements by lateral shifts of a camera for educational purposes

NASA Astrophysics Data System (ADS)

Rivera-Ortega, Uriel

2018-07-01

In this manuscript we propose a simple method to emulate fringe displacements in a fringe pattern, due to the interference of two plane waves, by using lateral shifts of a CMOS detector under the scheme of a Twyman–Green interferometric setup, avoiding unwanted vibrations and the need for specific and expensive devices in order to accomplish the task. The simplicity of the proposed experimental setup allows it to be easily replicated and used for teaching or demonstrative purposes, essentially for undergraduate students.

Real time, TV-based, point-image quantizer and sorter

DOEpatents

Case, Arthur L.; Davidson, Jackson B.

1976-01-01

A device is provided for improving the vertical resolution in a television-based, two-dimensional readout for radiation detection systems such as are used to determine the location of light or nuclear radiation impinging a target area viewed by a television camera, where it is desired to store the data indicative of the centroid location of such images. In the example embodiment, impinging nuclear radiation detected in the form of a scintillation occurring in a crystal is stored as a charge image on a television camera tube target. The target is scanned in a raster and the image position is stored according to a corresponding vertical scan number and horizontal position number along the scan. To determine the centroid location of an image that may overlap a number of horizontal scan lines along the vertical axis of the raster, digital logic circuits are provided with at least four series-connected shift registers, each having 512 bit positions according to a selected 512 horizontal increment of resolutions along a scan line. The registers are shifted by clock pulses at a rate of 512 pulses per scan line. When an image or portion thereof is detected along a scan, its horizontal center location is determined and the present front bit is set in the first shift register and shifted through the registers one at a time for each horizontal scan. Each register is compared bit-by-bit with the preceding register to detect coincident set bit positions until the last scan line detecting a portion of the image is determined. Depending on the number of shift registers through which the first detection of the image is shifted, circuitry is provided to store the vertical center position of the event according to the number of shift registers through which the first detection of the event is shifted. Interpolation circuitry is provided to determine if the event centroid is between adjacent scan lines and stored in a vertical address accordingly. The horizontal location of the event is stored in a separate address memory.

A dual slope charge sampling analog front-end for a wireless neural recording system.

PubMed

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

2014-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.

A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit

2015-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm2 and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µVrms in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW. PMID:25570655

Unattended Multiplicity Shift Register

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matt; Jones, David C.

2017-01-16

The Unattended Multiplicity Shift Register (UMSR) is a specialized pulse counter used primarily to count neutron events originating in neutron detection instruments. While the counter can be used to count any TTL input pulses, its unique ability to record time correlated events and the multiplicity distributions of these events makes it an ideal instrument for counting neutron events in the nuclear fields of material safeguards, waste assay and process monitoring and control. The UMSR combines the Los Alamos National Laboratory (LANL) simple and robust shift register design with a Commercial-Off-The-Shelf (COTS) processor and Ethernet communications. The UMSR is fully compatiblemore » with existing International Atomic Energy Agency (IAEA) neutron data acquisition instruments such as the Advance Multiplicity Shift Register (AMSR) and JSR-15. The UMSR has three input channels: a multiplicity shift register input and two auxiliary inputs. The UMSR provides 0V to 2kV of programmable High Voltage (HV) bias and both a 12V and a 5V detector power supply output. A serial over USB communication line to the UMSR allows the use of existing versions of INCC or MIC software while the Ethernet port is compatible with the new IAEA RAINSTORM communication protocol.« less

On-chip programmable ultra-wideband microwave photonic phase shifter and true time delay unit.

PubMed

Burla, Maurizio; Cortés, Luis Romero; Li, Ming; Wang, Xu; Chrostowski, Lukas; Azaña, José

2014-11-01

We proposed and experimentally demonstrated an ultra-broadband on-chip microwave photonic processor that can operate both as RF phase shifter (PS) and true-time-delay (TTD) line, with continuous tuning. The processor is based on a silicon dual-phase-shifted waveguide Bragg grating (DPS-WBG) realized with a CMOS compatible process. We experimentally demonstrated the generation of delay up to 19.4 ps over 10 GHz instantaneous bandwidth and a phase shift of approximately 160° over the bandwidth 22-29 GHz. The available RF measurement setup ultimately limits the phase shifting demonstration as the device is capable of providing up to 300° phase shift for RF frequencies over a record bandwidth approaching 1 THz.

Concatenated shift registers generating maximally spaced phase shifts of PN-sequences

NASA Technical Reports Server (NTRS)

Hurd, W. J.; Welch, L. R.

1977-01-01

A large class of linearly concatenated shift registers is shown to generate approximately maximally spaced phase shifts of pn-sequences, for use in pseudorandom number generation. A constructive method is presented for finding members of this class, for almost all degrees for which primitive trinomials exist. The sequences which result are not normally characterized by trinomial recursions, which is desirable since trinomial sequences can have some undesirable randomness properties.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

PubMed

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-12-26

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

Design of a compact CMOS-compatible photonic antenna by topological optimization.

PubMed

Pita, Julián L; Aldaya, Ivan; Dainese, Paulo; Hernandez-Figueroa, Hugo E; Gabrielli, Lucas H

2018-02-05

Photonic antennas are critical in applications such as spectroscopy, photovoltaics, optical communications, holography, and sensors. In most of those applications, metallic antennas have been employed due to their reduced sizes. Nevertheless, compact metallic antennas suffer from high dissipative loss, wavelength-dependent radiation pattern, and they are difficult to integrate with CMOS technology. All-dielectric antennas have been proposed to overcome those disadvantages because, in contrast to metallic ones, they are CMOS-compatible, easier to integrate with typical silicon waveguides, and they generally present a broader wavelength range of operation. These advantages are achieved, however, at the expense of larger footprints that prevent dense integration and their use in massive phased arrays. In order to overcome this drawback, we employ topological optimization to design an all-dielectric compact antenna with vertical emission over a broad wavelength range. The fabricated device has a footprint of 1.78 µm × 1.78 µm and shows a shift in the direction of its main radiation lobe of only 4° over wavelengths ranging from 1470 nm to 1550 nm and a coupling efficiency bandwidth broader than 150 nm.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Two-phase charge-coupled device

NASA Technical Reports Server (NTRS)

Kosonocky, W. F.; Carnes, J. E.

1973-01-01

A charge-transfer efficiency of 99.99% per stage was achieved in the fat-zero mode of operation of 64- and 128-stage two-phase charge-coupled shift registers at 1.0-MHz clock frequency. The experimental two-phase charge-coupled shift registers were constructed in the form of polysilicon gates overlapped by aluminum gates. The unidirectional signal flow was accomplished by using n-type substrates with 0.5 to 1.0 ohm-cm resistivity in conjunction with a channel oxide thickness of 1000 A for the polysilicon gates and 3000 A for the aluminum gates. The operation of the tested shift registers with fat zero is in good agreement with the free-charge transfer characteristics expected for the tested structures. The charge-transfer losses observed when operating the experimental shift registers without the fat zero are attributed to fast interface state trapping. The analytical part of the report contains a review backed up by an extensive appendix of the free-charge transfer characteristics of CCD's in terms of thermal diffusion, self-induced drift, and fringing field drift. Also, a model was developed for the charge-transfer losses resulting from charge trapping by fast interface states. The proposed model was verified by the operation of the experimental two-phase charge-coupled shift registers.

Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor.

PubMed

Zin, Hafiz M; Harris, Emma J; Osmond, John P F; Allinson, Nigel M; Evans, Philip M

2013-05-21

This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s(-1) with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

Electronic shift register memory based on molecular electron-transfer reactions

NASA Technical Reports Server (NTRS)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

Perceptions and observations of off-shift nursing.

PubMed

de Cordova, Pamela B; Phibbs, Ciaran S; Stone, Patricia W

2013-03-01

The purpose of this paper is to qualitatively explore registered nurse perceptions of off-shift (e.g. nights and weekends) nursing care and quality compared with regular hours. Patients admitted to hospitals on off-shifts have worse outcomes than patients admitted on more regular hours. The underlying mechanism for this association is not well understood. In-depth semi-structured interviews of 23 registered nurses and four observer-as-participant observations were conducted on both medical-surgical and intensive care units in two large (>850 beds) tertiary hospitals. Content analysis was used to identify themes. Six themes emerged: (1) collaboration among self-reliant night nurses; (2) completing tasks; (3) taking a breather on weekend day shift; (4) new nurse requirement to work at night; (5) mixture of registered nurse personnel; and (6) night nurse perception of under-appreciation. Although nurses collaborate, complete more tasks and work with other types of registered nurses, the decreased resources available on off-shifts may affect quality care delivered in hospitals. These findings support the importance of management to provide sufficient resources in terms of ancillary personnel and balance less experienced staff. Facilitating communication between night and day nurses may help allay night nurses' feelings of under-appreciation. © 2012 Blackwell Publishing Ltd.

Using advertisement light-panel and CMOS image sensor with frequency-shift-keying for visible light communication.

PubMed

Chow, Chi-Wai; Shiu, Ruei-Jie; Liu, Yen-Chun; Liao, Xin-Lan; Lin, Kun-Hsien; Wang, Yi-Chang; Chen, Yi-Yuan

2018-05-14

A frequency-shift-keying (FSK) visible light communication (VLC) system is proposed and demonstrated using advertisement light-panel as transmitter and mobile-phone image sensor as receiver. The developed application program (APP) in mobile-phone can retrieve the rolling shutter effect (RSE) pattern produced by the FSK VLC signal effectively. Here, we also define noise-ratio value (NRV) to evaluate the contrast of different advertisements displayed on the light-panel. Both mobile-phones under test can achieve success rate > 96% even when the transmission distance is up to 200 cm and the NRVs are low.

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

PubMed Central

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-01-01

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

Design Method For Ultra-High Resolution Linear CCD Imagers

NASA Astrophysics Data System (ADS)

Sheu, Larry S.; Truong, Thanh; Yuzuki, Larry; Elhatem, Abdul; Kadekodi, Narayan

1984-11-01

This paper presents the design method to achieve ultra-high resolution linear imagers. This method utilizes advanced design rules and novel staggered bilinear photo sensor arrays with quadrilinear shift registers. Design constraint in the detector arrays and shift registers are analyzed. Imager architecture to achieve ultra-high resolution is presented. The characteristics of MTF, aliasing, speed, transfer efficiency and fine photolithography requirements associated with this architecture are also discussed. A CCD imager with advanced 1.5 um minimum feature size was fabricated. It is intended as a test vehicle for the next generation small sampling pitch ultra-high resolution CCD imager. Standard double-poly, two-phase shift registers were fabricated at an 8 um pitch using the advanced design rules. A special process step that blocked the source-drain implant from the shift register area was invented. This guaranteed excellent performance of the shift registers regardless of the small poly overlaps. A charge transfer efficiency of better than 0.99995 and maximum transfer speed of 8 MHz were achieved. The imager showed excellent performance. The dark current was less than 0.2 mV/ms, saturation 250 mV, adjacent photoresponse non-uniformity ± 4% and responsivity 0.7 V/ μJ/cm2 for the 8 μm x 6 μm photosensor size. The MTF was 0.6 at 62.5 cycles/mm. These results confirm the feasibility of the next generation ultra-high resolution CCD imagers.

Geometrical principles of homomeric β-barrels and β-helices: Application to modeling amyloid protofilaments.

PubMed

Hayward, Steven; Milner-White, E James

2017-10-01

Examples of homomeric β-helices and β-barrels have recently emerged. Here we generalize the theory for the shear number in β-barrels to encompass β-helices and homomeric structures. We introduce the concept of the "β-strip," the set of parallel or antiparallel neighboring strands, from which the whole helix can be generated giving it n-fold rotational symmetry. In this context, the shear number is interpreted as the sum around the helix of the fixed register shift between neighboring identical β-strips. Using this approach, we have derived relationships between helical width, pitch, angle between strand direction and helical axis, mass per length, register shift, and number of strands. The validity and unifying power of the method is demonstrated with known structures including α-hemolysin, T4 phage spike, cylindrin, and the HET-s(218-289) prion. From reported dimensions measured by X-ray fiber diffraction on amyloid fibrils, the relationships can be used to predict the register shift and the number of strands within amyloid protofilaments. This was used to construct models of transthyretin and Alzheimer β(40) amyloid protofilaments that comprise a single strip of in-register β-strands folded into a "β-strip helix." Results suggest both stabilization of an individual β-strip helix and growth by addition of further β-strip helices can involve the same pair of sequence segments associating with β-sheet hydrogen bonding at the same register shift. This process would be aided by a repeat sequence. Hence, understanding how the register shift (as the distance between repeat sequences) relates to helical dimensions will be useful for nanotube design. © 2017 Wiley Periodicals, Inc.

Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits

NASA Technical Reports Server (NTRS)

Beagles, Grant; Winters, Kel; Eldin, A. G.

1992-01-01

A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.

CMOS-Memristor Hybrid Nanoelectronics for AES Encryption

DTIC Science & Technology

2013-03-01

characterizing memristive materials can be associated with the Raman Effect. The Raman Effect or Raman Scattering results from inelastic scattering...of the incident excitation photons from the vibrational phonons in a sample material. Raman interaction is typically very weak, on the order of 1...in 10 7 incident photons being Raman shifted. Intensity of Raman scattering is very nonlinearly related to the incident wavelength just as Rayleigh

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alloatti, L., E-mail: luca.alloatti@gmail.com; Cheian, D.; Ram, R. J.

A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

The Feynman-Y Statistic in Relation to Shift-Register Neutron Coincidence Counting: Precision and Dead Time

DOE Office of Scientific and Technical Information (OSTI.GOV)

Croft, Stephen; Santi, Peter A.; Henzlova, Daniela

The Feynman-Y statistic is a type of autocorrelation analysis. It is defined as the excess variance-to-mean ratio, Y = VMR - 1, of the number count distribution formed by sampling a pulse train using a series of non-overlapping gates. It is a measure of the degree of correlation present on the pulse train with Y = 0 for Poisson data. In the context of neutron coincidence counting we show that the same information can be obtained from the accidentals histogram acquired using the multiplicity shift-register method, which is currently the common autocorrelation technique applied in nuclear safeguards. In the casemore » of multiplicity shift register analysis however, overlapping gates, either triggered by the incoming pulse stream or by a periodic clock, are used. The overlap introduces additional covariance but does not alter the expectation values. In this paper we discuss, for a particular data set, the relative merit of the Feynman and shift-register methods in terms of both precision and dead time correction. Traditionally the Feynman approach is applied with a relatively long gate width compared to the dieaway time. The main reason for this is so that the gate utilization factor can be taken as unity rather than being treated as a system parameter to be determined at characterization/calibration. But because the random trigger interval gate utilization factor is slow to saturate this procedure requires a gate width many times the effective 1/e dieaway time. In the traditional approach this limits the number of gates that can be fitted into a given assay duration. We empirically show that much shorter gates, similar in width to those used in traditional shift register analysis can be used. Because the way in which the correlated information present on the pulse train is extracted is different for the moments based method of Feynman and the various shift register based approaches, the dead time losses are manifested differently for these two approaches. The resulting estimates for the dead time corrected first and second order reduced factorial moments should be independent of the method however and this allows the respective dead time formalism to be checked. We discuss how to make dead time corrections in both the shift register and the Feynman approaches.« less

A molecular shift register based on electron transfer

NASA Technical Reports Server (NTRS)

Hopfield, J. J.; Onuchic, Josenelson; Beratan, David N.

1988-01-01

An electronic shift-register memory at the molecular level is described. The memory elements are based on a chain of electron-transfer molecules and the information is shifted by photoinduced electron-transfer reactions. This device integrates designed electronic molecules onto a very large scale integrated (silicon microelectronic) substrate, providing an example of a 'molecular electronic device' that could actually be made. The design requirements for such a device and possible synthetic strategies are discussed. Devices along these lines should have lower energy usage and enhanced storage density.

Design of a reversible single precision floating point subtractor.

PubMed

Anantha Lakshmi, Av; Sudha, Gf

2014-01-04

In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition/subtraction to be the most used floating-point operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floating-point subtractor. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, an 8-bit and a 24-bit subtractor, and a normalization unit. For normalization, a 24-bit Reversible Leading Zero Detector and a 24-bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1-bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3. The total on-chip power consumed by the proposed 32-bit reversible floating point subtractor is 0.410 W.

Accurate estimation of camera shot noise in the real-time

NASA Astrophysics Data System (ADS)

Cheremkhin, Pavel A.; Evtikhiev, Nikolay N.; Krasnov, Vitaly V.; Rodin, Vladislav G.; Starikov, Rostislav S.

2017-10-01

Nowadays digital cameras are essential parts of various technological processes and daily tasks. They are widely used in optics and photonics, astronomy, biology and other various fields of science and technology such as control systems and video-surveillance monitoring. One of the main information limitations of photo- and videocameras are noises of photosensor pixels. Camera's photosensor noise can be divided into random and pattern components. Temporal noise includes random noise component while spatial noise includes pattern noise component. Temporal noise can be divided into signal-dependent shot noise and signal-nondependent dark temporal noise. For measurement of camera noise characteristics, the most widely used methods are standards (for example, EMVA Standard 1288). It allows precise shot and dark temporal noise measurement but difficult in implementation and time-consuming. Earlier we proposed method for measurement of temporal noise of photo- and videocameras. It is based on the automatic segmentation of nonuniform targets (ASNT). Only two frames are sufficient for noise measurement with the modified method. In this paper, we registered frames and estimated shot and dark temporal noises of cameras consistently in the real-time. The modified ASNT method is used. Estimation was performed for the cameras: consumer photocamera Canon EOS 400D (CMOS, 10.1 MP, 12 bit ADC), scientific camera MegaPlus II ES11000 (CCD, 10.7 MP, 12 bit ADC), industrial camera PixeLink PL-B781F (CMOS, 6.6 MP, 10 bit ADC) and video-surveillance camera Watec LCL-902C (CCD, 0.47 MP, external 8 bit ADC). Experimental dependencies of temporal noise on signal value are in good agreement with fitted curves based on a Poisson distribution excluding areas near saturation. Time of registering and processing of frames used for temporal noise estimation was measured. Using standard computer, frames were registered and processed during a fraction of second to several seconds only. Also the accuracy of the obtained temporal noise values was estimated.

Adaptive multiphoton endomicroscopy through a dynamically deformed multicore optical fiber using proximal detection.

PubMed

Warren, Sean C; Kim, Youngchan; Stone, James M; Mitchell, Claire; Knight, Jonathan C; Neil, Mark A A; Paterson, Carl; French, Paul M W; Dunsby, Chris

2016-09-19

This paper demonstrates multiphoton excited fluorescence imaging through a polarisation maintaining multicore fiber (PM-MCF) while the fiber is dynamically deformed using all-proximal detection. Single-shot proximal measurement of the relative optical path lengths of all the cores of the PM-MCF in double pass is achieved using a Mach-Zehnder interferometer read out by a scientific CMOS camera operating at 416 Hz. A non-linear least squares fitting procedure is then employed to determine the deformation-induced lateral shift of the excitation spot at the distal tip of the PM-MCF. An experimental validation of this approach is presented that compares the proximally measured deformation-induced lateral shift in focal spot position to an independent distally measured ground truth. The proximal measurement of deformation-induced shift in focal spot position is applied to correct for deformation-induced shifts in focal spot position during raster-scanning multiphoton excited fluorescence imaging.

CMOS Bit-Stream Band-Pass Beamforming

DTIC Science & Technology

2016-03-31

unlimited. with direct IF sampling, most of the signal processing, including digital down-conversion ( DDC ), is carried out in the digital domain, and I/Q...level digitized signals are directly processed without decimation filtering for I/Q DDC and phase shifting. This novel BSP approach replaces bulky...positive feedback. The resonator center frequency of fs/4 (260MHz) simplifies the design of DDC . 4b tunable capacitors adjust the center frequency

High-speed line-scan camera with digital time delay integration

NASA Astrophysics Data System (ADS)

Bodenstorfer, Ernst; Fürtler, Johannes; Brodersen, Jörg; Mayer, Konrad J.; Eckel, Christian; Gravogl, Klaus; Nachtnebel, Herbert

2007-02-01

Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical application are discussed and key features of the camera are listed.

Automatic oscillator frequency control system

NASA Technical Reports Server (NTRS)

Smith, S. F. (Inventor)

1985-01-01

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder.

A K-Band Low-Power Phase Shifter Based on Injection Locked Oscillator in 0.13 μm CMOS Technology

NASA Astrophysics Data System (ADS)

Qiu, Qi-Lin; Yu, Xiao-Peng; Sui, Wen-Quan

2017-11-01

In this paper, the design challenges of the injection-locked oscillator (ILO)-based phase shifter are reviewed and analyzed. The key design considerations such as the operating frequency, locking range, and linearity of the phase shifters are analysed in detail. It is possible to optimize the phase shifter in certain parameters such as ultra-low power while meeting the requirements of a certain system. As a design example, a K-band phase shifter is implemented using a commercial 0.13 μm CMOS technology, where a conventional LC tank based topology is implemented but optimised with a good balance among power consumption, working range, sensitivity, and silicon area, etc. Measurement results show that the proposed phase shift is able to work at 22-23.4 GHz with a range of 180∘ while consuming 3.14 mW from a 1.2 V supply voltage.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective

NASA Astrophysics Data System (ADS)

Das, Kushal; Lehmann, Torsten

2014-07-01

The effect of ultra low operating temperature on mismatch among identically designed Silicon-on-Sapphire CMOS devices is investigated in detail from a circuit design view point. The evolution of transistor matching properties for different operating conditions at both room and 4.2 K temperature are presented. The statistical analysis reveals that mismatch at low temperature is effectively unrelated to that at room temperature, which disagrees with previously published literature. The measurement data was used to extract key transistor parameters and the consequence of temperature lowering on their respective variance is estimated. We find that standard deviation of the threshold-voltage mismatch deteriorates by a factor ∼2 at 4.2 K temperature. Similar to room temperature operation, mismatch at 4.2 K is bias point dependent and the degradation of matching at very low temperature depends to some extent on how the bias point shifts upon cooling.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Chen, Cao; Bing, Zhang; Junfeng, Wang; Longsheng, Wu

2016-05-01

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices. Project supported by the National Defense Pre-Research Foundation of China (No. 51311050301095).

Fixed Pattern Noise pixel-wise linear correction for crime scene imaging CMOS sensor

NASA Astrophysics Data System (ADS)

Yang, Jie; Messinger, David W.; Dube, Roger R.; Ientilucci, Emmett J.

2017-05-01

Filtered multispectral imaging technique might be a potential method for crime scene documentation and evidence detection due to its abundant spectral information as well as non-contact and non-destructive nature. Low-cost and portable multispectral crime scene imaging device would be highly useful and efficient. The second generation crime scene imaging system uses CMOS imaging sensor to capture spatial scene and bandpass Interference Filters (IFs) to capture spectral information. Unfortunately CMOS sensors suffer from severe spatial non-uniformity compared to CCD sensors and the major cause is Fixed Pattern Noise (FPN). IFs suffer from "blue shift" effect and introduce spatial-spectral correlated errors. Therefore, Fixed Pattern Noise (FPN) correction is critical to enhance crime scene image quality and is also helpful for spatial-spectral noise de-correlation. In this paper, a pixel-wise linear radiance to Digital Count (DC) conversion model is constructed for crime scene imaging CMOS sensor. Pixel-wise conversion gain Gi,j and Dark Signal Non-Uniformity (DSNU) Zi,j are calculated. Also, conversion gain is divided into four components: FPN row component, FPN column component, defects component and effective photo response signal component. Conversion gain is then corrected to average FPN column and row components and defects component so that the sensor conversion gain is uniform. Based on corrected conversion gain and estimated image incident radiance from the reverse of pixel-wise linear radiance to DC model, corrected image spatial uniformity can be enhanced to 7 times as raw image, and the bigger the image DC value within its dynamic range, the better the enhancement.

Design of polarization imaging system based on CIS and FPGA

NASA Astrophysics Data System (ADS)

Zeng, Yan-an; Liu, Li-gang; Yang, Kun-tao; Chang, Da-ding

2008-02-01

As polarization is an important characteristic of light, polarization image detecting is a new image detecting technology of combining polarimetric and image processing technology. Contrasting traditional image detecting in ray radiation, polarization image detecting could acquire a lot of very important information which traditional image detecting couldn't. Polarization image detecting will be widely used in civilian field and military field. As polarization image detecting could resolve some problem which couldn't be resolved by traditional image detecting, it has been researched widely around the world. The paper introduces polarization image detecting in physical theory at first, then especially introduces image collecting and polarization image process based on CIS (CMOS image sensor) and FPGA. There are two parts including hardware and software for polarization imaging system. The part of hardware include drive module of CMOS image sensor, VGA display module, SRAM access module and the real-time image data collecting system based on FPGA. The circuit diagram and PCB was designed. Stokes vector and polarization angle computing method are analyzed in the part of software. The float multiply of Stokes vector is optimized into just shift and addition operation. The result of the experiment shows that real time image collecting system could collect and display image data from CMOS image sensor in real-time.

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

40-Gbit/s all-optical circulating shift register with an inverter.

PubMed

Hall, K L; Donnelly, J P; Groves, S H; Fennelly, C I; Bailey, R J; Napoleone, A

1997-10-01

We report what is believed to be the first demonstration of an all-optical circulating shift register using an ultrafast nonlinear interferometer with a polarization-insensitive semiconductor optical amplifier as the nonlinear switching element. The device operates at 40 Gbits/s, to our knowledge the highest speed demonstrated to date. Also, the demonstration proves the cascadability of the ultrafast nonlinear interferometric switch.

Multi-bit operations in vertical spintronic shift registers

NASA Astrophysics Data System (ADS)

Lavrijsen, Reinoud; Petit, Dorothée C. M. C.; Fernández-Pacheco, Amalio; Lee, JiHyun; Mansell, Mansell; Cowburn, Russell P.

2014-03-01

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

Multi-bit operations in vertical spintronic shift registers.

PubMed

Lavrijsen, Reinoud; Petit, Dorothée C M C; Fernández-Pacheco, Amalio; Lee, Jihyun; Mansell, Mansell; Cowburn, Russell P

2014-03-14

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

A novel optical detector concept for dedicated and multi-modality in vivo small animal imaging

NASA Astrophysics Data System (ADS)

Peter, Jörg; Schulz, Ralf B.; Unholtz, Daniel; Semmler, Wolfhard

2007-07-01

An optical detector suitable for inclusion in tomographic arrangements for non-contact in vivo bioluminescence and fluorescence imaging applications is proposed. It consists of a microlens array (MLA) intended for field-of-view definition, a large-field complementary metal-oxide-semiconductor (CMOS) chip for light detection, a septum mask for cross-talk suppression, and an exchangeable filter to block excitation light. Prototype detector units with sensitive areas of 2.5 cm x 5 cm each were assembled. The CMOS sensor constitutes a 512 x 1024 photodiode matrix at 48 μm pixel pitch. Refractive MLAs with plano-convex lenses of 480 μm in diameter and pitch were selected resulting in a 55 x 105 lens matrix. The CMOS sensor is aligned on the focal plane of the MLA at 2.15mm distance. To separate individual microlens images an opaque multi-bore septum mask of 2.1mm in thickness and bore diameters of 400 μm at 480 μm pitch, aligned with the lens pattern, is placed between MLA and CMOS. Intrinsic spatial detector resolution and sensitivity was evaluated experimentally as a function of detector-object distance. Due to its small overall dimensions such detectors can be favorably packed for tomographic imaging (optical diffusion tomography, ODT) yielding complete 2 π field-of-view coverage. We also present a design study of a device intended to simultaneously image positron labeled substrates (positron emission tomography, PET) and optical molecular probes in small animals such as mice and rats. It consists of a cylindrical allocation of optical detector units which form an inner detector ring while PET detector blocks are mounted in radial extension, those gaining complementary information in a single, intrinsically coregistered experimental data acquisition study. Finally, in a second design study we propose a method for integrated optical and magnetic resonance imaging (MRI) which yields in vivo functional/molecular information that is intrinsically registered with the anatomy of the image object.

Molecular implementation of molecular shift register memories

NASA Technical Reports Server (NTRS)

Beratan, David N. (Inventor); Onuchic, Jose N. (Inventor)

1991-01-01

An electronic shift register memory (20) at the molecular level is described. The memory elements are based on a chain of electron transfer molecules (22) and the information is shifted by photoinduced (26) electron transfer reactions. Thus, multi-step sequences of charge transfer reactions are used to move charge with high efficiency down a molecular chain. The device integrates compositions of the invention onto a VLSI substrate (36), providing an example of a molecular electronic device which may be fabricated. Three energy level schemes, molecular implementation of these schemes, optical excitation strategies, charge amplification strategies, and error correction strategies are described.

A high-throughput flow cytometry-on-a-CMOS platform for single-cell dielectric spectroscopy at microwave frequencies.

PubMed

Chien, Jun-Chau; Ameri, Ali; Yeh, Erh-Chia; Killilea, Alison N; Anwar, Mekhail; Niknejad, Ali M

2018-06-06

This work presents a microfluidics-integrated label-free flow cytometry-on-a-CMOS platform for the characterization of the cytoplasm dielectric properties at microwave frequencies. Compared with MHz impedance cytometers, operating at GHz frequencies offers direct intracellular permittivity probing due to electric fields penetrating through the cellular membrane. To overcome the detection challenges at high frequencies, the spectrometer employs on-chip oscillator-based sensors, which embeds simultaneous frequency generation, electrode excitation, and signal detection capabilities. By employing an injection-locking phase-detection technique, the spectrometer offers state-of-the-art sensitivity, achieving a less than 1 aFrms capacitance detection limit (or 5 ppm in frequency-shift) at a 100 kHz noise filtering bandwidth, enabling high throughput (>1k cells per s), with a measured cellular SNR of more than 28 dB. With CMOS/microfluidics co-design, we distribute four sensing channels at 6.5, 11, 17.5, and 30 GHz in an arrayed format whereas the frequencies are selected to center around the water relaxation frequency at 18 GHz. An issue in the integration of CMOS and microfluidics due to size mismatch is also addressed through introducing a cost-efficient epoxy-molding technique. With 3-D hydrodynamic focusing microfluidics, we perform characterization on four different cell lines including two breast cell lines (MCF-10A and MDA-MB-231) and two leukocyte cell lines (K-562 and THP-1). After normalizing the higher frequency signals to the 6.5 GHz ones, the size-independent dielectric opacity shows a differentiable distribution at 17.5 GHz between normal (0.905 ± 0.160, mean ± std.) and highly metastatic (1.033 ± 0.107) breast cells with p ≪ 0.001.

Flexible active-matrix displays and shift registers based on solution-processed organic transistors.

PubMed

Gelinck, Gerwin H; Huitema, H Edzer A; van Veenendaal, Erik; Cantatore, Eugenio; Schrijnemakers, Laurens; van der Putten, Jan B P H; Geuns, Tom C T; Beenhakkers, Monique; Giesbers, Jacobus B; Huisman, Bart-Hendrik; Meijer, Eduard J; Benito, Estrella Mena; Touwslager, Fred J; Marsman, Albert W; van Rens, Bas J E; de Leeuw, Dago M

2004-02-01

At present, flexible displays are an important focus of research. Further development of large, flexible displays requires a cost-effective manufacturing process for the active-matrix backplane, which contains one transistor per pixel. One way to further reduce costs is to integrate (part of) the display drive circuitry, such as row shift registers, directly on the display substrate. Here, we demonstrate flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-microm-thick polyimide substrates. The displays can be bent to a radius of 1 cm without significant loss in performance. Using the same process flow we prepared row shift registers. With 1,888 transistors, these are the largest organic integrated circuits reported to date. More importantly, the operating frequency of 5 kHz is sufficiently high to allow integration with the display operating at video speed. This work therefore represents a major step towards 'system-on-plastic'.

Optical modulator based on silicon nanowires racetrack resonator

NASA Astrophysics Data System (ADS)

Sherif, S. M.; Shahada, L.; Swillam, M.

2018-02-01

An optical modulator based on the racetrack resonator configuration is introduced. The structure of the resonator modulator is built from silicon nanowires on silica. The cladding and voids between the silicon nanowires are filled with an electro-optic polymer. The proposed modulator is fully CMOS compatible. When the resonance is tuned to the 1.55μm wavelength, it experiences a wavelength shift upon voltage application, which is measured at the output as a change in the power level.

Vocal and neural responses to unexpected changes in voice pitch auditory feedback during register transitions

PubMed Central

Patel, Sona; Lodhavia, Anjli; Frankford, Saul; Korzyukov, Oleg; Larson, Charles R.

2016-01-01

Objective/Hypothesis It is known that singers are able to control their voice to maintain a relatively constant vocal quality while transitioning between vocal registers; however, the neural mechanisms underlying this effect are not understood. It was hypothesized that greater attention to the acoustical feedback of the voice and increased control of the vocal musculature during register transitions compared to singing within a register would be represented as neurological differences in event-related potentials (ERPs). Study Design/Methods Nine singers sang musical notes at the high end of the modal register (the boundary between the modal and head/falsetto registers) and at the low end (the boundary between the modal and fry/pulse registers). While singing, the pitch of the voice auditory feedback was unexpectedly shifted either into the adjacent register (“toward” the register boundary) or within the modal register (“away from” the boundary). Singers were instructed to maintain a constant pitch and ignore any changes to their voice feedback. Results Vocal response latencies and magnitude of the accompanying N1 and P2 ERPs were greatest at the lower (modal-fry) boundary when the pitch shift carried the subjects’ voices into the fry register as opposed to remaining within the modal register. Conclusions These findings suggest that when a singer lowers the pitch of their voice such that it enters the fry register from the modal register, there is increased sensory-motor control of the voice, reflected as increased magnitude of the neural potentials to help minimize qualitative changes in the voice. PMID:26739860

A Wide Dynamic Range Tapped Linear Array Image Sensor

NASA Astrophysics Data System (ADS)

Washkurak, William D.; Chamberlain, Savvas G.; Prince, N. Daryl

1988-08-01

Detectors for acousto-optic signal processing applications require fast transient response as well as wide dynamic range. There are two major choices of detectors: conductive or integration mode. Conductive mode detectors have an initial transient period before they reach then' i equilibrium state. The duration of 1 his period is dependent on light level as well as detector capacitance. At low light levels a conductive mode detector is very slow; response time is typically on the order of milliseconds. Generally. to obtain fast transient response an integrating mode detector is preferred. With integrating mode detectors. the dynamic range is determined by the charge storage capability of the tran-sport shift registers and the noise level of the image sensor. The conventional net hod used to improve dynamic range is to increase the shift register charge storage capability. To achieve a dynamic range of fifty thousand assuming two hundred noise equivalent electrons, a charge storage capability of ten million electrons would be required. In order to accommodate this amount of charge. unrealistic shift registers widths would be required. Therefore, with an integrating mode detector it is difficult to achieve a dynamic range of over four orders of magnitude of input light intensity. Another alternative is to solve the problem at the photodetector aml not the shift, register. DALSA's wide dynamic range detector utilizes an optimized, ion implant doped, profiled MOSFET photodetector specifically designed for wide dynamic range. When this new detector operates at high speed and at low light levels the photons are collected and stored in an integrating fashion. However. at bright light levels where transient periods are short, the detector switches into a conductive mode. The light intensity is logarithmically compressed into small charge packets, easily carried by the CCD shift register. As a result of the logarithmic conversion, dynamic ranges of over six orders of magnitide are obtained. To achieve the short integration times necessary in acousto-optic applications. t he wide dynamic range detector has been implemented into a tapped array architecture with eight outputs and 256 photoelements. Operation of each 01)1,1)111 at 16 MHz yields detector integration times of 2 micro-seconds. Buried channel two phase CCD shift register technology is utilized to minimize image sensor noise improve video output rates and increase ease of operation.

A novel wireless power and data transmission AC to DC converter for an implantable device.

PubMed

Liu, Jhao-Yan; Tang, Kea-Tiong

2013-01-01

This article presents a novel AC to DC converter implemented by standard CMOS technology, applied for wireless power transmission. This circuit combines the functions of the rectifier and DC to DC converter, rather than using the rectifier to convert AC to DC and then supplying the required voltage with regulator as in the transitional method. This modification can reduce the power consumption and the area of the circuit. This circuit also transfers the loading condition back to the external circuit by the load shift keying(LSK), determining if the input power is not enough or excessive, which increases the efficiency of the total system. The AC to DC converter is fabricated with the TSMC 90nm CMOS process. The circuit area is 0.071mm(2). The circuit can produce a 1V DC voltage with maximum output current of 10mA from an AC input ranging from 1.5V to 2V, at 1MHz to 10MHz.

Demonstration of free space coherent optical communication using integrated silicon photonic orbital angular momentum devices.

PubMed

Su, Tiehui; Scott, Ryan P; Djordjevic, Stevan S; Fontaine, Nicolas K; Geisler, David J; Cai, Xinran; Yoo, S J B

2012-04-23

We propose and demonstrate silicon photonic integrated circuits (PICs) for free-space spatial-division-multiplexing (SDM) optical transmission with multiplexed orbital angular momentum (OAM) states over a topological charge range of -2 to +2. The silicon PIC fabricated using a CMOS-compatible process exploits tunable-phase arrayed waveguides with vertical grating couplers to achieve space division multiplexing and demultiplexing. The experimental results utilizing two silicon PICs achieve SDM mux/demux bit-error-rate performance for 1‑b/s/Hz, 10-Gb/s binary phase shifted keying (BPSK) data and 2-b/s/Hz, 20-Gb/s quadrature phase shifted keying (QPSK) data for individual and two simultaneous OAM states. © 2012 Optical Society of America

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Electrostatically Actuated Resonant Microcantilever Beam in CMOS Technology for the Detection of Chemical Weapons

DTIC Science & Technology

2005-01-01

sorption . In this regard, the length ( ) and 1530-437X/$20.00 © 2005 IEEE Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting...temperature. The beam’s resonant frequency shift re- sponse resulting from analyte sorption increases with increasing thickness of the polymer layer. At...pneumatic tubing used for all gas wetted parts was PFA . The chip mounted in the Kyocera package was sealed by positioning a Combo Lid (Chelsea Technology

Low-Power Architectures for Large Radio Astronomy Correlators

NASA Technical Reports Server (NTRS)

D'Addario, Larry R.

2011-01-01

The architecture of a cross-correlator for a synthesis radio telescope with N greater than 1000 antennas is studied with the objective of minimizing power consumption. It is found that the optimum architecture minimizes memory operations, and this implies preference for a matrix structure over a pipeline structure and avoiding the use of memory banks as accumulation registers when sharing multiply-accumulators among baselines. A straw-man design for N = 2000 and bandwidth of 1 GHz, based on ASICs fabricated in a 90 nm CMOS process, is presented. The cross-correlator proper (excluding per-antenna processing) is estimated to consume less than 35 kW.

A note on chaotic unimodal maps and applications.

PubMed

Zhou, C T; He, X T; Yu, M Y; Chew, L Y; Wang, X G

2006-09-01

Based on the word-lift technique of symbolic dynamics of one-dimensional unimodal maps, we investigate the relation between chaotic kneading sequences and linear maximum-length shift-register sequences. Theoretical and numerical evidence that the set of the maximum-length shift-register sequences is a subset of the set of the universal sequence of one-dimensional chaotic unimodal maps is given. By stabilizing unstable periodic orbits on superstable periodic orbits, we also develop techniques to control the generation of long binary sequences.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

NASA Astrophysics Data System (ADS)

Liu, Tianqi; Yang, Zhenlei; Guo, Jinlong; Du, Guanghua; Tong, Teng; Wang, Xiaohui; Su, Hong; Liu, Wenjing; Liu, Jiande; Wang, Bin; Ye, Bing; Liu, Jie

2017-08-01

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25 MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

Full-custom design of split-set data weighted averaging with output register for jitter suppression

NASA Astrophysics Data System (ADS)

Jubay, M. C.; Gerasta, O. J.

2015-06-01

A full-custom design of an element selection algorithm, named as Split-set Data Weighted Averaging (SDWA) is implemented in 90nm CMOS Technology Synopsys Library. SDWA is applied in seven unit elements (3-bit) using a thermometer-coded input. Split-set DWA is an improved DWA algorithm which caters the requirement for randomization along with long-term equal element usage. Randomization and equal element-usage improve the spectral response of the unit elements due to higher Spurious-free dynamic range (SFDR) and without significantly degrading signal-to-noise ratio (SNR). Since a full-custom, the design is brought to transistor-level and the chip custom layout is also provided, having a total area of 0.3mm2, a power consumption of 0.566 mW, and simulated at 50MHz clock frequency. On this implementation, SDWA is successfully derived and improved by introducing a register at the output that suppresses the jitter introduced at the final stage due to switching loops and successive delays.

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2015-01-01

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP). PMID:27069422

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

PubMed

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2016-01-15

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm 2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

Event sequence detector

NASA Technical Reports Server (NTRS)

Hanna, M. F. (Inventor)

1973-01-01

An event sequence detector is described with input units, each associated with a row of bistable elements arranged in an array of rows and columns. The detector also includes a shift register which is responsive to clock pulses from any of the units to sequentially provide signals on its output lines each of which is connected to the bistable elements in a corresponding column. When the event-indicating signal is received by an input unit it provides a clock pulse to the shift register to provide the signal on one of its output lines. The input unit also enables all its bistable elements so that the particular element in the column supplied with the signal from the register is driven to an event-indicating state.

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

PubMed

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

Scheduling and shift work characteristics associated with risk for occupational injury in newly licensed registered nurses: An observational study.

PubMed

Stimpfel, Amy Witkoski; Brewer, Carol S; Kovner, Christine T

2015-11-01

Registered nurses across the globe bear a heavy injury burden. Every shift, nurses are exposed to a variety of hazards that can jeopardize their health, which negatively impacts their ability to provide high-quality patient care. Previous research suggests that inexperienced, or newly licensed nurses, may have an increased risk for certain occupational injuries. However, the current knowledge base is insufficient to fully understand how work hours influence newly licensed nurses' occupational injury, given the significant variation in hospital organization and work characteristics. To describe newly licensed nurses' shift work characteristics and determine the association between shift type and scheduling characteristics and nurse injury, before and after adjusting for individual and combined effects of demographics, external context, organizational context, and work context, following the Organization of Work model. This study is a secondary analysis of a nationally representative survey of newly licensed registered nurses using a cross-sectional design. The analytic sample includes 1744 newly licensed registered nurses from 34 states and the District of Columbia who reported working in a hospital and were within 6-18 months of passing their state licensure exam at the time of survey administration. Descriptive statistics were calculated, followed by bivariate and multivariate Poisson regression models to assess the relationship between shift type and scheduling characteristics and nurse injury. Lastly, full models with the addition of demographics, external context, organizational context, and work context variables were calculated. The majority (79%) of newly licensed nurses worked 12-h shifts, a near majority worked night shift (44%), and over half (61%) worked overtime (mandatory or voluntary) weekly. Nurses working weekly overtime were associated with a 32% [incidence rate ratio (IRR) 1.32, CI 1.07-1.62] increase in the risk of a needle stick and nurses working night shift were associated with a 16% [IRR 1.16, CI 1.02-1.33] increase in the risk of a sprain or strain injury. Overtime and night shift work were significantly associated with increased injury risk in newly licensed nurses independent of other work factors and demographic characteristics. The findings warrant further study given the long-term consequences of these injuries, costs associated with treatment, and loss of worker productivity. Copyright © 2015 Elsevier Ltd. All rights reserved.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

NASA Astrophysics Data System (ADS)

Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

2017-02-01

The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Feedback shift register sequences versus uniformly distributed random sequences for correlation chromatography

NASA Technical Reports Server (NTRS)

Kaljurand, M.; Valentin, J. R.; Shao, M.

1996-01-01

Two alternative input sequences are commonly employed in correlation chromatography (CC). They are sequences derived according to the algorithm of the feedback shift register (i.e., pseudo random binary sequences (PRBS)) and sequences derived by using the uniform random binary sequences (URBS). These two sequences are compared. By applying the "cleaning" data processing technique to the correlograms that result from these sequences, we show that when the PRBS is used the S/N of the correlogram is much higher than the one resulting from using URBS.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

Scattering effects on the performance of carbon nanotube field effect transistor in a compact model

NASA Astrophysics Data System (ADS)

Hamieh, S. D.; Desgreys, P.; Naviner, J. F.

2010-01-01

Carbon nanotube field-effect transistors (CNTFET) are being extensively studied as possible successors to CMOS. Device simulators have been developed to estimate their performance in sub-10-nm and device structures have been fabricated. In this work, a new compact model of single-walled semiconducting CNTFET is proposed implementing the calculation of energy conduction sub-band minima and the treatment of scattering effects through energy shift in CNTFET. The developed model has been used to simulate I-V characteristics using VHDL-AMS simulator.

In-pixel conversion with a 10 bit SAR ADC for next generation X-ray FELs

NASA Astrophysics Data System (ADS)

Lodola, L.; Batignani, G.; Benkechkache, M. A.; Bettarini, S.; Casarosa, G.; Comotti, D.; Dalla Betta, G. F.; Fabris, L.; Forti, F.; Grassi, M.; Latreche, S.; Malcovati, P.; Manghisoni, M.; Mendicino, R.; Morsani, F.; Paladino, A.; Pancheri, L.; Paoloni, E.; Ratti, L.; Re, V.; Rizzo, G.; Traversi, G.; Vacchi, C.; Verzellesi, G.; Xu, H.

2016-07-01

This work presents the design of an interleaved Successive Approximation Register (SAR) ADC, part of the readout channel for the PixFEL detector. The PixFEL project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging for applications at the next generation Free Electron Laser (FEL) facilities. For this purpose, the collaboration is developing the fundamental microelectronic building blocks for the readout channel. This work focuses on the design of the ADC carried out in a 65 nm CMOS technology. To obtain a good tradeoff between power consumption, conversion speed and area occupation, an interleaved SAR ADC architecture was adopted.

Spin pumping driven auto-oscillator for phase-encoded logic—device design and material requirements

NASA Astrophysics Data System (ADS)

Rakheja, S.; Kani, N.

2017-05-01

In this work, we propose a spin nano-oscillator (SNO) device where information is encoded in the phase (time-shift) of the output oscillations. The spin current required to set up the oscillations in the device is generated through spin pumping from an input nanomagnet that is precessing at RF frequencies. We discuss the operation of the SNO device, in which either the in-plane (IP) or out-of-plane (OOP) magnetization oscillations are utilized toward implementing ultra-low-power circuits. Using physical models of the nanomagnet dynamics and the spin transport through non-magnetic channels, we quantify the reliability of the SNO device using a "scaling ratio". Material requirements for the nanomagnet and the channel to ensure correct logic functionality are identified using the scaling ratio metric. SNO devices consume (2-5)× lower energy compared to CMOS devices and other spin-based devices with similar device sizes and material parameters. The analytical models presented in this work can be used to optimize the performance and scaling of SNO devices in comparison to CMOS devices at ultra-scaled technology nodes.

InGaAsP Mach-Zehnder interferometer optical modulator monolithically integrated with InGaAs driver MOSFET on a III-V CMOS photonics platform.

PubMed

Park, Jin-Kown; Takagi, Shinichi; Takenaka, Mitsuru

2018-02-19

We demonstrated the monolithic integration of a carrier-injection InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) on a III-V-on-insulator (III-V-OI) wafer. A low-resistivity lateral PIN junction was formed along an InGaAsP rib waveguide by Zn diffusion and Ni-InGaAsP alloy, enabling direct driving of the InGaAsP optical modulator by the InGaAs MOSFET. A π phase shift of the InGaAsP optical modulator was obtained through the injection of a drain current from the InGaAs MOSFET with a gate voltage of approximately 1 V. This proof-of-concept demonstration of the monolithic integration of the InGaAsP optical modulator and InGaAs driver MOSFET will enable us to develop high-performance and low-power electronic-photonic integrated circuits on a III-V CMOS photonics platform.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

Assessment of Fatigue in Deployed Critical Care Air Transport Team Crews

DTIC Science & Technology

2015-07-31

that nurses who worked longer than 12.5 hours were three times more likely to make a patient error. They also identified 68% of Certified Registered ...and aviation professionals are using fatigue countermeasures. Seventy-seven percent of Certified Registered Nurse Anesthetists reported using fatigue...shift fatigue and use of countermeasures and avoidance strategies by certified registered nurse anesthetists: a national survey. AANA J. 2015; 83(2

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Low-frequency sine wave hard-limiting technique

NASA Technical Reports Server (NTRS)

Anderson, T. O.

1977-01-01

Circuit includes serial-in/parallel-out shift register and weighting network that are used to eliminate effects of noise and other nonrepetitive circuit transients. Register and weighting network average decisions from section of signal where decisions are more dependable or where differences between two consecutive samples are larger.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

A two-fold reduction in measurement time for neutron assay: Initial tests of a prototype dual-gated shift register

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stewart, J.E.; Bourret, S.C.; Krick, M.S.

1996-09-01

Neutron coincidence counting (NCC) is used routinely around the world for nondestructive mass assay of uranium and plutonium in many forms, including waste. Compared with other methods, NCC is generally the most flexible, economic, and rapid. Many applications of NCC would benefit from a reduction in counting time required for a fixed random error. We have developed and tested the first prototype of a dual- gated, shift-register-based electronics unit that offers the potential of decreased measurement time for all passive and active NCC applications.

A two-fold reduction in measurement time for neutron assay: Initial tests of a prototype dual-gated shift register

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stewart, J.E.; Bourret, S.C.; Krick, M.S.

1996-12-31

Neutron coincidence counting (NCC) is used routinely around the world for nondestructive mass assay of uranium and plutonium in many forms, including waste. Compared with other methods, NCC is generally the most flexible, economic, and rapid. Many applications of NCC would benefit from a reduction in counting time required for a fixed random error. The authors have developed and tested the first prototype of a dual-gated, shift-register-based electronics unit that offers the potential of decreased measurement time for all passive and active NCC applications.

Changes in nurses' decision making during a 12-h day shift.

PubMed

McClelland, L E; Switzer, F S; Pilcher, J J

2013-01-01

Although shift work is necessary in many health-care settings, research suggests that it can have detrimental effects on performance in health-care providers. To determine if a change in decision-making occurred across a 12-h day shift in a sample of registered nurses. The participants were nurses working a 12-h day shift (7 a.m.-7 p.m.) at a large hospital in the south-eastern USA. Participants completed a policy-capturing questionnaire, examining their likelihood of calling a physician in response to specific patient symptoms, at the beginning and end of the shift. They also completed self-report surveys on alertness, stress and sleepiness. Sixty-five nurses completed the study, an overall response rate of 41%. Participants significantly changed their decision-making policies from the beginning to the end of the work shift and also became significantly less alert and more stressed. However, there was no correlation between decision-making and reported alertness and stress. These results suggest that medical judgment in registered nurses changed from the beginning to the end of a 12-h day shift. One possible underlying mechanism responsible for the changes seen across the shift could be the ability to maintain attention, as suggested by the Controlled Attention Model. The current results expand upon previous research, indicating there are a variety of negative outcomes associated with shift work.

Electron trapping in rad-hard RCA IC's irradiated with electrons and gamma rays

NASA Technical Reports Server (NTRS)

Danchenko, V.; Brashears, S. S.; Fang, P. H.

1984-01-01

Enhanced electron trapping has been observed in n-channels of rad-hard CMOS devices due to electron and gamma-ray irradiation. Room-temperature annealing results in a positive shift in the threshold potential far beyond its initial value. The slope of the annealing curve immediately after irradiation was found to depend strongly on the gate bias applied during irradiation. Some dependence was also observed on the electron dose rate. No clear dependence on energy and shielding over a delidded device was observed. The threshold shift is probably due to electron trapping at the radiation-induced interface states and tunneling of electrons through the oxide-silicon energy barrier to fill the radiation-induced electron traps. A mathematical analysis, based on two parallel annealing kinetics, hole annealing and electron trapping, is applied to the data for various electron dose rates.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology

PubMed Central

Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

2016-01-01

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator’s high motion losses due to the possibility of their ‘system-on-chip’ integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design’s applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications. PMID:27391136

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator

NASA Astrophysics Data System (ADS)

Xue, Han; Hua, Fan; Qi, Wei; Huazhong, Yang

2013-08-01

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range (SFDR) and low power successive approximation register analog to digital converter (SAR ADC) for the radio-frequency (RF) transceiver front-end, especially for wireless sensor network (WSN) applications. This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology, the ADC performs a peak SFDR of 55.32 dB and effective number of bits (ENOB) of 5.1 bit for 10 MS/s. At the sample rate of 20 MS/s and the Nyquist input frequency, the 47.39-dB SFDR and 4.6-ENOB are achieved. The differential nonlinearity (DNL) is less than 0.83 LSB and the integral nonlinearity (INL) is less than 0.82 LSB. The experimental results indicate that this SAR ADC consumes a total of 522 μW power and occupies 0.98 mm2.

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.

PubMed

Koppa, Santosh; Mohandesi, Manouchehr; John, Eugene

2016-12-01

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

Associations of rotational shift work and night shift status with hypertension: a systematic review and meta-analysis.

PubMed

Manohar, Sandhya; Thongprayoon, Charat; Cheungpasitporn, Wisit; Mao, Michael A; Herrmann, Sandra M

2017-10-01

The reported risks of hypertension (HTN) in rotating shift and night shift workers are controversial. The objective of this meta-analysis was to assess the association between shift work status and HTN. A literature search was performed using MEDLINE, EMBASE and Cochrane Database from inception through October 2016. Studies that reported odds ratios (OR) comparing the risk of HTN in shift workers were included. A prespecified subgroup analysis by rotating shift and night shift statuses were also performed. Pooled OR and 95% confidence interval (CI) were calculated using a random-effect, generic inverse variance method. The protocol for this study is registered with International Prospective Register of Systematic Reviews; no. CRD42016051843. Twenty-seven observational studies (nine cohort and 18 cross-sectional studies) with a total of 394 793 individuals were enrolled. The pooled ORs of HTN in shift workers in cohort and cross-sectional studies were 1.31 (95% CI, 1.07-1.60) and 1.10 (95% CI, 1.00-1.20), respectively. When meta-analysis was restricted only to cohort studies in rotating shift, the pooled OR of HTN in rotating shift workers was 1.34 (95% CI, 1.08-1.67). The data regarding night shift and HTN in cohort studies was limited. The pooled OR of HTN in night shift workers in cross-sectional studies was 1.07 (95% CI, 0.85-1.35). Based on the findings of our meta-analysis, shiftwork status may play an important role in HTN, as there is a significant association between rotating shift work and HTN. However, there is no significant association between night shift status and risk of HTN.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

NASA Astrophysics Data System (ADS)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

In-line phase shift tomosynthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hammonds, Jeffrey C.; Price, Ronald R.; Pickens, David R.

2013-08-15

Purpose: The purpose of this work is to (1) demonstrate laboratory measurements of phase shift images derived from in-line phase-contrast radiographs using the attenuation-partition based algorithm (APBA) of Yan et al.[Opt. Express 18(15), 16074–16089 (2010)], (2) verify that the APBA reconstructed images obey the linearity principle, and (3) reconstruct tomosynthesis phase shift images from a collection of angularly sampled planar phase shift images.Methods: An unmodified, commercially available cabinet x-ray system (Faxitron LX-60) was used in this experiment. This system contains a tungsten anode x-ray tube with a nominal focal spot size of 10 μm. The digital detector uses CsI/CMOS withmore » a pixel size of 50 × 50 μm. The phantoms used consisted of one acrylic plate, two polystyrene plates, and a habanero pepper. Tomosynthesis images were reconstructed from 51 images acquired over a ±25° arc. All phase shift images were reconstructed using the APBA.Results: Image contrast derived from the planar phase shift image of an acrylic plate of uniform thickness exceeded the contrast of the traditional attenuation image by an approximate factor of two. Comparison of the planar phase shift images from a single, uniform thickness polystyrene plate with two polystyrene plates demonstrated an approximate linearity of the estimated phase shift with plate thickness (−1600 rad vs −2970 rad). Tomographic phase shift images of the habanero pepper exhibited acceptable spatial resolution and contrast comparable to the corresponding attenuation image.Conclusions: This work demonstrated the feasibility of laboratory-based phase shift tomosynthesis and suggests that phase shift imaging could potentially provide a new imaging biomarker. Further investigation will be needed to determine if phase shift contrast will be able to provide new tissue contrast information or improved clinical performance.« less

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Optical design of microlens array for CMOS image sensors

NASA Astrophysics Data System (ADS)

Zhang, Rongzhu; Lai, Liping

2016-10-01

The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

Wives' Shift Work Schedules and Husbands' and Wives' Well-Being in Dual-Earner Couples with Children: A within-Couple Analysis

ERIC Educational Resources Information Center

Chait Barnett, Rosalind; Gareis, Karen C.; Brennan, Robert T.

2008-01-01

In a sample of 55 dual-earner families with children aged 8 to 14 in which the mothers are registered nurses regularly working either day shifts (typically 7:00 a.m. to 3:00 p.m.) or evening shifts (typically 3:00 p.m. to 11:00 p.m.), we estimated the within-couple relationship between the wife's work variables (i.e., work shift, work hours, and…

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

Multiplane and Spectrally-Resolved Single Molecule Localization Microscopy with Industrial Grade CMOS cameras.

PubMed

Babcock, Hazen P

2018-01-29

This work explores the use of industrial grade CMOS cameras for single molecule localization microscopy (SMLM). We show that industrial grade CMOS cameras approach the performance of scientific grade CMOS cameras at a fraction of the cost. This makes it more economically feasible to construct high-performance imaging systems with multiple cameras that are capable of a diversity of applications. In particular we demonstrate the use of industrial CMOS cameras for biplane, multiplane and spectrally resolved SMLM. We also provide open-source software for simultaneous control of multiple CMOS cameras and for the reduction of the movies that are acquired to super-resolution images.

Time Difference Amplifier with Robust Gain Using Closed-Loop Control

NASA Astrophysics Data System (ADS)

Nakura, Toru; Mandai, Shingo; Ikeda, Makoto; Asada, Kunihiro

This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Chan-Shan; Chemical Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720; Tang, Tsung-Ta

Indium Tin Oxide (ITO) nanowhiskers (NWhs) obliquely evaporated by electron-beam glancing-angle deposition can serve simultaneously as transparent electrodes and alignment layer for liquid crystal (LC) devices in the terahertz (THz) frequency range. To demonstrate, we constructed a THz LC phase shifter with ITO NWhs. Phase shift exceeding π/2 at 1.0 THz was achieved in a ∼517 μm-thick cell. The phase shifter exhibits high transmittance (∼78%). The driving voltage required for quarter-wave operation is as low as 5.66 V (rms), compatible with complementary metal-oxide-semiconductor (CMOS) and thin-film transistor (TFT) technologies.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

NASA Astrophysics Data System (ADS)

Maity, H.; Biswas, A.; Bhattacharjee, A. K.; Pal, A.

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Pseudo-random dynamic address configuration (PRDAC) algorithm for mobile ad hoc networks

NASA Astrophysics Data System (ADS)

Wu, Shaochuan; Tan, Xuezhi

2007-11-01

By analyzing all kinds of address configuration algorithms, this paper provides a new pseudo-random dynamic address configuration (PRDAC) algorithm for mobile ad hoc networks. Based on PRDAC, the first node that initials this network randomly chooses a nonlinear shift register that can generates an m-sequence. When another node joins this network, the initial node will act as an IP address configuration sever to compute an IP address according to this nonlinear shift register, and then allocates this address and tell the generator polynomial of this shift register to this new node. By this means, when other node joins this network, any node that has obtained an IP address can act as a server to allocate address to this new node. PRDAC can also efficiently avoid IP conflicts and deal with network partition and merge as same as prophet address (PA) allocation and dynamic configuration and distribution protocol (DCDP). Furthermore, PRDAC has less algorithm complexity, less computational complexity and more sufficient assumption than PA. In addition, PRDAC radically avoids address conflicts and maximizes the utilization rate of IP addresses. Analysis and simulation results show that PRDAC has rapid convergence, low overhead and immune from topological structures.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Present and Future Supply of Registered Nurses.

ERIC Educational Resources Information Center

Altman, Stuart H.

During the 1960's, nursing education shifted dramatically away from hospital-operated diploma schools toward associate degree and baccalaureate programs. This report examines the nature of this shift in training and its anticipated impact on future supply. Other important factors affecting the future supply of nurses are analyzed, including the…

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio... underlying non-IO CMOs, and that the principal on each underlying PO CMO should decline at the same rate as...

All-CMOS night vision viewer with integrated microdisplay

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Sedki, Amor; André, Nicolas; Kilchytska, Valéria; Gérard, Pierre; Ali, Zeeshan; Udrea, Florin; Flandre, Denis

2018-01-01

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Impulse radio ultra wideband wireless transmission of dopamine concentration levels recorded by fast-scan cyclic voltammetry.

PubMed

Ebrazeh, Ali; Bozorgzadeh, Bardia; Mohseni, Pedram

2015-01-01

This paper demonstrates the feasibility of utilizing impulse radio ultra wideband (IR-UWB) signaling technique for reliable, wireless transmission of dopamine concentration levels recorded by fast-scan cyclic voltammetry (FSCV) at a carbon-fiber microelectrode (CFM) to address the problem of elevated data rates in high-channel-count neurochemical monitoring. Utilizing an FSCV-sensing chip fabricated in AMS 0.35μm 2P/4M CMOS, a 3-5-GHz, IR-UWB transceiver (TRX) chip fabricated in TSMC 90nm 1P/9M RF CMOS, and two off-chip, miniature, UWB antennae, wireless transfer of pseudo-random binary sequence (PRBS) data at 50Mbps over a distance of <;1m is first shown with bit-error rates (BER) <; 10(-3). Further, IR-UWB wireless transmission of dopamine concentration levels prerecorded with FSCV at a CFM during flow injection analysis (FIA) is also demonstrated with transmitter (TX) power dissipation of only ~4.4μW from 1.2V, representing two orders of magnitude reduction in TX power consumption compared to that of a conventional frequency-shift-keyed (FSK) link operating at ~433MHz.

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

PubMed

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Nurses' shift length and overtime working in 12 European countries: the association with perceived quality of care and patient safety.

PubMed

Griffiths, Peter; Dall'Ora, Chiara; Simon, Michael; Ball, Jane; Lindqvist, Rikard; Rafferty, Anne-Marie; Schoonhoven, Lisette; Tishelman, Carol; Aiken, Linda H

2014-11-01

Despite concerns as to whether nurses can perform reliably and effectively when working longer shifts, a pattern of two 12- to 13-hour shifts per day is becoming common in many hospitals to reduce shift to shift handovers, staffing overlap, and hence costs. To describe shift patterns of European nurses and investigate whether shift length and working beyond contracted hours (overtime) is associated with nurse-reported care quality, safety, and care left undone. Cross-sectional survey of 31,627 registered nurses in general medical/surgical units within 488 hospitals across 12 European countries. A total of 50% of nurses worked shifts of ≤ 8 hours, but 15% worked ≥ 12 hours. Typical shift length varied between countries and within some countries. Nurses working for ≥ 12 hours were more likely to report poor or failing patient safety [odds ratio (OR)=1.41; 95% confidence interval (CI), 1.13-1.76], poor/fair quality of care (OR=1.30; 95% CI, 1.10-1.53), and more care activities left undone (RR=1.13; 95% CI, 1.09-1.16). Working overtime was also associated with reports of poor or failing patient safety (OR=1.67; 95% CI, 1.51-1.86), poor/fair quality of care (OR=1.32; 95% CI, 1.23-1.42), and more care left undone (RR=1.29; 95% CI, 1.27-1.31). European registered nurses working shifts of ≥ 12 hours and those working overtime report lower quality and safety and more care left undone. Policies to adopt a 12-hour nursing shift pattern should proceed with caution. Use of overtime working to mitigate staffing shortages or increase flexibility may also incur additional risk to quality.

Nurses’ Shift Length and Overtime Working in 12 European Countries

PubMed Central

Dall’Ora, Chiara; Simon, Michael; Ball, Jane; Lindqvist, Rikard; Rafferty, Anne-Marie; Schoonhoven, Lisette; Tishelman, Carol; Aiken, Linda H.

2014-01-01

Background: Despite concerns as to whether nurses can perform reliably and effectively when working longer shifts, a pattern of two 12- to 13-hour shifts per day is becoming common in many hospitals to reduce shift to shift handovers, staffing overlap, and hence costs. Objectives: To describe shift patterns of European nurses and investigate whether shift length and working beyond contracted hours (overtime) is associated with nurse-reported care quality, safety, and care left undone. Methods: Cross-sectional survey of 31,627 registered nurses in general medical/surgical units within 488 hospitals across 12 European countries. Results: A total of 50% of nurses worked shifts of ≤8 hours, but 15% worked ≥12 hours. Typical shift length varied between countries and within some countries. Nurses working for ≥12 hours were more likely to report poor or failing patient safety [odds ratio (OR)=1.41; 95% confidence interval (CI), 1.13–1.76], poor/fair quality of care (OR=1.30; 95% CI, 1.10–1.53), and more care activities left undone (RR=1.13; 95% CI, 1.09–1.16). Working overtime was also associated with reports of poor or failing patient safety (OR=1.67; 95% CI, 1.51–1.86), poor/fair quality of care (OR=1.32; 95% CI, 1.23–1.42), and more care left undone (RR=1.29; 95% CI, 1.27–1.31). Conclusions: European registered nurses working shifts of ≥12 hours and those working overtime report lower quality and safety and more care left undone. Policies to adopt a 12-hour nursing shift pattern should proceed with caution. Use of overtime working to mitigate staffing shortages or increase flexibility may also incur additional risk to quality. PMID:25226543

The Comfort Measures Order Set at a Tertiary Care Academic Hospital: Is There a Comparable Difference in End-of-Life Care Between Patients Dying in Acute Care When CMOS Is Utilized?

PubMed

Lau, Christine; Stilos, Kalli; Nowell, Allyson; Lau, Fanchea; Moore, Jennifer; Wynnychuk, Lesia

2018-04-01

Standardized protocols have been previously shown to be helpful in managing end-of-life (EOL) care in hospital. The comfort measures order set (CMOS), a standardized framework for assessing imminently dying patients' symptoms and needs, was implemented at a tertiary academic hospital. We assessed whether there were comparable differences in the care of a dying patient when the CMOS was utilized and when it was not. A retrospective chart review was completed on patients admitted under oncology and general internal medicine, who were referred to the inpatient palliative care team for "EOL care" between February 2015 and March 2016. Of 83 patients, 56 (67%) received intiation of the CMOS and 27 (33%) did not for EOL care. There was significant involvement of spiritual care with the CMOS (66%), as compared to the group without CMOS (19%), P < .05. The use of CMOS resulted in 1.7 adjustments to symptom management per patient by palliative care, which was significantly less than the number of symptom management adjustments per patient when CMOS was not used (3.3), P < .05. However, initiating CMOS did not result in a signficant difference in patient distress around the time of death ( P = .11). Dyspnea was the most frequently identified symptom causing distress in actively dying patients. Implementation of the CMOS is helpful in providing a foundation to a comfort approach in imminently dying patients. However, more education on its utility as a framework for EOL care and assessment across the organization is still required.

Advanced investigation of two-phase charge-coupled devices

NASA Technical Reports Server (NTRS)

Kosonocky, W. F.; Carnes, J. E.

1973-01-01

The performance of experimental two phase, charge-coupled shift registers constructed using polysilicon gates overlapped by aluminum gates was studied. Shift registers with 64, 128, and 500 stages were built and operated. Devices were operated at the maximum clock frequency of 20 MHz. Loss per transfer of less than .0001 was demonstrated for fat zero operation. The effect upon transfer efficiency of various structural and materials parameters was investigated including substrate orientation, resistivity, and conductivity type; channel width and channel length; and method of channel confinement. Operation of the devices with and without fat zero was studied as well as operation in the complete charge transfer mode and the bias charge, or bucket brigade mode.

Novel latch for adiabatic quantum-flux-parametron logic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takeuchi, Naoki, E-mail: takeuchi-naoki-kx@ynu.jp; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2014-03-14

We herein propose the quantum-flux-latch (QFL) as a novel latch for adiabatic quantum-flux-parametron (AQFP) logic. A QFL is very compact and compatible with AQFP logic gates and can be read out in one clock cycle. Simulation results revealed that the QFL operates at 5 GHz with wide parameter margins of more than ±22%. The calculated energy dissipation was only ∼0.1 aJ/bit, which yields a small energy delay product of 20 aJ·ps. We also designed shift registers using QFLs to demonstrate more complex circuits with QFLs. Finally, we experimentally demonstrated correct operations of the QFL and a 1-bit shift register (a D flip-flop)

Cargo Movement Operations System (CMOS). Software Test Description

DTIC Science & Technology

1990-10-28

resulting in errors in paragraph numbers and titles. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...location to test the update of the truck manifest. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

CMOS image sensors: State-of-the-art

NASA Astrophysics Data System (ADS)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seco, Joao; Depauw, Nicolas

2011-02-15

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissuemore » contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.« less

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Cargo Movement Operations System (CMOS) System Segment Design Document (Draft) Increment II

DTIC Science & Technology

1990-05-02

and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SSDD-0003 PROGRAM...CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR

High power-efficient asynchronous SAR ADC for IoT devices

NASA Astrophysics Data System (ADS)

Zhang, Beichen; Yao, Bingbing; Liu, Liyuan; Liu, Jian; Wu, Nanjian

2017-10-01

This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed. The prototype was fabricated using 65 nm standard CMOS technology. At a 1.2-V supply and 100 MS/s, the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB. The ADC core consumes only 3.1 mW, resulting in a figure of merit (FOM) of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm2.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Multi-band infrared camera systems

NASA Astrophysics Data System (ADS)

Davis, Tim; Lang, Frank; Sinneger, Joe; Stabile, Paul; Tower, John

1994-12-01

The program resulted in an IR camera system that utilizes a unique MOS addressable focal plane array (FPA) with full TV resolution, electronic control capability, and windowing capability. Two systems were delivered, each with two different camera heads: a Stirling-cooled 3-5 micron band head and a liquid nitrogen-cooled, filter-wheel-based, 1.5-5 micron band head. Signal processing features include averaging up to 16 frames, flexible compensation modes, gain and offset control, and real-time dither. The primary digital interface is a Hewlett-Packard standard GPID (IEEE-488) port that is used to upload and download data. The FPA employs an X-Y addressed PtSi photodiode array, CMOS horizontal and vertical scan registers, horizontal signal line (HSL) buffers followed by a high-gain preamplifier and a depletion NMOS output amplifier. The 640 x 480 MOS X-Y addressed FPA has a high degree of flexibility in operational modes. By changing the digital data pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or noninterlaced format. The thermal sensitivity performance of the second system's Stirling-cooled head was the best of the systems produced.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Integrated phased array for wide-angle beam steering.

PubMed

Yaacobi, Ami; Sun, Jie; Moresco, Michele; Leake, Gerald; Coolbaugh, Douglas; Watts, Michael R

2014-08-01

We demonstrate an on-chip optical phased array fabricated in a CMOS compatible process with continuous, fast (100 kHz), wide-angle (51°) beam-steering suitable for applications such as low-cost LIDAR systems. The device demonstrates the largest (51°) beam-steering and beam-spacing to date while providing the ability to steer continuously over the entire range. Continuous steering is enabled by a cascaded phase shifting architecture utilizing, low power and small footprint, thermo-optic phase shifters. We demonstrate these results in the telecom C-band, but the same design can easily be adjusted for any wavelength between 1.2 and 3.5 μm.

Cargo Movement Operations System (CMOS) Requirements Traceability Matrix, Version 3 Increment II

DTIC Science & Technology

1990-12-17

above SCs should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...These two documents should be in agreement with each other. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...completeness, they should be documented. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

Shifting Codes: Education or Regulation? Trainee Teachers and the Code of Conduct and Practice in England

ERIC Educational Resources Information Center

Spendlove, David; Barton, Amanda; Hallett, Fiona; Shortt, Damien

2012-01-01

In 2009, the General Teaching Council for England (GTCE) introduced a revised Code of Conduct and Practice (2009) for registered teachers. The code also applies to all trainee teachers who are provisionally registered with the GTCE and who could be liable to a charge of misconduct during their periods of teaching practice. This paper presents the…

Cargo Movement Operations System (CMOS) Final Software User’s Manual

DTIC Science & Technology

1990-12-20

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ I COMMENT STATUS: OPEN...is correct. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS CO1MENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...RATIONALE: .."DA001041" is in the SUM but not in the SDD. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Ionizing doses and displacement damage testing of COTS CMOS imagers

NASA Astrophysics Data System (ADS)

Bernard, Frédéric; Petit, Sophie; Courtade, Sophie

2017-11-01

CMOS sensors begin to be a credible alternative to CCD sensors in some space missions. However, technology evolution of CMOS sensors is much faster than CCD one's. So a continuous technology evaluation is needed for CMOS imagers. Many of commercial COTS (Components Off The Shelf) CMOS sensors use organic filters, micro-lenses and non rad-hard technologies. An evaluation of the possibilities offered by such technologies is interesting before any custom development. This can be obtained by testing commercial COTS imagers. This article will present electro-optical performances evolution of off the shelves CMOS imagers after Ionizing Doses until 50kRad(Si) and Displacement Damage environment tests (until 1011 p/cm2 at 50 MeV). Dark current level and non uniformity evolutions are compared and discussed. Relative spectral response measurement and associated evolution with irradiation will also be presented and discussed. Tests have been performed on CNES detection benches.

Improved diagonal queue medical image steganography using Chaos theory, LFSR, and Rabin cryptosystem.

PubMed

Jain, Mamta; Kumar, Anil; Choudhary, Rishabh Charan

2017-06-01

In this article, we have proposed an improved diagonal queue medical image steganography for patient secret medical data transmission using chaotic standard map, linear feedback shift register, and Rabin cryptosystem, for improvement of previous technique (Jain and Lenka in Springer Brain Inform 3:39-51, 2016). The proposed algorithm comprises four stages, generation of pseudo-random sequences (pseudo-random sequences are generated by linear feedback shift register and standard chaotic map), permutation and XORing using pseudo-random sequences, encryption using Rabin cryptosystem, and steganography using the improved diagonal queues. Security analysis has been carried out. Performance analysis is observed using MSE, PSNR, maximum embedding capacity, as well as by histogram analysis between various Brain disease stego and cover images.

A 15-year prospective study of shift work and disability pension

PubMed Central

Tüchsen, F; Christensen, K B; Lund, T; Feveile, H

2008-01-01

Objective: To estimate the hazard ratio for disability pension associated with shift work. Methods: Cohorts of shift and day workers were identified in three waves of the Danish Work Environment Cohort Study and followed up for incidence of disability pension in a national register of social transfer payment. A total of 3980 female and 4025 male employees were included in the cohorts. Information about shift work status, age, smoking habits, body mass index and ergonomic work environment were updated according to responses in subsequent waves of the survey when possible. Respondents reporting shift work were classified as shift workers in the following waves as well. Respondents were followed in the register from the time of first interview and were censored at the time of their 60th birthday, emigration, death or end of follow-up (18 June 2006). The authors used the Cox proportional hazards model to estimate hazard ratios for incidence of disability pension and 95% confidence intervals. Results: The authors observed 253 new disability pensions among women and 173 among men during 56 903 and 57 886 person-years at risk respectively, Among women, shift work predicted disability after adjustment for age, general health and socioeconomic status HR 1.39 (95% CI 1.07 to 1.82). After further adjustment for body mass index, smoking habits, socioeconomic status and ergonomic exposures the association remained statistically significant HR 1.34 (95% CI 1.02 to 1.75). Shift work was not associated with disability among men. Conclusion: Shift work might be moderately associated with disability pension among women; however, more powerful studies are needed to establish the possible association. PMID:18198201

Intraoperative colon mucosal oxygen saturation during aortic surgery.

PubMed

Lee, Eugene S; Bass, Arie; Arko, Frank R; Heikkinen, Maarit; Harris, E John; Zarins, Christopher K; van der Starre, Pieter; Olcott, Cornelius

2006-11-01

Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the surgical procedure. Continuous CMOS, buccal mucosal oxygen saturation, systemic mean arterial pressure, heart rate, pulse oximetry, and pivotal intra-operative events were collected. Endovascular aneurysm repair (EVAR) was performed in 20 and open repair in 5 patients with a mean age of 75 +/- 10 (+/-SE) years. CMOS reliably decreased in EVAR from a baseline of 56% +/- 8% to 26 +/- 17% (P < 0.0001) during infrarenal aortic balloon occlusion and femoral arterial sheath placement. CMOS similarly decreased during open repair from 56% +/- 9% to 15 +/- 19% (P < 0.0001) when the infrarenal aorta and iliac arteries were clamped. When aortic circulation was restored in both EVAR and open surgery, CMOS returned to baseline values 56.5 +/- 10% (P = 0.81). Mean recovery time in CMOS after an aortic intervention was 6.4 +/- 3.3 min. Simultaneous buccal mucosal oxygen saturation was stable (82% +/- 6%) during aortic manipulation but would fall significantly during active bleeding. There were no device related CMOS measurement complications. Intra-operative CMOS is a sensitive measure of colon ischemia where intraoperative events correlated well with changes in mucosal oxygen saturation. Transient changes demonstrate no problem. However, persistently low CMOS suggests colon ischemia, thus providing an opportunity to revascularize the inferior mesenteric artery or hypogastric arteries to prevent colon infarction.

The challenge of sCMOS image sensor technology to EMCCD

NASA Astrophysics Data System (ADS)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Examining Harasim's Online Collaborative Learning Theory for Nursing Education

ERIC Educational Resources Information Center

Breen, Henny

2013-01-01

Online nursing education has been evolving at a rapid pace as it is recognized as offering the flexibility needed for practicing associate degree (ADN) and diploma prepared Registered Nurses to return to school to earn their BSN. At the same time, there is a paradigm shift in how nursing education is delivered. The focus has shifted from content…

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

NASA Technical Reports Server (NTRS)

Lee, C.; Johnston, A.

1998-01-01

This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Bi-stable vocal fold adduction: a mechanism of modal-falsetto register shifts and mixed registration.

PubMed

Titze, Ingo R

2014-04-01

The origin of vocal registers has generally been attributed to differential activation of cricothyroid and thyroarytenoid muscles in the larynx. Register shifts, however, have also been shown to be affected by glottal pressures exerted on vocal fold surfaces, which can change with loudness, pitch, and vowel. Here it is shown computationally and with empirical data that intraglottal pressures can change abruptly when glottal adductory geometry is changed relatively smoothly from convergent to divergent. An intermediate shape between large convergence and large divergence, namely, a nearly rectangular glottal shape with almost parallel vocal fold surfaces, is associated with mixed registration. It can be less stable than either of the highly angular shapes unless transglottal pressure is reduced and upper stiffness of vocal fold tissues is balanced with lower stiffness. This intermediate state of adduction is desirable because it leads to a low phonation threshold pressure with moderate vocal fold collision. Achieving mixed registration consistently across wide ranges of F0, lung pressure, and vocal tract shapes appears to be a balancing act of coordinating laryngeal muscle activation with vocal tract pressures. Surprisingly, a large transglottal pressure is not facilitative in this process, exacerbating the bi-stable condition and the associated register contrast.

Comparison of nurse staffing based on changes in unit-level workload associated with patient churn.

PubMed

Hughes, Ronda G; Bobay, Kathleen L; Jolly, Nicholas A; Suby, Chrysmarie

2015-04-01

This analysis compares the staffing implications of three measures of nurse staffing requirements: midnight census, turnover adjustment based on length of stay, and volume of admissions, discharges and transfers. Midnight census is commonly used to determine registered nurse staffing. Unit-level workload increases with patient churn, the movement of patients in and out of the nursing unit. Failure to account for patient churn in staffing allocation impacts nurse workload and may result in adverse patient outcomes. Secondary data analysis of unit-level data from 32 hospitals, where nursing units are grouped into three unit-type categories: intensive care, intermediate care, and medical surgical. Midnight census alone did not account adequately for registered nurse workload intensity associated with patient churn. On average, units were staffed with a mixture of registered nurses and other nursing staff not always to budgeted levels. Adjusting for patient churn increases nurse staffing across all units and shifts. Use of the discharges and transfers adjustment to midnight census may be useful in adjusting RN staffing on a shift basis to account for patient churn. Nurse managers should understand the implications to nurse workload of various methods of calculating registered nurse staff requirements. © 2013 John Wiley & Sons Ltd.

Bi-stable vocal fold adduction: A mechanism of modal-falsetto register shifts and mixed registration

PubMed Central

Titze, Ingo R.

2014-01-01

The origin of vocal registers has generally been attributed to differential activation of cricothyroid and thyroarytenoid muscles in the larynx. Register shifts, however, have also been shown to be affected by glottal pressures exerted on vocal fold surfaces, which can change with loudness, pitch, and vowel. Here it is shown computationally and with empirical data that intraglottal pressures can change abruptly when glottal adductory geometry is changed relatively smoothly from convergent to divergent. An intermediate shape between large convergence and large divergence, namely, a nearly rectangular glottal shape with almost parallel vocal fold surfaces, is associated with mixed registration. It can be less stable than either of the highly angular shapes unless transglottal pressure is reduced and upper stiffness of vocal fold tissues is balanced with lower stiffness. This intermediate state of adduction is desirable because it leads to a low phonation threshold pressure with moderate vocal fold collision. Achieving mixed registration consistently across wide ranges of F0, lung pressure, and vocal tract shapes appears to be a balancing act of coordinating laryngeal muscle activation with vocal tract pressures. Surprisingly, a large transglottal pressure is not facilitative in this process, exacerbating the bi-stable condition and the associated register contrast. PMID:25235006

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Spatial filtering velocimeter for vehicle navigation with extended measurement range

NASA Astrophysics Data System (ADS)

He, Xin; Zhou, Jian; Nie, Xiaoming; Long, Xingwu

2015-05-01

The idea of using spatial filtering velocimeter is proposed to provide accurate velocity information for vehicle autonomous navigation system. The presented spatial filtering velocimeter is based on a CMOS linear image sensor. The limited frame rate restricts high speed measurement of the vehicle. To extend measurement range of the velocimeter, a method of frequency shifting is put forward. Theoretical analysis shows that the frequency of output signal can be reduced and the measurement range can be doubled by this method when the shifting direction is set the same with that of image velocity. The approach of fast Fourier transform (FFT) is employed to obtain the power spectra of the spatially filtered signals. Because of limited frequency resolution of FFT, a frequency spectrum correction algorithm, called energy centrobaric correction, is used to improve the frequency resolution. The correction accuracy energy centrobaric correction is analyzed. Experiments are carried out to measure the moving surface of a conveyor belt. The experimental results show that the maximum measurable velocity is about 800deg/s without frequency shifting, 1600deg/s with frequency shifting, when the frame rate of the image is about 8117 Hz. Therefore, the measurement range is doubled by the method of frequency shifting. Furthermore, experiments were carried out to measure the vehicle velocity simultaneously using both the designed SFV and a laser Doppler velocimeter (LDV). The measurement results of the presented SFV are coincident with that of the LDV, but with bigger fluctuation. Therefore, it has the potential of application to vehicular autonomous navigation.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Fundamental performance differences between CMOS and CCD imagers, part IV

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

The Nightingale study: rationale, study design and baseline characteristics of a prospective cohort study on shift work and breast cancer risk among nurses.

PubMed

Pijpe, Anouk; Slottje, Pauline; van Pelt, Cres; Stehmann, Floor; Kromhout, Hans; van Leeuwen, Flora E; Vermeulen, Roel C H; Rookus, Matti A

2014-01-29

Evidence for the carcinogenicity of shift work in humans is limited because of significant heterogeneity of the results, thus more in-depth research in needed. The Nightingale Study is a nationwide prospective cohort study on occupational exposures and risks of chronic diseases among female nurses and focuses on the potential association between shift work and risk of breast cancer. The study design, methods, and baseline characteristics of the cohort are described. The source population for the cohort comprised 18 to 65 year old women who were registered as having completed training to be a nurse in the nationwide register for healthcare professionals in the Netherlands. Eligible women were invited to complete a web-based questionnaire including full job history, a detailed section on all domains of shift work (shift system, cumulative exposure, and shift intensity) and potential confounding factors, and an informed consent form for linkage with national (disease) registries. Women were also asked to donate toenail clippings as a source of DNA for genetic analyses. Between October 6, 2011 and February 1, 2012, 31% of the 192,931 women who were invited to participate completed the questionnaire, yielding a sample size of 59,947 cohort members. The mean age of the participants was 46.9 year (standard deviation 11.0 years). Toenail clippings were provided by 23,439 participants (39%). Results from the Nightingale Study will contribute to the scientific evidence of potential shift work-related health risks among nurses and will help develop preventive measures and policy aimed at reducing these risks.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

Shift work and hypertension: Prevalence and analysis of disease pathways in a German car manufacturing company.

PubMed

Ohlander, Johan; Keskin, Mekail-Cem; Stork, Joachim; Radon, Katja

2015-05-01

Hypertension and cardiovascular disease (CVD) may share a similar pathophysiology. Despite shift workers' CVD excess risk, studies on shift work and hypertension are inconclusive. Blood pressure and shift status for 25,343 autoworkers were obtained from medical check-ups and company registers. Cross-sectional associations modeling the total effect from shift work (day shifts, shift work without nights, rotating shift work with nights, and night shifts) on hypertension were assessed. By sequential adjustments, the influence of behavioral, psychosocial, and physiological factors on the total effect was examined, with subsequent mediation and moderation analyses. Adjusted for confounders, shift work without nights (vs. day shifts) was significantly associated with hypertension (OR 1.15, 95%CI 1.02-1.30). The total effect was mediated by BMI, physical inactivity, and sleep disorders. No moderation of the total effect by behaviors was found. The association between shift work and hypertension seems mainly attributable to behavioral mechanisms. © 2015 Wiley Periodicals, Inc.

12 CFR 703.16 - Prohibited investments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... credit union may invest in and hold exchangeable collateralized mortgage obligations (exchangeable CMOs) representing beneficial ownership interests in one or more interest-only classes of a CMO (IO CMOs) or principal-only classes of a CMO (PO CMOs), but only if: (i) At the time of purchase, the ratio of the market...

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Cargo Movement Operations System (CMOS). Final Software Requirements Specification, (Applications CSCI), Increment II

DTIC Science & Technology

1991-01-29

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL Nt3MBFR: SRS1-0002 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM...floppy diskette interface with CMOS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES ( 3 NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Tests of commercial colour CMOS cameras for astronomical applications

NASA Astrophysics Data System (ADS)

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

NASA Astrophysics Data System (ADS)

de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

2008-05-01

CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

High-precision register error control using active-motion-based roller in roll-to-roll gravure printing

NASA Astrophysics Data System (ADS)

Jung, Hoeryong; Nguyen, Ho Anh Duc; Choi, Jaeho; Yim, Hongsik; Shin, Kee-Hyun

2018-05-01

The roll-to-roll (R2R) gravure printing method is increasingly being utilized to fabricate electronic devices such as organic thin-film transistor (OTFT), radio-frequency identification (RFID) tags, and flexible PCB owing to its characteristics of high throughput and large area. High precision registration is crucial to satisfy the demand for device miniaturization, the improvement of resolution and accuracy. This paper presents a novel register control method that uses an active motion-based roller (AMBR) to reduce register error in R2R gravure printing. Instead of shifting the phase of the downstream printing roller, which leads to undesired tension disturbance, the 1 degree-of-freedom (1-DOF) mechanical device AMBR is used to compensate for web elongation by controlling its motion according to the register error. The performance of the proposed control method is verified through simulations and experiments, and the results show that the proposed register control method using the AMBR could maintain a register error under ±15 µm.

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

PubMed

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

The $500 Million Question: Can Charter Management Organizations Deliver Quality Education at Scale?

ERIC Educational Resources Information Center

Hall, Kevin; Lake, Robin

2011-01-01

Charter school management organizations (CMOs) have emerged as a popular means for bringing charter schooling to scale. Advocates credit CMOs with delivering a coherent model of charter schooling to a growing number of children across numerous sites. Skeptics have wondered whether CMOs constitute an effective management approach, whether they…

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and..., the sale for importation, and the sale within the United States after importation of certain CMOS image sensors and products containing same by reason of infringement of certain claims of U.S. Patent No...

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Huang, Shaoyan; Liu, Minbo

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic rangemore » (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.« less

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

640 X 480 MOS PtSi IR sensor

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1991-12-01

The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Carbon Nanotube Integration with a CMOS Process

PubMed Central

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

PubMed Central

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

PubMed Central

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-01-01

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction.

PubMed

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-07-14

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

Cargo Movement Operations System (CMOS) Interface Requirements Specification (Draft). Increment II

DTIC Science & Technology

1990-05-17

NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ 3 CLOSED [ ] ORIGINATOR CONTROL NUMBER: IRS1-0003 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM DISCREPANCY WORKSHEET CDRL NUMBER: A004-05 DATE: 05/17/90 ORIGINATOR NAME: Ronald J. Lacour OFFICE SYMBOL: SAIC TELEPHONE NUMBER: 272-2999 SUBSTANTIVE: X EDITORIAL: PAGE NUMBER: 9 PARA NUMBER: 3.2 c. COMMENT OR RECOMMENDED CHANGE: Change line 2 to read, "CMOS IRD/SBSS-01 and SBSS-03." Move "CMOS IRD/SBSS-02" to paragraph 3.3 c. RATIONALE: The CMOS IRD/SBSS-02 covers the Shipment Suspense

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

The Nightingale study: rationale, study design and baseline characteristics of a prospective cohort study on shift work and breast cancer risk among nurses

PubMed Central

2014-01-01

Background Evidence for the carcinogenicity of shift work in humans is limited because of significant heterogeneity of the results, thus more in-depth research in needed. The Nightingale Study is a nationwide prospective cohort study on occupational exposures and risks of chronic diseases among female nurses and focuses on the potential association between shift work and risk of breast cancer. The study design, methods, and baseline characteristics of the cohort are described. Methods/Design The source population for the cohort comprised 18 to 65 year old women who were registered as having completed training to be a nurse in the nationwide register for healthcare professionals in the Netherlands. Eligible women were invited to complete a web-based questionnaire including full job history, a detailed section on all domains of shift work (shift system, cumulative exposure, and shift intensity) and potential confounding factors, and an informed consent form for linkage with national (disease) registries. Women were also asked to donate toenail clippings as a source of DNA for genetic analyses. Between October 6, 2011 and February 1, 2012, 31% of the 192,931 women who were invited to participate completed the questionnaire, yielding a sample size of 59,947 cohort members. The mean age of the participants was 46.9 year (standard deviation 11.0 years). Toenail clippings were provided by 23,439 participants (39%). Discussion Results from the Nightingale Study will contribute to the scientific evidence of potential shift work-related health risks among nurses and will help develop preventive measures and policy aimed at reducing these risks. PMID:24475944

LSI arrays for space stations

NASA Technical Reports Server (NTRS)

Gassaway, J. D.

1976-01-01

Two approaches have been taken to study CCD's and some of their fundamental limitations. First a numerical analysis approach has been developed to solve the coupled transport and Poisson's equation for a thorough analysis of charge transfer in a CCD structure. The approach is formulated by treating the minority carriers as a surface distribution at the Si-SiO2 interface and setting up coupled difference equations for the charge and the potential. The SOR method is proposed for solving the two dimensional Poisson's equation for the potential. Methods are suggested for handling the discontinuities to improve convergence. Second, CCD shift registers were fabricated with parameters which should allow complete charge transfer independent of the transfer electrode gap width. A test instrument was designed and constructed which can be used to test this, or any similar, three phase CCD shift register.

Cargo Movement Operations System (CMOS). Software Requirements Specification

DTIC Science & Technology

1990-03-12

was erroneously deleted. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...previous SRS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] 0 ORIGINATOR CONTROL NUMBER

Cargo Movement Operations System (CMOS). System Segment Specification, Updated, Increment II

DTIC Science & Technology

1990-05-02

CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ 3 COMMENT STATUS: OPEN [ ] CLOSED...ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL...the LAN. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

Design and simulation of multi-color infrared CMOS metamaterial absorbers

NASA Astrophysics Data System (ADS)

Cheng, Zhengxi; Chen, Yongping; Ma, Bin

2016-05-01

Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

A proposal for digital electro-optic switches with free-carrier dispersion effect and Goos-Hanchen shift in silicon-on-insulator waveguide corner mirror

NASA Astrophysics Data System (ADS)

Sun, DeGui

2013-09-01

In a silicon-on-insulator (SOI) waveguide corner mirror (WCM) structure, with the quantum process of a frustrated total internal reflection (FTIR) phenomenon and the time delay principle in the two-dimensional potential barrier tunneling process of a mass of particles, we derive an accurate physical model for the Goos-Hanchen (GH) shift of optical guided-mode in the FTIR process, and in principle match the GH shift jumping states with the independent guided-modes. Then, we propose and demonstrate a new regime of 1 × N digital optical switches with a matching state between the free-carrier dispersion (FCD) based refractive index modulation (RIM) of silicon to create a GH shift jumping function of a photonic signal at the reflecting interface and the independent guided-modes in the FTIR process, where a MOS-capacitor type electro-optic modulation regime is proposed and discussed to realize an effective FCD-based RIM. At the critical matching state, i.e., the incident of an optical beam is at the vicinity of Brewster angle in the WCM, a mini-change of refractive index of waveguide material can cause a great jump of GH shift along the FTIR reflecting interface, and further a 1 × N digital optical switching process could be realized. For a 350-500 nm single-mode rib waveguide made on the 220 nm CMOS-compatible SOI substrate and with the FCD effect based RIM of silicon crystal, a concentration variation of 1018-1019 cm-3 has caused a 0.5-2.5 μm GH shift of reflected beam, which is at 2-5 times of a mode-size and hence radically convinces an optical switching function with a 1 × 3-1 × 10 scale.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Design of CMOS imaging system based on FPGA

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

PubMed

Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig

2018-02-05

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

The heterogeneous integration of single-walled carbon nanotubes onto complementary metal oxide semiconductor circuitry for sensing applications.

PubMed

Chen, Chia-Ling; Agarwal, Vinay; Sonkusale, Sameer; Dokmeci, Mehmet R

2009-06-03

A simple methodology for integrating single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry is presented. The SWNTs were incorporated onto the CMOS chip as the feedback resistor of a two-stage Miller compensated operational amplifier utilizing dielectrophoretic assembly. The measured electrical properties from the integrated SWNTs yield ohmic behavior with a two-terminal resistance of approximately 37.5 kOmega and the measured small signal ac gain (-2) from the inverting amplifier confirmed successful integration of carbon nanotubes onto the CMOS circuitry. Furthermore, the temperature response of the SWNTs integrated onto CMOS circuitry has been measured and had a thermal coefficient of resistance (TCR) of -0.4% degrees C(-1). This methodology, demonstrated for the integration of SWNTs onto CMOS technology, is versatile, high yield and paves the way for the realization of novel miniature carbon-nanotube-based sensor systems.

SOI-CMOS Process for Monolithic, Radiation-Tolerant, Science-Grade Imagers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, George; Lee, Adam

In Phase I, Voxtel worked with Jazz and Sandia to document and simulate the processes necessary to implement a DH-BSI SOI CMOS imaging process. The development is based upon mature SOI CMOS process at both fabs, with the addition of only a few custom processing steps for integration and electrical interconnection of the fully-depleted photodetectors. In Phase I, Voxtel also characterized the Sandia process, including the CMOS7 design rules, and we developed the outline of a process option that included a “BOX etch”, that will permit a “detector in handle” SOI CMOS process to be developed The process flows weremore » developed in cooperation with both Jazz and Sandia process engineers, along with detailed TCAD modeling and testing of the photodiode array architectures. In addition, Voxtel tested the radiation performance of the Jazz’s CA18HJ process, using standard and circular-enclosed transistors.« less

A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

NASA Astrophysics Data System (ADS)

Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

2014-01-01

A CMOS image sensor with stacked photodiodes was fabricated using 0.18 µm mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

Computing in the presence of soft bit errors. [caused by single event upset on spacecraft

NASA Technical Reports Server (NTRS)

Rasmussen, R. D.

1984-01-01

It is shown that single-event-upsets (SEUs) due to cosmic rays are a significant source of single bit error in spacecraft computers. The physical mechanism of SEU, electron hole generation by means of Linear Energy Transfer (LET), it discussed with reference made to the results of a study of the environmental effects on computer systems of the Galileo spacecraft. Techniques for making software more tolerant of cosmic ray effects are considered, including: reducing the number of registers used by the software; continuity testing of variables; redundant execution of major procedures for error detection; and encoding state variables to detect single-bit changes. Attention is also given to design modifications which may reduce the cosmic ray exposure of on-board hardware. These modifications include: shielding components operating in LEO; removing low-power Schottky parts; and the use of CMOS diodes. The SEU parameters of different electronic components are listed in a table.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

PubMed Central

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-01-01

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors. PMID:28368355

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems.

PubMed

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-04-03

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

A Three-Step Resolution-Reconfigurable Hazardous Multi-Gas Sensor Interface for Wireless Air-Quality Monitoring Applications.

PubMed

Choi, Subin; Park, Kyeonghwan; Lee, Seungwook; Lim, Yeongjin; Oh, Byungjoo; Chae, Hee Young; Park, Chan Sam; Shin, Heugjoo; Kim, Jae Joon

2018-03-02

This paper presents a resolution-reconfigurable wide-range resistive sensor readout interface for wireless multi-gas monitoring applications that displays results on a smartphone. Three types of sensing resolutions were selected to minimize processing power consumption, and a dual-mode front-end structure was proposed to support the detection of a variety of hazardous gases with wide range of characteristic resistance. The readout integrated circuit (ROIC) was fabricated in a 0.18 μm CMOS process to provide three reconfigurable data conversions that correspond to a low-power resistance-to-digital converter (RDC), a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a 16-bit delta-sigma modulator. For functional feasibility, a wireless sensor system prototype that included in-house microelectromechanical (MEMS) sensing devices and commercial device products was manufactured and experimentally verified to detect a variety of hazardous gases.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Cargo Movement Operations System (CMOS). Software User’s Manual

DTIC Science & Technology

1990-06-27

RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SUM-0003 PROGRAM...3.1.11. RATIONALE: Clarity. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS). Software Design Document

DTIC Science & Technology

1990-04-29

order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT...inadvertently omitted from the table. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDDI-0005 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

Multiple-Event, Single-Photon Counting Imaging Sensor

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

2011-01-01

The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

A Review on Passive and Integrated Near-Field Microwave Biosensors

PubMed Central

Guha, Subhajit; Jamal, Farabi Ibne

2017-01-01

In this paper we review the advancement of passive and integrated microwave biosensors. The interaction of microwave with biological material is discussed in this paper. Passive microwave biosensors are microwave structures, which are fabricated on a substrate and are used for sensing biological materials. On the other hand, integrated biosensors are microwave structures fabricated in standard semiconductor technology platform (CMOS or BiCMOS). The CMOS or BiCMOS sensor technology offers a more compact sensing approach which has the potential in the future for point of care testing systems. Various applications of the passive and the integrated sensors have been discussed in this review paper. PMID:28946617

Nanopore-CMOS Interfaces for DNA Sequencing

PubMed Central

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-01-01

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

Nanopore-CMOS Interfaces for DNA Sequencing.

PubMed

Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

2016-08-06

DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

Gas spectroscopy system with transmitters and receivers in SiGe BiCMOS for 225-273 GHz

NASA Astrophysics Data System (ADS)

Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

2017-10-01

This paper updates results of our work on gas spectroscopy based on transmitters (TXs) and receivers (RXs) in IHP's 0.13 μm SiGe BiCMOS technology. The improved performance of our system is shown by the absorption spectra of gaseous methanol in the range 241 - 242 GHz at 1.4 Pa, corresponding to an absorption line width of about 1 MHz. The signal-noise ratio (SNR) for the absorption line of methanol at 241.7 GHz is used as measure. The system includes two fractional-n phase-locked loops (PLLs), which allow frequency ramps for the TX and RX, and a superimposed frequency shift keying modulation (FSK) for the TX. Another option includes reference frequency ramps for the PLLs in integer-n mode, which are realized by a direct digital synthesizer (DDS). An SNR of 1515 is observed for the 241.7 GHz absorption line at 1.4 Pa. We extend our single band TX/RX system with the range 238 - 252 GHz to a multi-band system to cover the range 225 - 273 GHz. It is built by combining corresponding pairs of TXs and RXs of three frequency bands in this range. The multi-band operation allows parallel spectra acquisition for these bands. For the TXs and RXs appropriate frequency ramps are generated by their external fractional-n PLL devices.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks.

PubMed

Hou, Bing; Chen, Hua; Wang, Zhiyu; Mo, Jiongjiong; Chen, Junli; Yu, Faxin; Wang, Wenbo

2017-01-24

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm² (1.2 mm² including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of -60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

Surface-modified CMOS IC electrochemical sensor array targeting single chromaffin cells for highly parallel amperometry measurements.

PubMed

Huang, Meng; Delacruz, Joannalyn B; Ruelas, John C; Rathore, Shailendra S; Lindau, Manfred

2018-01-01

Amperometry is a powerful method to record quantal release events from chromaffin cells and is widely used to assess how specific drugs modify quantal size, kinetics of release, and early fusion pore properties. Surface-modified CMOS-based electrochemical sensor arrays allow simultaneous recordings from multiple cells. A reliable, low-cost technique is presented here for efficient targeting of single cells specifically to the electrode sites. An SU-8 microwell structure is patterned on the chip surface to provide insulation for the circuitry as well as cell trapping at the electrode sites. A shifted electrode design is also incorporated to increase the flexibility of the dimension and shape of the microwells. The sensitivity of the electrodes is validated by a dopamine injection experiment. Microwells with dimensions slightly larger than the cells to be trapped ensure excellent single-cell targeting efficiency, increasing the reliability and efficiency for on-chip single-cell amperometry measurements. The surface-modified device was validated with parallel recordings of live chromaffin cells trapped in the microwells. Rapid amperometric spikes with no diffusional broadening were observed, indicating that the trapped and recorded cells were in very close contact with the electrodes. The live cell recording confirms in a single experiment that spike parameters vary significantly from cell to cell but the large number of cells recorded simultaneously provides the statistical significance.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Serial data correlator/code translator

NASA Technical Reports Server (NTRS)

Morgan, L. E. (Inventor)

1982-01-01

A system for analyzing asynchronous signals containing bits of information for ensuring the validity of said signals, by sampling each bit of information a plurality of times, and feeding the sampled pieces of bits of information into a sequence controlled is described. The sequence controller has a plurality of maps or programs through which the sampled pieces of bits are stepped so as to identify the particular bit of information and determine the validity and phase of the bit. The step in which the sequence controller is clocked is controlled by a storage register. A data decoder decodes the information fed out of the storage register and feeds such information to shift registers for storage.

Perspective: 2D for beyond CMOS

NASA Astrophysics Data System (ADS)

Robinson, Joshua A.

2018-05-01

Two-Dimensional (2D) materials have been a "beyond CMOS" focus for more than a decade now, and we are on the verge of a variety of breakthroughs in the science to enable their incorporation into next generation electronics. This perspective discusses some of the challenges that must be overcome, as well as various opportunities that await us in the world of 2D for beyond CMOS.

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

Cargo Movement Operations System (CMOS) System Segment Design Document. Revision. Increment 2

DTIC Science & Technology

1990-06-14

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ J CLOSED [ ] Cmnt Page Paragraph No. No. Number...provided (SSDDII-0004). CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ 3 ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...but not in paragraph 10.1. CMOS PMO ACCEPTS COMMENT: YES [ ) NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] * COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS): Revised Preliminary Software Design Document (Applications CSCI), Increment II

DTIC Science & Technology

1991-05-23

background color does not change. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: CONMENT STATUS: OPEN...NO ( ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ) CLOSED [ ] ,$ ...collected on this worksheet and are arranged in page number order. RATIONALE: N/A CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO

Cargo Movement Operations System (CMOS). Software Requirements Specification (Applications CSCI) Increment 1, Update

DTIC Science & Technology

1990-05-31

12. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ 3 ORIGINATOR CONTROL NUMBER: SRS1-0004 PROGRAM OFFICE...operational state of the SBSS. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN

Cargo Movement Operations System (CMOS) Draft Software User’s Manual Increment II

DTIC Science & Technology

1991-06-26

the user. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED...indicated. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR...YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN r I CLOSED [ ] ORIGINATOR CONTROL NUMBER: SUM-0006 PROGRAM OFFICE CONTROL NUMBER: DATA ITEM

Large Format CMOS-based Detectors for Diffraction Studies

NASA Astrophysics Data System (ADS)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

A decoding procedure for the Reed-Solomon codes

NASA Technical Reports Server (NTRS)

Lim, R. S.

1978-01-01

A decoding procedure is described for the (n,k) t-error-correcting Reed-Solomon (RS) code, and an implementation of the (31,15) RS code for the I4-TENEX central system. This code can be used for error correction in large archival memory systems. The principal features of the decoder are a Galois field arithmetic unit implemented by microprogramming a microprocessor, and syndrome calculation by using the g(x) encoding shift register. Complete decoding of the (31,15) code is expected to take less than 500 microsecs. The syndrome calculation is performed by hardware using the encoding shift register and a modified Chien search. The error location polynomial is computed by using Lin's table, which is an interpretation of Berlekamp's iterative algorithm. The error location numbers are calculated by using the Chien search. Finally, the error values are computed by using Forney's method.

Characterizations of double pulsing in neutron multiplicity and coincidence counting systems

DOE PAGES

Koehler, Katrina E.; Henzl, Vladimir; Croft, Stephen; ...

2016-06-29

Passive neutron coincidence/multiplicity counters are subject to non-ideal behavior, such as double pulsing and dead time. It has been shown in the past that double-pulsing exhibits a distinct signature in a Rossi-alpha distribution, which is not readily noticed using traditional Multiplicity Shift Register analysis. But, it has been assumed that the use of a pre-delay in shift register analysis removes any effects of double pulsing. Here, we use high-fidelity simulations accompanied by experimental measurements to study the effects of double pulsing on multiplicity rates. By exploiting the information from the double pulsing signature peak observable in the Rossi-alpha distribution, themore » double pulsing fraction can be determined. Algebraic correction factors for the multiplicity rates in terms of the double pulsing fraction have been developed. We also discuss the role of these corrections across a range of scenarios.« less

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

DOE and JAEA Field Trial of the Single Chip Shift Register (SCSR)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matthew R.

2016-03-23

Los Alamos National Laboratories (LANL) has recently developed a new data acquisition system for multiplicity analysis of neutron detector pulse streams. This new technology, the Single Chip Shift Register (SCSR), places the entire data acquisition system along with the communications hardware onto a single chip. This greatly simplifies the instrument and reduces the size. The SCSR is designed to be mounted into the neutron detector head alongside the instrument amplifiers. The user’s computer connects via USB directly to the neutron detector eliminating the external data acquisition electronics entirely. JAEA, through the INSEP program, asked LANL to demonstrate the functionality ofmore » the SCSR in Tokai using the JAEA Epithermal Neutron Multiplicity Counter, ENMC. In late September of 2015 LANL traveled to Tokai to install, demonstrate and uninstall the SCSR in the ENMC. This report documents the results of that field trial.« less

New Energy-Dependent Soft X-Rav Damage In MOS Devices

NASA Astrophysics Data System (ADS)

Chan, Tung-Yi; Gaw, Henry; Seligson, Daniel; Pan, Lawrence; King, Paul L.; Pianetta, Piero

1988-06-01

An energy-dependent soft x-ray-induced device damage has been discovered in MOS devices fabricated using standard CMOS process. MOS devices were irradiated by monochromatic x-rays in energy range just above and below the silicon K-edge (1.84 keV). Photons below the K-edge is found to create more damage in the oxide and oxide/silicon interface than photons above the K-edge. This energy-dependent damage effect is believed to be due to charge traps generated during device fabrication. It is found that data for both n- and p-type devices lie along a universal curve if normalized threshold voltage shifts are plotted against absorbed dose in the oxide. The threshold voltage shift saturates when the absorbed dose in the oxide exceeds 1.4X105 mJ/cm3, corresponding to 6 Mrad in the oxide. Using isochronal anneals, the trapped charge damage is found to recover with an activation energy of 0.38 eV. A discrete radiation-induced damage state appears in the low frequency C-V curve in a temperature range from 1750C to 325°C.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Multiple-target tracking implementation in the ebCMOS camera system: the LUSIPHER prototype

NASA Astrophysics Data System (ADS)

Doan, Quang Tuyen; Barbier, Remi; Dominjon, Agnes; Cajgfinger, Thomas; Guerin, Cyrille

2012-06-01

The domain of the low light imaging systems progresses very fast, thanks to detection and electronic multiplication technology evolution, such as the emCCD (electron multiplying CCD) or the ebCMOS (electron bombarded CMOS). We present an ebCMOS camera system that is able to track every 2 ms more than 2000 targets with a mean number of photons per target lower than two. The point light sources (targets) are spots generated by a microlens array (Shack-Hartmann) used in adaptive optics. The Multiple-Target-Tracking designed and implemented on a rugged workstation is described. The results and the performances of the system on the identification and tracking are presented and discussed.

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

CMOS image sensor-based immunodetection by refractive-index change.

PubMed

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Drop casting of stiffness gradients for chip integration into stretchable substrates

NASA Astrophysics Data System (ADS)

Naserifar, Naser; LeDuc, Philip R.; Fedder, Gary K.

2017-04-01

Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems.

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

CMOS image sensors as an efficient platform for glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-07

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

MULTIPLE INPUT BINARY ADDER EMPLOYING MAGNETIC DRUM DIGITAL COMPUTING APPARATUS

DOEpatents

Cooke-Yarborough, E.H.

1960-12-01

A digital computing apparatus is described for adding a plurality of multi-digit binary numbers. The apparatus comprises a rotating magnetic drum, a recording head, first and second reading heads disposed adjacent to the first and second recording tracks, and a series of timing signals recorded on the first track. A series of N groups of digit-representing signals is delivered to the recording head at time intervals corresponding to the timing signals, each group consisting of digits of the same significance in the numbers, and the signal series is recorded on the second track of the drum in synchronism with the timing signals on the first track. The multistage registers are stepped cyclically through all positions, and each of the multistage registers is coupled to the control lead of a separate gate circuit to open the corresponding gate at only one selected position in each cycle. One of the gates has its input coupled to the bistable element to receive the sum digit, and the output lead of this gate is coupled to the recording device. The inputs of the other gates receive the digits to be added from the second reading head, and the outputs of these gates are coupled to the adding register. A phase-setting pulse source is connected to each of the multistage registers individually to step the multistage registers to different initial positions in the cycle, and the phase-setting pulse source is actuated each N time interval to shift a sum digit to the bistable element, where the multistage register coupled to bistable element is operated by the phase- setting pulse source to that position in its cycle N steps before opening the first gate, so that this gate opens in synchronism with each of the shifts to pass the sum digits to the recording head.

Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

DTIC Science & Technology

2013-04-01

structures; v) developed CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vi) also engaged in a partnership with...CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vii. exploring approaches to enhance spontaneous emission in...size and bandwidth, we are exploring phase-change materials and, in particular, vanadium dioxide. VO2 undergoes an insulator-to-metal phase transition

Registration of Large Motion Blurred Images

DTIC Science & Technology

2016-05-09

in handling the dynamics of the capturing system, for example, a drone. CMOS sensors , used in recent times, when employed in these cameras produce...handling the dynamics of the capturing system, for example, a drone. CMOS sensors , used in recent times, when employed in these cameras produce two types...blur in the captured image when there is camera motion during exposure. However, contemporary CMOS sensors employ an electronic rolling shutter (RS

Solid State Research.

DTIC Science & Technology

1984-08-15

for the Same Signal 30 3 -1 Schematic Diagrams of Two Configurations with SOI/ CMOS and Bipolar Devices Fabricated on the Same Si Wafer. The Bipolar...Waveform of 39-Stage SOI/ CMOS Ring Oscillator for 5-V Supply Voltage. The Propagation Delay per Stage is 藨 ps 33 3 -4 Common-Emitter I-V...multiple beam splitters and delay lines. 3 . MATERIALS RESEARCH Two merged CMOS ! bipolar technologies utilizing S01 films have been developed for

Cargo Movement Operations System (CMOS). Final Software Design Document. Increment III. (PC Unix - Air Force Configuration)

DTIC Science & Technology

1991-07-03

required changes to this matrix. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN...this appendix should be updated to include all necessary changes. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION...ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SDD3-0004 PROGRAM OFFICE

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Organic-on-silicon complementary metal–oxide–semiconductor colour image sensors

PubMed Central

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-01

Complementary metal–oxide–semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor. PMID:25578322

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

How registered nurses, licensed practical nurses and resident aides spend time in nursing homes: An observational study.

PubMed

McCloskey, Rose; Donovan, Cindy; Stewart, Connie; Donovan, Alicia

2015-09-01

Calls for improved conditions in nursing homes have pointed to the importance of optimizing the levels and skills of care providers. Understanding the work of care providers will help to determine if staff are being used to their full potential and if opportunities exist for improved efficiencies. To explore the activities of care providers in different nursing homes and to identify if variations exist within and across homes and shifts. A multi-centre cross-sectional observational work flow study was conducted in seven different nursing homes sites in one Canadian province. Data were collected by a research assistant who conducted 368 h of observation. The research assistant collected data by following an identical route in each site and recording observations on staff activities. Findings indicate staff activities vary across roles, sites and shifts. Licensed practical nurses (nursing assistants) have the greatest variation in their role while registered nurses have the least amount of variability. In some sites both registered nurses and licensed practical nurses perform activities that may be safely delegated to others. Care providers spend as much as 53.7% of their time engaged in non-value added activities. There may be opportunities for registered nurses and licensed practical nurses to delegate some of their activities to non-regulated workers. The time care providers spend in non-value activities suggest there may be opportunities to improve efficiencies within the nursing home setting. Copyright © 2015 Elsevier Ltd. All rights reserved.

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Work schedule flexibility is associated with emotional exhaustion among registered nurses in Swiss hospitals: A cross-sectional study.

PubMed

Dhaini, Suzanne R; Denhaerynck, Kris; Bachnick, Stefanie; Schwendimann, René; Schubert, Maria; De Geest, Sabina; Simon, Michael

2018-06-01

Emotional exhaustion among healthcare workers is a widely investigated, well-recognized problem, the incidence of which has recently been linked to work environment factors, particularly work/family conflict. However, another environmental feature that may be equally influential, but that is more amenable to nurse manager action, remains less recognized: shift schedule flexibility. This study's main purposes were to assess variations in work schedule flexibility between Swiss acute care hospital units, and to investigate associations between psychosocial work environment (e.g. work schedule flexibility) and self-reported emotional exhaustion among registered nurses. This is a secondary analysis of data collected for the multi-center observational cross-sectional Match RN study, which included a national sample of 23 hospitals and 1833 registered nurses across Switzerland. Overall, self-reported work schedule flexibility among registered nurses was limited: 32% of participants reported little or no influence in planning their own shifts. Work schedule flexibility (β -0.11; CI -0.16; -0.06) and perceived nurse manager ability (β -0.30; CI -0.49; -0.10) were negatively related to self-reported emotional exhaustion. Work-family conflict (β 0.39; CI 0.33; 0.45) was positively correlated to emotional exhaustion. The study results indicate that managerial efforts to improve working environments, including special efforts to improve work schedule flexibility, might play an important role in promoting nurses' emotional health. Copyright © 2018 Elsevier Ltd. All rights reserved.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

PubMed

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

[Non-rigid medical image registration based on mutual information and thin-plate spline].

PubMed

Cao, Guo-gang; Luo, Li-min

2009-01-01

To get precise and complete details, the contrast in different images is needed in medical diagnosis and computer assisted treatment. The image registration is the basis of contrast, but the regular rigid registration does not satisfy the clinic requirements. A non-rigid medical image registration method based on mutual information and thin-plate spline was present. Firstly, registering two images globally based on mutual information; secondly, dividing reference image and global-registered image into blocks and registering them; then getting the thin-plate spline transformation according to the shift of blocks' center; finally, applying the transformation to the global-registered image. The results show that the method is more precise than the global rigid registration based on mutual information and it reduces the complexity of getting control points and satisfy the clinic requirements better by getting control points of the thin-plate transformation automatically.

MEMS-Electronic-Photonic Heterogeneous Integrated FMCW Ladar Source

DTIC Science & Technology

2015-12-18

CMOS  ICs  in  a  seamless  manner,  and...the   heterogeneous   integration   is   to   leverage   on   the   available   foundry   capabilities   ( CMOS   and...dies”   or   “known  good  wafers”).  We  have  adopted  a  three-­‐dimensional  (3D)  integration  strategy:  The   CMOS

Delta Doping High Purity CCDs and CMOS for LSST

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

NASA Astrophysics Data System (ADS)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

NASA Astrophysics Data System (ADS)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Small Pixel Hybrid CMOS X-ray Detectors

NASA Astrophysics Data System (ADS)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

Simple BiCMOS CCCTA design and resistorless analog function realization.

PubMed

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

640 X 480 PtSi MOS infrared imager

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1992-09-01

The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 10(superscript 6) electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

What Do Nurses Want? Priorities for Action.

ERIC Educational Resources Information Center

Minnick, Ann; And Others

1989-01-01

Discusses a survey of 23 hospitals regarding the shortage of registered nurses (RNs). Found that four trends are fueling the demand for RNs: (1) changes in medical practice, (2) shifts in patient characteristics, (3) professional objectives, and (4) economic incentives. (JOW)

77 FR 59013 - State Journal Register, Camera and Plate Department, Springfield, IL; Notice of Affirmative...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-09-25

... engaged in activities related to the production of a daily newspaper. The subject worker group performs... affected by the shift of ``advertising ad work'' to a foreign country. The Department will conduct further...

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

NASA Astrophysics Data System (ADS)

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

CMOS technology: a critical enabler for free-form electronics-based killer applications

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

New integration concept of PIN photodiodes in 0.35μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Teva, J.; Park, J. M.; Jessenig, S.; Rohrbacher, M.; Wachmann, E.

2012-06-01

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel.

PubMed

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-11-01

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

Application of CMOS Technology to Silicon Photomultiplier Sensors.

PubMed

D'Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-09-25

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

PubMed Central

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-01-01

With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field. PMID:27879789

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

NASA Astrophysics Data System (ADS)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

Multiple channel programmable coincidence counter

DOEpatents

Arnone, Gaetano J.

1990-01-01

A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

Toward CMOS image sensor based glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

Single-photon sensitive fast ebCMOS camera system for multiple-target tracking of single fluorophores: application to nano-biophotonics

NASA Astrophysics Data System (ADS)

Cajgfinger, Thomas; Chabanat, Eric; Dominjon, Agnes; Doan, Quang T.; Guerin, Cyrille; Houles, Julien; Barbier, Remi

2011-03-01

Nano-biophotonics applications will benefit from new fluorescent microscopy methods based essentially on super-resolution techniques (beyond the diffraction limit) on large biological structures (membranes) with fast frame rate (1000 Hz). This trend tends to push the photon detectors to the single-photon counting regime and the camera acquisition system to real time dynamic multiple-target tracing. The LUSIPHER prototype presented in this paper aims to give a different approach than those of Electron Multiplied CCD (EMCCD) technology and try to answer to the stringent demands of the new nano-biophotonics imaging techniques. The electron bombarded CMOS (ebCMOS) device has the potential to respond to this challenge, thanks to the linear gain of the accelerating high voltage of the photo-cathode, to the possible ultra fast frame rate of CMOS sensors and to the single-photon sensitivity. We produced a camera system based on a 640 kPixels ebCMOS with its acquisition system. The proof of concept for single-photon based tracking for multiple single-emitters is the main result of this paper.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Nano-electromechanical switch-CMOS hybrid technology and its applications.

PubMed

Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

2011-01-01

Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Fully Integrated Optical Spectrometer in Visible and Near-IR in CMOS.

PubMed

Hong, Lingyu; Sengupta, Kaushik

2017-12-01

Optical spectrometry in the visible and near-infrared range has a wide range of applications in healthcare, sensing, imaging, and diagnostics. This paper presents the first fully integrated optical spectrometer in standard bulk CMOS process without custom fabrication, postprocessing, or any external optical passive structure such as lenses, gratings, collimators, or mirrors. The architecture exploits metal interconnect layers available in CMOS processes with subwavelength feature sizes to guide, manipulate, control, diffract light, integrated photodetector, and read-out circuitry to detect dispersed light, and then back-end signal processing for robust spectral estimation. The chip, realized in bulk 65-nm low power-CMOS process, measures 0.64 mm 0.56 mm in active area, and achieves 1.4 nm in peak detection accuracy for continuous wave excitations between 500 and 830 nm. This paper demonstrates the ability to use these metal-optic nanostructures to miniaturize complex optical instrumentation into a new class of optics-free CMOS-based systems-on-chip in the visible and near-IR for various sensing and imaging applications.

Design and fabrication of a CMOS-compatible MHP gas sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao

2014-03-15

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperaturemore » in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.« less

Overview of CMOS process and design options for image sensor dedicated to space applications

NASA Astrophysics Data System (ADS)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

PubMed Central

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors.

PubMed

Nguyen, Dung C; Ma, Dongsheng Brian; Roveda, Janet M W

2012-01-01

As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

Experiments with synchronized sCMOS cameras

NASA Astrophysics Data System (ADS)

Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

2016-07-01

Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

PubMed Central

Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

2009-01-01

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Process simulation in digital camera system

NASA Astrophysics Data System (ADS)

Toadere, Florin

2012-06-01

The goal of this paper is to simulate the functionality of a digital camera system. The simulations cover the conversion from light to numerical signal and the color processing and rendering. We consider the image acquisition system to be linear shift invariant and axial. The light propagation is orthogonal to the system. We use a spectral image processing algorithm in order to simulate the radiometric properties of a digital camera. In the algorithm we take into consideration the transmittances of the: light source, lenses, filters and the quantum efficiency of a CMOS (complementary metal oxide semiconductor) sensor. The optical part is characterized by a multiple convolution between the different points spread functions of the optical components. We use a Cooke triplet, the aperture, the light fall off and the optical part of the CMOS sensor. The electrical part consists of the: Bayer sampling, interpolation, signal to noise ratio, dynamic range, analog to digital conversion and JPG compression. We reconstruct the noisy blurred image by blending different light exposed images in order to reduce the photon shot noise, also we filter the fixed pattern noise and we sharpen the image. Then we have the color processing blocks: white balancing, color correction, gamma correction, and conversion from XYZ color space to RGB color space. For the reproduction of color we use an OLED (organic light emitting diode) monitor. The analysis can be useful to assist students and engineers in image quality evaluation and imaging system design. Many other configurations of blocks can be used in our analysis.

CMOS time-to-digital converter based on a pulse-mixing scheme

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Liu, Keng-Chih; Chen, Guan-Hong

2014-11-01

This paper proposes a new pulse-mixing scheme utilizing both pulse-shrinking and pulse-stretching mechanisms to improve the performance of time-to-digital converters (TDCs). The temporal resolution of the conventional pulse-shrinking mechanism is determined by the size ratio between homogeneous and inhomogeneous elements. The proposed scheme which features double-stage operation derives its resolution according to the time difference between pulse-shrinking and pulse-stretching amounts. Thus, it can achieve greater immunity against temperature and ambient variations than that of the single-stage scheme. The circuit area also can be reduced by the proposed pulse-mixing scheme. In addition, this study proposes an improved cyclic delay line to eliminate the undesirable shift in the temporal resolution successfully. Therefore, the effective resolution can be controlled completely by the pulse-mixing unit to improve accuracy. The proposed TDC composed of only one cyclic delay line and one counter is fabricated in a TSMC CMOS 0.35-μm DPQM process. The chip core occupies an extremely small area of 0.02 mm2, which is the best among the related works. The experimental result shows that an effective resolution of around 53 ps within ±13% variation over a 0-100 °C temperature range is achieved. The power consumption is 90 μW at a sample rate of 1000 samples/s. In addition to the reduced area, the proposed TDC circuit achieves its resolution with less thermal-sensitivity and better fluctuations caused by process variations.

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

NASA Astrophysics Data System (ADS)

Aggarwal, Bhawna; Gupta, Maneesha; Gupta, Anil Kumar; Sangal, Ankur

2016-10-01

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0-440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.

Multi-Modulator for Bandwidth-Efficient Communication

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Lay, Norman; Cheetham, Craig; Fong, Wai; Yeh, Pen-Shu; King, Robin; Ghuman, Parminder; Hoy, Scott; Fisher, Dave

2009-01-01

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

PubMed

Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

2017-10-02

Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel

PubMed Central

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-01-01

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments. PMID:25426316

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Application of CMOS Technology to Silicon Photomultiplier Sensors

PubMed Central

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

Large Area Field of View for Fast Temporal Resolution Astronomy

NASA Astrophysics Data System (ADS)

Covarrubias, Ricardo A.

2018-01-01

Scientific CMOS (sCMOS) technology is especially relevant for high temporal resolution astronomy combining high resolution, large field of view with very fast frame rates, without sacrificing ultra-low noise performance. Solar Astronomy, Near Earth Object detections, Space Debris Tracking, Transient Observations or Wavefront Sensing are among the many applications this technology can be utilized. Andor Technology is currently developing the next-generation, very large area sCMOS camera with an extremely low noise, rapid frame rates, high resolution and wide dynamic range.

CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

NASA Astrophysics Data System (ADS)

Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

NASA Technical Reports Server (NTRS)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

12 CFR 1270.5 - Leverage limit and credit rating requirements.

Code of Federal Regulations, 2012 CFR

2012-01-01

... Mortgage Association (Fannie Mae), or Collateralized Mortgage Obligations (CMOs), including Real Estate Mortgage Investment Conduits (REMICs), backed by such securities; (xi) Other MBS, CMOs, and REMICs rated in...

12 CFR 1270.5 - Leverage limit and credit rating requirements.

Code of Federal Regulations, 2013 CFR

2013-01-01

... Mortgage Association (Fannie Mae), or Collateralized Mortgage Obligations (CMOs), including Real Estate Mortgage Investment Conduits (REMICs), backed by such securities; (xi) Other MBS, CMOs, and REMICs rated in...

12 CFR 1270.5 - Leverage limit and credit rating requirements.

Code of Federal Regulations, 2014 CFR

2014-01-01

... Mortgage Association (Fannie Mae), or Collateralized Mortgage Obligations (CMOs), including Real Estate Mortgage Investment Conduits (REMICs), backed by such securities; (xi) Other MBS, CMOs, and REMICs rated in...

CMOS analog switches for adaptive filters

NASA Technical Reports Server (NTRS)

Dixon, C. E.

1980-01-01

Adaptive active low-pass filters incorporate CMOS (Complimentary Metal-Oxide Semiconductor) analog switches (such as 4066 switch) that reduce variation in switch resistance when filter is switched to any selected transfer function.

The impact of financial incentives on participants' food purchasing patterns in a supermarket-based randomized controlled trial.

PubMed

Olstad, Dana Lee; Crawford, David A; Abbott, Gavin; McNaughton, Sarah A; Le, Ha Nd; Ni Mhurchu, Cliona; Pollard, Christina; Ball, Kylie

2017-08-25

The impacts of supermarket-based nutrition promotion interventions might be overestimated if participants shift their proportionate food purchasing away from their usual stores. This study quantified whether participants who received price discounts on fruits and vegetables (FV) in the Supermarket Healthy Eating for Life (SHELf) randomized controlled trial (RCT) shifted their FV purchasing into study supermarkets during the intervention period. Participants were 642 females randomly assigned to a 1) skill-building (n = 160), 2) price reduction (n = 161), 3) combined skill-building and price reduction (n = 160), or 4) control (n = 161) group. Participants self-reported the proportion of FV purchased in study supermarkets at baseline, 3- and 6-months post-intervention. Fisher's exact and χ 2 tests assessed differences among groups in the proportion of FV purchased in study supermarkets at each time point. Multinomial logistic regression assessed differences among groups in the change in proportionate FV purchasing over time. Post-intervention, 49% of participants purchased ≥50% of their FV in study supermarkets. Compared to all other groups, the price reduction group was approximately twice as likely (RRR: 1.8-2.2) to have increased proportionate purchasing of FV in study supermarkets from baseline to post-intervention (p< 0.05). Participants who received price reductions on FV were approximately twice as likely to shift their FV purchasing from other stores into study supermarkets during the intervention period. Unless food purchasing data are available for all sources, differential changes in purchasing patterns can make it difficult to discern the true impacts of nutrition interventions. The SHELf trial is registered with Current Controlled Trials Registration ISRCTN39432901, Registered 30 June 2010, Retrospectively registered ( http://www.isrctn.com/ISRCTN39432901 ).

Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor)

2015-01-01

A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

A CMOS enhanced solid-state nanopore based single molecule detection platform.

PubMed

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-01-01

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data.

Equalizing Si photodetectors fabricated in standard CMOS processes

NASA Astrophysics Data System (ADS)

Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

2017-05-01

This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

CMOS dot matrix microdisplay

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Massively parallel processor computer

NASA Technical Reports Server (NTRS)

Fung, L. W. (Inventor)

1983-01-01

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

HLA-DR allele reading register shifting is associated with immunity induced by SERA peptide analogues.

PubMed

Salazar, Luz Mary; Bermúdez, Adriana; Patarroyo, Manuel E

2008-07-18

SERA protein is a leading candidate molecule to be included in an antimalarial vaccine. Conserved high activity binding peptides (HABP) binding to red blood cells (RBC) have been identified in this protein. One of them (6762) localising in the 18-kDa C-terminal fragment was used to induce protective immunity with negative result. Critical RBC binding residues (assessed by glycine-analogue scanning) were replaced by others having the same mass, volume and surface but different polarity, rendering some of them immunogenic as assessed by antibody production against the parasite or its proteins and protection-inducing against challenge with a highly infectious Aotus monkey-adapted Plasmodium falciparum strain. A shift in binding to purified HLA-DR allelic molecules from the same haplotype and in their reading register was found, suggesting that modified molecules had adopted a different (1)H NMR 3D structure allowing a better fit into the MHCII-pept-TCR complex, thereby representing a new mechanism for inducing immune protection.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness.

PubMed

Cao, Q; Brehler, M; Sisniega, A; Stayman, J W; Yorkston, J; Siewerdsen, J H; Zbijewski, W

2017-03-01

CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μ m, ~80 μ m and ~40 μ m, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μ m pixels) with CsI scintillator thicknesses of 400 μ m and 700 μ m, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6-5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μ m scintillator compared to the standard nominal CsI thickness of 700 μ m. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index ( d' 2 ) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μ m CsI compared to 700 μ m CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μ m panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μ m scinitllator. Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μ m CsI onto the clinical prototype of CMOS-based extremity CBCT.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness

PubMed Central

Cao, Q.; Brehler, M.; Sisniega, A.; Stayman, J. W.; Yorkston, J.; Siewerdsen, J. H.; Zbijewski, W.

2017-01-01

Purpose CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. Methods A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μm, ~80 μm and ~40 μm, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μm pixels) with CsI scintillator thicknesses of 400 μm and 700 μm, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6–5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Results Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μm scintillator compared to the standard nominal CsI thickness of 700 μm. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index (d′2) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μm CsI compared to 700 μm CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μm panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μm scinitllator. Conclusion Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μm CsI onto the clinical prototype of CMOS-based extremity CBCT. PMID:28989220

WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Q; Brehler, M; Sisniega, A

Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection)more » using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high-frequency imaging tasks through adoption of the CMOS detector and small FS x-ray source, motivating the use of these components in a new system for quantitative in-vivo imaging of trabecular bone. Financial Support: US NIH grant R01EB018896. Qian Cao is a Howard Hughes Medical Institute International Student Research Fellow. Disclosures: W Zbijewski, J Siewerdsen and A Sisniega receive research funding from Carestream Health.« less

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

NASA Astrophysics Data System (ADS)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

PubMed

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-11-17

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Determining the Performance of Fluorescence Molecular Imaging Devices using Traceable Working Standards with SI Units of Radiance

PubMed Central

Zhu, Banghe; Rasmussen, John C.; Litorja, Maritoni

2017-01-01

To date, no emerging preclinical or clinical near-infrared fluorescence (NIRF) imaging devices for non-invasive and/or surgical guidance have their performances validated on working standards with SI units of radiance that enable comparison or quantitative quality assurance. In this work, we developed and deployed a methodology to calibrate a stable, solid phantom for emission radiance with units of mW · sr−1 · cm−2 for use in characterizing the measurement sensitivity of ICCD and IsCMOS detection, signal-to-noise ratio, and contrast. In addition, at calibrated radiances, we assess transverse and lateral resolution of ICCD and IsCMOS camera systems. The methodology allowed determination of superior SNR of the ICCD over the IsCMOS camera system and superior resolution of the IsCMOS over the ICCD camera system. Contrast depended upon the camera settings (binning and integration time) and gain of intensifier. Finally, because of architecture of CMOS and CCD camera systems resulting in vastly different performance, we comment on the utility of these systems for small animal imaging as well as clinical applications for non-invasive and surgical guidance. PMID:26552078

Twenty-four-micrometer-pitch microelectrode array with 6912-channel readout at 12 kHz via highly scalable implementation for high-spatial-resolution mapping of action potentials.

PubMed

Ogi, Jun; Kato, Yuri; Matoba, Yoshihisa; Yamane, Chigusa; Nagahata, Kazunori; Nakashima, Yusaku; Kishimoto, Takuya; Hashimoto, Shigeki; Maari, Koichi; Oike, Yusuke; Ezaki, Takayuki

2017-12-19

A 24-μm-pitch microelectrode array (MEA) with 6912 readout channels at 12 kHz and 23.2-μV rms random noise is presented. The aim is to reduce noise in a "highly scalable" MEA with a complementary metal-oxide-semiconductor integration circuit (CMOS-MEA), in which a large number of readout channels and a high electrode density can be expected. Despite the small dimension and the simplicity of the in-pixel circuit for the high electrode-density and the relatively large number of readout channels of the prototype CMOS-MEA chip developed in this work, the noise within the chip is successfully reduced to less than half that reported in a previous work, for a device with similar in-pixel circuit simplicity and a large number of readout channels. Further, the action potential was clearly observed on cardiomyocytes using the CMOS-MEA. These results indicate the high-scalability of the CMOS-MEA. The highly scalable CMOS-MEA provides high-spatial-resolution mapping of cell action potentials, and the mapping can aid understanding of complex activities in cells, including neuron network activities.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Solid-state image sensor with focal-plane digital photon-counting pixel array

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Pain, Bedabrata (Inventor)

1995-01-01

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

A 65 nm CMOS LNA for Bolometer Application

NASA Astrophysics Data System (ADS)

Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

2016-04-01

Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

Challenges & Roadmap for Beyond CMOS Computing Simulation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rodrigues, Arun F.; Frank, Michael P.

Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Benoit, M.; de Mendizabal, J. Bilbao; Casse, G.

We investigated the active pixel sensors based on the High-Voltage CMOS technology as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. Our paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. These results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

DOE PAGES

Benoit, M.; de Mendizabal, J. Bilbao; Casse, G.; ...

2016-07-21

We investigated the active pixel sensors based on the High-Voltage CMOS technology as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. Our paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. These results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

Pixel super resolution using wavelength scanning

DTIC Science & Technology

2016-04-08

the light source is adjusted to ~20 μW. The image sensor chip is a color CMOS sensor chip with a pixel size of 1.12 μm manufactured for cellphone...pitch (that is, ~ 1 μm in Figure 3a, using a CMOS sensor that has a 1.12-μm pixel pitch). For the same configuration depicted in Figure 3, utilizing...section). The a Lens-free raw holograms captured by 1.12 μm CMOS image sensor Field of view ≈ 20.5 mm2 Angle change directions for synthetic aperture

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

NASA Astrophysics Data System (ADS)

Vigani, L.; Bortoletto, D.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-02-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

Preliminary performances measured on a CMOS long linear array for space application

NASA Astrophysics Data System (ADS)

Renard, Christophe; Artinian, Armand; Dantes, Didier; Lepage, Gérald; Diels, Wim

2017-11-01

This paper presents the design and the preliminary performances of a CMOS linear array, resulting from collaboration between Alcatel Alenia Space and Cypress Semiconductor BVBA, which takes advantage of emerging potentialities of CMOS technologies. The design of the sensor is presented: it includes 8000 panchromatic pixels with up to 25 rows used in TDI mode, and 4 lines of 2000 pixels for multispectral imaging. Main system requirements and detector tradeoffs are recalled, and the preliminary test results obtained with a first generation prototype are summarized and compared with predicted performances.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

CMOS sensor as charged particles and ionizing radiation detector

NASA Astrophysics Data System (ADS)

Cruz-Zaragoza, E.; Piña López, I.

2015-01-01

This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

Charge shielding in the In-situ Storage Image Sensor for a vertex detector at the ILC

NASA Astrophysics Data System (ADS)

Zhang, Z.; Stefanov, K. D.; Bailey, D.; Banda, Y.; Buttar, C.; Cheplakov, A.; Cussans, D.; Damerell, C.; Devetak, E.; Fopma, J.; Foster, B.; Gao, R.; Gillman, A.; Goldstein, J.; Greenshaw, T.; Grimes, M.; Halsall, R.; Harder, K.; Hawes, B.; Hayrapetyan, K.; Heath, H.; Hillert, S.; Jackson, D.; Pinto Jayawardena, T.; Jeffery, B.; John, J.; Johnson, E.; Kundu, N.; Laing, A.; Lastovicka, T.; Lau, W.; Li, Y.; Lintern, A.; Lynch, C.; Mandry, S.; Martin, V.; Murray, P.; Nichols, A.; Nomerotski, A.; Page, R.; Parkes, C.; Perry, C.; O'Shea, V.; Sopczak, A.; Tabassam, H.; Thomas, S.; Tikkanen, T.; Velthuis, J.; Walsh, R.; Woolliscroft, T.; Worm, S.

2009-08-01

The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device's operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application.

Real-time phase correlation based integrated system for seizure detection

NASA Astrophysics Data System (ADS)

Romaine, James B.; Delgado-Restituto, Manuel; Leñero-Bardallo, Juan A.; Rodríguez-Vázquez, Ángel

2017-05-01

This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

Spectroturbidimitry as applied to biomedical and immunological investigations

NASA Astrophysics Data System (ADS)

Shchyogolev, Sergei Y.; Khlebtsov, Nikolai G.; Schwartsburd, Boris I.

1993-06-01

Methods of optical shifting spectroscopy and laser nephelometry may be used to register antigen-antibody reaction. Usage of laser nephelometry in serodiagnostics, characteristics of a specific step in humoral immune reaction in infections, postinfectious and postinoculation processes response and immunity tension in some infectious diseases were investigated.

Electronics. Module 3: Digital Logic Application. Instructor's Guide.

ERIC Educational Resources Information Center

Carter, Ed; Murphy, Mark

This guide contains instructor's materials for a 10-unit secondary school course on digital logic application. The units are introduction to digital, logic gates, digital integrated circuits, combination logic, flip-flops, counters and shift registers, encoders and decoders, arithmetic circuits, memory, and analog/digital and digital/analog…

Problems with the random number generator RANF implemented on the CDC cyber 205

NASA Astrophysics Data System (ADS)

Kalle, Claus; Wansleben, Stephan

1984-10-01

We show that using RANF may lead to wrong results when lattice models are simulated by Monte Carlo methods. We present a shift-register sequence random number generator which generates two random numbers per cycle on a two pipe CDC Cyber 205.

THRESHOLD ELEMENTS AND THE DESIGN OF SEQUENTIAL SWITCHING NETWORKS.

DTIC Science & Technology

The report covers research performed from March 1966 to March 1967. The major topics treated are: (1) methods for finding weight- threshold vectors...that realize a given switching function in multi- threshold linear logic; (2) synthesis of sequential machines by means of shift registers and simple

A fail-safe CMOS logic gate

NASA Technical Reports Server (NTRS)

Bobin, V.; Whitaker, S.

1990-01-01

This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

PubMed Central

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

PubMed

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

An efficient current-based logic cell model for crosstalk delay analysis

NASA Astrophysics Data System (ADS)

Nazarian, Shahin; Das, Debasish

2013-04-01

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

PubMed Central

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is −42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Centroid measurement error of CMOS detector in the presence of detector noise for inter-satellite optical communications

NASA Astrophysics Data System (ADS)

Li, Xin; Zhou, Shihong; Ma, Jing; Tan, Liying; Shen, Tao

2013-08-01

CMOS is a good candidate tracking detector for satellite optical communications systems with outstanding feature of sub-window for the development of APS (Active Pixel Sensor) technology. For inter-satellite optical communications it is critical to estimate the direction of incident laser beam precisely by measuring the centroid position of incident beam spot. The presence of detector noise results in measurement error, which degrades the tracking performance of systems. In this research, the measurement error of CMOS is derived taking consideration of detector noise. It is shown that the measurement error depends on pixel noise, size of the tracking sub-window (pixels number), intensity of incident laser beam, relative size of beam spot. The influences of these factors are analyzed by numerical simulation. We hope the results obtained in this research will be helpful in the design of CMOS detector satellite optical communications systems.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

The Biolink Implantable Telemetry System

NASA Technical Reports Server (NTRS)

Betancourt-Zamora, Rafael J.

1999-01-01

Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHZ offset, showing good agreement with the theory. We also propose a novel superregenerative receiver architecture for implementing the command receiver. The superregenerative receiver's simplicity, low cost, and low power consumption has made it the receiver of choice for short-distance data communications, remote control and home automation. We present the design of a superregenerative AM receiver implemented in a 0.5um CMOS technology that operates at 433.92MHz and dissipates only 300uW. Further work entails detailed transistor-level design of the FLL and superregenerative receiver and a monolithic implementation of an implantable transceiver in 0.5um CMOS technology.

Modeling and evaluation of a high-resolution CMOS detector for cone-beam CT of the extremities.

PubMed

Cao, Qian; Sisniega, Alejandro; Brehler, Michael; Stayman, J Webster; Yorkston, John; Siewerdsen, Jeffrey H; Zbijewski, Wojciech

2018-01-01

Quantitative assessment of trabecular bone microarchitecture in extremity cone-beam CT (CBCT) would benefit from the high spatial resolution, low electronic noise, and fast scan time provided by complementary metal-oxide semiconductor (CMOS) x-ray detectors. We investigate the performance of CMOS sensors in extremity CBCT, in particular with respect to potential advantages of thin (<0.7 mm) scintillators offering higher spatial resolution. A cascaded systems model of a CMOS x-ray detector incorporating the effects of CsI:Tl scintillator thickness was developed. Simulation studies were performed using nominal extremity CBCT acquisition protocols (90 kVp, 0.126 mAs/projection). A range of scintillator thickness (0.35-0.75 mm), pixel size (0.05-0.4 mm), focal spot size (0.05-0.7 mm), magnification (1.1-2.1), and dose (15-40 mGy) was considered. The detectability index was evaluated for both CMOS and a-Si:H flat-panel detector (FPD) configurations for a range of imaging tasks emphasizing spatial frequencies associated with feature size aobj. Experimental validation was performed on a CBCT test bench in the geometry of a compact orthopedic CBCT system (SAD = 43.1 cm, SDD = 56.0 cm, matching that of the Carestream OnSight 3D system). The test-bench studies involved a 0.3 mm focal spot x-ray source and two CMOS detectors (Dalsa Xineos-3030HR, 0.099 mm pixel pitch) - one with the standard CsI:Tl thickness of 0.7 mm (C700) and one with a custom 0.4 mm thick scintillator (C400). Measurements of modulation transfer function (MTF), detective quantum efficiency (DQE), and CBCT scans of a cadaveric knee (15 mGy) were obtained for each detector. Optimal detectability for high-frequency tasks (feature size of ~0.06 mm, consistent with the size of trabeculae) was ~4× for the C700 CMOS detector compared to the a-Si:H FPD at nominal system geometry of extremity CBCT. This is due to ~5× lower electronic noise of a CMOS sensor, which enables input quantum-limited imaging at smaller pixel size. Optimal pixel size for high-frequency tasks was <0.1 mm for a CMOS, compared to ~0.14 mm for an a-Si:H FPD. For this fine pixel pitch, detectability of fine features could be improved by using a thinner scintillator to reduce light spread blur. A 22% increase in detectability of 0.06 mm features was found for the C400 configuration compared to C700. An improvement in the frequency at 50% modulation (f 50 ) of MTF was measured, increasing from 1.8 lp/mm for C700 to 2.5 lp/mm for C400. The C400 configuration also achieved equivalent or better DQE as C700 for frequencies above ~2 mm -1 . Images of cadaver specimens confirmed improved visualization of trabeculae with the C400 sensor. The small pixel size of CMOS detectors yields improved performance in high-resolution extremity CBCT compared to a-Si:H FPDs, particularly when coupled with a custom 0.4 mm thick scintillator. The results indicate that adoption of a CMOS detector in extremity CBCT can benefit applications in quantitative imaging of trabecular microstructure in humans. © 2017 American Association of Physicists in Medicine.

CMOS cassette for digital upgrade of film-based mammography systems

NASA Astrophysics Data System (ADS)

Baysal, Mehmet A.; Toker, Emre

2006-03-01

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

NASA Astrophysics Data System (ADS)

Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

2011-01-01

In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

Hyperspectral CMOS imager

NASA Astrophysics Data System (ADS)

Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

2017-11-01

CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

Detection of pointing errors with CMOS-based camera in intersatellite optical communications

NASA Astrophysics Data System (ADS)

Yu, Si-yuan; Ma, Jing; Tan, Li-ying

2005-01-01

For very high data rates, intersatellite optical communications hold a potential performance edge over microwave communications. Acquisition and Tracking problem is critical because of the narrow transmit beam. A single array detector in some systems performs both spatial acquisition and tracking functions to detect pointing errors, so both wide field of view and high update rate is required. The past systems tend to employ CCD-based camera with complex readout arrangements, but the additional complexity reduces the applicability of the array based tracking concept. With the development of CMOS array, CMOS-based cameras can employ the single array detector concept. The area of interest feature of the CMOS-based camera allows a PAT system to specify portion of the array. The maximum allowed frame rate increases as the size of the area of interest decreases under certain conditions. A commercially available CMOS camera with 105 fps @ 640×480 is employed in our PAT simulation system, in which only part pixels are used in fact. Beams angle varying in the field of view can be detected after getting across a Cassegrain telescope and an optical focus system. Spot pixel values (8 bits per pixel) reading out from CMOS are transmitted to a DSP subsystem via IEEE 1394 bus, and pointing errors can be computed by the centroid equation. It was shown in test that: (1) 500 fps @ 100×100 is available in acquisition when the field of view is 1mrad; (2)3k fps @ 10×10 is available in tracking when the field of view is 0.1mrad.

RF upset susceptibilities of CMOS and low power Schottky D-type flip-flops

NASA Astrophysics Data System (ADS)

Kenneally, Daniel J.; Koellen, Daniel S.; Epshtein, Stan

A description is given of measurements of RF upset levels on two D-type flip-flops, the CD4013B and 54ALS74A, which are functionally identical but fabricated from different technologies: CMOS and low-power Schottky. Continuous-wave electromagnetic interference (CW EMI) from 1 MHz to 200 MHz was coupled into the clock, data, and collector bias, Vcc, ports of each device type while test vectors were used to verify normal operation and subsequent upsets. Both the CMOS and the Schottky devices show decreasing RF susceptibility with increasing frequencies from 1 to 200 MHz. The CMOS device roll-off is almost 18 dB/decade as compared to about 12 dB/decade for the Schottky device. The differences in the Vcc ports' susceptibilities are also apparent. The CMOS device's upset levels decrease steeply with increasing frequency at approximate roll-offs of 60 dB/decade up to 5 MHz and 15 dB/decade from 5 to 100 MHz. Over the same bands, the Schottky device susceptibility at the Vcc port remains strikingly constant at a 6-dBm upset level. Measurements on the clock and data ports seem to suggest that: (1) the CMOS device is `RF harder' than the Schottky device by 3 to 18 dB at least above the 5 to 10 MHz range and out to 100 MHz; and (2) below that range, the Schottky device may be `RF harder' by 3 to 6 dB, but there are not enough measurement data to confirm this performance below 5 MHz.

Clock jitter generator with picoseconds resolution

NASA Astrophysics Data System (ADS)

Jovanović, Goran; Stojčev, Mile; Nikolić, Tatjana

2013-06-01

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Thermal annealing of radiation damage in CMOS ICs in the temperature range -140 C to +375 C

NASA Technical Reports Server (NTRS)

Danchenko, V.; Fang, P. H.; Brashears, S. S.

1982-01-01

Annealing of radiation damage was investigated in the commercial, Z- and J-processes of the RCA CD4007A ICs in the temperature range from -140 C to +375 C. Tempering curves were analyzed for activation energies of thermal annealing, following irradiation at -140 C. It was found that at -140 C, the radiation-induced shifts in the threshold potentials were similar for all three processes. The radiation hardness of the Z- and J-process is primarily due to rapid annealing of radiation damage at room temperature. In the region -140 to 20 C, no dopant-dependent charge trapping is seen, similar to that observed at higher temperatures. In the unbiased Z-process n-channels, after 1 MeV electron irradiation, considerable negative charge remains in the gate oxide.

Effects of Marital Status and Shift Work on Family Function among Registered Nurses

PubMed Central

TAI, Shu-Yu; LIN, Pei-Chen; CHEN, Yao-Mei; HUNG, Hsin-Chia; PAN, Chih-Hong; PAN, Shung-Mei; LEE, Chung-Yin; HUANG, Chia-Tsuan; WU, Ming-Tsang

2014-01-01

This study aims to assess the interactive effect of marital status and shift work on family function. A population-based sample of 1,438 nurses between the ages of 20–45 yr was recruited from Taiwan during the period from July 2005 to April 2006 using a mailed questionnaire. The self-administered questionnaire contained information about demographic data, work status, shift work schedule, and the Family APGAR (Adaptation, Partnership, Growth, Affection, and Resolve) Scale, to evaluate family function. Compared to day shift nurses, non-night and rotation shift nurses had 1.53- and 1.38-fold (95% CI=1.09–2.14 and 1.01–1.88) risk to have poor family function after adjusting for other covariates. Married nurses, by contrast, had a 0.44-fold (95% CI=0.29–0.66) risk to have poor family function compared to single nurses. In addition, married nurses who worked non-night or rotation shifts had a significantly higher percent of poor family function than those married nurses working day shifts; however, similar results were not replicated in single nurses. We concluded that shift work and marital status could influence family function. PMID:24909112

Effects of marital status and shift work on family function among registered nurses.

PubMed

Tai, Shu-Yu; Lin, Pei-Chen; Chen, Yao-Mei; Hung, Hsin-Chia; Pan, Chih-Hong; Pan, Shung-Mei; Lee, Chung-Yin; Huang, Chia-Tsuan; Wu, Ming-Tsang

2014-01-01

This study aims to assess the interactive effect of marital status and shift work on family function. A population-based sample of 1,438 nurses between the ages of 20-45 yr was recruited from Taiwan during the period from July 2005 to April 2006 using a mailed questionnaire. The self-administered questionnaire contained information about demographic data, work status, shift work schedule, and the Family APGAR (Adaptation, Partnership, Growth, Affection, and Resolve) Scale, to evaluate family function. Compared to day shift nurses, non-night and rotation shift nurses had 1.53- and 1.38-fold (95% CI=1.09-2.14 and 1.01-1.88) risk to have poor family function after adjusting for other covariates. Married nurses, by contrast, had a 0.44-fold (95% CI=0.29-0.66) risk to have poor family function compared to single nurses. In addition, married nurses who worked non-night or rotation shifts had a significantly higher percent of poor family function than those married nurses working day shifts; however, similar results were not replicated in single nurses. We concluded that shift work and marital status could influence family function.

Glottal Adduction and Subglottal Pressure in Singing.

PubMed

Herbst, Christian T; Hess, Markus; Müller, Frank; Švec, Jan G; Sundberg, Johan

2015-07-01

Previous research suggests that independent variation of vocal loudness and glottal configuration (type and degree of vocal fold adduction) does not occur in untrained speech production. This study investigated whether these factors can be varied independently in trained singing and how subglottal pressure is related to average glottal airflow, voice source properties, and sound level under these conditions. A classically trained baritone produced sustained phonations on the endoscopic vowel [i:] at pitch D4 (approximately 294 Hz), exclusively varying either (a) vocal register; (b) phonation type (from "breathy" to "pressed" via cartilaginous adduction); or (c) vocal loudness, while keeping the others constant. Phonation was documented by simultaneous recording of videokymographic, electroglottographic, airflow and voice source data, and by percutaneous measurement of relative subglottal pressure. Register shifts were clearly marked in the electroglottographic wavegram display. Compared with chest register, falsetto was produced with greater pulse amplitude of the glottal flow, H1-H2, mean airflow, and with lower maximum flow declination rate (MFDR), subglottal pressure, and sound pressure. Shifts of phonation type (breathy/flow/neutral/pressed) induced comparable systematic changes. Increase of vocal loudness resulted in increased subglottal pressure, average flow, sound pressure, MFDR, glottal flow pulse amplitude, and H1-H2. When changing either vocal register or phonation type, subglottal pressure and mean airflow showed an inverse relationship, that is, variation of glottal flow resistance. The direct relation between subglottal pressure and airflow when varying only vocal loudness demonstrated independent control of vocal loudness and glottal configuration. Achieving such independent control of phonatory control parameters would be an important target in vocal pedagogy and in voice therapy. Copyright © 2015 The Voice Foundation. Published by Elsevier Inc. All rights reserved.

Cargo Movement Operations (CMOS) Increment I Installation and Checkout Plan for Langley AFB

DTIC Science & Technology

1990-10-28

ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No...document. CMOS PMO ACCEPTS COMMENT: YES [ ) NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN [ ] CLOSED [

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

Cargo Movement Operations System (CMOS). Interface Requirements Specification. Revised Draft. Increment 2

DTIC Science & Technology

1990-08-02

NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment ------------ ---- --------- -------------------------------------------- 1. 12 Table 3.1.2 Add "(On-Base)" to CC0205 - ADAM III to CMOS. 2. 28 3.10.2 c. Add reference to Table 3.11.21. 3. 30 3.12.1 b.(2) Change "Conformation of Listed Manifest" to "Confirmation of Lifted Manifest". 4. 50 3.34 d. Change this paragraph ref 2rence to 3.33 d. 5. 58 Table 6.3 Change the second "CMOS to ADAM III

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Wafer-scale development and experimental verification of 0.36 mm2 228 mV open-circuit-voltage solid-state CMOS-compatible glucose fuel cell

NASA Astrophysics Data System (ADS)

Arata, Shigeki; Hayashi, Kenya; Nishio, Yuya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-04-01

The world’s smallest (0.36 mm2) solid-state CMOS-compatible glucose fuel cell, which exhibits an open-circuit voltage (OCV) of 228 mV and a power generation density of 1.32 µW/cm2 with a 30 mM glucose solution, is reported in this paper. Compared with conventional wet etching, dry etching (reactive ion etching) for patterning minimizes damage to the anode and cathode, resulting in a cell with a small size and a high OCV, sufficient for CMOS circuit operation.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.