High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

PubMed

Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

PubMed Central

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

2015-01-01

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

NASA Astrophysics Data System (ADS)

Rotta, Davide; Sebastiano, Fabio; Charbon, Edoardo; Prati, Enrico

2017-06-01

Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2 for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.

Solution Processed Metal Oxide High-κ Dielectrics for Emerging Transistors and Circuits.

PubMed

Liu, Ao; Zhu, Huihui; Sun, Huabin; Xu, Yong; Noh, Yong-Young

2018-06-14

The electronic functionalities of metal oxides comprise conductors, semiconductors, and insulators. Metal oxides have attracted great interest for construction of large-area electronics, particularly thin-film transistors (TFTs), for their high optical transparency, excellent chemical and thermal stability, and mechanical tolerance. High-permittivity (κ) oxide dielectrics are a key component for achieving low-voltage and high-performance TFTs. With the expanding integration of complementary metal oxide semiconductor transistors, the replacement of SiO 2 with high-κ oxide dielectrics has become urgently required, because their provided thicker layers suppress quantum mechanical tunneling. Toward low-cost devices, tremendous efforts have been devoted to vacuum-free, solution processable fabrication, such as spin coating, spray pyrolysis, and printing techniques. This review focuses on recent progress in solution processed high-κ oxide dielectrics and their applications to emerging TFTs. First, the history, basics, theories, and leakage current mechanisms of high-κ oxide dielectrics are presented, and the underlying mechanism for mobility enhancement over conventional SiO 2 is outlined. Recent achievements of solution-processed high-κ oxide materials and their applications in TFTs are summarized and traditional coating methods and emerging printing techniques are introduced. Finally, low temperature approaches, e.g., ecofriendly water-induced, self-combustion reaction, and energy-assisted post treatments, for the realization of flexible electronics and circuits are discussed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Direct Growth of Graphene Film on Germanium Substrate

PubMed Central

Wang, Gang; Zhang, Miao; Zhu, Yun; Ding, Guqiao; Jiang, Da; Guo, Qinglei; Liu, Su; Xie, Xiaoming; Chu, Paul K.; Di, Zengfeng; Wang, Xi

2013-01-01

Graphene has been predicted to play a role in post-silicon electronics due to the extraordinary carrier mobility. Chemical vapor deposition of graphene on transition metals has been considered as a major step towards commercial realization of graphene. However, fabrication based on transition metals involves an inevitable transfer step which can be as complicated as the deposition of graphene itself. By ambient-pressure chemical vapor deposition, we demonstrate large-scale and uniform depositon of high-quality graphene directly on a Ge substrate which is wafer scale and has been considered to replace conventional Si for the next generation of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The immiscible Ge-C system under equilibrium conditions dictates graphene depositon on Ge via a self-limiting and surface-mediated process rather than a precipitation process as observed from other metals with high carbon solubility. Our technique is compatible with modern microelectronics technology thus allowing integration with high-volume production of complementary metal-oxide-semiconductors (CMOS). PMID:23955352

Metal oxide semiconductor thin-film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

Petti, Luisa; Münzenrieder, Niko; Vogt, Christian; Faber, Hendrik; Büthe, Lars; Cantarella, Giuseppe; Bottacchi, Francesca; Anthopoulos, Thomas D.; Tröster, Gerhard

2016-06-01

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.

Metal oxide semiconductor thin-film transistors for flexible electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Vogt, Christian; Büthe, Lars

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This reviewmore » reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.« less

Towards a Chemiresistive Sensor-Integrated Electronic Nose: A Review

PubMed Central

Chiu, Shih-Wen; Tang, Kea-Tiong

2013-01-01

Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip. PMID:24152879

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Dimensional optimization of nanowire--complementary metal oxide--semiconductor inverter.

PubMed

Hashim, Yasir; Sidek, Othman

2013-01-01

This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

Design and fabrication of reflective spatial light modulator for high-dynamic-range wavefront control

NASA Astrophysics Data System (ADS)

Zhu, Hao; Bierden, Paul; Cornelissen, Steven; Bifano, Thomas; Kim, Jin-Hong

2004-10-01

This paper describes design and fabrication of a microelectromechanical metal spatial light modulator (SLM) integrated with complementary metal-oxide semiconductor (CMOS) electronics, for high-dynamic-range wavefront control. The metal SLM consists of a large array of piston-motion MEMS mirror segments (pixels) which can deflect up to 0.78 µm each. Both 32x32 and 150x150 arrays of the actuators (1024 and 22500 elements respectively) were fabricated onto the CMOS driver electronics and individual pixels were addressed. A new process has been developed to reduce the topography during the metal MEMS processing to fabricate mirror pixels with improved optical quality.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

PubMed

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-05-02

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

Single-photon imaging in complementary metal oxide semiconductor processes

PubMed Central

Charbon, E.

2014-01-01

This paper describes the basics of single-photon counting in complementary metal oxide semiconductors, through single-photon avalanche diodes (SPADs), and the making of miniaturized pixels with photon-counting capability based on SPADs. Some applications, which may take advantage of SPAD image sensors, are outlined, such as fluorescence-based microscopy, three-dimensional time-of-flight imaging and biomedical imaging, to name just a few. The paper focuses on architectures that are best suited to those applications and the trade-offs they generate. In this context, architectures are described that efficiently collect the output of single pixels when designed in large arrays. Off-chip readout circuit requirements are described for a variety of applications in physics, medicine and the life sciences. Owing to the dynamic nature of SPADs, designs featuring a large number of SPADs require careful analysis of the target application for an optimal use of silicon real estate and of limited readout bandwidth. The paper also describes the main trade-offs involved in architecting such chips and the solutions adopted with focus on scalability and miniaturization. PMID:24567470

Frequency jumps in single chip microwave LC oscillators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gualco, Gabriele; Grisi, Marco; Boero, Giovanni, E-mail: giovanni.boero@epfl.ch

2014-12-15

We report on the experimental observation of oscillation frequency jumps in microwave LC oscillators fabricated using standard complementary metal-oxide-semiconductor technologies. The LC oscillators, operating at a frequency of about 20 GHz, consist of a single turn planar coil, a metal-oxide-metal capacitor, and two cross-coupled metal-oxide-semiconductor field effect transistors used as negative resistance network. At 300 K as well as at 77 K, the oscillation frequency is a continuous function of the oscillator bias voltage. At 4 K, frequency jumps as large as 30 MHz are experimentally observed. This behavior is tentatively attributed to the emission and capture of single electrons from defects andmore » dopant atoms.« less

Method of physical vapor deposition of metal oxides on semiconductors

DOEpatents

Norton, David P.

2001-01-01

A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves the steps of heating the semiconductor surface and introducing hydrogen gas into the high-vacuum environment to develop conditions at the semiconductor surface which are favorable for growing the desired metal oxide upon the semiconductor surface yet is unfavorable for the formation of any native oxides upon the semiconductor. More specifically, the temperature of the semiconductor surface and the ratio of hydrogen partial pressure to water pressure within the vacuum environment are high enough to render the formation of native oxides on the semiconductor surface thermodynamically unstable yet are not so high that the formation of the desired metal oxide on the semiconductor surface is thermodynamically unstable. Having established these conditions, constituent atoms of the metal oxide to be deposited upon the semiconductor surface are directed toward the surface of the semiconductor by a physical vapor deposition technique so that the atoms come to rest upon the semiconductor surface as a thin film of metal oxide with no native oxide at the semiconductor surface/thin film interface. An example of a structure formed by this method includes an epitaxial thin film of (001)-oriented CeO.sub.2 overlying a substrate of (001) Ge.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

PubMed

Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

2015-07-16

We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

One-shot multivibrator with complementary metal-oxide-semiconductor components

NASA Technical Reports Server (NTRS)

Oneill, R. W.

1970-01-01

Breadboard model is tuned to produce output pulses from one microsecond up to several seconds in width with up to 95 percent duty cycle, and with lower power consumption than previously existing circuits.

Active pixel sensor array with multiresolution readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Kemeny, Sabrina E. (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

Video approach to chemiluminescence detection using a low-cost complementary metal oxide semiconductor (CMOS)-based camera: determination of paracetamol in pharmaceutical formulations.

PubMed

Lahuerta-Zamora, Luis; Mellado-Romero, Ana M

2017-06-01

A new system for continuous flow chemiluminescence detection, based on the use of a simple and low-priced lens-free digital camera (with complementary metal oxide semiconductor technology) as a detector, is proposed for the quantitative determination of paracetamol in commercial pharmaceutical formulations. Through the camera software, AVI video files of the chemiluminescence emission are captured and then, using friendly ImageJ public domain software (from National Institutes for Health), properly processed in order to extract the analytical information. The calibration graph was found to be linear over the range 0.01-0.10 mg L -1 and over the range 1.0-100.0 mg L -1 of paracetamol, the limit of detection being 10 μg L -1 . No significative interferences were found. Paracetamol was determined in three different pharmaceutical formulations: Termalgin®, Efferalgan® and Gelocatil®. The obtained results compared well with those declared on the formulation label and with those obtained through the official analytical method of British Pharmacopoeia. Graphical abstract Abbreviated scheme of the new chemiluminescence detection system proposed in this paper.

Potentiometric Dye Imaging for Pheochromocytoma and Cortical Neurons with a Novel Measurement System Using an Integrated Complementary Metal-Oxide-Semiconductor Imaging Device

NASA Astrophysics Data System (ADS)

Kobayashi, Takuma; Tagawa, Ayato; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Hatanaka, Yumiko; Tamura, Hideki; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2010-11-01

The combination of optical imaging with voltage-sensitive dyes is a powerful tool for studying the spatiotemporal patterns of neural activity and understanding the neural networks of the brain. To visualize the potential status of multiple neurons simultaneously using a compact instrument with high density and a wide range, we present a novel measurement system using an implantable biomedical photonic LSI device with a red absorptive light filter for voltage-sensitive dye imaging (BpLSI-red). The BpLSI-red was developed for sensing fluorescence by the on-chip LSI, which was designed by using complementary metal-oxide-semiconductor (CMOS) technology. A micro-electro-mechanical system (MEMS) microfabrication technique was used to postprocess the CMOS sensor chip; light-emitting diodes (LEDs) were integrated for illumination and to enable long-term cell culture. Using the device, we succeeded in visualizing the membrane potential of 2000-3000 cells and the process of depolarization of pheochromocytoma cells (PC12 cells) and mouse cerebral cortical neurons in a primary culture with cellular resolution. Therefore, our measurement application enables the detection of multiple neural activities simultaneously.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

SRAM As An Array Of Energetic-Ion Detectors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Lieneweg, Udo; Nixon, Robert H.

1993-01-01

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Siemens, Philips megaproject to yield superchip in 5 years

NASA Astrophysics Data System (ADS)

1985-02-01

The development of computer chips using complementary metal oxide semiconductor (CMOS) memory technology is described. The management planning and marketing strategy of the Philips and Siemens corporations with regard to the memory chip are discussed.

The heterogeneous integration of single-walled carbon nanotubes onto complementary metal oxide semiconductor circuitry for sensing applications.

PubMed

Chen, Chia-Ling; Agarwal, Vinay; Sonkusale, Sameer; Dokmeci, Mehmet R

2009-06-03

A simple methodology for integrating single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry is presented. The SWNTs were incorporated onto the CMOS chip as the feedback resistor of a two-stage Miller compensated operational amplifier utilizing dielectrophoretic assembly. The measured electrical properties from the integrated SWNTs yield ohmic behavior with a two-terminal resistance of approximately 37.5 kOmega and the measured small signal ac gain (-2) from the inverting amplifier confirmed successful integration of carbon nanotubes onto the CMOS circuitry. Furthermore, the temperature response of the SWNTs integrated onto CMOS circuitry has been measured and had a thermal coefficient of resistance (TCR) of -0.4% degrees C(-1). This methodology, demonstrated for the integration of SWNTs onto CMOS technology, is versatile, high yield and paves the way for the realization of novel miniature carbon-nanotube-based sensor systems.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

High-performance coatings for micromechanical mirrors.

PubMed

Gatto, Alexandre; Yang, Minghong; Kaiser, Norbert; Heber, Jörg; Schmidt, Jan Uwe; Sandner, Thilo; Schenk, Harald; Lakner, Hubert

2006-03-01

High-performance coatings for micromechanical mirrors were developed. The high-reflective metal systems can be integrated into the technology of MOEMS, such as spatial light modulators and microscanning mirrors from the near-infrared down to the vacuum-ultraviolet spectral regions. The reported metal designs permit high optical performances to be merged with suitable mechanical properties and fitting complementary metal-oxide semiconductor compatibility.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Atomic switches: atomic-movement-controlled nanodevices for new types of computing

PubMed Central

Hino, Takami; Hasegawa, Tsuyoshi; Terabe, Kazuya; Tsuruoka, Tohru; Nayak, Alpana; Ohno, Takeo; Aono, Masakazu

2011-01-01

Atomic switches are nanoionic devices that control the diffusion of metal cations and their reduction/oxidation processes in the switching operation to form/annihilate a metal atomic bridge, which is a conductive path between two electrodes in the on-state. In contrast to conventional semiconductor devices, atomic switches can provide a highly conductive channel even if their size is of nanometer order. In addition to their small size and low on-resistance, their nonvolatility has enabled the development of new types of programmable devices, which may achieve all the required functions on a single chip. Three-terminal atomic switches have also been developed, in which the formation and annihilation of a metal atomic bridge between a source electrode and a drain electrode are controlled by a third (gate) electrode. Three-terminal atomic switches are expected to enhance the development of new types of logic circuits, such as nonvolatile logic. The recent development of atomic switches that use a metal oxide as the ionic conductive material has enabled the integration of atomic switches with complementary metal-oxide-semiconductor (CMOS) devices, which will facilitate the commercialization of atomic switches. The novel characteristics of atomic switches, such as their learning and photosensing abilities, are also introduced in the latter part of this review. PMID:27877376

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Sathiyanarayanan, Rajesh; Kwon, Unoh; Narayanan, Vijay; Murali, K. V. R. M.

2013-07-01

We investigate the physical properties of a portion of the gate stack of an ultra-scaled complementary metal-oxide-semiconductor (CMOS) device. The effects of point defects, such as oxygen vacancy, oxygen, and aluminum interstitials at the HfO2/TiN interface, on the effective work function of TiN are explored using density functional theory. We compute the diffusion barriers of such point defects in the bulk TiN and across the HfO2/TiN interface. Diffusion of these point defects across the HfO2/TiN interface occurs during the device integration process. This results in variation of the effective work function and hence in the threshold voltage variation in the devices. Further, we simulate the effects of varying the HfO2/TiN interface stoichiometry on the effective work function modulation in these extremely-scaled CMOS devices. Our results show that the interface rich in nitrogen gives higher effective work function, whereas the interface rich in titanium gives lower effective work function, compared to a stoichiometric HfO2/TiN interface. This theoretical prediction is confirmed by the experiment, demonstrating over 700 meV modulation in the effective work function.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2011-01-01

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide–Semiconductor Image Sensors

PubMed Central

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-01-01

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components. PMID:28468324

Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

PubMed

Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

2017-10-02

Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Plasmonic nanohole arrays on Si-Ge heterostructures: an approach for integrated biosensors

NASA Astrophysics Data System (ADS)

Augel, L.; Fischer, I. A.; Dunbar, L. A.; Bechler, S.; Berrier, A.; Etezadi, D.; Hornung, F.; Kostecki, K.; Ozdemir, C. I.; Soler, M.; Altug, H.; Schulze, J.

2016-03-01

Nanohole array surface plasmon resonance (SPR) sensors offer a promising platform for high-throughput label-free biosensing. Integrating nanohole arrays with group-IV semiconductor photodetectors could enable low-cost and disposable biosensors compatible to Si-based complementary metal oxide semiconductor (CMOS) technology that can be combined with integrated circuitry for continuous monitoring of biosamples and fast sensor data processing. Such an integrated biosensor could be realized by structuring a nanohole array in the contact metal layer of a photodetector. We used Fouriertransform infrared spectroscopy to investigate nanohole arrays in a 100 nm Al film deposited on top of a vertical Si-Ge photodiode structure grown by molecular beam epitaxy (MBE). We find that the presence of a protein bilayer, constitute of protein AG and Immunoglobulin G (IgG), leads to a wavelength-dependent absorptance enhancement of ~ 8 %.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Note: A disposable x-ray camera based on mass produced complementary metal-oxide-semiconductor sensors and single-board computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoidn, Oliver R.; Seidler, Gerald T., E-mail: seidler@uw.edu

We have integrated mass-produced commercial complementary metal-oxide-semiconductor (CMOS) image sensors and off-the-shelf single-board computers into an x-ray camera platform optimized for acquisition of x-ray spectra and radiographs at energies of 2–6 keV. The CMOS sensor and single-board computer are complemented by custom mounting and interface hardware that can be easily acquired from rapid prototyping services. For single-pixel detection events, i.e., events where the deposited energy from one photon is substantially localized in a single pixel, we establish ∼20% quantum efficiency at 2.6 keV with ∼190 eV resolution and a 100 kHz maximum detection rate. The detector platform’s useful intrinsic energymore » resolution, 5-μm pixel size, ease of use, and obvious potential for parallelization make it a promising candidate for many applications at synchrotron facilities, in laser-heating plasma physics studies, and in laboratory-based x-ray spectrometry.« less

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

Vertical III-V nanowire device integration on Si(100).

PubMed

Borg, Mattias; Schmid, Heinz; Moselund, Kirsten E; Signorello, Giorgio; Gignac, Lynne; Bruley, John; Breslin, Chris; Das Kanungo, Pratyush; Werner, Peter; Riel, Heike

2014-01-01

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

The AMOS cell - An improved metal-semiconductor solar cell. [Antireflection coated Metal Oxide Semiconductor

NASA Technical Reports Server (NTRS)

Stirn, R. J.; Yeh, Y.-C. M.

1975-01-01

A new fabrication process is being developed which significantly improves the efficiency of metal-semiconductor solar cells. The resultant effect, a marked increase in the open-circuit voltage, is produced by the addition of an interfacial layer oxide on the semiconductor. Cells using gold on n-type gallium arsenide have been made in small areas (0.17 sq cm) with conversion efficiencies of 15% in terrestrial sunlight.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ao; Liu, Guoxia, E-mail: gxliu@qdu.edu.cn, E-mail: fukaishan@yahoo.com; Zhu, Huihui

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{submore » 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.« less

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

NASA Astrophysics Data System (ADS)

Yoshida, Takeshi; Sueishi, Katsuya; Iwata, Atsushi; Matsushita, Kojiro; Hirata, Masayuki; Suzuki, Takafumi

2011-04-01

This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal-oxide-silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process and occupies 0.09 mm2 on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1-100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.

CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

NASA Technical Reports Server (NTRS)

Fossum, Eric R.

1996-01-01

The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

New Mode For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.; Smith, Lawrence S.; Soli, George A.; Lo, Roger Y.

1988-01-01

Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.

An all-silicon passive optical diode.

PubMed

Fan, Li; Wang, Jian; Varghese, Leo T; Shen, Hao; Niu, Ben; Xuan, Yi; Weiner, Andrew M; Qi, Minghao

2012-01-27

A passive optical diode effect would be useful for on-chip optical information processing but has been difficult to achieve. Using a method based on optical nonlinearity, we demonstrate a forward-backward transmission ratio of up to 28 decibels within telecommunication wavelengths. Our device, which uses two silicon rings 5 micrometers in radius, is passive yet maintains optical nonreciprocity for a broad range of input power levels, and it performs equally well even if the backward input power is higher than the forward input. The silicon optical diode is ultracompact and is compatible with current complementary metal-oxide semiconductor processing.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Oxide semiconductor thin-film transistors: a review of recent advances.

PubMed

Fortunato, E; Barquinha, P; Martins, R

2012-06-12

Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

Cryogenic transimpedance amplifier for micromechanical capacitive sensors.

PubMed

Antonio, D; Pastoriza, H; Julián, P; Mandolesi, P

2008-08-01

We developed a cryogenic transimpedance amplifier that works at a broad range of temperatures, from room temperature down to 4 K. The device was realized with a standard complementary metal oxide semiconductor 1.5 mum process. Measurements of current-voltage characteristics, open-loop gain, input referred noise current, and power consumption are presented as a function of temperature. The transimpedance amplifier has been successfully applied to sense the motion of a polysilicon micromechanical oscillator at low temperatures. The whole device is intended to serve as a magnetometer for microscopic superconducting samples.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formedmore » with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.« less

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Investigation of Gallium Nitride Transistor Reliability through Accelerated Life Testing and Modeling

DTIC Science & Technology

2011-12-01

Carbon Cd Cadmium CdS Cadmium Sulfide CMOS Complementary Metal Oxide Semiconductor DC Direct Current DoD Department of Defense EBL Electron...Crane Division [NAVSEA Crane], Crane, Indiana ) are Section 4.1and Section 4.3, Condition 2. Eight devices were stressed for over 1000 hours each and

FIFO Buffer for Asynchronous Data Streams

NASA Technical Reports Server (NTRS)

Bascle, K. P.

1985-01-01

Variable-rate, asynchronous data signals from up to four measuring instruments or other sources combined in first-in/first-out (FIFO) buffer for transmission on single channel. Constructed in complementary metal-oxide-semiconductor (CMOS) logic, buffer consumes low power (only 125 mW at 5V) and conforms to aerospace standards of reliability and maintainability.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

An airborne multispectral imaging system based on two consumer-grade cameras for agricultural remote sensing

USDA-ARS?s Scientific Manuscript database

This paper describes the design and evaluation of an airborne multispectral imaging system based on two identical consumer-grade cameras for agricultural remote sensing. The cameras are equipped with a full-frame complementary metal oxide semiconductor (CMOS) sensor with 5616 × 3744 pixels. One came...

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Polymer waveguide grating sensor integrated with a thin-film photodetector

PubMed Central

Song, Fuchuan; Xiao, Jing; Xie, Antonio Jou; Seo, Sang-Woo

2014-01-01

This paper presents a planar waveguide grating sensor integrated with a photodetector (PD) for on-chip optical sensing systems which are suitable for diagnostics in the field and in-situ measurements. III–V semiconductor-based thin-film PD is integrated with a polymer based waveguide grating device on a silicon platform. The fabricated optical sensor successfully discriminates optical spectral characteristics of the polymer waveguide grating from the on-chip PD. In addition, its potential use as a refractive index sensor is demonstrated. Based on a planar waveguide structure, the demonstrated sensor chip may incorporate multiple grating waveguide sensing regions with their own optical detection PDs. In addition, the demonstrated processing is based on a post-integration process which is compatible with silicon complementary metal-oxide semiconductor (CMOS) electronics. Potentially, this leads a compact, chip-scale optical sensing system which can monitor multiple physical parameters simultaneously without need for external signal processing. PMID:24466407

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

A metallic metal oxide (Ti5O9)-metal oxide (TiO2) nanocomposite as the heterojunction to enhance visible-light photocatalytic activity

NASA Astrophysics Data System (ADS)

Li, L. H.; Deng, Z. X.; Xiao, J. X.; Yang, G. W.

2015-06-01

Coupling titanium dioxide (TiO2) with other semiconductors is a popular method to extend the optical response range of TiO2 and improve its photon quantum efficiency, as coupled semiconductors can increase the separation rate of photoinduced charge carriers in photocatalysts. Differing from normal semiconductors, metallic oxides have no energy gap separating occupied and unoccupied levels, but they can excite electrons between bands to create a high carrier mobility to facilitate kinetic charge separation. Here, we propose the first metallic metal oxide-metal oxide (Ti5O9-TiO2) nanocomposite as a heterojunction for enhancing the visible-light photocatalytic activity of TiO2 nanoparticles and we demonstrate that this hybridized TiO2-Ti5O9 nanostructure possesses an excellent visible-light photocatalytic performance in the process of photodegrading dyes. The TiO2-Ti5O9 nanocomposites are synthesized in one step using laser ablation in liquid under ambient conditions. The as-synthesized nanocomposites show strong visible-light absorption in the range of 300-800 nm and high visible-light photocatalytic activity in the oxidation of rhodamine B. They also exhibit excellent cycling stability in the photodegrading process. A working mechanism for the metallic metal oxide-metal oxide nanocomposite in the visible-light photocatalytic process is proposed based on first-principle calculations of Ti5O9. This study suggests that metallic metal oxides can be regarded as partners for metal oxide photocatalysts in the construction of heterojunctions to improve photocatalytic activity.

A metallic metal oxide (Ti5O9)-metal oxide (TiO2) nanocomposite as the heterojunction to enhance visible-light photocatalytic activity.

PubMed

Li, L H; Deng, Z X; Xiao, J X; Yang, G W

2015-01-26

Coupling titanium dioxide (TiO2) with other semiconductors is a popular method to extend the optical response range of TiO2 and improve its photon quantum efficiency, as coupled semiconductors can increase the separation rate of photoinduced charge carriers in photocatalysts. Differing from normal semiconductors, metallic oxides have no energy gap separating occupied and unoccupied levels, but they can excite electrons between bands to create a high carrier mobility to facilitate kinetic charge separation. Here, we propose the first metallic metal oxide-metal oxide (Ti5O9-TiO2) nanocomposite as a heterojunction for enhancing the visible-light photocatalytic activity of TiO2 nanoparticles and we demonstrate that this hybridized TiO2-Ti5O9 nanostructure possesses an excellent visible-light photocatalytic performance in the process of photodegrading dyes. The TiO2-Ti5O9 nanocomposites are synthesized in one step using laser ablation in liquid under ambient conditions. The as-synthesized nanocomposites show strong visible-light absorption in the range of 300-800 nm and high visible-light photocatalytic activity in the oxidation of rhodamine B. They also exhibit excellent cycling stability in the photodegrading process. A working mechanism for the metallic metal oxide-metal oxide nanocomposite in the visible-light photocatalytic process is proposed based on first-principle calculations of Ti5O9. This study suggests that metallic metal oxides can be regarded as partners for metal oxide photocatalysts in the construction of heterojunctions to improve photocatalytic activity.

An ultra-low-voltage electronic implementation of inertial neuron model with nonmonotonous Liao's activation function.

PubMed

Kant, Nasir Ali; Dar, Mohamad Rafiq; Khanday, Farooq Ahmad

2015-01-01

The output of every neuron in neural network is specified by the employed activation function (AF) and therefore forms the heart of neural networks. As far as the design of artificial neural networks (ANNs) is concerned, hardware approach is preferred over software one because it promises the full utilization of the application potential of ANNs. Therefore, besides some arithmetic blocks, designing AF in hardware is the most important for designing ANN. While attempting to design the AF in hardware, the designs should be compatible with the modern Very Large Scale Integration (VLSI) design techniques. In this regard, the implemented designs should: only be in Metal Oxide Semiconductor (MOS) technology in order to be compatible with the digital designs, provide electronic tunability feature, and be able to operate at ultra-low voltage. Companding is one of the promising circuit design techniques for achieving these goals. In this paper, 0.5 V design of Liao's AF using sinh-domain technique is introduced. Furthermore, the function is tested by implementing inertial neuron model. The performance of the AF and inertial neuron model have been evaluated through simulation results, using the PSPICE software with the MOS transistor models provided by the 0.18-μm Taiwan Semiconductor Manufacturer Complementary Metal Oxide Semiconductor (TSM CMOS) process.

Invisible two-dimensional barcode fabrication inside a synthetic fused silica by femtosecond laser processing using a computer-generated hologram

NASA Astrophysics Data System (ADS)

Kawashima, Hayato; Yamaji, Masahiro; Suzuki, Jun'ichi; Tanaka, Shuhei

2011-03-01

We report an invisible two-dimensional (2D) barcode embedded into a synthetic fused silica by femtosecond laser processing using a computer-generated hologram (CGH) that generates a spatially extended femtosecond pulse beam in the depth direction. When we illuminate the irradiated 2D barcode pattern with a 254 nm ultraviolet (UV) light, a strong red photoluminescence (PL) is observed, and we can read it by using a complementary metal oxide semiconductor (CMOS) camera and image processing technology. This work provides a novel barcode fabrication method by femtosecond laser processing using a CGH and a barcode reading method by a red PL.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-01-01

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90 %RH. PMID:25353984

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Upper-Bound Estimates Of SEU in CMOS

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

1990-01-01

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

PubMed

Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

2017-04-12

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10 6 , effective mobility up to 30 cm 2 V -1 s -1 , small hysteresis, and small subthreshold swing (90-140 mV dec -1 ), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V dd = 1 V) and a voltage gain as high as 30 (at V dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Patterning and templating for nanoelectronics.

PubMed

Galatsis, Kosmas; Wang, Kang L; Ozkan, Mihri; Ozkan, Cengiz S; Huang, Yu; Chang, Jane P; Monbouquette, Harold G; Chen, Yong; Nealey, Paul; Botros, Youssry

2010-02-09

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Vertical Isolation for Photodiodes in CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2008-01-01

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Ageing and proton irradiation damage of a low voltage EMCCD in a CMOS process

NASA Astrophysics Data System (ADS)

Dunford, A.; Stefanov, K.; Holland, A.

2018-02-01

Electron Multiplying Charge Coupled Devices (EMCCDs) have revolutionised low light level imaging, providing highly sensitive detection capabilities. Implementing Electron Multiplication (EM) in Charge Coupled Devices (CCDs) can increase the Signal to Noise Ratio (SNR) and lead to further developments in low light level applications such as improvements in image contrast and single photon imaging. Demand has grown for EMCCD devices with properties traditionally restricted to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, such as lower power consumption and higher radiation tolerance. However, EMCCDs are known to experience an ageing effect, such that the gain gradually decreases with time. This paper presents results detailing EM ageing in an Electron Multiplying Complementary Metal-Oxide-Semiconductor (EMCMOS) device and its effect on several device characteristics such as Charge Transfer Inefficiency (CTI) and thermal dark signal. When operated at room temperature an average decrease in gain of over 20% after an operational period of 175 hours was detected. With many image sensors deployed in harsh radiation environments, the radiation hardness of the device following proton irradiation was also tested. This paper presents the results of a proton irradiation completed at the Paul Scherrer Institut (PSI) at a 10 MeV equivalent fluence of 4.15× 1010 protons/cm2. The pre-irradiation characterisation, irradiation methodology and post-irradiation results are detailed, demonstrating an increase in dark current and a decrease in its activation energy. Finally, this paper presents a comparison of the damage caused by EM gain ageing and proton irradiation.

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

PubMed

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

NASA Astrophysics Data System (ADS)

Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

CMOS array design automation techniques. [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Ramondetta, P.; Feller, A.; Noto, R.; Lombardi, T.

1975-01-01

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Wobbly strings: calculating the capture rate of a webcam using the rolling shutter effect in a guitar

NASA Astrophysics Data System (ADS)

Cunnah, David

2014-07-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Wobbly Strings: Calculating the Capture Rate of a Webcam Using the Rolling Shutter Effect in a Guitar

ERIC Educational Resources Information Center

Cunnah, David

2014-01-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

An optical relay approach to very low cost hybrid polymer-complementary metal-oxide semiconductor electrophoresis instrumentation.

PubMed

Hall, Gordon H; Sloan, David L; Ma, Tianchi; Couse, Madeline H; Martel, Stephane; Elliott, Duncan G; Glerum, D Moira; Backhouse, Christopher J

2014-07-04

Electrophoresis is an integral part of many molecular diagnostics protocols and an inexpensive implementation would greatly facilitate point-of-care (POC) applications. However, the high instrumentation cost presents a substantial barrier, much of it associated with fluorescence detection. The cost of such systems could be substantially reduced by placing the fluidic channel and photodiode directly above the detector in order to collect a larger portion of the fluorescent light. In future, this could be achieved through the integration and monolithic fabrication of photoresist microchannels on complementary metal-oxide semiconductor microelectronics (CMOS). However, the development of such a device is expensive due to high non-recurring engineering costs. To facilitate that development, we present a system that utilises an optical relay to integrate low-cost polymeric microfluidics with a CMOS chip that provides a photodiode, analog-digital conversion and a standard serial communication interface. This system embodies an intermediate level of microelectronic integration, and significantly decreases development costs. With a limit of detection of 1.3±0.4nM of fluorescently end-labeled deoxyribonucleic acid (DNA), it is suitable for diagnostic applications. Copyright © 2014 Elsevier B.V. All rights reserved.

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

NASA Astrophysics Data System (ADS)

Lu, Y.; Tang, H.; Fung, S.; Wang, Q.; Tsai, J. M.; Daneman, M.; Boser, B. E.; Horsley, D. A.

2015-06-01

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ˜14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Low-Temperature UV-Assisted Fabrication of Metal Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Zhu, Shuanglin

Solution processed metal oxide semiconductors have attracted intensive attention in the last several decades and have emerged as a promising candidate for the application of thin film transistor (TFT) due to their nature of transparency, flexibility, high mobility, simple processing technique and potential low manufacturing cost. However, metal oxide thin film fabricated by solution process usually requires a high temperature (over 300 °C), which is above the glass transition temperature of some conventional polymer substrates. In order to fabricate the flexible electronic device on polymer substrates, it is necessary to find a facile approach to lower the fabrication temperature and minimize defects in metal oxide thin film. In this thesis, the electrical properties dependency on temperature is discussed and an UV-assisted annealing method incorporating Deep ultraviolet (DUV)-decomposable additives is demonstrated, which can effectively improve electrical properties solution processed metal oxide semiconductors processed at temperature as low as 220 °C. By studying a widely used indium oxide (In2O3) TFT as a model system, it is worth noted that compared with the sample without UV treatment, the linear mobility and saturation mobility of UV-annealing sample are improved by 56% and 40% respectively. Meanwhile, the subthreshold swing is decreased by 32%, indicating UV-treated device could turn on and off more efficiently. In addition to pure In2O3 film, the similar phenomena have also been observed in indium oxide based Indium-Gallium-Zinc Oxide (IGZO) system. These finding presented in this thesis suggest that the UV assisted annealing process open a new route to fabricate high performance metal oxide semiconductors under low temperatures.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

Sub-100 μm scale on-chip inductors with CoZrTa for GHz applications

NASA Astrophysics Data System (ADS)

Xu, Wei; Wu, Hao; Gardner, Donald S.; Sinha, Saurabh; Dastagir, Tawab; Bakkaloglu, Bertan; Cao, Yu; Yu, Hongbin

2011-04-01

On-chip inductors with magnetic material are fabricated with complementary metal-oxide semiconductor processes. The inductors use copper metallization and amorphous CoZrTa thinfilms. Enhancements of 3.5X in inductance and 3X for the quality factor at frequencies as highas 3 GHz have been successfully demonstrated by using a continuous CoZrTa-ring structure in spiral inductors at the 100 μm scale. Further improvement of the frequency response of inductance up to 6 GHz was achieved by micro-patterning the magnetic film. The effect ofincreasing the film thickness on the performance of strip line inductors was measured and modeled. This work demonstrates significantly larger increases in inductance and quality factor atabove 1 GHz as compared to prior efforts, thereby making the added processing cost worthwhile.

On-Chip Optical Nonreciprocity Using an Active Microcavity

PubMed Central

Jiang, Xiaoshun; Yang, Chao; Wu, Hongya; Hua, Shiyue; Chang, Long; Ding, Yang; Hua, Qian; Xiao, Min

2016-01-01

Optically nonreciprocal devices provide critical functionalities such as light isolation and circulation in integrated photonic circuits for optical communications and information processing, but have been difficult to achieve. By exploring gain-saturation nonlinearity, we demonstrate on-chip optical nonreciprocity with excellent isolation performance within telecommunication wavelengths using only one toroid microcavity. Compatible with current complementary metal-oxide-semiconductor process, our compact and simple scheme works for a very wide range of input power levels from ~10 microwatts down to ~10 nanowatts, and exhibits remarkable properties of one-way light transport with sufficiently low insertion loss. These superior features make our device become a promising critical building block indispensable for future integrated nanophotonic networks. PMID:27958356

Noise and linearity optimization methods for a 1.9GHz low noise amplifier.

PubMed

Guo, Wei; Huang, Da-Quan

2003-01-01

Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

Silicon-nanocrystal Optoelectronic Kerr Effect for Complementary Metal-oxide Semiconductor (CMOS) Compatible Optical Switching

DTIC Science & Technology

2011-04-01

changes the material’s index of refraction via dispersion . This absorption requires carrier transport and, in present implementations, suffers from slow...designed to take advantage of the large Kerr effect that has been reported in Si-nanocrystals imbedded in oxide (Si-nc). The expected refractive index ...estimate of the expected refractive index change versus applied voltage. An index change of ~2 x 10–4 is enough to modulate the light, corresponding to a

Control of GaAs Microwave Schottky Diode Electrical Characteristics by Contact Geometry: The Gap Diode.

DTIC Science & Technology

1982-05-01

semiconductor Schottky-barrier contacts are used in many semiconductor devices, including switches, rectifiers, varactors , IMPATTs, mixer and detector...ionic materials such as most of the II-VI compound semiconductors (e.g. ZnS and ZnO) and the transition-metal oxides , the barrier height is strongly...the alloying process described above is nonuniformity, due to the incomplete removal of residual surface oxides prior to the evaporation of the metal

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-07-17

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

NASA Astrophysics Data System (ADS)

Yoon, Bongno; Sung, Man Young; Yeon, Sujin; Oh, Hyun S.; Kwon, Yoonjoo; Kim, Chuljin; Kim, Kyung-Ho

2009-03-01

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag's persistence times (Tpt) for each session (S0-S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

Conductance Quantization in Resistive Random Access Memory

NASA Astrophysics Data System (ADS)

Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

2015-10-01

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

Conductance Quantization in Resistive Random Access Memory.

PubMed

Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

2015-12-01

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE PAGES

Wang, Lei; Yan, Danhua; Shaffer, David W.; ...

2017-12-27

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Improved Stability and Performance of Visible Photoelectrochemical Water Splitting on Solution-Processed Organic Semiconductor Thin Films by Ultrathin Metal Oxide Passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Lei; Yan, Danhua; Shaffer, David W.

Solution-processable organic semiconductors have potentials as visible photoelectrochemical (PEC) water splitting photoelectrodes due to their tunable small band gap and electronic energy levels, but they are typically limited by poor stability and photocatalytic activity. In this study, we demonstrate the direct visible PEC water oxidation on solution-processed organic semiconductor thin films with improved stability and performance by ultrathin metal oxide passivation layers. N-type fullerene-derivative thin films passivated by sub-2 nm ZnO via atomic layer deposition enabled the visible PEC water oxidation at wavelengths longer than 600 nm in harsh alkaline electrolyte environments with up to 30 μA/cm 2 photocurrents atmore » the thermodynamic water-oxidation equilibrium potential and the photoanode half-lifetime extended to ~1000 s. The systematic investigation reveals the enhanced water oxidation catalytic activity afforded by ZnO passivation and the charge tunneling governing the hole transfer through passivation layers. Further enhanced PEC performances were realized by improving the bottom ohmic contact to the organic semiconductor, achieving ~60 μA/cm 2 water oxidation photocurrent at the equilibrium potential, the highest values reported for organic semiconductor thin films to our knowledge. The improved stability and performance of passivated organic photoelectrodes and discovered design rationales provide useful guidelines for realizing the stable visible solar PEC water splitting based on organic semiconductor thin films.« less

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

PubMed Central

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively. PMID:22294897

Cobalt oxide nanosheet and CNT micro carbon monoxide sensor integrated with readout circuit on chip.

PubMed

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

Radiation Response of Emerging FeRAM Technology

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Scheick, L. Z.

2001-01-01

The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

An underlap field-effect transistor for electrical detection of influenza

NASA Astrophysics Data System (ADS)

Lee, Kwang-Won; Choi, Sung-Jin; Ahn, Jae-Hyuk; Moon, Dong-Il; Park, Tae Jung; Lee, Sang Yup; Choi, Yang-Kyu

2010-01-01

An underlap channel-embedded field-effect transistor (FET) is proposed for label-free biomolecule detection. Specifically, silica binding protein fused with avian influenza (AI) surface antigen and avian influenza antibody (anti-AI) were designed as a receptor molecule and a target material, respectively. The drain current was significantly decreased after the binding of negatively charged anti-AI on the underlap channel. A set of control experiments supports that only the biomolecules on the underlap channel effectively modulate the drain current. With the merits of a simple fabrication process, complementary metal-oxide-semiconductor compatibility, and enhanced sensitivity, the underlap FET could be a promising candidate for a chip-based biosensor.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Ultralow-Loss CMOS Copper Plasmonic Waveguides.

PubMed

Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

2016-01-13

Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter.

PubMed

Huang, Jun; Somu, Sivasubramanian; Busnaina, Ahmed

2012-08-24

We report a simple, bottom-up/top-down approach for integrating drastically different nanoscale building blocks to form a heterogeneous complementary inverter circuit based on layered molybdenum disulfide and carbon nanotube (CNT) bundles. The fabricated CNT/MoS(2) inverter is composed of n-type molybdenum disulfide (MOS(2)) and p-type CNT transistors, with a high voltage gain of 1.3. The CNT channels are fabricated using directed assembly while the layered molybdenum disulfide channels are fabricated by mechanical exfoliation. This bottom-up fabrication approach for integrating various nanoscale elements with unique characteristics provides an alternative cost-effective methodology to complementary metal-oxide-semiconductors, laying the foundation for the realization of high performance logic circuits.

Experimental identification of nitrogen-vacancy complexes in nitrogen implanted silicon

NASA Astrophysics Data System (ADS)

Adam, Lahir Shaik; Law, Mark E.; Szpala, Stanislaw; Simpson, P. J.; Lawther, Derek; Dokumaci, Omer; Hegde, Suri

2001-07-01

Nitrogen implantation is commonly used in multigate oxide thickness processing for mixed signal complementary metal-oxide-semiconductor and System on a Chip technologies. Current experiments and diffusion models indicate that upon annealing, implanted nitrogen diffuses towards the surface. The mechanism proposed for nitrogen diffusion is the formation of nitrogen-vacancy complexes in silicon, as indicated by ab initio studies by J. S. Nelson, P. A. Schultz, and A. F. Wright [Appl. Phys. Lett. 73, 247 (1998)]. However, to date, there does not exist any experimental evidence of nitrogen-vacancy formation in silicon. This letter provides experimental evidence through positron annihilation spectroscopy that nitrogen-vacancy complexes indeed form in nitrogen implanted silicon, and compares the experimental results to the ab initio studies, providing qualitative support for the same.

Chemically Derivatized Semiconductor Photoelectrodes.

ERIC Educational Resources Information Center

Wrighton, Mark S.

1983-01-01

Deliberate modification of semiconductor photoelectrodes to improve durability and enhance rate of desirable interfacial redox processes is discussed for a variety of systems. Modification with molecular-based systems or with metals/metal oxides yields results indicating an important role for surface modification in devices for fundamental study…

Nanostructure-directed physisorption vs chemisorption at semiconductor interfaces: the inverse of the HSAB concept.

PubMed

Gole, James L; Ozdemir, Serdar

2010-08-23

A concept, complementary to that of hard and soft acid-base interactions (HSAB-dominant chemisorption) and consistent with dominant physisorption to a semiconductor interface, is presented. We create a matrix of sensitivities and interactions with several basic gases. The concept, based on the reversible interaction of hard-acid surfaces with soft bases, hard-base surfaces with soft acids, or vice versa, corresponds 1) to the inverse of the HSAB concept and 2) to the selection of a combination of semiconductor interface and analyte materials, which can be used to direct a physisorbed vs chemisorbed interaction. The technology, implemented on nanopore coated porous silicon micropores, results in the coupling of acid-base chemistry with the depletion or enhancement of majority carriers in an extrinsic semiconductor. Using the inverse-HSAB (IHSAB) concept, significant and predictable changes in interface sensitivity for a variety of gases can be implemented. Nanostructured metal oxide particle depositions provide selectivity and complement a highly efficient electrical contact to a porous silicon nanopore covered microporous interface. The application of small quantities (much less than a monolayer) of nanostructured metals, metal oxides, and catalysts which focus the physisorbtive and chemisorbtive interactions of the interface, can be made to create a range of notably higher sensitivities for reversible physisorption. This is exemplified by an approach to reversible, sensitive, and selective interface responses. Nanostructured metal oxides developed from electroless gold (Au(x)O), tin (SnO(2)), copper (Cu(x)O), and nickel (NiO) depositions, nanoalumina, and nanotitania are used to demonstrate the IHSAB concept and provide for the detection of gases, including NH(3), PH(3), CO, NO, and H(2)S, in an array-based format to the sub-ppm level.

An Autonomous Circuit for the Measurement of Photovoltaic Devices Parameters.

DTIC Science & Technology

1986-09-01

Comparison Data, Gallium Arsenide ................ 80 A 7 A,. TABLE OF SYMBOLS A Curve Fitting Constant ADC Analog to Digital Converter AMO Air-Mass-Zero...in Radiation Fluence in the Logarithmic Region CMOS Complementary Metal-Oxide Semiconductor DAC Digital to Analog Converter DC Direct Current Dp Hole...characteristics of individual solar cells. A novel circuit is developed that uses a microprocessor controlled Digital to Analog Converter (DAC) to obtain

Radiation Status of Sub-65 nm Electronics

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.

2011-01-01

Ultra-scaled complementary metal oxide semiconductor (CMOS) includes commercial foundry capabilities at and below the 65 nm technology node Radiation evaluations take place using standard products and test characterization vehicles (memories, logic/latch chains, etc.) NEPP focus is two-fold: (1) Conduct early radiation evaluations to ascertain viability for future NASA missions (i.e. leverage commercial technology development). (2) Uncover gaps in current testing methodologies and mechanism comprehension -- early risk mitigation.

CMOS Camera Array With Onboard Memory

NASA Technical Reports Server (NTRS)

Gat, Nahum

2009-01-01

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Y.; Fung, S.; Wang, Q.

2015-06-29

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ∼14 kPa with a 28 V input, in reasonable agreement with predication from analyticalmore » calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.« less

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Real time in vivo imaging and measurement of serine protease activity in the mouse hippocampus using a dedicated complementary metal-oxide semiconductor imaging device.

PubMed

Ng, David C; Tamura, Hideki; Tokuda, Takashi; Yamamoto, Akio; Matsuo, Masamichi; Nunoshita, Masahiro; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2006-09-30

The aim of the present study is to demonstrate the application of complementary metal-oxide semiconductor (CMOS) imaging technology for studying the mouse brain. By using a dedicated CMOS image sensor, we have successfully imaged and measured brain serine protease activity in vivo, in real-time, and for an extended period of time. We have developed a biofluorescence imaging device by packaging the CMOS image sensor which enabled on-chip imaging configuration. In this configuration, no optics are required whereby an excitation filter is applied onto the sensor to replace the filter cube block found in conventional fluorescence microscopes. The fully packaged device measures 350 microm thick x 2.7 mm wide, consists of an array of 176 x 144 pixels, and is small enough for measurement inside a single hemisphere of the mouse brain, while still providing sufficient imaging resolution. In the experiment, intraperitoneally injected kainic acid induced upregulation of serine protease activity in the brain. These events were captured in real time by imaging and measuring the fluorescence from a fluorogenic substrate that detected this activity. The entire device, which weighs less than 1% of the body weight of the mouse, holds promise for studying freely moving animals.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

High-Speed Binary-Output Image Sensor

NASA Technical Reports Server (NTRS)

Fossum, Eric; Panicacci, Roger A.; Kemeny, Sabrina E.; Jones, Peter D.

1996-01-01

Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.

Micrometer-scale fabrication of complex three dimensional lattice + basis structures in silicon

DOE PAGES

Burckel, D. Bruce; Resnick, Paul J.; Finnegan, Patrick S.; ...

2015-01-01

A complementary metal oxide semiconductor (CMOS) compatible version of membrane projection lithography (MPL) for fabrication of micrometer-scale three-dimensional structures is presented. The approach uses all inorganic materials and standard CMOS processing equipment. In a single layer, MPL is capable of creating all 5 2D-Bravais lattices. Furthermore, standard semiconductor processing steps can be used in a layer-by-layer approach to create fully three dimensional structures with any of the 14 3D-Bravais lattices. The unit cell basis is determined by the projection of the membrane pattern, with many degrees of freedom for defining functional inclusions. Here we demonstrate several unique structural motifs, andmore » characterize 2D arrays of unit cells with split ring resonators in a silicon matrix. The structures exhibit strong polarization dependent resonances and, for properly oriented split ring resonators (SRRs), coupling to the magnetic field of a normally incident transverse electromagnetic wave, a response unique to 3D inclusions.« less

In Situ Chemical Modification of Schottky Barrier in Solution-Processed Zinc Tin Oxide Diode.

PubMed

Son, Youngbae; Li, Jiabo; Peterson, Rebecca L

2016-09-14

Here we present a novel in situ chemical modification process to form vertical Schottky diodes using palladium (Pd) rectifying bottom contacts, amorphous zinc tin oxide (Zn-Sn-O) semiconductor made via acetate-based solution process, and molybdenum top ohmic contacts. Using X-ray photoelectron spectroscopy depth profiling, we show that oxygen plasma treatment of Pd creates a PdOx interface layer, which is then reduced back to metallic Pd by in situ reactions during Zn-Sn-O film annealing. The plasma treatment ensures an oxygen-rich environment in the semiconductor near the Schottky barrier, reducing the level of oxygen-deficiency-related defects and improving the rectifying contact. Using this process, we achieve diodes with high forward current density exceeding 10(3)A cm(-2) at 1 V, rectification ratios of >10(2), and ideality factors of around 1.9. The measured diode current-voltage characteristics are compared to numerical simulations of thermionic field emission with sub-bandgap states in the semiconductor, which we attribute to spatial variations in metal stoichiometry of amorphous Zn-Sn-O. To the best of our knowledge, this is the first demonstration of vertical Schottky diodes using solution-processed amorphous metal oxide semiconductor. Furthermore, the in situ chemical modification method developed here can be adapted to tune interface properties in many other oxide devices.

Semiconductor assisted metal deposition for nanolithography applications

DOEpatents

Rajh, Tijana; Meshkov, Natalia; Nedelijkovic, Jovan M.; Skubal, Laura R.; Tiede, David M.; Thurnauer, Marion

2001-01-01

An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Semiconductor assisted metal deposition for nanolithography applications

DOEpatents

Rajh, Tijana; Meshkov, Natalia; Nedelijkovic, Jovan M.; Skubal, Laura R.; Tiede, David M.; Thurnauer, Marion

2002-01-01

An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Stable surface passivation process for compound semiconductors

DOEpatents

Ashby, Carol I. H.

2001-01-01

A passivation process for a previously sulfided, selenided or tellurated III-V compound semiconductor surface. The concentration of undesired mid-gap surface states on a compound semiconductor surface is reduced by the formation of a near-monolayer of metal-(sulfur and/or selenium and/or tellurium)-semiconductor that is effective for long term passivation of the underlying semiconductor surface. Starting with the III-V compound semiconductor surface, any oxidation present thereon is substantially removed and the surface is then treated with sulfur, selenium or tellurium to form a near-monolayer of chalcogen-semiconductor of the surface in an oxygen-free atmosphere. This chalcogenated surface is then contacted with a solution of a metal that will form a low solubility chalcogenide to form a near-monolayer of metal-chalcogen-semiconductor. The resulting passivating layer provides long term protection for the underlying surface at or above the level achieved by a freshly chalcogenated compound semiconductor surface in an oxygen free atmosphere.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Silicon Cations Intermixed Indium Zinc Oxide Interface for High-Performance Thin-Film Transistors Using a Solution Process.

PubMed

Na, Jae Won; Rim, You Seung; Kim, Hee Jun; Lee, Jin Hyeok; Hong, Seonghwan; Kim, Hyun Jae

2017-09-06

Solution-processed amorphous metal-oxide thin-film transistors (TFTs) utilizing an intermixed interface between a metal-oxide semiconductor and a dielectric layer are proposed. In-depth physical characterizations are carried out to verify the existence of the intermixed interface that is inevitably formed by interdiffusion of cations originated from a thermal process. In particular, when indium zinc oxide (IZO) semiconductor and silicon dioxide (SiO 2 ) dielectric layer are in contact and thermally processed, a Si 4+ intermixed IZO (Si/IZO) interface is created. On the basis of this concept, a high-performance Si/IZO TFT having both a field-effect mobility exceeding 10 cm 2 V -1 s -1 and a on/off current ratio over 10 7 is successfully demonstrated.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, G.; Li, S.; D'Andragora, A.

We present a front-end application-specific integrated circuit (ASIC) for a wire based time-projection-chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline neutrino oscillation experiments. The ASIC must provide a low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MSamples/s, compression, buffering and multiplexing. A resolution of better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We include the characterization of a commercial technology for operationmore » in the cryogenic environment and the first experimental results on the analog front end. The results demonstrate that complementary metal-oxide semiconductor transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of '1/f equivalent' to model the low-frequency component of the noise spectral density, for use in the input metal-oxide semiconductor field-effect transistor optimization.« less

Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

PubMed

Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

2015-08-01

This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

NASA Astrophysics Data System (ADS)

Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

2006-01-01

We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

DOEpatents

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji Won; Rondinone, Adam J.; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2014-06-24

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component containing at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Progress in ion torrent semiconductor chip based sequencing.

PubMed

Merriman, Barry; Rothberg, Jonathan M

2012-12-01

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Determination of Insulator-to-Semiconductor Transition in Sol-Gel Oxide Semiconductors Using Derivative Spectroscopy.

PubMed

Lee, Woobin; Choi, Seungbeom; Kim, Kyung Tae; Kang, Jingu; Park, Sung Kyu; Kim, Yong-Hoon

2015-12-23

We report a derivative spectroscopic method for determining insulator-to-semiconductor transition during sol-gel metal-oxide semiconductor formation. When an as-spun sol-gel precursor film is photochemically activated and changes to semiconducting state, the light absorption characteristics of the metal-oxide film is considerable changed particularly in the ultraviolet region. As a result, a peak is generated in the first-order derivatives of light absorption ( A' ) vs. wavelength (λ) plots, and by tracing the peak center shift and peak intensity, transition from insulating-to-semiconducting state of the film can be monitored. The peak generation and peak center shift are described based on photon-energy-dependent absorption coefficient of metal-oxide films. We discuss detailed analysis method for metal-oxide semiconductor films and its application in thin-film transistor fabrication. We believe this derivative spectroscopy based determination can be beneficial for a non-destructive and a rapid monitoring of the insulator-to-semiconductor transition in sol-gel oxide semiconductor formation.

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation.

PubMed

Amor, S; André, N; Kilchytska, V; Tounsi, F; Mezghani, B; Gérard, P; Ali, Z; Udrea, F; Flandre, D; Francis, L A

2017-05-05

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation

NASA Astrophysics Data System (ADS)

Amor, S.; André, N.; Kilchytska, V.; Tounsi, F.; Mezghani, B.; Gérard, P.; Ali, Z.; Udrea, F.; Flandre, D.; Francis, L. A.

2017-05-01

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors.

PubMed

Cho, Ah-Jin; Park, Kee Chan; Kwon, Jang-Yeon

2015-01-01

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Tungsten Contact and Line Resistance Reduction with Advanced Pulsed Nucleation Layer and Low Resistivity Tungsten Treatment

NASA Astrophysics Data System (ADS)

Chandrashekar, Anand; Chen, Feng; Lin, Jasmine; Humayun, Raashina; Wongsenakhum, Panya; Chang, Sean; Danek, Michal; Itou, Takamasa; Nakayama, Tomoo; Kariya, Atsushi; Kawaguchi, Masazumi; Hizume, Shunichi

2010-09-01

This paper describes electrical testing results of new tungsten chemical vapor deposition (CVD-W) process concepts that were developed to address the W contact and bitline scaling issues on 55 nm node devices. Contact resistance (Rc) measurements in complementary metal oxide semiconductor (CMOS) devices indicate that the new CVD-W process for sub-32 nm and beyond - consisting of an advanced pulsed nucleation layer (PNL) combined with low resistivity tungsten (LRW) initiation - produces a 20-30% drop in Rc for diffused NiSi contacts. From cross-sectional bright field and dark field transmission electron microscopy (TEM) analysis, such Rc improvement can be attributed to improved plugfill and larger in-feature W grain size with the advanced PNL+LRW process. More experiments that measured contact resistance for different feature sizes point to favorable Rc scaling with the advanced PNL+LRW process. Finally, 40% improvement in line resistance was observed with this process as tested on 55 nm embedded dynamic random access memory (DRAM) devices, confirming that the advanced PNL+LRW process can be an effective metallization solution for sub-32 nm devices.

Fluorescence-suppressed time-resolved Raman spectroscopy of pharmaceuticals using complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector.

PubMed

Rojalin, Tatu; Kurki, Lauri; Laaksonen, Timo; Viitala, Tapani; Kostamovaara, Juha; Gordon, Keith C; Galvis, Leonardo; Wachsmann-Hogiu, Sebastian; Strachan, Clare J; Yliperttula, Marjo

2016-01-01

In this work, we utilize a short-wavelength, 532-nm picosecond pulsed laser coupled with a time-gated complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector to acquire Raman spectra of several drugs of interest. With this approach, we are able to reveal previously unseen Raman features and suppress the fluorescence background of these drugs. Compared to traditional Raman setups, the present time-resolved technique has two major improvements. First, it is possible to overcome the strong fluorescence background that usually interferes with the much weaker Raman spectra. Second, using the high photon energy excitation light source, we are able to generate a stronger Raman signal compared to traditional instruments. In addition, observations in the time domain can be performed, thus enabling new capabilities in the field of Raman and fluorescence spectroscopy. With this system, we demonstrate for the first time the possibility of recording fluorescence-suppressed Raman spectra of solid, amorphous and crystalline, and non-photoluminescent and photoluminescent drugs such as caffeine, ranitidine hydrochloride, and indomethacin (amorphous and crystalline forms). The raw data acquired by utilizing only the picosecond pulsed laser and a CMOS SPAD detector could be used for identifying the compounds directly without any data processing. Moreover, to validate the accuracy of this time-resolved technique, we present density functional theory (DFT) calculations for a widely used gastric acid inhibitor, ranitidine hydrochloride. The obtained time-resolved Raman peaks were identified based on the calculations and existing literature. Raman spectra using non-time-resolved setups with continuous-wave 785- and 532-nm excitation lasers were used as reference data. Overall, this demonstration of time-resolved Raman and fluorescence measurements with a CMOS SPAD detector shows promise in diverse areas, including fundamental chemical research, the pharmaceutical setting, process analytical technology (PAT), and the life sciences.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Chan-Shan; Chemical Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720; Tang, Tsung-Ta

Indium Tin Oxide (ITO) nanowhiskers (NWhs) obliquely evaporated by electron-beam glancing-angle deposition can serve simultaneously as transparent electrodes and alignment layer for liquid crystal (LC) devices in the terahertz (THz) frequency range. To demonstrate, we constructed a THz LC phase shifter with ITO NWhs. Phase shift exceeding π/2 at 1.0 THz was achieved in a ∼517 μm-thick cell. The phase shifter exhibits high transmittance (∼78%). The driving voltage required for quarter-wave operation is as low as 5.66 V (rms), compatible with complementary metal-oxide-semiconductor (CMOS) and thin-film transistor (TFT) technologies.

Speed-Up Techniques for Complementary Metal Oxide Semiconductor Very Large Scale Integration.

DTIC Science & Technology

1984-12-14

The input voltage at which the two transistors are in the constant current region at the same time marks the active operating region of the inverter...decoder precharge configurations. One circuit displayed a marked enhancement in operation while the other precharged circuit displyed degraded operation due...34 IEEE Journal of Solid State Circuits, SC-18: 457-462 (October 1983). 19. Cobbold , R. Theory and Applications of Field Effect Transistors, New York: John

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

A comparison of imaging methods for use in an array biosensor

NASA Technical Reports Server (NTRS)

Golden, Joel P.; Ligler, Frances S.

2002-01-01

An array biosensor has been developed which uses an actively-cooled, charge-coupled device (CCD) imager. In an effort to save money and space, a complementary metal-oxide semiconductor (CMOS) camera and photodiode were tested as replacements for the cooled CCD imager. Different concentrations of CY5 fluorescent dye in glycerol were imaged using the three different detection systems with the same imaging optics. Signal discrimination above noise was compared for each of the three systems.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

2 Gbit/s 0.5 μm complementary metal-oxide semiconductor optical transceiver with event-driven dynamic power-on capability

NASA Astrophysics Data System (ADS)

Wang, Xingle; Kiamilev, Fouad; Gui, Ping; Wang, Xiaoqing; Ekman, Jeremy; Zuo, Yongrong; Blankenberg, Jason; Haney, Michael

2006-06-01

A 2 Gb/s0.5 μm complementary metal-oxide semiconductor optical transceiver designed for board- or backplane level power-efficient interconnections is presented. The transceiver supports optical wake-on-link (OWL), an event-driven dynamic power-on technique. Depending on external events, the transceiver resides in either the active mode or the sleep mode and switches accordingly. The active-to-sleep transition shuts off the normal, gigabit link and turns on dedicated circuits to establish a low-power (~1.8 mW), low data rate (less than 100 Mbits/s) link. In contrast the normal, gigabit link consumes over 100 mW. Similarly the sleep-to-active transition shuts off the low-power link and turns on the normal, gigabit link. The low-power link, sharing the same optical channel with the normal, gigabit link, is used to achieve transmitter/receiver pair power-on synchronization and greatly reduces the power consumption of the transceiver. A free-space optical platform was built to evaluate the transceiver performance. The experiment successfully demonstrated the event-driven dynamic power-on operation. To our knowledge, this is the first time a dynamic power-on scheme has been implemented for optical interconnects. The areas of the circuits that implement the low-power link are approximately one-tenth of the areas of the gigabit link circuits.

Laser line scan underwater imaging by complementary metal-oxide-semiconductor camera

NASA Astrophysics Data System (ADS)

He, Zhiyi; Luo, Meixing; Song, Xiyu; Wang, Dundong; He, Ning

2017-12-01

This work employs the complementary metal-oxide-semiconductor (CMOS) camera to acquire images in a scanning manner for laser line scan (LLS) underwater imaging to alleviate backscatter impact of seawater. Two operating features of the CMOS camera, namely the region of interest (ROI) and rolling shutter, can be utilized to perform image scan without the difficulty of translating the receiver above the target as the traditional LLS imaging systems have. By the dynamically reconfigurable ROI of an industrial CMOS camera, we evenly divided the image into five subareas along the pixel rows and then scanned them by changing the ROI region automatically under the synchronous illumination by the fun beams of the lasers. Another scanning method was explored by the rolling shutter operation of the CMOS camera. The fun beam lasers were turned on/off to illuminate the narrow zones on the target in a good correspondence to the exposure lines during the rolling procedure of the camera's electronic shutter. The frame synchronization between the image scan and the laser beam sweep may be achieved by either the strobe lighting output pulse or the external triggering pulse of the industrial camera. Comparison between the scanning and nonscanning images shows that contrast of the underwater image can be improved by our LLS imaging techniques, with higher stability and feasibility than the mechanically controlled scanning method.

Work function characterization of solution-processed cobalt silicide

DOE PAGES

Ullah, Syed Shihab; Robinson, Matt; Hoey, Justin; ...

2012-05-08

Cobalt silicide thin films were prepared by spin-coating Si6H12-based inks onto various substrates followed by a thermal treatment. The work function of the solution processed Co-Si was determined by both capacitance-voltage (C-V) measurements of metal-oxide-semiconductor (MOS) structures as well as by ultraviolet photoelectron spectroscopy (UPS). The UPS-derived work function was 4.80 eV for a Co-Si film on Si (100) while C-V of MOS structures yielded a work function of 4.36 eV where the metal was solution-processed Co-Si, the oxide was SiO2 and the semiconductor was a B-doped Si wafer.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

PubMed

Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

2018-04-12

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji-Won

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component comprising at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes duringmore » consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.« less

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Plasmonic colour generation

NASA Astrophysics Data System (ADS)

Kristensen, Anders; Yang, Joel K. W.; Bozhevolnyi, Sergey I.; Link, Stephan; Nordlander, Peter; Halas, Naomi J.; Mortensen, N. Asger

2017-01-01

Plasmonic colours are structural colours that emerge from resonant interactions between light and metallic nanostructures. The engineering of plasmonic colours is a promising, rapidly emerging research field that could have a large technological impact. We highlight basic properties of plasmonic colours and recent nanofabrication developments, comparing technology-performance indicators for traditional and nanophotonic colour technologies. The structures of interest include diffraction gratings, nanoaperture arrays, thin films, and multilayers and structures that support Mie resonances and whispering-gallery modes. We discuss plasmonic colour nanotechnology based on localized surface plasmon resonances, such as gap plasmons and hybridized disk-hole plasmons, which allow for colour printing with sub-diffraction resolution. We also address a range of fabrication approaches that enable large-area printing and nanoscale lithography compatible with complementary metal-oxide semiconductor technologies, including nanoimprint lithography and self-assembly. Finally, we review recent developments in dynamically reconfigurable plasmonic colours and in the laser-induced post-processing of plasmonic colour surfaces.

Split Bull's eye shaped aluminum antenna for plasmon-enhanced nanometer scale germanium photodetector.

PubMed

Ren, Fang-Fang; Ang, Kah-Wee; Ye, Jiandong; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

2011-03-09

Bull's eye antennas are capable of efficiently collecting and concentrating optical signals into an ultrasmall area, offering an excellent solution to break the bottleneck between speed and photoresponse in subwavelength photodetectors. Here, we exploit the idea of split bull's eye antenna for a nanometer germanium photodetector operating at a standard communication wavelength of 1310 nm. The nontraditional plasmonic metal aluminum has been implemented in the resonant antenna structure fabricated by standard complementary metal-oxide-semiconductor (CMOS) processing. A significant enhancement in photoresponse could be achieved over the conventional bull's eye scheme due to an increased optical near-field in the active region. Moreover, with this novel antenna design the effective grating area could be significantly reduced without sacrificing device performance. This work paves the way for the future development of low-cost, high-density, and high-speed CMOS-compatible germanium-based optoelectronic devices.

Site-Controlled Growth of Monolithic InGaAs/InP Quantum Well Nanopillar Lasers on Silicon.

PubMed

Schuster, Fabian; Kapraun, Jonas; Malheiros-Silveira, Gilliard N; Deshpande, Saniya; Chang-Hasnain, Connie J

2017-04-12

In this Letter, we report the site-controlled growth of InP nanolasers on a silicon substrate with patterned SiO 2 nanomasks by low-temperature metal-organic chemical vapor deposition, compatible with silicon complementary metal-oxide-semiconductor (CMOS) post-processing. A two-step growth procedure is presented to achieve smooth wurtzite faceting of vertical nanopillars. By incorporating InGaAs multiquantum wells, the nanopillar emission can be tuned over a wide spectral range. Enhanced quality factors of the intrinsic InP nanopillar cavities promote lasing at 0.87 and 1.21 μm, located within two important optical telecommunication bands. This is the first demonstration of a site-controlled III-V nanolaser monolithically integrated on silicon with a silicon-transparent emission wavelength, paving the way for energy-efficient on-chip optical links at typical telecommunication wavelengths.

Impact of oxygen plasma postoxidation process on Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lechaux, Y.; Fadjie-Djomkam, A. B.; Bollaert, S.; Wichmann, N.

2016-09-01

Capacitance-voltage (C-V) measurements and x-ray photoelectron spectroscopy (XPS) analysis were performed in order to investigate the effect of a oxygen (O2) plasma after oxide deposition on the Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor structure passivated with ammonia NH4OH solution. From C-V measurements, an improvement of charge control is observed using the O2 plasma postoxidation process on In0.53Ga0.47As, while the minimum of interface trap density remains at a good value lower than 1 × 1012 cm-2 eV-1. From XPS measurements, we found that NH4OH passivation removes drastically the Ga and As native oxides on the In0.53Ga0.47As surface and the O2 plasma postoxidation process enables the reduction of interface re-oxidation after post deposition annealing (PDA) of the oxide. The advanced hypothesis is the formation of interfacial barrier between Al2O3 and In0.53Ga0.47As which prevents the diffusion of oxygen species into the semiconductor surface during PDA.

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Metal Contacts in Semiconductors.

DTIC Science & Technology

1983-11-01

greater understanding of the role that imperfec- tions, defects etc. play in the formation of Schottk~y barriers and related devices. In section 1 of...these effects. In Section 2 of this report we consider the role of surface defects in the pinning of the Fermi level at free semiconductor surfaces and...in the adsorption and oxidation processes involved when these surfaces interact with gases and metals. The role of imperfections at metal

Colloidal inorganic nanocrystals: Nucleation, growth and biological applications

NASA Astrophysics Data System (ADS)

Lynch, Jared James

Colloidal inorganic nanocrystals are a class of material whose size ranges from a few nanometers to a hundred nanometers in dimension. These nanocrystals have size dependent properties that differ significantly from the bulk material counterparts. Due to their unique physical properties colloidal inorganic nanocrystals have several promising applications in a diverse range of areas, such as biomedical diagnosis, catalysis, plasmonics, high-density data storage and solar energy conversion. This dissertation presents the study of the formation of iron oxide nanocrystals under the influence of solvent and Ar gas bubbles, the phase transfer of metal oxide nanocrystals into water using inorganic ions, and the doping of semiconductor CdS/ZnS core/shell nanocrystals with copper and silver ions. First, the formation of iron oxide nanocrystals is investigated in the presence of boiling solvent or Ar bubbles. Using a non-injection based synthesis method, the thermal decomposition of iron oleate was studied under various reaction conditions, and the role of the bubbles on the nucleation and growth of iron oxide nanocrystals was determined. Kinetics studies were used to elucidate how latent heat transfer from the bubbles allows for "active monomers" to form preferentially from exothermic reactions taking place during nucleation. General insights into colloidal inorganic nanocrystal formation are discussed. Second, a non-injection based synthesis for CdS/ZnS core/shell nanocrystals is used to make high quality semiconductor particles which are intentionally doped with Cu or Ag ions. The Ag ions effect on the optical properties of the CdS/ZnS nanocrystals is investigated. The absorption and fluorescence of the samples is measured as a function of time and temperature. Proposed mechanisms for the observations are given and thoroughly discussed. Comparisons between previous results for Cu doped CdS/ZnS nanocrystals are also made to further understand how doping of semiconductor nanocrystals can be realized. Finally, a novel phase transfer process is demonstrated using inorganic salts, such as sodium arsenite, to make water soluble metal oxide nanocrystals. The water soluble iron oxide nanocrystals are fully characterized by several complementary techniques and then used in cellular studies. The arsenite-coated iron oxide composite nanocrystals (AICN) are shown to be effective cancer therapy agents.

All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application

NASA Astrophysics Data System (ADS)

Tsai, Chih-Wei; Lo, Yu-Lung; Chang, Chia-Chen; Liu, Han-Ying; Yang, Wei-Bin; Cheng, Kuo-Hsing

2017-04-01

A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40-60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Making a Back-Illuminated Imager with Back-Side Contact and Alignment Markers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2008-01-01

A design modification and a fabrication process that implements the modification have been conceived to solve two problems encountered in the development of back-illuminated, back-sidethinned complementary metal oxide/ semiconductor (CMOS) image-detector integrated circuits. The two problems are (1) how to form metal electrical-contact pads on the back side that are electrically connected through the thickness in proper alignment with electrical contact points on the front side and (2) how to provide alignment keys on the back side to ensure proper registration of backside optical components (e.g., microlenses and/or color filters) with the front-side pixel pattern. The essence of the design modification is to add metal plugs that extend from the desired front-side locations through the thickness and protrude from the back side of the substrate. The plugs afford the required front-to-back electrical conduction, and the protrusions of the plugs serve as both the alignment keys and the bases upon which the back-side electrical-contact pads can be formed.

Metal Oxide Thin Film Transistors on Paper Substrate: Fabrication, Characterization, and Printing Process

NASA Astrophysics Data System (ADS)

Choi, Nack-Bong

Flexible electronics is an emerging next-generation technology that offers many advantages such as light weight, durability, comfort, and flexibility. These unique features enable many new applications such as flexible display, flexible sensors, conformable electronics, and so forth. For decades, a variety of flexible substrates have been demonstrated for the application of flexible electronics. Most of them are plastic films and metal foils so far. For the fundamental device of flexible circuits, thin film transistors (TFTs) using poly silicon, amorphous silicon, metal oxide and organic semiconductor have been successfully demonstrated. Depending on application, low-cost and disposable flexible electronics will be required for convenience. Therefore it is important to study inexpensive substrates and to explore simple processes such as printing technology. In this thesis, paper is introduced as a new possible substrate for flexible electronics due to its low-cost and renewable property, and amorphous indium gallium zinc oxide (a-IGZO) TFTs are realized as the promising device on the paper substrate. The fabrication process and characterization of a-IGZO TFT on the paper substrate are discussed. a-IGZO TFTs using a polymer gate dielectric on the paper substrate demonstrate excellent performances with field effect mobility of ˜20 cm2 V-1 s-1, on/off current ratio of ˜106, and low leakage current, which show the enormous potential for flexible electronics application. In order to complement the n-channel a-IGZO TFTs and then enable complementary metal-oxide semiconductor (CMOS) circuit architectures, cuprous oxide is studied as a candidate material of p-channel oxide TFTs. In this thesis, a printing process is investigated as an alternative method for the fabrication of low-cost and disposable electronics. Among several printing methods, a modified offset roll printing that prints high resolution patterns is presented. A new method to fabricate a high resolution printing plate is investigated and the most favorable condition to transfer ink from a blanket to a cliche is studied. Consequently, a high resolution cliche is demonstrated and the printed patterns of 10mum width and 6mum line spacing are presented. In addition, the top gate a-IGZO TFTs with channel width/length of 12/6mum is successfully demonstrated by printing etch-resists. This work validates the compatibility of a-IGZO TFT on paper substrate for the disposable microelectronics application and presents the potential of low-cost and high resolution printing technology.

Impact of process temperature on GaSb metal-oxide-semiconductor interface properties fabricated by ex-situ process

NASA Astrophysics Data System (ADS)

Yokoyama, Masafumi; Asakura, Yuji; Yokoyama, Haruki; Takenaka, Mitsuru; Takagi, Shinichi

2014-06-01

We have studied the impact of process temperature on interface properties of GaSb metal-oxide-semiconductor (MOS) structures fabricated by an ex-situ atomic-layer-deposition (ALD) process. We have found that the ALD temperature strongly affects the Al2O3/GaSb MOS interface properties. The Al2O3/GaSb MOS interfaces fabricated at the low ALD temperature of 150 °C have the minimum interface-trap density (Dit) of ˜4.5 × 1013 cm-2 eV-1. We have also found that the post-metalization annealing at temperature higher than 200 °C degrades the Al2O3/GaSb MOS interface properties. The low-temperature process is preferable in fabricating GaSb MOS interfaces in the ex-situ ALD process to avoid the high-temperature-induced degradations.

Non-flickering 100 m RGB visible light communication transmission based on a CMOS image sensor.

PubMed

Chow, Chi-Wai; Shiu, Ruei-Jie; Liu, Yen-Chun; Liu, Yang; Yeh, Chien-Hung

2018-03-19

We demonstrate a non-flickering 100 m long-distance RGB visible light communication (VLC) transmission based on a complementary-metal-oxide-semiconductor (CMOS) camera. Experimental bit-error rate (BER) measurements under different camera ISO values and different transmission distances are evaluated. Here, we also experimentally reveal that the rolling shutter effect- (RSE) based VLC system cannot work at long distance transmission, and the under-sampled modulation- (USM) based VLC system is a good choice.

Packet Controller For Wireless Headset

NASA Technical Reports Server (NTRS)

Christensen, Kurt K.; Swanson, Richard J.

1993-01-01

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

PubMed Central

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Simulation of hole-mobility in doped relaxed and strained Ge layers

NASA Astrophysics Data System (ADS)

Watling, Jeremy R.; Riddet, Craig; Chan, Morgan Kah H.; Asenov, Asen

2010-11-01

As silicon based metal-oxide-semiconductor field-effect transistors (MOSFETs) are reaching the limits of their performance with scaling, alternative channel materials are being considered to maintain performance in future complementary metal-oxide semiconductor technology generations. Thus there is renewed interest in employing Ge as a channel material in p-MOSFETs, due to the significant improvement in hole mobility as compared to Si. Here we employ full-band Monte Carlo to study hole transport properties in Ge. We present mobility and velocity-field characteristics for different transport directions in p-doped relaxed and strained Ge layers. The simulations are based on a method for over-coming the potentially large dynamic range of scattering rates, which results from the long-range nature of the unscreened Coulombic interaction. Our model for ionized impurity scattering includes the affects of dynamic Lindhard screening, coupled with phase-shift, and multi-ion corrections along with plasmon scattering. We show that all these effects play a role in determining the hole carrier transport in doped Ge layers and cannot be neglected.

Holmium hafnate: An emerging electronic device material

NASA Astrophysics Data System (ADS)

Pavunny, Shojan P.; Sharma, Yogesh; Kooriyattil, Sudheendran; Dugu, Sita; Katiyar, Rajesh K.; Scott, James F.; Katiyar, Ram S.

2015-03-01

We report structural, optical, charge transport, and temperature properties as well as the frequency dependence of the dielectric constant of Ho2Hf2O7 (HHO) which make this material desirable as an alternative high-k dielectric for future silicon technology devices. A high dielectric constant of ˜20 and very low dielectric loss of ˜0.1% are temperature and voltage independent at 100 kHz near ambient conditions. The Pt/HHO/Pt capacitor exhibits exceptionally low Schottky emission-based leakage currents. In combination with the large observed bandgap Eg of 5.6 eV, determined by diffuse reflectance spectroscopy, our results reveal fundamental physics and materials science of the HHO metal oxide and its potential application as a high-k dielectric for the next generation of complementary metal-oxide-semiconductor devices.

Apparatus for photocatalytic treatment of liquids

NASA Technical Reports Server (NTRS)

Cooper, Gerald (Inventor); Ratcliff, Matthew A. (Inventor)

1992-01-01

Apparatus for decontaminating a contaminated fluid by using photocatalytic particles. The apparatus includes a reactor tank for holding a slurry of the contaminated fluid and the photocatalytic particles ultraviolet light irradiates the surface of the slurry, thereby activating the photocatalytic properties of the particles. Stirring blades for continuously agitate the irradiated fluid surface maintaining the particles in a suspended state within the fluid. A cross flow filter is used for separating the fluid from the semiconductor powder after the decomposition reaction is ended. The cross flow filter is occasionally back flushed to remove any caked semiconductor powder. The semiconductor powder may be recirculated back to the tank for reuse, or may be stored for future use. A series of reactor tanks may be used to gradually decompose a chemical in the fluid. The fluid may be pretreated to remove certain metal ions which interfere with the photocatalytic process. Such pretreatment may be accomplished by dispersing semiconductor particles within the fluid, which particles adsorb ions or photodeposit the metal as the free metal or its insoluble oxide or hydroxide, and then removing the semiconductor particles together with the adsorbed metal ions/oxides/hydroxide/free metal from the fluid.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Rapid Waterborne Pathogen Detection with Mobile Electronics.

PubMed

Wu, Tsung-Feng; Chen, Yu-Chen; Wang, Wei-Chung; Kucknoor, Ashwini S; Lin, Che-Jen; Lo, Yu-Hwa; Yao, Chun-Wei; Lian, Ian

2017-06-09

Pathogen detection in water samples, without complex and time consuming procedures such as fluorescent-labeling or culture-based incubation, is essential to public safety. We propose an immunoagglutination-based protocol together with the microfluidic device to quantify pathogen levels directly from water samples. Utilizing ubiquitous complementary metal-oxide-semiconductor (CMOS) imagers from mobile electronics, a low-cost and one-step reaction detection protocol is developed to enable field detection for waterborne pathogens. 10 mL of pathogen-containing water samples was processed using the developed protocol including filtration enrichment, immune-reaction detection and imaging processing. The limit of detection of 10 E. coli O157:H7 cells/10 mL has been demonstrated within 10 min of turnaround time. The protocol can readily be integrated into a mobile electronics such as smartphones for rapid and reproducible field detection of waterborne pathogens.

Active quench and reset integrated circuit with novel hold-off time control logic for Geiger-mode avalanche photodiodes.

PubMed

Deng, Shijie; Morrison, Alan P

2012-09-15

This Letter presents an active quench-and-reset circuit for Geiger-mode avalanche photodiodes (GM-APDs). The integrated circuit was fabricated using a conventional 0.35 μm complementary metal oxide semiconductor process. Experimental results show that the circuit is capable of linearly setting the hold-off time from several nanoseconds to microseconds with a resolution of 6.5 ns. This allows the selection of the optimal afterpulse-free hold-off time for the GM-APD via external digital inputs or additional signal processing circuitry. Moreover, this circuit resets the APD automatically following the end of the hold-off period, thus simplifying the control for the end user. Results also show that a minimum dead time of 28.4 ns is achieved, demonstrating a saturated photon-counting rate of 35.2 Mcounts/s.

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires.

PubMed

Hsieh, Chin-Hua; Chang, Mu-Tung; Chien, Yu-Jen; Chou, Li-Jen; Chen, Lih-Juann; Chen, Chii-Dong

2008-10-01

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Ultrafast acousto-optic mode conversion in optically birefringent ferroelectrics

NASA Astrophysics Data System (ADS)

Lejman, Mariusz; Vaudel, Gwenaelle; Infante, Ingrid C.; Chaban, Ievgeniia; Pezeril, Thomas; Edely, Mathieu; Nataf, Guillaume F.; Guennou, Mael; Kreisel, Jens; Gusev, Vitalyi E.; Dkhil, Brahim; Ruello, Pascal

2016-08-01

The ability to generate efficient giga-terahertz coherent acoustic phonons with femtosecond laser makes acousto-optics a promising candidate for ultrafast light processing, which faces electronic device limits intrinsic to complementary metal oxide semiconductor technology. Modern acousto-optic devices, including optical mode conversion process between ordinary and extraordinary light waves (and vice versa), remain limited to the megahertz range. Here, using coherent acoustic waves generated at tens of gigahertz frequency by a femtosecond laser pulse, we reveal the mode conversion process and show its efficiency in ferroelectric materials such as BiFeO3 and LiNbO3. Further to the experimental evidence, we provide a complete theoretical support to this all-optical ultrafast mechanism mediated by acousto-optic interaction. By allowing the manipulation of light polarization with gigahertz coherent acoustic phonons, our results provide a novel route for the development of next-generation photonic-based devices and highlight new capabilities in using ferroelectrics in modern photonics.

Copper nanorod array assisted silicon waveguide polarization beam splitter.

PubMed

Kim, Sangsik; Qi, Minghao

2014-04-21

We present the design of a three-dimensional (3D) polarization beam splitter (PBS) with a copper nanorod array placed between two silicon waveguides. The localized surface plasmon resonance (LSPR) of a metal nanorod array selectively cross-couples transverse electric (TE) mode to the coupler waveguide, while transverse magnetic (TM) mode passes through the original input waveguide without coupling. An ultra-compact and broadband PBS compared to all-dielectric devices is achieved with the LSPR. The output ports of waveguides are designed to support either TM or TE mode only to enhance the extinction ratios. Compared to silver, copper is fully compatible with complementary metal-oxide-semiconductor (CMOS) technology.

Optical Properties and Plasmonic Performance of Titanium Nitride

PubMed Central

Patsalas, Panos; Kalfagiannis, Nikolaos; Kassavetis, Spyros

2015-01-01

Titanium nitride (TiN) is one of the most well-established engineering materials nowadays. TiN can overcome most of the drawbacks of palsmonic metals due to its high electron conductivity and mobility, high melting point and due to the compatibility of its growth with Complementary Metal Oxide Semiconductor (CMOS) technology. In this work, we review the dielectric function spectra of TiN and we evaluate the plasmonic performance of TiN by calculating (i) the Surface Plasmon Polariton (SPP) dispersion relations and (ii) the Localized Surface Plasmon Resonance (LSPR) band of TiN nanoparticles, and we demonstrate a significant plasmonic performance of TiN.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

PubMed

Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

2015-07-01

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors. I. Analytical modeling of time-dependent characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Cramer, T.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

Metal-oxide-semiconductor (MOS) transistors fabricated with pentacene thin films were characterized by temperature-dependent current-voltage (I-V) characteristics, time-dependent current measurements, and admittance spectroscopy. The channel mobility shows almost linear variation with temperature, suggesting that only shallow traps are present in the semiconductor and at the oxide/semiconductor interface. The admittance spectra feature a broad peak, which can be modeled as the sum of a continuous distribution of relaxation times. The activation energy of this peak is comparable to the polaron binding energy in pentacene. The absence of trap signals in the admittance spectra confirmed that both the semiconductor and the oxide/semiconductor interface have negligible density of deep traps, likely owing to the passivation of SiO2 before pentacene growth. Nevertheless, current instabilities were observed in time-dependent current measurements following the application of gate-voltage pulses. The corresponding activation energy matches the energy of a hole trap in SiO2. We show that hole trapping in the oxide can explain both the temperature and the time dependences of the current instabilities observed in pentacene MOS transistors. The combination of these experimental techniques allows us to derive a comprehensive model for charge transport in hybrid architectures where trapping processes occur at various time and length scales.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Cylinder and metal grating polarization beam splitter

NASA Astrophysics Data System (ADS)

Yang, Junbo; Xu, Suzhi

2017-08-01

We propose a novel and compact metal grating polarization beam splitter (PBS) based on its different reflected and transmitted orders. The metal grating exhibits a broadband high reflectivity and polarization dependence. The rigorous coupled wave analysis is used to calculate the reflectivity and the transmitting spectra and optimize the structure parameters to realize the broadband PBS. The finite-element method is used to calculate the field distribution. The characteristics of the broadband high reflectivity, transmitting and the polarization dependence are investigated including wavelength, period, refractive index and the radius of circle grating. When grating period d = 400 nm, incident wavelength λ = 441 nm, incident angle θ = 60° and radius of circle d/5, then the zeroth reflection order R0 = 0.35 and the transmission zeroth order T0 = 0.08 for TE polarization, however, T0 = 0.34 and R0 = 0.01 for TM mode. The simple fabrication method involves only single etch step and good compatibility with complementary metal oxide semiconductor technology. PBS designed here is particularly suited for optical communication and optical information processing.

Alternative photocatalysts to TiO2 for the photocatalytic reduction of CO2

NASA Astrophysics Data System (ADS)

Nikokavoura, Aspasia; Trapalis, Christos

2017-01-01

The increased concentration of CO2 in the atmosphere, originating from the burning of fossil fuels in stationary and mobile sources, is referred as the "Anthropogenic Greenhouse Effect" and constitutes a major environmental concern. The scientific community is highly concerned about the resulting enhancement of the mean atmospheric temperature, so a vast diversity of methods has been applied. Thermochemical, electrochemical, photocatalytic, photoelectrochemical processes, as well as combination of solar electricity generation and water splitting processes have been performed in order to lower the CO2 atmospheric levels. Photocatalytic methods are environmental friendly and succeed in reducing the atmospheric CO2 concentration and producing fuels or/and useful organic compounds at the same time. The most common photocatalysts for the CO2 reduction are the inorganic, the carbon based semiconductors and the hybrids based on semiconductors, which combine stability, low cost and appropriate structure in order to accomplish redox reactions. In this review, inorganic semiconductors such as single-metal oxide, mixed-metal oxides, metal oxide composites, layered double hydroxides (LDHs), salt composites, carbon based semiconductors such as graphene based composites, CNT composites, g-C3N4 composites and hybrid organic-inorganic materials (ZIFs) were studied. TiO2 and Ti based photocatalysts are extensively studied and therefore in this review they are not mentioned.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materialsmore » on the basis of porous silicon and nanostructures with a high aspect ratio.« less

Studies of Thermophysical Properties of Metals and Semiconductors by Containerless Processing Under Microgravity

NASA Technical Reports Server (NTRS)

Seidel, A.; Soellner, W.; Stenzel, C.

2012-01-01

Electromagnetic levitation under microgravity provides unique opportunities for the investigation of liquid metals, alloys and semiconductors, both above and below their melting temperatures, with minimized disturbances of the sample under investigation. The opportunity to perform such experiments will soon be available on the ISS with the EML payload which is currently being integrated. With its high-performance diagnostics systems EML allows to measure various physical properties such as heat capacity, enthalpy of fusion, viscosity, surface tension, thermal expansion coefficient, and electrical conductivity. In studies of nucleation and solidification phenomena the nucleation kinetics, phase selection, and solidification velocity can be determined. Advanced measurement capabilities currently being studied include the measurement and control of the residual oxygen content of the process atmosphere and a complementary inductive technique to measure thermophysical properties.

Phase modulation in horizontal metal-insulator-silicon-insulator-metal plasmonic waveguides.

PubMed

Zhu, Shiyang; Lo, G Q; Kwong, D L

2013-04-08

An extremely compact Si phase modulator is proposed and validated, which relies on effective modulation of the real part of modal index of horizontal metal-insulator-Si-insulator-metal plasmonic waveguides by a voltage applied between the metal cover and the Si core. Proof-of-concept devices are fabricated on silicon-on-insulator substrates using standard complementary metal-oxide-semiconductor technology using copper as the metal and thermal silicon dioxide as the insulator. A modulator with a 1-μm-long phase shifter inserted in an asymmetric Si Mach-Zehnder interferometer exhibits 9-dB extinction ratio under a 6-V/10-kHz voltage swing. Numerical simulations suggest that high speed and low driving voltage could be achieved by shortening the distance between the Si core and the n(+)-contact and by using a high-κ dielectric as the insulator, respectively.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

A bi-stable nanoelectromechanical non-volatile memory based on van der Waals force

NASA Astrophysics Data System (ADS)

Soon, Bo Woon; Jiaqiang Ng, Eldwin; Qian, You; Singh, Navab; Julius Tsai, Minglin; Lee, Chengkuo

2013-07-01

By using complementary-metal-oxide-semiconductor processes, a silicon based bi-stable nanoelectromechanical non-volatile memory is fabricated and characterized. The main feature of this device is an 80 nm wide and 3 μm high silicon nanofin (SiNF) of a high aspect ratio (1:35). The switching mechanism is realized by electrostatic actuation between two lateral electrodes, i.e., terminals. Bi-stable hysteresis behavior is demonstrated when the SiNF maintains its contact to one of the two terminals by leveraging on van der Waals force even after voltage bias is turned off. The compelling results indicate that this design is promising for realization of high density non-volatile memory application due to its nano-scale footprint and zero on-hold power consumption.

Sub-micro-liter Electrochemical Single-Nucleotide-Polymorphism Detector for Lab-on-a-Chip System

NASA Astrophysics Data System (ADS)

Tanaka, Hiroyuki; Fiorini, Paolo; Peeters, Sara; Majeed, Bivragh; Sterken, Tom; de Beeck, Maaike Op; Hayashi, Miho; Yaku, Hidenobu; Yamashita, Ichiro

2012-04-01

A sub-micro-liter single-nucleotide-polymorphism (SNP) detector for lab-on-a-chip applications is developed. This detector enables a fast, sensitive, and selective SNP detection directly from human blood. The detector is fabricated on a Si substrate by a standard complementary metal oxide semiconductor/micro electro mechanical systems (CMOS/MEMS) process and Polydimethylsiloxane (PDMS) molding. Stable and reproducible measurements are obtained by implementing an on-chip Ag/AgCl electrode and encapsulating the detector. The detector senses the presence of SNPs by measuring the concentration of pyrophosphoric acid generated during selective DNA amplification. A 0.5-µL-volume detector enabled the successful performance of the typing of a SNP within the ABO gene using human blood. The measured sensitivity is 566 pA/µM.

A 72 × 60 Angle-Sensitive SPAD Imaging Array for Lens-less FLIM.

PubMed

Lee, Changhyuk; Johnson, Ben; Jung, TaeSung; Molnar, Alyosha

2016-09-02

We present a 72 × 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging. An A-SPAD pixel consists of (1) a SPAD to provide precise photon arrival time where a time-resolved operation is utilized to avoid stimulus-induced saturation, and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of the incoming light. The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale. Futhermore, the chip presented herein integrates pixel-level counters to reduce output data-rate and to enable a precise timing control. The array is implemented in standard 180 nm complementary metal-oxide-semiconductor (CMOS) technology and characterized without any post-processing.

Origin of noise in liquid-gated Si nanowire troponin biosensors.

PubMed

Kutovyi, Y; Zadorozhnyi, I; Hlukhova, H; Handziuk, V; Petrychuk, M; Ivanchuk, Andriy; Vitusevich, S

2018-04-27

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.

PubMed

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-12-31

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal-oxide-semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms.

Waveguide silicon nitride grating coupler

NASA Astrophysics Data System (ADS)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Design, fabrication, and measurement of two silicon-based ultraviolet and blue-extended photodiodes

NASA Astrophysics Data System (ADS)

Chen, Changping; Wang, Han; Jiang, Zhenyu; Jin, Xiangliang; Luo, Jun

2014-12-01

Two silicon-based ultraviolet (UV) and blue-extended photodiodes are presented, which were fabricated for light detection in the ultraviolet/blue spectral range. Stripe-shaped and octagon-ring-shaped structures were designed to verify parameters of the UV-responsivity, UV-selectivity, breakdown voltage, and response time. The ultra-shallow lateral pn junction had been successfully realized in a standard 0.5-μm complementary metal oxide semiconductor (CMOS) process to enlarge the pn junction area, enhance the absorption of UV light, and improve the responsivity and quantum efficiency. The test results illustrated that the stripe-shaped structure has the lower breakdown voltage, higher UV-responsicity, and higher UV-selectivity. But the octagon-ring-shaped structure has the lower dark current. The response time of both structures was almost the same.

Origin of noise in liquid-gated Si nanowire troponin biosensors

NASA Astrophysics Data System (ADS)

Kutovyi, Y.; Zadorozhnyi, I.; Hlukhova, H.; Handziuk, V.; Petrychuk, M.; Ivanchuk, Andriy; Vitusevich, S.

2018-04-01

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

A 72 × 60 Angle-Sensitive SPAD Imaging Array for Lens-less FLIM

PubMed Central

Lee, Changhyuk; Johnson, Ben; Jung, TaeSung; Molnar, Alyosha

2016-01-01

We present a 72 × 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging. An A-SPAD pixel consists of (1) a SPAD to provide precise photon arrival time where a time-resolved operation is utilized to avoid stimulus-induced saturation, and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of the incoming light. The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale. Futhermore, the chip presented herein integrates pixel-level counters to reduce output data-rate and to enable a precise timing control. The array is implemented in standard 180 nm complementary metal-oxide-semiconductor (CMOS) technology and characterized without any post-processing. PMID:27598170

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Superior Sensitivity of Copper-Based Plasmonic Biosensors.

PubMed

Stebunov, Yury V; Yakubovsky, Dmitry I; Fedyanin, Dmitry Yu; Arsenin, Aleksey V; Volkov, Valentyn S

2018-04-17

Plasmonic biosensing has been demonstrated to be a powerful technique for quantitative determination of molecular analytes and kinetic analysis of biochemical reactions. However, interfaces of most plasmonic biosensors are made of noble metals, such as gold and silver, which are not compatible with industrial production technologies. This greatly limits biosensing applications beyond biochemical and pharmaceutical research. Here, we propose and investigate copper-based biosensor chips fully fabricated with a standard complementary metal-oxide-semiconductor (CMOS) process. The protection of thin copper films from oxidation is achieved with SiO 2 and Al 2 O 3 dielectric films deposited onto the metal surface. In addition, the deposition of dielectric films with thicknesses of only several tens of nanometers significantly improves the biosensing sensitivity, owing to better localization of electromagnetic field above the biosensing surface. According to surface plasmon resonance (SPR) measurements, the copper biosensor chips coated with thin films of SiO 2 (25 nm) and Al 2 O 3 (15 nm) show 55% and 75% higher sensitivity to refractive index changes, respectively, in comparison to pure gold sensor chips. To test biomolecule immobilization, the copper-dielectric biosensor chips are coated with graphene oxide linking layers and used for the selective analysis of oligonucleotide hybridization. The proposed plasmonic biosensors make SPR technology more affordable for various applications and provide the basis for compact biosensors integrated with modern electronic devices.

Impact of process temperature on GaSb metal-oxide-semiconductor interface properties fabricated by ex-situ process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi

We have studied the impact of process temperature on interface properties of GaSb metal-oxide-semiconductor (MOS) structures fabricated by an ex-situ atomic-layer-deposition (ALD) process. We have found that the ALD temperature strongly affects the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The Al{sub 2}O{sub 3}/GaSb MOS interfaces fabricated at the low ALD temperature of 150 °C have the minimum interface-trap density (D{sub it}) of ∼4.5 × 10{sup 13 }cm{sup −2} eV{sup −1}. We have also found that the post-metalization annealing at temperature higher than 200 °C degrades the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The low-temperature process is preferable in fabricating GaSb MOS interfaces in the ex-situmore » ALD process to avoid the high-temperature-induced degradations.« less

Large Lateral Photovoltaic Effect in Metal-(Oxide-) Semiconductor Structures

PubMed Central

Yu, Chongqi; Wang, Hui

2010-01-01

The lateral photovoltaic effect (LPE) can be used in position-sensitive detectors to detect very small displacements due to its output of lateral photovoltage changing linearly with light spot position. In this review, we will summarize some of our recent works regarding LPE in metal-semiconductor and metal-oxide-semiconductor structures, and give a theoretical model of LPE in these two structures. PMID:22163463

Complementary metal-oxide semiconductor compatible source of single photons at near-visible wavelengths

NASA Astrophysics Data System (ADS)

Cernansky, Robert; Martini, Francesco; Politi, Alberto

2018-02-01

We demonstrate on chip generation of correlated pairs of photons in the near-visible spectrum using a CMOS compatible PECVD Silicon Nitride photonic device. Photons are generated via spontaneous four wave mixing enhanced by a ring resonator with high quality Q-factor of 320,000 resulting in a generation rate of 950,000 $\\frac{pairs}{mW}$. The high brightness of this source offers the opportunity to expand photonic quantum technologies over a broad wavelength range and provides a path to develop fully integrated quantum chips working at room temperature.

Read-noise characterization of focal plane array detectors via mean-variance analysis.

PubMed

Sperline, R P; Knight, A K; Gresham, C A; Koppenaal, D W; Hieftje, G M; Denton, M B

2005-11-01

Mean-variance analysis is described as a method for characterization of the read-noise and gain of focal plane array (FPA) detectors, including charge-coupled devices (CCDs), charge-injection devices (CIDs), and complementary metal-oxide-semiconductor (CMOS) multiplexers (infrared arrays). Practical FPA detector characterization is outlined. The nondestructive readout capability available in some CIDs and FPA devices is discussed as a means for signal-to-noise ratio improvement. Derivations of the equations are fully presented to unify understanding of this method by the spectroscopic community.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

Testability of VLSI (Very Large Scale Integration) Leakage Faults in CMOS (Complementary Metal Oxide Semiconductor).

DTIC Science & Technology

1983-09-01

has been reviewed and is approved for publication. Im Ŕ APPROVED: . L,.. &- MARK W. LEVI Project Engineer APPROVED: W.S. TUTHILL, Colonel, USAF Chief...ebetract entered In Block 20, if different from Report) Same IS. SUPPLEMENTARY NOTES RADC Project Engineer: Mark W. Levi (RBRP) This effort was funded...masking the presence of another fault which was a functional or reliability hazard. ’." • ’ ",, ,~ MARK W. LEVI A ec . ston For 1\\ T’ ir I .] / r "- T A

K-band single-chip electron spin resonance detector.

PubMed

Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

2012-04-01

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

Single Event Upset Rate Estimates for a 16-K CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory).

DTIC Science & Technology

1986-09-30

4 . ~**..ft.. ft . - - - ft SI TABLES 9 I. SA32~40 Single Event Upset Test, 1140-MeV Krypton, 9/l8/8~4. . .. .. .. .. .. .16 II. CRUP Simulation...cosmic ray interaction analysis described in the remainder of this report were calculated using the CRUP computer code 3 modified for funneling. The... CRUP code requires, as inputs, the size of a depletion region specified as a retangular parallel piped with dimensions a 9 b S c, the effective funnel

Bistability in a complementary metal oxide semiconductor inverter circuit.

PubMed

Carroll, Thomas L

2005-09-01

Radiofrequency signals can disrupt the operation of low frequency circuits. A digital inverter circuit would seem to be immune to such disruption, because its output state usually jumps abruptly between 0 and 5 V. Nevertheless, when driven with a high frequency signal, the inverter can have two coexisting stable states (which are not at 0 and 5 V). Slow switching between these states (by changing the rf signal) will produce a low frequency signal. I demonstrate the bistability in a circuit experiment and in a simple model of the circuit.

Millimeter wave complementary metal-oxide-semiconductor on-chip hexagonal nano-ferrite circulator

NASA Astrophysics Data System (ADS)

Chao, Liu; Oukacha, Hassan; Fu, Enjin; Koomson, Valencia Joyner; Afsar, Mohammed N.

2015-05-01

Hexagonal ferrites such as M-type BaFe12O19 and SrFe12O19 have strong uniaxial anisotropic magnetic field and remanent magnetism. The nano-sized ferrite powder exhibits high compatibility and processability in composite material. New magnetic devices using the M-type ferrite materials can work in the tens of GHz frequency range from microwave to millimeter wave without the application of strong external magnetic field. The micro- and nano-sized hexagonal ferrite can be conveniently utilized to fabricate magnetic components integrated in CMOS integrated circuits as thin as several micrometers. The micro-fabrication method of such nano ferrite device is presented in this paper. A circulator working at 60 GHz is designed and integrated into the commercial CMOS process. The circulator exhibits distinct circulation properties in the frequency range from 56 GHz to 58 GHz.

All-optical differential equation solver with constant-coefficient tunable based on a single microring resonator.

PubMed

Yang, Ting; Dong, Jianji; Lu, Liangjun; Zhou, Linjie; Zheng, Aoling; Zhang, Xinliang; Chen, Jianping

2014-07-04

Photonic integrated circuits for photonic computing open up the possibility for the realization of ultrahigh-speed and ultra wide-band signal processing with compact size and low power consumption. Differential equations model and govern fundamental physical phenomena and engineering systems in virtually any field of science and engineering, such as temperature diffusion processes, physical problems of motion subject to acceleration inputs and frictional forces, and the response of different resistor-capacitor circuits, etc. In this study, we experimentally demonstrate a feasible integrated scheme to solve first-order linear ordinary differential equation with constant-coefficient tunable based on a single silicon microring resonator. Besides, we analyze the impact of the chirp and pulse-width of input signals on the computing deviation. This device can be compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may motivate the development of integrated photonic circuits for optical computing.

All-optical differential equation solver with constant-coefficient tunable based on a single microring resonator

PubMed Central

Yang, Ting; Dong, Jianji; Lu, Liangjun; Zhou, Linjie; Zheng, Aoling; Zhang, Xinliang; Chen, Jianping

2014-01-01

Photonic integrated circuits for photonic computing open up the possibility for the realization of ultrahigh-speed and ultra wide-band signal processing with compact size and low power consumption. Differential equations model and govern fundamental physical phenomena and engineering systems in virtually any field of science and engineering, such as temperature diffusion processes, physical problems of motion subject to acceleration inputs and frictional forces, and the response of different resistor-capacitor circuits, etc. In this study, we experimentally demonstrate a feasible integrated scheme to solve first-order linear ordinary differential equation with constant-coefficient tunable based on a single silicon microring resonator. Besides, we analyze the impact of the chirp and pulse-width of input signals on the computing deviation. This device can be compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may motivate the development of integrated photonic circuits for optical computing. PMID:24993440

Argon–germane in situ plasma clean for reduced temperature Ge on Si epitaxy by high density plasma chemical vapor deposition

DOE PAGES

Douglas, Erica A.; Sheng, Josephine J.; Verley, Jason C.; ...

2015-06-04

We found that the demand for integration of near infrared optoelectronic functionality with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature germanium on silicon deposition processes. Our work describes the development of a high density plasma chemical vapor deposition process that uses a low temperature (<460 °C) in situ germane/argon plasma surface preparation step for epitaxial growth of germanium on silicon. It is shown that the germane/argon plasma treatment sufficiently removes SiO x and carbon at the surface to enable germanium epitaxy. Finally, the use of this surface preparation step demonstratesmore » an alternative way to produce germanium epitaxy at reduced temperatures, a key enabler for increased flexibility of integration with CMOS back-end-of-line fabrication.« less

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Photo-Patternable ZnO Thin Films Based on Cross-Linked Zinc Acrylate for Organic/Inorganic Hybrid Complementary Inverters.

PubMed

Jeong, Yong Jin; An, Tae Kyu; Yun, Dong-Jin; Kim, Lae Ho; Park, Seonuk; Kim, Yebyeol; Nam, Sooji; Lee, Keun Hyung; Kim, Se Hyun; Jang, Jaeyoung; Park, Chan Eon

2016-03-02

Complementary inverters consisting of p-type organic and n-type metal oxide semiconductors have received considerable attention as key elements for realizing low-cost and large-area future electronics. Solution-processed ZnO thin-film transistors (TFTs) have great potential for use in hybrid complementary inverters as n-type load transistors because of the low cost of their fabrication process and natural abundance of active materials. The integration of a single ZnO TFT into an inverter requires the development of a simple patterning method as an alternative to conventional time-consuming and complicated photolithography techniques. In this study, we used a photocurable polymer precursor, zinc acrylate (or zinc diacrylate, ZDA), to conveniently fabricate photopatternable ZnO thin films for use as the active layers of n-type ZnO TFTs. UV-irradiated ZDA thin films became insoluble in developing solvent as the acrylate moiety photo-cross-linked; therefore, we were able to successfully photopattern solution-processed ZDA thin films using UV light. We studied the effects of addition of a tiny amount of indium dopant on the transistor characteristics of the photopatterned ZnO thin films and demonstrated low-voltage operation of the ZnO TFTs within ±3 V by utilizing Al2O3/TiO2 laminate thin films or ion-gels as gate dielectrics. By combining the ZnO TFTs with p-type pentacene TFTs, we successfully fabricated organic/inorganic hybrid complementary inverters using solution-processed and photopatterned ZnO TFTs.

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}),more » which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.« less

Copper nanorod array assisted silicon waveguide polarization beam splitter

PubMed Central

Kim, Sangsik; Qi, Minghao

2014-01-01

We present the design of a three-dimensional (3D) polarization beam splitter (PBS) with a copper nanorod array placed between two silicon waveguides. The localized surface plasmon resonance (LSPR) of a metal nanorod array selectively cross-couples transverse electric (TE) mode to the coupler waveguide, while transverse magnetic (TM) mode passes through the original input waveguide without coupling. An ultra-compact and broadband PBS compared to all-dielectric devices is achieved with the LSPR. The output ports of waveguides are designed to support either TM or TE mode only to enhance the extinction ratios. Compared to silver, copper is fully compatible with complementary metal-oxide-semiconductor (CMOS) technology. PMID:24787839

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Role of order and disorder on the electronic performances of oxide semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Martins, R.; Barquinha, P.; Ferreira, I.; Pereira, L.; Gonçalves, G.; Fortunato, E.

2007-02-01

The role of order and disorder on the electronic performances of n-type ionic oxides such as zinc oxide, gallium zinc oxide, and indium zinc oxide used as active (channel) or passive (drain/source) layers in thin film transistors (TFTs) processed at room temperature are discussed, taking as reference the known behavior observed in conventional covalent semiconductors such as silicon. The work performed shows that while in the oxide semiconductors the Fermi level can be pinned up within the conduction band, independent of the state of order, the same does not happen with silicon. Besides, in the oxide semiconductors the carrier mobility is not bandtail limited and so disorder does not affect so strongly the mobility as it happens in covalent semiconductors. The electrical properties of the oxide films (resistivity, carrier concentration, and mobility) are highly dependent on the oxygen vacancies (source of free carriers), which can be controlled by changing the oxygen partial pressure during the deposition process and/or by adding other metal ions to the matrix. In this case, we make the oxide matrix less sensitive to the presence of oxygen, widening the range of oxygen partial pressures that can be used and thus improving the process control of the film resistivity. The results obtained in fully transparent TFT using polycrystalline ZnO or amorphous indium zinc oxide (IZO) as channel layers and highly conductive poly/nanocrystalline ZGO films or amorphous IZO as drain/source layers show that both devices work in the enhancement mode, but the TFT with the highest electronic saturation mobility and on/off ratio 49.9cm2/Vs and 4.3×108, respectively, are the ones in which the active and passive layers are amorphous. The ZnO TFT whose channel is based on polycrystalline ZnO, the mobility and on/off ratio are, respectively, 26cm2/Vs and 3×106. This behavior is attributed to the fact that the electronic transport is governed by the s-like metal cation conduction bands, not significantly affected by any type of angular disorder promoted by the 2p O states related to the valence band, or small amounts of incorporated metal impurities that lead to a better control of vacancies and of the TFT off current.

Dual passivation of intrinsic defects at the compound semiconductor/oxide interface using an oxidant and a reductant.

PubMed

Kent, Tyler; Chagarov, Evgeniy; Edmonds, Mary; Droopad, Ravi; Kummel, Andrew C

2015-05-26

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Research progress of Ge on insulator grown by rapid melting growth

NASA Astrophysics Data System (ADS)

Liu, Zhi; Wen, Juanjuan; Li, Chuanbo; Xue, Chunlai; Cheng, Buwen

2018-06-01

Ge is an attractive material for Si-based microelectronics and photonics due to its high carries mobility, pseudo direct bandgap structure, and the compatibility with complementary metal oxide semiconductor (CMOS) processes. Based on Ge, Ge on insulator (GOI) not only has these advantages, but also provides strong electronic and optical confinement. Recently, a novel technique to fabricate GOI by rapid melting growth (RMG) has been described. Here, we introduce the RMG technique and review recent efforts and progress in RMG. Firstly, we will introduce process steps of RMG. We will then review the researches which focus on characterizations of the GOI including growth dimension, growth mechanism, growth orientation, concentration distribution, and strain status. Finally, GOI based applications including high performance metal–oxide–semiconductor field effect transistors (MOSFETs) and photodetectors will be discussed. These results show that RMG is a promising technique for growth of high quality GOIs with different characterizations. The GOI grown by RMG is a potential material for the next-generation of integrated circuits and optoelectronic circuits. Project supported in part by the National Key Research and Development Program of China (No. 2017YFA0206404) and the National Natural Science Foundation of China (Nos. 61435013, 61534005, 61534004, 61604146).

Design of a Humidity Sensor Tag for Passive Wireless Applications.

PubMed

Wu, Xiang; Deng, Fangming; Hao, Yong; Fu, Zhihui; Zhang, Lihua

2015-10-07

This paper presents a wireless humidity sensor tag for low-cost and low-power applications. The proposed humidity sensor tag, based on radio frequency identification (RFID) technology, was fabricated in a standard 0.18 μm complementary metal oxide semiconductor (CMOS) process. The top metal layer was deposited to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture, resulting in a flat power conversion efficiency curve. The capacitive sensor interface, based on phase-locked loop (PLL) theory, employs a simple architecture and can work with 0.5 V supply voltage. The measurement results show that humidity sensor tag achieves excellent linearity, hysteresis and stability performance. The total power-dissipation of the sensor tag is 2.5 μW, resulting in a maximum operating distance of 23 m under 4 W of radiation power of the RFID reader.

Design of a Humidity Sensor Tag for Passive Wireless Applications

PubMed Central

Wu, Xiang; Deng, Fangming; Hao, Yong; Fu, Zhihui; Zhang, Lihua

2015-01-01

This paper presents a wireless humidity sensor tag for low-cost and low-power applications. The proposed humidity sensor tag, based on radio frequency identification (RFID) technology, was fabricated in a standard 0.18 μm complementary metal oxide semiconductor (CMOS) process. The top metal layer was deposited to form the interdigitated electrodes, which were then filled with polyimide as the humidity sensing layer. A two-stage rectifier adopts a dynamic bias-voltage generator to boost the effective gate-source voltage of the switches in differential-drive architecture, resulting in a flat power conversion efficiency curve. The capacitive sensor interface, based on phase-locked loop (PLL) theory, employs a simple architecture and can work with 0.5 V supply voltage. The measurement results show that humidity sensor tag achieves excellent linearity, hysteresis and stability performance. The total power-dissipation of the sensor tag is 2.5 μW, resulting in a maximum operating distance of 23 m under 4 W of radiation power of the RFID reader. PMID:26457707

Spatial optical crosstalk in CMOS image sensors integrated with plasmonic color filters.

PubMed

Yu, Yan; Chen, Qin; Wen, Long; Hu, Xin; Zhang, Hui-Fang

2015-08-24

Imaging resolution of complementary metal oxide semiconductor (CMOS) image sensor (CIS) keeps increasing to approximately 7k × 4k. As a result, the pixel size shrinks down to sub-2μm, which greatly increases the spatial optical crosstalk. Recently, plasmonic color filter was proposed as an alternative to conventional colorant pigmented ones. However, there is little work on its size effect and the spatial optical crosstalk in a model of CIS. By numerical simulation, we investigate the size effect of nanocross array plasmonic color filters and analyze the spatial optical crosstalk of each pixel in a Bayer array of a CIS with a pixel size of 1μm. It is found that the small pixel size deteriorates the filtering performance of nanocross color filters and induces substantial spatial color crosstalk. By integrating the plasmonic filters in the low Metal layer in standard CMOS process, the crosstalk reduces significantly, which is compatible to pigmented filters in a state-of-the-art backside illumination CIS.

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

NASA Astrophysics Data System (ADS)

Li, Hangbiao; Zhang, Bo; Luo, Ping; Zhen, Shaowei; Liao, Pengfei; He, Yajuan; Li, Zhaoji

2015-09-01

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.

Manufacture of radio frequency micromachined switches with annealing.

PubMed

Lin, Cheng-Yang; Dai, Ching-Liang

2014-01-17

The fabrication and characterization of a radio frequency (RF) micromachined switch with annealing were presented. The structure of the RF switch consists of a membrane, coplanar waveguide (CPW) lines, and eight springs. The RF switch is manufactured using the complementary metal oxide semiconductor (CMOS) process. The switch requires a post-process to release the membrane and springs. The post-process uses a wet etching to remove the sacrificial silicon dioxide layer, and to obtain the suspended structures of the switch. In order to improve the residual stress of the switch, an annealing process is applied to the switch, and the membrane obtains an excellent flatness. The finite element method (FEM) software CoventorWare is utilized to simulate the stress and displacement of the RF switch. Experimental results show that the RF switch has an insertion loss of 0.9 dB at 35 GHz and an isolation of 21 dB at 39 GHz. The actuation voltage of the switch is 14 V.

Manufacture of Radio Frequency Micromachined Switches with Annealing

PubMed Central

Lin, Cheng-Yang; Dai, Ching-Liang

2014-01-01

The fabrication and characterization of a radio frequency (RF) micromachined switch with annealing were presented. The structure of the RF switch consists of a membrane, coplanar waveguide (CPW) lines, and eight springs. The RF switch is manufactured using the complementary metal oxide semiconductor (CMOS) process. The switch requires a post-process to release the membrane and springs. The post-process uses a wet etching to remove the sacrificial silicon dioxide layer, and to obtain the suspended structures of the switch. In order to improve the residual stress of the switch, an annealing process is applied to the switch, and the membrane obtains an excellent flatness. The finite element method (FEM) software CoventorWare is utilized to simulate the stress and displacement of the RF switch. Experimental results show that the RF switch has an insertion loss of 0.9 dB at 35 GHz and an isolation of 21 dB at 39 GHz. The actuation voltage of the switch is 14 V. PMID:24445415

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Quantum ballistic transport in strained epitaxial germanium

NASA Astrophysics Data System (ADS)

Gul, Y.; Holmes, S. N.; Newton, P. J.; Ellis, D. J. P.; Morrison, C.; Pepper, M.; Barnes, C. H. W.; Myronov, M.

2017-12-01

Large scale fabrication using Complementary Metal Oxide Semiconductor compatible technology of semiconductor nanostructures that operate on the principles of quantum transport is an exciting possibility now due to the recent development of ultra-high mobility hole gases in epitaxial germanium grown on standard silicon substrates. We present here a ballistic transport study of patterned surface gates on strained Ge quantum wells with SiGe barriers, which confirms the quantum characteristics of the Ge heavy hole valence band structure in 1-dimension. Quantised conductance at multiples of 2e2/h is a universal feature of hole transport in Ge up to 10 × (2e2/h). The behaviour of ballistic plateaus with finite source-drain bias and applied magnetic field is elucidated. In addition, a reordering of the ground state is observed.

Multilevel metallization method for fabricating a metal oxide semiconductor device

NASA Technical Reports Server (NTRS)

Hollis, B. R., Jr.; Feltner, W. R.; Bouldin, D. L.; Routh, D. E. (Inventor)

1978-01-01

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Printing Peptide arrays with a complementary metal oxide semiconductor chip.

PubMed

Loeffler, Felix F; Cheng, Yun-Chien; Muenster, Bastian; Striffler, Jakob; Liu, Fanny C; Ralf Bischoff, F; Doersam, Edgar; Breitling, Frank; Nesterov-Mueller, Alexander

2013-01-01

: In this chapter, we discuss the state-of-the-art peptide array technologies, comparing the spot technique, lithographical methods, and microelectronic chip-based approaches. Based on this analysis, we describe a novel peptide array synthesis method with a microelectronic chip printer. By means of a complementary metal oxide semiconductor chip, charged bioparticles can be patterned on its surface. The bioparticles serve as vehicles to transfer molecule monomers to specific synthesis spots. Our chip offers 16,384 pixel electrodes on its surface with a spot-to-spot pitch of 100 μm. By switching the voltage of each pixel between 0 and 100 V separately, it is possible to generate arbitrary particle patterns for combinatorial molecule synthesis. Afterwards, the patterned chip surface serves as a printing head to transfer the particle pattern from its surface to a synthesis substrate. We conducted a series of proof-of-principle experiments to synthesize high-density peptide arrays. Our solid phase synthesis approach is based on the 9-fluorenylmethoxycarbonyl protection group strategy. After melting the particles, embedded monomers diffuse to the surface and participate in the coupling reaction to the surface. The method demonstrated herein can be easily extended to the synthesis of more complicated artificial molecules by using bioparticles with artificial molecular building blocks. The possibility of synthesizing artificial peptides was also shown in an experiment in which we patterned biotin particles in a high-density array format. These results open the road to the development of peptide-based functional modules for diverse applications in biotechnology.

Repeat analysis of intraoral digital imaging performed by undergraduate students using a complementary metal oxide semiconductor sensor: An institutional case study.

PubMed

Yusof, Mohd Yusmiaidil Putera Mohd; Rahman, Nur Liyana Abdul; Asri, Amiza Aqiela Ahmad; Othman, Noor Ilyani; Wan Mokhtar, Ilham

2017-12-01

This study was performed to quantify the repeat rate of imaging acquisitions based on different clinical examinations, and to assess the prevalence of error types in intraoral bitewing and periapical imaging using a digital complementary metal-oxide-semiconductor (CMOS) intraoral sensor. A total of 8,030 intraoral images were retrospectively collected from 3 groups of undergraduate clinical dental students. The type of examination, stage of the procedure, and reasons for repetition were analysed and recorded. The repeat rate was calculated as the total number of repeated images divided by the total number of examinations. The weighted Cohen's kappa for inter- and intra-observer agreement was used after calibration and prior to image analysis. The overall repeat rate on intraoral periapical images was 34.4%. A total of 1,978 repeated periapical images were from endodontic assessment, which included working length estimation (WLE), trial gutta-percha (tGP), obturation, and removal of gutta-percha (rGP). In the endodontic imaging, the highest repeat rate was from WLE (51.9%) followed by tGP (48.5%), obturation (42.2%), and rGP (35.6%). In bitewing images, the repeat rate was 15.1% and poor angulation was identified as the most common cause of error. A substantial level of intra- and interobserver agreement was achieved. The repeat rates in this study were relatively high, especially for certain clinical procedures, warranting training in optimization techniques and radiation protection. Repeat analysis should be performed from time to time to enhance quality assurance and hence deliver high-quality health services to patients.

Multi-Aperture-Based Probabilistic Noise Reduction of Random Telegraph Signal Noise and Photon Shot Noise in Semi-Photon-Counting Complementary-Metal-Oxide-Semiconductor Image Sensor

PubMed Central

Ishida, Haruki; Kagawa, Keiichiro; Komuro, Takashi; Zhang, Bo; Seo, Min-Woong; Takasawa, Taishi; Yasutomi, Keita; Kawahito, Shoji

2018-01-01

A probabilistic method to remove the random telegraph signal (RTS) noise and to increase the signal level is proposed, and was verified by simulation based on measured real sensor noise. Although semi-photon-counting-level (SPCL) ultra-low noise complementary-metal-oxide-semiconductor (CMOS) image sensors (CISs) with high conversion gain pixels have emerged, they still suffer from huge RTS noise, which is inherent to the CISs. The proposed method utilizes a multi-aperture (MA) camera that is composed of multiple sets of an SPCL CIS and a moderately fast and compact imaging lens to emulate a very fast single lens. Due to the redundancy of the MA camera, the RTS noise is removed by the maximum likelihood estimation where noise characteristics are modeled by the probability density distribution. In the proposed method, the photon shot noise is also relatively reduced because of the averaging effect, where the pixel values of all the multiple apertures are considered. An extremely low-light condition that the maximum number of electrons per aperture was the only 2e− was simulated. PSNRs of a test image for simple averaging, selective averaging (our previous method), and the proposed method were 11.92 dB, 11.61 dB, and 13.14 dB, respectively. The selective averaging, which can remove RTS noise, was worse than the simple averaging because it ignores the pixels with RTS noise and photon shot noise was less improved. The simulation results showed that the proposed method provided the best noise reduction performance. PMID:29587424

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

NASA Technical Reports Server (NTRS)

Fresh, D. L.; Adolphsen, J. W.

1974-01-01

A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

Fabrication of smooth patterned structures of refractory metals, semiconductors, and oxides via template stripping.

PubMed

Park, Jong Hyuk; Nagpal, Prashant; McPeak, Kevin M; Lindquist, Nathan C; Oh, Sang-Hyun; Norris, David J

2013-10-09

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics.

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

PubMed

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

2016-11-01

Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. Inmore » order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.« less

Method of decontaminating a contaminated fluid by using photocatalytic particles

NASA Technical Reports Server (NTRS)

Cooper, Gerald (Inventor); Ratcliff, Matthew A. (Inventor)

1994-01-01

A system for decontaminating the contaminated fluid by using photocatalytic particles. The system includes a reactor tank for holding the contaminated fluid and the photocatalytic particles suspended in the contaminated fluid to form a slurry. Light irradiates the surface of the slurry, thereby activating the photocatalytic properties of the particles. The system also includes stirring blades for continuously agitating the irradiated fluid surface and for maintaining the particles in a suspended state within the fluid. The system also includes a cross flow filter for segregating the fluid (after decomposition) from the semiconductor powder. The cross flow filter is occasionally back flushed to remove any semiconductor powder that might have caked on the filter. The semiconductor powder may be recirculated back to the tank for reuse, or may be stored for future use. A series of such systems may be used to gradually decompose a chemical in the fluid. Preferably, the fluid is pretreated to remove certain metal ions which interfere with the photocatalytic process. Such pretreatment may be accomplished by dispersing semiconductor particles within the fluid, which adsorb ions or photodeposit the metal as the free metal or its insoluble oxide or hydroxide, and then removing the semiconductor particles together with the adsorbed metal ions/oxides/hydroxide/free metal from the fluid. A method of decontaminating a contaminated fluid is also disclosed.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

PubMed Central

Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

2016-01-01

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

Review of silicon photonics: history and recent advances

NASA Astrophysics Data System (ADS)

Ye, Winnie N.; Xiong, Yule

2013-09-01

Silicon photonics has attracted tremendous attention and research effort as a promising technology in optoelectronic integration for computing, communications, sensing, and solar harvesting. Mainly due to the combination of its excellent material properties and the complementary metal-oxide semiconductor (CMOS) fabrication processing technology, silicon has becoming the material choice for photonic and optoelectronic circuits with low cost, ultra-compact device footprint, and high-density integration. This review paper provides an overview on silicon photonics, by highlighting the early work from the mid-1980s on the fundamental building blocks such as silicon platforms and waveguides, and the main milestones that have been achieved so far in the field. A summary of reported work on functional elements in both passive and active devices, as well as the applications of the technology in interconnect, sensing, and solar cells, is identified.

Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

PubMed Central

Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

2016-01-01

The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

An analog gamma correction scheme for high dynamic range CMOS logarithmic image sensors.

PubMed

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-12-15

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process.

Optical phased arrays with evanescently-coupled antennas

DOEpatents

Sun, Jie; Watts, Michael R; Yaacobi, Ami; Timurdogan, Erman

2015-03-24

An optical phased array formed of a large number of nanophotonic antenna elements can be used to project complex images into the far field. These nanophotonic phased arrays, including the nanophotonic antenna elements and waveguides, can be formed on a single chip of silicon using complementary metal-oxide-semiconductor (CMOS) processes. Directional couplers evanescently couple light from the waveguides to the nanophotonic antenna elements, which emit the light as beams with phases and amplitudes selected so that the emitted beams interfere in the far field to produce the desired pattern. In some cases, each antenna in the phased array may be optically coupled to a corresponding variable delay line, such as a thermo-optically tuned waveguide or a liquid-filled cell, which can be used to vary the phase of the antenna's output (and the resulting far-field interference pattern).

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

A graphene-based Fabry-Pérot spectrometer in mid-infrared region

PubMed Central

Wang, Xiaosai; Chen, Chen; Pan, Liang; Wang, Jicheng

2016-01-01

Mid-infrared spectroscopy is of great importance in many areas and its integration with thin-film technology can economically enrich the functionalities of many existing devices. In this paper we propose a graphene-based ultra-compact spectrometer (several micrometers in size) that is compatible with complementary metal-oxide-semiconductor (CMOS) processing. The proposed structure uses a monolayer graphene as a mid-infrared surface waveguide, whose optical response is spatially modulated using electric fields to form a Fabry-Pérot cavity. By varying the voltage acting on the cavity, we can control the transmitted wavelength of the spectrometer at room temperature. This design has potential applications in the graphene-silicon-based optoelectronic devices as it offers new possibilities for developing new ultra-compact spectrometers and low-cost hyperspectral imaging sensors in mid-infrared region. PMID:27573080

Power management circuits for self-powered systems based on micro-scale solar energy harvesting

NASA Astrophysics Data System (ADS)

Yoon, Eun-Jung; Yu, Chong-Gun

2016-03-01

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell's output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal-oxide-semiconductor process, and their performances are compared and analysed through measurements.

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

PubMed Central

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-01-01

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

Numerical investigation of metal-semiconductor-insulator-semiconductor passivated hole contacts based on atomic layer deposited AlO x

NASA Astrophysics Data System (ADS)

Ke, Cangming; Xin, Zheng; Ling, Zhi Peng; Aberle, Armin G.; Stangl, Rolf

2017-08-01

Excellent c-Si tunnel layer surface passivation has been obtained recently in our lab, using atomic layer deposited aluminium oxide (ALD AlO x ) in the tunnel layer regime of 0.9 to 1.5 nm, investigated to be applied for contact passivation. Using the correspondingly measured interface properties, this paper compares the theoretical collection efficiency of a conventional metal-semiconductor (MS) contact on diffused p+ Si to a metal-semiconductor-insulator-semiconductor (MSIS) contact on diffused p+ Si or on undoped n-type c-Si. The influences of (1) the tunnel layer passivation quality at the tunnel oxide interface (Q f and D it), (2) the tunnel layer thickness and the electron and hole tunnelling mass, (3) the tunnel oxide material, and (4) the semiconductor capping layer material properties are investigated numerically by evaluation of solar cell efficiency, open-circuit voltage, and fill factor.

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

NASA Astrophysics Data System (ADS)

Ferrandis, Philippe; Billaud, Mathilde; Duvernay, Julien; Martin, Mickael; Arnoult, Alexandre; Grampeix, Helen; Cassé, Mikael; Boutry, Hervé; Baron, Thierry; Vinet, Maud; Reimbold, Gilles

2018-04-01

To overcome the Fermi-level pinning in III-V metal-oxide-semiconductor capacitors, attention is usually focused on the choice of dielectric and surface chemical treatments prior to oxide deposition. In this work, we examined the influence of the III-V material surface cleaning and the semiconductor growth technique on the electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP(100) substrates. By means of the capacitance-voltage measurements, we demonstrated that samples do not have the same total oxide charge density depending on the cleaning solution used [(NH4)2S or NH4OH] prior to oxide deposition. The determination of the interface trap density revealed that a Fermi-level pinning occurs for samples grown by metalorganic chemical vapor deposition but not for similar samples grown by molecular beam epitaxy. Deep level transient spectroscopy analysis explained the Fermi-level pinning by an additional signal for samples grown by metalorganic chemical vapor deposition, attributed to the tunneling effect of carriers trapped in oxide toward interface states. This work emphasizes that the choice of appropriate oxide and cleaning treatment is not enough to prevent a Fermi-level pinning in III-V metal-oxide-semiconductor capacitors. The semiconductor growth technique needs to be taken into account because it impacts the trapping properties of the oxide.

Metal-Semiconductor Nanocomposites for High Efficiency Thermoelectric Power Generation

DTIC Science & Technology

2013-12-07

standard III–V compound semiconductor processing techniques with terbium- doped InGaAs of high terbium concentration, Journal of Vacuum Science...even lower the required temperature for strong covalent bonding. We performed the oxide bonding for this substrate transfer task (see Figure 16 for...appropriate controls for assessing ErSb:InGaSb and other nanocomposites of p-type III-V compound semiconductors and their alloys. UCSC group calculated

Process control of laser conduction welding by thermal imaging measurement with a color camera.

PubMed

Bardin, Fabrice; Morgan, Stephen; Williams, Stewart; McBride, Roy; Moore, Andrew J; Jones, Julian D C; Hand, Duncan P

2005-11-10

Conduction welding offers an alternative to keyhole welding. Compared with keyhole welding, it is an intrinsically stable process because vaporization phenomena are minimal. However, as with keyhole welding, an on-line process-monitoring system is advantageous for quality assurance to maintain the required penetration depth, which in conduction welding is more sensitive to changes in heat sinking. The maximum penetration is obtained when the surface temperature is just below the boiling point, and so we normally wish to maintain the temperature at this level. We describe a two-color optical system that we have developed for real-time temperature profile measurement of the conduction weld pool. The key feature of the system is the use of a complementary metal-oxide semiconductor standard color camera leading to a simplified low-cost optical setup. We present and discuss the real-time temperature measurement and control performance of the system when a defocused beam from a high power Nd:YAG laser is used on 5 mm thick stainless steel workpieces.

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

PubMed Central

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

PubMed Central

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique.

PubMed

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature.

Ultrafast acousto-optic mode conversion in optically birefringent ferroelectrics

PubMed Central

Lejman, Mariusz; Vaudel, Gwenaelle; Infante, Ingrid C.; Chaban, Ievgeniia; Pezeril, Thomas; Edely, Mathieu; Nataf, Guillaume F.; Guennou, Mael; Kreisel, Jens; Gusev, Vitalyi E.; Dkhil, Brahim; Ruello, Pascal

2016-01-01

The ability to generate efficient giga–terahertz coherent acoustic phonons with femtosecond laser makes acousto-optics a promising candidate for ultrafast light processing, which faces electronic device limits intrinsic to complementary metal oxide semiconductor technology. Modern acousto-optic devices, including optical mode conversion process between ordinary and extraordinary light waves (and vice versa), remain limited to the megahertz range. Here, using coherent acoustic waves generated at tens of gigahertz frequency by a femtosecond laser pulse, we reveal the mode conversion process and show its efficiency in ferroelectric materials such as BiFeO3 and LiNbO3. Further to the experimental evidence, we provide a complete theoretical support to this all-optical ultrafast mechanism mediated by acousto-optic interaction. By allowing the manipulation of light polarization with gigahertz coherent acoustic phonons, our results provide a novel route for the development of next-generation photonic-based devices and highlight new capabilities in using ferroelectrics in modern photonics. PMID:27492493

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

PubMed Central

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

NASA Astrophysics Data System (ADS)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.

High-contrast terahertz wave modulation by gated graphene enhanced by extraordinary transmission through ring apertures.

PubMed

Gao, Weilu; Shu, Jie; Reichel, Kimberly; Nickel, Daniel V; He, Xiaowei; Shi, Gang; Vajtai, Robert; Ajayan, Pulickel M; Kono, Junichiro; Mittleman, Daniel M; Xu, Qianfan

2014-03-12

Gate-controllable transmission of terahertz (THz) radiation makes graphene a promising material for making high-speed THz wave modulators. However, to date, graphene-based THz modulators have exhibited only small on/off ratios due to small THz absorption in single-layer graphene. Here we demonstrate a ∼50% amplitude modulation of THz waves with gated single-layer graphene by the use of extraordinary transmission through metallic ring apertures placed right above the graphene layer. The extraordinary transmission induced ∼7 times near-filed enhancement of THz absorption in graphene. These results promise complementary metal-oxide-semiconductor compatible THz modulators with tailored operation frequencies, large on/off ratios, and high speeds, ideal for applications in THz communications, imaging, and sensing.

Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

NASA Technical Reports Server (NTRS)

Adell, Philippe C.; Mojarradi, Mohammad; DelCastillo, Linda Y.; Vo, Tuan A.

2011-01-01

A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

A webcam in Bayer-mode as a light beam profiler for the near infra-red

PubMed Central

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-01-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique. PMID:23645943

Miniature biotelemeter gives multichannel wideband biomedical data

NASA Technical Reports Server (NTRS)

Carraway, J. B.

1972-01-01

A miniature biotelemeter was developed for sensing and transmitting multiple channels of biomedical data over a radio link. The design of this miniature, 10-channel, wideband (5 kHz/channel), pulse amplitude modulation/ frequency modulation biotelemeter takes advantage of modern device technology (e.g., integrated circuit operational amplifiers, complementary symmetry/metal oxide semiconductor logic, and solid state switches) and hybrid packaging techniques. The telemeter is being used to monitor 10 channels of neuron firings from specific regions of the brain in rats implanted with chronic electrodes. Design, fabrication, and testing of an engineering model biotelemeter are described.

Development of analog watch with minute repeater

NASA Astrophysics Data System (ADS)

Okigami, Tomio; Aoyama, Shigeru; Osa, Takashi; Igarashi, Kiyotaka; Ikegami, Tomomi

A complementary metal oxide semiconductor with large scale integration was developed for an electronic minute repeater. It is equipped with the synthetic struck sound circuit to generate natural struck sound necessary for the minute repeater. This circuit consists of an envelope curve drawing circuit, frequency mixer, polyphonic mixer, and booster circuit made by using analog circuit technology. This large scale integration is a single chip microcomputer with motor drivers and input ports in addition to the synthetic struck sound circuit, and it is possible to make an electronic system of minute repeater at a very low cost in comparison with the conventional type.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

Image Sensors Enhance Camera Technologies

NASA Technical Reports Server (NTRS)

2010-01-01

In the 1990s, a Jet Propulsion Laboratory team led by Eric Fossum researched ways of improving complementary metal-oxide semiconductor (CMOS) image sensors in order to miniaturize cameras on spacecraft while maintaining scientific image quality. Fossum s team founded a company to commercialize the resulting CMOS active pixel sensor. Now called the Aptina Imaging Corporation, based in San Jose, California, the company has shipped over 1 billion sensors for use in applications such as digital cameras, camera phones, Web cameras, and automotive cameras. Today, one of every three cell phone cameras on the planet feature Aptina s sensor technology.

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

NASA Astrophysics Data System (ADS)

Rahimunnisa, K.; Karthigaikumar, P.; Kirubavathy, J.; Jayakumar, J.; Kumar, S. Suresh

2014-02-01

A new architecture for encrypting and decrypting the confidential data using Advanced Encryption Standard algorithm is presented in this article. This structure combines the folded structure with parallel architecture to increase the throughput. The whole architecture achieved high throughput with less power. The proposed architecture is implemented in 0.13-µm Complementary metal-oxide-semiconductor (CMOS) technology. The proposed structure is compared with different existing structures, and from the result it is proved that the proposed structure gives higher throughput and less power compared to existing works.

A webcam in Bayer-mode as a light beam profiler for the near infra-red.

PubMed

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-05-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique.

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Ultra-high-extinction-ratio 2 × 2 silicon optical switch with variable splitter.

PubMed

Suzuki, Keijiro; Cong, Guangwei; Tanizawa, Ken; Kim, Sang-Hun; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-04-06

We demonstrate a record-high extinction-ratio of 50.4 dB in a 2 × 2 silicon Mach-Zehnder switch equipped with a variable splitter as the front 3-dB splitter. The variable splitter is adjusted to compensate for the splitting-ratio mismatch between the front and rear 3-dB splitters. The high extinction ratio does not rely on waveguide crossings and meets a strong demand in applications to multiport circuit switches. Large fabrication tolerance will make the high extinction ratio compatible with a volume production with standard complementary metal-oxide semiconductor fabrication facilities.

High Performance, Low Temperature Solution-Processed Barium and Strontium Doped Oxide Thin Film Transistors.

PubMed

Banger, Kulbinder K; Peterson, Rebecca L; Mori, Kiyotaka; Yamashita, Yoshihisa; Leedham, Timothy; Sirringhaus, Henning

2014-01-28

Amorphous mixed metal oxides are emerging as high performance semiconductors for thin film transistor (TFT) applications, with indium gallium zinc oxide, InGaZnO (IGZO), being one of the most widely studied and best performing systems. Here, we investigate alkaline earth (barium or strontium) doped InBa(Sr)ZnO as alternative, semiconducting channel layers and compare their performance of the electrical stress stability with IGZO. In films fabricated by solution-processing from metal alkoxide precursors and annealed to 450 °C we achieve high field-effect electron mobility up to 26 cm 2 V -1 s -1 . We show that it is possible to solution-process these materials at low process temperature (225-200 °C yielding mobilities up to 4.4 cm 2 V -1 s -1 ) and demonstrate a facile "ink-on-demand" process for these materials which utilizes the alcoholysis reaction of alkyl metal precursors to negate the need for complex synthesis and purification protocols. Electrical bias stress measurements which can serve as a figure of merit for performance stability for a TFT device reveal Sr- and Ba-doped semiconductors to exhibit enhanced electrical stability and reduced threshold voltage shift compared to IGZO irrespective of the process temperature and preparation method. This enhancement in stability can be attributed to the higher Gibbs energy of oxidation of barium and strontium compared to gallium.

High Performance, Low Temperature Solution-Processed Barium and Strontium Doped Oxide Thin Film Transistors

PubMed Central

2013-01-01

Amorphous mixed metal oxides are emerging as high performance semiconductors for thin film transistor (TFT) applications, with indium gallium zinc oxide, InGaZnO (IGZO), being one of the most widely studied and best performing systems. Here, we investigate alkaline earth (barium or strontium) doped InBa(Sr)ZnO as alternative, semiconducting channel layers and compare their performance of the electrical stress stability with IGZO. In films fabricated by solution-processing from metal alkoxide precursors and annealed to 450 °C we achieve high field-effect electron mobility up to 26 cm2 V–1 s–1. We show that it is possible to solution-process these materials at low process temperature (225–200 °C yielding mobilities up to 4.4 cm2 V–1 s–1) and demonstrate a facile “ink-on-demand” process for these materials which utilizes the alcoholysis reaction of alkyl metal precursors to negate the need for complex synthesis and purification protocols. Electrical bias stress measurements which can serve as a figure of merit for performance stability for a TFT device reveal Sr- and Ba-doped semiconductors to exhibit enhanced electrical stability and reduced threshold voltage shift compared to IGZO irrespective of the process temperature and preparation method. This enhancement in stability can be attributed to the higher Gibbs energy of oxidation of barium and strontium compared to gallium. PMID:24511184

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Spin-on metal oxide materials with high etch selectivity and wet strippability

NASA Astrophysics Data System (ADS)

Yao, Huirong; Mullen, Salem; Wolfer, Elizabeth; McKenzie, Douglas; Rahman, Dalil; Cho, JoonYeon; Padmanaban, Munirathna; Petermann, Claire; Hong, SungEun; Her, YoungJun

2016-03-01

Metal oxide or metal nitride films are used as hard mask materials in semiconductor industry for patterning purposes due to their excellent etch resistances against the plasma etches. Chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques are usually used to deposit the metal containing materials on substrates or underlying films, which uses specialized equipment and can lead to high cost-of-ownership and low throughput. We have reported novel spin-on coatings that provide simple and cost effective method to generate metal oxide films possessing good etch selectivity and can be removed by chemical agents. In this paper, new spin-on Al oxide and Zr oxide hard mask formulations are reported. The new metal oxide formulations provide higher metal content compared to previously reported material of specific metal oxides under similar processing conditions. These metal oxide films demonstrate ultra-high etch selectivity and good pattern transfer capability. The cured films can be removed by various chemical agents such as developer, solvents or wet etchants/strippers commonly used in the fab environment. With high metal MHM material as an underlayer, the pattern transfer process is simplified by reducing the number of layers in the stack and the size of the nano structure is minimized by replacement of a thicker film ACL. Therefore, these novel AZ® spinon metal oxide hard mask materials can potentially be used to replace any CVD or ALD metal, metal oxide, metal nitride or spin-on silicon-containing hard mask films in 193 nm or EUV process.

Novel Approach to Evaluation of Charging on Semiconductor Surface by Noncontact, Electrode-Free Capacitance/Voltage Measurement

NASA Astrophysics Data System (ADS)

Hirae, Sadao; Kohno, Motohiro; Okada, Hiroshi; Matsubara, Hideaki; Nakatani, Ikuyoshi; Kusuda, Tatsufumi; Sakai, Takamasa

1994-04-01

This paper describes a novel approach to the quantitative characterization of semiconductor surface charging caused by plasma exposures and ion implantations. The problems in conventional evaluation of charging are also discussed. Following the discussions above, the necessity of unified criteria is suggested for efficient development of systems or processes without charging damage. Hence, the charging saturation voltage between a top oxide surface and substrate, V s, and the charging density per unit area per second, ρ0, should be taken as criteria of charging behavior, which effectively represent the charging characteristics of both processes. The unified criteria can be obtained from the exposure time dependence of a net charging density on the thick field oxide. In order to determine V s and ρ0, the analysis using the C-V curve measured in a noncontact method with the metal-air-insulator-semiconductor (MAIS) technique is employed. The total space-charge density in oxide and its centroid can be determined at the same time by analyzing the flat-band voltage (V fb) of the MAIS capacitor as a function of the air gap. The net charge density can be obtained by analyzing the difference between the total space-charge density in oxide before and after charging. Finally, it is shown that charge damage of the large area metal-oxide-semiconductor (MOS) capacitor can be estimated from both V s and ρ0 which are obtained from results for a thick field oxide implanted with As+ and exposed to oxygen plasma.

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Comprehensive electrical analysis of metal/Al2O3/O-terminated diamond capacitance

NASA Astrophysics Data System (ADS)

Pham, T. T.; Maréchal, A.; Muret, P.; Eon, D.; Gheeraert, E.; Rouger, N.; Pernot, J.

2018-04-01

Metal oxide semiconductor capacitors were fabricated using p - type oxygen-terminated (001) diamond and Al2O3 deposited by atomic layer deposition at two different temperatures 250 °C and 380 °C. Current voltage I(V), capacitance voltage C(V), and capacitance frequency C(f) measurements were performed and analyzed for frequencies ranging from 1 Hz to 1 MHz and temperatures from 160 K to 360 K. A complete model for the Metal-Oxide-Semiconductor Capacitors electrostatics, leakage current mechanisms through the oxide into the semiconductor and small a.c. signal equivalent circuit of the device is proposed and discussed. Interface states densities are then evaluated in the range of 1012eV-1cm-2 . The strong Fermi level pinning is demonstrated to be induced by the combined effects of the leakage current through the oxide and the presence of diamond/oxide interface states.

Biodegradable elastomers and silicon nanomembranes/nanoribbons for stretchable, transient electronics, and biosensors.

PubMed

Hwang, Suk-Won; Lee, Chi Hwan; Cheng, Huanyu; Jeong, Jae-Woong; Kang, Seung-Kyun; Kim, Jae-Hwan; Shin, Jiho; Yang, Jian; Liu, Zhuangjian; Ameer, Guillermo A; Huang, Yonggang; Rogers, John A

2015-05-13

Transient electronics represents an emerging class of technology that exploits materials and/or device constructs that are capable of physically disappearing or disintegrating in a controlled manner at programmed rates or times. Inorganic semiconductor nanomaterials such as silicon nanomembranes/nanoribbons provide attractive choices for active elements in transistors, diodes and other essential components of overall systems that dissolve completely by hydrolysis in biofluids or groundwater. We describe here materials, mechanics, and design layouts to achieve this type of technology in stretchable configurations with biodegradable elastomers for substrate/encapsulation layers. Experimental and theoretical results illuminate the mechanical properties under large strain deformation. Circuit characterization of complementary metal-oxide-semiconductor inverters and individual transistors under various levels of applied loads validates the design strategies. Examples of biosensors demonstrate possibilities for stretchable, transient devices in biomedical applications.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Subwavelength InSb-based Slot wavguides for THz transport: concept and practical implementations.

PubMed

Ma, Youqiao; Zhou, Jun; Pištora, Jaromír; Eldlio, Mohamed; Nguyen-Huu, Nghia; Maeda, Hiroshi; Wu, Qiang; Cada, Michael

2016-12-07

Seeking better surface plasmon polariton (SPP) waveguides is of critical importance to construct the frequency-agile terahertz (THz) front-end circuits. We propose and investigate here a new class of semiconductor-based slot plasmonic waveguides for subwavelength THz transport. Optimizations of the key geometrical parameters demonstrate its better guiding properties for simultaneous realization of long propagation lengths (up to several millimeters) and ultra-tight mode confinement (~λ 2 /530) in the THz spectral range. The feasibility of the waveguide for compact THz components is also studied to lay the foundations for its practical implementations. Importantly, the waveguide is compatible with the current complementary metal-oxide-semiconductor (CMOS) fabrication technique. We believe the proposed waveguide configuration could offer a potential for developing a CMOS plasmonic platform and can be designed into various components for future integrated THz circuits (ITCs).

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

NASA Astrophysics Data System (ADS)

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

PubMed

Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-17

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

PubMed Central

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-01-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

Improvement of charge-pumping electrically detected magnetic resonance and its application to silicon metal-oxide-semiconductor field-effect transistor

NASA Astrophysics Data System (ADS)

Hori, Masahiro; Tsuchiya, Toshiaki; Ono, Yukinori

2017-01-01

Charge-pumping electrically detected magnetic resonance (CP EDMR), or EDMR in the CP mode, is improved and applied to a silicon metal-oxide-semiconductor field-effect transistor (MOSFET). Real-time monitoring of the CP process reveals that high-frequency transient currents are an obstacle to signal amplification for EDMR. Therefore, we introduce cutoff circuitry, leading to a detection limit for the number of spins as low as 103 for Si MOS interface defects. With this improved method, we demonstrate that CP EDMR inherits one of the most important features of the CP method: the gate control of the energy window of the detectable interface defects for spectroscopy.

Selective CO2 reduction conjugated with H2O oxidation utilizing semiconductor/metal-complex hybrid photocatalysts

NASA Astrophysics Data System (ADS)

Morikawa, T.; Sato, S.; Arai, T.; Uemura, K.; Yamanaka, K. I.; Suzuki, T. M.; Kajino, T.; Motohiro, T.

2013-12-01

We developed a new hybrid photocatalyst for CO2 reduction, which is composed of a semiconductor and a metal complex. In the hybrid photocatalyst, ΔG between the position of conduction band minimum (ECBM) of the semiconductor and the CO2 reduction potential of the complex is an essential factor for realizing fast electron transfer from the conduction band of semiconductor to metal complex leading to high photocatalytic activity. On the basis of this concept, the hybrid photocatalyst InP/Ru-complex, which functions in aqueous media, was developed. The photoreduction of CO2 to formate using water as an electron donor and a proton source was successfully achieved as a Z-scheme system by functionally conjugating the InP/Ru-complex photocatalyst for CO2 reduction with a TiO2 photocatalyst for water oxidation. The conversion efficiency from solar energy to chemical energy was ca. 0.04%, which approaches that for photosynthesis in a plant. Because this system can be applied to many other inorganic semiconductors and metal-complex catalysts, the efficiency and reaction selectivity can be enhanced by optimization of the electron transfer process including the energy-band configurations, conjugation conformations, and catalyst structures. This electrical-bias-free reaction is a huge leap forward for future practical applications of artificial photosynthesis under solar irradiation to produce organic species.

Interfacial oxide re-growth in thin film metal oxide III-V semiconductor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

McDonnell, S.; Dong, H.; Hawkins, J. M.

2012-04-02

The Al{sub 2}O{sub 3}/GaAs and HfO{sub 2}/GaAs interfaces after atomic layer deposition are studied using in situ monochromatic x-ray photoelectron spectroscopy. Samples are deliberately exposed to atmospheric conditions and interfacial oxide re-growth is observed. The extent of this re-growth is found to depend on the dielectric material and the exposure temperature. Comparisons with previous studies show that ex situ characterization can result in misleading conclusions about the interface reactions occurring during the metal oxide deposition process.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Visible light water splitting using dye-sensitized oxide semiconductors.

PubMed

Youngblood, W Justin; Lee, Seung-Hyun Anna; Maeda, Kazuhiko; Mallouk, Thomas E

2009-12-21

Researchers are intensively investigating photochemical water splitting as a means of converting solar to chemical energy in the form of fuels. Hydrogen is a key solar fuel because it can be used directly in combustion engines or fuel cells, or combined catalytically with CO(2) to make carbon containing fuels. Different approaches to solar water splitting include semiconductor particles as photocatalysts and photoelectrodes, molecular donor-acceptor systems linked to catalysts for hydrogen and oxygen evolution, and photovoltaic cells coupled directly or indirectly to electrocatalysts. Despite several decades of research, solar hydrogen generation is efficient only in systems that use expensive photovoltaic cells to power water electrolysis. Direct photocatalytic water splitting is a challenging problem because the reaction is thermodynamically uphill. Light absorption results in the formation of energetic charge-separated states in both molecular donor-acceptor systems and semiconductor particles. Unfortunately, energetically favorable charge recombination reactions tend to be much faster than the slow multielectron processes of water oxidation and reduction. Consequently, visible light water splitting has only recently been achieved in semiconductor-based photocatalytic systems and remains an inefficient process. This Account describes our approach to two problems in solar water splitting: the organization of molecules into assemblies that promote long-lived charge separation, and catalysis of the electrolysis reactions, in particular the four-electron oxidation of water. The building blocks of our artificial photosynthetic systems are wide band gap semiconductor particles, photosensitizer and electron relay molecules, and nanoparticle catalysts. We intercalate layered metal oxide semiconductors with metal nanoparticles. These intercalation compounds, when sensitized with [Ru(bpy)(3)](2+) derivatives, catalyze the photoproduction of hydrogen from sacrificial electron donors (EDTA(2-)) or non-sacrificial donors (I(-)). Through exfoliation of layered metal oxide semiconductors, we construct multilayer electron donor-acceptor thin films or sensitized colloids in which individual nanosheets mediate light-driven electron transfer reactions. When sensitizer molecules are "wired" to IrO(2).nH(2)O nanoparticles, a dye-sensitized TiO(2) electrode becomes the photoanode of a water-splitting photoelectrochemical cell. Although this system is an interesting proof-of-concept, the performance of these cells is still poor (approximately 1% quantum yield) and the dye photodegrades rapidly. We can understand the quantum efficiency and degradation in terms of competing kinetic pathways for water oxidation, back electron transfer, and decomposition of the oxidized dye molecules. Laser flash photolysis experiments allow us to measure these competing rates and, in principle, to improve the performance of the cell by changing the architecture of the electron transfer chain.

Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation.

PubMed

Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

2010-08-15

In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L(-1)). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K. Copyright 2010 Elsevier B.V. All rights reserved.

Semiconductor quantum dot super-emitters: spontaneous emission enhancement combined with suppression of defect environment using metal-oxide plasmonic metafilms

NASA Astrophysics Data System (ADS)

Sadeghi, Seyed M.; Wing, Waylin J.; Gutha, Rithvik R.; Sharp, Christina

2018-01-01

We demonstrate that a metal-oxide plasmonic metafilm consisting of a Si/Al oxide junction in the vicinity of a thin gold layer can quarantine excitons in colloidal semiconductor quantum dots against their defect environments. This process happens while the plasmon fields of the gold layer enhance spontaneous emission decay rates of the quantum dots. We study the emission dynamics of such quantum dots when the distance between the Si/Al oxide junction and the gold thin layer is varied. The results show that for distances less than a critical value the lifetime of the quantum dots can be elongated while they experience intense plasmon fields. This suggests that the metal-oxide metafilm can keep photo-excited electrons in the cores of the quantum dots, suppressing their migration to the surface defect sites. This leads to suppression of Auger recombination, offering quantum dot super-emitters with emission that is enhanced not only by the plasmon fields (Purcell effect), but also by strong suppression of the non-radiative decay caused by the defect sites.

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

PubMed

Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

2017-01-10

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swain, Basudev, E-mail: Swain@iae.re.kr; Mishra, Chinmayee; Lee, Chan Gi

2015-07-15

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leachmore » residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.« less

Dry soldering with hot filament produced atomic hydrogen

DOEpatents

Panitz, Janda K. G.; Jellison, James L.; Staley, David J.

1995-01-01

A system for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs.

Repeat analysis of intraoral digital imaging performed by undergraduate students using a complementary metal oxide semiconductor sensor: An institutional case study

PubMed Central

Rahman, Nur Liyana Abdul; Asri, Amiza Aqiela Ahmad; Othman, Noor Ilyani; Wan Mokhtar, Ilham

2017-01-01

Purpose This study was performed to quantify the repeat rate of imaging acquisitions based on different clinical examinations, and to assess the prevalence of error types in intraoral bitewing and periapical imaging using a digital complementary metal-oxide-semiconductor (CMOS) intraoral sensor. Materials and Methods A total of 8,030 intraoral images were retrospectively collected from 3 groups of undergraduate clinical dental students. The type of examination, stage of the procedure, and reasons for repetition were analysed and recorded. The repeat rate was calculated as the total number of repeated images divided by the total number of examinations. The weighted Cohen's kappa for inter- and intra-observer agreement was used after calibration and prior to image analysis. Results The overall repeat rate on intraoral periapical images was 34.4%. A total of 1,978 repeated periapical images were from endodontic assessment, which included working length estimation (WLE), trial gutta-percha (tGP), obturation, and removal of gutta-percha (rGP). In the endodontic imaging, the highest repeat rate was from WLE (51.9%) followed by tGP (48.5%), obturation (42.2%), and rGP (35.6%). In bitewing images, the repeat rate was 15.1% and poor angulation was identified as the most common cause of error. A substantial level of intra- and interobserver agreement was achieved. Conclusion The repeat rates in this study were relatively high, especially for certain clinical procedures, warranting training in optimization techniques and radiation protection. Repeat analysis should be performed from time to time to enhance quality assurance and hence deliver high-quality health services to patients. PMID:29279822

Fabrication of Smooth Patterned Structures of Refractory Metals, Semiconductors, and Oxides via Template Stripping

PubMed Central

2013-01-01

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics. PMID:24001174

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

PubMed

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-10-23

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

PubMed Central

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-01-01

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

PubMed Central

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-01-01

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors. PMID:28368355

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems.

PubMed

Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

2017-04-03

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

A self-reliant RSI payload development in Taiwan

NASA Astrophysics Data System (ADS)

Weng, Shui-Lin; Lian, Yu-Yung

2011-10-01

Instead of outsourcing the whole FORMOSAT-2 satellite to a foreign prime contractor, the National Space Organization in Taiwan is stepping ahead to take the full responsibility of consolidating self-reliant space technology capabilities. A newly initiated program FORMOSAT-5 satellite, not only to build a heritage design of a spacecraft bus but also, selfreliantly, to leap a big step toward Remote Sensing Instrument payload development, is sailing on its voyage. Among the payload development effort, an integrated circuit of the kind Complementary Metal Oxide Semiconductor instead of Charge-coupled Device is chosen as the image sensor playing the lead role for the instrument. Despite the foreseen technical concerns, management issues over scheduling and documentation are constantly emerging owing to the payload development underwent is collaborated by several domestic industries and research centers. Regardless of challenges we may confront with, a carefully planned strategy especially emphasizing on the product realization processes is considered, discussed, and implemented.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

An automated system using spatial oversampling for optical mapping in murine atria. Development and validation with monophasic and transmembrane action potentials.

PubMed

Yu, Ting Yue; Syeda, Fahima; Holmes, Andrew P; Osborne, Benjamin; Dehghani, Hamid; Brain, Keith L; Kirchhof, Paulus; Fabritz, Larissa

2014-08-01

We developed and validated a new optical mapping system for quantification of electrical activation and repolarisation in murine atria. The system makes use of a novel 2nd generation complementary metal-oxide-semiconductor (CMOS) camera with deliberate oversampling to allow both assessment of electrical activation with high spatial and temporal resolution (128 × 2048 pixels) and reliable assessment of atrial murine repolarisation using post-processing of signals. Optical recordings were taken from isolated, superfused and electrically stimulated murine left atria. The system reliably describes activation sequences, identifies areas of functional block, and allows quantification of conduction velocities and vectors. Furthermore, the system records murine atrial action potentials with comparable duration to both monophasic and transmembrane action potentials in murine atria. Copyright © 2014 The Authors. Published by Elsevier Ltd.. All rights reserved.

Microelectromechanical reprogrammable logic device.

PubMed

Hafiz, M A A; Kosuru, L; Younis, M I

2016-03-29

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

Microelectromechanical reprogrammable logic device

PubMed Central

Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

2016-01-01

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

Subeutectic Synthesis of Epitaxial Si-NWs with Diverse Catalysts Using a Novel Si Precursor

PubMed Central

2010-01-01

The applicability of a novel silicon precursor with respect to reasonable nanowire (NW) growth rates, feasibility of epitaxial NW growth and versatility with respect to diverse catalysts was investigated. Epitaxial growth of Si-NWs was achieved using octochlorotrisilane (OCTS) as Si precursor and Au as catalyst. In contrast to the synthesis approach with SiCl4 as precursor, OCTS provides Si without the addition of H2. By optimizing the growth conditions, effective NW synthesis is shown for alternative catalysts, in particular, Cu, Ag, Ni, and Pt with the latter two being compatible to complementary metal-oxide-semiconductor technology. As for these catalysts, the growth temperatures are lower than the lowest liquid eutectic; we suggest that the catalyst particle is in the solid state during NW growth and that a solid-phase diffusion process, either in the bulk, on the surface, or both, must be responsible for NW nucleation. PMID:20843058

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

NASA Technical Reports Server (NTRS)

Ohara, Tetsuo

2012-01-01

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems.

PubMed

Zumsteg, Zachary S; Kemere, Caleb; O'Driscoll, Stephen; Santhanam, Gopal; Ahmed, Rizwan E; Shenoy, Krishna V; Meng, Teresa H

2005-09-01

A new class of neural prosthetic systems aims to assist disabled patients by translating cortical neural activity into control signals for prosthetic devices. Based on the success of proof-of-concept systems in the laboratory, there is now considerable interest in increasing system performance and creating implantable electronics for use in clinical systems. A critical question that impacts system performance and the overall architecture of these systems is whether it is possible to identify the neural source of each action potential (spike sorting) in real-time and with low power. Low power is essential both for power supply considerations and heat dissipation in the brain. In this paper we report that state-of-the-art spike sorting algorithms are not only feasible using modern complementary metal oxide semiconductor very large scale integration processes, but may represent the best option for extracting large amounts of data in implantable neural prosthetic interfaces.

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications.

PubMed

Sang-Jin Lee; Kavehei, O; Yoon-Ki Hong; Tae Won Cho; Younggap You; Kyoungrok Cho; Eshraghian, K

2010-12-01

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Decoding mobile-phone image sensor rolling shutter effect for visible light communications

NASA Astrophysics Data System (ADS)

Liu, Yang

2016-01-01

Optical wireless communication (OWC) using visible lights, also known as visible light communication (VLC), has attracted significant attention recently. As the traditional OWC and VLC receivers (Rxs) are based on PIN photo-diode or avalanche photo-diode, deploying the complementary metal-oxide-semiconductor (CMOS) image sensor as the VLC Rx is attractive since nowadays nearly every person has a smart phone with embedded CMOS image sensor. However, deploying the CMOS image sensor as the VLC Rx is challenging. In this work, we propose and demonstrate two simple contrast ratio (CR) enhancement schemes to improve the contrast of the rolling shutter pattern. Then we describe their processing algorithms one by one. The experimental results show that both the proposed CR enhancement schemes can significantly mitigate the high-intensity fluctuations of the rolling shutter pattern and improve the bit-error-rate performance.

Impact of New Camera Technologies on Discoveries in Cell Biology.

PubMed

Stuurman, Nico; Vale, Ronald D

2016-08-01

New technologies can make previously invisible phenomena visible. Nowhere is this more obvious than in the field of light microscopy. Beginning with the observation of "animalcules" by Antonie van Leeuwenhoek, when he figured out how to achieve high magnification by shaping lenses, microscopy has advanced to this day by a continued march of discoveries driven by technical innovations. Recent advances in single-molecule-based technologies have achieved unprecedented resolution, and were the basis of the Nobel prize in Chemistry in 2014. In this article, we focus on developments in camera technologies and associated image processing that have been a major driver of technical innovations in light microscopy. We describe five types of developments in camera technology: video-based analog contrast enhancement, charge-coupled devices (CCDs), intensified sensors, electron multiplying gain, and scientific complementary metal-oxide-semiconductor cameras, which, together, have had major impacts in light microscopy. © 2016 Marine Biological Laboratory.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Electrografting of diazonium-functionalized polyoxometalates: synthesis, immobilisation and electron-transfer characterisation from glassy carbon.

PubMed

Rinfray, Corentin; Izzet, Guillaume; Pinson, Jean; Gam Derouich, Sarra; Ganem, Jean-Jacques; Combellas, Catherine; Kanoufi, Frédéric; Proust, Anna

2013-10-04

Polyoxometalates (POMs) are attractive candidates for the rational design of multi-level charge-storage materials because they display reversible multi-step reduction processes in a narrow range of potentials. The functionalization of POMs allows for their integration in hybrid complementary metal oxide semiconductor (CMOS)/molecular devices, provided that fine control of their immobilisation on various substrates can be achieved. Owing to the wide applicability of the diazonium route to surface modification, a functionalized Keggin-type POM [PW11 O39 {Ge(p-C6 H4 -CC-C6 H4 -${{\\rm N}{{+\\hfill \\atop 2\\hfill}}}$)}](3-) bearing a pending diazonium group was prepared and subsequently covalently anchored onto a glassy carbon electrode. Electron transfer with the immobilised POM was thoroughly investigated and compared to that of the free POM in solution. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Stabilized CdSe-CoPi composite photoanode for light-assisted water oxidation by transformation of a CdSe/cobalt metal thin film.

PubMed

Costi, Ronny; Young, Elizabeth R; Bulović, Vladimir; Nocera, Daniel G

2013-04-10

Integration of water splitting catalysts with visible-light-absorbing semiconductors would enable direct solar-energy-to-fuel conversion schemes such as those based on water splitting. A disadvantage of some common semiconductors that possess desirable optical bandgaps is their chemical instability under the conditions needed for oxygen evolution reaction (OER). In this study, we demonstrate the dual benefits gained from using a cobalt metal thin-film as the precursor for the preparation of cobalt-phosphate (CoPi) OER catalyst on cadmium chalcogenide photoanodes. The cobalt layer protects the underlying semiconductor from oxidation and degradation while forming the catalyst and simultaneously facilitates the advantageous incorporation of the cadmium chalcogenide layer into the CoPi layer during continued processing of the electrode. The resulting hybrid material forms a stable photoactive anode for light-assisted water splitting.

A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

NASA Astrophysics Data System (ADS)

Chien, Wei-Chih; Chen, Yi-Chou; Lee, Feng-Ming; Lin, Yu-Yu; Lai, Erh-Kun; Yao, Yeong-Der; Gong, Jeng; Horng, Sheng-Fu; Yeh, Chiao-Wen; Tsai, Shih-Chang; Lee, Ching-Hsiung; Huang, Yu-Kai; Chen, Chun-Fu; Kao, Hsiao-Feng; Shih, Yen-Hao; Hsieh, Kuang-Yeu; Lu, Chih-Yuan

2011-04-01

The behavior of WOX resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal-oxide-semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WOX ReRAM devices. The new Ni/WOX/W device can be switched at a low current density less than 8×105 A/cm2, with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Dispersion of Heat Flux Sensors Manufactured in Silicon Technology.

PubMed

Ziouche, Katir; Lejeune, Pascale; Bougrioua, Zahia; Leclercq, Didier

2016-06-09

In this paper, we focus on the dispersion performances related to the manufacturing process of heat flux sensors realized in CMOS (Complementary metal oxide semi-conductor) compatible 3-in technology. In particular, we have studied the performance dispersion of our sensors and linked these to the physical characteristics of dispersion of the materials used. This information is mandatory to ensure low-cost manufacturing and especially to reduce production rejects during the fabrication process. The results obtained show that the measured sensitivity of the sensors is in the range 3.15 to 6.56 μV/(W/m²), associated with measured resistances ranging from 485 to 675 kΩ. The dispersions correspond to a Gaussian-type distribution with more than 90% determined around average sensitivity S e ¯ = 4.5 µV/(W/m²) and electrical resistance R ¯ = 573.5 kΩ within the interval between the average and, more or less, twice the relative standard deviation.

Coincidence ion imaging with a fast frame camera

NASA Astrophysics Data System (ADS)

Lee, Suk Kyoung; Cudry, Fadia; Lin, Yun Fei; Lingenfelter, Steven; Winney, Alexander H.; Fan, Lin; Li, Wen

2014-12-01

A new time- and position-sensitive particle detection system based on a fast frame CMOS (complementary metal-oxide semiconductors) camera is developed for coincidence ion imaging. The system is composed of four major components: a conventional microchannel plate/phosphor screen ion imager, a fast frame CMOS camera, a single anode photomultiplier tube (PMT), and a high-speed digitizer. The system collects the positional information of ions from a fast frame camera through real-time centroiding while the arrival times are obtained from the timing signal of a PMT processed by a high-speed digitizer. Multi-hit capability is achieved by correlating the intensity of ion spots on each camera frame with the peak heights on the corresponding time-of-flight spectrum of a PMT. Efficient computer algorithms are developed to process camera frames and digitizer traces in real-time at 1 kHz laser repetition rate. We demonstrate the capability of this system by detecting a momentum-matched co-fragments pair (methyl and iodine cations) produced from strong field dissociative double ionization of methyl iodide.

Channel add-drop filter based on dual photonic crystal cavities in push-pull mode.

PubMed

Poulton, Christopher V; Zeng, Xiaoge; Wade, Mark T; Popović, Miloš A

2015-09-15

We demonstrate an add-drop filter based on a dual photonic crystal nanobeam cavity system that emulates the operation of a traveling wave resonator, and, thus, provides separation of the through and drop port transmission from the input port. The device is on a 3×3  mm chip fabricated in an advanced microelectronics silicon-on-insulator complementary metal-oxide semiconductor (SOI CMOS) process (IBM 45 nm SOI) without any foundry process modifications. The filter shows 1 dB of insertion loss in the drop port with a 3 dB bandwidth of 64 GHz, and 16 dB extinction in the through port. To the best of our knowledge, this is the first implementation of a port-separating, add-drop filter based on standing wave cavities coupled to conventional waveguides, and demonstrates a performance that suggests potential for photonic crystal devices within optical immersion lithography-based advanced CMOS electronics-photonics integration.

Super-resolution for scanning light stimulation systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bitzer, L. A.; Neumann, K.; Benson, N., E-mail: niels.benson@uni-due.de

Super-resolution (SR) is a technique used in digital image processing to overcome the resolution limitation of imaging systems. In this process, a single high resolution image is reconstructed from multiple low resolution images. SR is commonly used for CCD and CMOS (Complementary Metal-Oxide-Semiconductor) sensor images, as well as for medical applications, e.g., magnetic resonance imaging. Here, we demonstrate that super-resolution can be applied with scanning light stimulation (LS) systems, which are common to obtain space-resolved electro-optical parameters of a sample. For our purposes, the Projection Onto Convex Sets (POCS) was chosen and modified to suit the needs of LS systems.more » To demonstrate the SR adaption, an Optical Beam Induced Current (OBIC) LS system was used. The POCS algorithm was optimized by means of OBIC short circuit current measurements on a multicrystalline solar cell, resulting in a mean square error reduction of up to 61% and improved image quality.« less

Surface Charge Transfer Doping via Transition Metal Oxides for Efficient p-Type Doping of II-VI Nanostructures.

PubMed

Xia, Feifei; Shao, Zhibin; He, Yuanyuan; Wang, Rongbin; Wu, Xiaofeng; Jiang, Tianhao; Duhm, Steffen; Zhao, Jianwei; Lee, Shuit-Tong; Jie, Jiansheng

2016-11-22

Wide band gap II-VI nanostructures are important building blocks for new-generation electronic and optoelectronic devices. However, the difficulty of realizing p-type conductivity in these materials via conventional doping methods has severely handicapped the fabrication of p-n homojunctions and complementary circuits, which are the fundamental components for high-performance devices. Herein, by using first-principles density functional theory calculations, we demonstrated a simple yet efficient way to achieve controlled p-type doping on II-VI nanostructures via surface charge transfer doping (SCTD) using high work function transition metal oxides such as MoO 3 , WO 3 , CrO 3 , and V 2 O 5 as dopants. Our calculations revealed that these oxides were capable of drawing electrons from II-VI nanostructures, leading to accumulation of positive charges (holes injection) in the II-VI nanostructures. As a result, Fermi levels of the II-VI nanostructures were shifted toward the valence band regions after surface modifications, along with the large enhancement of work functions. In situ ultraviolet photoelectron spectroscopy and X-ray photoelectron spectroscopy characterizations verified the significant interfacial charge transfer between II-VI nanostructures and surface dopants. Both theoretical calculations and electrical transfer measurements on the II-VI nanostructure-based field-effect transistors clearly showed the p-type conductivity of the nanostructures after surface modifications. Strikingly, II-VI nanowires could undergo semiconductor-to-metal transition by further increasing the SCTD level. SCTD offers the possibility to create a variety of electronic and optoelectronic devices from the II-VI nanostructures via realization of complementary doping.

Materials and processing approaches for foundry-compatible transient electronics.

PubMed

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A; Song, Enming; Yu, Xinge; Rogers, John A

2017-07-11

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are ( i ) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, ( ii ) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and ( iii ) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Materials and processing approaches for foundry-compatible transient electronics

NASA Astrophysics Data System (ADS)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

PubMed

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Improved Hot Carrier Reliability Characteristics of Metal Oxide Semiconductor Field Effect Transistors with High-k Gate Dielectric by Using High Pressure Deuterium Post Metallization Annealing

NASA Astrophysics Data System (ADS)

Park, Hokyung; Choi, Rino; Lee, Byoung Hun; Hwang, Hyunsang

2007-09-01

High pressure deuterium annealing on the hot carrier reliability characteristics of HfSiO metal oxide semiconductor field effect transistor (MOSFET) was investigated. Comparing with the conventional forming gas (H2/Ar=10%/96%, 480 °C, 30 min) annealed sample, MOSFET annealed in 5 atm pure deuterium ambient at 400 °C showed the improvement of linear drain current, reduction of interface trap density, and improvement of the hot carrier reliability characteristics. These improvements can be attributed to the effective passivation of the interface trap site after high pressure annealing and heavy mass effect of deuterium. These results indicate that high pressure pure deuterium annealing can be a promising process for improving device performance as well as hot carrier reliability, together.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

High-Performance Quantum Dot Thin-Film Transistors with Environmentally Benign Surface Functionalization and Robust Defect Passivation.

PubMed

Jung, Su Min; Kang, Han Lim; Won, Jong Kook; Kim, JaeHyun; Hwang, ChaHwan; Ahn, KyungHan; Chung, In; Ju, Byeong-Kwon; Kim, Myung-Gil; Park, Sung Kyu

2018-01-31

The recent development of high-performance colloidal quantum dot (QD) thin-film transistors (TFTs) has been achieved with removal of surface ligand, defect passivation, and facile electronic doping. Here, we report on high-performance solution-processed CdSe QD-TFTs with an optimized surface functionalization and robust defect passivation via hydrazine-free metal chalcogenide (MCC) ligands. The underlying mechanism of the ligand effects on CdSe QDs has been studied with hydrazine-free ex situ reaction derived MCC ligands, such as Sn 2 S 6 4- , Sn 2 Se 6 4- , and In 2 Se 4 2- , to allow benign solution-process available. Furthermore, the defect passivation and remote n-type doping effects have been investigated by incorporating indium nanoparticles over the QD layer. Strong electronic coupling and solid defect passivation of QDs could be achieved by introducing electronically active MCC capping and thermal diffusion of the indium nanoparticles, respectively. It is also noteworthy that the diffused indium nanoparticles facilitate charge injection not only inter-QDs but also between source/drain electrodes and the QD semiconductors, significantly reducing contact resistance. With benign organic solvents, the Sn 2 S 6 4- , Sn 2 Se 6 4- , and In 2 Se 4 2- ligand based QD-TFTs exhibited field-effect mobilities exceeding 4.8, 12.0, and 44.2 cm 2 /(V s), respectively. The results reported here imply that the incorporation of MCC ligands and appropriate dopants provide a general route to high-performance, extremely stable solution-processed QD-based electronic devices with marginal toxicity, offering compatibility with standard complementary metal oxide semiconductor processing and large-scale on-chip device applications.

Positron studies of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-03-01

Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

Metal/oxide/semiconductor interface investigated by monoenergetic positrons

NASA Astrophysics Data System (ADS)

Uedono, A.; Tanigawa, S.; Ohji, Y.

1988-10-01

Variable-energy positron-beam studies have been carried out for the first time on a metal/oxide/semiconductor (MOS) structure of polycrystalline Si/SiO 2/Si-substrate. We were successful in collecting injected positrons at the SiO 2/Si interface by the application of an electric field between the MOS electrodes.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

Metal Oxide Semi-Conductor Gas Sensors in Environmental Monitoring

PubMed Central

Fine, George F.; Cavanagh, Leon M.; Afonja, Ayo; Binions, Russell

2010-01-01

Metal oxide semiconductor gas sensors are utilised in a variety of different roles and industries. They are relatively inexpensive compared to other sensing technologies, robust, lightweight, long lasting and benefit from high material sensitivity and quick response times. They have been used extensively to measure and monitor trace amounts of environmentally important gases such as carbon monoxide and nitrogen dioxide. In this review the nature of the gas response and how it is fundamentally linked to surface structure is explored. Synthetic routes to metal oxide semiconductor gas sensors are also discussed and related to their affect on surface structure. An overview of important contributions and recent advances are discussed for the use of metal oxide semiconductor sensors for the detection of a variety of gases—CO, NOx, NH3 and the particularly challenging case of CO2. Finally a description of recent advances in work completed at University College London is presented including the use of selective zeolites layers, new perovskite type materials and an innovative chemical vapour deposition approach to film deposition. PMID:22219672

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

PubMed

An Hu; Chodavarapu, Vamsy P

2010-10-01

We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

NASA Astrophysics Data System (ADS)

Kao, Wei-Chieh

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

Optical Fiber Chemical Sensor with Sol-Gel Derived Refractive Material as Transducer for High Temperature Gas Sensing in Clean Coal Technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shiquan Tao

2006-12-31

The chemistry of sol-gel derived silica and refractive metal oxide has been systematically studied. Sol-gel processes have been developed for preparing porous silica and semiconductor metal oxide materials. Micelle/reversed micelle techniques have been developed for preparing nanometer sized semiconductor metal oxides and noble metal particles. Techniques for doping metal ions, metal oxides and nanosized metal particles into porous sol-gel material have also been developed. Optical properties of sol-gel derived materials in ambient and high temperature gases have been studied by using fiber optic spectroscopic techniques, such as fiber optic ultraviolet/visible absorption spectrometry, fiber optic near infrared absorption spectrometry and fibermore » optic fluorescence spectrometry. Fiber optic spectrometric techniques have been developed for investigating the optical properties of these sol-gel derived materials prepared as porous optical fibers or as coatings on the surface of silica optical fibers. Optical and electron microscopic techniques have been used to observe the microstructure, such as pore size, pore shape, sensing agent distribution, of sol-gel derived material, as well as the size and morphology of nanometer metal particle doped in sol-gel derived porous silica, the nature of coating of sol-gel derived materials on silica optical fiber surface. In addition, the chemical reactions of metal ion, nanostructured semiconductor metal oxides and nanometer sized metal particles with gas components at room temperature and high temperatures have also been investigated with fiber optic spectrometric methods. Three classes of fiber optic sensors have been developed based on the thorough investigation of sol-gel chemistry and sol-gel derived materials. The first group of fiber optic sensors uses porous silica optical fibers doped with metal ions or metal oxide as transducers for sensing trace NH{sub 3} and H{sub 2}S in high temperature gas samples. The second group of fiber optic sensors uses sol-gel derived porous silica materials doped with nanometer particles of noble metals in the form of fiber or coating for sensing trace H{sub 2}, NH{sub 3} and HCl in gas samples at for applications ambient temperature. The third classes of fiber optic sensors use sol-gel derived semiconductor metal oxide coating on the surface of silica optical fiber as transducers for selectively sensing H{sub 2}, CH{sub 4} and CO at high temperature. In addition, optical fiber temperature sensors use the fluorescence signal of rare-earth metal ions doped porous silica optical fiber or the optical absorption signal of thermochromic metal oxide materials coated on the surface of silica optical fibers have also been developed for monitoring gas temperature of corrosive gas. Based on the results obtained from this project, the principle of fiber optic sensor techniques for monitoring matrix gas components as well as trace components of coal gasification derived syngas has been established. Prototype sensors for sensing trace ammonia and hydrogen sulfide in gasification derived syngas have been built up in our laboratory and have been tested using gas samples with matrix gas composition similar to that of gasification derived fuel gas. Test results illustrated the feasibility of these sensors for applications in IGCC processes.« less

Recent Radiation Test Results for Power MOSFETs

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Topper, Alyson D.; Casey, Megan C.; Wilcox, Edward P.; Phan, Anthony M.; Kim, Hak S.; LaBel, Kenneth A.

2013-01-01

Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Oxygen-ion-migration-modulated bipolar resistive switching and complementary resistive switching in tungsten/indium tin oxide/gold memory device

NASA Astrophysics Data System (ADS)

Wu, Xinghui; Zhang, Qiuhui; Cui, Nana; Xu, Weiwei; Wang, Kefu; Jiang, Wei; Xu, Qixing

2018-06-01

In this paper, we report our investigation of room-temperature-fabricated tungsten/indium tin oxide/gold (W/ITO/Au) resistive random access memory (RRAM), which exhibits asymmetric bipolar resistive switching (BRS) behavior. The device displays good write/erase endurance and data retention properties. The device shows complementary resistive switching (CRS) characteristics after controlling the compliance current. A WO x layer electrically formed at the W/ITO in the forming process. Mobile oxygen ions within ITO migrate toward the electrode/ITO interface and produce a semiconductor-like layer that acts as a free-carrier barrier. The CRS characteristic here can be elucidated in light of the evolution of an asymmetric free-carrier blocking layer at the electrode/ITO interface.

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nam, Chang-Yong; Stein, Aaron

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE PAGES

Nam, Chang-Yong; Stein, Aaron

2017-11-15

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Note: An improved 3D imaging system for electron-electron coincidence measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lin, Yun Fei; Lee, Suk Kyoung; Adhikari, Pradip

We demonstrate an improved imaging system that can achieve highly efficient 3D detection of two electrons in coincidence. The imaging system is based on a fast frame complementary metal-oxide semiconductor camera and a high-speed waveform digitizer. We have shown previously that this detection system is capable of 3D detection of ions and electrons with good temporal and spatial resolution. Here, we show that with a new timing analysis algorithm, this system can achieve an unprecedented dead-time (<0.7 ns) and dead-space (<1 mm) when detecting two electrons. A true zero dead-time detection is also demonstrated.

Note: An improved 3D imaging system for electron-electron coincidence measurements

NASA Astrophysics Data System (ADS)

Lin, Yun Fei; Lee, Suk Kyoung; Adhikari, Pradip; Herath, Thushani; Lingenfelter, Steven; Winney, Alexander H.; Li, Wen

2015-09-01

We demonstrate an improved imaging system that can achieve highly efficient 3D detection of two electrons in coincidence. The imaging system is based on a fast frame complementary metal-oxide semiconductor camera and a high-speed waveform digitizer. We have shown previously that this detection system is capable of 3D detection of ions and electrons with good temporal and spatial resolution. Here, we show that with a new timing analysis algorithm, this system can achieve an unprecedented dead-time (<0.7 ns) and dead-space (<1 mm) when detecting two electrons. A true zero dead-time detection is also demonstrated.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Facet-embedded thin-film III-V edge-emitting lasers integrated with SU-8 waveguides on silicon.

PubMed

Palit, Sabarni; Kirch, Jeremy; Huang, Mengyuan; Mawst, Luke; Jokerst, Nan Marie

2010-10-15

A thin-film InGaAs/GaAs edge-emitting single-quantum-well laser has been integrated with a tapered multimode SU-8 waveguide onto an Si substrate. The SU-8 waveguide is passively aligned to the laser using mask-based photolithography, mimicking electrical interconnection in Si complementary metal-oxide semiconductor, and overlaps one facet of the thin-film laser for coupling power from the laser to the waveguide. Injected threshold current densities of 260A/cm(2) are measured with the reduced reflectivity of the embedded laser facet while improving single mode coupling efficiency, which is theoretically simulated to be 77%.

Passive ultrasonics using sub-Nyquist sampling of high-frequency thermal-mechanical noise.

PubMed

Sabra, Karim G; Romberg, Justin; Lani, Shane; Degertekin, F Levent

2014-06-01

Monolithic integration of capacitive micromachined ultrasonic transducer arrays with low noise complementary metal oxide semiconductor electronics minimizes interconnect parasitics thus allowing the measurement of thermal-mechanical (TM) noise. This enables passive ultrasonics based on cross-correlations of diffuse TM noise to extract coherent ultrasonic waves propagating between receivers. However, synchronous recording of high-frequency TM noise puts stringent requirements on the analog to digital converter's sampling rate. To alleviate this restriction, high-frequency TM noise cross-correlations (12-25 MHz) were estimated instead using compressed measurements of TM noise which could be digitized at a sampling frequency lower than the Nyquist frequency.

A new coupling mechanism between two graphene electron waveguides for ultrafast switching

NASA Astrophysics Data System (ADS)

Huang, Wei; Liang, Shi-Jun; Kyoseva, Elica; Ang, Lay Kee

2018-03-01

In this paper, we report a novel coupling between two graphene electron waveguides, in analogy the optical waveguides. The design is based on the coherent quantum mechanical tunneling of Rabi oscillation between the two graphene electron waveguides. Based on this coupling mechanism, we propose that it can be used as an ultrafast electronic switching device. Based on a modified coupled mode theory, we construct a theoretical model to analyze the device characteristics, and predict that the switching speed is faster than 1 ps and the on-off ratio exceeds 106. Due to the long mean free path of electrons in graphene at room temperature, the proposed design avoids the limitation of low temperature operation required in the traditional design by using semiconductor quantum-well structure. The layout of our design is similar to that of a standard complementary metal-oxide-semiconductor transistor that should be readily fabricated with current state-of-art nanotechnology.

Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation

PubMed Central

Tseng, Yun-Hua; Lu, Chih-Wen

2017-01-01

Compressed sensing (CS) is a promising approach to the compression and reconstruction of electrocardiogram (ECG) signals. It has been shown that following reconstruction, most of the changes between the original and reconstructed signals are distributed in the Q, R, and S waves (QRS) region. Furthermore, any increase in the compression ratio tends to increase the magnitude of the change. This paper presents a novel approach integrating the near-precise compressed (NPC) and CS algorithms. The simulation results presented notable improvements in signal-to-noise ratio (SNR) and compression ratio (CR). The efficacy of this approach was verified by fabricating a highly efficient low-cost chip using the Taiwan Semiconductor Manufacturing Company’s (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The proposed core has an operating frequency of 60 MHz and gate counts of 2.69 K. PMID:28991216

Measurement of n-type Dry Thermally Oxidized 6H-SiC Metal-oxide Semiconductor Diodes by Quasistatic and High-Frequency Capacitance Versus Voltage and Capacitance Transient Techniques

NASA Technical Reports Server (NTRS)

Neudeck, P.; Kang, S.; Petit, J.; Tabib-Azar, M.

1994-01-01

Dry-oxidized n-type 6H-SiC metal-oxide-semiconductor capacitors are investigated using quasistatic capacitance versus voltage (C-V), high-frequency C-V, and pulsed high-frequency capacitance transient (C-t) analysis over the temperature range from 297 to 573 K. The quasistatic C - V characteristics presented are the first reported for 6H-SiC MOS capacitors, and exhibit startling nonidealities due to nonequilibrium conditions that arise from the fact that the recombination/generation process in 6H-SiC is extraordinarily slow even at the highest measurement temperature employed. The high-frequency dark C-V characteristics all showed deep depletion with no observable hysteresis. The recovery of the high-frequency capacitance from deep depletion to inversion was used to characterize the minority-carrier generation process as a function of temperature. Zerbst analysis conducted on the resulting C-t transients, which were longer than 1000 s at 573 K, showed a generation lifetime thermal activation energy of 0.49 eV.

Parasitic resistive switching uncovered from complementary resistive switching in single active-layer oxide memory device

NASA Astrophysics Data System (ADS)

Zhu, Lisha; Hu, Wei; Gao, Chao; Guo, Yongcai

2017-12-01

This paper reports the reversible transition processes between the bipolar and complementary resistive switching (CRS) characteristics on the binary metal-oxide resistive memory devices of Pt/HfO x /TiN and Pt/TaO x /TiN by applying the appropriate bias voltages. More interestingly, by controlling the amplitude of the negative bias, the parasitic resistive switching effect exhibiting repeatable switching behavior is uncovered from the CRS behavior. The electrical observation of the parasitic resistive switching effect can be explained by the controlled size of the conductive filament. This work confirms the transformation and interrelationship among the bipolar, parasitic, and CRS effects, and thus provides new insight into the understanding of the physical mechanism of the binary metal-oxide resistive switching memory devices.

Nanostructure-directed chemical sensing: The IHSAB principle and the dynamics of acid/base-interface interaction

PubMed Central

Laminack, William

2013-01-01

Summary Nanostructure-decorated n-type semiconductor interfaces are studied in order to develop chemical sensing with nanostructured materials. We couple the tenets of acid/base chemistry with the majority charge carriers of an extrinsic semiconductor. Nanostructured islands are deposited in a process that does not require self-assembly in order to direct a dominant electron-transduction process that forms the basis for reversible chemical sensing in the absence of chemical-bond formation. Gaseous analyte interactions on a metal-oxide-decorated n-type porous silicon interface show a dynamic electron transduction to and from the interface depending upon the relative strength of the gas and metal oxides. The dynamic interaction of NO with TiO2, SnO2, NiO, CuxO, and AuxO (x >> 1), in order of decreasing acidity, demonstrates this effect. Interactions with the metal-oxide-decorated interface can be modified by the in situ nitridation of the oxide nanoparticles, enhancing the basicity of the decorated interface. This process changes the interaction of the interface with the analyte. The observed change to the more basic oxinitrides does not represent a simple increase in surface basicity but appears to involve a change in molecular electronic structure, which is well explained by using the recently developed IHSAB model. The optical pumping of a TiO2 and TiO2− xNx decorated interface demonstrates a significant enhancement in the ability to sense NH3 and NO2. Comparisons to traditional metal-oxide sensors are also discussed. PMID:23400337

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Dry soldering with hot filament produced atomic hydrogen

DOEpatents

Panitz, J.K.G.; Jellison, J.L.; Staley, D.J.

1995-04-25

A system is disclosed for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs. 1 fig.

Selective CO{sub 2} reduction conjugated with H{sub 2}O oxidation utilizing semiconductor/metal-complex hybrid photocatalysts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morikawa, T., E-mail: morikawa@mosk.tytlabs.co.jp; Sato, S., E-mail: morikawa@mosk.tytlabs.co.jp; Arai, T., E-mail: morikawa@mosk.tytlabs.co.jp

2013-12-10

We developed a new hybrid photocatalyst for CO{sub 2} reduction, which is composed of a semiconductor and a metal complex. In the hybrid photocatalyst, ΔG between the position of conduction band minimum (E{sub CBM}) of the semiconductor and the CO{sub 2} reduction potential of the complex is an essential factor for realizing fast electron transfer from the conduction band of semiconductor to metal complex leading to high photocatalytic activity. On the basis of this concept, the hybrid photocatalyst InP/Ru-complex, which functions in aqueous media, was developed. The photoreduction of CO{sub 2} to formate using water as an electron donor andmore » a proton source was successfully achieved as a Z-scheme system by functionally conjugating the InP/Ru-complex photocatalyst for CO{sub 2} reduction with a TiO{sub 2} photocatalyst for water oxidation. The conversion efficiency from solar energy to chemical energy was ca. 0.04%, which approaches that for photosynthesis in a plant. Because this system can be applied to many other inorganic semiconductors and metal-complex catalysts, the efficiency and reaction selectivity can be enhanced by optimization of the electron transfer process including the energy-band configurations, conjugation conformations, and catalyst structures. This electrical-bias-free reaction is a huge leap forward for future practical applications of artificial photosynthesis under solar irradiation to produce organic species.« less

Single InAs/GaSb nanowire low-power CMOS inverter.

PubMed

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

A review of molecular beam epitaxy of ferroelectric BaTiO3 films on Si, Ge and GaAs substrates and their applications

PubMed Central

Mazet, Lucie; Yang, Sang Mo; Kalinin, Sergei V; Schamm-Chardon, Sylvie; Dubourdieu, Catherine

2015-01-01

SrTiO3 epitaxial growth by molecular beam epitaxy (MBE) on silicon has opened up the route to the monolithic integration of various complex oxides on the complementary metal-oxide–semiconductor silicon platform. Among functional oxides, ferroelectric perovskite oxides offer promising perspectives to improve or add functionalities on-chip. We review the growth by MBE of the ferroelectric compound BaTiO3 on silicon (Si), germanium (Ge) and gallium arsenide (GaAs) and we discuss the film properties in terms of crystalline structure, microstructure and ferroelectricity. Finally, we review the last developments in two areas of interest for the applications of BaTiO3 films on silicon, namely integrated photonics, which benefits from the large Pockels effect of BaTiO3, and low power logic devices, which may benefit from the negative capacitance of the ferroelectric. PMID:27877816

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

NASA Astrophysics Data System (ADS)

Kim, Y.; Pham, C.; Chang, J. P.

2015-02-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal-oxide-semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the materials’ full potential.

Facile Routes To Improve Performance of Solution-Processed Amorphous Metal Oxide Thin Film Transistors by Water Vapor Annealing.

PubMed

Park, Won-Tae; Son, Inyoung; Park, Hyun-Woo; Chung, Kwun-Bum; Xu, Yong; Lee, Taegweon; Noh, Yong-Young

2015-06-24

Here, we report on a simple and high-rate oxidization method for producing solution-based compound mixtures of indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO) metal-oxide semiconductors (MOS) for thin-film transistor (TFT) applications. One of the issues for solution-based MOS fabrication is how to sufficiently oxidize the precursor in order to achieve high performance. As the oxidation rate of solution processing is lower than vacuum-based deposition such as sputtering, devices using solution-processed MOS exhibit relatively poorer performance. Therefore, we propose a method to prepare the metal-oxide precursor upon exposure to saturated water vapor in a closed volume for increasing the oxidization efficiency without requiring additional oxidizing agent. We found that the hydroxide rate of the MOS film exposed to water vapor is lower than when unexposed (≤18%). Hence, we successfully fabricated oxide TFTs with high electron mobility (27.9 cm(2)/V·s) and established a rapid process (annealing at 400 °C for 5 min) that is much shorter than the conventional as-deposited long-duration annealing (at 400 °C for 1 h) whose corresponding mobility is even lower (19.2 cm(2)/V·s).

MCT/MOSFET Switch

NASA Technical Reports Server (NTRS)

Rippel, Wally E.

1990-01-01

Metal-oxide/semiconductor-controlled thyristor (MCT) and metal-oxide/semiconductor field-effect transistor (MOSFET) connected in switching circuit to obtain better performance. Offers high utilization of silicon, low forward voltage drop during "on" period of operating cycle, fast turnon and turnoff, and large turnoff safe operating area. Includes ability to operate at high temperatures, high static blocking voltage, and ease of drive.

Hierarchical Assembly of Multifunctional Oxide-based Composite Nanostructures for Energy and Environmental Applications

PubMed Central

Gao, Pu-Xian; Shimpi, Paresh; Gao, Haiyong; Liu, Caihong; Guo, Yanbing; Cai, Wenjie; Liao, Kuo-Ting; Wrobel, Gregory; Zhang, Zhonghua; Ren, Zheng; Lin, Hui-Jan

2012-01-01

Composite nanoarchitectures represent a class of nanostructured entities that integrates various dissimilar nanoscale building blocks including nanoparticles, nanowires, and nanofilms toward realizing multifunctional characteristics. A broad array of composite nanoarchitectures can be designed and fabricated, involving generic materials such as metal, ceramics, and polymers in nanoscale form. In this review, we will highlight the latest progress on composite nanostructures in our research group, particularly on various metal oxides including binary semiconductors, ABO3-type perovskites, A2BO4 spinels and quaternary dielectric hydroxyl metal oxides (AB(OH)6) with diverse application potential. Through a generic template strategy in conjunction with various synthetic approaches— such as hydrothermal decomposition, colloidal deposition, physical sputtering, thermal decomposition and thermal oxidation, semiconductor oxide alloy nanowires, metal oxide/perovskite (spinel) composite nanowires, stannate based nanocompostes, as well as semiconductor heterojunction—arrays and networks have been self-assembled in large scale and are being developed as promising classes of composite nanoarchitectures, which may open a new array of advanced nanotechnologies in solid state lighting, solar absorption, photocatalysis and battery, auto-emission control, and chemical sensing. PMID:22837702

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Improvement of hot-carrier and radiation hardnesses in metal-oxide-nitride-oxide semiconductor devices by irradiation-then-anneal treatments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang-Liao, K.S.; Hwu, J.G.

The hardnesses of hot-carrier and radiation of metal-oxide nitride-oxide semiconductor (MONOS) devices can be improved by the irradiation-then-anneal (ITA) treatments. Each treatment includes an irradiation of Co-60 with a total dose of 1M rads(SiO[sub 2]) and an anneal in N[sub 2] at 400 C for 10 min successively. This improvement can be explained by the release of SiO[sub 2]/Si interfacial strain.

Metal-oxide-semiconductor devices using Ga2O3 dielectrics on n-type GaN

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Chen, Hong-Wei; Lee, Hsin-Ying

2003-06-01

Using a photoelectrochemical method involving a He-Cd laser, Ga2O3 oxide layers were directly grown on n-type GaN. We demonstrated the performance of the resultant metal-oxide-semiconductor devices based on the grown Ga2O3 layer. An extremely low reverse leakage current of 200 pA was achieved when devices operated at -20 V. Furthermore, high forward and reverse breakdown electric fields of 2.80 MV/cm and 5.70 MV/cm, respectively, were obtained. Using a photoassisted current-voltage method, a low interface state density of 2.53×1011 cm-2 eV-1 was estimated. The varactor devices permit formation of inversion layers, so that they may be applied for the fabrication of metal-oxide-semiconductor field-effect transistors.

Understanding the synthesis, performance, and passivation of metal oxide photocathodes

NASA Astrophysics Data System (ADS)

Flynn, Cory James

Metal oxides are ubiquitous in semiconductor technologies for their ease of synthesis, chemical stability, and tunable optical/electronic properties. These properties are especially important to fabricating efficient photoelectrodes for solar-energy applications. To counter inherent problems in these materials, new strategies were developed and successfully implemented on the widely-utilized p-type semiconductor, NiO. As the size of semiconductor materials shrink, the surface-to-volume ratio increases and surface defects dominate the performance of the materials. Surface defects can alter the optical and electronic characteristics of materials by changing the Fermi level, charge-carrier mobility, and surface reactivity. We first present a strategy to increase the electrical mobility of mesoporous metal oxide electrode materials by optimizing shape morphology. Transitioning from nanospheres to hexagonal nanoplatelets increased the charge-carrier mobility by one order of magnitude. We then employed this improved material with a new vapor-phase deposition method termed targeted atomic deposition (TAD) to selectively passivate defect sites in semiconductor nanomaterials. We demonstrated the capabilities of this passivation method by applying a TAD of aluminum onto NiO. By exploiting a temperature-dependent deposition process, we selectively passivated the highly reactive sites in NiO: oxygen dangling bonds associated with Ni vacancies. The TAD treatment completely passivated all measurable surface defects, optically bleached the material, and significantly improved all photovoltaic performance metrics in dye-sensitized solar cells. The technique was proven to be generic to numerous forms of NiO. While the implementation of TAD of Al was successful, the process involved pulsing two precursors to passivate the material. Ideally, the TAD process should require only a single precursor and continuous exposure. We utilized a continuous flow of diborane to perform a TAD of B onto NiO. The TAD process was successfully implemented in a simplified manner. The treatment moderately increased DSSC performance and proved viability with a different vapor-phase precursor.

Rapid Transition of the Hole Rashba Effect from Strong Field Dependence to Saturation in Semiconductor Nanowires

NASA Astrophysics Data System (ADS)

Luo, Jun-Wei; Li, Shu-Shen; Zunger, Alex

2017-09-01

The electric field manipulation of the Rashba spin-orbit coupling effects provides a route to electrically control spins, constituting the foundation of the field of semiconductor spintronics. In general, the strength of the Rashba effects depends linearly on the applied electric field and is significant only for heavy-atom materials with large intrinsic spin-orbit interaction under high electric fields. Here, we illustrate in 1D semiconductor nanowires an anomalous field dependence of the hole (but not electron) Rashba effect (HRE). (i) At low fields, the strength of the HRE exhibits a steep increase with the field so that even low fields can be used for device switching. (ii) At higher fields, the HRE undergoes a rapid transition to saturation with a giant strength even for light-atom materials such as Si (exceeding 100 meV Å). (iii) The nanowire-size dependence of the saturation HRE is rather weak for light-atom Si, so size fluctuations would have a limited effect; this is a key requirement for scalability of Rashba-field-based spintronic devices. These three features offer Si nanowires as a promising platform for the realization of scalable complementary metal-oxide-semiconductor compatible spintronic devices.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Microscale Soft Patterning for Solution Processable Metal Oxide Thin Film Transistors.

PubMed

Jung, Sang Wook; Chae, Soo Sang; Park, Jee Ho; Oh, Jin Young; Bhang, Suk Ho; Baik, Hong Koo; Lee, Tae Il

2016-03-23

We introduce a microscale soft pattering (MSP) route utilizing contact printing of chemically inert sub-nanometer thick low molecular weight (LMW) poly(dimethylsiloxane) (PDMS) layers. These PDMS layers serve as a release agent layer between the n-type Ohmic metal and metal oxide semiconductors (MOSs) and provide a layer that protects the MOS from water in the surrounding environment. The feasibility of our MSP route was experimentally demonstrated by fabricating solution processable In2O3, IZO, and IGZO TFTs with aluminum (Al), a typical n-type Ohmic metal. We have demonstrated patterning gaps as small as 13 μm. The TFTs fabricated using MSP showed higher field-effect-mobility and lower hysteresis in comparison with those made using conventional photolithography.

Thermomechanical Stresses Analysis of a Single Event Burnout Process

NASA Astrophysics Data System (ADS)

Tais, Carlos E.; Romero, Eduardo; Demarco, Gustavo L.

2009-06-01

This work analyzes the thermal and mechanical effects arising in a power Diffusion Metal Oxide Semiconductor (DMOS) during a Single Event Burnout (SEB) process. For studying these effects we propose a more detailed simulation structure than the previously used by other authors, solving the mathematical models by means of the Finite Element Method. We use a cylindrical heat generation region, with 5 W, 10 W, 50 W and 100 W for emulating the thermal phenomena occurring during SEB processes, avoiding the complexity of the mathematical treatment of the ion-semiconductor interaction.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Method of photocatalytic conversion of C-H organics

DOEpatents

Camaioni, Donald M.; Lilga, Michael A.

1998-01-01

The present invention is the addition of a semiconductor material and energy to the reaction mixture of organic, acid (for example, trifluoroacetate), and oxygen. A transition metal ion may be added to the reaction mixture. The semiconductor material converts energy to oxidants thereby promoting oxidation of the organic. Alternatively, using metal in combination with exposure to light may be used.

Method of photocatalytic conversion of C-H organics

DOEpatents

Camaioni, D.M.; Lilga, M.A.

1998-01-13

The present invention is the addition of a semiconductor material and energy to the reaction mixture of organic, acid (for example, trifluoroacetate), and oxygen. A transition metal ion may be added to the reaction mixture. The semiconductor material converts energy to oxidants thereby promoting oxidation of the organic. Alternatively, using metal in combination with exposure to light may be used.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

In situ growth of metal particles on 3D urchin-like WO3 nanostructures.

PubMed

Xi, Guangcheng; Ye, Jinhua; Ma, Qiang; Su, Ning; Bai, Hua; Wang, Chao

2012-04-18

Metal/semiconductor hybrid materials of various sizes and morphologies have many applications in areas such as catalysis and sensing. Various organic agents are necessary to stabilize metal nanoparticles during synthesis, which leads to a layer of organic compounds present at the interfaces between the metal particles and the semiconductor supports. Generally, high-temperature oxidative treatment is used to remove the organics, which can extensively change the size and morphology of the particles, in turn altering their activity. Here we report a facile method for direct growth of noble-metal particles on WO(3) through an in situ redox reaction between weakly reductive WO(2.72) and oxidative metal salts in aqueous solution. This synthetic strategy has the advantages that it takes place in one step and requires no foreign reducing agents, stabilizing agents, or pretreatment of the precursors, making it a practical method for the controlled synthesis of metal/semiconductor hybrid nanomaterials. This synthetic method may open up a new way to develop metal-nanoparticle-loaded semiconductor composites. © 2012 American Chemical Society

A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Sedki, Amor; André, Nicolas; Kilchytska, Valéria; Gérard, Pierre; Ali, Zeeshan; Udrea, Florin; Flandre, Denis

2018-01-01

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

Detection of Short-Waved Spin Waves in Individual Microscopic Spin-Wave Waveguides Using the Inverse Spin Hall Effect.

PubMed

Brächer, T; Fabre, M; Meyer, T; Fischer, T; Auffret, S; Boulle, O; Ebels, U; Pirro, P; Gaudin, G

2017-12-13

The miniaturization of complementary metal-oxide-semiconductor (CMOS) devices becomes increasingly difficult due to fundamental limitations and the increase of leakage currents. Large research efforts are devoted to find alternative concepts that allow for a larger data-density and lower power consumption than conventional semiconductor approaches. Spin waves have been identified as a potential technology that can complement and outperform CMOS in complex logic applications, profiting from the fact that these waves enable wave computing on the nanoscale. The practical application of spin waves, however, requires the demonstration of scalable, CMOS compatible spin-wave detection schemes in material systems compatible with standard spintronics as well as semiconductor circuitry. Here, we report on the wave-vector independent detection of short-waved spin waves with wavelengths down to 150 nm by the inverse spin Hall effect in spin-wave waveguides made from ultrathin Ta/Co 8 Fe 72 B 20 /MgO. These findings open up the path for miniaturized scalable interconnects between spin waves and CMOS and the use of ultrathin films made from standard spintronic materials in magnonics.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

NASA Astrophysics Data System (ADS)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Memory effects in a Al/Ti:HfO2/CuPc metal-oxide-semiconductor device

NASA Astrophysics Data System (ADS)

Tripathi, Udbhav; Kaur, Ramneek

2016-05-01

Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO2) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Smart Camera Technology Increases Quality

NASA Technical Reports Server (NTRS)

2004-01-01

When it comes to real-time image processing, everyone is an expert. People begin processing images at birth and rapidly learn to control their responses through the real-time processing of the human visual system. The human eye captures an enormous amount of information in the form of light images. In order to keep the brain from becoming overloaded with all the data, portions of an image are processed at a higher resolution than others, such as a traffic light changing colors. changing colors. In the same manner, image processing products strive to extract the information stored in light in the most efficient way possible. Digital cameras available today capture millions of pixels worth of information from incident light. However, at frame rates more than a few per second, existing digital interfaces are overwhelmed. All the user can do is store several frames to memory until that memory is full and then subsequent information is lost. New technology pairs existing digital interface technology with an off-the-shelf complementary metal oxide semiconductor (CMOS) imager to provide more than 500 frames per second of specialty image processing. The result is a cost-effective detection system unlike any other.

A review of molecular beam epitaxy of ferroelectric BaTiO 3 films on Si, Ge and GaAs substrates and their applications

DOE PAGES

Mazet, Lucie; Yang, Sang Mo; Kalinin, Sergei V.; ...

2015-06-30

SrTiO 3 epitaxial growth by molecular beam epitaxy (MBE) on silicon has opened up the route to the monolithic integration of various complex oxides on the complementary metal-oxide-semiconductor silicon platform. Among functional oxides, ferroelectric perovskite oxides offer promising perspectives to improve or add functionalities on-chip. We review the growth by MBE of the ferroelectric compound BaTiO 3 on silicon (Si), germanium (Ge) and gallium arsenide (GaAs) and we discuss the film properties in terms of crystalline structure, microstructure and ferroelectricity. Lastly, we review the last developments in two areas of interest for the applications of BaTiO 3 films on silicon,more » namely integrated photonics, which benefits from the large Pockels effect of BaTiO 3, and low power logic devices, which may benefit from the negative capacitance of the ferroelectric.« less

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Solution combustion synthesis of oxide semiconductors

NASA Astrophysics Data System (ADS)

Thomas, Abegayl Lorenda Shara-Lynn

The quest for stable and efficient photocatalytic materials beyond TiO2 and WO3 has over the years led to the development of new materials that possess varied interfacial energetics. This dissertation study focused on using for the first time a novel method, solution combustion synthesis (SCS), to prepare two distinct families of binary metal-based oxide semiconductor materials. Detailed studies on material characteristics and applications were carried out on tungsten- and niobium-based oxide semiconductors with varying principal metals. Initial emphasis was placed on the SCS of tungsten-based oxide semiconductors (ZnWO4, CuWO4, and Ag2WO4). The influence of different tungsten precursor's on the resultant product was of particular relevance to this study, with the most significant effects highlighted. Upon characterization, each sample's photocatalytic activity towards methyl orange dye degradation was studied, and benchmarked against their respective commercial oxide sample, obtained by solid-state ceramic synthesis. Detailed analysis highlighted the importance of the SCS process as a time- and energy-efficient method to produce crystalline nano-sized materials even without additional or excessive heat treatment. It was observed that using different tungstate precursors does influence the structural and morphological make-up of the resulting materials. The as-synthesized tungstate materials showed good photocatalytic performance for the degradation of methyl orange dye, while taking into account specific surface area and adsorbed dye amount on the surface of the material. Like the tungstate's, niobium-based oxide semiconductors CuNb 2O6 and ZnNb2O6 were the first to be synthesized via solution combustion synthesis. Particular attention was placed on the crystal structures formed while using an oxalate niobium precursor during the reaction process. X-ray patterns yielded a multiphase structure for the ZnNb2O6 and a single phase structure for CuNb 2O6. Photoelectrochemical (PEC) measurements were used both as a characterization tool as well as an application for CO2 reduction. The PEC data was consistent with an n-type and p-type semiconductor for ZnNb 2O6 and CuNb2O6 respectively. Good phototelectrochemical behavior was observed for CuNb2O6 with stable, high photocurrents suggesting a suitable material for CO 2 reduction while in a 0.1 M NaHCO3 + CO2 medium. All in all, this dissertation study expounds on metal ion insertion into various structural frameworks (e.g. WO3) which may open sustainable materials chemistry avenues to solar energy conversion and environmental remediation.

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

PubMed

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis.

The Pr 2O 3/Si(0 0 1) interface studied by synchrotron radiation photo-electron spectroscopy

NASA Astrophysics Data System (ADS)

Schmeißer, D.; Müssig, H.-J.

2003-10-01

Pr 2O 3 is currently under consideration as a potential replacement for SiO 2 as the gate-dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. We studied the Pr 2O 3/Si(0 0 1) interface by a non-destructive depth profiling using synchrotron radiation photoelectron spectroscopy. Our data suggests that there is no silicide formation at the interface. Based on reported results, a chemical reactive interface exists, consisting of a mixed Si-Pr oxide such as (Pr 2O 3) x(SiO 2) 1- x, i.e. as a silicate phase with variable silicon content. This pseudo-binary alloy at the interface offers large flexibility toward successful integration of Pr 2O 3 into future CMOS technologies.

Colossal change in thermopower with temperature-driven p-n-type conduction switching in La x Sr2-x TiFeO6 double perovskites

NASA Astrophysics Data System (ADS)

Roy, Pinku; Maiti, Tanmoy

2018-02-01

Double perovskite materials have been studied in detail by many researchers, as their magnetic and electronic properties can be controlled by the substitution of alkaline earth metals or lanthanides in the A site and transition metals in the B site. Here we report the temperature-driven, p-n-type conduction switching assisted, large change in thermopower in La3+-doped Sr2TiFeO6-based double perovskites. Stoichiometric compositions of La x Sr2-x TiFeO6 (LSTF) with 0  ⩽  x  ⩽  0.25 were synthesized by the solid-state reaction method. Rietveld refinement of room-temperature XRD data confirmed a single-phase solid solution with cubic crystal structure and Pm\\bar{3}m space group. From temperature-dependent electrical conductivity and Seebeck coefficient (S) studies it is evident that all the compositions underwent an intermediate semiconductor-to-metal transition before the semiconductor phase reappeared at higher temperature. In the process of semiconductor-metal-semiconductor transition, LSTF compositions demonstrated temperature-driven p-n-type conduction switching behavior. The electronic restructuring which occurs due to the intermediate metallic phase between semiconductor phases leads to the colossal change in S for LSTF oxides. The maximum drop in thermopower (ΔS ~ 2516 µV K-1) was observed for LSTF with x  =  0.1 composition. Owing to their enormous change in thermopower of the order of millivolts per kelvin, integrated with p-n-type resistance switching, these double perovskites can be used for various high-temperature multifunctional device applications such as diodes, sensors, switches, thermistors, thyristors, thermal runaway monitors etc. Furthermore, the conduction mechanisms of these oxides were explained by the small polaron hopping model.

Plasmonic doped semiconductor nanocrystals: Properties, fabrication, applications and perspectives

NASA Astrophysics Data System (ADS)

Kriegel, Ilka; Scotognella, Francesco; Manna, Liberato

2017-02-01

Degenerately doped semiconductor nanocrystals (NCs) are of recent interest to the NC community due to their tunable localized surface plasmon resonances (LSPRs) in the near infrared (NIR). The high level of doping in such materials with carrier densities in the range of 1021cm-3 leads to degeneracy of the doping levels and intense plasmonic absorption in the NIR. The lower carrier density in degenerately doped semiconductor NCs compared to noble metals enables LSPR tuning over a wide spectral range, since even a minor change of the carrier density strongly affects the spectral position of the LSPR. Two classes of degenerate semiconductors are most relevant in this respect: impurity doped semiconductors, such as metal oxides, and vacancy doped semiconductors, such as copper chalcogenides. In the latter it is the density of copper vacancies that controls the carrier concentration, while in the former the introduction of impurity atoms adds carriers to the system. LSPR tuning in vacancy doped semiconductor NCs such as copper chalcogenides occurs by chemically controlling the copper vacancy density. This goes in hand with complex structural modifications of the copper chalcogenide crystal lattice. In contrast the LSPR of degenerately doped metal oxide NCs is modified by varying the doping concentration or by the choice of host and dopant atoms, but also through the addition of capacitive charge carriers to the conduction band of the metal oxide upon post-synthetic treatments, such as by electrochemical- or photodoping. The NIR LSPRs and the option of their spectral fine-tuning make accessible important new features, such as the controlled coupling of the LSPR to other physical signatures or the enhancement of optical signals in the NIR, sensing application by LSPR tracking, energy production from the NIR plasmon resonance or bio-medical applications in the biological window. In this review we highlight the recent advances in the synthesis of various different plasmonic semiconductor NCs with LSPRs covering the entire spectral range, from the mid- to the NIR. We focus on copper chalcogenide NCs and impurity doped metal oxide NCs as the most investigated alternatives to noble metals. We shed light on the structural changes upon LSPR tuning in vacancy doped copper chalcogenide NCs and deliver a picture for the fundamentally different mechanism of LSPR modification of impurity doped metal oxide NCs. We review on the peculiar optical properties of plasmonic degenerately doped NCs by highlighting the variety of different optical measurements and optical modeling approaches. These findings are merged in an exhaustive section on new and exciting applications based on the special characteristics that plasmonic semiconductor NCs bring along.

Lowering the environmental impact of high-kappa/ metal gate stack surface preparation processes

NASA Astrophysics Data System (ADS)

Zamani, Davoud

ABSTRACT Hafnium based oxides and silicates are promising high-κ dielectrics to replace SiO2 as gate material for state-of-the-art semiconductor devices. However, integrating these new high-κ materials into the existing complementary metal-oxide semiconductor (CMOS) process remains a challenge. One particular area of concern is the use of large amounts of HF during wet etching of hafnium based oxides and silicates. The patterning of thin films of these materials is accomplished by wet etching in HF solutions. The use of HF allows dissolution of hafnium as an anionic fluoride complex. Etch selectivity with respect to SiO2 is achieved by appropriately diluting the solutions and using slightly elevated temperatures. From an ESH point of view, it would be beneficial to develop methods which would lower the use of HF. The first objective of this study is to find new chemistries and developments of new wet etch methods to reduce fluoride consumption during wet etching of hafnium based high-κ materials. Another related issue with major environmental impact is the usage of large amounts of rinsing water for removal of HF in post-etch cleaning step. Both of these require a better understanding of the HF interaction with the high-κ surface during the etching, cleaning, and rinsing processes. During the rinse, the cleaning chemical is removed from the wafers. Ensuring optimal resource usage and cycle time during the rinse requires a sound understanding and quantitative description of the transport effects that dominate the removal rate of the cleaning chemicals from the surfaces. Multiple processes, such as desorption and re-adsorption, diffusion, migration and convection, all factor into the removal rate of the cleaning chemical during the rinse. Any of these processes can be the removal rate limiting process, the bottleneck of the rinse. In fact, the process limiting the removal rate generally changes as the rinse progresses, offering the opportunity to save resources. The second objective of this study is to develop new rinse methods to reduce water and energy usage during rinsing and cleaning of hafnium based high-κ materials in single wafer-cleaning tools. It is necessary to have a metrology method which can study the effect of all process parameters that affect the rinsing by knowing surface concentration of contaminants in patterned hafnium based oxides and silicate wafers. This has been achieved by the introduction of a metrology method at The University of Arizona which monitors the transport of contaminant concentrations inside micro- and nano- structures. This is the only metrology which will be able to provide surface concentration of contaminants inside hafnium based oxides and silicate micro-structures while the rinsing process is taking place. The goal of this research is to study the effect of various process parameters on rinsing of patterned hafnium based oxides and silicate wafers, and modify a metrology method for end point detection.

Comparative analysis of breakdown mechanism in thin SiO2 oxide films in metal-oxide-semiconductor structures under the action of heavy charged particles and a pulsed voltage

NASA Astrophysics Data System (ADS)

Zinchenko, V. F.; Lavrent'ev, K. V.; Emel'yanov, V. V.; Vatuev, A. S.

2016-02-01

Regularities in the breakdown of thin SiO2 oxide films in metal-oxide-semiconductors structures of power field-effect transistors under the action of single heavy charged particles and a pulsed voltage are studied experimentally. Using a phenomenological approach, we carry out comparative analysis of physical mechanisms and energy criteria of the SiO2 breakdown in extreme conditions of excitation of the electron subsystem in the subpicosecond time range.

Ionic Liquid Activation of Amorphous Metal-Oxide Semiconductors for Flexible Transparent Electronic Devices

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2016-02-09

To begin this abstract, amorphous metal-oxide semiconductors offer the high carrier mobilities and excellent large-area uniformity required for high performance, transparent, flexible electronic devices; however, a critical bottleneck to their widespread implementation is the need to activate these materials at high temperatures which are not compatible with flexible polymer substrates. The highly controllable activation of amorphous indium gallium zinc oxide semiconductor channels using ionic liquid gating at room temperature is reported. Activation is controlled by electric field-induced oxygen migration across the ionic liquid-semiconductor interface. In addition to activation of unannealed devices, it is shown that threshold voltages of a transistormore » can be linearly tuned between the enhancement and depletion modes. Finally, the first ever example of transparent flexible thin film metal oxide transistor on a polyamide substrate created using this simple technique is demonstrated. Finally, this study demonstrates the potential of field-induced activation as a promising alternative to traditional postdeposition thermal annealing which opens the door to wide scale implementation into flexible electronic applications.« less

Accuracy of dielectric-dependent hybrid functionals in the prediction of optoelectronic properties of metal oxide semiconductors: a comprehensive comparison with many-body GW and experiments

NASA Astrophysics Data System (ADS)

Gerosa, M.; E Bottani, C.; Di Valentin, C.; Onida, G.; Pacchioni, G.

2018-01-01

Understanding the electronic structure of metal oxide semiconductors is crucial to their numerous technological applications, such as photoelectrochemical water splitting and solar cells. The needed experimental and theoretical knowledge goes beyond that of pristine bulk crystals, and must include the effects of surfaces and interfaces, as well as those due to the presence of intrinsic defects (e.g. oxygen vacancies), or dopants for band engineering. In this review, we present an account of the recent efforts in predicting and understanding the optoelectronic properties of oxides using ab initio theoretical methods. In particular, we discuss the performance of recently developed dielectric-dependent hybrid functionals, providing a comparison against the results of many-body GW calculations, including G 0 W 0 as well as more refined approaches, such as quasiparticle self-consistent GW. We summarize results in the recent literature for the band gap, the band level alignment at surfaces, and optical transition energies in defective oxides, including wide gap oxide semiconductors and transition metal oxides. Correlated transition metal oxides are also discussed. For each method, we describe successes and drawbacks, emphasizing the challenges faced by the development of improved theoretical approaches. The theoretical section is preceded by a critical overview of the main experimental techniques needed to characterize the optoelectronic properties of semiconductors, including absorption and reflection spectroscopy, photoemission, and scanning tunneling spectroscopy (STS).

Epitaxial growth of CoO films on semiconductor and metal substrates by constructing a complex heterostructure

NASA Astrophysics Data System (ADS)

Entani, S.; Kiguchi, M.; Saiki, K.; Koma, A.

2003-01-01

Epitaxial growth of CoO films was studied using reflection high-energy electron diffraction (RHEED), electron energy loss spectroscopy (EELS), ultraviolet photoelectron spectroscopy (UPS) and Auger electron spectroscopy (AES). The RHEED results indicated that an epitaxial CoO film grew on semiconductor and metal substrates (CoO (0 0 1)∥GaAs (0 0 1), Cu (0 0 1), Ag (0 0 1) and [1 0 0]CoO∥[1 0 0] substrates) by constructing a complex heterostructure with two alkali halide buffer layers. The AES, EELS and UPS results showed that the grown CoO film had almost the same electronic structure as bulk CoO. We could show that use of alkali halide buffer layers was a good way to grow metal oxide films on semiconductor and metal substrates in an O 2 atmosphere. The alkali halide layers not only works as glue to connect very dissimilar materials but also prevents oxidation of metal and semiconductor substrates.

Area-Selective Atomic Layer Deposition of Metal Oxides on Noble Metals through Catalytic Oxygen Activation

PubMed Central

2017-01-01

Area-selective atomic layer deposition (ALD) is envisioned to play a key role in next-generation semiconductor processing and can also provide new opportunities in the field of catalysis. In this work, we developed an approach for the area-selective deposition of metal oxides on noble metals. Using O2 gas as co-reactant, area-selective ALD has been achieved by relying on the catalytic dissociation of the oxygen molecules on the noble metal surface, while no deposition takes place on inert surfaces that do not dissociate oxygen (i.e., SiO2, Al2O3, Au). The process is demonstrated for selective deposition of iron oxide and nickel oxide on platinum and iridium substrates. Characterization by in situ spectroscopic ellipsometry, transmission electron microscopy, scanning Auger electron spectroscopy, and X-ray photoelectron spectroscopy confirms a very high degree of selectivity, with a constant ALD growth rate on the catalytic metal substrates and no deposition on inert substrates, even after 300 ALD cycles. We demonstrate the area-selective ALD approach on planar and patterned substrates and use it to prepare Pt/Fe2O3 core/shell nanoparticles. Finally, the approach is proposed to be extendable beyond the materials presented here, specifically to other metal oxide ALD processes for which the precursor requires a strong oxidizing agent for growth. PMID:29503508

Selective photon counter for digital x-ray mammography tomosynthesis

NASA Astrophysics Data System (ADS)

Goldan, Amir H.; Karim, Karim S.; Rowlands, J. A.

2006-03-01

Photon counting is an emerging detection technique that is promising for mammography tomosynthesis imagers. In photon counting systems, the value of each image pixel is equal to the number of photons that interact with the detector. In this research, we introduce the design and implementation of a low noise, novel selective photon counting pixel for digital mammography tomosynthesis in crystalline silicon CMOS (complementary metal oxide semiconductor) 0.18 micron technology. The design comprises of a low noise charge amplifier (CA), two low offset voltage comparators, a decision-making unit (DMU), a mode selector, and a pseudo-random counter. Theoretical calculations and simulation results of linearity, gain, and noise of the photon counting pixel are presented.

Fabrication and characterization of spiral interdigitated electrodes based biosensor for salivary glucose detection

NASA Astrophysics Data System (ADS)

Adelyn, P. Y. P.; Hashim, U.; Arshad, M. K. Md; Voon, C. H.; Liu, Wei-Wen; Kahar, S. M.; Huda, A. R. N.; Lee, H. Cheun

2017-03-01

This work introduces the non-invasive glucose monitoring technique by using the Complementary Metal Oxide Semiconductor (CMOS) technologically fabricated spiral Interdigitated Electrodes (IDE) based biosensor. Scanning Electron Microscopy (SEM) image explores the morphology of spiral IDE while Energy Dispersive X-Ray (EDX) determines the elements induced in spiral IDE. Oral saliva of two patients are collected and tested on the spiral IDE sensor with electrical characterization as glucose detection results. However, both patients exhibit their glucose level characteristics inconsistently. Therefore, this work could be extended and enhanced by adding Glutaraldehyde in between 3-Aminoproply)triethoxysilane (APTES) modified and glucose oxidase (GOD) enzyme immobilized layer with FTIR validation for bonding attachment.

PbSe Nanocrystal Solids for n- and p-Channel Thin Film Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Talapin, Dmitri V.; Murray, Christopher B.

2005-10-01

Initially poorly conducting PbSe nanocrystal solids (quantum dot arrays or superlattices) can be chemically ``activated'' to fabricate n- and p-channel field effect transistors with electron and hole mobilities of 0.9 and 0.2 square centimeters per volt-second, respectively; with current modulations of about 103 to 104; and with current density approaching 3 × 104 amperes per square centimeter. Chemical treatments engineer the interparticle spacing, electronic coupling, and doping while passivating electronic traps. These nanocrystal field-effect transistors allow reversible switching between n- and p-transport, providing options for complementary metal oxide semiconductor circuits and enabling a range of low-cost, large-area electronic, optoelectronic, thermoelectric, and sensing applications.

Crosstalk quantification, analysis, and trends in CMOS image sensors.

PubMed

Blockstein, Lior; Yadid-Pecht, Orly

2010-08-20

Pixel crosstalk (CTK) consists of three components, optical CTK (OCTK), electrical CTK (ECTK), and spectral CTK (SCTK). The CTK has been classified into two groups: pixel-architecture dependent and pixel-architecture independent. The pixel-architecture-dependent CTK (PADC) consists of the sum of two CTK components, i.e., the OCTK and the ECTK. This work presents a short summary of a large variety of methods for PADC reduction. Following that, this work suggests a clear quantifiable definition of PADC. Three complementary metal-oxide-semiconductor (CMOS) image sensors based on different technologies were empirically measured, using a unique scanning technology, the S-cube. The PADC is analyzed, and technology trends are shown.

Communication: Time- and space-sliced velocity map electron imaging

NASA Astrophysics Data System (ADS)

Lee, Suk Kyoung; Lin, Yun Fei; Lingenfelter, Steven; Fan, Lin; Winney, Alexander H.; Li, Wen

2014-12-01

We develop a new method to achieve slice electron imaging using a conventional velocity map imaging apparatus with two additional components: a fast frame complementary metal-oxide semiconductor camera and a high-speed digitizer. The setup was previously shown to be capable of 3D detection and coincidence measurements of ions. Here, we show that when this method is applied to electron imaging, a time slice of 32 ps and a spatial slice of less than 1 mm thick can be achieved. Each slice directly extracts 3D velocity distributions of electrons and provides electron velocity distributions that are impossible or difficult to obtain with a standard 2D imaging electron detector.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

Design and Simulations of an Energy Harvesting Capable CMOS Pixel for Implantable Retinal Prosthesis

NASA Astrophysics Data System (ADS)

Ansaripour, Iman; Karami, Mohammad Azim

2017-12-01

A new pixel is designed with the capability of imaging and energy harvesting for the retinal prosthesis implant in 0.18 µm standard Complementary Metal Oxide Semiconductor technology. The pixel conversion gain and dynamic range, are 2.05 \\upmu{{V}}/{{e}}^{ - } and 63.2 dB. The power consumption 53.12 pW per pixel while energy harvesting performance is 3.87 nW in 60 klx of illuminance per pixel. These results have been obtained using post layout simulation. In the proposed pixel structure, the high power production capability in energy harvesting mode covers the demanded energy by using all available p-n junction photo generated currents.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Average output polarization dataset for signifying the temperature influence for QCA designed reversible logic circuits.

PubMed

Abdullah-Al-Shafi, Md; Bahar, Ali Newaz; Bhuiyan, Mohammad Maksudur Rahman; Shamim, S M; Ahmed, Kawser

2018-08-01

Quantum-dot cellular automata (QCA) as nanotechnology is a pledging contestant that has incredible prospective to substitute complementary metal-oxide-semiconductor (CMOS) because of its superior structures such as intensely high device thickness, minimal power depletion with rapid operation momentum. In this study, the dataset of average output polarization (AOP) for fundamental reversible logic circuits is organized as presented in (Abdullah-Al-Shafi and Bahar, 2017; Bahar et al., 2016; Abdullah-Al-Shafi et al., 2015; Abdullah-Al-Shafi, 2016) [1-4]. QCADesigner version 2.0.3 has been utilized to survey the AOP of reversible circuits at separate temperature point in Kelvin (K) unit.

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Physicochemical and Electrophysical Properties of Metal/Semiconductor Containing Nanostructured Composites

NASA Astrophysics Data System (ADS)

Gerasimov, G. N.; Gromov, V. F.; Trakhtenberg, L. I.

2018-06-01

The properties of nanostructured composites based on metal oxides and metal-polymer materials are analyzed, along with ways of preparing them. The effect the interaction between metal and semiconductor nanoparticles has on the conductivity, photoconductivity, catalytic activity, and magnetic, dielectric, and sensor properties of nanocomposites is discussed. It is shown that as a result of this interaction, a material can acquire properties that do not exist in systems of isolated particles. The transfer of electrons between metal particles of different sizes in polymeric matrices leads to specific dielectric losses, and to an increase in the rate and a change in the direction of chemical reactions catalyzed by these particles. The interaction between metal-oxide semiconductor particles results in the electronic and chemical sensitization of sensor effects in nanostructured composite materials. Studies on creating molecular machines (Brownian motors), devices for magnetic recording of information, and high-temperature superconductors based on nanostructured systems are reviewed.

Growth of Bulk Wide Bandgap Semiconductor Crystals and Their Potential Applications

NASA Technical Reports Server (NTRS)

Chen, Kuo-Tong; Shi, Detang; Morgan, S. H.; Collins, W. Eugene; Burger, Arnold

1997-01-01

Developments in bulk crystal growth research for electro-optical devices in the Center for Photonic Materials and Devices since its establishment have been reviewed. Purification processes and single crystal growth systems employing physical vapor transport and Bridgman methods were assembled and used to produce high purity and superior quality wide bandgap materials such as heavy metal halides and II-VI compound semiconductors. Comprehensive material characterization techniques have been employed to reveal the optical, electrical and thermodynamic properties of crystals, and the results were used to establish improved material processing procedures. Postgrowth treatments such as passivation, oxidation, chemical etching and metal contacting during the X-ray and gamma-ray device fabrication process have also been investigated and low noise threshold with improved energy resolution has been achieved.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vais, Abhitosh, E-mail: Abhitosh.Vais@imec.be; Martens, Koen; DeMeyer, Kristin

2015-08-03

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperaturemore » dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.« less

Materials and processing approaches for foundry-compatible transient electronics

PubMed Central

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-01-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries. PMID:28652373

Electrically coupling complex oxides to semiconductors: A route to novel material functionalities

DOE PAGES

Ngai, J. H.; Ahmadi-Majlan, K.; Moghadam, J.; ...

2017-01-12

Complex oxides and semiconductors exhibit distinct yet complementary properties owing to their respective ionic and covalent natures. By electrically coupling complex oxides to traditional semiconductors within epitaxial heterostructures, enhanced or novel functionalities beyond those of the constituent materials can potentially be realized. Essential to electrically coupling complex oxides to semiconductors is control of the physical structure of the epitaxially grown oxide, as well as the electronic structure of the interface. In this paper, we discuss how composition of the perovskite A- and B-site cations can be manipulated to control the physical and electronic structure of semiconductor—complex oxide heterostructures. Two prototypicalmore » heterostructures, Ba 1-xSr xTiO 3/Ge and SrZr xTi 1-xO 3/Ge, will be discussed. In the case of Ba 1-xSr xTiO 3/Ge, we discuss how strain can be engineered through A-site composition to enable the re-orientable ferroelectric polarization of the former to be coupled to carriers in the semiconductor. In the case of SrZr xTi 1-xO 3/Ge we discuss how B-site composition can be exploited to control the band offset at the interface. Finally, analogous to heterojunctions between compound semiconducting materials, control of band offsets, i.e., band-gap engineering, provides a pathway to electrically couple complex oxides to semiconductors to realize a host of functionalities.« less

Electrically coupling complex oxides to semiconductors: A route to novel material functionalities

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ngai, J. H.; Ahmadi-Majlan, K.; Moghadam, J.

Complex oxides and semiconductors exhibit distinct yet complementary properties owing to their respective ionic and covalent natures. By electrically coupling complex oxides to traditional semiconductors within epitaxial heterostructures, enhanced or novel functionalities beyond those of the constituent materials can potentially be realized. Essential to electrically coupling complex oxides to semiconductors is control of the physical structure of the epitaxially grown oxide, as well as the electronic structure of the interface. In this paper, we discuss how composition of the perovskite A- and B-site cations can be manipulated to control the physical and electronic structure of semiconductor—complex oxide heterostructures. Two prototypicalmore » heterostructures, Ba 1-xSr xTiO 3/Ge and SrZr xTi 1-xO 3/Ge, will be discussed. In the case of Ba 1-xSr xTiO 3/Ge, we discuss how strain can be engineered through A-site composition to enable the re-orientable ferroelectric polarization of the former to be coupled to carriers in the semiconductor. In the case of SrZr xTi 1-xO 3/Ge we discuss how B-site composition can be exploited to control the band offset at the interface. Finally, analogous to heterojunctions between compound semiconducting materials, control of band offsets, i.e., band-gap engineering, provides a pathway to electrically couple complex oxides to semiconductors to realize a host of functionalities.« less

Optimal scan strategy for mega-pixel and kilo-gray-level OLED-on-silicon microdisplay.

PubMed

Ji, Yuan; Ran, Feng; Ji, Weigui; Xu, Meihua; Chen, Zhangjing; Jiang, Yuxi; Shen, Weixin

2012-06-10

The digital pixel driving scheme makes the organic light-emitting diode (OLED) microdisplays more immune to the pixel luminance variations and simplifies the circuit architecture and design flow compared to the analog pixel driving scheme. Additionally, it is easily applied in full digital systems. However, the data bottleneck becomes a notable problem as the number of pixels and gray levels grow dramatically. This paper will discuss the digital driving ability to achieve kilogray-levels for megapixel displays. The optimal scan strategy is proposed for creating ultra high gray levels and increasing light efficiency and contrast ratio. Two correction schemes are discussed to improve the gray level linearity. A 1280×1024×3 OLED-on-silicon microdisplay, with 4096 gray levels, is designed based on the optimal scan strategy. The circuit driver is integrated in the silicon backplane chip in the 0.35 μm 3.3 V-6 V dual voltage one polysilicon layer, four metal layers (1P4M) complementary metal-oxide semiconductor (CMOS) process with custom top metal. The design aspects of the optimal scan controller are also discussed. The test results show the gray level linearity of the correction schemes for the optimal scan strategy is acceptable by the human eye.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Thermal Flow Sensors for Harsh Environments.

PubMed

Balakrishnan, Vivekananthan; Phan, Hoang-Phuong; Dinh, Toan; Dao, Dzung Viet; Nguyen, Nam-Trung

2017-09-08

Flow sensing in hostile environments is of increasing interest for applications in the automotive, aerospace, and chemical and resource industries. There are thermal and non-thermal approaches for high-temperature flow measurement. Compared to their non-thermal counterparts, thermal flow sensors have recently attracted a great deal of interest due to the ease of fabrication, lack of moving parts and higher sensitivity. In recent years, various thermal flow sensors have been developed to operate at temperatures above 500 °C. Microelectronic technologies such as silicon-on-insulator (SOI), and complementary metal-oxide semiconductor (CMOS) have been used to make thermal flow sensors. Thermal sensors with various heating and sensing materials such as metals, semiconductors, polymers and ceramics can be selected according to the targeted working temperature. The performance of these thermal flow sensors is evaluated based on parameters such as thermal response time, flow sensitivity. The data from thermal flow sensors reviewed in this paper indicate that the sensing principle is suitable for the operation under harsh environments. Finally, the paper discusses the packaging of the sensor, which is the most important aspect of any high-temperature sensing application. Other than the conventional wire-bonding, various novel packaging techniques have been developed for high-temperature application.