Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

2015-12-01

This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

The c-mos proto-oncogene protein kinase turns on and maintains the activity of MAP kinase, but not MPF, in cell-free extracts of Xenopus oocytes and eggs.

PubMed Central

Nebreda, A R; Hunt, T

1993-01-01

During studies of the activation and inactivation of the cyclin B-p34cdc2 protein kinase (MPF) in cell-free extracts of Xenopus oocytes and eggs, we found that a bacterially expressed fusion protein between the Escherichia coli maltose-binding protein and the Xenopus c-mos protein kinase (malE-mos) activated a 42 kDa MAP kinase. The activation of MAP kinase on addition of malE-mos was consistent, whereas the activation of MPF was variable and failed to occur in some oocyte extracts in which cyclin A or okadaic acid activated both MPF and MAP kinase. In cases when MPF activation was transient, MAP kinase activity declined after MPF activity was lost, and MAP kinase, but not MPF, could be maintained at a high level by the presence of malE-mos. When intact oocytes were treated with progesterone, however, the activation of MPF and MAP kinase occurred simultaneously, in contrast to the behaviour of extracts. These observations suggest that one role of c-mos may be to maintain high MAP kinase activity in meiosis. They also imply that the activation of MPF and MAP kinase in vivo are synchronous events that normally rely on an agent that has still to be identified. Images PMID:8387916

MoS2/Ni3S4 composite nanosheets on interconnected carbon shells as an excellent supercapacitor electrode architecture for long term cycling at high current densities

NASA Astrophysics Data System (ADS)

Qin, Shengchun; Yao, Tinghui; Guo, Xin; Chen, Qiang; Liu, Dequan; Liu, Qiming; Li, Yali; Li, Junshuai; He, Deyan

2018-05-01

In this paper, we report an electrode architecture of molybdenum disulfide (MoS2)/nickel sulfide (Ni3S4) composite nanosheets anchored on interconnected carbon (C) shells (C@MoS2/Ni3S4). Electrochemical measurements indicate that the C@MoS2/Ni3S4 structure possesses excellent supercapacitive properties especially for long term cycling at high current densities. A specific capacitance as high as ∼640.7 F g-1 can still be delivered even after 10,000 cycles at a high current density of 20 A g-1. From comparison of microstructures and electrochemical properties of the related materials/structures, the improved performance of C@MoS2/Ni3S4 can be attributed to the relatively dispersedly distributed nanosheet-shaped MoS2/Ni3S4 that provides efficient contact with electrolyte and effectively buffers the volume change during charge/discharge processes, enhanced cycling stability by MoS2, and reduced equivalent series resistance by the interconnected C shells.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Investigation of noise insensitive electronic circuits for automotive applications with particular regard to MOS circuits

NASA Astrophysics Data System (ADS)

Gorille, I.

1980-11-01

The application of MOS switching circuits of high complexity in essential automobile systems, such as ignition and injection, was investigated. A bipolar circuit technology, current hogging logic (CHL), was compared to MOS technologies for its competitiveness. The functional requirements of digital automotive systems can only be met by technologies allowing large packing densities and medium speeds. The properties of n-MOS and CMOS are promising whereas the electrical power needed by p-MOS circuits is in general prohibitively large.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Precision Voltage Referencing Techniques in MOS Technology.

NASA Astrophysics Data System (ADS)

Song, Bang-Sup

With the increasing complexity of functions on a single MOS chip, precision analog cicuits implemented in the same technology are in great demand so as to be integrated together with digital circuits. The future development of MOS data acquisition systems will require precision on-chip MOS voltage references. This dissertation will probe two most promising configurations of on-chip voltage references both in NMOS and CMOS technologies. In NMOS, an ion-implantation effect on the temperature behavior of MOS devices is investigated to identify the fundamental limiting factors of a threshold voltage difference as an NMOS voltage source. For this kind of voltage reference, the temperature stability on the order of 20ppm/(DEGREES)C is achievable with a shallow single-threshold implant and a low-current, high-body bias operation. In CMOS, a monolithic prototype bandgap reference is designed, fabricated and tested which embodies a curvature compensation and exhibits a minimized sensitivity to the process parameter variation. Experimental results imply that an average temperature stability on the order of 10ppm/(DEGREES)C with a production spread of less than 10ppm/(DEGREES)C feasible over the commercial temperature range.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Involvement of Mos-MEK-MAPK pathway in cytostatic factor (CSF) arrest in eggs of the parthenogenetic insect, Athalia rosae.

PubMed

Yamamoto, Daisuke S; Tachibana, Kazunori; Sumitani, Megumi; Lee, Jae Min; Hatakeyama, Masatsugu

2008-01-01

Extensive survey of meiotic metaphase II arrest during oocyte maturation in vertebrates revealed that the mitogen-activated protein kinase (MAPK) pathway regulated by the c-mos proto-oncogene product, Mos, has an essential role in cytostatic activity, termed cytostatic factor (CSF). In contrast, little is known in invertebrates in which meiotic arrest occurs in most cases at metaphase I (MI arrest). A parthenogenetic insect, the sawfly Athalia rosae, in which artificial egg activation is practicable, has advantages to investigate the mechanisms of MI arrest. Both the MAPK/extracellular signal-regulated protein kinase kinase (MEK) and MAPK were phosphorylated and maintained active in MI-arrested sawfly eggs, whereas they were dephosphorylated soon after egg activation. Treatment of MI-arrested eggs with U0126, an inhibitor of MEK, resulted in dephosphorylation of MAPK and MI arrest was resumed. The sawfly c-mos gene orthologue encoding a serine/threonine kinase was cloned and analyzed. It was expressed in nurse cells in the ovaries. To examine CSF activity of the sawfly Mos, synthesized glutathione S-transferase (GST)-fusion sawfly Mos protein was injected into MI-resumed eggs in which MEK and MAPK were dephosphorylated. Both MEK and MAPK were phosphorylated again upon injection. In these GST-fusion sawfly Mos-injected eggs subsequent mitotic (syncytial) divisions were blocked and embryonic development was ceased. These results demonstrated that the MEK-MAPK pathway was involved in maintaining CSF arrest in sawfly eggs and Mos functioned as its upstream regulatory molecule.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

A study of charged particles/radiation damage to VLSI device materials

NASA Technical Reports Server (NTRS)

Okyere, John G.

1987-01-01

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Interferometry-based free space communication and information processing

NASA Astrophysics Data System (ADS)

Arain, Muzammil Arshad

This dissertation studies, analyzes, and experimentally demonstrates the innovative use of interference phenomenon in the field of opto-electronic information processing and optical communications. A number of optical systems using interferometric techniques both in the optical and the electronic domains has been demonstrated in the filed of signal transmission and processing, optical metrology, defense, and physical sensors. Specifically it has been shown that the interference of waves in the form of holography can be exploited to realize a novel optical scanner called Code Multiplexed Optical Scanner (C-MOS). The C-MOS features large aperture, wide scan angles, 3-D beam control, no moving parts, and high beam scanning resolution. A C-MOS based free space optical transceiver for bi-directional communication has also been experimentally demonstrated. For high speed, large bandwidth, and high frequency operation, an optically implemented reconfigurable RF transversal filter design is presented that implements wide range of filtering algorithms. A number of techniques using heterodyne interferometry via acousto-optic device for optical path length measurements have been described. Finally, a whole new class of interferometric sensors for optical metrology and sensing applications is presented. A non-traditional interferometric output signal processing scheme has been developed. Applications include, for example, temperature sensors for harsh environments for a wide temperature range from room temperature to 1000°C.

Giant Gating Tunability of Optical Refractive Index in Transition Metal Dichalcogenide Monolayers.

PubMed

Yu, Yiling; Yu, Yifei; Huang, Lujun; Peng, Haowei; Xiong, Liwei; Cao, Linyou

2017-06-14

We report that the refractive index of transition metal dichacolgenide (TMDC) monolayers, such as MoS 2 , WS 2 , and WSe 2 , can be substantially tuned by >60% in the imaginary part and >20% in the real part around exciton resonances using complementary metal-oxide-semiconductor (CMOS) compatible electrical gating. This giant tunablility is rooted in the dominance of excitonic effects in the refractive index of the monolayers and the strong susceptibility of the excitons to the influence of injected charge carriers. The tunability mainly results from the effects of injected charge carriers to broaden the spectral width of excitonic interband transitions and to facilitate the interconversion of neutral and charged excitons. The other effects of the injected charge carriers, such as renormalizing bandgap and changing exciton binding energy, only play negligible roles. We also demonstrate that the atomically thin monolayers, when combined with photonic structures, can enable the efficiencies of optical absorption (reflection) tuned from 40% (60%) to 80% (20%) due to the giant tunability of the refractive index. This work may pave the way toward the development of field-effect photonics in which the optical functionality can be controlled with CMOS circuits.

Integrated 3D porous C-MoS2/nitrogen-doped graphene electrode for high capacity and prolonged stability lithium storage

NASA Astrophysics Data System (ADS)

Xie, D.; Tang, W. J.; Xia, X. H.; Wang, D. H.; Zhou, D.; Shi, F.; Wang, X. L.; Gu, C. D.; Tu, J. P.

2015-11-01

Scrupulous design and fabrication of advanced anode materials are of great importance for developing high-performance lithium ion batteries. Herein, we report a facile strategy for construction of free-standing and free-binder 3D porous carbon coated MoS2/nitrogen-doped graphene (C-MoS2/N-G) integrated electrode via a hydrothermal-induced self-assembly process. The preformed carbon coated MoS2 is strongly anchored on the porous nitrogen-doped graphene aerogel architecture. As an anode for lithium ion batteries, the C-MoS2/N-G electrode delivers a high first discharge capacity of 1600 mAh g-1 and maintains 900 mAh g-1 after 500 cycles at a current density of 200 mA g-1. Impressively, superior high-rate capability is achieved for the C-MoS2/N-G with a reversible capacity of 500 mAh g-1 at a high current density of 4000 mA g-1. Furthermore, the lithium storage mechanism of the obtained integrated electrode is investigated by ex-situ X-ray photoelectron spectroscopy and transmission electron microscopy in detail.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology

DTIC Science & Technology

2006-06-01

controlled oscillators. Varactor , transistor, and in- ductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between...quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 m result both good...millimeter wave, MOS varactor , quality factor, transmission line, voltage-controlled oscillator (VCO). I. INTRODUCTION WITH THE RAPID advance of high

An ultra-low-voltage electronic implementation of inertial neuron model with nonmonotonous Liao's activation function.

PubMed

Kant, Nasir Ali; Dar, Mohamad Rafiq; Khanday, Farooq Ahmad

2015-01-01

The output of every neuron in neural network is specified by the employed activation function (AF) and therefore forms the heart of neural networks. As far as the design of artificial neural networks (ANNs) is concerned, hardware approach is preferred over software one because it promises the full utilization of the application potential of ANNs. Therefore, besides some arithmetic blocks, designing AF in hardware is the most important for designing ANN. While attempting to design the AF in hardware, the designs should be compatible with the modern Very Large Scale Integration (VLSI) design techniques. In this regard, the implemented designs should: only be in Metal Oxide Semiconductor (MOS) technology in order to be compatible with the digital designs, provide electronic tunability feature, and be able to operate at ultra-low voltage. Companding is one of the promising circuit design techniques for achieving these goals. In this paper, 0.5 V design of Liao's AF using sinh-domain technique is introduced. Furthermore, the function is tested by implementing inertial neuron model. The performance of the AF and inertial neuron model have been evaluated through simulation results, using the PSPICE software with the MOS transistor models provided by the 0.18-μm Taiwan Semiconductor Manufacturer Complementary Metal Oxide Semiconductor (TSM CMOS) process.

Charge-Transfer-Induced p-Type Channel in MoS2 Flake Field Effect Transistors.

PubMed

Min, Sung-Wook; Yoon, Minho; Yang, Sung Jin; Ko, Kyeong Rok; Im, Seongil

2018-01-31

The two-dimensional transition-metal dichalcogenide semiconductor MoS 2 has received extensive attention for decades because of its outstanding electrical and mechanical properties for next-generation devices. One weakness of MoS 2 , however, is that it shows only n-type conduction, revealing its limitations for homogeneous PN diodes and complementary inverters. Here, we introduce a charge-transfer method to modify the conduction property of MoS 2 from n- to p-type. We initially deposited an n-type InGaZnO (IGZO) film on top of the MoS 2 flake so that electron charges might be transferred from MoS 2 to IGZO during air ambient annealing. As a result, electron charges were depleted in MoS 2 . Such charge depletion lowered the MoS 2 Fermi level, which makes hole conduction favorable in MoS 2 when optimum source/drain electrodes with a high work function are selected. Our IGZO-supported MoS 2 flake field effect transistors (FETs) clearly display channel-type conversion from n- to p-channel in this way. Under short- and long-annealing conditions, n- and p-channel MoS 2 FETs are achieved, respectively, and a low-voltage complementary inverter is demonstrated using both channels in a single MoS 2 flake.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, James D.

1997-01-01

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controled switching and effecting a direction of rectification.

Schottky barrier MOSFET systems and fabrication thereof

DOEpatents

Welch, J.D.

1997-09-02

(MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controlled switching and effecting a direction of rectification. 89 figs.

A Coherent VLSI Design Environment.

DTIC Science & Technology

1986-03-31

Schema were a CMOS sorter and a TTL PC board for gathering statistics from a Multibus. Neither design was completed using Schema, but at least in the...technique for automatically adjusting signal delays in an MOS system has been developed. The Dynamic Delay Adjustment (DDA) technique provides...34Synchronization Reliability in CMOS Technology," IEEE J. of Solid - State Circuits, Vol. SC-20, No. 4, pp. 880-883, 1985. * [8] J. Hohl, W. Larsen and L. Schooley

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Electrical properties of HfO2 high- k thin-film MOS capacitors for advanced CMOS technology

NASA Astrophysics Data System (ADS)

Khairnar, A. G.; Patil, L. S.; Salunke, R. S.; Mahajan, A. M.

2015-11-01

We deposited the hafnium dioxide (HfO2) thin films on p-Si (100) substrates. The thin films were deposited with deposition time variations, viz 2, 4, 7 and 20 min using RF-sputtering technique. The thickness and refractive index of the films were measured using spectroscopic ellipsometer. The thicknesses of the films were measured to be 13.7, 21.9, 35.38 and 92.2 nm and refractive indices of 1.90, 1.93, 1.99 and 1.99, respectively, of the films deposited for 2, 4, 7 and 20 min deposition time. The crystal structures of the deposited HfO2 thin films were determined using XRD spectra and showed the monoclinic structure, confirmed with the ICDD card no 34-0104. Aluminum metallization was carried to form the Al/HfO2/ p-Si MOS structures by using thermal evaporation system with electrode area of 12.56 × 10-4 cm2. Capacitance voltage and current voltage measurements were taken to know electrical behavior of these fabricated MOS structures. The electrical parameters such as dielectric constant, flat-band shift and interface trap density determined through CV measurement were 7.99, 0.11 V and 6.94 × 1011 eV-1 cm-2, respectively. The low leakage current density was obtained from IV measurement of fabricated MOS structure at 1.5 V is 4.85 × 10-10 Acm-2. Aforesaid properties explored the suitability of the fabricated HfO2 high- k-based MOS capacitors for advanced CMOS technology.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

Radiation Effects on the Electrical Properties of MOS Device Materials.

DTIC Science & Technology

1978-02-01

3 Under Contract e ~i8 DAAG39~~ C.0O88 tJTtj~ J b This work _ sponsored by di. Ds~nse Nuclear Aisocy undur Nuclear ~ ffiupons Effucta flussarch...numb •r) Si02, MOS , CMOS Vacuum Ultraviolet Radiation Radiation Hardness Interfac e States Capture Cross Sections 2 ’ ~~’*~~ TRACT (Continu e on...When 0 t e Entered ) Results show that unannealed dry oxides have the lowest interface— state density after irrad iation, making them more desirable

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

NASA Astrophysics Data System (ADS)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Low-power low-voltage superior-order curvature corrected voltage reference

NASA Astrophysics Data System (ADS)

Popa, Cosmin

2010-06-01

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The heterogeneous integration of single-walled carbon nanotubes onto complementary metal oxide semiconductor circuitry for sensing applications.

PubMed

Chen, Chia-Ling; Agarwal, Vinay; Sonkusale, Sameer; Dokmeci, Mehmet R

2009-06-03

A simple methodology for integrating single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry is presented. The SWNTs were incorporated onto the CMOS chip as the feedback resistor of a two-stage Miller compensated operational amplifier utilizing dielectrophoretic assembly. The measured electrical properties from the integrated SWNTs yield ohmic behavior with a two-terminal resistance of approximately 37.5 kOmega and the measured small signal ac gain (-2) from the inverting amplifier confirmed successful integration of carbon nanotubes onto the CMOS circuitry. Furthermore, the temperature response of the SWNTs integrated onto CMOS circuitry has been measured and had a thermal coefficient of resistance (TCR) of -0.4% degrees C(-1). This methodology, demonstrated for the integration of SWNTs onto CMOS technology, is versatile, high yield and paves the way for the realization of novel miniature carbon-nanotube-based sensor systems.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Single-poly EEPROM cell with lightly doped MOS capacitors

DOEpatents

Riekels, James E [New Hope, MN; Lucking, Thomas B [Maple Grove, MN; Larsen, Bradley J [Mound, MN; Gardner, Gary R [Golden Valley, MN

2008-05-27

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

DTIC Science & Technology

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

PubMed

Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

2016-06-01

Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Creation of a Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2010-08-01

To support space applications we will develop an 0.13 micron CMOS library which should be radiation hard up to 200 krad. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latchup (SEL). To reduce single event upset (SEU) we will add two p-MOS transistors to all flip flops. For reliability reasons we will use double contacts in all library elements. The additional rules and the library elements will then be integrated in our Cadence mixed signal designkit, Virtuoso IC6.1 [1]. A test chip will be produced with our in house 0.13 micron BiCMOS technology, see Ref. [2].Thereafter we will doing radiation tests according the ESA specifications, see Ref. [3], [4].

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Encapsulation of Mo2C in MoS2 inorganic fullerene-like nanoparticles and nanotubes

NASA Astrophysics Data System (ADS)

Wiesel, Inna; Popovitz-Biro, Ronit; Tenne, Reshef

2013-01-01

Mo2C nanoparticles encapsulated within MoS2 inorganic fullerene-like nanoparticles and nanotubes were produced by carbothermal reaction at 1200-1300 °C inside a vertical induction furnace. The particles were analyzed using various electron microscopy techniques and complementary methods.

Organic-on-silicon complementary metal-oxide-semiconductor colour image sensors.

PubMed

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-12

Complementary metal-oxide-semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor.

Organic-on-silicon complementary metal–oxide–semiconductor colour image sensors

PubMed Central

Lim, Seon-Jeong; Leem, Dong-Seok; Park, Kyung-Bae; Kim, Kyu-Sik; Sul, Sangchul; Na, Kyoungwon; Lee, Gae Hwang; Heo, Chul-Joon; Lee, Kwang-Hee; Bulliard, Xavier; Satoh, Ryu-Ichi; Yagi, Tadao; Ro, Takkyun; Im, Dongmo; Jung, Jungkyu; Lee, Myungwon; Lee, Tae-Yon; Han, Moon Gyu; Jin, Yong Wan; Lee, Sangyoon

2015-01-01

Complementary metal–oxide–semiconductor (CMOS) colour image sensors are representative examples of light-detection devices. To achieve extremely high resolutions, the pixel sizes of the CMOS image sensors must be reduced to less than a micron, which in turn significantly limits the number of photons that can be captured by each pixel using silicon (Si)-based technology (i.e., this reduction in pixel size results in a loss of sensitivity). Here, we demonstrate a novel and efficient method of increasing the sensitivity and resolution of the CMOS image sensors by superposing an organic photodiode (OPD) onto a CMOS circuit with Si photodiodes, which consequently doubles the light-input surface area of each pixel. To realise this concept, we developed organic semiconductor materials with absorption properties selective to green light and successfully fabricated highly efficient green-light-sensitive OPDs without colour filters. We found that such a top light-receiving OPD, which is selective to specific green wavelengths, demonstrates great potential when combined with a newly designed Si-based CMOS circuit containing only blue and red colour filters. To demonstrate the effectiveness of this state-of-the-art hybrid colour image sensor, we acquired a real full-colour image using a camera that contained the organic-on-Si hybrid CMOS colour image sensor. PMID:25578322

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

The damage equivalence of electrons, protons, and gamma rays in MOS devices

NASA Technical Reports Server (NTRS)

Brucker, G. J.; Stassinopoulos, E. G.; Van Gunten, O.; August, L. S.; Jordan, T. M.

1982-01-01

The results of laboratory tests to determine the radiation damage effects induced on MOS devices from Co-60, electron, and proton radiation are reported. The tests are performed to establish the relationship between the Co-60 gamma rays and the level of damage to the MOS devices in regards to different damages which can be expected with the electron and particle bombardments experienced in space applications. CMOS devices were exposed to the Co-60 gamma rays, 1 MeV electrons, and 1 MeV protons while operating at 3, 10, and 15 V. The test data indicated that the Co-60 source was reliable for an initial evaluation of the electron damages up to 2 MeV charge. A correction factor was devised for transferring the Co-60 measurements to proton damages, independent of bias and transistor types, for any orbit or environment.

CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

NASA Technical Reports Server (NTRS)

Fossum, Eric R.

1996-01-01

The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2013-08-01

To support space applications we have developed an 0.13 micron CMOS library which should be radiation hard up to 200 krad. The article describes the concept to come to a radiation hard digital circuit and was introduces in 2010 [1]. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latch-up (SEL). To reduce single event upset (SEU) we add two p-MOS transistors to all flip flops. For reliability reasons we use double contacts in all library elements. The additional rules and the library elements are integrated in our Cadence mixed signal design kit, “Virtuoso” IC6.1 [2]. A test chip is produced with our in house 0.13 micron BiCMOS technology, see Ref. [3]. As next step we will doing radiation tests according the european space agency (ESA) specifications, see Ref. [4], [5].

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

Ultralow-power complementary metal-oxide-semiconductor inverters constructed on Schottky barrier modified nanowire metal-oxide-semiconductor field-effect-transistors.

PubMed

Ma, R M; Peng, R M; Wen, X N; Dai, L; Liu, C; Sun, T; Xu, W J; Qin, G G

2010-10-01

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

TiO2-Based Indium Phosphide Metal-Oxide-Semiconductor Capacitor with High Capacitance Density.

PubMed

Cheng, Chun-Hu; Hsu, Hsiao-Hsuan; Chou, Kun-i

2015-04-01

We report a low-temperature InP p-MOS with a high capacitance density of 2.7 µF/cm2, low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.

Versatile synthesis and rational design of caged morpholinos.

PubMed

Ouyang, Xiaohu; Shestopalov, Ilya A; Sinha, Surajit; Zheng, Genhua; Pitt, Cameron L W; Li, Wen-Hong; Olson, Andrew J; Chen, James K

2009-09-23

Embryogenesis is regulated by genetic programs that are dynamically executed in a stereotypic manner, and deciphering these molecular mechanisms requires the ability to control embryonic gene function with similar spatial and temporal precision. Chemical technologies can enable such genetic manipulations, as exemplified by the use of caged morpholino (cMO) oligonucleotides to inactivate genes in zebrafish and other optically transparent organisms with spatiotemporal control. Here we report optimized methods for the design and synthesis of hairpin cMOs incorporating a dimethoxynitrobenzyl (DMNB)-based bifunctional linker that permits cMO assembly in only three steps from commercially available reagents. Using this simplified procedure, we have systematically prepared cMOs with differing structural configurations and investigated how the in vitro thermodynamic properties of these reagents correlate with their in vivo activities. Through these studies, we have established general principles for cMO design and successfully applied them to several developmental genes. Our optimized synthetic and design methodologies have also enabled us to prepare a next-generation cMO that contains a bromohydroxyquinoline (BHQ)-based linker for two-photon uncaging. Collectively, these advances establish the generality of cMO technologies and will facilitate the application of these chemical probes in vivo for functional genomic studies.

Versatile Synthesis and Rational Design of Caged Morpholinos

PubMed Central

2009-01-01

Embryogenesis is regulated by genetic programs that are dynamically executed in a stereotypic manner, and deciphering these molecular mechanisms requires the ability to control embryonic gene function with similar spatial and temporal precision. Chemical technologies can enable such genetic manipulations, as exemplified by the use of caged morpholino (cMO) oligonucleotides to inactivate genes in zebrafish and other optically transparent organisms with spatiotemporal control. Here we report optimized methods for the design and synthesis of hairpin cMOs incorporating a dimethoxynitrobenzyl (DMNB)-based bifunctional linker that permits cMO assembly in only three steps from commercially available reagents. Using this simplified procedure, we have systematically prepared cMOs with differing structural configurations and investigated how the in vitro thermodynamic properties of these reagents correlate with their in vivo activities. Through these studies, we have established general principles for cMO design and successfully applied them to several developmental genes. Our optimized synthetic and design methodologies have also enabled us to prepare a next-generation cMO that contains a bromohydroxyquinoline (BHQ)-based linker for two-photon uncaging. Collectively, these advances establish the generality of cMO technologies and will facilitate the application of these chemical probes in vivo for functional genomic studies. PMID:19708646

Design automation techniques for custom LSI arrays

NASA Technical Reports Server (NTRS)

Feller, A.

1975-01-01

The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

NASA Technical Reports Server (NTRS)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Polarization-dependent optical absorption of MoS₂ for refractive index sensing.

PubMed

Tan, Yang; He, Ruiyun; Cheng, Chen; Wang, Dong; Chen, Yanxue; Chen, Feng

2014-12-17

As a noncentrosymmetric crystal with spin-polarized band structure, MoS2 nanomaterials have attracts increasing attention in many areas such as lithium ion batteries, flexible electronic devices, photoluminescence and valleytronics. The investigation of MoS2 is mainly focused on the electronics and spintronics instead of optics, which restrict its applications as key elements of photonics. In this work, we demonstrate the first observation of the polarization-dependent optical absorption of the MoS2 thin film, which is integrated onto an optical waveguide device. With this feature, a novel optical sensor combining MoS2 thin-film and a microfluidic structure has been constituted to achieve the sensitive monitoring of refractive index. Our work indicates the MoS2 thin film as a complementary material to graphene for the optical polarizer in the visible light range, and explores a new application direction of MoS2 nanomaterials for the construction of photonic circuits.

Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

PubMed

Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

2017-10-02

Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

PubMed

Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

2017-04-12

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10 6 , effective mobility up to 30 cm 2 V -1 s -1 , small hysteresis, and small subthreshold swing (90-140 mV dec -1 ), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V dd = 1 V) and a voltage gain as high as 30 (at V dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Polarization-dependent optical absorption of MoS2 for refractive index sensing

PubMed Central

Tan, Yang; He, Ruiyun; Cheng, Chen; Wang, Dong; Chen, Yanxue; Chen, Feng

2014-01-01

As a noncentrosymmetric crystal with spin-polarized band structure, MoS2 nanomaterials have attracts increasing attention in many areas such as lithium ion batteries, flexible electronic devices, photoluminescence and valleytronics. The investigation of MoS2 is mainly focused on the electronics and spintronics instead of optics, which restrict its applications as key elements of photonics. In this work, we demonstrate the first observation of the polarization-dependent optical absorption of the MoS2 thin film, which is integrated onto an optical waveguide device. With this feature, a novel optical sensor combining MoS2 thin-film and a microfluidic structure has been constituted to achieve the sensitive monitoring of refractive index. Our work indicates the MoS2 thin film as a complementary material to graphene for the optical polarizer in the visible light range, and explores a new application direction of MoS2 nanomaterials for the construction of photonic circuits. PMID:25516116

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

PubMed

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Upper-Bound Estimates Of SEU in CMOS

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

1990-01-01

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network

NASA Astrophysics Data System (ADS)

Cohen, Marc H.; Andreou, Andreas G.

1992-05-01

The translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing are investigated. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2-microns n-well double-polysilicon, double-metal CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The design methodology and constraints as well as test results from the fabricated chips are discussed.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Prediction and measurement results of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Stassinopoulos, E. G.; Danchenko, V.; Cliff, R. A.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1977-01-01

Final results from the CMOS Radiation Effects Measurement (CREM) experiment flown on Explorer 55 are presented and discussed, based on about 15 months of observations and measurements. Conclusions are given relating to long-range annealing, effects of operating temperature on semiconductor performance in space, biased and unbiased P-MOS device degradation, unbiased n-channel device performance, changes in device transconductance, and the difference in ionization efficiency between Co-60 gamma rays and 1-Mev Van de Graaff electrons. The performance of devices in a heavily shielded electronic subsystem box within the spacecraft is evaluated and compared. Environment models and computational methods and their impact on device-degradation estimates are being reviewed to determine whether they permit cost-effective design of spacecraft.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

PubMed Central

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices. PMID:22163968

New analysis and design of a RF rectifier for RFID and implantable devices.

PubMed

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from -15 dBm to -4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitable to passive UHF RFID tag IC and implantable devices.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

Wobbly strings: calculating the capture rate of a webcam using the rolling shutter effect in a guitar

NASA Astrophysics Data System (ADS)

Cunnah, David

2014-07-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Wobbly Strings: Calculating the Capture Rate of a Webcam Using the Rolling Shutter Effect in a Guitar

ERIC Educational Resources Information Center

Cunnah, David

2014-01-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Lead sulfide - Silicon MOSFET infrared focal plane development

NASA Technical Reports Server (NTRS)

Barrett, J. R.; Jhabvala, M. D.

1983-01-01

A process for directly integrating photoconductive lead sulfide (PbS) infrared detector material with silicon MOS integrated circuits has been developed primarily for application in long (greater than 10,000 detector elements) linear arrays for pushbroom scanning applications. The processing technology is based on the conventional PMOS and CMOS technologies with a variation in the metallization. Results and measurements on a fully integrated eight-element multiplexer are shown.

C-MOS bulk metal design handbook. [LSI standard cell (circuits)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Ultrasensitive and label-free detection of pathogenic avian influenza DNA by using CMOS impedimetric sensors.

PubMed

Lai, Wei-An; Lin, Chih-Heng; Yang, Yuh-Shyong; Lu, Michael S-C

2012-05-15

This work presents miniaturized CMOS (complementary metal oxide semiconductor) sensors for non-faradic impedimetric detection of AIV (avian influenza virus) oligonucleotides. The signal-to-noise ratio is significantly improved by monolithic sensor integration to reduce the effect of parasitic capacitances. The use of sub-μm interdigitated microelectrodes is also beneficial for promoting the signal coupling efficiency. Capacitance changes associated with surface modification, functionalization, and DNA hybridization were extracted from the measured frequency responses based on an equivalent-circuit model. Hybridization of the AIV H5 capture and target DNA probes produced a capacitance reduction of -13.2 ± 2.1% for target DNA concentrations from 1 fM to 10 fM, while a capacitance increase was observed when H5 target DNA was replaced with non-complementary H7 target DNA. With the demonstrated superior sensing capabilities, this miniaturized CMOS sensing platform shows great potential for label-free point-of-care biosensing applications. Copyright © 2012 Elsevier B.V. All rights reserved.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

MIT Laboratory for Computer Science Progress Report 20 - July 1982 - Jun 1983,

DTIC Science & Technology

1984-07-01

system by the Programming Technology Group. Research in the second and largest area entitled Machines, Languages , and Systems, strives to discover and...utilization and cost effectiveness . For example, the Programming Methodology Group and the Real Time Systems Group are developing languages and...100 Megabits per second when implemented with the 1.2[im. n- well cMOS process. 3. LANGUAGES 3.1. Demand Driven Evaluation In his engineer’s thesis

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

CMOS Cell Sensors for Point-of-Care Diagnostics

PubMed Central

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS cell sensors for point-of-care diagnostics.

PubMed

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

CMOS Camera Array With Onboard Memory

NASA Technical Reports Server (NTRS)

Gat, Nahum

2009-01-01

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

PubMed

Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig

2018-02-05

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

New Energy-Dependent Soft X-Rav Damage In MOS Devices

NASA Astrophysics Data System (ADS)

Chan, Tung-Yi; Gaw, Henry; Seligson, Daniel; Pan, Lawrence; King, Paul L.; Pianetta, Piero

1988-06-01

An energy-dependent soft x-ray-induced device damage has been discovered in MOS devices fabricated using standard CMOS process. MOS devices were irradiated by monochromatic x-rays in energy range just above and below the silicon K-edge (1.84 keV). Photons below the K-edge is found to create more damage in the oxide and oxide/silicon interface than photons above the K-edge. This energy-dependent damage effect is believed to be due to charge traps generated during device fabrication. It is found that data for both n- and p-type devices lie along a universal curve if normalized threshold voltage shifts are plotted against absorbed dose in the oxide. The threshold voltage shift saturates when the absorbed dose in the oxide exceeds 1.4X105 mJ/cm3, corresponding to 6 Mrad in the oxide. Using isochronal anneals, the trapped charge damage is found to recover with an activation energy of 0.38 eV. A discrete radiation-induced damage state appears in the low frequency C-V curve in a temperature range from 1750C to 325°C.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Update on parts SEE suspectibility from heavy ions. [Single Event Effects

NASA Technical Reports Server (NTRS)

Nichols, D. K.; Smith, L. S.; Schwartz, H. R.; Soli, G.; Watson, K.; Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.

1991-01-01

JPL and the Aerospace Corporation have collected a fourth set of heavy ion single event effects (SEE) test data. Trends in SEE susceptibility (including soft errors and latchup) for state-of-the-art parts are displayed. All data are conveniently divided into two tables: one for MOS devices, and one for a shorter list of recently tested bipolar devices. In addition, a new table of data for latchup tests only (invariably CMOS processes) is given.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays.

PubMed

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-11-07

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Laser line scan underwater imaging by complementary metal-oxide-semiconductor camera

NASA Astrophysics Data System (ADS)

He, Zhiyi; Luo, Meixing; Song, Xiyu; Wang, Dundong; He, Ning

2017-12-01

This work employs the complementary metal-oxide-semiconductor (CMOS) camera to acquire images in a scanning manner for laser line scan (LLS) underwater imaging to alleviate backscatter impact of seawater. Two operating features of the CMOS camera, namely the region of interest (ROI) and rolling shutter, can be utilized to perform image scan without the difficulty of translating the receiver above the target as the traditional LLS imaging systems have. By the dynamically reconfigurable ROI of an industrial CMOS camera, we evenly divided the image into five subareas along the pixel rows and then scanned them by changing the ROI region automatically under the synchronous illumination by the fun beams of the lasers. Another scanning method was explored by the rolling shutter operation of the CMOS camera. The fun beam lasers were turned on/off to illuminate the narrow zones on the target in a good correspondence to the exposure lines during the rolling procedure of the camera's electronic shutter. The frame synchronization between the image scan and the laser beam sweep may be achieved by either the strobe lighting output pulse or the external triggering pulse of the industrial camera. Comparison between the scanning and nonscanning images shows that contrast of the underwater image can be improved by our LLS imaging techniques, with higher stability and feasibility than the mechanically controlled scanning method.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

CMOS image sensor-based immunodetection by refractive-index change.

PubMed

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

CMOS image sensors as an efficient platform for glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-07

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

PubMed

Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

2015-08-01

This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

Video-rate nanoscopy enabled by sCMOS camera-specific single-molecule localization algorithms

PubMed Central

Huang, Fang; Hartwich, Tobias M. P.; Rivera-Molina, Felix E.; Lin, Yu; Duim, Whitney C.; Long, Jane J.; Uchil, Pradeep D.; Myers, Jordan R.; Baird, Michelle A.; Mothes, Walther; Davidson, Michael W.; Toomre, Derek; Bewersdorf, Joerg

2013-01-01

Newly developed scientific complementary metal–oxide–semiconductor (sCMOS) cameras have the potential to dramatically accelerate data acquisition in single-molecule switching nanoscopy (SMSN) while simultaneously increasing the effective quantum efficiency. However, sCMOS-intrinsic pixel-dependent readout noise substantially reduces the localization precision and introduces localization artifacts. Here we present algorithms that overcome these limitations and provide unbiased, precise localization of single molecules at the theoretical limit. In combination with a multi-emitter fitting algorithm, we demonstrate single-molecule localization super-resolution imaging at up to 32 reconstructed images/second (recorded at 1,600–3,200 camera frames/second) in both fixed and living cells. PMID:23708387

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

Bandwidth tunable amplifier for recording biopotential signals.

PubMed

Hwang, Sungkil; Aninakwa, Kofi; Sonkusale, Sameer

2010-01-01

This paper presents a low noise, low power, bandwidth tunable amplifier for bio-potential signal recording applications. By employing depletion-mode pMOS transistor in diode configuration as a tunable sub pA current source to adjust the resistivity of MOS-Bipolar pseudo-resistor, the bandwidth is adjusted without any need for a separate band-pass filter stage. For high CMRR, PSRR and dynamic range, a fully differential structure is used in the design of the amplifier. The amplifier achieves a midband gain of 39.8dB with a tunable high-pass cutoff frequency ranging from 0.1Hz to 300Hz. The amplifier is fabricated in 0.18εm CMOS process and occupies 0.14mm(2) of chip area. A three electrode ECG measurement is performed using the proposed amplifier to show its feasibility for low power, compact wearable ECG monitoring application.

Novel five-state latch using double-peak negative differential resistance and standard ternary inverter

NASA Astrophysics Data System (ADS)

Shin, Sunhae; Rok Kim, Kyung

2016-04-01

We propose complement double-peak negative differential resistance (NDR) devices with ultrahigh peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with conventional CMOS and its compact five-state latch circuit by introducing standard ternary inverter (STI). At the “high”-state of STI, n-type NDR device (tunnel diode with nMOS) has 1st NDR characteristics with 1st peak and valley by band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT), whereas p-type NDR device (tunnel diode with pMOS) has second NDR characteristics from the suppression of diode current by off-state MOSFET. The “intermediate”-state of STI permits double-peak NDR device to operate five-state latch with only four transistors, which has 33% area reduction compared with that of binary inverter and 57% bit-density reduction compared with binary latch.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Preparation of MoS2/TiO2 based nanocomposites for photocatalysis and rechargeable batteries: progress, challenges, and perspective.

PubMed

Chen, Biao; Meng, Yuhuan; Sha, Junwei; Zhong, Cheng; Hu, Wenbin; Zhao, Naiqin

2017-12-21

The rapidly increasing severity of the energy crisis and environmental degradation are stimulating the rapid development of photocatalysts and rechargeable lithium/sodium ion batteries. In particular, MoS 2 /TiO 2 based nanocomposites show great potential and have been widely studied in the areas of both photocatalysis and rechargeable lithium/sodium ion batteries due to their superior combination properties. In addition to the low-cost, abundance, and high chemical stability of both MoS 2 and TiO 2 , MoS 2 /TiO 2 composites also show complementary advantages. These include the strong optical absorption of TiO 2 vs. the high catalytic activity of MoS 2 , which is promising for photocatalysis; and excellent safety and superior structural stability of TiO 2 vs. the high theoretic specific capacity and unique layered structure of MoS 2 , thus, these composites are exciting as anode materials. In this review, we first summarize the recent progress in MoS 2 /TiO 2 -based nanomaterials for applications in photocatalysis and rechargeable batteries. We highlight the synthesis, structure and mechanism of MoS 2 /TiO 2 -based nanomaterials. Then, advancements and strategies for improving the performance of these composites in photocatalytic degradation, hydrogen evolution, CO 2 reduction, LIBs and SIBs are critically discussed. Finally, perspectives on existing challenges and probable opportunities for future exploration of MoS 2 /TiO 2 -based composites towards photocatalysis and rechargeable batteries are presented. We believe the present review would provide enriched information for a deeper understanding of MoS 2 /TiO 2 composites and open avenues for the rational design of MoS 2 /TiO 2 based composites for energy and environment-related applications.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays

NASA Astrophysics Data System (ADS)

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-10-01

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems. Electronic supplementary information (ESI) available: Electrical characterization of fabricated n- and p-type nanowires, and influence of Debye screening on PSA sensing. See DOI: 10.1039/c4nr03210a

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Non-flickering 100 m RGB visible light communication transmission based on a CMOS image sensor.

PubMed

Chow, Chi-Wai; Shiu, Ruei-Jie; Liu, Yen-Chun; Liu, Yang; Yeh, Chien-Hung

2018-03-19

We demonstrate a non-flickering 100 m long-distance RGB visible light communication (VLC) transmission based on a complementary-metal-oxide-semiconductor (CMOS) camera. Experimental bit-error rate (BER) measurements under different camera ISO values and different transmission distances are evaluated. Here, we also experimentally reveal that the rolling shutter effect- (RSE) based VLC system cannot work at long distance transmission, and the under-sampled modulation- (USM) based VLC system is a good choice.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

Weight ratio effects on morphology and electrocapacitive performance for the MoS2/polypyrrole electrodes

NASA Astrophysics Data System (ADS)

Tu, Chao-Chi; Peng, Pei-Wen; Lin, Lu-Yin

2018-06-01

MoS2 is one of the promising electroactive materials for charge-storage devices. The charges cannot only be stored in the intersheet of MoS2 and the intrasheet of individual atomic layers, but also can be accumulated by conducting the Faradaic reactions on the Mo center. To further enhance the electrocapacitive performance of MoS2, incorporating conducting polymers is one of the feasible ways to improve the connection between MoS2 nanosheets. At the same time, the growth of conducting polymers can also be controlled via incorporating MoS2 nanosheets in the synthesis to enhance the conductivity and increase the specific surface area of the conducting polymers. In this work, layered structures of MoS2 nanosheets are successfully synthesized via a simple hydrothermal method, and pyrrole monomers are oxidative polymerized in the MoS2 solution to prepare the nanocomposites with different ratios of MoS2 and polypyrrole (Ppy). The optimized MoS2/Ppy electrode shows a specific capacitance (CF) of 182.28 F/g, which is higher than those of the MoS2 (40.58 F/g) and Ppy (116.95 F/g) electrodes measured at the same scan rate of 10 mV/s. The excellent high-rate capacity and good cycling stability with 20% decay on the CF value comparing to the initial value after the 1000 times repeated charge/discharge process are also achieved for the optimized MoS2/Ppy electrode. The better performance for the MoS2/Ppy electrode is resulting from the larger surface area for charge accumulation and the enhanced interconnection networks for charge transportation. The results suggest that combining two materials with complementary properties as the electrocapacitive material is one of the attractive ways to realize efficient charge-storage devices with efficient electrochemical performances and good cycling lifes.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

NASA Astrophysics Data System (ADS)

Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

2017-02-01

This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Doping of two-dimensional MoS2 by high energy ion implantation

NASA Astrophysics Data System (ADS)

Xu, Kang; Zhao, Yuda; Lin, Ziyuan; Long, Yan; Wang, Yi; Chan, Mansun; Chai, Yang

2017-12-01

Two-dimensional (2D) materials have been demonstrated to be promising candidates for next generation electronic circuits. Analogues to conventional Si-based semiconductors, p- and n-doping of 2D materials are essential for building complementary circuits. Controllable and effective doping strategies require large tunability of the doping level and negligible structural damage to ultrathin 2D materials. In this work, we demonstrate a doping method utilizing a conventional high-energy ion-implantation machine. Before the implantation, a Polymethylmethacrylate (PMMA) protective layer is used to decelerate the dopant ions and minimize the structural damage to MoS2, thus aggregating the dopants inside MoS2 flakes. By optimizing the implantation energy and fluence, phosphorus dopants are incorporated into MoS2 flakes. Our Raman and high-resolution transmission electron microscopy (HRTEM) results show that only negligibly structural damage is introduced to the MoS2 lattice during the implantation. P-doping effect by the incorporation of p+ is demonstrated by Photoluminescence (PL) and electrical characterizations. Thin PMMA protection layer leads to large kinetic damage but also a more significant doping effect. Also, MoS2 with large thickness shows less kinetic damage. This doping method makes use of existing infrastructures in the semiconductor industry and can be extended to other 2D materials and dopant species as well.

Siemens, Philips megaproject to yield superchip in 5 years

NASA Astrophysics Data System (ADS)

1985-02-01

The development of computer chips using complementary metal oxide semiconductor (CMOS) memory technology is described. The management planning and marketing strategy of the Philips and Siemens corporations with regard to the memory chip are discussed.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

NASA Astrophysics Data System (ADS)

Almuslem, A. S.; Hanna, A. N.; Yapici, T.; Wehbe, N.; Diallo, E. M.; Kutbee, A. T.; Bahabry, R. R.; Hussain, M. M.

2017-02-01

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

PubMed Central

Yu, Woo Jong; Li, Zheng; Zhou, Hailong; Chen, Yu; Wang, Yang; Huang, Yu; Duan, Xiangfeng

2014-01-01

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration. PMID:23241535

Toward CMOS image sensor based glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

PubMed Central

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

Computing motion using resistive networks

NASA Technical Reports Server (NTRS)

Koch, Christof; Luo, Jin; Mead, Carver; Hutchinson, James

1988-01-01

Recent developments in the theory of early vision are described which lead from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain 'cost' functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. It is shown how the optical flow can be computed by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. These networks can be implemented in cMOS VLSI circuits and represent plausible candidates for biological vision systems.

Nanoscale plasmonic phenomena in CVD-grown MoS 2 monolayer revealed by ultra-broadband synchrotron radiation based nano-FTIR spectroscopy and near-field microscopy

DOE PAGES

Patoka, Piotr; Ulrich, Georg; Nguyen, Ariana E.; ...

2016-01-13

Here, nanoscale plasmonic phenomena observed in single and bi-layers of molybdenum disulfide (MoS 2) on silicon dioxide (SiO 2) are reported. A scattering type scanning near-field optical microscope (s-SNOM) with a broadband synchrotron radiation (SR) infrared source was used. We also present complementary optical mapping using tunable CO 2-laser radiation. Specifically, there is a correlation of the topography of well-defined MoS 2 islands grown by chemical vapor deposition, as determined by atomic force microscopy, with the infrared (IR) signature of MoS 2. The influence of MoS 2 islands on the SiO 2 phonon resonance is discussed. The results reveal themore » plasmonic character of the MoS 2 structures and their interaction with the SiO 2 phonons leading to an enhancement of the hybridized surface plasmon-phonon mode. A theoretical analysis shows that, in the case of monolayer islands, the coupling of the MoS 2 optical plasmon mode to the SiO 2 surface phonons does not affect the infrared spectrum significantly. For two-layer MoS 2, the coupling of the extra inter-plane acoustic plasmon mode with the SiO 2 surface transverse phonon leads to a remarkable increase of the surface phonon peak at 794 cm -1. This is in agreement with the experimental data. These results show the capability of the s-SNOM technique to study local multiple excitations in complex non-homogeneous structures.« less

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Ultralow-Loss CMOS Copper Plasmonic Waveguides.

PubMed

Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

2016-01-13

Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

A CMOS smart temperature and humidity sensor with combined readout.

PubMed

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

Real time in vivo imaging and measurement of serine protease activity in the mouse hippocampus using a dedicated complementary metal-oxide semiconductor imaging device.

PubMed

Ng, David C; Tamura, Hideki; Tokuda, Takashi; Yamamoto, Akio; Matsuo, Masamichi; Nunoshita, Masahiro; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2006-09-30

The aim of the present study is to demonstrate the application of complementary metal-oxide semiconductor (CMOS) imaging technology for studying the mouse brain. By using a dedicated CMOS image sensor, we have successfully imaged and measured brain serine protease activity in vivo, in real-time, and for an extended period of time. We have developed a biofluorescence imaging device by packaging the CMOS image sensor which enabled on-chip imaging configuration. In this configuration, no optics are required whereby an excitation filter is applied onto the sensor to replace the filter cube block found in conventional fluorescence microscopes. The fully packaged device measures 350 microm thick x 2.7 mm wide, consists of an array of 176 x 144 pixels, and is small enough for measurement inside a single hemisphere of the mouse brain, while still providing sufficient imaging resolution. In the experiment, intraperitoneally injected kainic acid induced upregulation of serine protease activity in the brain. These events were captured in real time by imaging and measuring the fluorescence from a fluorogenic substrate that detected this activity. The entire device, which weighs less than 1% of the body weight of the mouse, holds promise for studying freely moving animals.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

ESD protection design for advanced CMOS

NASA Astrophysics Data System (ADS)

Huang, Jin B.; Wang, Gewen

2001-10-01

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

PubMed

Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

2011-09-01

Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

A research on radiation calibration of high dynamic range based on the dual channel CMOS

NASA Astrophysics Data System (ADS)

Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

2017-10-01

The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

Dimensional-Hybrid Structures of 2D Materials with ZnO Nanostructures via pH-Mediated Hydrothermal Growth for Flexible UV Photodetectors.

PubMed

Lee, Young Bum; Kim, Seong Ku; Lim, Yi Rang; Jeon, In Su; Song, Wooseok; Myung, Sung; Lee, Sun Sook; Lim, Jongsun; An, Ki-Seok

2017-05-03

Complementary combination of heterostructures is a crucial factor for the development of 2D materials-based optoelectronic devices. Herein, an appropriate solution for fabricating complementary dimensional-hybrid nanostructures comprising structurally tailored ZnO nanostructures and 2D materials such as graphene and MoS 2 is suggested. Structural features of ZnO nanostructures hydrothermally grown on graphene and MoS 2 are deliberately manipulated by adjusting the pH value of the growing solution, which will result in the formation of ZnO nanowires, nanostars, and nanoflowers. The detailed growth mechanism is further explored for the structurally tailored ZnO nanostructures on the 2D materials. Furthermore, a UV photodetector based on the dimensional-hybrid nanostructures is fabricated, which demonstrates their excellent photocurrent and mechanical durability. This can be understood by the existence of oxygen vacancies and oxygen-vacancies-induced band narrowing in the ZnO nanostructures, which is a decisive factor for determining their photoelectrical properties in the hybrid system.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

PubMed

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Encapsulation of Mo₂C in MoS₂ inorganic fullerene-like nanoparticles and nanotubes.

PubMed

Wiesel, Inna; Popovitz-Biro, Ronit; Tenne, Reshef

2013-02-21

Mo(2)C nanoparticles encapsulated within MoS(2) inorganic fullerene-like nanoparticles and nanotubes were produced by carbothermal reaction at 1200-1300 °C inside a vertical induction furnace. The particles were analyzed using various electron microscopy techniques and complementary methods.

Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors

NASA Astrophysics Data System (ADS)

Sun, Xiao

As the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology. In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT). By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed. The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

NASA Astrophysics Data System (ADS)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

Twenty-four-micrometer-pitch microelectrode array with 6912-channel readout at 12 kHz via highly scalable implementation for high-spatial-resolution mapping of action potentials.

PubMed

Ogi, Jun; Kato, Yuri; Matoba, Yoshihisa; Yamane, Chigusa; Nagahata, Kazunori; Nakashima, Yusaku; Kishimoto, Takuya; Hashimoto, Shigeki; Maari, Koichi; Oike, Yusuke; Ezaki, Takayuki

2017-12-19

A 24-μm-pitch microelectrode array (MEA) with 6912 readout channels at 12 kHz and 23.2-μV rms random noise is presented. The aim is to reduce noise in a "highly scalable" MEA with a complementary metal-oxide-semiconductor integration circuit (CMOS-MEA), in which a large number of readout channels and a high electrode density can be expected. Despite the small dimension and the simplicity of the in-pixel circuit for the high electrode-density and the relatively large number of readout channels of the prototype CMOS-MEA chip developed in this work, the noise within the chip is successfully reduced to less than half that reported in a previous work, for a device with similar in-pixel circuit simplicity and a large number of readout channels. Further, the action potential was clearly observed on cardiomyocytes using the CMOS-MEA. These results indicate the high-scalability of the CMOS-MEA. The highly scalable CMOS-MEA provides high-spatial-resolution mapping of cell action potentials, and the mapping can aid understanding of complex activities in cells, including neuron network activities.

Highly sensitive aptasensor based on synergetic catalysis activity of MoS2-Au-HE composite using cDNA-Au-GOD for signal amplification.

PubMed

Song, Hai-Yan; Kang, Tian-Fang; Lu, Li-Ping; Cheng, Shui-Yuan

2017-03-01

Single or few-layer nanosheets of MoS 2 (MoS 2 nanosheets) and a composite composed of MoS 2 nanosheets, Au nanoparticles (AuNPs) and hemin (HE) (denoted as MoS 2 -Au-HE) were prepared. The composites possessed high synergetic catalysis activity towards the electroreduction of hydrogen peroxide. Furthermore, glucose oxidase (GOD) and AuNPs were used as marker of the complementary DNA (cDNA) strand of kanamycin aptamer to prepare a conjugate (reffered as cDNA-Au-GOD) that was designed as the signal probe. Both cDNA-Au-GOD and MoS 2 -Au-HE were applied to fabricate aptasensor for kanamycin. MoS 2 -Au-HE acted as solid platform for kanamycin aptamer and signal transmitters. AuNPs were employed as the supporter of cDNA and GOD which catalyze dissolved oxygen to produce hydrogen peroxide in the presence of glucose. Then cathodic peak current of H 2 O 2 was recorded by differential pulse voltammetry (DPV). The electrochemical reduction of H 2 O 2 was catalyzed by MoS 2 -Au-HE that was modified onto the surface of a glassy carbon electrode (GCE). The cathodic peak current of H 2 O 2 was highly linearly decreased with an increase of kanamycin concentrations from 1.0ng/L to 1.0×10 5 ng/L, with a detection limit of 0.8ng/L. This aptasensor can be used to detect kanamycin in milk with high specificity, sensitivity and selectivity. Copyright © 2016 Elsevier B.V. All rights reserved.

Image Sensors Enhance Camera Technologies

NASA Technical Reports Server (NTRS)

2010-01-01

In the 1990s, a Jet Propulsion Laboratory team led by Eric Fossum researched ways of improving complementary metal-oxide semiconductor (CMOS) image sensors in order to miniaturize cameras on spacecraft while maintaining scientific image quality. Fossum s team founded a company to commercialize the resulting CMOS active pixel sensor. Now called the Aptina Imaging Corporation, based in San Jose, California, the company has shipped over 1 billion sensors for use in applications such as digital cameras, camera phones, Web cameras, and automotive cameras. Today, one of every three cell phone cameras on the planet feature Aptina s sensor technology.

Vertical Isolation for Photodiodes in CMOS Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2008-01-01

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

CMOS plasmonics in WDM data transmission: 200 Gb/s (8 × 25Gb/s) transmission over aluminum plasmonic waveguides.

PubMed

Dabos, G; Manolis, A; Papaioannou, S; Tsiokos, D; Markey, L; Weeber, J-C; Dereux, A; Giesecke, A L; Porschatis, C; Chmielak, B; Pleros, N

2018-05-14

We demonstrate wavelength-division-multiplexed (WDM) 200 Gb/s (8 × 25 Gb/s) data transmission over 100 μm long aluminum (Al) surface-plasmon-polariton (SPP) waveguides on a Si 3 N 4 waveguide platform at telecom wavelengths. The Al SPP waveguide was evaluated in terms of signal integrity by performing bit-error-rate (BER) measurements that revealed error-free operation for all eight 25 Gb/s non-return-to-zero (NRZ) modulated data channels with power penalties not exceeding 0.2 dB at 10 -9 . To the best of our knowledge, this is the first demonstration of WDM enabled data transmission over complementary-metal-oxide-semiconductor (CMOS) SPP waveguides fueling future development of CMOS compatible plasmo-photonic devices for on-chip optical interconnections.

Differential wide temperature range CMOS interface circuit for capacitive MEMS pressure sensors.

PubMed

Wang, Yucai; Chodavarapu, Vamsy P

2015-02-12

We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between -55 °C and 225 °C. The circuit is implemented using IBM 0.13 μm CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%.

Differential Wide Temperature Range CMOS Interface Circuit for Capacitive MEMS Pressure Sensors

PubMed Central

Wang, Yucai; Chodavarapu, Vamsy P.

2015-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between −55 °C and 225 °C. The circuit is implemented using IBM 0.13 μm CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%. PMID:25686312

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

CMOS nanoelectrode array for all-electrical intracellular electrophysiological imaging

NASA Astrophysics Data System (ADS)

Abbott, Jeffrey; Ye, Tianyang; Qin, Ling; Jorgolli, Marsela; Gertner, Rona S.; Ham, Donhee; Park, Hongkun

2017-05-01

Developing a new tool capable of high-precision electrophysiological recording of a large network of electrogenic cells has long been an outstanding challenge in neurobiology and cardiology. Here, we combine nanoscale intracellular electrodes with complementary metal-oxide-semiconductor (CMOS) integrated circuits to realize a high-fidelity all-electrical electrophysiological imager for parallel intracellular recording at the network level. Our CMOS nanoelectrode array has 1,024 recording/stimulation 'pixels' equipped with vertical nanoelectrodes, and can simultaneously record intracellular membrane potentials from hundreds of connected in vitro neonatal rat ventricular cardiomyocytes. We demonstrate that this network-level intracellular recording capability can be used to examine the effect of pharmaceuticals on the delicate dynamics of a cardiomyocyte network, thus opening up new opportunities in tissue-based pharmacological screening for cardiac and neuronal diseases as well as fundamental studies of electrogenic cells and their networks.

RAD hard PROM design study

NASA Technical Reports Server (NTRS)

1981-01-01

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Note: A disposable x-ray camera based on mass produced complementary metal-oxide-semiconductor sensors and single-board computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoidn, Oliver R.; Seidler, Gerald T., E-mail: seidler@uw.edu

We have integrated mass-produced commercial complementary metal-oxide-semiconductor (CMOS) image sensors and off-the-shelf single-board computers into an x-ray camera platform optimized for acquisition of x-ray spectra and radiographs at energies of 2–6 keV. The CMOS sensor and single-board computer are complemented by custom mounting and interface hardware that can be easily acquired from rapid prototyping services. For single-pixel detection events, i.e., events where the deposited energy from one photon is substantially localized in a single pixel, we establish ∼20% quantum efficiency at 2.6 keV with ∼190 eV resolution and a 100 kHz maximum detection rate. The detector platform’s useful intrinsic energymore » resolution, 5-μm pixel size, ease of use, and obvious potential for parallelization make it a promising candidate for many applications at synchrotron facilities, in laser-heating plasma physics studies, and in laboratory-based x-ray spectrometry.« less

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter.

PubMed

Huang, Jun; Somu, Sivasubramanian; Busnaina, Ahmed

2012-08-24

We report a simple, bottom-up/top-down approach for integrating drastically different nanoscale building blocks to form a heterogeneous complementary inverter circuit based on layered molybdenum disulfide and carbon nanotube (CNT) bundles. The fabricated CNT/MoS(2) inverter is composed of n-type molybdenum disulfide (MOS(2)) and p-type CNT transistors, with a high voltage gain of 1.3. The CNT channels are fabricated using directed assembly while the layered molybdenum disulfide channels are fabricated by mechanical exfoliation. This bottom-up fabrication approach for integrating various nanoscale elements with unique characteristics provides an alternative cost-effective methodology to complementary metal-oxide-semiconductors, laying the foundation for the realization of high performance logic circuits.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

PubMed Central

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-01-01

With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field. PMID:27879789

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

High-speed sorting of grains by color and surface texture

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect mobility with the layer thickness. The non-monotonic trend suggests that in order to harvest the maximum potential of MoS2 for high performance device applications, a layer thickness in the range of 6-12 nm would be ideal. Finally using scandium contacts on 10nm thick exfoliated MoS2 flakes that are covered by a 15nm ALD grown Al2O3 film, record high mobility of 700cm2/Vs is achieved at room-temperature which is extremely encouraging for the design of high performance logic devices. The destructive nature of the readout process in Ferroelectric Random Access Memories (FeRAMs) is one of the major limiting factors for their wide scale commercialization. Utilizing Ferroelectric Field-Effect Transistor RAM (FeTRAM) instead solves the destructive read out problem, but at the expense of introducing crystalline ferroelectrics that are hard to integrate into CMOS. In order to address these challenges a novel, fully functional, CMOS compatible, One-Transistor-One-Transistor (1T1T) memory cell architecture using an organic ferroelectric -- PVDF-TrFE -- as the memory storage unit (gate oxide) and a silicon nanowire as the memory read out unit (channel material) is proposed and experimentally demonstrated. While evaluating the scaling potential of the above mentioned organic FeTRAM, it is found that the switching time and switching voltage of this organic copolymer PVDF-TrFE exhibits an unexpected scaling behavior as a function of the lateral device dimensions. The phenomenological theory, that explains this abnormal scaling trend, involves in-plane interchain and intrachain interaction of the copolymer - resulting in a power-law dependence of the switching field on the device area (ESW alpha ACH0.1) that is ultimately responsible for the decrease in the switching time and switching voltage. These findings are encouraging since they indicate that scaling the switching voltage and switching time without aggressively scaling the copolymer thickness occurs naturally while scaling the device area -- in this way ultimately improving the packing density and leading towards high performance memory devices.

Single photon detection using Geiger mode CMOS avalanche photodiodes

NASA Astrophysics Data System (ADS)

Lawrence, William G.; Stapels, Christopher; Augustine, Frank L.; Christian, James F.

2005-10-01

Geiger mode Avalanche Photodiodes fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication technology combine high sensitivity detectors with pixel-level auxiliary circuitry. Radiation Monitoring Devices has successfully implemented CMOS manufacturing techniques to develop prototype detectors with active diameters ranging from 5 to 60 microns and measured detection efficiencies of up to 60%. CMOS active quenching circuits are included in the pixel layout. The actively quenched pixels have a quenching time less than 30 ns and a maximum count rate greater than 10 MHz. The actively quenched Geiger mode avalanche photodiode (GPD) has linear response at room temperature over six orders of magnitude. When operating in Geiger mode, these GPDs act as single photon-counting detectors that produce a digital output pulse for each photon with no associated read noise. Thermoelectrically cooled detectors have less than 1 Hz dark counts. The detection efficiency, dark count rate, and after-pulsing of two different pixel designs are measured and demonstrate the differences in the device operation. Additional applications for these devices include nuclear imaging and replacement of photomultiplier tubes in dosimeters.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Detection of Short-Waved Spin Waves in Individual Microscopic Spin-Wave Waveguides Using the Inverse Spin Hall Effect.

PubMed

Brächer, T; Fabre, M; Meyer, T; Fischer, T; Auffret, S; Boulle, O; Ebels, U; Pirro, P; Gaudin, G

2017-12-13

The miniaturization of complementary metal-oxide-semiconductor (CMOS) devices becomes increasingly difficult due to fundamental limitations and the increase of leakage currents. Large research efforts are devoted to find alternative concepts that allow for a larger data-density and lower power consumption than conventional semiconductor approaches. Spin waves have been identified as a potential technology that can complement and outperform CMOS in complex logic applications, profiting from the fact that these waves enable wave computing on the nanoscale. The practical application of spin waves, however, requires the demonstration of scalable, CMOS compatible spin-wave detection schemes in material systems compatible with standard spintronics as well as semiconductor circuitry. Here, we report on the wave-vector independent detection of short-waved spin waves with wavelengths down to 150 nm by the inverse spin Hall effect in spin-wave waveguides made from ultrathin Ta/Co 8 Fe 72 B 20 /MgO. These findings open up the path for miniaturized scalable interconnects between spin waves and CMOS and the use of ultrathin films made from standard spintronic materials in magnonics.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

PubMed

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-10-23

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

PubMed Central

Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

2015-01-01

A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

2016-11-01

Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. Inmore » order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.« less

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Decoding mobile-phone image sensor rolling shutter effect for visible light communications

NASA Astrophysics Data System (ADS)

Liu, Yang

2016-01-01

Optical wireless communication (OWC) using visible lights, also known as visible light communication (VLC), has attracted significant attention recently. As the traditional OWC and VLC receivers (Rxs) are based on PIN photo-diode or avalanche photo-diode, deploying the complementary metal-oxide-semiconductor (CMOS) image sensor as the VLC Rx is attractive since nowadays nearly every person has a smart phone with embedded CMOS image sensor. However, deploying the CMOS image sensor as the VLC Rx is challenging. In this work, we propose and demonstrate two simple contrast ratio (CR) enhancement schemes to improve the contrast of the rolling shutter pattern. Then we describe their processing algorithms one by one. The experimental results show that both the proposed CR enhancement schemes can significantly mitigate the high-intensity fluctuations of the rolling shutter pattern and improve the bit-error-rate performance.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

640 X 480 PtSi MOS infrared imager

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1992-09-01

The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 10(superscript 6) electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

Non-Faradaic electrochemical detection of protein interactions by integrated neuromorphic CMOS sensors.

PubMed

Jacquot, Blake C; Muñoz, Nini; Branch, Darren W; Kan, Edwin C

2008-05-15

Electronic detection of the binding event between biotinylated bovine serum albumen (BSA) and streptavidin is demonstrated with the chemoreceptive neuron MOS (CnuMOS) device. Differing from the ion-sensitive field-effect transistors (ISFET), CnuMOS, with the potential of the extended floating gate determined by both the sensing and control gates in a neuromorphic style, can provide protein detection without requiring analyte reference electrodes. In comparison with the microelectrode arrays, measurements are gathered through purely capacitive, non-Faradaic interactions across insulating interfaces. By using a (3-glycidoxypropyl)trimethoxysilane (3-GPS) self-assembled monolayer (SAM) as a simple covalent link for attaching proteins to a silicon dioxide sensing surface, a fully integrated, electrochemical detection platform is realized for protein interactions through monotone large-signal measurements or small-signal impedance spectroscopy. Calibration curves were created to coordinate the sensor response with ellipsometric measurements taken on witness samples. By monitoring the film thickness of streptavidin capture, a sensitivity of 25ng/cm2 or 2A of film thickness was demonstrated. With an improved noise floor the sensor can detect down to 2ng/(cm2mV) based on the calibration curve. AC measurements are shown to significantly reduce long-term sensor drift. Finally, a noise analysis of electrochemical data indicates 1/f(alpha) behavior with a noise floor beginning at approximately 1Hz.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

PubMed Central

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

Hardware-based image processing for high-speed inspection of grains

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

New Mode For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.; Smith, Lawrence S.; Soli, George A.; Lo, Roger Y.

1988-01-01

Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.

Design and fabrication of reflective spatial light modulator for high-dynamic-range wavefront control

NASA Astrophysics Data System (ADS)

Zhu, Hao; Bierden, Paul; Cornelissen, Steven; Bifano, Thomas; Kim, Jin-Hong

2004-10-01

This paper describes design and fabrication of a microelectromechanical metal spatial light modulator (SLM) integrated with complementary metal-oxide semiconductor (CMOS) electronics, for high-dynamic-range wavefront control. The metal SLM consists of a large array of piston-motion MEMS mirror segments (pixels) which can deflect up to 0.78 µm each. Both 32x32 and 150x150 arrays of the actuators (1024 and 22500 elements respectively) were fabricated onto the CMOS driver electronics and individual pixels were addressed. A new process has been developed to reduce the topography during the metal MEMS processing to fabricate mirror pixels with improved optical quality.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

NASA Astrophysics Data System (ADS)

Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

2012-04-01

In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

PubMed

Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

2013-06-01

We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

PubMed Central

Kim, Sungho; Lepkowski, William; Wilk, Seth J.; Thornton, Trevor J.; Bakkaloglu, Bertan

2014-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of −70dBm and −98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10−3 at the input powers of −70dBm at 1.2V and −98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Electric-field-controlled ferromagnetism in high-Curie-temperature Mn0.05Ge0.95 quantum dots.

PubMed

Xiu, Faxian; Wang, Yong; Kim, Jiyoung; Hong, Augustin; Tang, Jianshi; Jacob, Ajey P; Zou, Jin; Wang, Kang L

2010-04-01

Electric-field manipulation of ferromagnetism has the potential for developing a new generation of electric devices to resolve the power consumption and variability issues in today's microelectronics industry. Among various dilute magnetic semiconductors (DMSs), group IV elements such as Si and Ge are the ideal material candidates because of their excellent compatibility with the conventional complementary metal-oxide-semiconductor (MOS) technology. Here we report, for the first time, the successful synthesis of self-assembled dilute magnetic Mn(0.05)Ge(0.95) quantum dots with ferromagnetic order above room temperature, and the demonstration of electric-field control of ferromagnetism in MOS ferromagnetic capacitors up to 100 K. We found that by applying electric fields to a MOS gate structure, the ferromagnetism of the channel layer can be effectively modulated through the change of hole concentration inside the quantum dots. Our results are fundamentally important in the understanding and to the realization of high-efficiency Ge-based spin field-effect transistors.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1982-01-01

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Making A D-Latch Sensitive To Alpha Particles

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Nixon, Robert H.

1994-01-01

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Investigation of Gallium Nitride Transistor Reliability through Accelerated Life Testing and Modeling

DTIC Science & Technology

2011-12-01

Carbon Cd Cadmium CdS Cadmium Sulfide CMOS Complementary Metal Oxide Semiconductor DC Direct Current DoD Department of Defense EBL Electron...Crane Division [NAVSEA Crane], Crane, Indiana ) are Section 4.1and Section 4.3, Condition 2. Eight devices were stressed for over 1000 hours each and

FIFO Buffer for Asynchronous Data Streams

NASA Technical Reports Server (NTRS)

Bascle, K. P.

1985-01-01

Variable-rate, asynchronous data signals from up to four measuring instruments or other sources combined in first-in/first-out (FIFO) buffer for transmission on single channel. Constructed in complementary metal-oxide-semiconductor (CMOS) logic, buffer consumes low power (only 125 mW at 5V) and conforms to aerospace standards of reliability and maintainability.

An airborne multispectral imaging system based on two consumer-grade cameras for agricultural remote sensing

USDA-ARS?s Scientific Manuscript database

This paper describes the design and evaluation of an airborne multispectral imaging system based on two identical consumer-grade cameras for agricultural remote sensing. The cameras are equipped with a full-frame complementary metal oxide semiconductor (CMOS) sensor with 5616 × 3744 pixels. One came...

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor.

PubMed

Wenga, G; Jacques, E; Salaün, A-C; Rogel, R; Pichon, L; Geneste, F

2013-02-15

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology. Copyright © 2012 Elsevier B.V. All rights reserved.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

PubMed

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-05-02

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide–Semiconductor Image Sensors

PubMed Central

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-01-01

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components. PMID:28468324

Crosstalk quantification, analysis, and trends in CMOS image sensors.

PubMed

Blockstein, Lior; Yadid-Pecht, Orly

2010-08-20

Pixel crosstalk (CTK) consists of three components, optical CTK (OCTK), electrical CTK (ECTK), and spectral CTK (SCTK). The CTK has been classified into two groups: pixel-architecture dependent and pixel-architecture independent. The pixel-architecture-dependent CTK (PADC) consists of the sum of two CTK components, i.e., the OCTK and the ECTK. This work presents a short summary of a large variety of methods for PADC reduction. Following that, this work suggests a clear quantifiable definition of PADC. Three complementary metal-oxide-semiconductor (CMOS) image sensors based on different technologies were empirically measured, using a unique scanning technology, the S-cube. The PADC is analyzed, and technology trends are shown.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

CMOS technology: a critical enabler for free-form electronics-based killer applications

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors.

PubMed

Qu, Chen; Bi, Du-Yan; Sui, Ping; Chao, Ai-Nong; Wang, Yun-Fei

2017-09-22

The CMOS (Complementary Metal-Oxide-Semiconductor) is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze), causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF) framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

Performance analysis and enhancement for visible light communication using CMOS sensors

NASA Astrophysics Data System (ADS)

Guan, Weipeng; Wu, Yuxiang; Xie, Canyu; Fang, Liangtao; Liu, Xiaowei; Chen, Yingcong

2018-03-01

Complementary Metal-Oxide-Semiconductor (CMOS) sensors are widely used in mobile-phone and cameras. Hence, it is attractive if these camera can be used as the receivers of visible light communication (VLC). Using the rolling shutter mechanism can increase the data rate of VLC based on CMOS camera, and different techniques have been proposed to improve the demodulation of the rolling shutter mechanism. However, these techniques are too complexity. In this work, we demonstrate and analyze the performance of the VLC link using CMOS camera for different LED luminaires for the first time in our knowledge. Experimental evaluation to compare their bit-error-rate (BER) performances and demodulation are also performed, and it can be summarized that just need to change the LED luminaire with more uniformity light output, the blooming effect would not exist; which not only can reduce the complexity of the demodulation but also enhance the communication quality. In addition, we propose and demonstrate to use contrast limited adaptive histogram equalization to extend the transmission distance and mitigate the influence of the background noise. And the experimental results show that the BER can be decreased by an order of magnitude by using the proposed method.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

A Hybrid CMOS-Memristor Neuromorphic Synapse.

PubMed

Azghadi, Mostafa Rahimi; Linares-Barranco, Bernabe; Abbott, Derek; Leong, Philip H W

2017-04-01

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as [Formula: see text] in a [Formula: see text] process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

PubMed

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

2018-04-05

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

Implementation of material decomposition using an EMCCD and CMOS-based micro-CT system.

PubMed

Podgorsak, Alexander R; Nagesh, Sv Setlur; Bednarek, Daniel R; Rudin, Stephen; Ionita, Ciprian N

2017-02-11

This project assessed the effectiveness of using two different detectors to obtain dual-energy (DE) micro-CT data for the carrying out of material decomposition. A micro-CT coupled to either a complementary metal-oxide semiconductor (CMOS) or an electron multiplying CCD (EMCCD) detector was used to acquire image data of a 3D-printed phantom with channels filled with different materials. At any instance, materials such as iohexol contrast agent, water, and platinum were selected to make up the scanned object. DE micro-CT data was acquired, and slices of the scanned object were differentiated by material makeup. The success of the decomposition was assessed quantitatively through the computation of percentage normalized root-mean-square error (%NRMSE). Our results indicate a successful decomposition of iohexol for both detectors (%NRMSE values of 1.8 for EMCCD, 2.4 for CMOS), as well as platinum (%NRMSE value of 4.7). The CMOS detector performed material decomposition on air and water on average with 7 times more %NRMSE, possibly due to the decreased sensitivity of the CMOS system. Material decomposition showed the potential to differentiate between materials such as the iohexol and platinum, perhaps opening the door for its use in the neurovascular anatomical region. Work supported by Toshiba America Medical Systems, and partially supported by NIH grant 2R01EB002873.

Implementation of material decomposition using an EMCCD and CMOS-based micro-CT system

NASA Astrophysics Data System (ADS)

Podgorsak, Alexander R.; Nagesh, S. V. Setlur; Bednarek, Daniel R.; Rudin, Stephen; Ionita, Ciprian N.

2017-03-01

This project assessed the effectiveness of using two different detectors to obtain dual-energy (DE) micro-CT data for the carrying out of material decomposition. A micro-CT coupled to either a complementary metal-oxide semiconductor (CMOS) or an electron multiplying CCD (EMCCD) detector was used to acquire image data of a 3D-printed phantom with channels filled with different materials. At any instance, materials such as iohexol contrast agent, water, and platinum were selected to make up the scanned object. DE micro-CT data was acquired, and slices of the scanned object were differentiated by material makeup. The success of the decomposition was assessed quantitatively through the computation of percentage normalized root-mean-square error (%NRMSE). Our results indicate a successful decomposition of iohexol for both detectors (%NRMSE values of 1.8 for EMCCD, 2.4 for CMOS), as well as platinum (%NRMSE value of 4.7). The CMOS detector performed material decomposition on air and water on average with 7 times more %NRMSE, possibly due to the decreased sensitivity of the CMOS system. Material decomposition showed the potential to differentiate between materials such as the iohexol and platinum, perhaps opening the door for its use in the neurovascular anatomical region. Work supported by Toshiba America Medical Systems, and partially supported by NIH grant 2R01EB002873.

Minimal Power Latch for Single-Slope ADCs

NASA Technical Reports Server (NTRS)

Hancock, Bruce R.

2013-01-01

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

PubMed Central

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Spatial optical crosstalk in CMOS image sensors integrated with plasmonic color filters.

PubMed

Yu, Yan; Chen, Qin; Wen, Long; Hu, Xin; Zhang, Hui-Fang

2015-08-24

Imaging resolution of complementary metal oxide semiconductor (CMOS) image sensor (CIS) keeps increasing to approximately 7k × 4k. As a result, the pixel size shrinks down to sub-2μm, which greatly increases the spatial optical crosstalk. Recently, plasmonic color filter was proposed as an alternative to conventional colorant pigmented ones. However, there is little work on its size effect and the spatial optical crosstalk in a model of CIS. By numerical simulation, we investigate the size effect of nanocross array plasmonic color filters and analyze the spatial optical crosstalk of each pixel in a Bayer array of a CIS with a pixel size of 1μm. It is found that the small pixel size deteriorates the filtering performance of nanocross color filters and induces substantial spatial color crosstalk. By integrating the plasmonic filters in the low Metal layer in standard CMOS process, the crosstalk reduces significantly, which is compatible to pigmented filters in a state-of-the-art backside illumination CIS.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

Miniature atomic scalar magnetometer for space based on the rubidium isotope 87Rb.

PubMed

Korth, Haje; Strohbehn, Kim; Tejada, Francisco; Andreou, Andreas G; Kitching, John; Knappe, Svenja; Lehtonen, S John; London, Shaughn M; Kafel, Matiwos

2016-08-01

A miniature atomic scalar magnetometer based on the rubidium isotope 87 Rb was developed for operation in space. The instrument design implements both M x and M z mode operation and leverages a novel microelectromechanical system (MEMS) fabricated vapor cell and a custom silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS) integrated circuit. The vapor cell has a volume of only 1 mm 3 so that it can be efficiently heated to its operating temperature by a specially designed, low-magnetic-field-generating resistive heater implemented in multiple metal layers of the transparent sapphire substrate of the SOS-CMOS chips. The SOS-CMOS chip also hosts the Helmholtz coil and associated circuitry to stimulate the magnetically sensitive atomic resonance and temperature sensors. The prototype instrument has a total mass of fewer than 500 g and uses less than 1 W of power, while maintaining a sensitivity of 15 pT/√Hz at 1 Hz, comparable to present state-of-the-art absolute magnetometers.

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

A novel optical detector concept for dedicated and multi-modality in vivo small animal imaging

NASA Astrophysics Data System (ADS)

Peter, Jörg; Schulz, Ralf B.; Unholtz, Daniel; Semmler, Wolfhard

2007-07-01

An optical detector suitable for inclusion in tomographic arrangements for non-contact in vivo bioluminescence and fluorescence imaging applications is proposed. It consists of a microlens array (MLA) intended for field-of-view definition, a large-field complementary metal-oxide-semiconductor (CMOS) chip for light detection, a septum mask for cross-talk suppression, and an exchangeable filter to block excitation light. Prototype detector units with sensitive areas of 2.5 cm x 5 cm each were assembled. The CMOS sensor constitutes a 512 x 1024 photodiode matrix at 48 μm pixel pitch. Refractive MLAs with plano-convex lenses of 480 μm in diameter and pitch were selected resulting in a 55 x 105 lens matrix. The CMOS sensor is aligned on the focal plane of the MLA at 2.15mm distance. To separate individual microlens images an opaque multi-bore septum mask of 2.1mm in thickness and bore diameters of 400 μm at 480 μm pitch, aligned with the lens pattern, is placed between MLA and CMOS. Intrinsic spatial detector resolution and sensitivity was evaluated experimentally as a function of detector-object distance. Due to its small overall dimensions such detectors can be favorably packed for tomographic imaging (optical diffusion tomography, ODT) yielding complete 2 π field-of-view coverage. We also present a design study of a device intended to simultaneously image positron labeled substrates (positron emission tomography, PET) and optical molecular probes in small animals such as mice and rats. It consists of a cylindrical allocation of optical detector units which form an inner detector ring while PET detector blocks are mounted in radial extension, those gaining complementary information in a single, intrinsically coregistered experimental data acquisition study. Finally, in a second design study we propose a method for integrated optical and magnetic resonance imaging (MRI) which yields in vivo functional/molecular information that is intrinsically registered with the anatomy of the image object.

Fluorescence-suppressed time-resolved Raman spectroscopy of pharmaceuticals using complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector.

PubMed

Rojalin, Tatu; Kurki, Lauri; Laaksonen, Timo; Viitala, Tapani; Kostamovaara, Juha; Gordon, Keith C; Galvis, Leonardo; Wachsmann-Hogiu, Sebastian; Strachan, Clare J; Yliperttula, Marjo

2016-01-01

In this work, we utilize a short-wavelength, 532-nm picosecond pulsed laser coupled with a time-gated complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector to acquire Raman spectra of several drugs of interest. With this approach, we are able to reveal previously unseen Raman features and suppress the fluorescence background of these drugs. Compared to traditional Raman setups, the present time-resolved technique has two major improvements. First, it is possible to overcome the strong fluorescence background that usually interferes with the much weaker Raman spectra. Second, using the high photon energy excitation light source, we are able to generate a stronger Raman signal compared to traditional instruments. In addition, observations in the time domain can be performed, thus enabling new capabilities in the field of Raman and fluorescence spectroscopy. With this system, we demonstrate for the first time the possibility of recording fluorescence-suppressed Raman spectra of solid, amorphous and crystalline, and non-photoluminescent and photoluminescent drugs such as caffeine, ranitidine hydrochloride, and indomethacin (amorphous and crystalline forms). The raw data acquired by utilizing only the picosecond pulsed laser and a CMOS SPAD detector could be used for identifying the compounds directly without any data processing. Moreover, to validate the accuracy of this time-resolved technique, we present density functional theory (DFT) calculations for a widely used gastric acid inhibitor, ranitidine hydrochloride. The obtained time-resolved Raman peaks were identified based on the calculations and existing literature. Raman spectra using non-time-resolved setups with continuous-wave 785- and 532-nm excitation lasers were used as reference data. Overall, this demonstration of time-resolved Raman and fluorescence measurements with a CMOS SPAD detector shows promise in diverse areas, including fundamental chemical research, the pharmaceutical setting, process analytical technology (PAT), and the life sciences.

Contact CMOS imaging of gaseous oxygen sensor array

PubMed Central

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Contact CMOS imaging of gaseous oxygen sensor array.

PubMed

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

NASA Astrophysics Data System (ADS)

Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

2011-01-01

In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

A portable electronic system for radiation dosimetry using electrets

NASA Astrophysics Data System (ADS)

Cruvinel, P. E.; Mascarenhas, S.; Cameron, J.

1990-02-01

An electret dosimeter with a cylindrical active volume has been introduced by Mascarenhas and collaborators [Proc. 10th Anniversary Conf. 1969-1979, Associacâo Brasileira de Fisicos em Medicina, p. 488; Topics Appl. Phys. 33 (1987) 321] for possible use in personnel and area monitoring. The full energy response curve as well as the degree of reproducibility and accuracy of the dosimeter are reported in a previous report [O. Guerrini, Master Science Thesis, São Carlos, USP-IFQSC (1982)]. For dimensions similar to those of the common pen dosimeter, the electret has a total surface charge of the order of 10 -9 C and it has a readout sensitivity of the order of 10 -5 Gy with a useful range of 5 × 10 -2 Gy. In this paper we describe a portable electronic system to measure X and γ-rays using a cylindrical electret ionization chamber. It uses commercially available operational amplifiers, and charge measurements can also be made by connecting a suitable capacitor in the feedback loop. With this system it is possible to measure equivalent surface charges up to (19.99±0.01) on the dosimeter. The readout doses are shown on a 3 {1}/{2} digit liquid crystal display (LCD). We have used complementary metal oxide semiconductor (CMOS) and bipolar metal oxide semiconductor (BiMOS) operatonal amplifier devices in the system's design. This choice provides small power consumption and is ideal for battery powered instruments. Furthermore the instrument is ideally suited for in situ measurements of X and γ radiation using a cylindrical electret ionization chamber.

A wirelessly powered electro-acupuncture based on adaptive pulsewidth monophase stimulation.

PubMed

Kiseok Song; Long Yan; Seulki Lee; Yoo, Jerald; Hoi-Jun Yoo

2011-04-01

A wirelessly powered electro-acupuncture (EA) system with adaptive-pulsewidth (APW) monophase stimulation is presented for convenient invasive medicine. The proposed system removes cumbersome wires connected between EA nodes and an EA controller in order to realize both patients' convenience and remedial values simultaneously. An ultra-low-power stimulator integrated circuit (IC) that is integrated on the flexible-printed-circuit board (F-PCB) is attached to the tip of a needle electrode. Combined with a conductive yarn helical antenna wound around the needle electrode, the EA node receives wireless power from the EA controller using 433 MHz with the maximum loss of 6 dB. A zero-Vth nMOS rectifier harvests a supply voltage of 1.0 V from a -16-dBm incoming power signal with 32% efficiency. To deal with a body impedance variation (BIV) in the range of 100-200 kΩ , the proposed APW stimulator IC, fabricated in a 0.18-μm 1P6M complementary metal-oxide semiconductor CMOS process and occupying 1.56 mm(2), enables constant charge injection of 80-nC/stimulation. To ensure the patients' safety, the EA node (a pair of EAs) shares ground and clock wires to operate in alternate monophase (AMP) fashion for neutralizing the injected charge. The proposed wirelessly powered EA node was verified by applying it to a chunk of pork as a body model with the wireless power supplied from an RF signal generator (output power of 10 dBm and located 30 cm away).

Two different ways for waveguides and optoelectronics components on top of C-MOS

NASA Astrophysics Data System (ADS)

Fedeli, J. M.; Jeannot, S.; Kostrzewa, M.; Di Cioccio, L.; Jousseaume, V.; Orobtchouk, R.; Maury, P.; Zussy, M.

2006-02-01

While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators" technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

Layout optimization of GGISCR structure for on-chip system level ESD protection applications

NASA Astrophysics Data System (ADS)

Zeng, Jie; Dong, Shurong; Wong, Hei; Hu, Tao; Li, Xiang

2016-12-01

To improve the holding voltage, area efficiency and robustness, a comparative study on single finger, 4-finger and round shape layout of gate-grounded-nMOS incorporated SCR (GGISCR) devices are conducted. The devices were fabricated with a commercial 0.35 μm HV-CMOS process without any additional mask or process modification. To have a fair comparison, we develop a new Figure-of-Merit (FOM) modeling for the performance evaluation of these devices. We found that the ring type device which has an It2 value of 18.9 A is area efficient and has smaller effective capacitance. The different characteristics were explained with the different effective ESD currents in these layout structures.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

A highly linear baseband Gm—C filter for WLAN application

NASA Astrophysics Data System (ADS)

Lijun, Yang; Zheng, Gong; Yin, Shi; Zhiming, Chen

2011-09-01

A low voltage, highly linear transconductan—C (Gm—C) low-pass filter for wireless local area network (WLAN) transceiver application is proposed. This transmitter (Tx) filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency. By utilizing pseudo-differential linear-region MOS transconductors, the filter IIP3 is measured to be as high as 9.5 dBm. Fabricated in a 0.35 μm standard CMOS technology, the proposed filter chip occupies a 0.41 × 0.17 mm2 die area and consumes 3.36 mA from a 3.3-V power supply.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

High density submicron magnetoresistive random access memory (invited)

NASA Astrophysics Data System (ADS)

Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

1999-04-01

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

Compressive Sensing Image Sensors-Hardware Implementation

PubMed Central

Dadkhah, Mohammadreza; Deen, M. Jamal; Shirani, Shahram

2013-01-01

The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed. PMID:23584123

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

FDSOI 28nm performances study for RF energy scavenging

NASA Astrophysics Data System (ADS)

Rochefeuille, E.; Alicalapa, F.; Douyère, A.; Vuong, T. P.

2018-03-01

This paper presents a study on an integrated technology: Fully-Depleted-Silicon-On-Insulator (FDSOI) at a 28nm node. FDSOI results are compared to another technology: Complementary-Metal-Oxide-Semiconductor (CMOS) 350nm. The aim of this work was to demonstrate the advantages of using FDSOI technology in RF energy scavenging applications. Characteristics of transistors are pointed out and results showed an improved 22%-output voltage gain for a series rectifier and a 13%-output voltage gain for a Dickson charge pump in FDSOI technology compared to CMOS, for an input voltage and power of 0.5 V and 0 dBm respectively. Those results allowed to prove that FDSOI 28nm is a better technology choice for energy scavenging and low-power applications.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Large Format CMOS-based Detectors for Diffraction Studies

NASA Astrophysics Data System (ADS)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Oxide-mediated recovery of field-effect mobility in plasma-treated MoS2

PubMed Central

Jadwiszczak, Jakub; O’Callaghan, Colin; Zhou, Yangbo; Fox, Daniel S.; Weitz, Eamonn; Keane, Darragh; Cullen, Conor P.; O’Reilly, Ian; Downing, Clive; Shmeliov, Aleksey; Maguire, Pierce; Gough, John J.; McGuinness, Cormac; Ferreira, Mauro S.; Bradley, A. Louise; Boland, John J.; Duesberg, Georg S.; Nicolosi, Valeria; Zhang, Hongzhou

2018-01-01

Precise tunability of electronic properties of two-dimensional (2D) nanomaterials is a key goal of current research in this field of materials science. Chemical modification of layered transition metal dichalcogenides leads to the creation of heterostructures of low-dimensional variants of these materials. In particular, the effect of oxygen-containing plasma treatment on molybdenum disulfide (MoS2) has long been thought to be detrimental to the electrical performance of the material. We show that the mobility and conductivity of MoS2 can be precisely controlled and improved by systematic exposure to oxygen/argon plasma and characterize the material using advanced spectroscopy and microscopy. Through complementary theoretical modeling, which confirms conductivity enhancement, we infer the role of a transient 2D substoichiometric phase of molybdenum trioxide (2D-MoOx) in modulating the electronic behavior of the material. Deduction of the beneficial role of MoOx will serve to open the field to new approaches with regard to the tunability of 2D semiconductors by their low-dimensional oxides in nano-modified heterostructures. PMID:29511736

Multi-band infrared camera systems

NASA Astrophysics Data System (ADS)

Davis, Tim; Lang, Frank; Sinneger, Joe; Stabile, Paul; Tower, John

1994-12-01

The program resulted in an IR camera system that utilizes a unique MOS addressable focal plane array (FPA) with full TV resolution, electronic control capability, and windowing capability. Two systems were delivered, each with two different camera heads: a Stirling-cooled 3-5 micron band head and a liquid nitrogen-cooled, filter-wheel-based, 1.5-5 micron band head. Signal processing features include averaging up to 16 frames, flexible compensation modes, gain and offset control, and real-time dither. The primary digital interface is a Hewlett-Packard standard GPID (IEEE-488) port that is used to upload and download data. The FPA employs an X-Y addressed PtSi photodiode array, CMOS horizontal and vertical scan registers, horizontal signal line (HSL) buffers followed by a high-gain preamplifier and a depletion NMOS output amplifier. The 640 x 480 MOS X-Y addressed FPA has a high degree of flexibility in operational modes. By changing the digital data pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or noninterlaced format. The thermal sensitivity performance of the second system's Stirling-cooled head was the best of the systems produced.

2D materials integrated in Si3N4 photonics platform

NASA Astrophysics Data System (ADS)

Faneca, Joaquin; Hogan, Benjamin T.; Torres Alonso, E.; Craciun, Monica; Baldycheva, Anna

2018-02-01

In this paper, we discuss a back-end CMOS fabrication process for the large-scale integration of 2D materials on SOI (siliconon-insulator) platform and present a complete theoretical study of the change in the effective refractive index of 2D materialsenabled silicon nitride waveguide structures. The chemical vapour deposition (CVD) and liquid exfoliation fabrication methods are described for the fabrication of graphene, WS2 and MoS2 thin films. Finite-difference frequency-domain (FDFD) approach and the Transfer Matrix Method were used in order to mathematically describe these structures. The introduction of thin films of 2D material onto Si3N4 waveguide structures allows manipulation of the optical characteristics to a high degree of precision by varying the Fermi-level through the engineering of the number of atomically thin layers or by electrical tuning, for example. Based on the proposed tuning approach, designs of graphene, WS2 and MoS2 enabled Si3N4 micro-ring structures are presented for the visible and NIR range, which demonstrate versatility and desirable properties for a wide range of applications, such as bio-chemical sensing and optical communications.

Protection of MOS capacitors during anodic bonding

NASA Astrophysics Data System (ADS)

Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

2002-07-01

We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

Ferroelectric memory based on molybdenum disulfide and ferroelectric hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Xia, Qiangfei; Zhu, Wenjuan

Recently, ferroelectric hafnium oxide (HfO2) was discovered as a new type of ferroelectric material with the advantages of high coercive field, excellent scalability (down to 2.5 nm), and good compatibility with CMOS processing. In this work, we demonstrate, for the first time, 2D ferroelectric memories with molybdenum disulfide (MoS2) as the channel material and aluminum doped HfO2 as the ferroelectric gate dielectric. A 16 nm thick layer of HfO2, doped with 5.26% aluminum, was deposited via atomic layer deposition (ALD), then subjected to rapid thermal annealing (RTA) at 1000 °C, and the polarization-voltage characteristics of the resulting metal-ferroelectric-metal (MFM) capacitors were measured, showing a remnant polarization of 0.6 μC/cm2. Ferroelectric memories with embedded ferroelectric hafnium oxide stacks and monolayer MoS2 were fabricated. The transfer characteristics after program and erase pulses revealed a clear ferroelectric memory window. In addition, endurance (up to 10,000 cycles) of the devices were tested and effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, were observed. This research can potentially lead to advances of 2D materials in low-power logic and memory applications.

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Potentiometric Dye Imaging for Pheochromocytoma and Cortical Neurons with a Novel Measurement System Using an Integrated Complementary Metal-Oxide-Semiconductor Imaging Device

NASA Astrophysics Data System (ADS)

Kobayashi, Takuma; Tagawa, Ayato; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Hatanaka, Yumiko; Tamura, Hideki; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2010-11-01

The combination of optical imaging with voltage-sensitive dyes is a powerful tool for studying the spatiotemporal patterns of neural activity and understanding the neural networks of the brain. To visualize the potential status of multiple neurons simultaneously using a compact instrument with high density and a wide range, we present a novel measurement system using an implantable biomedical photonic LSI device with a red absorptive light filter for voltage-sensitive dye imaging (BpLSI-red). The BpLSI-red was developed for sensing fluorescence by the on-chip LSI, which was designed by using complementary metal-oxide-semiconductor (CMOS) technology. A micro-electro-mechanical system (MEMS) microfabrication technique was used to postprocess the CMOS sensor chip; light-emitting diodes (LEDs) were integrated for illumination and to enable long-term cell culture. Using the device, we succeeded in visualizing the membrane potential of 2000-3000 cells and the process of depolarization of pheochromocytoma cells (PC12 cells) and mouse cerebral cortical neurons in a primary culture with cellular resolution. Therefore, our measurement application enables the detection of multiple neural activities simultaneously.

An optical relay approach to very low cost hybrid polymer-complementary metal-oxide semiconductor electrophoresis instrumentation.

PubMed

Hall, Gordon H; Sloan, David L; Ma, Tianchi; Couse, Madeline H; Martel, Stephane; Elliott, Duncan G; Glerum, D Moira; Backhouse, Christopher J

2014-07-04

Electrophoresis is an integral part of many molecular diagnostics protocols and an inexpensive implementation would greatly facilitate point-of-care (POC) applications. However, the high instrumentation cost presents a substantial barrier, much of it associated with fluorescence detection. The cost of such systems could be substantially reduced by placing the fluidic channel and photodiode directly above the detector in order to collect a larger portion of the fluorescent light. In future, this could be achieved through the integration and monolithic fabrication of photoresist microchannels on complementary metal-oxide semiconductor microelectronics (CMOS). However, the development of such a device is expensive due to high non-recurring engineering costs. To facilitate that development, we present a system that utilises an optical relay to integrate low-cost polymeric microfluidics with a CMOS chip that provides a photodiode, analog-digital conversion and a standard serial communication interface. This system embodies an intermediate level of microelectronic integration, and significantly decreases development costs. With a limit of detection of 1.3±0.4nM of fluorescently end-labeled deoxyribonucleic acid (DNA), it is suitable for diagnostic applications. Copyright © 2014 Elsevier B.V. All rights reserved.

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

NASA Astrophysics Data System (ADS)

Lu, Y.; Tang, H.; Fung, S.; Wang, Q.; Tsai, J. M.; Daneman, M.; Boser, B. E.; Horsley, D. A.

2015-06-01

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ˜14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

PubMed

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors.

PubMed

Zhang, Xiang; Zhao, Jianwen; Dou, Junyan; Tange, Masayoshi; Xu, Weiwei; Mo, Lixin; Xie, Jianjun; Xu, Wenya; Ma, Changqi; Okazaki, Toshiya; Cui, Zheng

2016-09-01

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO 2 thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10 5 , mobility of ≈15 cm 2 V -1 s -1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V dd = 1.5 V) and maximum voltage gain of 30 at V dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V dd of 1 V is achieved. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

PubMed Central

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun

2018-01-01

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256×13 real-time radar image display with a throughput of 28.2 frames per second. PMID:29621170

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

PubMed

Hussain, Aftab M; Hussain, Muhammad M

2016-06-01

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

PubMed Central

Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

2014-01-01

Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

An ultrasensitive method of real time pH monitoring with complementary metal oxide semiconductor image sensor.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2015-02-09

CMOS sensors are becoming a powerful tool in the biological and chemical field. In this work, we introduce a new approach on quantifying various pH solutions with a CMOS image sensor. The CMOS image sensor based pH measurement produces high-accuracy analysis, making it a truly portable and user friendly system. pH indicator blended hydrogel matrix was fabricated as a thin film to the accurate color development. A distinct color change of red, green and blue (RGB) develops in the hydrogel film by applying various pH solutions (pH 1-14). The semi-quantitative pH evolution was acquired by visual read out. Further, CMOS image sensor absorbs the RGB color intensity of the film and hue value converted into digital numbers with the aid of an analog-to-digital converter (ADC) to determine the pH ranges of solutions. Chromaticity diagram and Euclidean distance represent the RGB color space and differentiation of pH ranges, respectively. This technique is applicable to sense the various toxic chemicals and chemical vapors by situ sensing. Ultimately, the entire approach can be integrated into smartphone and operable with the user friendly manner. Copyright © 2014 Elsevier B.V. All rights reserved.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

PubMed Central

Boukhayma, Assim; Peizerat, Arnaud; Enz, Christian

2016-01-01

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

NASA Astrophysics Data System (ADS)

Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

2016-07-01

In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

Single-layer MoS2 electronics.

PubMed

Lembke, Dominik; Bertolazzi, Simone; Kis, Andras

2015-01-20

CONSPECTUS: Atomic crystals of two-dimensional materials consisting of single sheets extracted from layered materials are gaining increasing attention. The most well-known material from this group is graphene, a single layer of graphite that can be extracted from the bulk material or grown on a suitable substrate. Its discovery has given rise to intense research effort culminating in the 2010 Nobel Prize in physics awarded to Andre Geim and Konstantin Novoselov. Graphene however represents only the proverbial tip of the iceberg, and increasing attention of researchers is now turning towards the veritable zoo of so-called "other 2D materials". They have properties complementary to graphene, which in its pristine form lacks a bandgap: MoS2, for example, is a semiconductor, while NbSe2 is a superconductor. They could hold the key to important practical applications and new scientific discoveries in the two-dimensional limit. This family of materials has been studied since the 1960s, but most of the research focused on their tribological applications: MoS2 is best known today as a high-performance dry lubricant for ultrahigh-vacuum applications and in car engines. The realization that single layers of MoS2 and related materials could also be used in functional electronic devices where they could offer advantages compared with silicon or graphene created a renewed interest in these materials. MoS2 is currently gaining the most attention because the material is easily available in the form of a mineral, molybdenite, but other 2D transition metal dichalcogenide (TMD) semiconductors are expected to have qualitatively similar properties. In this Account, we describe recent progress in the area of single-layer MoS2-based devices for electronic circuits. We will start with MoS2 transistors, which showed for the first time that devices based on MoS2 and related TMDs could have electrical properties on the same level as other, more established semiconducting materials. This allowed rapid progress in this area and was followed by demonstrations of basic digital circuits and transistors operating in the technologically relevant gigahertz range of frequencies, showing that the mobility of MoS2 and TMD materials is sufficiently high to allow device operation at such high frequencies. Monolayer MoS2 and other TMDs are also direct band gap semiconductors making them interesting for realizing optoelectronic devices. These range from simple phototransistors showing high sensitivity and low noise, to light emitting diodes and solar cells. All the electronic and optoelectronic properties of MoS2 and TMDs are accompanied by interesting mechanical properties with monolayer MoS2 being as stiff as steel and 30× stronger. This makes it especially interesting in the context of flexible electronics where it could combine the high degree of mechanical flexibility commonly associated with organic semiconductors with high levels of electrical performance. All these results show that MoS2 and TMDs are promising materials for electronic and optoelectronic applications.

Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

DTIC Science & Technology

2016-04-01

with Al top electrodes and Cu bottom electrodes. ................... 9 Figure 4. SPICE netlist structure...memory elements play a part in logic gate. 4.4.2 Simulation SPICE Simulation Program for Integrated Circuits Emphasis ( SPICE ) is a general-purpose...analog circuit simulator that was developed at the Electronics Research Laboratory of the University of California, Berkeley [6]. In 1975, SPICE

Radiation Response of Emerging FeRAM Technology

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Scheick, L. Z.

2001-01-01

The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Resistive switching phenomena of tungsten nitride thin films with excellent CMOS compatibility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Seok Man; Kim, Hee-Dong; An, Ho-Myoung

2013-12-15

Graphical abstract: - Highlights: • The resistive switching characteristics of WN{sub x} thin films. • Excellent CMOS compatibility WN{sub x} films as a resistive switching material. • Resistive switching mechanism revealed trap-controlled space charge limited conduction. • Good endurance and retention properties over 10{sup 5} cycles, and 10{sup 5} s, respectively - Abstract: We report the resistive switching (RS) characteristics of tungsten nitride (WN{sub x}) thin films with excellent complementary metal-oxide-semiconductor (CMOS) compatibility. A Ti/WN{sub x}/Pt memory cell clearly shows bipolar RS behaviors at a low voltage of approximately ±2.2 V. The dominant conduction mechanisms at low and high resistancemore » states were verified by Ohmic behavior and trap-controlled space-charge-limited conduction, respectively. A conducting filament model by a redox reaction explains the RS behavior in WN{sub x} films. We also demonstrate the memory characteristics during pulse operation, including a high endurance over >10{sup 5} cycles and a long retention time of >10{sup 5} s.« less

CMOS-Compatible Fabrication for Photonic Crystal-Based Nanofluidic Structure.

PubMed

Peng, Wang; Chen, Youping; Ai, Wu; Zhang, Dailin; Song, Han; Xiong, Hui; Huang, Pengcheng

2017-12-01

Photonic crystal (PC)-based devices have been widely used since 1990s, while PC has just stepped into the research area of nanofluidic. In this paper, photonic crystal had been used as a complementary metal oxide semiconductors (CMOS) compatible part to create a nanofluidic structure. A nanofluidic structure prototype had been fabricated with CMOS-compatible techniques. The nanofluidic channels were sealed by direct bonding polydimethylsiloxane (PDMS) and the periodic gratings on photonic crystal structure. The PC was fabricated on a 4-in. Si wafer with Si 3 N 4 as the guided mode layer and SiO 2 film as substrate layer. The higher order mode resonance wavelength of PC-based nanofluidic structure had been selected, which can confine the enhanced electrical field located inside the nanochannel area. A design flow chart was used to guide the fabrication process. By optimizing the fabrication device parameters, the periodic grating of PC-based nanofluidic structure had a high-fidelity profile with fill factor at 0.5. The enhanced electric field was optimized and located within the channel area, and it can be used for PC-based nanofluidic applications with high performance.

A miniaturized neuroprosthesis suitable for implantation into the brain

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Binkley, David; Blalock, Benjamin; Andersen, Richard; Ulshoefer, Norbert; Johnson, Travis; Del Castillo, Linda

2003-01-01

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

The effects of the geosynchronous energetic particle radiation environment on spacecraft charging phenomena

NASA Technical Reports Server (NTRS)

Reagan, J. B.; Imhof, W. L.; Gaines, E. E.

1977-01-01

The energetic electron environment at the geosynchronous orbit is responsible for a variety of adverse charging effects on spacecraft components. The most serious of these is the degradation and failure of a complementary-metal-oxide-semiconductor (CMOS) electronic components as a result of internal charge-buildup induced by the energetic electrons. Efforts to accurately determine the expected lifetime of these components in this orbit are hampered by the lack of detailed knowledge of the electron spectrum and intensity, particularly of the more penetrating energies greater than 1.5 MeV. This problem is illustrated through the calculation of the dose received by a CMOS device from the energetic electrons and associated bremsstrahlung as a function of aluminum shielding thickness using the NASA AE-6 and the Aerospace measured electron environments. Two computational codes which were found to be in good agreement were used to perform the calculations. For a given shielding thickness the dose received with the two radiation environments differ by as much as a factor of seven with a corresponding variation in lifetime of the CMOS.

Hyperspectral Image-Based Night-Time Vehicle Light Detection Using Spectral Normalization and Distance Mapper for Intelligent Headlight Control.

PubMed

Kim, Heekang; Kwon, Soon; Kim, Sungho

2016-07-08

This paper proposes a vehicle light detection method using a hyperspectral camera instead of a Charge-Coupled Device (CCD) or Complementary metal-Oxide-Semiconductor (CMOS) camera for adaptive car headlamp control. To apply Intelligent Headlight Control (IHC), the vehicle headlights need to be detected. Headlights are comprised from a variety of lighting sources, such as Light Emitting Diodes (LEDs), High-intensity discharge (HID), and halogen lamps. In addition, rear lamps are made of LED and halogen lamp. This paper refers to the recent research in IHC. Some problems exist in the detection of headlights, such as erroneous detection of street lights or sign lights and the reflection plate of ego-car from CCD or CMOS images. To solve these problems, this study uses hyperspectral images because they have hundreds of bands and provide more information than a CCD or CMOS camera. Recent methods to detect headlights used the Spectral Angle Mapper (SAM), Spectral Correlation Mapper (SCM), and Euclidean Distance Mapper (EDM). The experimental results highlight the feasibility of the proposed method in three types of lights (LED, HID, and halogen).

Latchup in CMOS devices from heavy ions

NASA Technical Reports Server (NTRS)

Soliman, K.; Nichols, D. K.

1983-01-01

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

Patterning and templating for nanoelectronics.

PubMed

Galatsis, Kosmas; Wang, Kang L; Ozkan, Mihri; Ozkan, Cengiz S; Huang, Yu; Chang, Jane P; Monbouquette, Harold G; Chen, Yong; Nealey, Paul; Botros, Youssry

2010-02-09

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Comotti, Daniele; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio

2015-10-01

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor.

PubMed

Zin, Hafiz M; Harris, Emma J; Osmond, John P F; Allinson, Nigel M; Evans, Philip M

2013-05-21

This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s(-1) with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

Combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on CMOS APS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Chen, Wei; Sheng, Jiangkun

The combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on complementary metal-oxide semiconductor (CMOS) active pixel sensors (APS) have been discussed and some new experimental phenomena are presented. The samples are manufactured in the standard 0.35-μm CMOS technology. Two samples were first exposed to {sup 60}Co γ-rays up to the total ionizing dose (TID) level of 200 krad(Si) at the dose rates of 50.0 and 0.2 rad(Si)/s, and then exposed to neutron fluence up to 1 × 10{sup 11} n/cm{sup 2} (1-MeV equivalent neutron fluence). One sample was first exposed to neutron fluence up to 1 × 10{supmore » 11} n/cm{sup 2} (1-MeV equivalent neutron fluence), and then exposed to {sup 60}Co γ-rays up to the TID level of 200 krad(Si) at the dose rate of 0.2 rad(Si)/s. The mean dark signal (K{sub D}), the dark signal non-uniformity (DSNU), and the noise (V{sub N}) versus the total dose and neutron fluence has been investigated. The degradation mechanisms of CMOS APS image sensors have been analyzed, especially for the interaction induced by neutron displacement damage and TID damage.« less

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

An Autonomous Circuit for the Measurement of Photovoltaic Devices Parameters.

DTIC Science & Technology

1986-09-01

Comparison Data, Gallium Arsenide ................ 80 A 7 A,. TABLE OF SYMBOLS A Curve Fitting Constant ADC Analog to Digital Converter AMO Air-Mass-Zero...in Radiation Fluence in the Logarithmic Region CMOS Complementary Metal-Oxide Semiconductor DAC Digital to Analog Converter DC Direct Current Dp Hole...characteristics of individual solar cells. A novel circuit is developed that uses a microprocessor controlled Digital to Analog Converter (DAC) to obtain

Radiation Status of Sub-65 nm Electronics

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.

2011-01-01

Ultra-scaled complementary metal oxide semiconductor (CMOS) includes commercial foundry capabilities at and below the 65 nm technology node Radiation evaluations take place using standard products and test characterization vehicles (memories, logic/latch chains, etc.) NEPP focus is two-fold: (1) Conduct early radiation evaluations to ascertain viability for future NASA missions (i.e. leverage commercial technology development). (2) Uncover gaps in current testing methodologies and mechanism comprehension -- early risk mitigation.

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Y.; Fung, S.; Wang, Q.

2015-06-29

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ∼14 kPa with a 28 V input, in reasonable agreement with predication from analyticalmore » calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.« less

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Sathiyanarayanan, Rajesh; Kwon, Unoh; Narayanan, Vijay; Murali, K. V. R. M.

2013-07-01

We investigate the physical properties of a portion of the gate stack of an ultra-scaled complementary metal-oxide-semiconductor (CMOS) device. The effects of point defects, such as oxygen vacancy, oxygen, and aluminum interstitials at the HfO2/TiN interface, on the effective work function of TiN are explored using density functional theory. We compute the diffusion barriers of such point defects in the bulk TiN and across the HfO2/TiN interface. Diffusion of these point defects across the HfO2/TiN interface occurs during the device integration process. This results in variation of the effective work function and hence in the threshold voltage variation in the devices. Further, we simulate the effects of varying the HfO2/TiN interface stoichiometry on the effective work function modulation in these extremely-scaled CMOS devices. Our results show that the interface rich in nitrogen gives higher effective work function, whereas the interface rich in titanium gives lower effective work function, compared to a stoichiometric HfO2/TiN interface. This theoretical prediction is confirmed by the experiment, demonstrating over 700 meV modulation in the effective work function.

An All-Solution-Based Hybrid CMOS-Like Quantum Dot/Carbon Nanotube Inverter.

PubMed

Shulga, Artem G; Derenskyi, Vladimir; Salazar-Rios, Jorge Mario; Dirin, Dmitry N; Fritsch, Martin; Kovalenko, Maksym V; Scherf, Ullrich; Loi, Maria A

2017-09-01

The development of low-cost, flexible electronic devices is subordinated to the advancement in solution-based and low-temperature-processable semiconducting materials, such as colloidal quantum dots (QDs) and single-walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high-performance complementary metal-oxide-semiconductor (CMOS)-like inverters is demonstrated. The n-type field effect transistors (FETs) based on I - capped PbS QDs (V th = 0.2 V, on/off = 10 5 , S S-th = 114 mV dec -1 , µ e = 0.22 cm 2 V -1 s -1 ) and the p-type FETs with tailored parameters based on low-density random network of SWCNTs (V th = -0.2 V, on/off > 10 5 , S S-th = 63 mV dec -1 , µ h = 0.04 cm 2 V -1 s -1 ) are integrated on the same substrate in order to obtain high-performance hybrid inverters. The inverters operate in the sub-1 V range (0.9 V) and have high gain (76 V/V), large maximum-equal-criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV). © 2017 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The study of dispersive 'b'-mode in monolayer MoS2 in temperature dependent resonant Raman scattering experiments

NASA Astrophysics Data System (ADS)

Kutrowska-Girzycka, Joanna; Jadczak, Joanna; Bryja, Leszek

2018-07-01

We report on resonant Raman scattering studies of monolayer MoS2 as a function of the excitation laser energy (1.959-2.033 eV) and temperature (T = 7-295 K). In complementary reflectivity contrast experiments we determined the temperature evolution of the A exciton and trion resonances. We focus our studies on the dispersive, second order 'b' mode related to the resonant two phonon Raman process of successive emissions of the acoustic LA and TA phonons at K points. We found that when excitation laser energy is tuned across the A exciton level this mode shifts almost linearly to lower frequency with the rate equal -83 and -71 cm-1/eV at T = 7 and 295 K, respectively, which is about two times higher rate than those reported in the previous studies of monolayer MoS2 but very close the relevant rate recorded for bulk MoS2. We interpret this effect as related to the difference of concentration of two dimensional electron gas. We also determined, using excitation with the He-Ne laser the temperature shifts of the Raman peaks of dispersive 'b' and dispersionless E‧ and A1‧ modes. We found that absolute value of the temperature coefficient of 'b' mode, equals 3.5 × 10-2 cm-1/K, is much higher than those of E‧ and A1‧ modes, equal 0.4 × 10-2 and 0.8 × 10-2 cm-1/K, respectively.

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

NASA Astrophysics Data System (ADS)

Davidson, Bradley Darren

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

640 X 480 MOS PtSi IR sensor

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1991-12-01

The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

Design of a 16 gray scales 320 × 240 pixels OLED-on-silicon driving circuit

NASA Astrophysics Data System (ADS)

Ran, Huang; Xiaohui, Wang; Wenbo, Wang; Huan, Du; Zhengsheng, Han

2009-01-01

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4 × 28.4 μm2 and the display area is 10.7 × 8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

PubMed Central

Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

2016-01-01

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

The Pr 2O 3/Si(0 0 1) interface studied by synchrotron radiation photo-electron spectroscopy

NASA Astrophysics Data System (ADS)

Schmeißer, D.; Müssig, H.-J.

2003-10-01

Pr 2O 3 is currently under consideration as a potential replacement for SiO 2 as the gate-dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. We studied the Pr 2O 3/Si(0 0 1) interface by a non-destructive depth profiling using synchrotron radiation photoelectron spectroscopy. Our data suggests that there is no silicide formation at the interface. Based on reported results, a chemical reactive interface exists, consisting of a mixed Si-Pr oxide such as (Pr 2O 3) x(SiO 2) 1- x, i.e. as a silicate phase with variable silicon content. This pseudo-binary alloy at the interface offers large flexibility toward successful integration of Pr 2O 3 into future CMOS technologies.

Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

PubMed Central

Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

2016-01-01

The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

An analog gamma correction scheme for high dynamic range CMOS logarithmic image sensors.

PubMed

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-12-15

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process.

The Multidimensional Integrated Intelligent Imaging project (MI-3)

NASA Astrophysics Data System (ADS)

Allinson, N.; Anaxagoras, T.; Aveyard, J.; Arvanitis, C.; Bates, R.; Blue, A.; Bohndiek, S.; Cabello, J.; Chen, L.; Chen, S.; Clark, A.; Clayton, C.; Cook, E.; Cossins, A.; Crooks, J.; El-Gomati, M.; Evans, P. M.; Faruqi, W.; French, M.; Gow, J.; Greenshaw, T.; Greig, T.; Guerrini, N.; Harris, E. J.; Henderson, R.; Holland, A.; Jeyasundra, G.; Karadaglic, D.; Konstantinidis, A.; Liang, H. X.; Maini, K. M. S.; McMullen, G.; Olivo, A.; O'Shea, V.; Osmond, J.; Ott, R. J.; Prydderch, M.; Qiang, L.; Riley, G.; Royle, G.; Segneri, G.; Speller, R.; Symonds-Tayler, J. R. N.; Triger, S.; Turchetta, R.; Venanzi, C.; Wells, K.; Zha, X.; Zin, H.

2009-06-01

MI-3 is a consortium of 11 universities and research laboratories whose mission is to develop complementary metal-oxide semiconductor (CMOS) active pixel sensors (APS) and to apply these sensors to a range of imaging challenges. A range of sensors has been developed: On-Pixel Intelligent CMOS (OPIC)—designed for in-pixel intelligence; FPN—designed to develop novel techniques for reducing fixed pattern noise; HDR—designed to develop novel techniques for increasing dynamic range; Vanilla/PEAPS—with digital and analogue modes and regions of interest, which has also been back-thinned; Large Area Sensor (LAS)—a novel, stitched LAS; and eLeNA—which develops a range of low noise pixels. Applications being developed include autoradiography, a gamma camera system, radiotherapy verification, tissue diffraction imaging, X-ray phase-contrast imaging, DNA sequencing and electron microscopy.

Subwavelength InSb-based Slot wavguides for THz transport: concept and practical implementations.

PubMed

Ma, Youqiao; Zhou, Jun; Pištora, Jaromír; Eldlio, Mohamed; Nguyen-Huu, Nghia; Maeda, Hiroshi; Wu, Qiang; Cada, Michael

2016-12-07

Seeking better surface plasmon polariton (SPP) waveguides is of critical importance to construct the frequency-agile terahertz (THz) front-end circuits. We propose and investigate here a new class of semiconductor-based slot plasmonic waveguides for subwavelength THz transport. Optimizations of the key geometrical parameters demonstrate its better guiding properties for simultaneous realization of long propagation lengths (up to several millimeters) and ultra-tight mode confinement (~λ 2 /530) in the THz spectral range. The feasibility of the waveguide for compact THz components is also studied to lay the foundations for its practical implementations. Importantly, the waveguide is compatible with the current complementary metal-oxide-semiconductor (CMOS) fabrication technique. We believe the proposed waveguide configuration could offer a potential for developing a CMOS plasmonic platform and can be designed into various components for future integrated THz circuits (ITCs).

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization.

PubMed

Tran, Duy Phu; Pham, Thuy Thi Thanh; Wolfrum, Bernhard; Offenhäusser, Andreas; Thierry, Benjamin

2018-05-11

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs' promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Real-time, continuous, fluorescence sensing in a freely-moving subject with an implanted hybrid VCSEL/CMOS biosensor

PubMed Central

O’Sullivan, Thomas D.; Heitz, Roxana T.; Parashurama, Natesh; Barkin, David B.; Wooley, Bruce A.; Gambhir, Sanjiv S.; Harris, James S.; Levi, Ofer

2013-01-01

Performance improvements in instrumentation for optical imaging have contributed greatly to molecular imaging in living subjects. In order to advance molecular imaging in freely moving, untethered subjects, we designed a miniature vertical-cavity surface-emitting laser (VCSEL)-based biosensor measuring 1cm3 and weighing 0.7g that accurately detects both fluorophore and tumor-targeted molecular probes in small animals. We integrated a critical enabling component, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit, which digitized the fluorescence signal to achieve autofluorescence-limited sensitivity. After surgical implantation of the lightweight sensor for two weeks, we obtained continuous and dynamic fluorophore measurements while the subject was un-anesthetized and mobile. The technology demonstrated here represents a critical step in the path toward untethered optical sensing using an integrated optoelectronic implant. PMID:24009996

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

PubMed Central

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-01-01

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Metal oxides for optoelectronic applications.

PubMed

Yu, Xinge; Marks, Tobin J; Facchetti, Antonio

2016-04-01

Metal oxides (MOs) are the most abundant materials in the Earth's crust and are ingredients in traditional ceramics. MO semiconductors are strikingly different from conventional inorganic semiconductors such as silicon and III-V compounds with respect to materials design concepts, electronic structure, charge transport mechanisms, defect states, thin-film processing and optoelectronic properties, thereby enabling both conventional and completely new functions. Recently, remarkable advances in MO semiconductors for electronics have been achieved, including the discovery and characterization of new transparent conducting oxides, realization of p-type along with traditional n-type MO semiconductors for transistors, p-n junctions and complementary circuits, formulations for printing MO electronics and, most importantly, commercialization of amorphous oxide semiconductors for flat panel displays. This Review surveys the uniqueness and universality of MOs versus other unconventional electronic materials in terms of materials chemistry and physics, electronic characteristics, thin-film fabrication strategies and selected applications in thin-film transistors, solar cells, diodes and memories.

Metal oxides for optoelectronic applications

NASA Astrophysics Data System (ADS)

Yu, Xinge; Marks, Tobin J.; Facchetti, Antonio

2016-04-01

Metal oxides (MOs) are the most abundant materials in the Earth's crust and are ingredients in traditional ceramics. MO semiconductors are strikingly different from conventional inorganic semiconductors such as silicon and III-V compounds with respect to materials design concepts, electronic structure, charge transport mechanisms, defect states, thin-film processing and optoelectronic properties, thereby enabling both conventional and completely new functions. Recently, remarkable advances in MO semiconductors for electronics have been achieved, including the discovery and characterization of new transparent conducting oxides, realization of p-type along with traditional n-type MO semiconductors for transistors, p-n junctions and complementary circuits, formulations for printing MO electronics and, most importantly, commercialization of amorphous oxide semiconductors for flat panel displays. This Review surveys the uniqueness and universality of MOs versus other unconventional electronic materials in terms of materials chemistry and physics, electronic characteristics, thin-film fabrication strategies and selected applications in thin-film transistors, solar cells, diodes and memories.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

A 5 nW Quasi-Linear CMOS Hot-Electron Injector for Self-Powered Monitoring of Biomechanical Strain Variations.

PubMed

Zhou, Liang; Abraham, Adam C; Tang, Simon Y; Chakrabartty, Shantanu

2016-12-01

Piezoelectricity-driven hot-electron injectors (p-HEI) are used for self-powered monitoring of mechanical activity in biomechanical implants and structures. Previously reported p-HEI devices operate by harvesting energy from a piezoelectric transducer to generate current and voltage references which are then used for initiating and controlling the process of hot-electron injection. As a result, the minimum energy required to activate the device is limited by the power requirements of the reference circuits. In this paper we present a p-HEI device that operates by directly exploiting the self-limiting capability of an energy transducer when driving the process of hot-electron injection in a pMOS floating-gate transistor. As a result, the p-HEI device can activate itself at input power levels less than 5 nW. Using a prototype fabricated in a 0.5- [Formula: see text] bulk CMOS process we validate the functionality of the proposed injector and show that for a fixed input power, its dynamics is quasi-linear with respect to time. The paper also presents measurement results using a cadaver phantom where the fabricated p-HEI device has been integrated with a piezoelectric transducer and is used for self-powered monitoring of mechanical activity.

Impact of time-dependent annealing on TiO2 films for CMOS application

NASA Astrophysics Data System (ADS)

Gyanan, Mondal, Sandip; Kumar, Arvind

2017-05-01

Post-deposition annealing (PDA) is the inherent part of sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. The annealing removes the oxygen vacancies and improves the structural order of dielectric films. The process also reduces the interface related defects and improves the interfacial properties. In this work, we have integrated the sol-gel spin-coating deposited high-κ TiO2 films in MOS. The films are fired at 400°C for the duration of 20, 40, 60 and 80 min. The thicknesses of the films were found to be of ˜ 30 nm using ellipsometry. The (Al/TiO2/p-Si) devices were examined with current-voltage (I-V) and capacitance-voltage (C-V) at room temperature to understand the influence of firing time. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. The accumulation capacitance (Cox), dielectric constant (κ) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25nm, respectively with a low leakage current density (1.09 × 10-6 A/cm2) fired for 80 min at +1 V.

PREFACE: The Second Conference on Microelectronics, Microsystems and Nanotechnology

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.; Papanikolaou, Nikos; Tsamis, Christos

2005-01-01

The Second Conference on Microelectronics, Microsystems and Nanotechnology took place at the National Centre for Scientific Research `Demokritos', in Athens, Greece, between 14 and 17 November 2004. The conference was organized by the Institute of Microelectronics (IMEL) with the aim to bring together scientists and engineers working in the above exciting fields in an interactive forum. The conference included 45 oral presentations with 9 invited papers and was attended by 146 participants from 16 countries. The topics covered were nanotechnologies, quantum devices, sensors, micro- and nano-systems, semiconductor devices, C-MOS fabrication and characterization techniques, new materials, and IC design. Quantum devices and nanostructured materials attracted considerable attention. Both theoretical and experimental studies of metallic and semiconducting quantum systems were presented, with emphasis on their applications in electronics, optoelectronics, and nanocrystal memory devices. Another exciting topic was the recent developments in biocompatible lithographic processes for applications in biosensors. In particular novel processes for bio-friendly lithography, together with innovations in Si sensors for applications in medicine and food industry were presented. Recent developments and perspectives in CMOS technology towards the ultimate limit were also discussed. The conference covered issues and concepts of IC design with two invited talks on RF design and cryptography.The conference included presentations from several companies active in the field of microelectronics and systems in Greece.

Phase partitioning, crystal growth, electrodeposition and cosmic ray experiments in microgravity

NASA Technical Reports Server (NTRS)

Wessling, Francis C.

1987-01-01

Five experiments are contained in one Get Away Special Canister (5 cu ft). The first utilizes microgravity to separate biological cells and to study the mechanism of phase partitioning in 12 separate cuvettes. Two experiments are designed to grow organic crystals by physical vapor transport. One experiment consists of eight electroplating cells with various chemicals to produce surfaces electroplated in microgravity. Some of the surfaces have micron sized particles of hard materials co-deposited during electrodeposition. The fifth experiment intercepts cosmic ray particles and records their paths on photographic emulsions. The first four experiments are controlled by an on-board C-MOS controller. The fifth experiment is totally passive. These are the first in Space. Their purpose is to create new commercial products with microgravity processing.

Ga:Ge array development

NASA Technical Reports Server (NTRS)

Young, Erick T.; Rieke, G. H.; Low, Frank J.; Haller, E. E.; Beeman, J. W.

1989-01-01

Work at the University of Arizona and at Lawrence Berkeley Laboratory on the development of a far infrared array camera for the Multiband Imaging Photometer on the Space Infrared Telescope Facility (SIRTF) is discussed. The camera design uses stacked linear arrays of Ge:Ga photoconductors to make a full two-dimensional array. Initial results from a 1 x 16 array using a thermally isolated J-FET readout are presented. Dark currents below 300 electrons s(exp -1) and readout noises of 60 electrons were attained. Operation of these types of detectors in an ionizing radiation environment are discussed. Results of radiation testing using both low energy gamma rays and protons are given. Work on advanced C-MOS cascode readouts that promise lower temperature operation and higher levels of performance than the current J-FET based devices is described.

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

NASA Technical Reports Server (NTRS)

1983-01-01

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

PubMed

Zhao, C; Vassiljev, N; Konstantinidis, A C; Speller, R D; Kanicki, J

2017-03-07

High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm -1 ) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

NASA Astrophysics Data System (ADS)

Zhao, C.; Vassiljev, N.; Konstantinidis, A. C.; Speller, R. D.; Kanicki, J.

2017-03-01

High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm-1) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Heterointegration of Dissimilar Materials

DTIC Science & Technology

2015-07-28

computing capabilities. This has been possible due to the aggressive scaling undertaken by the Si industry for complementary metal oxide semiconductor...current due to quantum mechanical tunneling. After years of research and development, Hf- based gate dielectric with metal gates is now being used in CMOS...the oxide in this study was 1ML or ~3.9 Å/ min. The native SiO2 was removed using a low temperature process involving the deposition of Sr metal

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

SRAM As An Array Of Energetic-Ion Detectors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Lieneweg, Udo; Nixon, Robert H.

1993-01-01

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

NASA Astrophysics Data System (ADS)

Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

2017-01-01

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

PubMed

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-10-16

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

Efficacy of lead foil for reducing doses in the head and neck: a simulation study using digital intraoral systems

PubMed Central

Silva, A I V; Brasil, D M; Vasconcelos, K F; Haiter Neto, F; Boscolo, F N

2015-01-01

Objectives: To assess the efficacy of lead foils in reducing the radiation dose received by different anatomical sites of the head and neck during periapical intraoral examinations performed with digital systems. Methods: Images were acquired through four different manners: phosphor plate (PSP; VistaScan® system; Dürr Dental GmbH, Bissingen, Germany) alone, PSP plus lead foil, complementary metal oxide semiconductor (CMOS; DIGORA® Toto, Soredex®, Tuusula, Finland) alone and CMOS plus lead foil. Radiation dose was measured after a full-mouth periapical series (14 radiographs) using the long-cone paralleling technique. Lithium fluoride (LiF 100) thermoluminescent dosemeters were placed in an anthropomorphic phantom at points corresponding to the tongue, thyroid, crystalline lenses, parotid glands and maxillary sinuses. Results: Dosemeter readings demonstrated the efficacy of the addition of lead foil in the intraoral digital X-ray systems provided in reducing organ doses in the selected structures, approximately 32% in the PSP system and 59% in the CMOS system. Conclusions: The use of lead foils associated with digital X-ray sensors is an effective alternative for the protection of different anatomical sites of the head and neck during full-mouth periapical series acquisition. PMID:26084474

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Single-silicon CCD-CMOS platform for multi-spectral detection from terahertz to x-rays.

PubMed

Shalaby, Mostafa; Vicario, Carlo; Hauri, Christoph P

2017-11-15

Charge-coupled devices (CCDs) are a well-established imaging technology in the visible and x-ray frequency ranges. However, the small quantum photon energies of terahertz radiation have hindered the use of this mature semiconductor technological platform in this frequency range, leaving terahertz imaging totally dependent on low-resolution bolometer technologies. Recently, it has been shown that silicon CCDs can detect terahertz photons at a high field, but the detection sensitivity is limited. Here we show that silicon, complementary metal-oxide-semiconductor (CMOS) technology offers enhanced detection sensitivity of almost two orders of magnitude, compared to CCDs. Our findings allow us to extend the low-frequency terahertz cutoff to less than 2 THz, nearly closing the technological gap with electronic imagers operating up to 1 THz. Furthermore, with the silicon CCD/CMOS technology being sensitive to mid-infrared (mid-IR) and the x-ray ranges, we introduce silicon as a single detector platform from 1 EHz to 2 THz. This overcomes the present challenge in spatially overlapping a terahertz/mid-IR pump and x-ray probe radiation at facilities such as free electron lasers, synchrotron, and laser-based x-ray sources.

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

PubMed

Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

2017-09-09

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

PubMed Central

Han, Seong-Tae; Baek, Donghyun

2017-01-01

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB. PMID:28891927

In vitro near-infrared imaging of occlusal dental caries using a germanium-enhanced CMOS camera

NASA Astrophysics Data System (ADS)

Lee, Chulsung; Darling, Cynthia L.; Fried, Daniel

2010-02-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310-nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study was to determine whether the lesion contrast derived from NIR transillumination can be used to estimate lesion severity. Another aim was to compare the performance of a new Ge enhanced complementary metal-oxide-semiconductor (CMOS) based NIR imaging camera with the InGaAs focal plane array (FPA). Extracted human teeth (n=52) with natural occlusal caries were imaged with both cameras at 1310-nm and the image contrast between sound and carious regions was calculated. After NIR imaging, teeth were sectioned and examined using more established methods, namely polarized light microscopy (PLM) and transverse microradiography (TMR) to calculate lesion severity. Lesions were then classified into 4 categories according to the lesion severity. Lesion contrast increased significantly with lesion severity for both cameras (p<0.05). The Ge enhanced CMOS camera equipped with the larger array and smaller pixels yielded higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

In vitro near-infrared imaging of occlusal dental caries using germanium enhanced CMOS camera.

PubMed

Lee, Chulsung; Darling, Cynthia L; Fried, Daniel

2010-03-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310-nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study was to determine whether the lesion contrast derived from NIR transillumination can be used to estimate lesion severity. Another aim was to compare the performance of a new Ge enhanced complementary metal-oxide-semiconductor (CMOS) based NIR imaging camera with the InGaAs focal plane array (FPA). Extracted human teeth (n=52) with natural occlusal caries were imaged with both cameras at 1310-nm and the image contrast between sound and carious regions was calculated. After NIR imaging, teeth were sectioned and examined using more established methods, namely polarized light microscopy (PLM) and transverse microradiography (TMR) to calculate lesion severity. Lesions were then classified into 4 categories according to the lesion severity. Lesion contrast increased significantly with lesion severity for both cameras (p<0.05). The Ge enhanced CMOS camera equipped with the larger array and smaller pixels yielded higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

Hyperspectral Image-Based Night-Time Vehicle Light Detection Using Spectral Normalization and Distance Mapper for Intelligent Headlight Control

PubMed Central

Kim, Heekang; Kwon, Soon; Kim, Sungho

2016-01-01

This paper proposes a vehicle light detection method using a hyperspectral camera instead of a Charge-Coupled Device (CCD) or Complementary metal-Oxide-Semiconductor (CMOS) camera for adaptive car headlamp control. To apply Intelligent Headlight Control (IHC), the vehicle headlights need to be detected. Headlights are comprised from a variety of lighting sources, such as Light Emitting Diodes (LEDs), High-intensity discharge (HID), and halogen lamps. In addition, rear lamps are made of LED and halogen lamp. This paper refers to the recent research in IHC. Some problems exist in the detection of headlights, such as erroneous detection of street lights or sign lights and the reflection plate of ego-car from CCD or CMOS images. To solve these problems, this study uses hyperspectral images because they have hundreds of bands and provide more information than a CCD or CMOS camera. Recent methods to detect headlights used the Spectral Angle Mapper (SAM), Spectral Correlation Mapper (SCM), and Euclidean Distance Mapper (EDM). The experimental results highlight the feasibility of the proposed method in three types of lights (LED, HID, and halogen). PMID:27399720

WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Q; Brehler, M; Sisniega, A

Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection)more » using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high-frequency imaging tasks through adoption of the CMOS detector and small FS x-ray source, motivating the use of these components in a new system for quantitative in-vivo imaging of trabecular bone. Financial Support: US NIH grant R01EB018896. Qian Cao is a Howard Hughes Medical Institute International Student Research Fellow. Disclosures: W Zbijewski, J Siewerdsen and A Sisniega receive research funding from Carestream Health.« less

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A novel CMOS image sensor system for quantitative loop-mediated isothermal amplification assays to detect food-borne pathogens.

PubMed

Wang, Tiantian; Kim, Sanghyo; An, Jeong Ho

2017-02-01

Loop-mediated isothermal amplification (LAMP) is considered as one of the alternatives to the conventional PCR and it is an inexpensive portable diagnostic system with minimal power consumption. The present work describes the application of LAMP in real-time photon detection and quantitative analysis of nucleic acids integrated with a disposable complementary-metal-oxide semiconductor (CMOS) image sensor. This novel system works as an amplification-coupled detection platform, relying on a CMOS image sensor, with the aid of a computerized circuitry controller for the temperature and light sources. The CMOS image sensor captures the light which is passing through the sensor surface and converts into digital units using an analog-to-digital converter (ADC). This new system monitors the real-time photon variation, caused by the color changes during amplification. Escherichia coli O157 was used as a proof-of-concept target for quantitative analysis, and compared with the results for Staphylococcus aureus and Salmonella enterica to confirm the efficiency of the system. The system detected various DNA concentrations of E. coli O157 in a short time (45min), with a detection limit of 10fg/μL. The low-cost, simple, and compact design, with low power consumption, represents a significant advance in the development of a portable, sensitive, user-friendly, real-time, and quantitative analytic tools for point-of-care diagnosis. Copyright © 2016 Elsevier B.V. All rights reserved.

Homogeneous 2D MoTe2 p-n Junctions and CMOS Inverters formed by Atomic-Layer-Deposition-Induced Doping.

PubMed

Lim, June Yeong; Pezeshki, Atiye; Oh, Sehoon; Kim, Jin Sung; Lee, Young Tack; Yu, Sanghyuck; Hwang, Do Kyung; Lee, Gwan-Hyoung; Choi, Hyoung Joon; Im, Seongil

2017-08-01

Recently, α-MoTe 2 , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe 2 a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe 2 appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe 2 , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe 2 nanosheet by a straightforward selective doping technique. In a single α-MoTe 2 flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm 2 V -1 s -1 by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe 2 for future electronic devices based on 2D semiconducting materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

PubMed

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-01

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro-mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm. PMID:25594598

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

PubMed Central

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-01-01

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

PubMed

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-10-27

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

PubMed Central

Wolfrum, Bernhard; Thierry, Benjamin

2018-01-01

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs’ promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology. PMID:29751688

Millimeter wave complementary metal-oxide-semiconductor on-chip hexagonal nano-ferrite circulator

NASA Astrophysics Data System (ADS)

Chao, Liu; Oukacha, Hassan; Fu, Enjin; Koomson, Valencia Joyner; Afsar, Mohammed N.

2015-05-01

Hexagonal ferrites such as M-type BaFe12O19 and SrFe12O19 have strong uniaxial anisotropic magnetic field and remanent magnetism. The nano-sized ferrite powder exhibits high compatibility and processability in composite material. New magnetic devices using the M-type ferrite materials can work in the tens of GHz frequency range from microwave to millimeter wave without the application of strong external magnetic field. The micro- and nano-sized hexagonal ferrite can be conveniently utilized to fabricate magnetic components integrated in CMOS integrated circuits as thin as several micrometers. The micro-fabrication method of such nano ferrite device is presented in this paper. A circulator working at 60 GHz is designed and integrated into the commercial CMOS process. The circulator exhibits distinct circulation properties in the frequency range from 56 GHz to 58 GHz.

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Ethanol microsensors with a readout circuit manufactured using the CMOS-MEMS technique.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang

2015-01-14

The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS)-microelectro -mechanical system (MEMS) technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

NASA Technical Reports Server (NTRS)

Ohara, Tetsuo

2012-01-01

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

Split Bull's eye shaped aluminum antenna for plasmon-enhanced nanometer scale germanium photodetector.

PubMed

Ren, Fang-Fang; Ang, Kah-Wee; Ye, Jiandong; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

2011-03-09

Bull's eye antennas are capable of efficiently collecting and concentrating optical signals into an ultrasmall area, offering an excellent solution to break the bottleneck between speed and photoresponse in subwavelength photodetectors. Here, we exploit the idea of split bull's eye antenna for a nanometer germanium photodetector operating at a standard communication wavelength of 1310 nm. The nontraditional plasmonic metal aluminum has been implemented in the resonant antenna structure fabricated by standard complementary metal-oxide-semiconductor (CMOS) processing. A significant enhancement in photoresponse could be achieved over the conventional bull's eye scheme due to an increased optical near-field in the active region. Moreover, with this novel antenna design the effective grating area could be significantly reduced without sacrificing device performance. This work paves the way for the future development of low-cost, high-density, and high-speed CMOS-compatible germanium-based optoelectronic devices.

Mechanical Computing Redux: Limitations at the Nanoscale

NASA Astrophysics Data System (ADS)

Liu, Tsu-Jae King

2014-03-01

Technology solutions for overcoming the energy efficiency limits of nanoscale complementary metal oxide semiconductor (CMOS) technology ultimately will be needed in order to address the growing issue of integrated-circuit chip power density. Off-state leakage current sets a fundamental lower limit in energy per operation for any voltage-level-based digital logic implemented with transistors (CMOS and beyond), which leads to practical limits for device density (i.e. cost) and operating frequency (i.e. system performance). Mechanical switches have zero off-state leakag and hence can overcome this fundamental limit. Contact adhesive force sets a lower limit for the switching energy of a mechanical switch, however, and also directly impacts its performance. This paper will review recent progress toward the development of nano-electro-mechanical relay technology and discuss remaining challenges for realizing the promise of mechanical computing for ultra-low-power computing. Supported by the Center for Energy Efficient Electronics Science (NSF Award 0939514).

Argon–germane in situ plasma clean for reduced temperature Ge on Si epitaxy by high density plasma chemical vapor deposition

DOE PAGES

Douglas, Erica A.; Sheng, Josephine J.; Verley, Jason C.; ...

2015-06-04

We found that the demand for integration of near infrared optoelectronic functionality with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature germanium on silicon deposition processes. Our work describes the development of a high density plasma chemical vapor deposition process that uses a low temperature (<460 °C) in situ germane/argon plasma surface preparation step for epitaxial growth of germanium on silicon. It is shown that the germane/argon plasma treatment sufficiently removes SiO x and carbon at the surface to enable germanium epitaxy. Finally, the use of this surface preparation step demonstratesmore » an alternative way to produce germanium epitaxy at reduced temperatures, a key enabler for increased flexibility of integration with CMOS back-end-of-line fabrication.« less

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-07-17

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

PubMed

Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

PubMed Central

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

2015-01-01

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

Detection systems for mass spectrometry imaging: a perspective on novel developments with a focus on active pixel detectors.

PubMed

Jungmann, Julia H; Heeren, Ron M A

2013-01-15

Instrumental developments for imaging and individual particle detection for biomolecular mass spectrometry (imaging) and fundamental atomic and molecular physics studies are reviewed. Ion-counting detectors, array detection systems and high mass detectors for mass spectrometry (imaging) are treated. State-of-the-art detection systems for multi-dimensional ion, electron and photon detection are highlighted. Their application and performance in three different imaging modes--integrated, selected and spectral image detection--are described. Electro-optical and microchannel-plate-based systems are contrasted. The analytical capabilities of solid-state pixel detectors--both charge coupled device (CCD) and complementary metal oxide semiconductor (CMOS) chips--are introduced. The Medipix/Timepix detector family is described as an example of a CMOS hybrid active pixel sensor. Alternative imaging methods for particle detection and their potential for future applications are investigated. Copyright © 2012 John Wiley & Sons, Ltd.

CMOS capacitive biosensors for highly sensitive biosensing applications.

PubMed

Chang, An-Yu; Lu, Michael S-C

2013-01-01

Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

NASA Astrophysics Data System (ADS)

Aloulou, R.; De Peslouan, P.-O. Lucas; Mnif, H.; Alicalapa, F.; Luk, J. D. Lan Sun; Loulou, M.

2016-05-01

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.

Antimicrobial Properties of 2D MnO2 and MoS2 Nanomaterials Vertically Aligned on Graphene Materials and Ti3C2 MXene.

PubMed

Alimohammadi, Farbod; Sharifian Gh, Mohammad; Attanayake, Nuwan H; Thenuwara, Akila C; Gogotsi, Yury; Anasori, Babak; Strongin, Daniel R

2018-06-07

Two-dimensional (2D) nanomaterials have attracted considerable attention in biomedical and environmental applications due to their antimicrobial activity. In the interest of investigating the primary antimicrobial mode-of-action of 2D nanomaterials, we studied the antimicrobial properties of MnO 2 and MoS 2 , toward Gram-positive and Gram-negative bacteria. Bacillus subtilis and Escherichia coli bacteria were treated individually with 100 μg/mL of randomly oriented and vertically aligned nanomaterials for ∼3 h in the dark. The vertically aligned 2D MnO 2 and MoS 2 were grown on 2D sheets of graphene oxide, reduced graphene oxide, and Ti 3 C 2 MXene. Measurements to determine the viability of bacteria in the presence of the 2D nanomaterials performed by using two complementary techniques, flow cytometry, and fluorescence imaging showed that, while MnO 2 and MoS 2 nanosheets show different antibacterial activities, in both cases, Gram-positive bacteria show a higher loss in membrane integrity. Scanning electron microscopy images suggest that the 2D nanomaterials, which have a detrimental effect on bacteria viability, compromise the cell wall, leading to significant morphological changes. We propose that the peptidoglycan mesh (PM) in the bacterial wall is likely the primary target of the 2D nanomaterials. Vertically aligned 2D MnO 2 nanosheets showed the highest antimicrobial activity, suggesting that the edges of the nanosheets were likely compromising the cell walls upon contact.

A comparison of imaging methods for use in an array biosensor

NASA Technical Reports Server (NTRS)

Golden, Joel P.; Ligler, Frances S.

2002-01-01

An array biosensor has been developed which uses an actively-cooled, charge-coupled device (CCD) imager. In an effort to save money and space, a complementary metal-oxide semiconductor (CMOS) camera and photodiode were tested as replacements for the cooled CCD imager. Different concentrations of CY5 fluorescent dye in glycerol were imaged using the three different detection systems with the same imaging optics. Signal discrimination above noise was compared for each of the three systems.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

Design of ultra-low power biopotential amplifiers for biosignal acquisition applications.

PubMed

Zhang, Fan; Holleman, Jeremy; Otis, Brian P

2012-08-01

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

NASA Astrophysics Data System (ADS)

Greene, Andrew M.

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1,500 and sub-threshold swing = 340 mV/dec. Split C-V measurements were used to extract an effective channel mobility of muh* = 300 cm2/Vs at Ns = 2 x 1012 cm -2. "Gate-last" MOSFETs grown with an epitaxial p + contact layer were fabricated using selective gate-recess etching techniques. A parasitic "n-channel" limited ION/I OFF ratio and sub-threshold swing, most likely due to effects from the InAs surface layer.

Nanocharacterization Challenges in a Changing Microelectronics Landscape

NASA Astrophysics Data System (ADS)

Brilloüt, Michel

2011-11-01

As the microelectronics industry enters the "nano"-era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling "Moore's law". New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate-all-around nanowire structures. Due to the escalating cost and complexity of sub-28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non-digital technologies (the so-called "More-than-Moore" domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

Heavy ion induced Single Event Phenomena (SEP) data for semiconductor devices from engineering testing

NASA Technical Reports Server (NTRS)

Nichols, Donald K.; Huebner, Mark A.; Price, William E.; Smith, L. S.; Coss, James R.

1988-01-01

The accumulation of JPL data on Single Event Phenomena (SEP), from 1979 to August 1986, is presented in full report format. It is expected that every two years a supplement report will be issued for the follow-on period. This data for 135 devices expands on the abbreviated test data presented as part of Refs. (1) and (3) by including figures of Single Event Upset (SEU) cross sections as a function of beam Linear Energy Transfer (LET) when available. It also includes some of the data complied in the JPL computer in RADATA and the SPACERAD data bank. This volume encompasses bipolar and MOS (CMOS and MHNOS) device data as two broad categories for both upsets (bit-flips) and latchup. It also includes comments on less well known phenomena, such as transient upsets and permanent damage modes.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

PubMed

Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

PubMed Central

Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. PMID:24723808

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

2012-06-01

Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

Silicon-nanocrystal Optoelectronic Kerr Effect for Complementary Metal-oxide Semiconductor (CMOS) Compatible Optical Switching

DTIC Science & Technology

2011-04-01

changes the material’s index of refraction via dispersion . This absorption requires carrier transport and, in present implementations, suffers from slow...designed to take advantage of the large Kerr effect that has been reported in Si-nanocrystals imbedded in oxide (Si-nc). The expected refractive index ...estimate of the expected refractive index change versus applied voltage. An index change of ~2 x 10–4 is enough to modulate the light, corresponding to a

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Technology modules from micro- and nano-electronics for the life sciences.

PubMed

Birkholz, M; Mai, A; Wenger, C; Meliani, C; Scholz, R

2016-05-01

The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website. © 2015 Wiley Periodicals, Inc.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors.

PubMed

Ge, Xiaoliang; Theuwissen, Albert J P

2018-02-27

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip.

PubMed

Huys, Roeland; Braeken, Dries; Jans, Danny; Stassen, Andim; Collaert, Nadine; Wouters, Jan; Loo, Josine; Severi, Simone; Vleugels, Frank; Callewaert, Geert; Verstreken, Kris; Bartic, Carmen; Eberle, Wolfgang

2012-04-07

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks. This journal is © The Royal Society of Chemistry 2012

Microelectrode array-induced neuronal alignment directs neurite outgrowth: analysis using a fast Fourier transform (FFT).

PubMed

Radotić, Viktorija; Braeken, Dries; Kovačić, Damir

2017-12-01

Many studies have shown that the topography of the substrate on which neurons are cultured can promote neuronal adhesion and guide neurite outgrowth in the same direction as the underlying topography. To investigate this effect, isotropic substrate-complementary metal-oxide-semiconductor (CMOS) chips were used as one example of microelectrode arrays (MEAs) for directing neurite growth of spiral ganglion neurons. Neurons were isolated from 5 to 7-day-old rat pups, cultured 1 day in vitro (DIV) and 4 DIV, and then fixed with 4% paraformaldehyde. For analysis of neurite alignment and orientation, fast Fourier transformation (FFT) was used. Results revealed that on the micro-patterned surface of a CMOS chip, neurons orient their neurites along three directional axes at 30, 90, and 150° and that neurites aligned in straight lines between adjacent pillars and mostly followed a single direction while occasionally branching perpendicularly. We conclude that the CMOS substrate guides neurites towards electrodes by means of their structured pillar organization and can produce electrical stimulation of aligned neurons as well as monitoring their neural activities once neurites are in the vicinity of electrodes. These findings are of particular interest for neural tissue engineering with the ultimate goal of developing a new generation of MEA essential for improved electrical stimulation of auditory neurons.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors †

PubMed Central

Theuwissen, Albert J. P.

2018-01-01

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models. PMID:29495496

Using Polynomials to Simplify Fixed Pattern Noise and Photometric Correction of Logarithmic CMOS Image Sensors

PubMed Central

Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

2015-01-01

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. PMID:26501287

A wireless narrowband imaging chip for capsule endoscope.

PubMed

Lan-Rong Dung; Yin-Yi Wu

2010-12-01

This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now. The narrowband image acquisition and power dissipation reduction are the main challenges of NBI capsule endoscope. In this paper, we present the first narrowband imaging capsule endoscope that can assist clinical doctors to effectively diagnose early gastrointestinal cancers, profited from our dedicated dual-mode complementary metal-oxide semiconductor (CMOS) sensor. The dedicated dual-mode CMOS sensor can offer white-light and narrowband images. Implementation results show that the proposed 512 × 512 CMOS sensor consumes only 2 mA at a 3-V power supply. The average current of the NBI capsule with an 8-Mb/s RF transmitter is nearly 7 ~ 8 mA that can continuously work for 6 ~ 8 h with two 1.5-V 80-mAh button batteries while the frame rate is 2 fps. Experimental results on backside mucosa of a human tongue and pig's small intestine showed that the wireless NBI capsule endoscope can significantly improve the image quality, compared with a commercial-of-the-shelf capsule endoscope for gastrointestinal tract diagnosis.

Direct determination of the local Hamaker constant of inorganic surfaces based on scanning force microscopy

NASA Astrophysics Data System (ADS)

Krajina, Brad A.; Kocherlakota, Lakshmi S.; Overney, René M.

2014-10-01

The energetics involved in the bonding fluctuations between nanometer-sized silicon dioxide (SiO2) probes and highly oriented pyrolytic graphite (HOPG) and molybdenum disulfide (MoS2) could be quantified directly and locally on the submicron scale via a time-temperature superposition analysis of the lateral forces between scanning force microscopy silicon dioxide probes and inorganic sample surfaces. The so-called "intrinsic friction analysis" (IFA) provided direct access to the Hamaker constants for HOPG and MoS2, as well as the control sample, calcium fluoride (CaF2). The use of scanning probe enables nanoscopic analysis of bonding fluctuations, thereby overcoming challenges associated with larger scale inhomogeneity and surface roughness common to conventional techniques used to determine surface free energies and dielectric properties. A complementary numerical analysis based on optical and electron energy loss spectroscopy and the Lifshitz quantum electrodynamic theory of van der Waals interactions is provided and confirms quantitatively the IFA results.

Direct determination of the local Hamaker constant of inorganic surfaces based on scanning force microscopy.

PubMed

Krajina, Brad A; Kocherlakota, Lakshmi S; Overney, René M

2014-10-28

The energetics involved in the bonding fluctuations between nanometer-sized silicon dioxide (SiO2) probes and highly oriented pyrolytic graphite (HOPG) and molybdenum disulfide (MoS2) could be quantified directly and locally on the submicron scale via a time-temperature superposition analysis of the lateral forces between scanning force microscopy silicon dioxide probes and inorganic sample surfaces. The so-called "intrinsic friction analysis" (IFA) provided direct access to the Hamaker constants for HOPG and MoS2, as well as the control sample, calcium fluoride (CaF2). The use of scanning probe enables nanoscopic analysis of bonding fluctuations, thereby overcoming challenges associated with larger scale inhomogeneity and surface roughness common to conventional techniques used to determine surface free energies and dielectric properties. A complementary numerical analysis based on optical and electron energy loss spectroscopy and the Lifshitz quantum electrodynamic theory of van der Waals interactions is provided and confirms quantitatively the IFA results.

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

NASA Astrophysics Data System (ADS)

Yoon, Bongno; Sung, Man Young; Yeon, Sujin; Oh, Hyun S.; Kwon, Yoonjoo; Kim, Chuljin; Kim, Kyung-Ho

2009-03-01

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag's persistence times (Tpt) for each session (S0-S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

PubMed

Oh, Sungjin; Ahn, Jae-Hyun; Lee, Sangmin; Ko, Hyoungho; Seo, Jong Mo; Goo, Yong-Sook; Cho, Dong-il Dan

2015-01-01

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 μm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 μ m × 55 μm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 μA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

Multichannel lens-free CMOS sensors for real-time monitoring of cell growth.

PubMed

Chang, Ko-Tung; Chang, Yu-Jen; Chen, Chia-Ling; Wang, Yao-Nan

2015-02-01

A low-cost platform is proposed for the growth and real-time monitoring of biological cells. The main components of the platform include a PMMA cell culture microchip and a multichannel lens-free CMOS (complementary metal-oxide-semiconductor) / LED imaging system. The PMMA microchip comprises a three-layer structure and is fabricated using a low-cost CO2 laser ablation technique. The CMOS / LED monitoring system is controlled using a self-written LabVIEW program. The platform has overall dimensions of just 130 × 104 × 115 mm(3) and can therefore be placed within a commercial incubator. The feasibility of the proposed system is demonstrated using HepG2 cancer cell samples with concentrations of 5000, 10 000, 20 000, and 40 000 cells/mL. In addition, cell cytotoxicity tests are performed using 8, 16, and 32 mM cyclophosphamide. For all of the experiments, the cell growth is observed over a period of 48 h. The cell growth rate is found to vary in the range of 44∼52% under normal conditions and from 17.4∼34.5% under cyclophosphamide-treated conditions. In general, the results confirm the long-term cell growth and real-time monitoring ability of the proposed system. Moreover, the magnification provided by the lens-free CMOS / LED observation system is around 40× that provided by a traditional microscope. Consequently, the proposed system has significant potential for long-term cell proliferation and cytotoxicity evaluation investigations. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Design rules for quantum imaging devices: experimental progress using CMOS single-photon detectors

NASA Astrophysics Data System (ADS)

Charbon, Edoardo; Gunther, Neil J.; Boiko, Dmitri L.; Beretta, Giordano B.

2006-08-01

We continue our previous program1 where we introduced a set of quantum-based design rules directed at quantum engineers who design single-photon quantum communications and quantum imaging devices. Here, we report on experimental progress using SPAD (single photon avalanche diode) arrays of our design and fabricated in CMOS (complementary metal oxide semiconductor) technology. Emerging high-resolution imaging techniques based on SPAD arrays have proven useful in a variety of disciplines including bio-fluorescence microscopy and 3D vision systems. They have also been particularly successful for intra-chip optical communications implemented entirely in CMOS technology. More importantly for our purposes, a very low dark count allows SPADs to detect rare photon events with a high dynamic range and high signal-to-noise ratio. Our CMOS SPADs support multi-channel detection of photon arrivals with picosecond accuracy, several million times per second, due to a very short detection cycle. The tiny chip area means they are suitable for highly miniaturized quantum imaging devices and that is how we employ them in this paper. Our quantum path integral analysis of the Young-Afshar-Wheeler interferometer showed that Bohr's complementarity principle was not violated due the previously overlooked effect of photon bifurcation within the lens--a phenomenon consistent with our quantum design rules--which accounts for the loss of which-path information in the presence of interference. In this paper, we report on our progress toward the construction of quantitative design rules as well as some proposed tests for quantum imaging devices using entangled photon sources with our SPAD imager.

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization.

PubMed

Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C; Patel, Tushita

2015-11-01

Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50-300 e-) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). In this study, imaging performance of a large area (29×23 cm2) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165-400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. The LFW mode shows better DQE at low air kerma (Ka<10 μGy) and should be used for DBT. At current DBT applications, air kerma (Ka∼10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165-400 μm in size can be resolved using a MGD range of 0.3-1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for microcalcifications was observed using the Dexela 2923 MAM CMOS APS x-ray imager at a lower MGD (2.0 mGy). The Dexela 2923 MAM CMOS APS x-ray imager is capable to achieve a high imaging performance at spatial frequencies up to 6.7 lp/mm. Microcalcifications of 165 μm are distinguishable based on reported data and their modeling results due to the small pixel pitch of 75 μm. At the same time, potential dose reduction is expected using the studied CMOS APS x-ray imager.

Ammonia gas sensors based on poly (3-hexylthiophene)-molybdenum disulfide film transistors.

PubMed

Xie, Tao; Xie, Guangzhong; Su, Yuanjie; Hongfei, Du; Ye, Zongbiao; Jiang, Yadong

2016-02-12

In this work, in order to enhance the recovery performance of organic thin film transistors (OTFTs) ammonia (NH3) sensors, poly (3-hexylthiophene) (P3HT) and molybdenum disulfide (MoS2) were combined as sensitive materials. Different sensitive film structures as active layers of OTFTs, i.e., P3HT-MoS2 composite film, P3HT/MoS2 bilayer film and MoS2/P3HT bilayer film were fabricated by spray technology. OTFT gas sensors based on P3HT-MoS2 composite film showed a shorter recovery time than others when the ammonia concentration changed from 4 to 20 ppm. Specifically, x-ray diffraction (XRD), Raman and UV-visible absorption were employed to explore the interface properties between P3HT and single-layer MoS2. Through the complementary characterization, a mechanism based on charge transfer is proposed to explain the physical originality of these OTFT gas sensors: closer interlayer d-spacing and better π-π stacking of the P3HT chains in composite film have ensured a short recovery time of OTFT gas sensors. Moreover, sensing mechanisms of OTFTs were further studied by comparing the device performance in the presence of nitrogen or dry air as a carrier gas. This work not only strengthens the fundamental understanding of the sensing mechanism, but provides a promising approach to optimizing the OTFT gas sensors.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Ageing and proton irradiation damage of a low voltage EMCCD in a CMOS process

NASA Astrophysics Data System (ADS)

Dunford, A.; Stefanov, K.; Holland, A.

2018-02-01

Electron Multiplying Charge Coupled Devices (EMCCDs) have revolutionised low light level imaging, providing highly sensitive detection capabilities. Implementing Electron Multiplication (EM) in Charge Coupled Devices (CCDs) can increase the Signal to Noise Ratio (SNR) and lead to further developments in low light level applications such as improvements in image contrast and single photon imaging. Demand has grown for EMCCD devices with properties traditionally restricted to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, such as lower power consumption and higher radiation tolerance. However, EMCCDs are known to experience an ageing effect, such that the gain gradually decreases with time. This paper presents results detailing EM ageing in an Electron Multiplying Complementary Metal-Oxide-Semiconductor (EMCMOS) device and its effect on several device characteristics such as Charge Transfer Inefficiency (CTI) and thermal dark signal. When operated at room temperature an average decrease in gain of over 20% after an operational period of 175 hours was detected. With many image sensors deployed in harsh radiation environments, the radiation hardness of the device following proton irradiation was also tested. This paper presents the results of a proton irradiation completed at the Paul Scherrer Institut (PSI) at a 10 MeV equivalent fluence of 4.15× 1010 protons/cm2. The pre-irradiation characterisation, irradiation methodology and post-irradiation results are detailed, demonstrating an increase in dark current and a decrease in its activation energy. Finally, this paper presents a comparison of the damage caused by EM gain ageing and proton irradiation.

Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

PubMed

Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

2015-07-16

We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.