Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Modeling of short channel MOS transistors

NASA Technical Reports Server (NTRS)

Lin, H. C.; Kokalis, D. P.; Bandy, W. R.

1976-01-01

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Energetic distributions of interface states Dit(phi sub s) of MOS transistors in extension of Kuhn's quasistatic C(V)-method

NASA Astrophysics Data System (ADS)

Krautschneider, W.; Wagemann, H. G.

1983-10-01

Kuhn's quasi-static C(V)-method has been extended to MOS transistors by considering the capacitances of the source and drain p-n junctions additionally to the MOS varactor circuit model. The width of the space charge layers w(phi sub s) is calculated as a function of the surface potential phi sub s and applied to the MOS capacitance as a function of the gate voltage. Capacitance behavior for different channel length is presented as a model and compared to measurement results and evaluations of energetic distributions of interface states Dit(phi sub s) for MOS transistor and MOS varactor on the same chip.

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

NASA Astrophysics Data System (ADS)

Gentil, P.; Mounib, A.

1981-05-01

Flicker noise in MOS transistors can be evaluated by measuring the spectrum SID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of {S I D}/{Sve} are in good agreement with gm2 by considering a model of the transconductance gm which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Transistors and tunnel diodes enabled by large-scale MoS2 nanosheets grown on GaN

NASA Astrophysics Data System (ADS)

San Yip, Pak; Zou, Xinbo; Cho, Wai Ching; Wu, Kam Lam; Lau, Kei May

2017-07-01

We report growth, fabrication, and device results of MoS2-based transistors and diodes implemented on a single 2D/3D material platform. The 2D/3D platform consists of a large-area MoS2 thin film grown on SiO2/p-GaN substrates. Atomic force microscopy, scanning electron microscopy, and Raman spectroscopy were used to characterize the thickness and quality of the as-grown MoS2 film, showing that the large-area MoS2 nanosheet has a smooth surface morphology constituted by small grains. Starting from the same material, both top-gated MoS2 field effect transistors and MoS2/SiO2/p-GaN heterojunction diodes were fabricated. The transistors exhibited a high on/off ratio of 105, a subthreshold swing of 74 mV dec-1, field effect mobility of 0.17 cm2 V-1 s-1, and distinctive current saturation characteristics. For the heterojunction diodes, current-rectifying characteristics were demonstrated with on-state current density of 29 A cm-2 and a current blocking property up to -25 V without breakdown. The reported transistors and diodes enabled by the same 2D/3D material stack present promising building blocks for constructing future nanoscale electronics.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

High-temperature performance of MoS2 thin-film transistors: Direct current and pulse current-voltage characteristics

NASA Astrophysics Data System (ADS)

Jiang, C.; Rumyantsev, S. L.; Samnakay, R.; Shur, M. S.; Balandin, A. A.

2015-02-01

We report on fabrication of MoS2 thin-film transistors (TFTs) and experimental investigations of their high-temperature current-voltage characteristics. The measurements show that MoS2 devices remain functional to temperatures of at least as high as 500 K. The temperature increase results in decreased threshold voltage and mobility. The comparison of the direct current (DC) and pulse measurements shows that the direct current sub-linear and super-linear output characteristics of MoS2 thin-films devices result from the Joule heating and the interplay of the threshold voltage and mobility temperature dependences. At temperatures above 450 K, a kink in the drain current occurs at zero gate voltage irrespective of the threshold voltage value. This intriguing phenomenon, referred to as a "memory step," was attributed to the slow relaxation processes in thin films similar to those in graphene and electron glasses. The fabricated MoS2 thin-film transistors demonstrated stable operation after two months of aging. The obtained results suggest new applications for MoS2 thin-film transistors in extreme-temperature electronics and sensors.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

A Novel SPM Probe with MOS Transistor and Nano Tip for Surface Electric Properties

NASA Astrophysics Data System (ADS)

Lee, Sang H.; Lim, Geunbae; Moon, Wonkyu

2007-03-01

In this paper, the novel SPM (Scanning Probe Microscope) probe with the planar MOS (Metal-Oxide-Semiconductor) transistor and the FIB (Focused Ion Beam) nano tip is fabricated for the surface electric properties. Since the MOS transistor has high working frequency, the device can overcome the speed limitation of EFM (Electrostatic Force Microscope) system. The sensitivity is also high, and no bulky device such as lock-in-amplifier is required. Moreover, the nano tip with nanometer scale tip radius is fabricated with FIB system, and the resolution can be improved. Therefore, the probe can rapidly detect small localized electric properties with high sensitivity and high resolution. The MOS transistor is fabricated with the common semiconductor process, and the nano tip is grown by the FIB system. The planar structure of the MOS transistor makes the fabrication process easier, which is the advantage on the commercial production. Various electric signals are applied using the function generator, and the measured data represent the well-established electric properties of the device. It shows the promising aspect of the local surface electric property detection with high sensitivity and high resolution.

Ammonia gas sensors based on poly (3-hexylthiophene)-molybdenum disulfide film transistors.

PubMed

Xie, Tao; Xie, Guangzhong; Su, Yuanjie; Hongfei, Du; Ye, Zongbiao; Jiang, Yadong

2016-02-12

In this work, in order to enhance the recovery performance of organic thin film transistors (OTFTs) ammonia (NH3) sensors, poly (3-hexylthiophene) (P3HT) and molybdenum disulfide (MoS2) were combined as sensitive materials. Different sensitive film structures as active layers of OTFTs, i.e., P3HT-MoS2 composite film, P3HT/MoS2 bilayer film and MoS2/P3HT bilayer film were fabricated by spray technology. OTFT gas sensors based on P3HT-MoS2 composite film showed a shorter recovery time than others when the ammonia concentration changed from 4 to 20 ppm. Specifically, x-ray diffraction (XRD), Raman and UV-visible absorption were employed to explore the interface properties between P3HT and single-layer MoS2. Through the complementary characterization, a mechanism based on charge transfer is proposed to explain the physical originality of these OTFT gas sensors: closer interlayer d-spacing and better π-π stacking of the P3HT chains in composite film have ensured a short recovery time of OTFT gas sensors. Moreover, sensing mechanisms of OTFTs were further studied by comparing the device performance in the presence of nitrogen or dry air as a carrier gas. This work not only strengthens the fundamental understanding of the sensing mechanism, but provides a promising approach to optimizing the OTFT gas sensors.

Electric-field-controlled ferromagnetism in high-Curie-temperature Mn0.05Ge0.95 quantum dots.

PubMed

Xiu, Faxian; Wang, Yong; Kim, Jiyoung; Hong, Augustin; Tang, Jianshi; Jacob, Ajey P; Zou, Jin; Wang, Kang L

2010-04-01

Electric-field manipulation of ferromagnetism has the potential for developing a new generation of electric devices to resolve the power consumption and variability issues in today's microelectronics industry. Among various dilute magnetic semiconductors (DMSs), group IV elements such as Si and Ge are the ideal material candidates because of their excellent compatibility with the conventional complementary metal-oxide-semiconductor (MOS) technology. Here we report, for the first time, the successful synthesis of self-assembled dilute magnetic Mn(0.05)Ge(0.95) quantum dots with ferromagnetic order above room temperature, and the demonstration of electric-field control of ferromagnetism in MOS ferromagnetic capacitors up to 100 K. We found that by applying electric fields to a MOS gate structure, the ferromagnetism of the channel layer can be effectively modulated through the change of hole concentration inside the quantum dots. Our results are fundamentally important in the understanding and to the realization of high-efficiency Ge-based spin field-effect transistors.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

Improving the Stability of High-Performance Multilayer MoS2 Field-Effect Transistors.

PubMed

Liu, Na; Baek, Jongyeol; Kim, Seung Min; Hong, Seongin; Hong, Young Ki; Kim, Yang Soo; Kim, Hyun-Suk; Kim, Sunkook; Park, Jozeph

2017-12-13

In this study, we propose a method for improving the stability of multilayer MoS 2 field-effect transistors (FETs) by O 2 plasma treatment and Al 2 O 3 passivation while sustaining the high performance of bulk MoS 2 FET. The MoS 2 FETs were exposed to O 2 plasma for 30 s before Al 2 O 3 encapsulation to achieve a relatively small hysteresis and high electrical performance. A MoO x layer formed during the plasma treatment was found between MoS 2 and the top passivation layer. The MoO x interlayer prevents the generation of excess electron carriers in the channel, owing to Al 2 O 3 passivation, thereby minimizing the shift in the threshold voltage (V th ) and increase of the off-current leakage. However, prolonged exposure of the MoS 2 surface to O 2 plasma (90 and 120 s) was found to introduce excess oxygen into the MoO x interlayer, leading to more pronounced hysteresis and a high off-current. The stable MoS 2 FETs were also subjected to gate-bias stress tests under different conditions. The MoS 2 transistors exhibited negligible decline in performance under positive bias stress, positive bias illumination stress, and negative bias stress, but large negative shifts in V th were observed under negative bias illumination stress, which is attributed to the presence of sulfur vacancies. This simple approach can be applied to other transition metal dichalcogenide materials to understand their FET properties and reliability, and the resulting high-performance hysteresis-free MoS 2 transistors are expected to open up new opportunities for the development of sophisticated electronic applications.

Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

PubMed

Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

2016-08-23

We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

Fabrication of flexible MoS2 thin-film transistor arrays for practical gas-sensing applications.

PubMed

He, Qiyuan; Zeng, Zhiyuan; Yin, Zongyou; Li, Hai; Wu, Shixin; Huang, Xiao; Zhang, Hua

2012-10-08

By combining two kinds of solution-processable two-dimensional materials, a flexible transistor array is fabricated in which MoS(2) thin film is used as the active channel and reduced graphene oxide (rGO) film is used as the drain and source electrodes. The simple device configuration and the 1.5 mm-long MoS(2) channel ensure highly reproducible device fabrication and operation. This flexible transistor array can be used as a highly sensitive gas sensor with excellent reproducibility. Compared to using rGO thin film as the active channel, this new gas sensor exhibits much higher sensitivity. Moreover, functionalization of the MoS(2) thin film with Pt nanoparticles further increases the sensitivity by up to ∼3 times. The successful incorporation of a MoS(2) thin-film into the electronic sensor promises its potential application in various electronic devices. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Atomic-Monolayer MoS2 Band-to-Band Tunneling Field-Effect Transistor.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Tsai, Shin-Hung; Zhu, Xiaodan; Shi, Yumeng; Li, Ming-Yang; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-11-01

The experimental observation of band-to-band tunneling in novel tunneling field-effect transistors utilizing a monolayer of MoS 2 as the conducting channel is demonstrated. Our results indicate that the strong gate-coupling efficiency enabled by two-dimensional materials, such as monolayer MoS 2 , results in the direct manifestation of a band-to-band tunneling current and an ambipolar transport. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Large Area CVD MoS2 RF transistors with GHz performance

NASA Astrophysics Data System (ADS)

Nagavalli Yogeesh, Maruthi; Sanne, Atresh; Park, Saungeun; Akinwade, Deji; Banerjee, Sanjay

Molybdenum disulfide (MoS2) is a 2D semiconductor in the family of transition metal dichalcogenides (TMDs). Its single layer direct bandgap of 1.8 eV allows for high ION/IOFF metal-oxide semiconducting field-effect transistors (FETs). More relevant for radio frequency (RF) wireless applications, theoretical studies predict MoS2 to have saturation velocities, vsat >3×106 cm/s. Facilitated by cm-scale CVD MoS2, here we design and fabricate both top-gated and embedded gate short channel MoS2 RF transistors, and provide a systematic comparison of channel length scaling, extrinsic doping from oxygen-deficient dielectrics, and a gate-first gate-last process flow. The intrinsic fT (fmax) obtained from the embedded gate transistors shows 3X (2X) improvement over top-gated CVD MoS2 RF FETs, and the largest high-field saturation velocity, vsat = 1.88 ×106 cm/s, in MoS2 reported so far. The gate-first approach, offers enhancement mode operation, ION/IOFF ratio of 10, 8< and the highest reported transconductance (gm) of 70 μS/ μm. By manipulating the interfacial oxygen vacancies in atomic layer deposited (ALD) HfO2-x we are able to achieve 2X current density over stoichiometric Al2O3. We demonstrate a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

Effects of Electron Beam Irradiation and Thiol Molecule Treatment on the Properties of MoS2 Field Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Barbara Yuri; Cho, Kyungjune; Pak, Jinsu; Kim, Tae-Young; Kim, Jae-Keun; Shin, Jiwon; Seo, Junseok; Chung, Seungjun; Lee, Takhee

2018-05-01

We investigated the effects of the structural defects intentionally created by electron-beam irradiation with an energy of 30 keV on the electrical properties of monolayer MoS2 field effect transistors (FETs). We observed that the created defects by electron beam irradiation on the MoS2 surface working as trap sites deteriorated the carrier mobility and carrier concentration with increasing the subthreshold swing value and shifting the threshold voltage in MoS2 FETs. The electrical properties of electron-beam irradiated MoS2 FETs were slightly improved by treating the devices with thiol-terminated molecules which presumably passivated the structural defects of MoS2. The results of this study may enhance the understanding of the electrical properties of MoS2 FETs in terms of creating and passivating defect sites.

Enhanced carrier mobility of multilayer MoS2 thin-film transistors by Al2O3 encapsulation

NASA Astrophysics Data System (ADS)

Kim, Seong Yeoul; Park, Seonyoung; Choi, Woong

2016-10-01

We report the effect of Al2O3 encapsulation on the carrier mobility and contact resistance of multilayer MoS2 thin-film transistors by statistically investigating 70 devices with SiO2 bottom-gate dielectric. After Al2O3 encapsulation by atomic layer deposition, calculation based on Y-function method indicates that the enhancement of carrier mobility from 24.3 cm2 V-1 s-1 to 41.2 cm2 V-1 s-1 occurs independently from the reduction of contact resistance from 276 kΩ.μm to 118 kΩ.μm. Furthermore, contrary to the previous literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method of improving the carrier mobility of multilayer MoS2 transistors, providing important implications on the application of MoS2 and other two-dimensional materials into high-performance transistors.

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

2008-01-01

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Influence of the Metal-MoS2 interface on MoS2 Transistor Performance

NASA Astrophysics Data System (ADS)

Yuan, Hui; Cheng, Guangjun; Hight Walker, Angela; You, Lin; Kopanski, Joseph J.; Li, Qiliang; Richter, Curt A.

2015-03-01

We compare the electrical characteristics of MoS2 field-effect transistors (FETS) with Ag source/drain contacts with transistors with Ti contacts, and we demonstrate that the metal-MoS2 interface is crucial to the final device performance. The topography of 5nm Au/5nm Ag (contact layer) and 5nm Au/5nm Ti metal films deposited onto mono- and few-layer MoS2 was characterized by using scanning electron microscopy and atomic force microscopy. The surface morphology of the Au/Ti films on MoS2 shows a rough, dewetting pattern while Au/Ag forms smooth, dense films. These smoother and denser Au/Ag contacts lead to improved carrier transport efficiency. FETs with Ag contacts show more than 60 times higher on-state current and a steeper subthreshold slope. Raman spectroscopy of MoS2 covered with Au/Ag or Au/Ti films revealed that the contact layer is Ag or Ti, respectively. In addition, there is a dramatic difference in the heat transfer between the MoS2 and the two metals: while laser heating is observed in Au/Ti covered MoS2, no heating effects are seen in Au/Ag covered MoS2. It is reasonable to conclude that the smoother and denser Ag contact leads to higher carrier transport efficiency and contributes to the improved thermal properties.

A convenient method of manufacturing liquid-gated MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Lin, Kabin; Yuan, Zhishan; Yu, Yu; Li, Kun; Li, Zhongwu; Sha, Jingjie; Li, Tie; Chen, Yunfei

2017-10-01

In this paper, we present a simple and convenient method of manufacturing liquid-gated MoS2 field effect transistors (FETs). A Si3N4 chip is firstly fabricated by the semiconductor manufacturing process, then the mechanical exfoliation MoS2 is transferred onto the Si3N4 chip and is connected with the gold electrodes by depositing platinum to construct the MoS2 FETs. The liquid-gated is formed by injecting 0.1 M NaCl solution into reservoir to contact the back side of the Si3N4. Our measured results show that the contact properties between MoS2 and electrodes are in well condition and the liquid-gated MoS2 FETs have a high mobility that can reach up to 109 cm2 V-1 s-1.

Anti-site defected MoS2 sheet-based single electron transistor as a gas sensor

NASA Astrophysics Data System (ADS)

Sharma, Archana; Husain, Mushahid; Srivastava, Anurag; Khan, Mohd. Shahid

2018-05-01

To prevent harmful and poisonous CO gas molecules, catalysts are needed for converting them into benign substances. Density functional theory (DFT) calculations have been used to study the adsorption of CO and CO2 gas molecules on the surface of MoS2 monolayer with Mo atom embedded at S-vacancy site (MoS). The strong interaction between Mo metal with pristine MoS2 sheet suggests its strong binding nature. Doping Mo into MoS2 sheet enhances CO and CO2 adsorption strength. The sensing response of MoS-doped MoS2 system to CO and CO2 gas molecules is obtained in the single electron transistor (SET) environment by varying bias voltage. Doping reduces charging energy of the device which results in fast switching of the device from OFF to ON state.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

PubMed

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

PubMed Central

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Enhanced photoresponse characteristics of transistors using CVD-grown MoS2/WS2 heterostructures

NASA Astrophysics Data System (ADS)

Shan, Junjie; Li, Jinhua; Chu, Xueying; Xu, Mingze; Jin, Fangjun; Fang, Xuan; Wei, Zhipeng; Wang, Xiaohua

2018-06-01

Semiconductor heterostructures based on transition metal dichalcogenides provide a broad platform to research two-dimensional nanomaterials and design atomically thin devices for fundamental and applied interests. The MoS2/WS2 heterostructure was prepared on SiO2/Si substrate by chemical vapor deposition (CVD) in our research. And the optical properties of the heterostructure was characterized by Raman and photoluminescence (PL) spectroscopy. The similar 2 orders of magnitude decrease of PL intensity in MoS2/WS2 heterostructures was tested, which is attribute to the electrical and optical modulation effects are connected with the interfacial charge transfer between MoS2 and WS2 films. Using MoS2/WS2 heterostructure as channel material of the phototransistor, we demonstrated over 50 folds enhanced photoresponsivity of multilayer MoS2 field-effect transistor. The results indicate that the MoS2/WS2 films can be a promising heterostructure material to enhance the photoresponse characteristics of MoS2-based phototransistors.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

A new surface-potential-based compact model for the MoS2 field effect transistors in active matrix display applications

NASA Astrophysics Data System (ADS)

Cao, Jingchen; Peng, Songang; Liu, Wei; Wu, Quantan; Li, Ling; Geng, Di; Yang, Guanhua; Ji, Zhouyu; Lu, Nianduan; Liu, Ming

2018-02-01

We present a continuous surface-potential-based compact model for molybdenum disulfide (MoS2) field effect transistors based on the multiple trapping release theory and the variable-range hopping theory. We also built contact resistance and velocity saturation models based on the analytical surface potential. This model is verified with experimental data and is able to accurately predict the temperature dependent behavior of the MoS2 field effect transistor. Our compact model is coded in Verilog-A, which can be implemented in a computer-aided design environment. Finally, we carried out an active matrix display simulation, which suggested that the proposed model can be successfully applied to circuit design.

Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application.

PubMed

Nourbakhsh, Amirhasan; Zubair, Ahmad; Dresselhaus, Mildred S; Palacios, Tomás

2016-02-10

This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temperature negative differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an average conductance slope of 75 mV/dec with a high curvature coefficient of 62 V(-1). Associated with the tunnel-diode characteristics, a positive-to-negative transconductance in the MoS2/WSe2 heterojunction transistors is observed. The transition is induced by strong interlayer coupling between the films, which results in charge density and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.

GaN-Based High Temperature and Radiation-Hard Electronics for Harsh Environments

NASA Technical Reports Server (NTRS)

Son, Kyung-ah; Liao, Anna; Lung, Gerald; Gallegos, Manuel; Hatakeh, Toshiro; Harris, Richard D.; Scheick, Leif Z.; Smythe, William D.

2010-01-01

We develop novel GaN-based high temperature and radiation-hard electronics to realize data acquisition electronics and transmitters suitable for operations in harsh planetary environments. In this paper, we discuss our research on metal-oxide-semiconductor (MOS) transistors that are targeted for 500 (sup o)C operation and >2 Mrad radiation hardness. For the target device performance, we develop Schottky-free AlGaN/GaN MOS transistors, where a gate electrode is processed in a MOS layout using an Al2O3 gate dielectric layer....

All-Electrical Spin Field Effect Transistor in van der Waals Heterostructures at Room Temperature

NASA Astrophysics Data System (ADS)

Dankert, André; Dash, Saroj

Spintronics aims to exploit the spin degree of freedom in solid state devices for data storage and information processing. Its fundamental concepts (creation, manipulation and detection of spin polarization) have been demonstrated in semiconductors and spin transistor structures using electrical and optical methods. However, an unsolved challenge is the realization of all-electrical methods to control the spin polarization in a transistor manner at ambient temperatures. Here we combine graphene and molybdenum disulfide (MoS2) in a van der Waals heterostructure to realize a spin field-effect transistor (spin-FET) at room temperature. These two-dimensional crystals offer a unique platform due to their contrasting properties, such as weak spin-orbit coupling (SOC) in graphene and strong SOC in MoS2. The gate-tuning of the Schottky barrier at the MoS2/graphene interface and MoS2 channel yields spins to interact with high SOC material and allows us to control the spin polarization and lifetime. This all-electrical spin-FET at room temperature is a substantial step in the field of spintronics and opens a new platform for testing a plethora of exotic physical phenomena, which can be key building blocks in future device architectures.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Flexible low-power RF nanoelectronics in the GHz regime using CVD MoS2

NASA Astrophysics Data System (ADS)

Yogeesh, Maruthi

Two-dimensional (2D) materials have attracted substantial interest for flexible nanoelectronics due to the overall device mechanical flexibility and thickness scalability for high mechanical performance and low operating power. In this work, we demonstrate the first MoS2 RF transistors on flexible substrates based on CVD-grown monolayers, featuring record GHz cutoff frequency (5.6 GHz) and saturation velocity (~1.8×106 cm/s), which is significantly superior to contemporary organic and metal oxide thin-film transistors. Furthermore, multicycle three-point bending results demonstrated the electrical robustness of our flexible MoS2 transistors after 10,000 cycles of mechanical bending. Additionally, basic RF communication circuit blocks such as amplifier, mixer and wireless AM receiver have been demonstrated. These collective results indicate that MoS2 is an ideal advanced semiconducting material for low-power, RF devices for large-area flexible nanoelectronics and smart nanosystems owing to its unique combination of large bandgap, high saturation velocity and high mechanical strength.

High-performance a MoS2 nanosheet-based nonvolatile memory transistor with a ferroelectric polymer and graphene source-drain electrode

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Im, Seongil

2015-11-01

Two-dimensional (2D) van der Waals (vdWs) materials are a class of new materials due to their unique physical properties. Of the many 2D vdWs materials, molybdenum disulfide (MoS2) is a representative n-type transition-metal dichalcogenide (TMD) semiconductor. Here, we report on a high-performance MoS2 nanosheet-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. In order to enhance the ohmic contact property, we use graphene flakes as source/drain electrodes prepared by using the direct imprinting method with an elastomer stamp. The MoS2 ferroelectric field-effect transistor (FeFET) shows the highest linear electron mobility value of 175 cm2/Vs with a high on/off current ratio of more than 107, and a very clear memory window of more than 15 V. The program and erase dynamics and the static retention properties are also well demonstrated.

Phase transition and field effect topological quantum transistor made of monolayer MoS2

NASA Astrophysics Data System (ADS)

Simchi, H.; Simchi, M.; Fardmanesh, M.; Peeters, F. M.

2018-06-01

We study topological phase transitions and topological quantum field effect transistor in monolayer molybdenum disulfide (MoS2) using a two-band Hamiltonian model. Without considering the quadratic (q 2) diagonal term in the Hamiltonian, we show that the phase diagram includes quantum anomalous Hall effect, quantum spin Hall effect, and spin quantum anomalous Hall effect regions such that the topological Kirchhoff law is satisfied in the plane. By considering the q 2 diagonal term and including one valley, it is shown that MoS2 has a non-trivial topology, and the valley Chern number is non-zero for each spin. We show that the wave function is (is not) localized at the edges when the q 2 diagonal term is added (deleted) to (from) the spin-valley Dirac mass equation. We calculate the quantum conductance of zigzag MoS2 nanoribbons by using the nonequilibrium Green function method and show how this device works as a field effect topological quantum transistor.

Single-layer MoS2 electronics.

PubMed

Lembke, Dominik; Bertolazzi, Simone; Kis, Andras

2015-01-20

CONSPECTUS: Atomic crystals of two-dimensional materials consisting of single sheets extracted from layered materials are gaining increasing attention. The most well-known material from this group is graphene, a single layer of graphite that can be extracted from the bulk material or grown on a suitable substrate. Its discovery has given rise to intense research effort culminating in the 2010 Nobel Prize in physics awarded to Andre Geim and Konstantin Novoselov. Graphene however represents only the proverbial tip of the iceberg, and increasing attention of researchers is now turning towards the veritable zoo of so-called "other 2D materials". They have properties complementary to graphene, which in its pristine form lacks a bandgap: MoS2, for example, is a semiconductor, while NbSe2 is a superconductor. They could hold the key to important practical applications and new scientific discoveries in the two-dimensional limit. This family of materials has been studied since the 1960s, but most of the research focused on their tribological applications: MoS2 is best known today as a high-performance dry lubricant for ultrahigh-vacuum applications and in car engines. The realization that single layers of MoS2 and related materials could also be used in functional electronic devices where they could offer advantages compared with silicon or graphene created a renewed interest in these materials. MoS2 is currently gaining the most attention because the material is easily available in the form of a mineral, molybdenite, but other 2D transition metal dichalcogenide (TMD) semiconductors are expected to have qualitatively similar properties. In this Account, we describe recent progress in the area of single-layer MoS2-based devices for electronic circuits. We will start with MoS2 transistors, which showed for the first time that devices based on MoS2 and related TMDs could have electrical properties on the same level as other, more established semiconducting materials. This allowed rapid progress in this area and was followed by demonstrations of basic digital circuits and transistors operating in the technologically relevant gigahertz range of frequencies, showing that the mobility of MoS2 and TMD materials is sufficiently high to allow device operation at such high frequencies. Monolayer MoS2 and other TMDs are also direct band gap semiconductors making them interesting for realizing optoelectronic devices. These range from simple phototransistors showing high sensitivity and low noise, to light emitting diodes and solar cells. All the electronic and optoelectronic properties of MoS2 and TMDs are accompanied by interesting mechanical properties with monolayer MoS2 being as stiff as steel and 30× stronger. This makes it especially interesting in the context of flexible electronics where it could combine the high degree of mechanical flexibility commonly associated with organic semiconductors with high levels of electrical performance. All these results show that MoS2 and TMDs are promising materials for electronic and optoelectronic applications.

Laser direct writing and inkjet printing for a sub-2 μm channel length MoS2 transistor with high-resolution electrodes

NASA Astrophysics Data System (ADS)

Kwon, Hyuk-Jun; Chung, Seungjun; Jang, Jaewon; Grigoropoulos, Costas P.

2016-10-01

Patterns formed by the laser direct writing (LDW) lithography process are used either as channels or barriers for MoS2 transistors fabricated via inkjet printing. Silver (Ag) nanoparticle ink is printed over patterns formed on top of the MoS2 flakes in order to construct high-resolution source/drain (S/D) electrodes. When positive photoresist is used, the produced grooves are filled with inkjetted Ag ink by capillary forces. On the other hand, in the case of negative photoresist, convex barrier-like patterns are written on the MoS2 flakes and patterns, dividing the printed Ag ink into the S/D electrodes by self-alignment. LDW lithography combined with inkjet printing is applied to MoS2 thin-film transistors that exhibit moderate electrical performance such as mobility and subthreshold swing. However, especially in the linear operation regime, their features are limited by the contact effect. The Y-function method can exclude the contact effect and allow proper evaluation of the maximum available mobility and contact resistance. The presented fabrication methods may facilitate the development of cost-effective fabrication processes.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

NASA Astrophysics Data System (ADS)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Nanoscale-Barrier Formation Induced by Low-Dose Electron-Beam Exposure in Ultrathin MoS2 Transistors.

PubMed

Matsunaga, Masahiro; Higuchi, Ayaka; He, Guanchen; Yamada, Tetsushi; Krüger, Peter; Ochiai, Yuichi; Gong, Yongji; Vajtai, Robert; Ajayan, Pulickel M; Bird, Jonathan P; Aoki, Nobuyuki

2016-10-05

Utilizing an innovative combination of scanning-probe and spectroscopic techniques, supported by first-principles calculations, we demonstrate how electron-beam exposure of field-effect transistors, implemented from ultrathin molybdenum disulfide (MoS 2 ), may cause nanoscale structural modifications that in turn significantly modify the electrical operation of these devices. Quite surprisingly, these modifications are induced by even the relatively low electron doses used in conventional electron-beam lithography, which are found to induce compressive strain in the atomically thin MoS 2 . Likely arising from sulfur-vacancy formation in the exposed regions, the strain gives rise to a local widening of the MoS 2 bandgap, an idea that is supported both by our experiment and by the results of first-principles calculations. A nanoscale potential barrier develops at the boundary between exposed and unexposed regions and may cause extrinsic variations in the resulting electrical characteristics exhibited by the transistor. The widespread use of electron-beam lithography in nanofabrication implies that the presence of such strain must be carefully considered when seeking to harness the potential of atomically thin transistors. At the same time, this work also promises the possibility of exploiting the strain as a means to achieve "bandstructure engineering" in such devices.

Enhancement of near-infrared detectability from InGaZnO thin film transistor with MoS2 light absorbing layer.

PubMed

Pak, Sang Woo; Chu, Dongil; Song, Da Ye; Lee, Seung Kyo; Kim, Eun Kyu

2017-11-24

We report an enhancement of near-infrared (NIR) detectability from amorphous InGaZnO (α-IGZO) thin film transistor in conjunction with randomly distributed molybdenum disulfide (MoS 2 ) flakes. The electrical characteristics of the α-IGZO grown by radio-frequency magnetron sputtering exhibit high effective mobility exceeding 15 cm 2 V -1 s -1 and current on/off ratio up to 10 7 . By taking advantages of the high quality α-IGZO and MoS 2 light absorbing layer, photodetection spectra are able to extend from ultra-violet to NIR range. The α-IGZO channel detector capped by MoS 2 show a photo-responsivity of approximately 14.9 mA W -1 at 1100 nm wavelength, which is five times higher than of the α-IGZO device without MoS 2 layer.

Enhancement of near-infrared detectability from InGaZnO thin film transistor with MoS2 light absorbing layer

NASA Astrophysics Data System (ADS)

Pak, Sang Woo; Chu, Dongil; Song, Da Ye; Kyo Lee, Seung; Kim, Eun Kyu

2017-11-01

We report an enhancement of near-infrared (NIR) detectability from amorphous InGaZnO (α-IGZO) thin film transistor in conjunction with randomly distributed molybdenum disulfide (MoS2) flakes. The electrical characteristics of the α-IGZO grown by radio-frequency magnetron sputtering exhibit high effective mobility exceeding 15 cm2 V-1 s-1 and current on/off ratio up to 107. By taking advantages of the high quality α-IGZO and MoS2 light absorbing layer, photodetection spectra are able to extend from ultra-violet to NIR range. The α-IGZO channel detector capped by MoS2 show a photo-responsivity of approximately 14.9 mA W-1 at 1100 nm wavelength, which is five times higher than of the α-IGZO device without MoS2 layer.

A theoretical modeling of photocurrent generation and decay in layered MoS2 thin-film transistor photosensors

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Park, Junghak; Jeon, Sanghun

2017-02-01

A model that universally describes the characteristics of photocurrent in molybdenum disulphide (MoS2) thin-film transistor (TFT) photosensors in both ‘light on’ and ‘light off’ conditions is presented for the first time. We considered possible material-property dependent carrier generation and recombination mechanisms in layered MoS2 channels with different numbers of layers. We propose that the recombination rates that are mainly composed of direct band-to-band recombination and interface trap-involved recombination change on changing the light condition and the number of layers. By comparing the experimental results, it is shown that the model performs well in describing the photocurrent behaviors of MoS2 TFT photosensors, including the photocurrent generation under illumination and a hugely long time persistent trend of the photocurrent decay in the dark condition, for a range of MoS2 layer numbers.

Tailoring the charge carrier in few layers MoS2 field-effect transistors by Au metal adsorbate

NASA Astrophysics Data System (ADS)

Singh, Arun Kumar; Pandey, Rajiv K.; Prakash, Rajiv; Eom, Jonghwa

2018-04-01

It is an essential to tune the charge carrier concentrations in semiconductor in order to approach high-performance of the electronic and optoelectronic devices. Here, we report the effect of thin layer of gold (Au) metal on few layer (FL) molybdenum disulfide (MoS2) by atomic force microscopy (AFM), Raman spectroscopy and electrical charge transport measurements. The Raman spectra and charge transport measurements show that Au thin layer affect the electronic properties of the FL MoS2. After deposition of Au thin layer, the threshold voltages of FL MoS2 field-effect transistors (FETs) shift towards positive gate voltages, this reveal the p-doping in FL MoS2 nanosheets. The shift of peak frequencies of the Raman bands are also analyzed after the deposition of Au metal films of different thickness on FL MoS2 nanosheets. The surface morphology of Au metal on FL MoS2 is characterized by AFM and shows the smoother and denser film in comparison to Au metal on SiO2.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Soft-type trap-induced degradation of MoS2 field effect transistors.

PubMed

Cho, Young-Hoon; Ryu, Min-Yeul; Lee, Kook Jin; Park, So Jeong; Choi, Jun Hee; Lee, Byung-Chul; Kim, Wungyeon; Kim, Gyu-Tae

2018-06-01

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS 2 multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation-correlated mobility fluctuation (CNF-CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF-CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS 2 FETs.

Soft-type trap-induced degradation of MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Cho, Young-Hoon; Ryu, Min-Yeul; Lee, Kook Jin; Park, So Jeong; Choi, Jun Hee; Lee, Byung-Chul; Kim, Wungyeon; Kim, Gyu-Tae

2018-06-01

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS2 multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation–correlated mobility fluctuation (CNF–CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF–CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS2 FETs.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS₂ Transistors.

PubMed

Ma, Jiyeon; Yoo, Geonwook

2018-09-01

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

MOSFET and MOS capacitor responses to ionizing radiation

NASA Technical Reports Server (NTRS)

Benedetto, J. M.; Boesch, H. E., Jr.

1984-01-01

The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

PubMed

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Method of making self-aligned lightly-doped-drain structure for MOS transistors

DOEpatents

Weiner, Kurt H.; Carey, Paul G.

2001-01-01

A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

Single-layer MoS2 - electrical transport properties, devices and circuits

NASA Astrophysics Data System (ADS)

Kis, Andras

2013-03-01

After quantum dots, nanotubes and nanowires, two-dimensional materials in the shape of sheets with atomic-scale thickness represent the newest addition to the diverse family of nanoscale materials. Single-layer molybdenum disulphide (MoS2) , a direct-gap semiconductor is a typical example of these new graphene-like materials that can be produced using the adhesive-tape based cleavage technique originally developed for graphene. The presence of a band gap in MoS2 allowed us to fabricate transistors that can be turned off and operate with negligible leakage currents. Furthermore, our transistors can be used to build simple integrated circuits capable of performing logic operations and amplifying small signals. I will report here on our latest 2D MoS2 transistors with improved performance due to enhanced electrostatic control, showing improved currents and transconductance as well as current saturation. We also record electrical breakdown of our devices and find that MoS2 can support very high current densities, exceeding the current carrying capacity of copper by a factor of fifty. Furthermore, I will show optoelectronic devices incorporating MoS2 with sensitivity that surpasses similar graphene devices by several orders of magnitude. Finally, I will present temperature-dependent electrical transport and mobility measurements that show clear mobility enhancement due to the suppression of the influence of charge impurities with the deposition of an HfO2 capping layer. Financially supported by grants from Swiss National Science Foundation, EU-FP7, EU-ERC and Swiss Nanoscience Institute.

Vacuum ultraviolet radiation effects on two-dimensional MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

McMorrow, Julian J.; Cress, Cory D.; Arnold, Heather N.; Sangwan, Vinod K.; Jariwala, Deep; Schmucker, Scott W.; Marks, Tobin J.; Hersam, Mark C.

2017-02-01

Atomically thin MoS2 has generated intense interest for emerging electronics applications. Its two-dimensional nature and potential for low-power electronics are particularly appealing for space-bound electronics, motivating the need for a fundamental understanding of MoS2 electronic device response to the space radiation environment. In this letter, we quantify the response of MoS2 field-effect transistors (FETs) to vacuum ultraviolet (VUV) total ionizing dose radiation. Single-layer (SL) and multilayer (ML) MoS2 FETs are compared to identify differences that arise from thickness and band structure variations. The measured evolution of the FET transport properties is leveraged to identify the nature of VUV-induced trapped charge, isolating the effects of the interface and bulk oxide dielectric. In both the SL and ML cases, oxide trapped holes compete with interface trapped electrons, exhibiting an overall shift toward negative gate bias. Raman spectroscopy shows no variation in the MoS2 signatures as a result of VUV exposure, eliminating significant crystalline damage or oxidation as possible radiation degradation mechanisms. Overall, this work presents avenues for achieving radiation-hard MoS2 devices through dielectric engineering that reduces oxide and interface trapped charge.

Improved photoswitching response times of MoS2 field-effect transistors by stacking p-type copper phthalocyanine layer

NASA Astrophysics Data System (ADS)

Pak, Jinsu; Min, Misook; Cho, Kyungjune; Lien, Der-Hsien; Ahn, Geun Ho; Jang, Jingon; Yoo, Daekyoung; Chung, Seungjun; Javey, Ali; Lee, Takhee

2016-10-01

Photoswitching response times (rise and decay times) of a vertical organic and inorganic heterostructure with p-type copper phthalocyanine (CuPc) and n-type molybdenum disulfide (MoS2) semiconductors are investigated. By stacking a CuPc layer on MoS2 field effect transistors, better photodetection capability and fast photoswitching rise and decay phenomena are observed. Specifically, with a 2 nm-thick CuPc layer on the MoS2 channel, the photoswitching decay time decreases from 3.57 s to 0.18 s. The p-type CuPc layer, as a passivation layer, prevents the absorption of oxygen on the surface of the MoS2 channel layer, which results in a shortened photoswitching decay time because adsorbed oxygen destroys the balanced ratio of electrons and holes, leading to the interruption of recombination processes. The suggested heterostructure may deliver enhanced photodetection abilities and photoswitching characteristics for realizing ultra-thin and sensitive photodetectors.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

PubMed Central

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices. PMID:22163968

New analysis and design of a RF rectifier for RFID and implantable devices.

PubMed

Liu, Dong-Sheng; Li, Feng-Bo; Zou, Xue-Cheng; Liu, Yao; Hui, Xue-Mei; Tao, Xiong-Fei

2011-01-01

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from -15 dBm to -4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitable to passive UHF RFID tag IC and implantable devices.

Development of Process Technologies for High-Performance MOS-Based SiC Power Switching Devices

DTIC Science & Technology

2007-08-01

investigated are insulated-gate bipolar transistors ( IGBTs ) in 4H-SiC. The IGBT combines the best aspects of MOS and bipolar power transistors... IGBTs can be thought of as a fusion of a MOSFET and a BJT. The MOSFET provides a high input impedance while the BJT provides conductivity modulation of...region due to conductivity modulation from the forward-biased BJT. The IGBT is structurally identical to a MOSFET, except that the substrate doping

Enhancement of photodetection characteristics of MoS2 field effect transistors using surface treatment with copper phthalocyanine.

PubMed

Pak, Jinsu; Jang, Jingon; Cho, Kyungjune; Kim, Tae-Young; Kim, Jae-Keun; Song, Younggul; Hong, Woong-Ki; Min, Misook; Lee, Hyoyoung; Lee, Takhee

2015-11-28

Recently, two-dimensional materials such as molybdenum disulfide (MoS2) have been extensively studied as channel materials for field effect transistors (FETs) because MoS2 has outstanding electrical properties such as a low subthreshold swing value, a high on/off ratio, and good carrier mobility. In this study, we characterized the electrical and photo-responsive properties of MoS2 FET when stacking a p-type organic copper phthalocyanine (CuPc) layer on the MoS2 surface. We observed that the threshold voltage of MoS2 FET could be controlled by stacking the CuPc layers due to a charge transfer phenomenon at the interface. Particularly, we demonstrated that CuPc/MoS2 hybrid devices exhibited high performance as a photodetector compared with the pristine MoS2 FETs, caused by more electron-hole pairs separation at the p-n interface. Furthermore, we found the optimized CuPc thickness (∼2 nm) on the MoS2 surface for the best performance as a photodetector with a photoresponsivity of ∼1.98 A W(-1), a detectivity of ∼6.11 × 10(10) Jones, and an external quantum efficiency of ∼12.57%. Our study suggests that the MoS2 vertical hybrid structure with organic material can be promising as efficient photodetecting devices and optoelectronic circuits.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Models of MOS and SOS devices

NASA Technical Reports Server (NTRS)

Gassaway, J. D.; Mahmood, Q.; Trotter, J. D.

1980-01-01

Quarterly report describes progress in three programs: dc sputtering machine for aluminum and aluminum alloys; two dimensional computer modeling of MOS transistors; and development of computer techniques for calculating redistribution diffusion of dopants in silicon on sapphire films.

All-dry transferred single- and few-layer MoS2 field effect transistor with enhanced performance by thermal annealing

NASA Astrophysics Data System (ADS)

Islam, Arnob; Lee, Jaesung; Feng, Philip X.-L.

2018-01-01

We report on the experimental demonstration of all-dry stamp transferred single- and few-layer (1L to 3L) molybdenum disulfide (MoS2) field effect transistors (FETs), with a significant enhancement of device performance by employing thermal annealing in moderate vacuum. Three orders of magnitude reduction in both contact and channel resistances have been attained via thermal annealing. We obtain a low contact resistance of 22 kΩ μm after thermal annealing of 1L MoS2 FETs stamp-transferred onto gold (Au) contact electrodes. Furthermore, nearly two orders of magnitude enhancement of field effect mobility are also observed after thermal annealing. Finally, we employ Raman and photoluminescence measurements to reveal the phenomena of alloying or hybridization between 1L MoS2 and its contacting electrodes during annealing, which is responsible for attaining the low contact resistance.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Synthesis of bilayer MoS2 and corresponding field effect characteristics

NASA Astrophysics Data System (ADS)

Fang, Mingxu; Feng, Yulin; Wang, Fang; Yang, Zhengchun; Zhang, Kailiang

2017-06-01

Two-dimensional transition-metal dichalcogenides such as MoS2 are promising materials for next-generation nano-electronic devices. The physical properties of MoS2 are determined by layer number according to the variation of band-gap. Here, we synthesize large-size bilayer-MoS2 with triangle and hexagonal nanosheets in one step by chemical vapor deposition, Monolayer and bilayer-MoS2 back-gate field effect transistors are also fabricated and the performance including mobility and on/off ratios are compared. The bilayer-MoS2 back-gate field effect transistor shows superior performance with field effect mobility of ∼21.27cm2V-1s-1, and Ion/Ioff ratio of ∼3.9×107.

Contact-Engineered Electrical Properties of MoS2 Field-Effect Transistors via Selectively Deposited Thiol-Molecules.

PubMed

Cho, Kyungjune; Pak, Jinsu; Kim, Jae-Keun; Kang, Keehoon; Kim, Tae-Young; Shin, Jiwon; Choi, Barbara Yuri; Chung, Seungjun; Lee, Takhee

2018-05-01

Although 2D molybdenum disulfide (MoS 2 ) has gained much attention due to its unique electrical and optical properties, the limited electrical contact to 2D semiconductors still impedes the realization of high-performance 2D MoS 2 -based devices. In this regard, many studies have been conducted to improve the carrier-injection properties by inserting functional paths, such as graphene or hexagonal boron nitride, between the electrodes and 2D semiconductors. The reported strategies, however, require relatively time-consuming and low-yield transfer processes on sub-micrometer MoS 2 flakes. Here, a simple contact-engineering method is suggested, introducing chemically adsorbed thiol-molecules as thin tunneling barriers between the metal electrodes and MoS 2 channels. The selectively deposited thiol-molecules via the vapor-deposition process provide additional tunneling paths at the contact regions, improving the carrier-injection properties with lower activation energies in MoS 2 field-effect transistors. Additionally, by inserting thiol-molecules at the only one contact region, asymmetric carrier-injection is feasible depending on the temperature and gate bias. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

Dual-mode operation of 2D material-base hot electron transistors

PubMed Central

Lan, Yann-Wen; Torres, Jr., Carlos M.; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications. PMID:27581550

Dual-mode operation of 2D material-base hot electron transistors.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Optically transparent thin-film transistors based on 2D multilayer MoS₂ and indium zinc oxide electrodes.

PubMed

Kwon, Junyeon; Hong, Young Ki; Kwon, Hyuk-Jun; Park, Yu Jin; Yoo, Byungwook; Kim, Jiwan; Grigoropoulos, Costas P; Oh, Min Suk; Kim, Sunkook

2015-01-21

We report on optically transparent thin film transistors (TFTs) fabricated using multilayered molybdenum disulfide (MoS2) as the active channel, indium tin oxide (ITO) for the back-gated electrode and indium zinc oxide (IZO) for the source/drain electrodes, respectively, which showed more than 81% transmittance in the visible wavelength. In spite of a relatively large Schottky barrier between MoS2 and IZO, the n-type behavior with a field-effect mobility (μ(eff)) of 1.4 cm(2) V(-1) s(-1) was observed in as-fabricated transparent MoS2 TFT. In order to enhance the performances of transparent MoS2 TFTs, a picosecond pulsed laser was selectively irradiated onto the contact region of the IZO electrodes. Following laser annealing, μ(eff) increased to 4.5 cm(2) V(-1) s(-1), and the on-off current ratio (I(on)/I(off)) increased to 10(4), which were attributed to the reduction of the contact resistance between MoS2 and IZO.

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

Steep-slope hysteresis-free negative capacitance MoS2 transistors

NASA Astrophysics Data System (ADS)

Si, Mengwei; Su, Chun-Jung; Jiang, Chunsheng; Conrad, Nathan J.; Zhou, Hong; Maize, Kerry D.; Qiu, Gang; Wu, Chien-Ting; Shakouri, Ali; Alam, Muhammad A.; Ye, Peide D.

2018-01-01

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4-12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

A study of charged particles/radiation damage to VLSI device materials

NASA Technical Reports Server (NTRS)

Okyere, John G.

1987-01-01

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Nanoimprint-Assisted Shear Exfoliation (NASE) for Producing Multilayer MoS2 Structures as Field-Effect Transistor Channel Arrays.

PubMed

Chen, Mikai; Nam, Hongsuk; Rokni, Hossein; Wi, Sungjin; Yoon, Jeong Seop; Chen, Pengyu; Kurabayashi, Katsuo; Lu, Wei; Liang, Xiaogan

2015-09-22

MoS2 and other semiconducting transition metal dichalcogenides (TMDCs) are of great interest due to their excellent physical properties and versatile chemistry. Although many recent research efforts have been directed to explore attractive properties associated with MoS2 monolayers, multilayer/few-layer MoS2 structures are indeed demanded by many practical scale-up device applications, because multilayer structures can provide sizable electronic/photonic state densities for driving upscalable electrical/optical signals. Currently there is a lack of processes capable of producing ordered, pristine multilayer structures of MoS2 (or other relevant TMDCs) with manufacturing-grade uniformity of thicknesses and electronic/photonic properties. In this article, we present a nanoimprint-based approach toward addressing this challenge. In this approach, termed as nanoimprint-assisted shear exfoliation (NASE), a prepatterned bulk MoS2 stamp is pressed into a polymeric fixing layer, and the imprinted MoS2 features are exfoliated along a shear direction. This shear exfoliation can significantly enhance the exfoliation efficiency and thickness uniformity of exfoliated flakes in comparison with previously reported exfoliation processes. Furthermore, we have preliminarily demonstrated the fabrication of multiple transistors and biosensors exhibiting excellent device-to-device performance consistency. Finally, we present a molecular dynamics modeling analysis of the scaling behavior of NASE. This work holds significant potential to leverage the superior properties of MoS2 and other emerging TMDCs for practical scale-up device applications.

Influence of water vapor on the electronic property of MoS2 field effect transistors.

PubMed

Shu, Jiapei; Wu, Gongtao; Gao, Song; Liu, Bo; Wei, Xianlong; Chen, Qing

2017-05-19

The influence of water vapor on the electronic property of MoS 2 field effect transistors (FETs) is studied through controlled experiments. We fabricate supported and suspended FETs on the same piece of MoS 2 to figure out the role of SiO 2 substrate on the water sensing property of MoS 2 . The two kinds of devices show similar response to water vapor and to different treatments, such as pumping in the vacuum, annealing at 500 K and current annealing, indicating the substrate does not play an important role in the MoS 2 water sensor. Water adsorption is found to decrease the carrier mobility probably through introducing a scattering center on the surface of MoS 2 . The threshold voltage and subthreshold swing of the FETs do not change obviously after introducing water vapor, indicating there is no obvious doping and trap introducing effects. Long time pumping in a high vacuum and 500 K annealing show negligible effects on removing the water adsorption on the devices. Current annealing at high source-drain bias is found to be able to remove the water adsorption and set the FETs to their initial states. The mechanism is proposed to be through the hot carriers at high bias.

Enhanced two dimensional electron gas transport characteristics in Al2O3/AlInN/GaN metal-oxide-semiconductor high-electron-mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Freedsman, J. J.; Watanabe, A.; Urayama, Y.; Egawa, T.

2015-09-01

The authors report on Al2O3/Al0.85In0.15N/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor (MOS-HEMT) on Si fabricated by using atomic layer deposited Al2O3 as gate insulator and passivation layer. The MOS-HEMT with the gate length of 2 μm exhibits excellent direct-current (dc) characteristics with a drain current maximum of 1270 mA/mm at a gate bias of 3 V and an off-state breakdown voltage of 180 V for a gate-drain spacing of 4 μm. Also, the 1 μm-gate MOS-HEMT shows good radio-frequency (rf) response such as current gain and maximum oscillation cut-off frequencies of 10 and 34 GHz, respectively. The capacitance-voltage characteristics at 1 MHz revealed significant increase in two-dimensional electron gas (2DEG) density for the MOS-HEMT compared to conventional Schottky barrier HEMTs. Analyses using drain-source conductivity measurements showed improvements in 2DEG transport characteristics for the MOS-HEMT. The enhancements in dc and rf performances of the Al2O3/Al0.85In0.15N/GaN MOS-HEMT are attributed to the improvements in 2DEG characteristics.

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

NASA Astrophysics Data System (ADS)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Radio Frequency Transistors and Circuits Based on CVD MoS2.

PubMed

Sanne, Atresh; Ghosh, Rudresh; Rai, Amritesh; Yogeesh, Maruthi Nagavalli; Shin, Seung Heon; Sharma, Ankit; Jarvis, Karalee; Mathew, Leo; Rao, Rajesh; Akinwande, Deji; Banerjee, Sanjay

2015-08-12

We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

Prospects of zero Schottky barrier height in a graphene-inserted MoS2-metal interface

NASA Astrophysics Data System (ADS)

Chanana, Anuja; Mahapatra, Santanu

2016-01-01

A low Schottky barrier height (SBH) at source/drain contact is essential for achieving high drive current in atomic layer MoS2-channel-based field effect transistors. Approaches such as choosing metals with appropriate work functions and chemical doping are employed previously to improve the carrier injection from the contact electrodes to the channel and to mitigate the SBH between the MoS2 and metal. Recent experiments demonstrate significant SBH reduction when graphene layer is inserted between metal slab (Ti and Ni) and MoS2. However, the physical or chemical origin of this phenomenon is not yet clearly understood. In this work, density functional theory simulations are performed, employing pseudopotentials with very high basis sets to get insights of the charge transfer between metal and monolayer MoS2 through the inserted graphene layer. Our atomistic simulations on 16 different interfaces involving five different metals (Ti, Ag, Ru, Au, and Pt) reveal that (i) such a decrease in SBH is not consistent among various metals, rather an increase in SBH is observed in case of Au and Pt; (ii) unlike MoS2-metal interface, the projected dispersion of MoS2 remains preserved in any MoS2-graphene-metal system with shift in the bands on the energy axis. (iii) A proper choice of metal (e.g., Ru) may exhibit ohmic nature in a graphene-inserted MoS2-metal contact. These understandings would provide a direction in developing high-performance transistors involving heteroatomic layers as contact electrodes.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Performance Investigation of Multilayer MoS2 Thin-Film Transistors Fabricated via Mask-free Optically Induced Electrodeposition.

PubMed

Li, Meng; Liu, Na; Li, Pan; Shi, Jialin; Li, Guangyong; Xi, Ning; Wang, Yuechao; Liu, Lianqing

2017-03-08

Transition metal dichalcogenides, particularly MoS 2 , have recently received enormous interest in explorations of the physics and technology of nanodevice applications because of their excellent optical and electronic properties. Although monolayer MoS 2 has been extensively investigated for various possible applications, its difficulty of fabrication renders it less appealing than multilayer MoS 2 . Moreover, multilayer MoS 2 , with its inherent high electronic/photonic state densities, has higher output driving capabilities and can better satisfy the ever-increasing demand for versatile devices. Here, we present multilayer MoS 2 back-gate thin-film transistors (TFTs) that can achieve a relatively low subthreshold swing of 0.75 V/decade and a high mobility of 41 cm 2 ·V -1 ·s -1 , which exceeds the typical mobility value of state-of-the-art amorphous silicon-based TFTs by a factor of 80. Ag and Au electrode-based MoS 2 TFTs were fabricated by a convenient and rapid process. Then we performed a detailed analysis of the impacts of metal contacts and MoS 2 film thickness on electronic performance. Our findings show that smoother metal contacts exhibit better electronic characteristics and that MoS 2 film thickness should be controlled within a reasonable range of 30-40 nm to obtain the best mobility values, thereby providing valuable insights regarding performance enhancement for MoS 2 TFTs. Additionally, to overcome the limitations of the conventional fabrication method, we employed a novel approach known as optically induced electrodeposition (OIE), which allows the flexible and precise patterning of metal films and enables rapid and mask-free device fabrication, for TFT fabrication.

Relation between film thickness and surface doping of MoS2 based field effect transistors

NASA Astrophysics Data System (ADS)

Lockhart de la Rosa, César J.; Arutchelvan, Goutham; Leonhardt, Alessandra; Huyghebaert, Cedric; Radu, Iuliana; Heyns, Marc; De Gendt, Stefan

2018-05-01

Ultra-thin MoS2 film doping through surface functionalization with physically adsorbed species is of great interest due to its ability to dope the film without reduction in the carrier mobility. However, there is a need for understanding how the thickness of the MoS2 film is related to the induced surface doping for improved electrical performance. In this work, we report on the relation of MoS2 film thickness with the doping effect induced by the n-dopant adsorbate poly(vinyl-alcohol). Field effect transistors built using MoS2 films of different thicknesses were electrically characterized, and it was observed that the ION/OFF ratio after doping in thin films is more than four orders of magnitudes greater when compared with thick films. Additionally, a semi-classical model tuned with the experimental devices was used to understand the spatial distribution of charge in the channel and explain the observed behavior. From the simulation results, it was revealed that the two-dimensional carrier density induced by the adsorbate is distributed rather uniformly along the complete channel for thin films (<5.2 nm) contrary to what happens for thicker films.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

PubMed Central

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

Few-Layer MoS2-Organic Thin-Film Hybrid Complementary Inverter Pixel Fabricated on a Glass Substrate.

PubMed

Lee, Hee Sung; Shin, Jae Min; Jeon, Pyo Jin; Lee, Junyeong; Kim, Jin Sung; Hwang, Hyun Chul; Park, Eunyoung; Yoon, Woojin; Ju, Sang-Yong; Im, Seongil

2015-05-13

Few-layer MoS2-organic thin-film hybrid complementary inverters demonstrate a great deal of device performance with a decent voltage gain of ≈12, a few hundred pW power consumption, and 480 Hz switching speed. As fabricated on glass, this hybrid CMOS inverter operates as a light-detecting pixel as well, using a thin MoS2 channel. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Miniature electrometer preamplifier effectively compensates for input capacitance

NASA Technical Reports Server (NTRS)

Burrous, C. N.; Deboo, G. J.

1966-01-01

Negative capacitance preamplifier using a dual MOS /Metal Oxide Silicon/ transistor in conjunction with bipolar transistors is used with intracellular microelectrodes in recording bioelectric potentials. Applications would include use as a pickup plate video amplifier in storage tube tests and for pH and ionization chamber measurements.

THE SILICON OLFACTORY BULB: A NEUROMORPHIC APPROACH TO MOLECULAR SENSING WITH CHEMORECEPTIVE NEURON MOS TRANSISTORS (CNMOS)

EPA Science Inventory

Within the 3 -year effort, we have established several major findings:

• Chemical sensor in fluid environment with inorganic and polymer sensing surfaces (1,5): Conventional metal oxide semiconductor field effect transistor (MOSFET)-based chemical sensing su...

• Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

  NASA Astrophysics Data System (ADS)

  Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

  2009-12-01

  The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

• Small-signal amplifier based on single-layer MoS2

  NASA Astrophysics Data System (ADS)

  Radisavljevic, Branimir; Whitwick, Michael B.; Kis, Andras

  2012-07-01

  In this letter we demonstrate the operation of an analog small-signal amplifier based on single-layer MoS2, a semiconducting analogue of graphene. Our device consists of two transistors integrated on the same piece of single-layer MoS2. The high intrinsic band gap of 1.8 eV allows MoS2-based amplifiers to operate with a room temperature gain of 4. The amplifier operation is demonstrated for the frequencies of input signal up to 2 kHz preserving the gain higher than 1. Our work shows that MoS2 can effectively amplify signals and that it could be used for advanced analog circuits based on two-dimensional materials.

• Observation of abnormal mobility enhancement in multilayer MoS2 transistor by synergy of ultraviolet illumination and ozone plasma treatment

  NASA Astrophysics Data System (ADS)

  Guo, Junjie; Yang, Bingchu; Zheng, Zhouming; Jiang, Jie

  2017-03-01

  Mobility engineering through physical or chemical process is a fruitful approach for the atomically-layered two-dimensional electronic applications. Unfortunately, the usual process with either illumination or oxygen treatment would greatly deteriorate the mobility in two-dimensional MoS2 field-effect transistor (FET). Here, in this work, we report that the mobility can be abnormally enhanced to an order of magnitude by the synergy of ultraviolet illumination (UV) and ozone plasma treatment in multilayer MoS2 FET. This abnormal mobility enhancement is attributed to the trap passivation due to the photo-generated excess carriers during UV/ozone plasma treatment. An energy band model based on Schottky barrier modulation is proposed to understand the underlying mechanism. Raman spectra results indicate that the oxygen ions are incorporated into the surface of MoS2 (some of them are in the form of ultra-thin Mo-oxide) and can further confirm this proposed mechanism. Our results can thus provide a simple approach for mobility engineering in MoS2-based FET and can be easily expanded to other 2D electronic devices, which represents a significant step toward applications of 2D layered materials in advanced cost-effective electronics.

• Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

  PubMed

  Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

  2004-07-15

  We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

• Large-Area Monolayer MoS2 for Flexible Low-Power RF Nanoelectronics in the GHz Regime.

  PubMed

  Chang, Hsiao-Yu; Yogeesh, Maruthi Nagavalli; Ghosh, Rudresh; Rai, Amritesh; Sanne, Atresh; Yang, Shixuan; Lu, Nanshu; Banerjee, Sanjay Kumar; Akinwande, Deji

  2016-03-02

  Flexible synthesized MoS2 transistors are advanced to perform at GHz speeds. An intrinsic cutoff frequency of 5.6 GHz is achieved and analog circuits are realized. Devices are mechanically robust for 10,000 bending cycles. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

• An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors.

  PubMed

  Liu, Jiangwei; Koide, Yasuo

  2018-06-04

  Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high- k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High- k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high- k oxides of ALD-Al₂O₃, ALD-HfO₂, ALD-HfO₂/ALD-Al₂O₃ multilayer, SD-HfO₂/ALD-HfO₂ bilayer, SD-TiO₂/ALD-Al₂O₃ bilayer, and ALD-TiO₂/ALD-Al₂O₃ bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al₂O₃/H-diamond and SD-HfO₂/ALD-HfO₂/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO₂/ALD-Al₂O₃ bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p -type channel characteristics for the ALD-Al₂O₃/H-diamond, SD-HfO₂/ALD-HfO₂/H-diamond, and ALD-TiO₂/ALD-Al₂O₃/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high- k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

• Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS2 flake based field effect transistors on SiO2 and hBN substrates.

  PubMed

  Lee, Changhee; Rathi, Servin; Khan, Muhammad Atif; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo-Hyeb; Watanabe, Kenji; Taniguchi, Takashi; Kim, Gil-Ho

  2018-08-17

  Molybdenum disulfide (MoS 2 ) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS 2 flake are fabricated on hBN and SiO 2 substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS 2 -SiO 2 and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS 2 layer with a single hBN on both the devices. The device to device variations induced by different MoS 2 layer is also eliminated by employing a single MoS 2 layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 10 11 cm -2 on hBN substrate as compared to 1.1 × 10 12 cm -2 on SiO 2 substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO 2 and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS 2 FETs.

• CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

  NASA Astrophysics Data System (ADS)

  Uryu, Yuko; Asano, Tanemasa

  2002-04-01

  A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

• A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

  PubMed

  Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

  2011-10-01

  Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

• A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

  PubMed Central

  Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

  2012-01-01

  Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

• Schottky Barrier Height Engineering for Electrical Contacts of Multilayered MoS2 Transistors with Reduction of Metal-Induced Gap States.

  PubMed

  Kim, Gwang-Sik; Kim, Seung-Hwan; Park, June; Han, Kyu Hyun; Kim, Jiyoung; Yu, Hyun-Yong

  2018-06-06

  The difficulty in Schottky barrier height (SBH) control arising from Fermi-level pinning (FLP) at electrical contacts is a bottleneck in designing high-performance nanoscale electronics and optoelectronics based on molybdenum disulfide (MoS 2 ). For electrical contacts of multilayered MoS 2 , the Fermi level on the metal side is strongly pinned near the conduction-band edge of MoS 2 , which makes most MoS 2 -channel field-effect transistors (MoS 2 FETs) exhibit n-type transfer characteristics regardless of their source/drain (S/D) contact metals. In this work, SBH engineering is conducted to control the SBH of electrical top contacts of multilayered MoS 2 by introducing a metal-interlayer-semiconductor (MIS) structure which induces the Fermi-level unpinning by a reduction of metal-induced gap states (MIGS). An ultrathin titanium dioxide (TiO 2 ) interlayer is inserted between the metal contact and the multilayered MoS 2 to alleviate FLP and tune the SBH at the S/D contacts of multilayered MoS 2 FETs. A significant alleviation of FLP is demonstrated as MIS structures with 1 nm thick TiO 2 interlayers are introduced into the S/D contacts. Consequently, the pinning factor ( S) increases from 0.02 for metal-semiconductor (MS) contacts to 0.24 for MIS contacts, and the controllable SBH range is widened from 37 meV (50-87 meV) to 344 meV (107-451 meV). Furthermore, the Fermi-level unpinning effect is reinforced as the interlayer becomes thicker. This work widens the scope for modifying electrical characteristics of contacts by providing a platform to control the SBH through a simple process as well as understanding of the FLP at the electrical top contacts of multilayered MoS 2 .

• Strain and structure heterogeneity in MoS 2 atomic layers grown by chemical vapour deposition

  DOE PAGES

  Liu, Zheng; Amani, Matin; Najmaei, Sina; ...

  2014-11-18

  Monolayer molybdenum disulfide (MoS 2) has attracted tremendous attention due to its promising applications in high-performance field-effect transistors, phototransistors, spintronic devices, and nonlinear optics. The enhanced photoluminescence effect in monolayer MoS 2 was discovered and, as a strong tool, was employed for strain and defect analysis in MoS 2. Recently, large-size monolayer MoS 2 has been produced by chemical vapor deposition but has not yet been fully explored. Here we systematically characterize chemical vapor deposition grown MoS 2 by PL spectroscopy and mapping, and demonstrate non-uniform strain in single-crystalline monolayer MoS 2 and strain-induced band gap engineering. We also evaluatemore » the effective strain transferred from polymer substrates to MoS 2 by three-dimensional finite element analysis. In addition, our work demonstrates that PL mapping can be used as a non-contact approach for quick identification of grain boundaries in MoS 2.« less

• Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

  NASA Astrophysics Data System (ADS)

  Naquin, Clint Alan

  Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

• Research Update: Nanoscale surface potential analysis of MoS2 field-effect transistors for biomolecular detection using Kelvin probe force microscopy

  NASA Astrophysics Data System (ADS)

  Kim, Min Hyung; Park, Heekyeong; Lee, Hyungbeen; Nam, Kihwan; Jeong, Seokhwan; Omkaram, Inturu; Yoon, Dae Sung; Lee, Sei Young; Kim, Sunkook; Lee, Sang Woo

  2016-10-01

  We used high-resolution Kelvin probe force microscopy (KPFM) to investigate the immobilization of a prostate specific antigen (PSA) antibody by measuring the surface potential (SP) on a MoS2 surface over an extensive concentration range (1 pg/ml-100 μg/ml). After PSA antibody immobilization, we demonstrated that the SP on the MoS2 surface characterized by KPFM strongly correlated to the electrical signal of a MoS2 bioFET. This demonstration can not only be used to optimize the immobilization conditions for captured molecules, but can also be applied as a diagnostic tool to complement the electrical detection of a MoS2 FET biosensor.

• Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors.

  PubMed

  Lee, Ching-Ting; Chen, Chia-Chi; Lee, Hsin-Ying

  2018-03-05

  The three dimensional inverters were fabricated using novel complementary structure of stacked bottom n-type aluminum-doped zinc oxide (Al:ZnO) thin-film transistor and top p-type nickel oxide (NiO) thin-film transistor. When the inverter operated at the direct voltage (V DD ) of 10 V and the input voltage from 0 V to 10 V, the obtained high performances included the output swing of 9.9 V, the high noise margin of 2.7 V, and the low noise margin of 2.2 V. Furthermore, the high performances of unskenwed inverter were demonstrated by using the novel complementary structure of the stacked n-type Al:ZnO thin-film transistor and p-type nickel oxide (NiO) thin-film transistor.

• Environmental Effects on Hysteresis of Transfer Characteristics in Molybdenum Disulfide Field-Effect Transistors

  NASA Astrophysics Data System (ADS)

  Shimazu, Yoshihiro; Tashiro, Mitsuki; Sonobe, Satoshi; Takahashi, Masaki

  2016-07-01

  Molybdenum disulfide (MoS2) has recently received much attention for nanoscale electronic and photonic applications. To explore the intrinsic properties and enhance the performance of MoS2-based field-effect transistors, thorough understanding of extrinsic effects such as environmental gas and contact resistance of the electrodes is required. Here, we report the effects of environmental gases on the transport properties of back-gated multilayered MoS2 field-effect transistors. Comparisons between different gases (oxygen, nitrogen, and air and nitrogen with varying relative humidities) revealed that water molecules acting as charge-trapping centers are the main cause of hysteresis in the transfer characteristics. While the hysteresis persisted even after pumping out the environmental gas for longer than 10 h at room temperature, it disappeared when the device was cooled to 240 K, suggesting a considerable increase in the time constant of the charge trapping/detrapping at these modestly low temperatures. The suppression of the hysteresis or instability in the easily attainable temperature range without surface passivation is highly advantageous for the device application of this system. The humidity dependence of the threshold voltages in the transfer curves indicates that the water molecules dominantly act as hole-trapping centers. A strong dependence of the on-state current on oxygen pressure was also observed.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

Facile Routes To Improve Performance of Solution-Processed Amorphous Metal Oxide Thin Film Transistors by Water Vapor Annealing.

PubMed

Park, Won-Tae; Son, Inyoung; Park, Hyun-Woo; Chung, Kwun-Bum; Xu, Yong; Lee, Taegweon; Noh, Yong-Young

2015-06-24

Here, we report on a simple and high-rate oxidization method for producing solution-based compound mixtures of indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO) metal-oxide semiconductors (MOS) for thin-film transistor (TFT) applications. One of the issues for solution-based MOS fabrication is how to sufficiently oxidize the precursor in order to achieve high performance. As the oxidation rate of solution processing is lower than vacuum-based deposition such as sputtering, devices using solution-processed MOS exhibit relatively poorer performance. Therefore, we propose a method to prepare the metal-oxide precursor upon exposure to saturated water vapor in a closed volume for increasing the oxidization efficiency without requiring additional oxidizing agent. We found that the hydroxide rate of the MOS film exposed to water vapor is lower than when unexposed (≤18%). Hence, we successfully fabricated oxide TFTs with high electron mobility (27.9 cm(2)/V·s) and established a rapid process (annealing at 400 °C for 5 min) that is much shorter than the conventional as-deposited long-duration annealing (at 400 °C for 1 h) whose corresponding mobility is even lower (19.2 cm(2)/V·s).

Effect of substrate and temperature on the electronic properties of monolayer molybdenum disulfide field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Qizhi; Fang, Jiajia; Zhang, Guangru; Wang, Quan

2018-03-01

The use of two-dimensional nanostructured molybdenum disulfide (MoS2) films in field-effect transistors (FETs) in place of graphene was investigated. Monolayer MoS2 films were fabricated by chemical vapor deposition. The output and transfer curves of supported and suspended MoS2 FETs were measured. The mobility of the suspended device reached 364.2 cm2 V-1 s-1 at 150 °C. The hysteresis of the supported device in transfer curves was much larger than that of the suspended device, and it increased at higher temperatures. These results indicate that the device mobility was limited by Coulomb scattering at ambient temperature, and surface/interface phonon scattering at 150 °C, and the injection of electrons, via quantum tunneling through the Schottky barrier at the contact, was enhanced at higher temperatures and led to the increase of the hysteresis. The suspended MoS2 films show potential for application as a channel material in electronic devices, and further understanding the causes of hysteresis in a material is important for its use in technologies, such as memory devices and sensing cells.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could enable complex neuromorphic learning and the study of the physics of defect kinetics in two-dimensional materials.

On current transients in MoS2 Field Effect Transistors.

PubMed

Macucci, Massimo; Tambellini, Gerry; Ovchinnikov, Dmitry; Kis, Andras; Iannaccone, Giuseppe; Fiori, Gianluca

2017-09-14

We present an experimental investigation of slow transients in the gate and drain currents of MoS 2 -based transistors. We focus on the measurement of both the gate and drain currents and, from the comparative analysis of the current transients, we conclude that there are at least two independent trapping mechanisms: trapping of charges in the silicon oxide substrate, occurring with time constants of the order of tens of seconds and involving charge motion orthogonal to the MoS 2 sheet, and trapping at the channel surface, which occurs with much longer time constants, in particular when the device is in a vacuum. We observe that the presence of such slow phenomena makes it very difficult to perform reliable low-frequency noise measurements, requiring a stable and repeatable steady-state bias point condition, and may explain the sometimes contradictory results that can be found in the literature about the dependence of the flicker noise power spectral density on gate bias.

Mimicking Neurotransmitter Release in Chemical Synapses via Hysteresis Engineering in MoS2 Transistors.

PubMed

Arnold, Andrew J; Razavieh, Ali; Nasr, Joseph R; Schulman, Daniel S; Eichfeld, Chad M; Das, Saptarshi

2017-03-28

Neurotransmitter release in chemical synapses is fundamental to diverse brain functions such as motor action, learning, cognition, emotion, perception, and consciousness. Moreover, improper functioning or abnormal release of neurotransmitter is associated with numerous neurological disorders such as epilepsy, sclerosis, schizophrenia, Alzheimer's disease, and Parkinson's disease. We have utilized hysteresis engineering in a back-gated MoS 2 field effect transistor (FET) in order to mimic such neurotransmitter release dynamics in chemical synapses. All three essential features, i.e., quantal, stochastic, and excitatory or inhibitory nature of neurotransmitter release, were accurately captured in our experimental demonstration. We also mimicked an important phenomenon called long-term potentiation (LTP), which forms the basis of human memory. Finally, we demonstrated how to engineer the LTP time by operating the MoS 2 FET in different regimes. Our findings could provide a critical component toward the design of next-generation smart and intelligent human-like machines and human-machine interfaces.

Unstable Resonator Mid-Infrared Laser Sources

DTIC Science & Technology

2016-02-26

of individual materials depending on metal species and growth temperatures . Fig. 8 (a) Average power consumption and (b) delay of C2MOS and double...feedback lasers, chirped gratings, interferometric lithography, nanowire transistors, tunnel field- effect transistors, nanoscale epitaxial growth, nanowire...technical approaches. Approaches to wavelength tuning include thermal/operation temperature tuning [1], variable cavity length with cantilever/piezo

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor

NASA Astrophysics Data System (ADS)

Yang, Paul; Kim, Hyung Jun; Zheng, Hong; Beom, Geon Won; Park, Jong-Sung; Kang, Chi Jung; Yoon, Tae-Sik

2017-06-01

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor.

PubMed

Yang, Paul; Jun Kim, Hyung; Zheng, Hong; Won Beom, Geon; Park, Jong-Sung; Jung Kang, Chi; Yoon, Tae-Sik

2017-06-02

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Photothermoelectric and photovoltaic effects both present in MoS2

PubMed Central

Zhang, Youwei; Li, Hui; Wang, Lu; Wang, Haomin; Xie, Xiaomin; Zhang, Shi-Li; Liu, Ran; Qiu, Zhi-Jun

2015-01-01

As a finite-energy-bandgap alternative to graphene, semiconducting molybdenum disulfide (MoS2) has recently attracted extensive interest for energy and sensor applications. In particular for broad-spectral photodetectors, multilayer MoS2 is more appealing than its monolayer counterpart. However, little is understood regarding the physics underlying the photoresponse of multilayer MoS2. Here, we employ scanning photocurrent microscopy to identify the nature of photocurrent generated in multilayer MoS2 transistors. The generation and transport of photocurrent in multilayer MoS2 are found to differ from those in other low-dimensional materials that only contribute with either photovoltaic effect (PVE) or photothermoelectric effect (PTE). In multilayer MoS2, the PVE at the MoS2-metal interface dominates in the accumulation regime whereas the hot-carrier-assisted PTE prevails in the depletion regime. Besides, the anomalously large Seebeck coefficient observed in multilayer MoS2, which has also been reported by others, is caused by hot photo-excited carriers that are not in thermal equilibrium with the MoS2 lattice. PMID:25605348

Phosphorous doped p-type MoS2 polycrystalline thin films via direct sulfurization of Mo film

NASA Astrophysics Data System (ADS)

Momose, Tomohiro; Nakamura, Atsushi; Daniel, Moraru; Shimomura, Masaru

2018-02-01

We report on the successful synthesis of a p-type, substitutional doping at S-site, MoS2 thin film using Phosphorous (P) as the dopant. MoS2 thin films were directly sulfurized for molybdenum films by chemical vapor deposition technique. Undoped MoS2 film showed n-type behavior and P doped samples showed p-type behavior by Hall-effect measurements in a van der Pauw (vdP) configuration of 10×10 mm2 area samples and showed ohmic behavior between the silver paste contacts. The donor and the acceptor concentration were detected to be ˜2.6×1015 cm-3 and ˜1.0×1019 cm-3, respectively. Hall-effect mobility was 61.7 cm2V-1s-1 for undoped and varied in the range of 15.5 ˜ 0.5 cm2V-1s-1 with P supply rate. However, the performance of field-effect transistors (FETs) declined by double Schottky barrier contacts where the region between Ni electrodes on the source/drain contact and the MoS2 back-gate cannot be depleted and behaves as a 3D material when used in transistor geometry, resulting in poor on/off ratio. Nevertheless, the FETs exhibit hole transport and the field-effect mobility showed values as high as the Hall-effect mobility, 76 cm2V-1s-1 in undoped MoS2 with p-type behavior and 43 cm2V-1s-1 for MoS2:P. Our findings provide important insights into the doping constraints for transition metal dichalcogenides.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

New highly linear tunable transconductor circuits with low number of MOS transistors

NASA Astrophysics Data System (ADS)

Yucel, Firat; Yuce, Erkan

2016-08-01

In this article, two new highly linear tunable transconductor circuits are proposed. The transconductors employ only six MOS transistors operated in saturation region. The second transconductor is derived from the first one with a slight modification. Transconductance of both transconductors can be tuned by a control voltage. Both of the transconductors do not need any additional bias voltages and currents. Another important feature of the transconductors is their high input and output impedances for cascadability with other circuits. Besides, total harmonic distortions are less than 1.5% for both transconductors. A positive lossless grounded inductor simulator with a grounded capacitor is given as an application example of the transconductors. Simulation and experimental test results are included to show effectiveness of the proposed circuits.

An ultra-low-voltage electronic implementation of inertial neuron model with nonmonotonous Liao's activation function.

PubMed

Kant, Nasir Ali; Dar, Mohamad Rafiq; Khanday, Farooq Ahmad

2015-01-01

The output of every neuron in neural network is specified by the employed activation function (AF) and therefore forms the heart of neural networks. As far as the design of artificial neural networks (ANNs) is concerned, hardware approach is preferred over software one because it promises the full utilization of the application potential of ANNs. Therefore, besides some arithmetic blocks, designing AF in hardware is the most important for designing ANN. While attempting to design the AF in hardware, the designs should be compatible with the modern Very Large Scale Integration (VLSI) design techniques. In this regard, the implemented designs should: only be in Metal Oxide Semiconductor (MOS) technology in order to be compatible with the digital designs, provide electronic tunability feature, and be able to operate at ultra-low voltage. Companding is one of the promising circuit design techniques for achieving these goals. In this paper, 0.5 V design of Liao's AF using sinh-domain technique is introduced. Furthermore, the function is tested by implementing inertial neuron model. The performance of the AF and inertial neuron model have been evaluated through simulation results, using the PSPICE software with the MOS transistor models provided by the 0.18-μm Taiwan Semiconductor Manufacturer Complementary Metal Oxide Semiconductor (TSM CMOS) process.

Electronic Subsystem Analysis (ESA)

DTIC Science & Technology

1977-01-01

than aluminum for the gate material, 0 Ion implanted source and draia regions, 0 Dielectrically isolated transistors. The use of a doped polysilicon gate...second level of interconnect ( polysilicon ). Ion implantation is essentially a precisely controllable pre-deposition of the required dopants. It’s use...discussed below). Radiation effects on MOS devices include the following: 0 Total Dose ol Dose Rate o Neutrons Because MOS technology is based on

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

PubMed

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Interface Properties of Atomic-Layer-Deposited Al2O3 Thin Films on Ultraviolet/Ozone-Treated Multilayer MoS2 Crystals.

PubMed

Park, Seonyoung; Kim, Seong Yeoul; Choi, Yura; Kim, Myungjun; Shin, Hyunjung; Kim, Jiyoung; Choi, Woong

2016-05-11

We report the interface properties of atomic-layer-deposited Al2O3 thin films on ultraviolet/ozone (UV/O3)-treated multilayer MoS2 crystals. The formation of S-O bonds on MoS2 after low-power UV/O3 treatment increased the surface energy, allowing the subsequent deposition of uniform Al2O3 thin films. The capacitance-voltage measurement of Au-Al2O3-MoS2 metal oxide semiconductor capacitors indicated n-type MoS2 with an electron density of ∼10(17) cm(-3) and a minimum interface trap density of ∼10(11) cm(-2) eV(-1). These results demonstrate the possibility of forming a high-quality Al2O3-MoS2 interface by proper UV/O3 treatment, providing important implications for their integration into field-effect transistors.

Remote hydrogen sensing techniques

NASA Technical Reports Server (NTRS)

Perry, Cortes L.

1992-01-01

The objective of this project is to evaluate remote hydrogen sensing methodologies utilizing metal oxide semi-conductor field effect transistors (MOS-FET) and mass spectrometric (MS) technologies and combinations thereof.

Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications

PubMed Central

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dechen; Tsuboi, Hidetoshi; Kitabayashi, Yuya; Matsumura, Daisuke; Shibata, Masanobu; Kudo, Takuya; Inaba, Masafumi; Hiraiwa, Atsushi

2017-01-01

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al2O3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and VB. PMID:28218234

Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications.

PubMed

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dechen; Tsuboi, Hidetoshi; Kitabayashi, Yuya; Matsumura, Daisuke; Shibata, Masanobu; Kudo, Takuya; Inaba, Masafumi; Hiraiwa, Atsushi

2017-02-20

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al 2 O 3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and V B .

Modification of the optoelectronic properties of two-dimensional MoS2 crystals by ultraviolet-ozone treatment

NASA Astrophysics Data System (ADS)

Yang, Hae In; Park, Seonyoung; Choi, Woong

2018-06-01

We report the modification of the optoelectronic properties of mechanically-exfoliated single layer MoS2 by ultraviolet-ozone exposure. Photoluminescence emission of pristine MoS2 monotonically decreased and eventually quenched as ultraviolet-ozone exposure time increased from 0 to 10 min. The reduction of photoluminescence emission accompanied reduction of Raman modes, suggesting structural degradation in ultraviolet-ozone exposed MoS2. Analysis with X-ray photoelectron spectroscopy revealed that the formation of Ssbnd O and Mosbnd O bonding increases with ultraviolet-ozone exposure time. Measurement of electrical transport properties of MoS2 in a bottom-gate thin-film transistor configuration suggested the presence of insulating MoO3 after ultraviolet-ozone exposure. These results demonstrate that ultraviolet-ozone exposure can significantly influence the optoelectronic properties of single layer MoS2, providing important implications on the application of MoS2 and other two-dimensional materials into optoelectronic devices.

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology

DTIC Science & Technology

2006-06-01

controlled oscillators. Varactor , transistor, and in- ductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between...quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 m result both good...millimeter wave, MOS varactor , quality factor, transmission line, voltage-controlled oscillator (VCO). I. INTRODUCTION WITH THE RAPID advance of high

A CCD Monolithic LMS Adaptive Analog Signal Processor Integrated Circuit.

DTIC Science & Technology

1980-03-01

adaptive filter with electrically- reprogrammable MOS analog conductance weights. I The analog and digital peripheral MOS on-chip circuits are provided with...electrically reprogrammable analog weights at tap positions along a CCD analog delay line in order to form a basic linear combiner for adaptive filtering...electrically reprogrammable analog conductance weights was introduced with the use of non-volatile MNOS memory 6-7 transistors biased in their triode

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Laser Direct Writing Process for Making Electrodes and High-k Sol-Gel ZrO2 for Boosting Performances of MoS2 Transistors.

PubMed

Kwon, Hyuk-Jun; Jang, Jaewon; Grigoropoulos, Costas P

2016-04-13

A series of two-dimensional (2D) transition metal dichalcogenides (TMDCs), including molybdenum disulfide (MoS2), can be attractive materials for photonic and electronic applications due to their exceptional properties. Among these unique properties, high mobility of 2D TMDCs enables realization of high-performance nanoelectronics based on a thin film transistor (TFT) platform. In this contribution, we report highly enhanced field effect mobility (μ(eff) = 50.1 cm(2)/(V s), ∼2.5 times) of MoS2 TFTs through the sol-gel processed high-k ZrO2 (∼22.0) insulator, compared to those of typical MoS2/SiO2/Si structures (μ(eff) = 19.4 cm(2)/(V s)) because a high-k dielectric layer can suppress Coulomb electron scattering and reduce interface trap concentration. Additionally, in order to avoid costly conventional mask based photolithography and define the patterns, we employ a simple laser direct writing (LDW) process. This process allows precise and flexible control with reasonable resolution (up to ∼10 nm), depending on the system, and enables fabrication of arbitrarily patterned devices. Taking advantage of continuing developments in laser technology offers a substantial cost decrease, and LDW may emerge as a promising technology.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Transistor analogs of emergent iono-neuronal dynamics.

PubMed

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

Low-frequency electronic noise in single-layer MoS2 transistors.

PubMed

Sangwan, Vinod K; Arnold, Heather N; Jariwala, Deep; Marks, Tobin J; Lauhon, Lincoln J; Hersam, Mark C

2013-09-11

Ubiquitous low-frequency 1/f noise can be a limiting factor in the performance and application of nanoscale devices. Here, we quantitatively investigate low-frequency electronic noise in single-layer transition metal dichalcogenide MoS2 field-effect transistors. The measured 1/f noise can be explained by an empirical formulation of mobility fluctuations with the Hooge parameter ranging between 0.005 and 2.0 in vacuum (<10(-5) Torr). The field-effect mobility decreased, and the noise amplitude increased by an order of magnitude in ambient conditions, revealing the significant influence of atmospheric adsorbates on charge transport. In addition, single Lorentzian generation-recombination noise was observed to increase by an order of magnitude as the devices were cooled from 300 to 6.5 K.

Rail-to-rail differential input amplification stage with main and surrogate differential pairs

DOEpatents

Britton, Jr., Charles Lanier; Smith, Stephen Fulton

2007-03-06

An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.

Pressurizing Field-Effect Transistors of Few-Layer MoS 2 in a Diamond Anvil Cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Yabin; Ke, Feng; Ci, Penghong

Hydrostatic pressure applied using diamond anvil cells (DAC) has been widely explored to modulate physical properties of materials by tuning their lattice degree of freedom. Independently, electrical field is able to tune the electronic degree of freedom of functional materials via, for example, the field-effect transistor (FET) configuration. Combining these two orthogonal approaches would allow discovery of new physical properties and phases going beyond the known phase space. Such experiments are, however, technically challenging and have not been demonstrated. In this paper, we report a feasible strategy to prepare and measure FETs in a DAC by lithographically patterning the nanodevicesmore » onto the diamond culet. Multiple-terminal FETs were fabricated in the DAC using few-layer MoS 2 and BN as the channel semiconductor and dielectric layer, respectively. It is found that the mobility, conductance, carrier concentration, and contact conductance of MoS 2 can all be significantly enhanced with pressure. Finally, we expect that the approach could enable unprecedented ways to explore new phases and properties of materials under coupled mechano-electrostatic modulation.« less

Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors.

PubMed

Roy, Tania; Tosun, Mahmut; Cao, Xi; Fang, Hui; Lien, Der-Hsien; Zhao, Peida; Chen, Yu-Ze; Chueh, Yu-Lun; Guo, Jing; Javey, Ali

2015-02-24

Two-dimensional layered semiconductors present a promising material platform for band-to-band-tunneling devices given their homogeneous band edge steepness due to their atomically flat thickness. Here, we experimentally demonstrate interlayer band-to-band tunneling in vertical MoS2/WSe2 van der Waals (vdW) heterostructures using a dual-gate device architecture. The electric potential and carrier concentration of MoS2 and WSe2 layers are independently controlled by the two symmetric gates. The same device can be gate modulated to behave as either an Esaki diode with negative differential resistance, a backward diode with large reverse bias tunneling current, or a forward rectifying diode with low reverse bias current. Notably, a high gate coupling efficiency of ∼80% is obtained for tuning the interlayer band alignments, arising from weak electrostatic screening by the atomically thin layers. This work presents an advance in the fundamental understanding of the interlayer coupling and electron tunneling in semiconductor vdW heterostructures with important implications toward the design of atomically thin tunnel transistors.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Dose measurement based on threshold shift in MOSFET arrays in commercial SRAMS

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Swift, G.

2002-01-01

A new method using an array of MOS transistors isdescribed for measuring dose absorbed from ionizingradiation. Using the array of MOSFETs in a SRAM, a direct measurement of the number of MOS cells which change as a function of applied bias on the SRAM. Since the input and output of a SRAM used as a dosimeter is completely digital, the measurement of dose is easily accessible by a remote processing system.

Improvement and Analysis of the Radiation Response of RADFET Dosimeters

DTIC Science & Technology

1992-06-15

TLD ), silicon p-i-n diode responses and silicon calorimetry (AWE Dosimetry Service). Intensive preparations were made by REM and the experiments were...SUB-GROUP dose: RADFET : tactical dosimetry silicon : metal-oxide- 0705 emiconductor (MOS) field effect transistor (FET) : silicon Idioxide space...1.1 Principle of a dosimetry system, based on the RADFET (radiation-sensitive field-effect transistor) (a) microscopic cross-section of chip (b) chip

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Observing Ambipolar Behavior and Bandgap Engineering of MoS2 with Transport Measurements

NASA Astrophysics Data System (ADS)

Morris, Rachael; Wilson, Cedric; Hamblin, Glen; Tsuchikawa, Ryuichi; Deshpande, Vikram V.

Molybdenum disulfide is a transition metal semiconductor with a relatively large bandgap about 1.8 eV. In MoS2\\ it is expected that the bandgap is layer dependent and changes with the application of strain. In this talk I will outline our attempt to make simple field effect transistors with thin MoS2 on flexible substrates. Our aim was to see the bandgap of MoS2 directly via transport measurements using electrolytic gating, then apply uniaxial strain to a single layer MoS2 device to see the bandgap change. This was to be one way of confirming theoretical expectations, as well as compare with experimental results already obtained through photoluminescence spectroscopy. Though we did not obtain our target result with this stage of the experiment, future experimental work is planned. I will discuss the experimental method, the challenges of obtaining data and the results we obtained.

Effect of interfaces on electron transport properties of MoS2-Au Contacts

NASA Astrophysics Data System (ADS)

Aminpour, Maral; Hapala, Prokop; Le, Duy; Jelinek, Pavel; Rahman, Talat S.; Rahman's Group Collaboration; Nanosurf Lab Collaboration

2014-03-01

Single layer MoS2 is a promising material for future electronic devices such as transistors since it has good transport characteristics with mobility greater than 200 cm-1V-1s-1 and on-off current ratios up to 108. However, before MoS2 can become a mainstream electronic material for the semiconductor industry, the design of low resistive metal-semiconductor junctions as contacts of the electronic devices needs to be addressed and studied systematically. We have examined the effect of Au contacts on the electronic transport properties of single layer MoS2 using density functional theory in combination with the non-equilibrium Green's function method. The Schottky barrier between Au contact and MoS2, transmission spectra, and I-V curves will be reported and discussed as a function of MoS2 and Au interfaces of varying geometry. This work is supported in part by the US Department of Energy under grant DE-FG02-07ER15842.

Wafer-scale production of highly uniform two-dimensional MoS2 by metal-organic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Kim, TaeWan; Mun, Jihun; Park, Hyeji; Joung, DaeHwa; Diware, Mangesh; Won, Chegal; Park, Jonghoo; Jeong, Soo-Hwan; Kang, Sang-Woo

2017-05-01

Semiconducting two-dimensional (2D) materials, particularly extremely thin molybdenum disulfide (MoS2) films, are attracting considerable attention from academia and industry owing to their distinctive optical and electrical properties. Here, we present the direct growth of a MoS2 monolayer with unprecedented spatial and structural uniformity across an entire 8 inch SiO2/Si wafer. The influences of growth pressure, ambient gases (Ar, H2), and S/Mo molar flow ratio on the MoS2 layered growth were explored by considering the domain size, nucleation sites, morphology, and impurity incorporation. Monolayer MoS2-based field effect transistors achieve an electron mobility of 0.47 cm2 V-1 s-1 and on/off current ratio of 5.4 × 104. This work demonstrates the potential for reliable wafer-scale production of 2D MoS2 for practical applications in next-generation electronic and optical devices.

Variability Analysis of MOS Differential Amplifier

NASA Astrophysics Data System (ADS)

Aoki, Masakazu; Seto, Kenji; Yamawaki, Taizo; Tanaka, Satoshi

Variation characteristics in MOS differential amplifier are evaluated by using the concise statistical model parameters for SPICE simulation. We find that the variation in the differential-mode gain, Adm, induced by the current factor variation, Δβ0, in the Id-variation of the differential MOS transistors is more than one order of magnitude larger than that induced by the threshold voltage variation, ΔVth, which has been regarded as a major factor for circuit variations in SoC's (2). The results obtained by the Monte Carlo simulations are verified by the theoretical analysis combined with the sensitivity analysis which clarifies the specific device parameter dependences of the variation in Adm.

Electrical and electronic devices and components: A compilation

NASA Technical Reports Server (NTRS)

1975-01-01

Components and techniques which may be useful in the electronics industry are described. Topics discussed include transducer technology, printed-circuit technology, solid state devices, MOS transistors, Gunn device, microwave antennas, and position indicators.

Combined electrical transport and capacitance spectroscopy of a MoS2-LiNbO3 field effect transistor

NASA Astrophysics Data System (ADS)

Michailow, Wladislaw; Schülein, Florian J. R.; Möller, Benjamin; Preciado, Edwin; Nguyen, Ariana E.; von Son, Gretel; Mann, John; Hörner, Andreas L.; Wixforth, Achim; Bartels, Ludwig; Krenner, Hubert J.

2017-01-01

We have measured both the current-voltage ( ISD - VGS ) and capacitance-voltage (C- VGS ) characteristics of a MoS2-LiNbO3 field effect transistor. From the measured capacitance, we calculate the electron surface density and show that its gate voltage dependence follows the theoretical prediction resulting from the two-dimensional free electron model. This model allows us to fit the measured ISD - VGS characteristics over the entire range of VGS . Combining this experimental result with the measured current-voltage characteristics, we determine the field effect mobility as a function of gate voltage. We show that for our device, this improved combined approach yields significantly smaller values (more than a factor of 4) of the electron mobility than the conventional analysis of the current-voltage characteristics only.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Thermal management in MoS2 based integrated device using near-field radiation

NASA Astrophysics Data System (ADS)

Peng, Jiebin; Zhang, Gang; Li, Baowen

2015-09-01

Recently, wafer-scale growth of monolayer MoS2 films with spatial homogeneity is realized on SiO2 substrate. Together with the latest reported high mobility, MoS2 based integrated electronic devices are expected to be fabricated in the near future. Owing to the low lattice thermal conductivity in monolayer MoS2, and the increased transistor density accompanied with the increased power density, heat dissipation will become a crucial issue for these integrated devices. In this letter, using the formalism of fluctuation electrodynamics, we explored the near-field radiative heat transfer from a monolayer MoS2 to graphene. We demonstrate that in resonance, the maximum heat transfer via near-field radiation between MoS2 and graphene can be ten times higher than the in-plane lattice thermal conduction for MoS2 sheet. Therefore, an efficient thermal management strategy for MoS2 integrated device is proposed: Graphene sheet is brought into close proximity, 10-20 nm from MoS2 device; heat energy transfer from MoS2 to graphene via near-field radiation; this amount of heat energy then be conducted to contact due to ultra-high lattice thermal conductivity of graphene. Our work sheds light for developing cooling strategy for nano devices constructing with low thermal conductivity materials.

Carbon-Nanotube-Confined Vertical Heterostructures with Asymmetric Contacts.

PubMed

Zhang, Jin; Zhang, Kenan; Xia, Bingyu; Wei, Yang; Li, Dongqi; Zhang, Ke; Zhang, Zhixing; Wu, Yang; Liu, Peng; Duan, Xidong; Xu, Yong; Duan, Wenhui; Fan, Shoushan; Jiang, Kaili

2017-10-01

Van der Waals (vdW) heterostructures have received intense attention for their efficient stacking methodology with 2D nanomaterials in vertical dimension. However, it is still a challenge to scale down the lateral size of vdW heterostructures to the nanometer and make proper contacts to achieve optimized performances. Here, a carbon-nanotube-confined vertical heterostructure (CCVH) is employed to address this challenge, in which 2D semiconductors are asymmetrically sandwiched by an individual metallic single-walled carbon nanotube (SWCNT) and a metal electrode. By using WSe 2 and MoS 2 , the CCVH can be made into p-type and n-type field effect transistors with high on/off ratios even when the channel length is 3.3 nm. A complementary inverter was further built with them, indicating their potential in logic circuits with a high integration level. Furthermore, the Fermi level of SWCNTs can be efficiently modulated by the gate voltage, making it competent for both electron and hole injection in the CCVHs. This unique property is shown by the transition of WSe 2 CCVH from unipolar to bipolar, and the transition of WSe 2 /MoS 2 from p-n junction to n-n junction under proper source-drain biases and gate voltages. Therefore, the CCVH, as a member of 1D/2D mixed heterostructures, shows great potentials in future nanoelectronics and nano-optoelectronics. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

NASA Astrophysics Data System (ADS)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

High speed capacitor-inverter based carbon nanotube full adder.

PubMed

Navi, K; Rashtian, M; Khatir, A; Keshavarzian, P; Hashemipour, O

2010-03-18

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Comparative Study on Graded-Barrier AlxGa1‑xN/AlN/GaN/Si Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistor by Using Ultrasonic Spray Pyrolysis Deposition Technique

NASA Astrophysics Data System (ADS)

Lee, Ching-Sung; Hsu, Wei-Chou; Huang, Yi-Ping; Liu, Han-Yin; Yang, Wen-Luh; Yang, Shen-Tin

2018-06-01

Comparative study on a novel Al2O3-dielectric graded-barrier (GB) AlxGa1‑xN/AlN/GaN/Si (x = 0.22 ∼ 0.3) metal-oxide-semiconductor heterostructure field-effect transistor (MOS-HFET) formed by using the ultrasonic spray pyrolysis deposition (USPD) technique has been made with respect to a conventional-barrier (CB) Al0.26Ga0.74N/AlN/GaN/Si MOS-HFET and the reference Schottky-gate HFET devices. The GB AlxGa1‑xN was devised to improve the interfacial quality and enhance the Schottky barrier height at the same time. A cost-effective ultrasonic spray pyrolysis deposition (USPD) method was used to form the high-k Al2O3 gate dielectric and surface passivation on the AlGaN barrier of the present MOS-HFETs. Comprehensive device performances, including maximum extrinsic transconductance (g m,max), maximum drain-source current density (I DS,max), gate-voltage swing (GVS) linearity, breakdown voltages, subthreshold swing (SS), on/off current ratio (I on /I off ), high frequencies, and power performance are investigated.

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Electrical Performance of Monolayer MoS2 Field-Effect Transistors Prepared by Chemical Vapor Deposition

DTIC Science & Technology

2013-05-16

Furthermore, MoS2 also shows promise for use in logic circuits and optoelectronic devices, and it is a promising material for use on flexible and...onto an auxiliary silicon substrate and placed inside a tube furnace with the growth substrates surrounding it. Sulfur powder, placed upstream near the...opening of the furnace at an approximate temperature of 600 C, was subli- mated for use as the sulfur vapor source. The furnace was heated to a peak

Inverter Circuits using Pentacene and ZnO Transistors

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2007-04-01

We report two types of integrated circuits based on a pentacene static-induction transistor (SIT), a pentacene thin-film transistor (TFT) and a zinc oxide (ZnO) TFT. The operating characteristics of a p-p inverter using pentacene SITs and a complementary inverter using a p-channel pentacene TFT and an n-channel ZnO TFT are described. The basic operation of logic circuits at a low voltage was achieved for the first time using the pentacene SIT inverter and complementary circuits with hybrid inorganic and organic materials. Furthermore, we describe the electrical properties of the ZnO films depending on sputtering conditions, and the complementary circuits using ZnO and pentacene TFTs.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Flexible active-matrix organic light-emitting diode display enabled by MoS2 thin-film transistor.

PubMed

Choi, Minwoo; Park, Yong Ju; Sharma, Bhupendra K; Bae, Sa-Rang; Kim, Soo Young; Ahn, Jong-Hyun

2018-04-01

Atomically thin molybdenum disulfide (MoS 2 ) has been extensively investigated in semiconductor electronics but has not been applied in a backplane circuitry of organic light-emitting diode (OLED) display. Its applicability as an active drive element is hampered by the large contact resistance at the metal/MoS 2 interface, which hinders the transport of carriers at the dielectric surface, which in turn considerably deteriorates the mobility. Modified switching device architecture is proposed for efficiently exploiting the high- k dielectric Al 2 O 3 layer, which, when integrated in an active matrix, can drive the ultrathin OLED display even in dynamic folding states. The proposed architecture exhibits 28 times increase in mobility compared to a normal back-gated thin-film transistor, and its potential as a wearable display attached to a human wrist is demonstrated.

Model for the Operation of a Monolayer MoS2 Thin-Film Transistor with Charges Trapped near the Channel Interface

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Park, Junghak; Kim, Deok-kee; Jeon, Sanghun

2017-04-01

We propose a model that describes the operation characteristics of a two-dimensional electron gas (2DEG) in a monolayer transition-metal dichalcogenide thin-film transistor (TFT) having trapped charges near the channel interface. We calculate the drift mobility of the carriers scattered by charged defects located in the channel or near the channel interfaces. The calculated drift mobility is a function of the 2DEG areal density of interface traps. Finally, we calculate the model transfer (ID-VG S ) and output (ID-VS D ) characteristics and verify them by comparing with the experimental results performed with monolayer MoS2 TFTs. We find the modeled results to be excellently consistent with the experiments. This proposed model can be utilized for measuring the interface-trapped charge and trap site densities from the measured transfer curves directly, avoiding more complicated and expensive measurement methods.

Flexible active-matrix organic light-emitting diode display enabled by MoS2 thin-film transistor

PubMed Central

Park, Yong Ju

2018-01-01

Atomically thin molybdenum disulfide (MoS2) has been extensively investigated in semiconductor electronics but has not been applied in a backplane circuitry of organic light-emitting diode (OLED) display. Its applicability as an active drive element is hampered by the large contact resistance at the metal/MoS2 interface, which hinders the transport of carriers at the dielectric surface, which in turn considerably deteriorates the mobility. Modified switching device architecture is proposed for efficiently exploiting the high-k dielectric Al2O3 layer, which, when integrated in an active matrix, can drive the ultrathin OLED display even in dynamic folding states. The proposed architecture exhibits 28 times increase in mobility compared to a normal back-gated thin-film transistor, and its potential as a wearable display attached to a human wrist is demonstrated. PMID:29713686

Improved dc and power performance of AlGaN/GaN high electron mobility transistors with Sc 2O 3 gate dielectric or surface passivation

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R. C.; Moser, N.; Gillespie, J. K.; Jessen, G. H.; Jenkins, T. J.; Yannuzi, M. J.; Via, G. D.; Crespo, A.

2003-10-01

The dc and power characteristics of AlGaN/GaN MOS-HEMTs with Sc 2O 3 gate dielectrics were compared with that of conventional metal-gate HEMTs fabricated on the same material. The MOS-HEMT shows higher saturated drain-source current (˜0.75 A/mm) and significantly better power-added efficiency (PAE, 27%) relative to the HEMT (˜0.6 A/mm and ˜5%). The Sc 2O 3 also provides effective surface passivation, with higher drain current, lower leakage currents and higher three-terminal breakdown voltage in passivated devices relative to unpassivated devices. The PAE also increases (from ˜5% to 12%) on the surface passivated HEMTs, showing that Sc 2O 3 is an attractive option for reducing gate and surface leakage in AlGaN/GaN heterostructure transistors.

Effect of buffer layer on photoresponse of MoS2 phototransistor

NASA Astrophysics Data System (ADS)

Miyamoto, Yuga; Yoshikawa, Daiki; Takei, Kuniharu; Arie, Takayuki; Akita, Seiji

2018-06-01

An atomically thin MoS2 field-effect transistor (FET) is expected as an ultrathin photosensor with high sensitivity. However, a persistent photoconductivity phenomenon prevents high-speed photoresponse. Here, we investigate the photoresponse of a MoS2 FET with a thin Al2O3 buffer layer on a SiO2 gate insulator. The application of a 2-nm-thick Al2O3 buffer layer greatly improves not only the steady state properties but also the response speed from 1700 to 0.2 s. These experimental results are well explained by the random localized potential fluctuation model combined with the model based on the recombination of the bounded electrons around the trapped hole.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Analysis of optical and electronic properties of MoS2 for optoelectronics and FET applications

NASA Astrophysics Data System (ADS)

Ullah, Muhammad S.; Yousuf, Abdul Hamid Bin; Es-Sakhi, Azzedin D.; Chowdhury, Masud H.

2018-04-01

Molybdenum disulfide (MoS2) is considered as a promising alternative to conventional semiconductor materials that used in the IC industry because of its novel properties. In this paper, we explore the optical and electronic properties of MoS2 for photodetector and transistors applications. This simulation is done using `DFT materials properties simulator'. Our findings show that mono- and multi-layer MoS2 is suitable for conventional and tunnel FET applications due to direct and indirect band-gap respectively. The bulk MoS2 crystal, which are composed of stacked layers have indirect bandgap and mono-layer MoS2 crystal form direct bandgap at the K-point of Brillouin zone. Indirect bandgap of bulk MoS2 crystal implies that phonons need to be involved in band-to-band tunneling (BTBT) process. Degenerately doped semiconductor, which is basically spinning the Fermi level, changing the DOS profile, and thinning the indirect bandgap that allow tunneling from valence band to conduction band. The optical properties of MoS2 is explored in terms of Absorption coefficient, extinction coefficient and refractive index. Our results shows that a MoS2 based photodetector can be fabricate to detect light in the visible range (below 500nm). It is also observed that the MoS2 is most sensitive for the light of wavelength 450nm.

Trilayer TMDC Heterostructures for MOSFETs and Nanobiosensors

NASA Astrophysics Data System (ADS)

Datta, Kanak; Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-02-01

Two dimensional materials such as transition metal dichalcogenides (TMDC) and their bi-layer/tri-layer heterostructures have become the focus of intense research and investigation in recent years due to their promising applications in electronics and optoelectronics. In this work, we have explored device level performance of trilayer TMDC heterostructure (MoS2/MX2/MoS2; M = Mo or, W and X = S or, Se) metal oxide semiconductor field effect transistors (MOSFETs) in the quantum ballistic regime. Our simulation shows that device `on' current can be improved by inserting a WS2 monolayer between two MoS2 monolayers. Application of biaxial tensile strain reveals a reduction in drain current which can be attributed to the lowering of carrier effective mass with increased tensile strain. In addition, it is found that gate underlap geometry improves electrostatic device performance by improving sub-threshold swing. However, increase in channel resistance reduces drain current. Besides exploring the prospect of these materials in device performance, novel trilayer TMDC heterostructure double gate field effect transistors (FETs) are proposed for sensing Nano biomolecules as well as for pH sensing. Bottom gate operation ensures these FETs operating beyond Nernst limit of 59 mV/pH. Simulation results found in this work reveal that scaling of bottom gate oxide results in better sensitivity while top oxide scaling exhibits an opposite trend. It is also found that, for identical operating conditions, proposed TMDC FET pH sensors show super-Nernst sensitivity indicating these materials as potential candidates in implementing such sensor. Besides pH sensing, all these materials show high sensitivity in the sub-threshold region as a channel material in nanobiosensor while MoS2/WS2/MoS2 FET shows the least sensitivity among them.

Low-power low-voltage superior-order curvature corrected voltage reference

NASA Astrophysics Data System (ADS)

Popa, Cosmin

2010-06-01

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

Hydrogen-induced reversible changes in drain current in Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2004-06-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage) are approximately an order of magnitude larger than for Pt/GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide-semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10% H2/90% N2 ambients relative to pure N2 and is due to catalytic dissociation of the H2 on the Pt contact, followed by diffusion to the Sc2O3/AlGaN interface.

Extraordinary attributes of 2-dimensional MoS2 nanosheets

NASA Astrophysics Data System (ADS)

Rao, C. N. R.; Maitra, Urmimala; Waghmare, Umesh V.

2014-08-01

The discovery of the amazing properties of graphene has stimulated exploration of single- and few-layer structures of layered inorganic materials. Of all the inorganic 2D nanosheet structures, those of MoS2 have attracted great attention because of their novel properties such as the presence of a direct bandgap, good field-effect transistor characteristics, large spin-orbit splitting, intense photoluminescence, catalytic properties, magnetism, superconductivity, ferroelectricity and several other properties with potential applications in electronics, optoelectronics, energy devices and spintronics. MoS2 nanosheets have been used in lithium batteries, supercapacitors and to generate hydrogen. Highlights of the impressive properties of MoS2 nanosheets, along with their structural and spectroscopic features are presented in this Letter. MoS2 typifies the family of metal dichalcogenides such as MoSe2 and WS2 and there is much to be done on nanosheets of these materials. Linus Pauling would have been pleased to see how molybdenite whose structure he studied in 1923 has become so important today.

Metal–insulator transition in a transition metal dichalcogenide: Dependence on metal contacts

NASA Astrophysics Data System (ADS)

Shimazu, Y.; Arai, K.; Iwabuchi, T.

2018-03-01

Transition metal dichalcogenides are promising layered materials for realizing novel nanoelectronic and nano-optoelectronic devices. Molybdenum disulfide (MoS2), a typical transition metal dichalcogenide, has been extensively investigated due to the presence of a sizable band gap, which enables the use of MoS2 as a channel material in field-effect transistors (FET). The gate-voltage-tunable metal–insulator transition and superconductivity using MoS2 have been demonstrated in previous studies. These interesting phenomena can be considered as quantum phase transitions in two-dimensional systems. In this study, we observed that the transport properties of thin MoS2 flakes in FET geometry significantly depend on metal contacts. On comparing Ti/Au with Al contacts, it was found that the threshold voltages for FET switching and metal–insulator transition were considerably lower for the device with Al contacts. This result indicated the significant influence of the Al contacts on the properties of MoS2 devices.

High performance MoS2 TFT using graphene contact first process

NASA Astrophysics Data System (ADS)

Chang Chien, Chih-Shiang; Chang, Hsun-Ming; Lee, Wei-Ta; Tang, Ming-Ru; Wu, Chao-Hsin; Lee, Si-Chen

2017-08-01

An ohmic contact of graphene/MoS2 heterostructure is determined by using ultraviolet photoelectron spectroscopy (UPS). Since graphene shows a great potential to replace metal contact, a direct comparison of Cr/Au contact and graphene contact on the MoS2 thin film transistor (TFT) is made. Different from metal contacts, the work function of graphene can be modulated. As a result, the subthreshold swing can be improved. And when Vg

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Back-gated Nb-doped MoS2 junctionless field-effect-transistors

NASA Astrophysics Data System (ADS)

Mirabelli, Gioele; Schmidt, Michael; Sheehan, Brendan; Cherkaoui, Karim; Monaghan, Scott; Povey, Ian; McCarthy, Melissa; Bell, Alan P.; Nagle, Roger; Crupi, Felice; Hurley, Paul K.; Duffy, Ray

2016-02-01

Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb). The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm) deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm-3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM) structure, showing a promising contact resistivity of 1.05 × 10-7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

Electrical characteristics of multilayer MoS2 FET's with MoS2/graphene heterojunction contacts.

PubMed

Kwak, Joon Young; Hwang, Jeonghyun; Calderon, Brian; Alsalman, Hussain; Munoz, Nini; Schutter, Brian; Spencer, Michael G

2014-08-13

The electrical properties of multilayer MoS2/graphene heterojunction transistors are investigated. Temperature-dependent I-V measurements indicate the concentration of unintentional donors in exfoliated MoS2 to be 3.57 × 10(11) cm(-2), while the ionized donor concentration is determined as 3.61 × 10(10) cm(-2). The temperature-dependent measurements also reveal two dominant donor levels, one at 0.27 eV below the conduction band and another located at 0.05 eV below the conduction band. The I-V characteristics are asymmetric with drain bias voltage and dependent on the junction used for the source or drain contact. I-V characteristics of the device are consistent with a long channel one-dimensional field-effect transistor model with Schottky contact. Utilizing devices, which have both graphene/MoS2 and Ti/MoS2 contacts, the Schottky barrier heights of both interfaces are measured. The charge transport mechanism in both junctions was determined to be either thermionic-field emission or field emission depending on bias voltage and temperature. On the basis of a thermionic field emission model, the barrier height at the graphene/MoS2 interface was determined to be 0.23 eV, while the barrier height at the Ti/MoS2 interface was 0.40 eV. The value of Ti/MoS2 barrier is higher than previously reported values, which did not include the effects of thermionic field emission.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Low-frequency noise in multilayer MoS2 field-effect transistors: the effect of high-k passivation.

PubMed

Na, Junhong; Joo, Min-Kyu; Shin, Minju; Huh, Junghwan; Kim, Jae-Sung; Piao, Mingxing; Jin, Jun-Eon; Jang, Ho-Kyun; Choi, Hyung Jong; Shim, Joon Hyung; Kim, Gyu-Tae

2014-01-07

Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

Encapsulation of Mo2C in MoS2 inorganic fullerene-like nanoparticles and nanotubes

NASA Astrophysics Data System (ADS)

Wiesel, Inna; Popovitz-Biro, Ronit; Tenne, Reshef

2013-01-01

Mo2C nanoparticles encapsulated within MoS2 inorganic fullerene-like nanoparticles and nanotubes were produced by carbothermal reaction at 1200-1300 °C inside a vertical induction furnace. The particles were analyzed using various electron microscopy techniques and complementary methods.

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Graphene as tunable contact for high performance thin film transistor

NASA Astrophysics Data System (ADS)

Liu, Yuan

Graphene has been one of the most extensively studied materials due to its unique band structure, the linear dispersion at the K point. It gives rise to novel phenomena, such as the anomalous quantum Hall effect, and has opened up a new category of "Fermi-Dirac" physics. Graphene has also attracted enormous attention for future electronics because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. However, graphene has zero intrinsic band gap, thus can not be used as the active channel material for logic transistors with sufficient on/off current ratio. Previous approaches to address this challenge include the induction of a transport gap in graphene nanostructures or bilayer graphene. However, these approaches have proved successful in improving the on-- off ratio of the resulting devices, but often at a severe sacrifice of the deliverable current density. Alternatively, with a finite density of states, tunable work-function and optical transparency, graphene can function as a unique tunable contact material to create a new structure of electronic devices. In this thesis, I will present my effort toward on-off ratio of graphene based vertical thin film transistor. I will include the work form four of my first author publication. I will first present my research studies on the a dramatic enhancement of the overall quantum efficiency and spectral selectivity of graphene photodetector, by coupling with plasmonic nanostructures. It is observed that metallic plasmonic nanostructures can be integrated with graphene photodetectors to greatly enhance the photocurrent and external quantum efficiency by up to 1,500%. Plasmonic nanostructures of variable resonance frequencies selectively amplify the photoresponse of graphene to light of different wavelengths, enabling highly specific detection of multicolours. Then I will show a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 105. The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. Furthermore, I will, demonstrate a new design strategy for vertical OTFT with ultra-short channel length without using conventional high-resolution lithography process. They can deliver a high current density over 1.8 A/ cm2 and thus enable a high cutoff frequency devices (~ 0.4 MHz) comparable with the ultra-short channel organic transistors. Importantly, with unique vertical architecture, the entire organic channel material is sandwiched between the source and drain electrodes and is thus naturally protected to ensure excellent air-stability. Finally I will present a new strategy by using graphene as the back electrodes to achieve Ohmic contact to MoS2. With a finite density of states, the Fermi level of graphene can be readily tuned by a gate potential to enable a nearly perfect band alignment with MoS2. For the first time, a transparent contact to MoS2 is demonstrated with zero contact barrier and linear output behaviour at cryogenic temperatures (down to 1.9 K) for both monolayer and multilayer MoS2. Benefiting from the barrier-free transparent contacts, we show that a metal-insulator-transition (MIT) can be observed in a two-terminal MoS2 device, a phenomenon that could be easily masked by Schottky barriers found in conventional metal-contacted MoS2 devices. With further passivation by boron nitride (BN) encapsulation, we demonstrate a record-high extrinsic (two-terminal) field effect mobility up to 1300 cm2/V s in MoS2 at low temperature. These findings can open up exciting new opportunities for atomically thin 2D semiconductors as well as other conventional semiconductors in general.

Total Ionizing Dose Effects on Strained Ge pMOS FinFETs on Bulk Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, En Xia; Fleetwood, Daniel M.; Hachtel, Jordan A.

2016-12-02

In this paper, we have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO 2) show minimal transconductance degradation (less than 5%), very small V th shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p MOS FinFETs is far superior to that of past generations of planar Ge pmore » MOS devices. Finally, these improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology.« less

Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET

NASA Astrophysics Data System (ADS)

Qian, Qingkai; Zhang, Zhaofu; Hua, Mengyuan; Wei, Jin; Lei, Jiacheng; Chen, Kevin J.

2017-12-01

Remote N2 plasma treatment is explored as a surface functionalization technique to deposit ultrathin high-k dielectric on single-layer MoS2. The ultrathin dielectric is used as a tunneling contact layer, which also serves as an interfacial layer below the gate region for fabricating top-gate MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs). The fabricated devices exhibited small hysteresis and mobility as high as 14 cm2·V-1·s-1. The contact resistance was significantly reduced, which resulted in the increase of drain current from 20 to 56 µA/µm. The contact resistance reduction can be attributed to the alleviated metal-MoS2 interface reaction and the preserved conductivity of MoS2 below the source/drain metal contact.

NANOELECTRONICS. Epitaxial growth of a monolayer WSe2-MoS2 lateral p-n junction with an atomically sharp interface.

PubMed

Li, Ming-Yang; Shi, Yumeng; Cheng, Chia-Chin; Lu, Li-Syuan; Lin, Yung-Chang; Tang, Hao-Lin; Tsai, Meng-Lin; Chu, Chih-Wei; Wei, Kung-Hwa; He, Jr-Hau; Chang, Wen-Hao; Suenaga, Kazu; Li, Lain-Jong

2015-07-31

Two-dimensional transition metal dichalcogenides (TMDCs) such as molybdenum sulfide MoS2 and tungsten sulfide WSe2 have potential applications in electronics because they exhibit high on-off current ratios and distinctive electro-optical properties. Spatially connected TMDC lateral heterojunctions are key components for constructing monolayer p-n rectifying diodes, light-emitting diodes, photovoltaic devices, and bipolar junction transistors. However, such structures are not readily prepared via the layer-stacking techniques, and direct growth favors the thermodynamically preferred TMDC alloys. We report the two-step epitaxial growth of lateral WSe2-MoS2 heterojunction, where the edge of WSe2 induces the epitaxial MoS2 growth despite a large lattice mismatch. The epitaxial growth process offers a controllable method to obtain lateral heterojunction with an atomically sharp interface. Copyright © 2015, American Association for the Advancement of Science.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Aqueous gating of van der Waals materials on bilayer nanopaper.

PubMed

Bao, Wenzhong; Fang, Zhiqiang; Wan, Jiayu; Dai, Jiaqi; Zhu, Hongli; Han, Xiaogang; Yang, Xiaofeng; Preston, Colin; Hu, Liangbing

2014-10-28

In this work, we report transistors made of van der Waals materials on a mesoporous paper with a smooth nanoscale surface. The aqueous transistor has a novel planar structure with source, drain, and gate electrodes on the same surface of the paper, while the mesoporous paper is used as an electrolyte reservoir. These transistors are enabled by an all-cellulose paper with nanofibrillated cellulose (NFC) on the top surface that leads to an excellent surface smoothness, while the rest of the microsized cellulose fibers can absorb electrolyte effectively. Based on two-dimensional van der Waals materials, including MoS2 and graphene, we demonstrate high-performance transistors with a large on-off ratio and low subthreshold swing. Such planar transistors with absorbed electrolyte gating can be used as sensors integrated with other components to form paper microfluidic systems. This study is significant for future paper-based electronics and biosensors.

Transport properties and device-design of Z-shaped MoS2 nanoribbon planar junctions

NASA Astrophysics Data System (ADS)

Zhang, Hua; Zhou, Wenzhe; Liu, Qi; Yang, Zhixiong; Pan, Jiangling; Ouyang, Fangping; Xu, Hui

2017-09-01

Based on MoS2 nanoribbons, metal-semiconductor-metal planar junction devices were constructed. The electronic and transport properties of the devices were studied by using density function theory (DFT) and nonequilibrium Green's functions (NEGF). It is found that a band gap about 0.4 eV occurs in the planar junction. The electron and hole transmissions of the devices are mainly contributed by the Mo atomic orbitals. The electron transport channel is located at the edge of armchair MoS2 nanoribbon, while the hole transport channel is delocalized in the channel region. The I-V curve of the two-probe device shows typical transport behavior of Schottky barrier, and the threshold voltage is of about 0.2 V. The field effect transistors (FET) based on the planar junction turn out to be good bipolar transistors, the maximum current on/off ratio can reach up to 1 × 104, and the subthreshold swing is 243 mV/dec. It is found that the off-state current is dependent on the length and width of the channel, while the on-state current is almost unaffected. The switching performance of the FET is improved with increasing the length of the channel, and shows oscillation behavior with the change of the channel width.

Solution-processed hybrid organic-inorganic complementary thin-film transistor inverter

NASA Astrophysics Data System (ADS)

Cheong, Heajeong; Kuribara, Kazunori; Ogura, Shintaro; Fukuda, Nobuko; Yoshida, Manabu; Ushijima, Hirobumi; Uemura, Sei

2016-04-01

We investigated hybrid organic-inorganic complementary inverters with a solution-processed indium-gallium-zinc-oxide (IGZO) n-channel thin-film transistor (TFT) and p-channel TFTs using the high-uniformity polymer poly[2,5-bis(alkyl)pyrrolo[3,4-c]pyrrolo-1,4(2H,5H)-dione-alt-5,5-di(thiophene-2-yl)-2,2-(E)-2-(2-(thiophen-2-yl)vinyl)thiophene] (PDVT-10). The IGZO TFT was fabricated at 150 °C for 1 min. It showed a high field-effect mobility of 0.9 cm2·V-1·s-1 and a high on/off current ratio of 107. A hybrid complementary inverter was fabricated by combining IGZO with a PDVT-10 thin-film transistor and its operation was confirmed.

Hydrogen sensors based on Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Baik, K. H.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2005-05-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage at 25 °C for the HEMTs and a change in forward current of 40 μA at a bias of 2.5 V was obtained for the MOS-diodes in response to a change in ambient from pure N2 to 10% H2/90% N2. The current changes in the latter case are almost linearly proportional to the testing temperature and reach around 400 μA at 400 °C. These signals are approximately an order of magnitude larger than for Pt /GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10%H2/90%N₂ ambients relative to pure N₂ and is due to catalytic dissociation of the H₂ on the Pt contact, followed by diffusion to the Sc₂O₃/AlGaN interface.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

PubMed Central

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

MoS2-InGaZnO Heterojunction Phototransistors with Broad Spectral Responsivity.

PubMed

Yang, Jaehyun; Kwak, Hyena; Lee, Youngbin; Kang, Yu-Seon; Cho, Mann-Ho; Cho, Jeong Ho; Kim, Yong-Hoon; Jeong, Seong-Jun; Park, Seongjun; Lee, Hoo-Jeong; Kim, Hyoungsub

2016-04-06

We introduce an amorphous indium-gallium-zinc-oxide (a-IGZO) heterostructure phototransistor consisting of solution-based synthetic molybdenum disulfide (few-layered MoS2, with a band gap of ∼1.7 eV) and sputter-deposited a-IGZO (with a band gap of ∼3.0 eV) films as a novel sensing element with a broad spectral responsivity. The MoS2 and a-IGZO films serve as a visible light-absorbing layer and a high mobility channel layer, respectively. Spectroscopic measurements reveal that appropriate band alignment at the heterojunction provides effective transfer of the visible light-induced electrons generated in the few-layered MoS2 film to the underlying a-IGZO channel layer with a high carrier mobility. The photoresponse characteristics of the a-IGZO transistor are extended to cover most of the visible range by forming a heterojunction phototransistor that harnesses a visible light responding MoS2 film with a small band gap prepared through a large-area synthetic route. The MoS2-IGZO heterojunction phototransistors exhibit a photoresponsivity of approximately 1.7 A/W at a wavelength of 520 nm (an optical power of 1 μW) with excellent time-dependent photoresponse dynamics.

Experimental detection of active defects in few layers MoS2 through random telegraphic signals analysis observed in its FET characteristics

NASA Astrophysics Data System (ADS)

Fang, Nan; Nagashio, Kosuke; Toriumi, Akira

2017-03-01

Transition-metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS2), are expected to be promising for next generation device applications. The existence of sulfur vacancies formed in MoS2, however, will potentially make devices unstable and problematic. Random telegraphic signals (RTSs) have often been studied in small area Si metal-oxide-semiconductor field-effect transistors (MOSFETs) to identify the carrier capture and emission processes at defects. In this paper, we have systemically analyzed RTSs observed in atomically thin layer MoS2 FETs. Several types of RTSs have been analyzed. One is the simple on/off type of telegraphic signals, the second is multilevel telegraphic signals with a superposition of the simple signals, and the third is multilevel telegraphic signals that are correlated with each other. The last one is discussed from the viewpoint of the defect-defect interaction in MoS2 FETs with a weak screening in atomically confined two-dimensional electron-gas systems. Furthermore, the position of defects causing RTSs has also been investigated by preparing MoS2 FETs with multi-probes. The electron beam was locally irradiated to intentionally generate defects in the MoS2 channel. It is clearly demonstrated that the MoS2 channel is one of the RTS origins. RTS analysis enables us to analyze the defect dynamics of TMD devices.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors. I. Analytical modeling of time-dependent characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Cramer, T.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

Metal-oxide-semiconductor (MOS) transistors fabricated with pentacene thin films were characterized by temperature-dependent current-voltage (I-V) characteristics, time-dependent current measurements, and admittance spectroscopy. The channel mobility shows almost linear variation with temperature, suggesting that only shallow traps are present in the semiconductor and at the oxide/semiconductor interface. The admittance spectra feature a broad peak, which can be modeled as the sum of a continuous distribution of relaxation times. The activation energy of this peak is comparable to the polaron binding energy in pentacene. The absence of trap signals in the admittance spectra confirmed that both the semiconductor and the oxide/semiconductor interface have negligible density of deep traps, likely owing to the passivation of SiO2 before pentacene growth. Nevertheless, current instabilities were observed in time-dependent current measurements following the application of gate-voltage pulses. The corresponding activation energy matches the energy of a hole trap in SiO2. We show that hole trapping in the oxide can explain both the temperature and the time dependences of the current instabilities observed in pentacene MOS transistors. The combination of these experimental techniques allows us to derive a comprehensive model for charge transport in hybrid architectures where trapping processes occur at various time and length scales.

Direct observation of inversion capacitance in p-type diamond MOS capacitors with an electron injection layer

NASA Astrophysics Data System (ADS)

Matsumoto, Tsubasa; Kato, Hiromitsu; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Yamasaki, Satoshi; Imura, Masataka; Ueda, Akihiro; Inokuma, Takao; Tokuda, Norio

2018-04-01

The electrical properties of Al2O3/p-type diamond (111) MOS capacitors were studied with the goal of furthering diamond-based semiconductor research. To confirm the formation of an inversion layer in the p-type diamond body, an n-type layer for use as a minority carrier injection layer was selectively deposited onto p-type diamond. To form the diamond MOS capacitors, Al2O3 was deposited onto OH-terminated diamond using atomic layer deposition. The MOS capacitor showed clear inversion capacitance at 10 Hz. The minority carrier injection from the n-type layer reached the inversion n-channel diamond MOS field-effect transistor (MOSFET). Using the high-low frequency capacitance method, the interface state density, D it, within an energy range of 0.1-0.5 eV from the valence band edge energy, E v, was estimated at (4-9) × 1012 cm-2 eV-1. However, the high D it near E v remains an obstacle to improving the field effect mobility for the inversion p-channel diamond MOSFET.

Oxidation of gallium arsenide in a plasma multipole device. Study of the MOS structures obtained

NASA Technical Reports Server (NTRS)

Gourrier, S.; Mircea, A.; Simondet, F.

1980-01-01

The oxygen plasma oxidation of GaAs was studied in order to obtain extremely high frequency responses with MOS devices. In the multipole system a homogeneous oxygen plasma of high density can easily be obtained in a large volume. This system is thus convenient for the study of plasma oxidation of GaAs. The electrical properties of the MOS diodes obtained in this way are controlled by interface states, located mostly in the upper half of the band gap where densities in the 10 to the 13th power/(sq cm) (eV) range can be estimated. Despite these interface states the possibility of fabricating MOSFET transistors working mostly in the depletion mode for a higher frequency cut-off still exists.

Polarization-dependent optical absorption of MoS₂ for refractive index sensing.

PubMed

Tan, Yang; He, Ruiyun; Cheng, Chen; Wang, Dong; Chen, Yanxue; Chen, Feng

2014-12-17

As a noncentrosymmetric crystal with spin-polarized band structure, MoS2 nanomaterials have attracts increasing attention in many areas such as lithium ion batteries, flexible electronic devices, photoluminescence and valleytronics. The investigation of MoS2 is mainly focused on the electronics and spintronics instead of optics, which restrict its applications as key elements of photonics. In this work, we demonstrate the first observation of the polarization-dependent optical absorption of the MoS2 thin film, which is integrated onto an optical waveguide device. With this feature, a novel optical sensor combining MoS2 thin-film and a microfluidic structure has been constituted to achieve the sensitive monitoring of refractive index. Our work indicates the MoS2 thin film as a complementary material to graphene for the optical polarizer in the visible light range, and explores a new application direction of MoS2 nanomaterials for the construction of photonic circuits.

Polarization-dependent optical absorption of MoS2 for refractive index sensing

PubMed Central

Tan, Yang; He, Ruiyun; Cheng, Chen; Wang, Dong; Chen, Yanxue; Chen, Feng

2014-01-01

As a noncentrosymmetric crystal with spin-polarized band structure, MoS2 nanomaterials have attracts increasing attention in many areas such as lithium ion batteries, flexible electronic devices, photoluminescence and valleytronics. The investigation of MoS2 is mainly focused on the electronics and spintronics instead of optics, which restrict its applications as key elements of photonics. In this work, we demonstrate the first observation of the polarization-dependent optical absorption of the MoS2 thin film, which is integrated onto an optical waveguide device. With this feature, a novel optical sensor combining MoS2 thin-film and a microfluidic structure has been constituted to achieve the sensitive monitoring of refractive index. Our work indicates the MoS2 thin film as a complementary material to graphene for the optical polarizer in the visible light range, and explores a new application direction of MoS2 nanomaterials for the construction of photonic circuits. PMID:25516116

Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors

NASA Astrophysics Data System (ADS)

Sun, Xiao

As the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology. In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT). By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed. The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.

Scalable fabrication of a hybrid field-effect and acousto-electric device by direct growth of monolayer MoS2/LiNbO3

PubMed Central

Preciado, Edwin; Schülein, Florian J.R.; Nguyen, Ariana E.; Barroso, David; Isarraraz, Miguel; von Son, Gretel; Lu, I-Hsi; Michailow, Wladislaw; Möller, Benjamin; Klee, Velveth; Mann, John; Wixforth, Achim; Bartels, Ludwig; Krenner, Hubert J.

2015-01-01

Lithium niobate is the archetypical ferroelectric material and the substrate of choice for numerous applications including surface acoustic wave radio frequencies devices and integrated optics. It offers a unique combination of substantial piezoelectric and birefringent properties, yet its lack of optical activity and semiconducting transport hamper application in optoelectronics. Here we fabricate and characterize a hybrid MoS2/LiNbO3 acousto-electric device via a scalable route that uses millimetre-scale direct chemical vapour deposition of MoS2 followed by lithographic definition of a field-effect transistor structure on top. The prototypical device exhibits electrical characteristics competitive with MoS2 devices on silicon. Surface acoustic waves excited on the substrate can manipulate and probe the electrical transport in the monolayer device in a contact-free manner. We realize both a sound-driven battery and an acoustic photodetector. Our findings open directions to non-invasive investigation of electrical properties of monolayer films. PMID:26493867

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Summary of Research 2000: Department of Electrical and Computer Engineering

DTIC Science & Technology

2001-12-01

provides promising radiation hardening characteristics but the effect of microdose issues are not understood. As transistors shrink, trapping of small...examines the effects of enacting a microdose single event effect (SEE) upon a thick gate oxide of an SOI MOS capacitor in order to determine the degree

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Energetic mapping of oxide traps in MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Illarionov, Yury Yu; Knobloch, Theresia; Waltl, Michael; Rzepa, Gerhard; Pospischil, Andreas; Polyushkin, Dmitry K.; Furchi, Marco M.; Mueller, Thomas; Grasser, Tibor

2017-06-01

The performance of MoS2 transistors is strongly affected by charge trapping in oxide traps with very broad distributions of time constants. These defects degrade the mobility and additionally lead to the hysteresis of the gate transfer characteristics, which presents a crucial performance and reliability issue for these new technologies. Here we perform a detailed study of the hysteresis in double-gated MoS2 FETs and show that this issue is nothing else than a combination of threshold voltage shifts resulting from positive and negative bias-temperature instabilities. While these instabilities are well known from silicon devices, they are even more important in 2D devices given the considerably larger defect densities. Most importantly, the magnitudes of these threshold voltage shifts depend strongly on the density and energetic alignment of the active oxide traps. Based on this, we introduce the incremental hysteresis sweep method which allows for an accurate mapping of these defects and extract their energy distributions from simulations. By applying our method to analyze the impact of oxide traps situated in the Al2O3 top gate of several devices, we confirm its versatility. Since all 2D devices investigated so far suffer from a similar hysteresis behavior, the incremental hysteresis sweep method provides a unique and powerful way for the detailed characterization of their defect bands.

Vertical power MOS transistor as a thermoelectric quasi-nanowire device

NASA Astrophysics Data System (ADS)

Roizin, Gregory; Beeri, Ofer; Peretz, Mor Mordechai; Gelbstein, Yaniv

2016-12-01

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved.

Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui

2014-01-01

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (-27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Tunneling in BP-MoS2 heterostructure

NASA Astrophysics Data System (ADS)

Liu, Xiaochi; Qu, Deshun; Kim, Changsik; Ahmed, Faisal; Yoo, Won Jong

Tunnel field effect transistor (TFET) is considered to be a leading option for achieving SS <60 mV/dec. In this work, black phosphorus (BP) and molybdenum disulfide (MoS2) heterojunction devices are fabricated. We find that thin BP flake and MoS2 form normal p-n junctions, tunneling phenomena can be observed when BP thickness increases to certain level. PEO:CsClO4 is applied on the surface of the device together with a side gate electrode patterned together with source and drain electrodes. The Fermi level of MoS2 on top of BP layer can be modulated by the side gating, and this enables to vary the MoS2-BP tunnel diode property from off-state to on-state. Since tunneling is the working mechanism of MoS2-BP junction, and PEO:CsClO4\\ possesses ultra high dielectric constant and small equivalent oxide thickness (EOT), a low SS of 55 mV/dec is obtained from MoS2-BP TFET. This work was supported by the Global Research Laboratory and Global Frontier R&D Programs at the Center for Hybrid Interface Materials, both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea (NRF).

Interfacial Coupling Effect on Electron Transport in MoS2/SrTiO3 Heterostructure: An Ab-initio Study.

PubMed

Bano, Amreen; Gaur, N K

2018-01-15

A variety of theoretical and experimental works have reported several potential applications of MoS 2 monolayer based heterostructures (HSs) such as light emitting diodes, photodetectors and field effect transistors etc. In the present work, we have theoretically performed as a model case study, MoS 2 monolayer deposited over insulating SrTiO 3 (001) to study the band alignment at TiO 2 termination. The interfacial characteristics are found to be highly dependent on the interface termination. With an insulating oxide material, a significant band gap (0.85eV) is found in MoS 2 /TiO 2 interface heterostructure (HS). A unique electronic band profile with an indirect band gap (0.67eV) is observed in MoS 2 monolayer when confined in a cubic environment of SrTiO 3 (STO). Adsorption analysis showed the chemisorption of MoS 2 on the surface of STO substrate with TiO 2 termination which is justified by the charge density calculations that shows the existence of covalent bonding at the interface. The fabrication of HS of such materials paves the path for developing the unprecedented 2D materials with exciting properties such as semiconducting devices, thermoelectric and optoelectronic applications.

High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass.

PubMed

Shokouh, Seyed Hossein Hosseini; Pezeshki, Atiye; Ali Raza, Syed Raza; Lee, Hee Sung; Min, Sung-Wook; Jeon, Pyo Jin; Shin, Jae Min; Im, Seongil

2015-01-07

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices

NASA Astrophysics Data System (ADS)

Shaneyfelt, M. R.; Schwank, J. R.; Fleetwood, D. M.; Winokur, P. S.; Hughes, K. L.

1990-12-01

The electric field dependence of radiation-induced oxide- and interface-trap charge (Delta Vot and Delta Vit) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (Eox) from -4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of Delta Vot and the saturated value of Delta Vit for both polysilicon- and metal-gate transistors are shown to follow an approximate E exp -1/2 field dependence for Eox = 0.4 MV/cm or greater. An E exp -1/2 dependence for the saturated value of Delta Vit was also observed for negative-bias irradiation followed by a constant positive-bias anneal. The E exp -1/2 field dependence observed suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO2 interface for positive-bias irradiation or near the gate/SiO2 interface for negative bias irradiation, though H+ drift remains the likely rate-limiting step in the process. Based on these results, a hole-trapping/hydrogen transport model-involving hole trapping and subsequent near-interfacial H+ release, transport, and reaction at the interface-is proposed as a possible explanation of Delta Vit buildup in these polysilicon- and metal-gate transistors.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

PubMed

Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

PubMed Central

Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. PMID:24723808

Dual-mode MOS SOI nanoscale transistor serving as a building block for optical communication between blocks

NASA Astrophysics Data System (ADS)

Bendayan, Michael; Sabo, Roi; Zolberg, Roee; Mandelbaum, Yaakov; Chelly, Avraham; Karsenty, Avi

2017-02-01

We developed a new type of silicon MOSFET Quantum Well transistor, coupling both electronic and optical properties which should overcome the indirect silicon bandgap constraint, and serve as a future light emitting device in the range 0.8-2μm, as part of a new building block in integrated circuits allowing ultra-high speed processors. Such Quantum Well structure enables discrete energy levels for light recombination. Model and simulations of both optical and electric properties are presented pointing out the influence of the channel thickness and the drain voltage on the optical emission spectrum.

A New Mirroring Circuit for Power MOS Current Sensing Highly Immune to EMI

PubMed Central

Aiello, Orazio; Fiori, Franco

2013-01-01

This paper deals with the monitoring of power transistor current subjected to radio-frequency interference. In particular, a new current sensor with no connection to the power transistor drain and with improved performance with respect to the existing current-sensing schemes is presented. The operation of the above mentioned current sensor is discussed referring to time-domain computer simulations. The susceptibility of the proposed circuit to radio-frequency interference is evaluated through time-domain computer simulations and the results are compared with those obtained for a conventional integrated current sensor. PMID:23385408

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

NASA Technical Reports Server (NTRS)

Rao, Hariprasad Nannapaneni

1989-01-01

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.

Low Power Monolayer MoS2 Transistors for RF Applications

DTIC Science & Technology

2015-03-24

techniques. Some of this was done in-house, while others were done in collaboration with Dr. Madan Dubey’s team at the Army Research Laboratories...quality. In our work we have used a combination of room temperature and low temperature Raman and PL mapping (collaboration with Dr Madan Dubey’s lab

A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistor

NASA Technical Reports Server (NTRS)

Halsor, J. L.; Lin, H. C.

1974-01-01

Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Metal-semiconductor barrier modulation for high photoresponse in transition metal dichalcogenide field effect transistors.

PubMed

Li, Hua-Min; Lee, Dae-Yeong; Choi, Min Sup; Qu, Deshun; Liu, Xiaochi; Ra, Chang-Ho; Yoo, Won Jong

2014-02-10

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

PubMed

Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

2016-07-20

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

The damage equivalence of electrons, protons, and gamma rays in MOS devices

NASA Technical Reports Server (NTRS)

Brucker, G. J.; Stassinopoulos, E. G.; Van Gunten, O.; August, L. S.; Jordan, T. M.

1982-01-01

The results of laboratory tests to determine the radiation damage effects induced on MOS devices from Co-60, electron, and proton radiation are reported. The tests are performed to establish the relationship between the Co-60 gamma rays and the level of damage to the MOS devices in regards to different damages which can be expected with the electron and particle bombardments experienced in space applications. CMOS devices were exposed to the Co-60 gamma rays, 1 MeV electrons, and 1 MeV protons while operating at 3, 10, and 15 V. The test data indicated that the Co-60 source was reliable for an initial evaluation of the electron damages up to 2 MeV charge. A correction factor was devised for transferring the Co-60 measurements to proton damages, independent of bias and transistor types, for any orbit or environment.

Ferroelectric-Domain-Patterning-Controlled Schottky Junction State in Monolayer MoS 2

DOE PAGES

Xiao, Zhiyong; Song, Jingfeng; Ferry, David K.; ...

2017-06-08

Here, we exploit scanning probe controlled domain patterning in a ferroelectric top-layer to induce nonvolatile modulation of the conduction characteristic of monolayer MoS 2 between a transistor and a junction state. In the presence of a domain wall, MoS 2 exhibits rectified I-V that is well described by the thermionic emission model. The induced Schottky barrier height Φ eff Β varies from 0.38 eV to 0.57 eV and is tunabe by a SiO 2 global back-gate, while the tuning range of Φ eff Β the barrier height depends sensitively on the conduction band tail trapping states. Our work points tomore » a new route to achieve programmable functionalities in van der Waals materials and sheds light on the critical performance limiting factors in these hybrid systems.« less

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Resonant tunneling through discrete quantum states in stacked atomic-layered MoS2.

PubMed

Nguyen, Linh-Nam; Lan, Yann-Wen; Chen, Jyun-Hong; Chang, Tay-Rong; Zhong, Yuan-Liang; Jeng, Horng-Tay; Li, Lain-Jong; Chen, Chii-Dong

2014-05-14

Two-dimensional crystals can be assembled into three-dimensional stacks with atomic layer precision, which have already shown plenty of fascinating physical phenomena and been used for prototype vertical-field-effect-transistors.1,2 In this work, interlayer electron tunneling in stacked high-quality crystalline MoS2 films were investigated. A trilayered MoS2 film was sandwiched between top and bottom electrodes with an adjacent bottom gate, and the discrete energy levels in each layer could be tuned by bias and gate voltages. When the discrete energy levels aligned, a resonant tunneling peak appeared in the current-voltage characteristics. The peak position shifts linearly with perpendicular magnetic field, indicating formation of Landau levels. From this linear dependence, the effective mass and Fermi velocity are determined and are confirmed by electronic structure calculations. These fundamental parameters are useful for exploitation of its unique properties.

Ferroelectric-Domain-Patterning-Controlled Schottky Junction State in Monolayer MoS 2

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiao, Zhiyong; Song, Jingfeng; Ferry, David K.

Here, we exploit scanning probe controlled domain patterning in a ferroelectric top-layer to induce nonvolatile modulation of the conduction characteristic of monolayer MoS 2 between a transistor and a junction state. In the presence of a domain wall, MoS 2 exhibits rectified I-V that is well described by the thermionic emission model. The induced Schottky barrier height Φ eff Β varies from 0.38 eV to 0.57 eV and is tunabe by a SiO 2 global back-gate, while the tuning range of Φ eff Β the barrier height depends sensitively on the conduction band tail trapping states. Our work points tomore » a new route to achieve programmable functionalities in van der Waals materials and sheds light on the critical performance limiting factors in these hybrid systems.« less

Role of Hole Trap Sites in MoS2 for Inconsistency in Optical and Electrical Phenomena.

PubMed

Tran, Minh Dao; Kim, Ji-Hee; Kim, Hyun; Doan, Manh Ha; Duong, Dinh Loc; Lee, Young Hee

2018-03-28

Because of strong Coulomb interaction in two-dimensional van der Waals-layered materials, the trap charges at the interface strongly influence the scattering of the majority carriers and thus often degrade their electrical properties. However, the photogenerated minority carriers can be trapped at the interface, modulate the electron-hole recombination, and eventually influence the optical properties. In this study, we report the role of the hole trap sites on the inconsistency in the electrical and optical phenomena between two systems with different interfacial trap densities, which are monolayer MoS 2 -based field-effect transistors (FETs) on hexagonal boron nitride (h-BN) and SiO 2 substrates. Electronic transport measurements indicate that the use of h-BN as a gate insulator can induce a higher n-doping concentration of the monolayer MoS 2 by suppressing the free-electron transfer from the intrinsically n-doped MoS 2 to the SiO 2 gate insulator. Nevertheless, optical measurements show that the electron concentration in MoS 2 /SiO 2 is heavier than that in MoS 2 /h-BN, manifested by the relative red shift of the A 1g Raman peak. The inconsistency in the evaluation of the electron concentration in MoS 2 by electrical and optical measurements is explained by the trapping of the photogenerated holes in the spatially modulated valence band edge of the monolayer MoS 2 caused by the local strain from the SiO 2 /Si substrate. This photoinduced electron doping in MoS 2 /SiO 2 is further confirmed by the development of the trion component in the power-dependent photoluminescence spectra and negative shift of the threshold voltage of the FET after illumination.

Fabrication of MoS2 biosensor to detect lower-concentrated area of biological molecules(Conference Presentation)

NASA Astrophysics Data System (ADS)

Yang, Erika; Ryu, Byunghoon; Nam, Hongsuk; Liang, Xiaogan

2017-03-01

Two dimensional layered transition metal dichalcogenides (TMDC) materials have the growing potential to upstage graphene in the next generation of biosensors in detecting lower-concentrated areas of biomolecules. The current gold-standard detection method is the enzyme-linked immunosorbent assay (ELISA), an immunological assay technique that makes use of an enzyme bonded to a particular antibody or antigen. However, this technique is not only bulky, labor-intensive, and time extensive, but more importantly, the ELISA has relatively low detection limits of only 600 femtomolar (fM). In this work, for the first time, we present a novel flexible, sensitive MoS2 (molybdenum disulfide) biosensor, as shown in Figure 1, composed of few-layer of MoS2 as the channel material, and flexible polyimide as the substrate. In order to nano-fabricate this flexible biosensor, we mechanically transferred a few layers of MoS2 onto the flexible substrate polyimide and photolithography to create a patterning on the surface, and as a result, we were able to create a transistor that used MoS2 as its conductance channel. We successfully fabricated this MoS2 biosensor onto a flexible polyimide substrate. Furthermore, the fabricated flexible MoS2 biosensor can be utilized for quantifying the time-dependent reaction kinetics of streptavidin-biotin binding. Figure 2 shows the transfer characteristics of flexible MoS2 biosensors measured under different concentrations of streptavidin. The flexible MoS2 biosensor could illustrate a faster detection time in matters of minutes, and higher sensitivity with detection limits as low as 10 fM. Time versus equilibrium constants will be presented in details.

A Novel and Facile Route to Synthesize Atomic-Layered MoS2 Film for Large-Area Electronics.

PubMed

Boandoh, Stephen; Choi, Soo Ho; Park, Ji-Hoon; Park, So Young; Bang, Seungho; Jeong, Mun Seok; Lee, Joo Song; Kim, Hyeong Jin; Yang, Woochul; Choi, Jae-Young; Kim, Soo Min; Kim, Ki Kang

2017-10-01

High-quality and large-area molybdenum disulfide (MoS 2 ) thin film is highly desirable for applications in large-area electronics. However, there remains a challenge in attaining MoS 2 film of reasonable crystallinity due to the absence of appropriate choice and control of precursors, as well as choice of suitable growth substrates. Herein, a novel and facile route is reported for synthesizing few-layered MoS 2 film with new precursors via chemical vapor deposition. Prior to growth, an aqueous solution of sodium molybdate as the molybdenum precursor is spun onto the growth substrate and dimethyl disulfide as the liquid sulfur precursor is supplied with a bubbling system during growth. To supplement the limiting effect of Mo (sodium molybdate), a supplementary Mo is supplied by dissolving molybdenum hexacarbonyl (Mo(CO) 6 ) in the liquid sulfur precursor delivered by the bubbler. By precisely controlling the amounts of precursors and hydrogen flow, full coverage of MoS 2 film is readily achievable in 20 min. Large-area MoS 2 field effect transistors (FETs) fabricated with a conventional photolithography have a carrier mobility as high as 18.9 cm 2 V -1 s -1 , which is the highest reported for bottom-gated MoS 2 -FETs fabricated via photolithography with an on/off ratio of ≈10 5 at room temperature. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Zero-static power radio-frequency switches based on MoS2 atomristors.

PubMed

Kim, Myungsoo; Ge, Ruijing; Wu, Xiaohan; Lan, Xing; Tice, Jesse; Lee, Jack C; Akinwande, Deji

2018-06-28

Recently, non-volatile resistance switching or memristor (equivalently, atomristor in atomic layers) effect was discovered in transitional metal dichalcogenides (TMD) vertical devices. Owing to the monolayer-thin transport and high crystalline quality, ON-state resistances below 10 Ω are achievable, making MoS 2 atomristors suitable as energy-efficient radio-frequency (RF) switches. MoS 2 RF switches afford zero-hold voltage, hence, zero-static power dissipation, overcoming the limitation of transistor and mechanical switches. Furthermore, MoS 2 switches are fully electronic and can be integrated on arbitrary substrates unlike phase-change RF switches. High-frequency results reveal that a key figure of merit, the cutoff frequency (f c ), is about 10 THz for sub-μm 2 switches with favorable scaling that can afford f c above 100 THz for nanoscale devices, exceeding the performance of contemporary switches that suffer from an area-invariant scaling. These results indicate a new electronic application of TMDs as non-volatile switches for communication platforms, including mobile systems, low-power internet-of-things, and THz beam steering.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Gate-Induced Metal–Insulator Transition in MoS 2 by Solid Superionic Conductor LaF 3

DOE PAGES

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin; ...

2018-03-23

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Vu, Quoc An; Fan, Sidi; Hyup Lee, Sang; Joo, Min-Kyu; Jong Yu, Woo; Lee, Young Hee

2018-07-01

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2  ×  109 cm‑2 eV‑1, a thousand times smaller than previously reported values.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Single-phase frequency converter

NASA Astrophysics Data System (ADS)

Baciu, I.; Cunţan, C. D.

2017-01-01

The paper presents a continuous voltage inverter - AC (12V / 230V) made with IGBT and two-stage voltage transformer. The sequence control transistors is achieved using a ring counter whose clock signal is obtained with a monostable circuit LM 555. The frequency of the clock signal can be adjustment with a potentiometer that modifies the charging current of the capacitor which causes constant monostable circuit time. Command sequence consists of 8 intervals of which 6 are assigned to command four transistors and two for the period break at the beginning and end of the sequence control. To obtain an alternation consisting of two different voltage level, two transistors will be comanded, connected to different windings of the transformer and the one connected to the winding providing lower voltage must be comanded twice. The output of the numerator goes through an inverter type MOS and a current amplifier with bipolar transistor.To achieve galvanic separation, an optocoupler will be used for each IGBT transistor, while protection is achieved with resistance and diode circuit. At the end there is connected an LC filter for smoothing voltage variations.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Tunable Electrical and Optical Characteristics in Monolayer Graphene and Few-Layer MoS2 Heterostructure Devices.

PubMed

Rathi, Servin; Lee, Inyeal; Lim, Dongsuk; Wang, Jianwei; Ochiai, Yuichi; Aoki, Nobuyuki; Watanabe, Kenji; Taniguchi, Takashi; Lee, Gwan-Hyoung; Yu, Young-Jun; Kim, Philip; Kim, Gil-Ho

2015-08-12

Lateral and vertical two-dimensional heterostructure devices, in particular graphene-MoS2, have attracted profound interest as they offer additional functionalities over normal two-dimensional devices. Here, we have carried out electrical and optical characterization of graphene-MoS2 heterostructure. The few-layer MoS2 devices with metal electrode at one end and monolayer graphene electrode at the other end show nonlinearity in drain current with drain voltage sweep due to asymmetrical Schottky barrier height at the contacts and can be modulated with an external gate field. The doping effect of MoS2 on graphene was observed as double Dirac points in the transfer characteristics of the graphene field-effect transistor (FET) with a few-layer MoS2 overlapping the middle part of the channel, whereas the underlapping of graphene have negligible effect on MoS2 FET characteristics, which showed typical n-type behavior. The heterostructure also exhibits a strongest optical response for 520 nm wavelength, which decreases with higher wavelengths. Another distinct feature observed in the heterostructure is the peak in the photocurrent around zero gate voltage. This peak is distinguished from conventional MoS2 FETs, which show a continuous increase in photocurrent with back-gate voltage. These results offer significant insight and further enhance the understanding of the graphene-MoS2 heterostructure.

Scalable Patterning of MoS2 Nanoribbons by Micromolding in Capillaries.

PubMed

Hung, Yu-Han; Lu, Ang-Yu; Chang, Yung-Huang; Huang, Jing-Kai; Chang, Jeng-Kuei; Li, Lain-Jong; Su, Ching-Yuan

2016-08-17

In this study, we report a facile approach to prepare dense arrays of MoS2 nanoribbons by combining procedures of micromolding in capillaries (MIMIC) and thermolysis of thiosalts ((NH4)2MoS4) as the printing ink. The obtained MoS2 nanoribbons had a thickness reaching as low as 3.9 nm, a width ranging from 157 to 465 nm, and a length up to 2 cm. MoS2 nanoribbons with an extremely high aspect ratio (length/width) of ∼7.4 × 10(8) were achieved. The MoS2 pattern can be printed on versatile substrates, such as SiO2/Si, sapphire, Au film, FTO/glass, and graphene-coated glass. The degree of crystallinity of the as-prepared MoS2 was discovered to be adjustable by varying the temperature through postannealing. The high-temperature thermolysis (1000 °C) results in high-quality conductive samples, and field-effect transistors based on the patterned MoS2 nanoribbons were demonstrated and characterized, where the carrier mobility was comparable to that of thin-film MoS2. In contrast, the low-temperature-treated samples (170 °C) result in a unique nanocrystalline MoSx structure (x ≈ 2.5), where the abundant and exposed edge sites were obtained from highly dense arrays of nanoribbon structures by this MIMIC patterning method. The patterned MoSx was revealed to have superior electrocatalytic efficiency (an overpotential of ∼211 mV at 10 mA/cm(2) and a Tafel slope of 43 mV/dec) in the hydrogen evolution reaction (HER) when compared to the thin-film MoS2. The report introduces a new concept for rapidly fabricating cost-effective and high-density MoS2/MoSx nanostructures on versatile substrates, which may pave the way for potential applications in nanoelectronics/optoelectronics and frontier energy materials.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

PubMed

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

PubMed

Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

2014-02-25

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

Integrated P-channel MOS gyrator

NASA Technical Reports Server (NTRS)

Hochmair, E. S. (Inventor)

1974-01-01

A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.

Graphene/MoS2 hybrid technology for large-scale two-dimensional electronics.

PubMed

Yu, Lili; Lee, Yi-Hsien; Ling, Xi; Santos, Elton J G; Shin, Yong Cheol; Lin, Yuxuan; Dubey, Madan; Kaxiras, Efthimios; Kong, Jing; Wang, Han; Palacios, Tomás

2014-06-11

Two-dimensional (2D) materials have generated great interest in the past few years as a new toolbox for electronics. This family of materials includes, among others, metallic graphene, semiconducting transition metal dichalcogenides (such as MoS2), and insulating boron nitride. These materials and their heterostructures offer excellent mechanical flexibility, optical transparency, and favorable transport properties for realizing electronic, sensing, and optical systems on arbitrary surfaces. In this paper, we demonstrate a novel technology for constructing large-scale electronic systems based on graphene/molybdenum disulfide (MoS2) heterostructures grown by chemical vapor deposition. We have fabricated high-performance devices and circuits based on this heterostructure, where MoS2 is used as the transistor channel and graphene as contact electrodes and circuit interconnects. We provide a systematic comparison of the graphene/MoS2 heterojunction contact to more traditional MoS2-metal junctions, as well as a theoretical investigation, using density functional theory, of the origin of the Schottky barrier height. The tunability of the graphene work function with electrostatic doping significantly improves the ohmic contact to MoS2. These high-performance large-scale devices and circuits based on this 2D heterostructure pave the way for practical flexible transparent electronics.

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

PubMed Central

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-01-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design. PMID:28145438

Impact of GaN cap on charges in Al₂O₃/(GaN/)AlGaN/GaN metal-oxide-semiconductor heterostructures analyzed by means of capacitance measurements and simulations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ťapajna, M., E-mail: milan.tapajna@savba.sk; Jurkovič, M.; Válik, L.

2014-09-14

Oxide/semiconductor interface trap density (D{sub it}) and net charge of Al₂O₃/(GaN)/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) structures with and without GaN cap were comparatively analyzed using comprehensive capacitance measurements and simulations. D{sub it} distribution was determined in full band gap of the barrier using combination of three complementary capacitance techniques. A remarkably higher D{sub it} (∼5–8 × 10¹²eV⁻¹ cm⁻²) was found at trap energies ranging from E C-0.5 to 1 eV for structure with GaN cap compared to that (D{sub it} ∼ 2–3 × 10¹²eV⁻¹ cm⁻²) where the GaN cap was selectively etched away. D{sub it} distributions were then used for simulation of capacitance-voltage characteristics. A good agreement betweenmore » experimental and simulated capacitance-voltage characteristics affected by interface traps suggests (i) that very high D{sub it} (>10¹³eV⁻¹ cm⁻²) close to the barrier conduction band edge hampers accumulation of free electron in the barrier layer and (ii) the higher D{sub it} centered about E C-0.6 eV can solely account for the increased C-V hysteresis observed for MOS-HEMT structure with GaN cap. Analysis of the threshold voltage dependence on Al₂O₃ thickness for both MOS-HEMT structures suggests that (i) positive charge, which compensates the surface polarization, is not necessarily formed during the growth of III-N heterostructure, and (ii) its density is similar to the total surface polarization charge of the GaN/AlGaN barrier, rather than surface polarization of the top GaN layer only. Some constraints for the positive surface compensating charge are discussed.« less

Electronic properties of MoS2 / MoOx interfaces: Implications in Tunnel Field Effect Transistors and Hole Contacts

DOE PAGES

Santosh, K. C.; Longo, Roberto; Addou, Rafik; ...

2016-09-26

In an electronic device based on two dimensional (2D) transitional metal dichalcogenides (TMDs), finding a low resistance metal contact is critical in order to achieve the desired performance. However, due to the unusual Fermi level pinning in metal/2D TMD interface, the performance is limited. Here, we investigate the electronic properties of TMDs and transition metal oxide (TMO) interfaces (MoS 2/MoO 3) using density functional theory (DFT). Our results demonstrate that, due to the large work function of MoO 3 and the relative band alignment with MoS 2, together with small energy gap, the MoS 2/MoO 3 interface is a goodmore » candidate for a tunnel field effect (TFET)-type device. Moreover, if the interface is not stoichiometric because of the presence of oxygen vacancies in MoO 3, the heterostructure is more suitable for p-type (hole) contacts, exhibiting an Ohmic electrical behavior as experimentally demonstrated for different TMO/TMD interfaces. Our results reveal that the defect state induced by an oxygen vacancy in the MoO3 aligns with the valance band of MoS 2, showing an insignificant impact on the band gap of the TMD. This result highlights the role of oxygen vacancies in oxides on facilitating appropriate contacts at the MoS 2 and MoO x (x < 3) interface, which consistently explains the available experimental observations.« less

Two-dimensional materials based transparent flexible electronics

NASA Astrophysics Data System (ADS)

Yu, Lili; Ha, Sungjae; El-Damak, Dina; McVay, Elaine; Ling, Xi; Chandrakasan, Anantha; Kong, Jing; Palacios, Tomas

2015-03-01

Two-dimensional (2D) materials have generated great interest recently as a set of tools for electronics, as these materials can push electronics beyond traditional boundaries. These materials and their heterostructures offer excellent mechanical flexibility, optical transparency, and favorable transport properties for realizing electronic, sensing, and optical systems on arbitrary surfaces. These thin, lightweight, bendable, highly rugged and low-power devices may bring dramatic changes in information processing, communications and human-electronic interaction. In this report, for the first time, we demonstrate two complex transparent flexible systems based on molybdenum disulfide (MoS2) grown by chemical vapor method: a transparent active-matrix organic light-emitting diode (AMOLED) display and a MoS2 wireless link for sensor nodes. The 1/2 x 1/2 square inch, 4 x 5 pixels AMOLED structures are built on transparent substrates, containing MoS2 back plane circuit and OLEDs integrated on top of it. The back plane circuit turns on and off the individual pixel with two MoS2 transistors and a capacitor. The device is designed and fabricated based on SPICE simulation to achieve desired DC and transient performance. We have also demonstrated a MoS2 wireless self-powered sensor node. The system consists of as energy harvester, rectifier, sensor node and logic units. AC signals from the environment, such as near-field wireless power transfer, piezoelectric film and RF signal, are harvested, then rectified into DC signal by a MoS2 diode. CIQM, CICS, SRC.

Electronic properties of MoS2/MoOx interfaces: Implications in Tunnel Field Effect Transistors and Hole Contacts

PubMed Central

K. C., Santosh; Longo, Roberto C.; Addou, Rafik; Wallace, Robert M.; Cho, Kyeongjae

2016-01-01

In an electronic device based on two dimensional (2D) transitional metal dichalcogenides (TMDs), finding a low resistance metal contact is critical in order to achieve the desired performance. However, due to the unusual Fermi level pinning in metal/2D TMD interface, the performance is limited. Here, we investigate the electronic properties of TMDs and transition metal oxide (TMO) interfaces (MoS2/MoO3) using density functional theory (DFT). Our results demonstrate that, due to the large work function of MoO3 and the relative band alignment with MoS2, together with small energy gap, the MoS2/MoO3 interface is a good candidate for a tunnel field effect (TFET)-type device. Moreover, if the interface is not stoichiometric because of the presence of oxygen vacancies in MoO3, the heterostructure is more suitable for p-type (hole) contacts, exhibiting an Ohmic electrical behavior as experimentally demonstrated for different TMO/TMD interfaces. Our results reveal that the defect state induced by an oxygen vacancy in the MoO3 aligns with the valance band of MoS2, showing an insignificant impact on the band gap of the TMD. This result highlights the role of oxygen vacancies in oxides on facilitating appropriate contacts at the MoS2 and MoOx (x < 3) interface, which consistently explains the available experimental observations. PMID:27666523

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

NASA Astrophysics Data System (ADS)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

High-Performance All 2D-Layered Tin Disulfide: Graphene Photodetecting Transistors with Thickness-Controlled Interface Dynamics.

PubMed

Chang, Ren-Jie; Tan, Haijie; Wang, Xiaochen; Porter, Benjamin; Chen, Tongxin; Sheng, Yuewen; Zhou, Yingqiu; Huang, Hefu; Bhaskaran, Harish; Warner, Jamie H

2018-04-18

Tin disulfide crystals with layered two-dimensional (2D) sheets are grown by chemical vapor deposition using a novel precursor approach and integrated into all 2D transistors with graphene (Gr) electrodes. The Gr:SnS 2 :Gr transistors exhibit excellent photodetector response with high detectivity and photoresponsivity. We show that the response of the all 2D photodetectors depends upon charge trapping at the interface and the Schottky barrier modulation. The thickness-dependent SnS 2 measurements in devices reveal a transition from the interface-dominated response for thin crystals to bulklike response for the thicker SnS 2 crystals, showing the sensitivity of devices fabricated using layered materials on the number of layers. These results show that SnS 2 has photosensing performance when combined with Gr electrodes that is comparable to other 2D transition metal dichalcogenides of MoS 2 and WS 2 .

Polarity control in WSe2 double-gate transistors

NASA Astrophysics Data System (ADS)

Resta, Giovanni V.; Sutar, Surajit; Balaji, Yashwanth; Lin, Dennis; Raghavan, Praveen; Radu, Iuliana; Catthoor, Francky; Thean, Aaron; Gaillardon, Pierre-Emmanuel; de Micheli, Giovanni

2016-07-01

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical properties. Here, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer WSe2. We show how modulation of the Schottky barriers at drain and source by a separate gate, named program gate, can enable the selection of the carriers injected in the channel, and achieved controllable polarity behaviour with ON/OFF current ratios >106 for both electrons and holes conduction. Polarity-controlled WSe2 transistors enable the design of compact logic gates, leading to higher computational densities in 2D-flatronics.

Molybdenum disulfide nanoflake-zinc oxide nanowire hybrid photoinverter.

PubMed

Hosseini Shokouh, Seyed Hossein; Pezeshki, Atiye; Ali Raza, Syed Raza; Choi, Kyunghee; Min, Sung-Wook; Jeon, Pyo Jin; Lee, Hee Sung; Im, Seongil

2014-05-27

We demonstrate a hybrid inverter-type nanodevice composed of a MoS2 nanoflake field-effect transistor (FET) and ZnO nanowire Schottky diode on one substrate, aiming at a one-dimensional (1D)-two-dimensional (2D) hybrid integrated electronic circuit with multifunctional capacities of low power consumption, high gain, and photodetection. In the present work, we used a nanotransfer printing method using polydimethylsiloxane for the fabrication of patterned bottom-gate MoS2 nanoflake FETs, so that they could be placed near the ZnO nanowire Schottky diodes that were initially fabricated. The ZnO nanowire Schottky diode and MoS2 FET worked respectively as load and driver for a logic inverter, which exhibits a high voltage gain of ∼50 at a supply voltage of 5 V and also shows a low power consumption of less than 50 nW. Moreover, our inverter effectively operates as a photoinverter, detecting visible photons, since MoS2 FETs appear very photosensitive, while the serially connected ZnO nanowire Schottky diode was blind to visible light. Our 1D-2D hybrid nanoinverter would be quite promising for both logic and photosensing applications due to its performance and simple device configuration as well.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Ultralow-power complementary metal-oxide-semiconductor inverters constructed on Schottky barrier modified nanowire metal-oxide-semiconductor field-effect-transistors.

PubMed

Ma, R M; Peng, R M; Wen, X N; Dai, L; Liu, C; Sun, T; Xu, W J; Qin, G G

2010-10-01

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

Band edge states, intrinsic defects, and dopants in monolayer HfS2 and SnS2

NASA Astrophysics Data System (ADS)

Lu, Haichang; Guo, Yuzheng; Robertson, John

2018-02-01

Although monolayer HfS2 and SnS2 do not have a direct bandgap like MoS2, they have much higher carrier mobilities. Their band offsets are favorable for use with WSe2 in tunnel field effect transistors. Here, we study the effective masses, intrinsic defects, and substitutional dopants of these dichalcogenides. We find that HfS2 has surprisingly small effective masses for a compound that might appear partly ionic. The S vacancy in HfS2 is found to be a shallow donor while that in SnS2 is a deep donor. Substitutional dopants at the S site are found to be shallow. This contrasts with MoS2 where donors and acceptors are not always shallow or with black phosphorus where dopants can reconstruct into deep non-doping configurations. It is pointed out that HfS2 is more favorable than MoS2 for semiconductor processing because it has the more convenient CVD precursors developed for growing HfO2.

Study of interfacial strain at the α-Al2O3/monolayer MoS2 interface by first principle calculations

NASA Astrophysics Data System (ADS)

Yu, Sheng; Ran, Shunjie; Zhu, Hao; Eshun, Kwesi; Shi, Chen; Jiang, Kai; Gu, Kunming; Seo, Felix Jaetae; Li, Qiliang

2018-01-01

With the advances in two-dimensional (2D) transition metal dichalcogenides (TMDCs) based metal-oxide-semiconductor field-effect transistor (MOSFET), the interface between the semiconductor channel and gate dielectrics has received considerable attention due to its significant impacts on the morphology and charge transport of the devices. In this study, first principle calculations were utilized to investigate the strain effect induced by the interface between crystalline α-Al2O3 (0001)/h-MoS2 monolayer. The results indicate that the 1.3 nm Al2O3 can induce a 0.3% tensile strain on the MoS2 monolayer. The strain monotonically increases with thicker dielectric layers, inducing more significant impact on the properties of MoS2. In addition, the study on temperature effect indicates that the increasing temperature induces monotonic lattice expansion. This study clearly indicates that the dielectric engineering can effectively tune the properties of 2D TMDCs, which is very attractive for nanoelectronics.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Improvement of charge-pumping electrically detected magnetic resonance and its application to silicon metal-oxide-semiconductor field-effect transistor

NASA Astrophysics Data System (ADS)

Hori, Masahiro; Tsuchiya, Toshiaki; Ono, Yukinori

2017-01-01

Charge-pumping electrically detected magnetic resonance (CP EDMR), or EDMR in the CP mode, is improved and applied to a silicon metal-oxide-semiconductor field-effect transistor (MOSFET). Real-time monitoring of the CP process reveals that high-frequency transient currents are an obstacle to signal amplification for EDMR. Therefore, we introduce cutoff circuitry, leading to a detection limit for the number of spins as low as 103 for Si MOS interface defects. With this improved method, we demonstrate that CP EDMR inherits one of the most important features of the CP method: the gate control of the energy window of the detectable interface defects for spectroscopy.

Vibrational and optical properties of MoS2: From monolayer to bulk

NASA Astrophysics Data System (ADS)

Molina-Sánchez, Alejandro; Hummer, Kerstin; Wirtz, Ludger

2015-12-01

Molybdenum disulfide, MoS2, has recently gained considerable attention as a layered material where neighboring layers are only weakly interacting and can easily slide against each other. Therefore, mechanical exfoliation allows the fabrication of single and multi-layers and opens the possibility to generate atomically thin crystals with outstanding properties. In contrast to graphene, it has an optical gap of ~1.9 eV. This makes it a prominent candidate for transistor and opto-electronic applications. Single-layer MoS2 exhibits remarkably different physical properties compared to bulk MoS2 due to the absence of interlayer hybridization. For instance, while the band gap of bulk and multi-layer MoS2 is indirect, it becomes direct with decreasing number of layers. In this review, we analyze from a theoretical point of view the electronic, optical, and vibrational properties of single-layer, few-layer and bulk MoS2. In particular, we focus on the effects of spin-orbit interaction, number of layers, and applied tensile strain on the vibrational and optical properties. We examine the results obtained by different methodologies, mainly ab initio approaches. We also discuss which approximations are suitable for MoS2 and layered materials. The effect of external strain on the band gap of single-layer MoS2 and the crossover from indirect to direct band gap is investigated. We analyze the excitonic effects on the absorption spectra. The main features, such as the double peak at the absorption threshold and the high-energy exciton are presented. Furthermore, we report on the the phonon dispersion relations of single-layer, few-layer and bulk MoS2. Based on the latter, we explain the behavior of the Raman-active A1g and E2g1 modes as a function of the number of layers. Finally, we compare theoretical and experimental results of Raman, photoluminescence, and optical-absorption spectroscopy.

Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network

NASA Astrophysics Data System (ADS)

Cohen, Marc H.; Andreou, Andreas G.

1992-05-01

The translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing are investigated. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2-microns n-well double-polysilicon, double-metal CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The design methodology and constraints as well as test results from the fabricated chips are discussed.

Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks

NASA Astrophysics Data System (ADS)

Kondo, Shuhei; Shibata, Tadashi; Ohmi, Tadahiro

1995-02-01

We have investigated the learning performance of the hardware backpropagation (HBP) algorithm, a hardware-oriented learning algorithm developed for the self-learning architecture of neural networks constructed using neuron MOS (metal-oxide-semiconductor) transistors. The solution to finding a mirror symmetry axis in a 4×4 binary pixel array was tested by computer simulation based on the HBP algorithm. Despite the inherent restrictions imposed on the hardware-learning algorithm, HBP exhibits equivalent learning performance to that of the original backpropagation (BP) algorithm when all the pertinent parameters are optimized. Very importantly, we have found that HBP has a superior generalization capability over BP; namely, HBP exhibits higher performance in solving problems that the network has not yet learnt.

Preparation and applications of mechanically exfoliated single-layer and multilayer MoS₂ and WSe₂ nanosheets.

PubMed

Li, Hai; Wu, Jumiati; Yin, Zongyou; Zhang, Hua

2014-04-15

Although great progress has been achieved in the study of graphene, the small current ON/OFF ratio in graphene-based field-effect transistors (FETs) limits its application in the fields of conventional transistors or logic circuits for low-power electronic switching. Recently, layered transition metal dichalcogenide (TMD) materials, especially MoS2, have attracted increasing attention. In contrast to its bulk material with an indirect band gap, a single-layer (1L) MoS2 nanosheet is a semiconductor with a direct band gap of ~1.8 eV, which makes it a promising candidate for optoelectronic applications due to the enhancement of photoluminescence and high current ON/OFF ratio. Compared with TMD nanosheets prepared by chemical vapor deposition and liquid exfoliation, mechanically exfoliated ones possess pristine, clean, and high-quality structures, which are suitable for the fundamental study and potential applications based on their intrinsic thickness-dependent properties. In this Account, we summarize our recent research on the preparation, characterization, and applications of 1L and multilayer MoS2 and WSe2 nanosheets produced by mechanical exfoliation. During the preparation of nanosheets, we proposed a simple optical identification method to distinguish 1L and multilayer MoS2 and WSe2 nanosheets on a Si substrate coated with 90 and 300 nm SiO2. In addition, we used Raman spectroscopy to characterize mechanically exfoliated 1L and multilayer WSe2 nanosheets. For the first time, a new Raman peak at 308 cm(-1) was observed in the spectra of WSe2 nanosheets except for the 1L WSe2 nanosheet. Importantly, we found that the 1L WSe2 nanosheet is very sensitive to the laser power during characterization. The high power laser-induced local oxidation of WSe2 nanosheets and single crystals was monitored by Raman spectroscopy and atomic force microscopy (AFM). Hexagonal and monoclinic structured WO3 thin films were obtained from the local oxidization of single- to triple-layer (1L-3L) and quadruple- to quintuple-layer (4L-5L) WSe2 nanosheets, respectively. Then, we present Raman characterization of shear and breathing modes of 1L and multilayer MoS2 and WSe2 nanosheets in the low frequency range (<50 cm(-1)), which can be used to accurately identify the layer number of nanosheets. Magnetic force microscopy was used to characterize 1L and multilayer MoS2 nanosheets, and thickness-dependent magnetic response was found. In the last part, we briefly introduce the applications of 1L and multilayer MoS2 nanosheets in the fields of gas sensors and phototransistors.

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Preparation of MoS2/TiO2 based nanocomposites for photocatalysis and rechargeable batteries: progress, challenges, and perspective.

PubMed

Chen, Biao; Meng, Yuhuan; Sha, Junwei; Zhong, Cheng; Hu, Wenbin; Zhao, Naiqin

2017-12-21

The rapidly increasing severity of the energy crisis and environmental degradation are stimulating the rapid development of photocatalysts and rechargeable lithium/sodium ion batteries. In particular, MoS 2 /TiO 2 based nanocomposites show great potential and have been widely studied in the areas of both photocatalysis and rechargeable lithium/sodium ion batteries due to their superior combination properties. In addition to the low-cost, abundance, and high chemical stability of both MoS 2 and TiO 2 , MoS 2 /TiO 2 composites also show complementary advantages. These include the strong optical absorption of TiO 2 vs. the high catalytic activity of MoS 2 , which is promising for photocatalysis; and excellent safety and superior structural stability of TiO 2 vs. the high theoretic specific capacity and unique layered structure of MoS 2 , thus, these composites are exciting as anode materials. In this review, we first summarize the recent progress in MoS 2 /TiO 2 -based nanomaterials for applications in photocatalysis and rechargeable batteries. We highlight the synthesis, structure and mechanism of MoS 2 /TiO 2 -based nanomaterials. Then, advancements and strategies for improving the performance of these composites in photocatalytic degradation, hydrogen evolution, CO 2 reduction, LIBs and SIBs are critically discussed. Finally, perspectives on existing challenges and probable opportunities for future exploration of MoS 2 /TiO 2 -based composites towards photocatalysis and rechargeable batteries are presented. We believe the present review would provide enriched information for a deeper understanding of MoS 2 /TiO 2 composites and open avenues for the rational design of MoS 2 /TiO 2 based composites for energy and environment-related applications.

Seeing diabetes: visual detection of glucose based on the intrinsic peroxidase-like activity of MoS2 nanosheets

NASA Astrophysics Data System (ADS)

Lin, Tianran; Zhong, Liangshuang; Guo, Liangqia; Fu, Fengfu; Chen, Guonan

2014-09-01

Molybdenum disulfide (MoS2) has attracted increasing research interest recently due to its unique physical, optical and electrical properties, correlated with its 2D ultrathin atomic-layered structure. Until now, however, great efforts have focused on its applications such as lithium ion batteries, transistors, and hydrogen evolution reactions. Herein, for the first time, MoS2 nanosheets are discovered to possess an intrinsic peroxidase-like activity and can catalytically oxidize 3,3',5,5'-tetramethylbenzidine (TMB) by H2O2 to produce a color reaction. The catalytic activity follows the typical Michaelis-Menten kinetics and is dependent on temperature, pH, H2O2 concentration, and reaction time. Based on this finding, a highly sensitive and selective colorimetric method for H2O2 and glucose detection is developed and applied to detect glucose in serum samples. Moreover, a simple, inexpensive, instrument-free and portable test kit for the visual detection of glucose in normal and diabetic serum samples is constructed by utilizing agarose hydrogel as a visual detection platform.Molybdenum disulfide (MoS2) has attracted increasing research interest recently due to its unique physical, optical and electrical properties, correlated with its 2D ultrathin atomic-layered structure. Until now, however, great efforts have focused on its applications such as lithium ion batteries, transistors, and hydrogen evolution reactions. Herein, for the first time, MoS2 nanosheets are discovered to possess an intrinsic peroxidase-like activity and can catalytically oxidize 3,3',5,5'-tetramethylbenzidine (TMB) by H2O2 to produce a color reaction. The catalytic activity follows the typical Michaelis-Menten kinetics and is dependent on temperature, pH, H2O2 concentration, and reaction time. Based on this finding, a highly sensitive and selective colorimetric method for H2O2 and glucose detection is developed and applied to detect glucose in serum samples. Moreover, a simple, inexpensive, instrument-free and portable test kit for the visual detection of glucose in normal and diabetic serum samples is constructed by utilizing agarose hydrogel as a visual detection platform. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr03393k

Weight ratio effects on morphology and electrocapacitive performance for the MoS2/polypyrrole electrodes

NASA Astrophysics Data System (ADS)

Tu, Chao-Chi; Peng, Pei-Wen; Lin, Lu-Yin

2018-06-01

MoS2 is one of the promising electroactive materials for charge-storage devices. The charges cannot only be stored in the intersheet of MoS2 and the intrasheet of individual atomic layers, but also can be accumulated by conducting the Faradaic reactions on the Mo center. To further enhance the electrocapacitive performance of MoS2, incorporating conducting polymers is one of the feasible ways to improve the connection between MoS2 nanosheets. At the same time, the growth of conducting polymers can also be controlled via incorporating MoS2 nanosheets in the synthesis to enhance the conductivity and increase the specific surface area of the conducting polymers. In this work, layered structures of MoS2 nanosheets are successfully synthesized via a simple hydrothermal method, and pyrrole monomers are oxidative polymerized in the MoS2 solution to prepare the nanocomposites with different ratios of MoS2 and polypyrrole (Ppy). The optimized MoS2/Ppy electrode shows a specific capacitance (CF) of 182.28 F/g, which is higher than those of the MoS2 (40.58 F/g) and Ppy (116.95 F/g) electrodes measured at the same scan rate of 10 mV/s. The excellent high-rate capacity and good cycling stability with 20% decay on the CF value comparing to the initial value after the 1000 times repeated charge/discharge process are also achieved for the optimized MoS2/Ppy electrode. The better performance for the MoS2/Ppy electrode is resulting from the larger surface area for charge accumulation and the enhanced interconnection networks for charge transportation. The results suggest that combining two materials with complementary properties as the electrocapacitive material is one of the attractive ways to realize efficient charge-storage devices with efficient electrochemical performances and good cycling lifes.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

Annealing shallow traps in electron beam irradiated high mobility metal-oxide-silicon transistors

NASA Astrophysics Data System (ADS)

Kim, Jin-Sung; Tyryshkin, Alexei; Lyon, Stephen

In metal-oxide-silicon (MOS) quantum devices, electron beam lithography (EBL) is known to create defects at the Si/SiO2 interface which can be catastrophic for single electron control. Shallow traps ( meV), which only manifest themselves at low temperature ( 4 K), are especially detrimental to quantum devices but little is known about annealing them. In this work, we use electron spin resonance (ESR) to measure the density of shallow traps in two sets of high mobility (μ) MOS transistors. One set (μ=14,000 cm2/Vs) was irradiated with an EBL dose (10 kV, 40 μC/cm2) and was subsequently annealed in forming gas while the other remained unexposed (μ=23,000 cm2/Vs). Our ESR data show that the forming gas anneal is sufficient to remove shallow traps generated by the EBL dose over the measured shallow trap energy range (0.3-4 meV). We additionally fit these devices' conductivity data to a percolation transition model and extract a zero temperature percolation threshold density, n0 ( 9 ×1010 cm-2 for both devices). We find that the extracted n0 agrees within 15 % with our lowest temperature (360 mK) ESR measurements, demonstrating agreement between two independent methods of evaluating the interface.

Design of a 16 gray scales 320 × 240 pixels OLED-on-silicon driving circuit

NASA Astrophysics Data System (ADS)

Ran, Huang; Xiaohui, Wang; Wenbo, Wang; Huan, Du; Zhengsheng, Han

2009-01-01

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4 × 28.4 μm2 and the display area is 10.7 × 8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

NASA Technical Reports Server (NTRS)

Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

1979-01-01

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

NASA Astrophysics Data System (ADS)

Wei Shih, Chen; Chin, Albert; Fu Lu, Chun; Fang Su, Wei

2016-01-01

High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm2/Vs field-effect mobility, high ION/IOFF of 2.3 × 107, small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals.

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

PubMed Central

Wei Shih, Chen; Chin, Albert; Fu Lu, Chun; Fang Su, Wei

2016-01-01

High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm2/Vs field-effect mobility, high ION/IOFF of 2.3 × 107, small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals. PMID:26744240

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

NASA Technical Reports Server (NTRS)

Rafferty, Connor S.; Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario G.; Bude, J.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Origin of flatband voltage shift and unusual minority carrier generation in thermally grown GeO2/Ge metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Hosoi, Takuji; Kutsuki, Katsuhiro; Okamoto, Gaku; Saito, Marina; Shimura, Takayoshi; Watanabe, Heiji

2009-05-01

Improvement in electrical properties of thermally grown GeO2/Ge metal-oxide-semiconductor (MOS) capacitors, such as significantly reduced flatband voltage (VFB) shift, small hysteresis, and minimized minority carrier response in capacitance-voltage (C-V) characteristics, has been demonstrated by in situ low temperature vacuum annealing prior to gate electrode deposition. Thermal desorption analysis has revealed that not only water but also hydrocarbons are easily infiltrated into GeO2 layers during air exposure and desorbed at around 300 °C, indicating that organic molecules within GeO2/Ge MOS structures are possible origins of electrical defects. The inversion capacitance, indicative of minority carrier generation, increases with air exposure time for Au/GeO2/Ge MOS capacitors, while maintaining an interface state density (Dit) of about a few 1011 cm-2 eV-1. Unusual increase in inversion capacitance was found to be suppressed by Al2O3 capping (Au/Al2O3/GeO2/Ge structures). This suggests that electrical defects induced outside the Au electrode by infiltrated molecules may enhance the minority carrier generation, and thus acting as a minority carrier source just like MOS field-effect transistors.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

High-speed low-power photonic transistor devices based on optically-controlled gain or absorption to affect optical interference.

PubMed

Huang, Yingyan; Ho, Seng-Tiong

2008-10-13

We show that a photonic transistor device can be realized via the manipulation of optical interference by optically controlled gain or absorption in novel ways, resulting in efficient transistor signal gain and switching action. Exemplary devices illustrate two complementary device types with high operating speed, microm size, microW switching power, and switching gain. They can act in tandem to provide a wide variety of operations including wavelength conversion, pulse regeneration, and logical operations. These devices could have a Transistor Figure-of-Merits >10(5) times higher than current chi((3)) approaches and are highly attractive.

Graphene-Molybdenum Disulfide-Graphene Tunneling Junctions with Large-Area Synthesized Materials.

PubMed

Joiner, Corey A; Campbell, Philip M; Tarasov, Alexey A; Beatty, Brian R; Perini, Chris J; Tsai, Meng-Yen; Ready, William J; Vogel, Eric M

2016-04-06

Tunneling devices based on vertical heterostructures of graphene and other 2D materials can overcome the low on-off ratios typically observed in planar graphene field-effect transistors. This study addresses the impact of processing conditions on two-dimensional materials in a fully integrated heterostructure device fabrication process. In this paper, graphene-molybdenum disulfide-graphene tunneling heterostructures were fabricated using only large-area synthesized materials, unlike previous studies that used small exfoliated flakes. The MoS2 tunneling barrier is either synthesized on a sacrificial substrate and transferred to the bottom-layer graphene or synthesized directly on CVD graphene. The presence of graphene was shown to have no impact on the quality of the grown MoS2. The thickness uniformity of MoS2 grown on graphene and SiO2 was found to be 1.8 ± 0.22 nm. XPS and Raman spectroscopy are used to show how the MoS2 synthesis process introduces defects into the graphene structure by incorporating sulfur into the graphene. The incorporation of sulfur was shown to be greatly reduced in the absence of molybdenum suggesting molybdenum acts as a catalyst for sulfur incorporation. Tunneling simulations based on the Bardeen transfer Hamiltonian were performed and compared to the experimental tunneling results. The simulations show the use of MoS2 as a tunneling barrier suppresses contributions to the tunneling current from the conduction band. This is a result of the observed reduction of electron conduction within the graphene sheets.

Doping of two-dimensional MoS2 by high energy ion implantation

NASA Astrophysics Data System (ADS)

Xu, Kang; Zhao, Yuda; Lin, Ziyuan; Long, Yan; Wang, Yi; Chan, Mansun; Chai, Yang

2017-12-01

Two-dimensional (2D) materials have been demonstrated to be promising candidates for next generation electronic circuits. Analogues to conventional Si-based semiconductors, p- and n-doping of 2D materials are essential for building complementary circuits. Controllable and effective doping strategies require large tunability of the doping level and negligible structural damage to ultrathin 2D materials. In this work, we demonstrate a doping method utilizing a conventional high-energy ion-implantation machine. Before the implantation, a Polymethylmethacrylate (PMMA) protective layer is used to decelerate the dopant ions and minimize the structural damage to MoS2, thus aggregating the dopants inside MoS2 flakes. By optimizing the implantation energy and fluence, phosphorus dopants are incorporated into MoS2 flakes. Our Raman and high-resolution transmission electron microscopy (HRTEM) results show that only negligibly structural damage is introduced to the MoS2 lattice during the implantation. P-doping effect by the incorporation of p+ is demonstrated by Photoluminescence (PL) and electrical characterizations. Thin PMMA protection layer leads to large kinetic damage but also a more significant doping effect. Also, MoS2 with large thickness shows less kinetic damage. This doping method makes use of existing infrastructures in the semiconductor industry and can be extended to other 2D materials and dopant species as well.

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fabrication and transfer of flexible few-layers MoS2 thin film transistors to any arbitrary substrate.

PubMed

Salvatore, Giovanni A; Münzenrieder, Niko; Barraud, Clément; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Ensslin, Klaus; Tröster, Gerhard

2013-10-22

Recently, transition metal dichalcogenides (TMDCs) have attracted interest thanks to their large field effective mobility (>100 cm(2)/V · s), sizable band gap (around 1-2 eV), and mechanical properties, which make them suitable for high performance and flexible electronics. In this paper, we present a process scheme enabling the fabrication and transfer of few-layers MoS2 thin film transistors from a silicon template to any arbitrary organic or inorganic and flexible or rigid substrate or support. The two-dimensional semiconductor is mechanically exfoliated from a bulk crystal on a silicon/polyvinyl alcohol (PVA)/polymethyl methacrylane (PMMA) stack optimized to ensure high contrast for the identification of subnanometer thick flakes. Thin film transistors (TFTs) with structured source/drain and gate electrodes are fabricated following a designed procedure including steps of UV lithography, wet etching, and atomic layer deposited (ALD) dielectric. Successively, after the dissolution of the PVA sacrificial layer in water, the PMMA film, with the devices on top, can be transferred to another substrate of choice. Here, we transferred the devices on a polyimide plastic foil and studied the performance when tensile strain is applied parallel to the TFT channel. We measured an electron field effective mobility of 19 cm(2)/(V s), an I(on)/I(off)ratio greater than 10(6), a gate leakage current as low as 0.3 pA/μm, and a subthreshold swing of about 250 mV/dec. The devices continue to work when bent to a radius of 5 mm and after 10 consecutive bending cycles. The proposed fabrication strategy can be extended to any kind of 2D materials and enable the realization of electronic circuits and optical devices easily transferrable to any other support.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

PubMed

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Strained InGaAs/InAlAs Quantum Wells for Complementary III-V Transistors

DTIC Science & Technology

2014-01-01

GaAs substrates for low power and high frequency applications, J. Appl. Phys. 109 (2011) 033706. [28] A. Ali, H. Madan , A. Agrawal, I. Ramirez, R...Growth of InAsSb-channel high electron mobility transistor structures, J. Vac. Sci. Technol. B 23 (2005) 1441–1444. [30] A. Ali, H. Madan , M.J

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

International Technical Exchange on 2D Atomic Sheets: Optoelectronics, Strain, and Energy Applications

DTIC Science & Technology

2015-01-15

Shi, University of Texas - Austin Thermal and Thermoelectric Properties and Applications of Two-Dimensional Materials beyond Graphene 11:45 – 1:15 pm...M., et al., Large and tunable photo- thermoelectric effect in single-layer MoS2, Nano Letters (2013) [4] Castellanos-Gomez, A., et al., Isolation...phosphorus field- effect transistors. Nano Letters (2014) [6] Buscema M., et al., Photovoltaic effect in few-layer black phosphorus PN junctions

Solid state image sensing arrays

NASA Technical Reports Server (NTRS)

Sadasiv, G.

1972-01-01

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Computer Aided Engineering of Semiconductor Integrated Circuits

DTIC Science & Technology

1976-04-01

from that of the ideal charge-contrpl model. Application of the test developed here to a practical MOS NAND gate demonstrates marked violations of...defining properties: [31] J. E. Meyer, RCA Review, 321, 42 (1971). [32] R.S.C. Cobbold , Theory and Applications of Field-Effect Transistors...decrease of thxs dxs- I ’ [!] H.K.J. Ihantola and J. L. Moll, Solid State Electronics, 7, 423 (1964). [2] R.S.C. Cobbold , Theory and

Research Investigation Directed Toward Extending the Useful Range of the Electromagnetic Spectrum. Appendix.

DTIC Science & Technology

1987-12-31

CuCl Excimer Si x Ge Quadropole mass spectrometer ions photoionic emission, threshold low temperature processing low energy ion beam silicon oxidation ...Etching," ECS Proceedings, 1986. C. F. Yu, M. T. Schmidt, D. V. Podlesnik, and R. M. Osgood, "Optically-Induced, Room- Temperature Oxidation of Gallium...MOS transistors with gate dielectrics obtained by ion beam oxidation at room temperature . Introduction control over the process parameters and

Low-Voltage Complementary Electronics from Ion-Gel-Gated Vertical Van der Waals Heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Yongsuk; Kang, Junmo; Jariwala, Deep

2016-03-22

Low-voltage complementary circuits comprising n-type and p-type van der Waals heterojunction vertical field-effect transistors (VFETs) are demonstrated. The resulting VFETs possess high on-state current densities (>3000 A cm-2) and on/off current ratios (>104) in a narrow voltage window (<3 V).

Nanoscale plasmonic phenomena in CVD-grown MoS 2 monolayer revealed by ultra-broadband synchrotron radiation based nano-FTIR spectroscopy and near-field microscopy

DOE PAGES

Patoka, Piotr; Ulrich, Georg; Nguyen, Ariana E.; ...

2016-01-13

Here, nanoscale plasmonic phenomena observed in single and bi-layers of molybdenum disulfide (MoS 2) on silicon dioxide (SiO 2) are reported. A scattering type scanning near-field optical microscope (s-SNOM) with a broadband synchrotron radiation (SR) infrared source was used. We also present complementary optical mapping using tunable CO 2-laser radiation. Specifically, there is a correlation of the topography of well-defined MoS 2 islands grown by chemical vapor deposition, as determined by atomic force microscopy, with the infrared (IR) signature of MoS 2. The influence of MoS 2 islands on the SiO 2 phonon resonance is discussed. The results reveal themore » plasmonic character of the MoS 2 structures and their interaction with the SiO 2 phonons leading to an enhancement of the hybridized surface plasmon-phonon mode. A theoretical analysis shows that, in the case of monolayer islands, the coupling of the MoS 2 optical plasmon mode to the SiO 2 surface phonons does not affect the infrared spectrum significantly. For two-layer MoS 2, the coupling of the extra inter-plane acoustic plasmon mode with the SiO 2 surface transverse phonon leads to a remarkable increase of the surface phonon peak at 794 cm -1. This is in agreement with the experimental data. These results show the capability of the s-SNOM technique to study local multiple excitations in complex non-homogeneous structures.« less

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Electrical and photo-electrical properties of MoS2 nanosheets with and without an Al2O3 capping layer under various environmental conditions.

PubMed

Khan, Muhammad Farooq; Nazir, Ghazanfar; Lermolenko, Volodymyr M; Eom, Jonghwa

2016-01-01

The electrical and photo-electrical properties of exfoliated MoS 2 were investigated in the dark and in the presence of deep ultraviolet (DUV) light under various environmental conditions (vacuum, N 2 gas, air, and O 2 gas). We examined the effects of environmental gases on MoS 2 flakes in the dark and after DUV illumination through Raman spectroscopy and found that DUV light induced red and blue shifts of peaks (E 1 2 g and A 1 g ) position in the presence of N 2 and O 2 gases, respectively. In the dark, the threshold voltage in the transfer characteristics of few-layer (FL) MoS 2 field-effect transistors (FETs) remained almost the same in vacuum and N 2 gas but shifted toward positive gate voltages in air or O 2 gas because of the adsorption of oxygen atoms/molecules on the MoS 2 surface. We analyzed light detection parameters such as responsivity, detectivity, external quantum efficiency, linear dynamic range, and relaxation time to characterize the photoresponse behavior of FL-MoS 2 FETs under various environmental conditions. All parameters were improved in their performances in N 2 gas, but deteriorated in O 2 gas environment. The photocurrent decayed with a large time constant in N 2 gas, but decayed with a small time constant in O 2 gas. We also investigated the characteristics of the devices after passivating by Al 2 O 3 film on the MoS 2 surface. The devices became almost hysteresis-free in the transfer characteristics and stable with improved mobility. Given its outstanding performance under DUV light, the passivated device may be potentially used for applications in MoS 2 -based integrated optoelectronic circuits, light sensing devices, and solar cells.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Dimensional-Hybrid Structures of 2D Materials with ZnO Nanostructures via pH-Mediated Hydrothermal Growth for Flexible UV Photodetectors.

PubMed

Lee, Young Bum; Kim, Seong Ku; Lim, Yi Rang; Jeon, In Su; Song, Wooseok; Myung, Sung; Lee, Sun Sook; Lim, Jongsun; An, Ki-Seok

2017-05-03

Complementary combination of heterostructures is a crucial factor for the development of 2D materials-based optoelectronic devices. Herein, an appropriate solution for fabricating complementary dimensional-hybrid nanostructures comprising structurally tailored ZnO nanostructures and 2D materials such as graphene and MoS 2 is suggested. Structural features of ZnO nanostructures hydrothermally grown on graphene and MoS 2 are deliberately manipulated by adjusting the pH value of the growing solution, which will result in the formation of ZnO nanowires, nanostars, and nanoflowers. The detailed growth mechanism is further explored for the structurally tailored ZnO nanostructures on the 2D materials. Furthermore, a UV photodetector based on the dimensional-hybrid nanostructures is fabricated, which demonstrates their excellent photocurrent and mechanical durability. This can be understood by the existence of oxygen vacancies and oxygen-vacancies-induced band narrowing in the ZnO nanostructures, which is a decisive factor for determining their photoelectrical properties in the hybrid system.

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect mobility with the layer thickness. The non-monotonic trend suggests that in order to harvest the maximum potential of MoS2 for high performance device applications, a layer thickness in the range of 6-12 nm would be ideal. Finally using scandium contacts on 10nm thick exfoliated MoS2 flakes that are covered by a 15nm ALD grown Al2O3 film, record high mobility of 700cm2/Vs is achieved at room-temperature which is extremely encouraging for the design of high performance logic devices. The destructive nature of the readout process in Ferroelectric Random Access Memories (FeRAMs) is one of the major limiting factors for their wide scale commercialization. Utilizing Ferroelectric Field-Effect Transistor RAM (FeTRAM) instead solves the destructive read out problem, but at the expense of introducing crystalline ferroelectrics that are hard to integrate into CMOS. In order to address these challenges a novel, fully functional, CMOS compatible, One-Transistor-One-Transistor (1T1T) memory cell architecture using an organic ferroelectric -- PVDF-TrFE -- as the memory storage unit (gate oxide) and a silicon nanowire as the memory read out unit (channel material) is proposed and experimentally demonstrated. While evaluating the scaling potential of the above mentioned organic FeTRAM, it is found that the switching time and switching voltage of this organic copolymer PVDF-TrFE exhibits an unexpected scaling behavior as a function of the lateral device dimensions. The phenomenological theory, that explains this abnormal scaling trend, involves in-plane interchain and intrachain interaction of the copolymer - resulting in a power-law dependence of the switching field on the device area (ESW alpha ACH0.1) that is ultimately responsible for the decrease in the switching time and switching voltage. These findings are encouraging since they indicate that scaling the switching voltage and switching time without aggressively scaling the copolymer thickness occurs naturally while scaling the device area -- in this way ultimately improving the packing density and leading towards high performance memory devices.

SWCNT-MoS2 -SWCNT Vertical Point Heterostructures.

PubMed

Zhang, Jin; Wei, Yang; Yao, Fengrui; Li, Dongqi; Ma, He; Lei, Peng; Fang, Hehai; Xiao, Xiaoyang; Lu, Zhixing; Yang, Juehan; Li, Jingbo; Jiao, Liying; Hu, Weida; Liu, Kaihui; Liu, Kai; Liu, Peng; Li, Qunqing; Lu, Wei; Fan, Shoushan; Jiang, Kaili

2017-02-01

A vertical point heterostructure (VPH) is constructed by sandwiching a two-dimensional (2D) MoS 2 flake with two cross-stacked metallic single-walled carbon nanotubes. It can be used as a field-effect transistor with high on/off ratio and a light detector with high spatial resolution. Moreover, the hybrid 1D-2D-1D VPHs open up new possibilities for nanoelectronics and nano-optoelectronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Annealing shallow Si/SiO2 interface traps in electron-beam irradiated high-mobility metal-oxide-silicon transistors

NASA Astrophysics Data System (ADS)

Kim, J.-S.; Tyryshkin, A. M.; Lyon, S. A.

2017-03-01

Electron-beam (e-beam) lithography is commonly used in fabricating metal-oxide-silicon (MOS) quantum devices but creates defects at the Si/SiO2 interface. Here, we show that a forming gas anneal is effective at removing shallow defects (≤4 meV below the conduction band edge) created by an e-beam exposure by measuring the density of shallow electron traps in two sets of high-mobility MOS field-effect transistors. One set was irradiated with an electron-beam (10 keV, 40 μC/cm2) and was subsequently annealed in forming gas while the other set remained unexposed. Low temperature (335 mK) transport measurements indicate that the forming gas anneal recovers the e-beam exposed sample's peak mobility (14 000 cm2/Vs) to within a factor of two of the unexposed sample's mobility (23 000 cm2/Vs). Using electron spin resonance (ESR) to measure the density of shallow traps, we find that the two sets of devices are nearly identical, indicating the forming gas anneal is sufficient to anneal out shallow defects generated by the e-beam exposure. Fitting the two sets of devices' transport data to a percolation transition model, we extract a T = 0 percolation threshold density in quantitative agreement with our lowest temperature ESR-measured trap densities.

Low-resistance 2D/2D ohmic contacts: A universal approach to high-performance WSe 2, MoS 2, and MoSe 2 transistors

DOE PAGES

Chuang, Hsun -Jen; Chamlagain, Bhim; Koehler, Michael; ...

2016-02-04

Here, we report a new strategy for fabricating 2D/2D low-resistance ohmic contacts for a variety of transition metal dichalcogenides (TMDs) using van der Waals assembly of substitutionally doped TMDs as drain/source contacts and TMDs with no intentional doping as channel materials. We demonstrate that few-layer WSe 2 field-effect transistors (FETs) with 2D/2D contacts exhibit low contact resistances of ~0.3 kΩ μm, high on/off ratios up to >10 9, and high drive currents exceeding 320 μA μm –1. These favorable characteristics are combined with a two-terminal field-effect hole mobility μ FE ≈ 2 × 10 2 cm 2 V –1 smore » –1 at room temperature, which increases to >2 × 10 3 cm 2 V –1 s –1 at cryogenic temperatures. We observe a similar performance also in MoS 2 and MoSe 2 FETs with 2D/2D drain and source contacts. The 2D/2D low-resistance ohmic contacts presented here represent a new device paradigm that overcomes a significant bottleneck in the performance of TMDs and a wide variety of other 2D materials as the channel materials in postsilicon electronics.« less

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

The Acoustoelectric and Electric Characterization of Single Layer Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Preciado, Edwin Sabas

The acoustoelectric effect in single-layer molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) is studied in a hybrid setup. Such effects, which rely on the transfer of momentum from surface acoustic waves (SAWs), are generated on the surface of lithium niobate (LiNbO3) to the carriers in MoS2 and WSe2, resulting in an attenuation and velocity shift of the wave and giving rise to an acoustoelectric current. This dissertation examines the feasibility of integrating high-quality, single-layer MoS2 and WSe2 onto LiNbO3 to ultimately fabricate and characterize a hybrid chip that combines the functionality of a field-effect transistor (FET) and SAW device. MoS2 and WSe2 were synthesized by chemical vapor deposition (CVD) directly onto a chemically-reduced LiNbO3 substrate. LiNbO3 is a ferroelectric material that offers a unique blend of piezoelectric and birefringent properties, yet it lacks both optical activity and semiconductor transport. The prototypical device exhibits electrical characteristics that are competitive with MoS2 and WSe2 devices on silicon. These results demonstrate both a sound-driven battery and an acoustic photodetector, and ultimately open directions to non-invasive investigation of electrical properties of single-layer films. The experiments reveal close agreement between transport measurements utilizing conventional contacts and SAW spectroscopy. This approach will set forth the possibility of contact-free transport characterization of two-dimensional (2D) transition metal dichalcogenides (TMD) films, avoiding such concerns as the role of charge transfer at contacts as an artifact of such measurements.

Tuning on-off current ratio and field-effect mobility in a MoS(2)-graphene heterostructure via Schottky barrier modulation.

PubMed

Shih, Chih-Jen; Wang, Qing Hua; Son, Youngwoo; Jin, Zhong; Blankschtein, Daniel; Strano, Michael S

2014-06-24

Field-effect transistor (FET) devices composed of a MoS2-graphene heterostructure can combine the advantages of high carrier mobility in graphene with the permanent band gap of MoS2 for digital applications. Herein, we investigate the electron transfer, photoluminescence, and gate-controlled carrier transport in such a heterostructure. We show that the junction is a Schottky barrier, whose height can be artificially controlled by gating or doping graphene. When the applied gate voltage (or the doping level) is zero, the photoexcited electron-hole pairs in monolayer MoS2 can be split by the heterojunction, significantly reducing the photoluminescence. By applying negative gate voltage (or p-doping) in graphene, the interlayer impedance formed between MoS2 and graphene exhibits an 100-fold increase. For the first time, we show that the gate-controlled interlayer Schottky impedance can be utilized to modulate carrier transport in graphene, significantly depleting the hole transport, but preserving the electron transport. Accordingly, we demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics. In the NMOS digital regime, we report a very high room temperature on/off current ratio (ION/IOFF ∼ 36) in comparison to graphene-based FET devices without sacrificing the field-effect electron mobilities in graphene. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered. The device architecture presented here may enable semiconducting behavior in graphene for digital and analogue electronics.

Observation of Wigner crystal phase and ripplon-limited mobility behavior in monolayer CVD MoS2 with grain boundary.

PubMed

Chen, Jyun-Hong; Zhong, Yuan-Liang; Li, Lain-Jong; Chen, Chii-Dong

2018-06-01

Two-dimensional electron gas (2DEG) is crucial in condensed matter physics and is present on the surface of liquid helium and at the interface of semiconductors. Monolayer MoS 2 of 2D materials also contains 2DEG in an atomic layer as a field effect transistor (FET) ultrathin channel. In this study, we synthesized double triangular MoS 2 through a chemical vapor deposition method to obtain grain boundaries for forming a ripple structure in the FET channel. When the temperature was higher than approximately 175 K, the temperature dependence of the electron mobility μ was consistent with those in previous experiments and theoretical predictions. When the temperature was lower than approximately 175 K, the mobility behavior decreased with the temperature; this finding was also consistent with that of the previous experiments. We are the first research group to explain the decreasing mobility behavior by using the Wigner crystal phase and to discover the temperature independence of ripplon-limited mobility behavior at lower temperatures. Although these mobility behaviors have been studied on the surface of liquid helium through theories and experiments, they have not been previously analyzed in 2D materials and semiconductors. We are the first research group to report the similar temperature-dependent mobility behavior of the surface of liquid helium and the monolayer MoS 2 .

Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene

NASA Astrophysics Data System (ADS)

Amani, Matin; Burke, Robert A.; Proie, Robert M.; Dubey, Madan

2015-03-01

Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >107 and field effect mobilities as high as 16.4 cm2 V-1 s-1. Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W-1. Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322-1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform.

Observation of Wigner crystal phase and ripplon-limited mobility behavior in monolayer CVD MoS2 with grain boundary

NASA Astrophysics Data System (ADS)

Chen, Jyun-Hong; Zhong, Yuan-Liang; Li, Lain-Jong; Chen, Chii-Dong

2018-06-01

Two-dimensional electron gas (2DEG) is crucial in condensed matter physics and is present on the surface of liquid helium and at the interface of semiconductors. Monolayer MoS2 of 2D materials also contains 2DEG in an atomic layer as a field effect transistor (FET) ultrathin channel. In this study, we synthesized double triangular MoS2 through a chemical vapor deposition method to obtain grain boundaries for forming a ripple structure in the FET channel. When the temperature was higher than approximately 175 K, the temperature dependence of the electron mobility μ was consistent with those in previous experiments and theoretical predictions. When the temperature was lower than approximately 175 K, the mobility behavior decreased with the temperature; this finding was also consistent with that of the previous experiments. We are the first research group to explain the decreasing mobility behavior by using the Wigner crystal phase and to discover the temperature independence of ripplon-limited mobility behavior at lower temperatures. Although these mobility behaviors have been studied on the surface of liquid helium through theories and experiments, they have not been previously analyzed in 2D materials and semiconductors. We are the first research group to report the similar temperature-dependent mobility behavior of the surface of liquid helium and the monolayer MoS2.

Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene.

PubMed

Amani, Matin; Burke, Robert A; Proie, Robert M; Dubey, Madan

2015-03-20

Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >10(7) and field effect mobilities as high as 16.4 cm(2) V(-1) s(-1). Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W(-1). Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322-1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform.

Photo-Patternable ZnO Thin Films Based on Cross-Linked Zinc Acrylate for Organic/Inorganic Hybrid Complementary Inverters.

PubMed

Jeong, Yong Jin; An, Tae Kyu; Yun, Dong-Jin; Kim, Lae Ho; Park, Seonuk; Kim, Yebyeol; Nam, Sooji; Lee, Keun Hyung; Kim, Se Hyun; Jang, Jaeyoung; Park, Chan Eon

2016-03-02

Complementary inverters consisting of p-type organic and n-type metal oxide semiconductors have received considerable attention as key elements for realizing low-cost and large-area future electronics. Solution-processed ZnO thin-film transistors (TFTs) have great potential for use in hybrid complementary inverters as n-type load transistors because of the low cost of their fabrication process and natural abundance of active materials. The integration of a single ZnO TFT into an inverter requires the development of a simple patterning method as an alternative to conventional time-consuming and complicated photolithography techniques. In this study, we used a photocurable polymer precursor, zinc acrylate (or zinc diacrylate, ZDA), to conveniently fabricate photopatternable ZnO thin films for use as the active layers of n-type ZnO TFTs. UV-irradiated ZDA thin films became insoluble in developing solvent as the acrylate moiety photo-cross-linked; therefore, we were able to successfully photopattern solution-processed ZDA thin films using UV light. We studied the effects of addition of a tiny amount of indium dopant on the transistor characteristics of the photopatterned ZnO thin films and demonstrated low-voltage operation of the ZnO TFTs within ±3 V by utilizing Al2O3/TiO2 laminate thin films or ion-gels as gate dielectrics. By combining the ZnO TFTs with p-type pentacene TFTs, we successfully fabricated organic/inorganic hybrid complementary inverters using solution-processed and photopatterned ZnO TFTs.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Encapsulation of Mo₂C in MoS₂ inorganic fullerene-like nanoparticles and nanotubes.

PubMed

Wiesel, Inna; Popovitz-Biro, Ronit; Tenne, Reshef

2013-02-21

Mo(2)C nanoparticles encapsulated within MoS(2) inorganic fullerene-like nanoparticles and nanotubes were produced by carbothermal reaction at 1200-1300 °C inside a vertical induction furnace. The particles were analyzed using various electron microscopy techniques and complementary methods.

An inductorless active mixer using stacked nMOS/pMOS configuration and LO shaping technique

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Wang, Xuebing; Chen, Hongpeng

2018-04-01

In this paper, a CMOS active down-conversion mixer is presented for wideband applications. Specifically, a LO generation chain is suggested to convert AC LO signal to shaped trapezoid burst, which reduces the sinusoidal LO power level requirement by the mixer. The current-reuse technique by stacked nMOS/pMOS architecture is used to save the power consumption of the circuit. Moreover, this complementary configuration is also employed to compensate second-order nonlinearity of the circuit. Implemented in a 0.18-μm CMOS process, post-simulations show that, driven by only ‑10 dBm sinusoidal LO signal, the proposed inductorless mixer provides a maximal conversion gain of 15.7 dB and a noise figure (NF) of 9.1-12 dB across RF input frequency range 0.5-1.6 GHz. The IIP3 and IP1dB of 3.5 dBm and ‑4.8 dBm are obtained, respectively. The mixer core only consumes 3.6 mW from a 1.8-V supply.

Highly sensitive aptasensor based on synergetic catalysis activity of MoS2-Au-HE composite using cDNA-Au-GOD for signal amplification.

PubMed

Song, Hai-Yan; Kang, Tian-Fang; Lu, Li-Ping; Cheng, Shui-Yuan

2017-03-01

Single or few-layer nanosheets of MoS 2 (MoS 2 nanosheets) and a composite composed of MoS 2 nanosheets, Au nanoparticles (AuNPs) and hemin (HE) (denoted as MoS 2 -Au-HE) were prepared. The composites possessed high synergetic catalysis activity towards the electroreduction of hydrogen peroxide. Furthermore, glucose oxidase (GOD) and AuNPs were used as marker of the complementary DNA (cDNA) strand of kanamycin aptamer to prepare a conjugate (reffered as cDNA-Au-GOD) that was designed as the signal probe. Both cDNA-Au-GOD and MoS 2 -Au-HE were applied to fabricate aptasensor for kanamycin. MoS 2 -Au-HE acted as solid platform for kanamycin aptamer and signal transmitters. AuNPs were employed as the supporter of cDNA and GOD which catalyze dissolved oxygen to produce hydrogen peroxide in the presence of glucose. Then cathodic peak current of H 2 O 2 was recorded by differential pulse voltammetry (DPV). The electrochemical reduction of H 2 O 2 was catalyzed by MoS 2 -Au-HE that was modified onto the surface of a glassy carbon electrode (GCE). The cathodic peak current of H 2 O 2 was highly linearly decreased with an increase of kanamycin concentrations from 1.0ng/L to 1.0×10 5 ng/L, with a detection limit of 0.8ng/L. This aptasensor can be used to detect kanamycin in milk with high specificity, sensitivity and selectivity. Copyright © 2016 Elsevier B.V. All rights reserved.

Chemical-free n-type and p-type multilayer-graphene transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dissanayake, D. M. N. M., E-mail: nandithad@voxtel-inc.com; Eisaman, M. D.; Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794

A single-step doping method to fabricate n- and p-type multilayer graphene (MG) top-gate field effect transistors (GFETs) is demonstrated. The transistors are fabricated on soda-lime glass substrates, with the n-type doping of MG caused by the sodium in the substrate without the addition of external chemicals. Placing a hydrogen silsesquioxane (HSQ) barrier layer between the MG and the substrate blocks the n-doping, resulting in p-type doping of the MG above regions patterned with HSQ. The HSQ is deposited in a single fabrication step using electron beam lithography, allowing the patterning of arbitrary sub-micron spatial patterns of n- and p-type doping.more » When a MG channel is deposited partially on the barrier and partially on the glass substrate, a p-type and n-type doping profile is created, which is used for fabricating complementary transistors pairs. Unlike chemically doped GFETs in which the external dopants are typically introduced from the top, these substrate doped GFETs allow for a top gate which gives a stronger electrostatic coupling to the channel, reducing the operating gate bias. Overall, this method enables scalable fabrication of n- and p-type complementary top-gated GFETs with high spatial resolution for graphene microelectronic applications.« less

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

PubMed

Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

2017-04-12

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10 6 , effective mobility up to 30 cm 2 V -1 s -1 , small hysteresis, and small subthreshold swing (90-140 mV dec -1 ), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V dd = 1 V) and a voltage gain as high as 30 (at V dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Bandwidth tunable amplifier for recording biopotential signals.

PubMed

Hwang, Sungkil; Aninakwa, Kofi; Sonkusale, Sameer

2010-01-01

This paper presents a low noise, low power, bandwidth tunable amplifier for bio-potential signal recording applications. By employing depletion-mode pMOS transistor in diode configuration as a tunable sub pA current source to adjust the resistivity of MOS-Bipolar pseudo-resistor, the bandwidth is adjusted without any need for a separate band-pass filter stage. For high CMRR, PSRR and dynamic range, a fully differential structure is used in the design of the amplifier. The amplifier achieves a midband gain of 39.8dB with a tunable high-pass cutoff frequency ranging from 0.1Hz to 300Hz. The amplifier is fabricated in 0.18εm CMOS process and occupies 0.14mm(2) of chip area. A three electrode ECG measurement is performed using the proposed amplifier to show its feasibility for low power, compact wearable ECG monitoring application.

A high-resolution time-to-digital converter using a three-level resolution

NASA Astrophysics Data System (ADS)

Dehghani, Asma; Saneei, Mohsen; Mahani, Ali

2016-08-01

In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.

Creation of half-metallic f -orbital Dirac fermion with superlight elements in orbital-designed molecular lattice

NASA Astrophysics Data System (ADS)

Cui, Bin; Huang, Bing; Li, Chong; Zhang, Xiaoming; Jin, Kyung-Hwan; Zhang, Lizhi; Jiang, Wei; Liu, Desheng; Liu, Feng

2017-08-01

Magnetism in solids generally originates from the localized d or f orbitals that are hosted by heavy transition-metal elements. Here, we demonstrate a mechanism for designing a half-metallic f -orbital Dirac fermion from superlight s p elements. Combining first-principles and model calculations, we show that bare and flat-band-sandwiched (FBS) Dirac bands can be created when C20 molecules are deposited into a two-dimensional hexagonal lattice, which are composed of f -molecular orbitals (MOs) derived from s p -atomic orbitals (AOs). Furthermore, charge doping of the FBS Dirac bands induces spontaneous spin polarization, converting the system into a half-metallic Dirac state. Based on this discovery, a model of a spin field effect transistor is proposed to generate and transport 100% spin-polarized carriers. Our finding illustrates a concept to realize exotic quantum states by manipulating MOs, instead of AOs, in orbital-designed molecular crystal lattices.

A design solution to increasing the sensitivity of pMOS dosimeters: The stacked RADFET approach

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kelleher, A.; Lane, W.; Adams, L.

1995-02-01

pMOS Radiation Sensitive Field Effect Transistors (RADFET`S) have applications as integrating dosimeters in laboratories and medicine to measure the amount of radiation dose absorbed. The suitability of these dosimeters to a certain application depends on the sensitivity of the RADFET being used. To date, this sensitivity is limited to the sensitivity of the gate oxide to radiation. The aim of this paper is to introduce a new design approach which will allow greater sensitivities to be achieved than is currently possible. An additional attractive feature of this design approach is that the sensitivity of the dosimeter may be changed dependingmore » on the total dose which is to be measured; essentially a dosimeter with auto-scaling may be achieved. This study introduces this autoscaling concept along with presenting the optimum RADFET device requirements which are necessary for this new design approach.« less

Novel five-state latch using double-peak negative differential resistance and standard ternary inverter

NASA Astrophysics Data System (ADS)

Shin, Sunhae; Rok Kim, Kyung

2016-04-01

We propose complement double-peak negative differential resistance (NDR) devices with ultrahigh peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with conventional CMOS and its compact five-state latch circuit by introducing standard ternary inverter (STI). At the “high”-state of STI, n-type NDR device (tunnel diode with nMOS) has 1st NDR characteristics with 1st peak and valley by band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT), whereas p-type NDR device (tunnel diode with pMOS) has second NDR characteristics from the suppression of diode current by off-state MOSFET. The “intermediate”-state of STI permits double-peak NDR device to operate five-state latch with only four transistors, which has 33% area reduction compared with that of binary inverter and 57% bit-density reduction compared with binary latch.

Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

NASA Technical Reports Server (NTRS)

Brucker, G. J.; Van Gunten, O.; Stassinopoulos, E. G.; Shapiro, P.; August, L. S.; Jordan, T. M.

1983-01-01

This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors.

PubMed

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-03-21

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm²/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm²/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors

PubMed Central

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-01-01

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm2/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm2/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics. PMID:28772679

Experimental analysis of the Schottky barrier height of metal contacts in black phosphorus field-effect transistors

NASA Astrophysics Data System (ADS)

Chang, Hsun-Ming; Fan, Kai-Lin; Charnas, Adam; Ye, Peide D.; Lin, Yu-Ming; Wu, Chih-I.; Wu, Chao-Hsin

2018-04-01

Compared to graphene and MoS2, studies on metal contacts to black phosphorus (BP) transistors are still immature. In this work, we present the experimental analysis of titanium contacts on BP based upon the theory of thermionic emssion. The Schottky barrier height (SBH) is extracted by thermionic emission methods to analyze the properties of Ti-BP contact. To examine the results, the band gap of BP is extracted followed by theoretical band alignment by Schottky-Mott rule. However, an underestimated SBH is found due to the hysteresis in electrical results. Hence, a modified SBH extraction for contact resistance that avoids the effects of hysteresis is proposed and demonstrated, showing a more accurate SBH that agrees well with theoretical value and results of transmission electron microscopy and energy-dispersive x-ray spectroscopy.

FinFET and UTBB for RF SOI communication systems

NASA Astrophysics Data System (ADS)

Raskin, Jean-Pierre

2016-11-01

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Development of optimized detector/spectrophotometer technology for low background space astronomy missions

NASA Technical Reports Server (NTRS)

Jones, B.

1985-01-01

This program was directed towards a better understanding of some of the important factors in the performance of infrared detector arrays at low background conditions appropriate for space astronomy. The arrays were manufactured by Aerojet Electrosystems Corporation, Azusa. Two arrays, both bismuth doped silicon, were investigated: an AMCID 32x32 Engineering mosiac Si:Bi accumulation mode charge injection device detector array and a metal oxide semiconductor/field effect transistor (MOS-FET) switched array of 16x32 pixels.

Dosimetry and microdosimetry using COTS ICs: A comparative study

NASA Technical Reports Server (NTRS)

Scheick, L.; Swift, G.; Guertin, S.; Roth, D.; McNulty, P.; Nguyen, D.

2002-01-01

A new method using an array of MOS transistors formeasuring dose absorbed from ionizing radiation is compared to previous dosimetric methods., The accuracy and precision of dosimetry based on COTS SRAMs, DRAMs, and WPROMs are compared and contrasted. Applications of these devices in various space missions will be discussed. TID results are presented for this summary and microdosimetricresults will be added to the full paper. Finally, an analysis of the optimal condition for a digital dosimeter will be presented.

Modeling a Common-Source Amplifier Using a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Sayyah, Rana; Hunt, Mitchell; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

Electronic system for data acquisition to study radiation effects on operating MOSFET transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alves de Oliveira, Juliano; Assis de Melo, Marco Antônio; Guazzelli da Silveira, Marcilei A.

In this work we present the development of an acquisition system for characterizing transistors under X-ray radiation. The system is able to carry out the acquisition and to storage characteristic transistor curves. To test the acquisition system we have submitted polarized P channel MOS transistors under continuous 10-keV X-ray doses up to 1500 krad. The characterization system can operate in the saturation region or in the linear region in order to observe the behavior of the currents or voltages involved during the irradiation process. Initial tests consisted of placing the device under test (DUT) in front of the X-ray beammore » direction, while its drain current was constantly monitored through the prototype generated in this work, the data are stored continuously and system behavior was monitored during the test. In order to observe the behavior of the DUT during the radiation tests, we used an acquisition system that consists of an ultra-low consumption16-bit Texas Instruments MSP430 microprocessor. Preliminary results indicate linear behavior of the voltage as a function of the exposure time and fast recovery. These features may be favorable to use this device as a radiation dosimeter to monitor low rate X-ray.« less

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Reduction of Charge Traps and Stability Enhancement in Solution-Processed Organic Field-Effect Transistors Based on a Blended n-Type Semiconductor.

PubMed

Campos, Antonio; Riera-Galindo, Sergi; Puigdollers, Joaquim; Mas-Torrent, Marta

2018-05-09

Solution-processed n-type organic field-effect transistors (OFETs) are essential elements for developing large-area, low-cost, and all organic logic/complementary circuits. Nonetheless, the development of air-stable n-type organic semiconductors (OSCs) lags behind their p-type counterparts. The trapping of electrons at the semiconductor-dielectric interface leads to a lower performance and operational stability. Herein, we report printed small-molecule n-type OFETs based on a blend with a binder polymer, which enhances the device stability due to the improvement of the semiconductor-dielectric interface quality and a self-encapsulation. Both combined effects prevent the fast deterioration of the OSC. Additionally, a complementary metal-oxide semiconductor-like inverter is fabricated depositing p-type and n-type OSCs simultaneously.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

Speed-Up Techniques for Complementary Metal Oxide Semiconductor Very Large Scale Integration.

DTIC Science & Technology

1984-12-14

The input voltage at which the two transistors are in the constant current region at the same time marks the active operating region of the inverter...decoder precharge configurations. One circuit displayed a marked enhancement in operation while the other precharged circuit displyed degraded operation due...34 IEEE Journal of Solid State Circuits, SC-18: 457-462 (October 1983). 19. Cobbold , R. Theory and Applications of Field Effect Transistors, New York: John

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Operation of the GaSb p-channel metal-oxide-semiconductor field-effect transistors fabricated on (111)A surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishi, K., E-mail: nishi@mosfet.t.u-tokyo.ac.jp; Takenaka, M.; Takagi, S.

2014-12-08

We demonstrate the operation of GaSb p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on (111)A surfaces with Al{sub 2}O{sub 3} gate dielectrics formed by atomic-layer deposition at 150 °C. The p-MOSFETs on (111)A surfaces exhibit higher drain current and lower subthreshold swing than those on (100) surfaces. We find that the interface-state density (D{sub it}) values at the Al{sub 2}O{sub 3}/GaSb MOS interfaces on the (111)A surfaces are lower than those on the (100) surfaces, which can lead to performance enhancement of the GaSb p-MOSFETs on (111)A surfaces. The mobility of the GaSb p-MOSFETs on (111)A surfaces is 80% higher than that onmore » (100) surfaces.« less

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

N-type organic electrochemical transistors with stability in water

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan -Tiberiu

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurementsmore » in water show no degradation when tested for 2 h under continuous cycling. Furthermore, this demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.« less

N-type organic electrochemical transistors with stability in water

DOE PAGES

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan -Tiberiu; ...

2016-10-07

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurementsmore » in water show no degradation when tested for 2 h under continuous cycling. Furthermore, this demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.« less

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Flexible ambipolar organic field-effect transistors with reverse-offset-printed silver electrodes for a complementary inverter.

PubMed

Park, Junsu; Kim, Minseok; Yeom, Seung-Won; Ha, Hyeon Jun; Song, Hyenggun; Min Jhon, Young; Kim, Yun-Hi; Ju, Byeong-Kwon

2016-06-03

We report ambipolar organic field-effect transistors and complementary inverter circuits with reverse-offset-printed (ROP) Ag electrodes fabricated on a flexible substrate. A diketopyrrolopyrrole-based co-polymer (PDPP-TAT) was used as the semiconductor and poly(methyl methacrylate) was used as the gate insulator. Considerable improvement is observed in the n-channel electrical characteristics by inserting a cesium carbonate (Cs2CO3) as the electron-injection/hole-blocking layer at the interface between the semiconductors and the electrodes. The saturation mobility values are 0.35 cm(2) V(-1) s(-1) for the p-channel and 0.027 cm(2) V(-1) s(-1) for the n-channel. A complementary inverter is demonstrated based on the ROP process, and it is selectively controlled by the insertion of Cs2CO3 onto the n-channel region via thermal evaporation. Moreover, the devices show stable operation during the mechanical bending test using tensile strains ranging from 0.05% to 0.5%. The results confirm that these devices have great potential for use in flexible and inexpensive integrated circuits over a large area.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

PubMed

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (<3 g/m(2)), and good mechanical robustness (accommodating severe crumpling and 67% compressive strain). Furthermore, the nanotube circuits can operate properly with 33% compressive strain. On the basis of the aforementioned features, our ultraflexible p-type nanotube transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

PbSe Nanocrystal Solids for n- and p-Channel Thin Film Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Talapin, Dmitri V.; Murray, Christopher B.

2005-10-01

Initially poorly conducting PbSe nanocrystal solids (quantum dot arrays or superlattices) can be chemically ``activated'' to fabricate n- and p-channel field effect transistors with electron and hole mobilities of 0.9 and 0.2 square centimeters per volt-second, respectively; with current modulations of about 103 to 104; and with current density approaching 3 × 104 amperes per square centimeter. Chemical treatments engineer the interparticle spacing, electronic coupling, and doping while passivating electronic traps. These nanocrystal field-effect transistors allow reversible switching between n- and p-transport, providing options for complementary metal oxide semiconductor circuits and enabling a range of low-cost, large-area electronic, optoelectronic, thermoelectric, and sensing applications.

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

Accelerated life testing and temperature dependence of device characteristics in GaAs CHFET devices

NASA Technical Reports Server (NTRS)

Gallegos, M.; Leon, R.; Vu, D. T.; Okuno, J.; Johnson, A. S.

2002-01-01

Accelerated life testing of GaAs complementary heterojunction field effect transistors (CHFET) was carried out. Temperature dependence of single and synchronous rectifier CHFET device characteristics were also obtained.

Junctionless Diode Enabled by Self-Bias Effect of Ion Gel in Single-Layer MoS2 Device.

PubMed

Khan, Muhammad Atif; Rathi, Servin; Park, Jinwoo; Lim, Dongsuk; Lee, Yoontae; Yun, Sun Jin; Youn, Doo-Hyeb; Kim, Gil-Ho

2017-08-16

The self-biasing effects of ion gel from source and drain electrodes on electrical characteristics of single layer and few layer molybdenum disulfide (MoS 2 ) field-effect transistor (FET) have been studied. The self-biasing effect of ion gel is tested for two different configurations, covered and open, where ion gel is in contact with either one or both, source and drain electrodes, respectively. In open configuration, the linear output characteristics of the pristine device becomes nonlinear and on-off ratio drops by 3 orders of magnitude due to the increase in "off" current for both single and few layer MoS 2 FETs. However, the covered configuration results in a highly asymmetric output characteristics with a rectification of around 10 3 and an ideality factor of 1.9. This diode like behavior has been attributed to the reduction of Schottky barrier width by the electric field of self-biased ion gel, which enables an efficient injection of electrons by tunneling at metal-MoS 2 interface. Finally, finite element method based simulations are carried out and the simulated results matches well in principle with the experimental analysis. These self-biased diodes can perform a crucial role in the development of high-frequency optoelectronic and valleytronic devices.

Electrical transport and low-frequency noise in chemical vapor deposited single-layer MoS2 devices.

PubMed

Sharma, Deepak; Amani, Matin; Motayed, Abhishek; Shah, Pankaj B; Birdwell, A Glen; Najmaei, Sina; Ajayan, Pulickel M; Lou, Jun; Dubey, Madan; Li, Qiliang; Davydov, Albert V

2014-04-18

We have studied temperature-dependent (77-300 K) electrical characteristics and low-frequency noise (LFN) in chemical vapor deposited (CVD) single-layer molybdenum disulfide (MoS2) based back-gated field-effect transistors (FETs). Electrical characterization and LFN measurements were conducted on MoS2 FETs with Al2O3 top-surface passivation. We also studied the effect of top-surface passivation etching on the electrical characteristics of the device. Significant decrease in channel current and transconductance was observed in these devices after the Al2O3 passivation etching. For passivated devices, the two-terminal resistance variation with temperature showed a good fit to the activation energy model, whereas for the etched devices the trend indicated a hopping transport mechanism. A significant increase in the normalized drain current noise power spectral density (PSD) was observed after the etching of the top passivation layer. The observed channel current noise was explained using a standard unified model incorporating carrier number fluctuation and correlated surface mobility fluctuation mechanisms. Detailed analysis of the gate-referred noise voltage PSD indicated the presence of different trapping states in passivated devices when compared to the etched devices. Etched devices showed weak temperature dependence of the channel current noise, whereas passivated devices exhibited near-linear temperature dependence.

Graphene - ferroelectric and MoS2 - ferroelectric heterostructures for memory applications

NASA Astrophysics Data System (ADS)

Lipatov, Alexey; Sharma, Pankaj; Gruverman, Alexei; Sinitskii, Alexander

In recent years there has been an unprecedented interest in two-dimensional (2D) materials with unique physical and chemical properties that cannot be found in their three-dimensional (3D) counterparts. One of the important advantages of 2D materials is that they can be easily integrated with other 2D materials and functional films, resulting in multilayered structures with new properties. We fabricated and tested electronic and memory properties of field-effect transistors (FETs) based on a single-layer graphene combined with lead zirconium titanate (PZT) substrate. Previously studied graphene-PZT devices exhibited an unusual electronic behavior such as clockwise hysteresis of electronic transport, in contradiction with counterclockwise polarization dependence of PZT. We investigated how the interplay of polarization and interfacial phenomena affects the electronic behavior and memory characteristics of graphene-PZT FETs, explain the origin of unusual clockwise hysteresis and experimentally demonstrate a reversed polarization-dependent hysteresis of electronic transport. In addition we fabricated and tested properties of MoS2-PZT FETs which exhibit a large hysteresis of electronic transport with high ON/OFF ratios. We demonstrate that MoS2-PZT memories have a number of advantages over commercial FeRAMs, such as nondestructive data readout, low operation voltage, wide memory window and the possibility to write and erase them both electrically and optically.

Highly Stable, Dual-Gated MoS2 Transistors Encapsulated by Hexagonal Boron Nitride with Gate-Controllable Contact, Resistance, and Threshold Voltage.

PubMed

Lee, Gwan-Hyoung; Cui, Xu; Kim, Young Duck; Arefe, Ghidewon; Zhang, Xian; Lee, Chul-Ho; Ye, Fan; Watanabe, Kenji; Taniguchi, Takashi; Kim, Philip; Hone, James

2015-07-28

Emerging two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have been intensively studied because of their novel properties for advanced electronics and optoelectronics. However, 2D materials are by nature sensitive to environmental influences, such as temperature, humidity, adsorbates, and trapped charges in neighboring dielectrics. Therefore, it is crucial to develop device architectures that provide both high performance and long-term stability. Here we report high performance of dual-gated van der Waals (vdW) heterostructure devices in which MoS2 layers are fully encapsulated by hexagonal boron nitride (hBN) and contacts are formed using graphene. The hBN-encapsulation provides excellent protection from environmental factors, resulting in highly stable device performance, even at elevated temperatures. Our measurements also reveal high-quality electrical contacts and reduced hysteresis, leading to high two-terminal carrier mobility (33-151 cm(2) V(-1) s(-1)) and low subthreshold swing (80 mV/dec) at room temperature. Furthermore, adjustment of graphene Fermi level and use of dual gates enable us to separately control contact resistance and threshold voltage. This novel vdW heterostructure device opens up a new way toward fabrication of stable, high-performance devices based on 2D materials.

Thermal transport properties of bulk and monolayer MoS2: an ab-initio approach

NASA Astrophysics Data System (ADS)

Bano, Amreen; Khare, Preeti; Gaur, N. K.

2017-05-01

The transport properties of semiconductors are key to the performance of many solid-state devices (transistors, data storage, thermoelectric cooling and power generation devices, etc). In recent years simulation tools based on first-principles calculations have been greatly improved, being able to obtain the fundamental ground-state properties of materials accurately. The quasi harmonic thermal properties of bulk and monolayer of MoS2 has been computed with ab initio periodic simulations based of density functional theory (DFT). The temperature dependence of bulk modulus, specific heat, thermal expansion and gruneisen parameter have been calculated in our work within the temperature range of 0K to 900K with projected augmented wave (PAW) method using generalized gradient approximation (GGA). Our results show that the optimized lattice parameters are in good agreement with the earlier reported works and also for thermoelastic parameter, i.e. isothermal bulk modulus (B) at 0K indicates that monolayer MoS2 (48.5 GPa)is more compressible than the bulk structure (159.23 GPa). The thermal expansion of monolayer structure is slightly less than the bulk. Similarly, other parameters like heat capacity and gruneisen parameter shows different nature which is due to the confinement of 3 dimensional structure to 2 dimension (2D) for improving its transport characteristics.

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

A New Method for Negative Bias Temperature Instability Assessment in P-Channel Metal Oxide Semiconductor Transistors

NASA Astrophysics Data System (ADS)

Djezzar, Boualem; Tahi, Hakim; Benabdelmoumene, Abdelmadjid; Chenouf, Amel; Kribes, Youcef

2012-11-01

In this paper, we present a new method, named on the fly oxide trap (OTFOT), to extract the bias temperature instability (BTI) in MOS transistors. The OTFOT method is based on charge pumping technique (CP) at low and high frequencies. We emphasize on the theoretical-based concept, giving a clear insight on the easy-use of the OTFOT methodology and demonstrating its viability to characterize the negative BTI (NBTI). Using alternatively high and low frequencies, OTFOT method separates the interface-traps (ΔNit) and border-trap (ΔNbt) (switching oxide-trap) densities independently and also their contributions to the threshold voltage shift (ΔVth), without needing additional methods. The experimental results, from two experimental scenarios, showing the extraction of NBTI-induced shifts caused by interface- and oxide-trap increases are also presented. In the first scenario, all stresses are performed on the same transistor. It exhibits an artifact value of exponent n. In the second scenario, each voltage stress is applied only on one transistor. Its results show an average n of 0.16, 0.05, and 0.11 for NBTI-induced ΔNit, ΔNbt, ΔVth, respectively. Therefore, OTFOT method can contribute to further understand the behavior of the NBTI degradation, especially through the threshold voltage shift components such as ΔVit and ΔVot caused by interface-trap and border-trap, respectively.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Saptarshi; Roelofs, Andreas; Dubey, Madan

2014-08-25

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for themore » NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Inkjet printed graphene-based field-effect transistors on flexible substrate

NASA Astrophysics Data System (ADS)

Monne, Mahmuda Akter; Enuka, Evarestus; Wang, Zhuo; Chen, Maggie Yihong

2017-08-01

This paper presents the design and fabrication of inkjet printed graphene field-effect transistors (GFETs). The inkjet printed GFET is fabricated on a DuPont Kapton FPC Polyimide film with a thickness of 5 mill and dielectric constant of 3.9 by using a Fujifilm Dimatix DMP-2831 materials deposition system. A layer by layer 3D printing technique is deployed with an initial printing of source and drain by silver nanoparticle ink. Then graphene active layer doped with molybdenum disulfide (MoS2) monolayer/multilayer dispersion, is printed onto the surface of substrate covering the source and drain electrodes. High capacitance ion gel is adopted as the dielectric material due to the high dielectric constant. Then the dielectric layer is then covered with silver nanoparticle gate electrode. Characterization of GFET has been done at room temperature (25°C) using HP-4145B semiconductor parameter analyzer (Hewlett-Packard). The characterization result shows for a voltage sweep from -2 volts to 2 volts, the drain current changes from 949 nA to 32.3 μA and the GFET achieved an on/off ratio of 38:1, which is a milestone for inkjet printed flexible graphene transistor.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

A monolithic lead sulfide-silicon MOS integrated-circuit structure

NASA Technical Reports Server (NTRS)

Jhabvala, M. D.; Barrett, J. R.

1982-01-01

A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

Large Work Function Modulation of Monolayer MoS2 by Ambient Gases.

PubMed

Lee, Si Young; Kim, Un Jeong; Chung, JaeGwan; Nam, Honggi; Jeong, Hye Yun; Han, Gang Hee; Kim, Hyun; Oh, Hye Min; Lee, Hyangsook; Kim, Hyochul; Roh, Young-Geun; Kim, Jineun; Hwang, Sung Woo; Park, Yeonsang; Lee, Young Hee

2016-06-28

Although two-dimensional monolayer transition-metal dichalcogenides reveal numerous unique features that are inaccessible in bulk materials, their intrinsic properties are often obscured by environmental effects. Among them, work function, which is the energy required to extract an electron from a material to vacuum, is one critical parameter in electronic/optoelectronic devices. Here, we report a large work function modulation in MoS2 via ambient gases. The work function was measured by an in situ Kelvin probe technique and further confirmed by ultraviolet photoemission spectroscopy and theoretical calculations. A measured work function of 4.04 eV in vacuum was converted to 4.47 eV with O2 exposure, which is comparable with a large variation in graphene. The homojunction diode by partially passivating a transistor reveals an ideal junction with an ideality factor of almost one and perfect electrical reversibility. The estimated depletion width obtained from photocurrent mapping was ∼200 nm, which is much narrower than bulk semiconductors.

Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

NASA Astrophysics Data System (ADS)

Bersch, Brian M.; Eichfeld, Sarah M.; Lin, Yu-Chuan; Zhang, Kehao; Bhimanapati, Ganesh R.; Piasecki, Aleksander F.; Labella, Michael, III; Robinson, Joshua A.

2017-06-01

Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I-V method

NASA Astrophysics Data System (ADS)

Park, Junghak; Hur, Ji-Hyun; Jeon, Sanghun

2018-04-01

The threshold voltage instabilities and huge hysteresis of MoS2 thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS2 TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS2 TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS2 TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I-V method.

PubMed

Park, Junghak; Hur, Ji-Hyun; Jeon, Sanghun

2018-04-27

The threshold voltage instabilities and huge hysteresis of MoS 2 thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS 2 TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS 2 TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS 2 TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

PubMed

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

PubMed

Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

2016-06-01

Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

Low-temperature electron cyclotron resonance plasma-enhanced chemical-vapor deposition silicon dioxide as gate insulator for polycrystalline silicon thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maiolo, L.; Pecora, A.; Fortunato, G.

2006-03-15

Silicon dioxide films have been deposited at temperatures below 270 deg. C in an electron cyclotron resonance (ECR) plasma reactor from O{sub 2}, SiH{sub 4}, and He gas mixture. Pinhole density analysis as a function of substrate temperature for different microwave powers was carried out. Films deposited at higher microwave power and at room temperature show defect densities (<7 pinhole/mm{sup 2}), ensuring low-temperature process integration on large area. From Fourier transform infrared analysis and thermal desorption spectrometry we also evaluated very low hydrogen content if compared to conventional rf-plasma-enhanced chemical-vapor-deposited (PECVD) SiO{sub 2} deposited at 350 deg. C. Electrical propertiesmore » have been measured in metal-oxide-semiconductor (MOS) capacitors, depositing SiO{sub 2} at RT as gate dielectric; breakdown electric fields >10 MV/cm and charge trapping at fields >6 MV/cm have been evaluated. From the study of interface quality in MOS capacitors, we found that even for low annealing temperature (200 deg. C), it is possible to considerably reduce the interface state density down to 5x10{sup 11} cm{sup -2} eV{sup -1}. To fully validate the ECR-PECVD silicon dioxide we fabricated polycrystalline silicon thin-film transistors using RT-deposited SiO{sub 2} as gate insulator. Different postdeposition thermal treatments have been studied and good device characteristics were obtained even for annealing temperature as low as 200 deg. C.« less

High mobility n-type organic thin-film transistors deposited at room temperature by supersonic molecular beam deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiarella, F., E-mail: fabio.chiarella@spin.cnr.it; Barra, M.; Ciccullo, F.

In this paper, we report on the fabrication of N,N′-1H,1H-perfluorobutil dicyanoperylenediimide (PDIF-CN{sub 2}) organic thin-film transistors by Supersonic Molecular Beam Deposition. The devices exhibit mobility up to 0.2 cm{sup 2}/V s even if the substrate is kept at room temperature during the organic film growth, exceeding by three orders of magnitude the electrical performance of those grown at the same temperature by conventional Organic Molecular Beam Deposition. The possibility to get high-mobility n-type transistors avoiding thermal treatments during or after the deposition could significantly extend the number of substrates suitable to the fabrication of flexible high-performance complementary circuits by using this compound.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Adaptation of ion beam technology to microfabrication of solid state devices and transducers

NASA Technical Reports Server (NTRS)

Topich, J. A.

1977-01-01

It was found that ion beam texturing of silicon surfaces can be used to increase the effective surface area of MOS capacitors. There is, however, a problem with low dielectric breakdown. Preliminary work was begun on the fabrication of ion implanted resistors on textured surfaces and the potential improvement of wire bond strength by bonding to a textured surface. In the area of ion beam sputtering, the techniques for sputtering PVC were developed. A PVC target containing valinomycin was used to sputter an ion selective membrane on a field effect transistor to form a potassium ion sensor.

Oxide-mediated recovery of field-effect mobility in plasma-treated MoS2

PubMed Central

Jadwiszczak, Jakub; O’Callaghan, Colin; Zhou, Yangbo; Fox, Daniel S.; Weitz, Eamonn; Keane, Darragh; Cullen, Conor P.; O’Reilly, Ian; Downing, Clive; Shmeliov, Aleksey; Maguire, Pierce; Gough, John J.; McGuinness, Cormac; Ferreira, Mauro S.; Bradley, A. Louise; Boland, John J.; Duesberg, Georg S.; Nicolosi, Valeria; Zhang, Hongzhou

2018-01-01

Precise tunability of electronic properties of two-dimensional (2D) nanomaterials is a key goal of current research in this field of materials science. Chemical modification of layered transition metal dichalcogenides leads to the creation of heterostructures of low-dimensional variants of these materials. In particular, the effect of oxygen-containing plasma treatment on molybdenum disulfide (MoS2) has long been thought to be detrimental to the electrical performance of the material. We show that the mobility and conductivity of MoS2 can be precisely controlled and improved by systematic exposure to oxygen/argon plasma and characterize the material using advanced spectroscopy and microscopy. Through complementary theoretical modeling, which confirms conductivity enhancement, we infer the role of a transient 2D substoichiometric phase of molybdenum trioxide (2D-MoOx) in modulating the electronic behavior of the material. Deduction of the beneficial role of MoOx will serve to open the field to new approaches with regard to the tunability of 2D semiconductors by their low-dimensional oxides in nano-modified heterostructures. PMID:29511736

Epitaxial Single-Layer MoS2 on GaN with Enhanced Valley Helicity.

PubMed

Wan, Yi; Xiao, Jun; Li, Jingzhen; Fang, Xin; Zhang, Kun; Fu, Lei; Li, Pan; Song, Zhigang; Zhang, Hui; Wang, Yilun; Zhao, Mervin; Lu, Jing; Tang, Ning; Ran, Guangzhao; Zhang, Xiang; Ye, Yu; Dai, Lun

2018-02-01

Engineering the substrate of 2D transition metal dichalcogenides can couple the quasiparticle interaction between the 2D material and substrate, providing an additional route to realize conceptual quantum phenomena and novel device functionalities, such as realization of a 12-time increased valley spitting in single-layer WSe 2 through the interfacial magnetic exchange field from a ferromagnetic EuS substrate, and band-to-band tunnel field-effect transistors with a subthreshold swing below 60 mV dec -1 at room temperature based on bilayer n-MoS 2 and heavily doped p-germanium, etc. Here, it is demonstrated that epitaxially grown single-layer MoS 2 on a lattice-matched GaN substrate, possessing a type-I band alignment, exhibits strong substrate-induced interactions. The phonons in GaN quickly dissipate the energy of photogenerated carriers through electron-phonon interaction, resulting in a short exciton lifetime in the MoS 2 /GaN heterostructure. This interaction enables an enhanced valley helicity at room temperature (0.33 ± 0.05) observed in both steady-state and time-resolved circularly polarized photoluminescence measurements. The findings highlight the importance of substrate engineering for modulating the intrinsic valley carriers in ultrathin 2D materials and potentially open new paths for valleytronics and valley-optoelectronic device applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Non-Faradaic electrochemical detection of protein interactions by integrated neuromorphic CMOS sensors.

PubMed

Jacquot, Blake C; Muñoz, Nini; Branch, Darren W; Kan, Edwin C

2008-05-15

Electronic detection of the binding event between biotinylated bovine serum albumen (BSA) and streptavidin is demonstrated with the chemoreceptive neuron MOS (CnuMOS) device. Differing from the ion-sensitive field-effect transistors (ISFET), CnuMOS, with the potential of the extended floating gate determined by both the sensing and control gates in a neuromorphic style, can provide protein detection without requiring analyte reference electrodes. In comparison with the microelectrode arrays, measurements are gathered through purely capacitive, non-Faradaic interactions across insulating interfaces. By using a (3-glycidoxypropyl)trimethoxysilane (3-GPS) self-assembled monolayer (SAM) as a simple covalent link for attaching proteins to a silicon dioxide sensing surface, a fully integrated, electrochemical detection platform is realized for protein interactions through monotone large-signal measurements or small-signal impedance spectroscopy. Calibration curves were created to coordinate the sensor response with ellipsometric measurements taken on witness samples. By monitoring the film thickness of streptavidin capture, a sensitivity of 25ng/cm2 or 2A of film thickness was demonstrated. With an improved noise floor the sensor can detect down to 2ng/(cm2mV) based on the calibration curve. AC measurements are shown to significantly reduce long-term sensor drift. Finally, a noise analysis of electrochemical data indicates 1/f(alpha) behavior with a noise floor beginning at approximately 1Hz.

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

PubMed

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of Defect Distributions in SiO2/AlGaN/GaN High-Electron-Mobility Transistors by Using Capacitance-Voltage Measurement with Resonant Optical Excitation

NASA Astrophysics Data System (ADS)

Kim, Tae-Soo; Lim, Seung-Young; Park, Yong-Keun; Jung, Gunwoo; Song, Jung-Hoon; Cha, Ho-Young; Han, Sang-Woo

2018-06-01

We investigated the distributions and the energy levels of defects in SiO2/AlGaN/GaN highelectron-mobility transistors (HEMTs) by using frequency-dependent ( F- D) capacitance-voltage ( C- V) measurements with resonant optical excitation. A Schottky barrier (SB) and a metal-oxidesemiconductor (MOS) HEMT were prepared to compare the effects of defects in their respective layers. We also investigated the effects of those layers on the threshold voltage ( V th ). A drastic voltage shift in the C- V curve at higher frequencies was caused by the large number of defect levels in the SiO2/GaN interface. A significant shift in V th with additional light illumination was observed due to a charging of the defect states in the SiO2/GaN interface. The voltage shifts were attributed to the detrapping of defect states at the SiO2/GaN interface.

Investigation of trap states in Al2O3 InAlN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Zhang, Peng; Zhao, Sheng-Lei; Xue, Jun-Shuai; Zhu, Jie-Jie; Ma, Xiao-Hua; Zhang, Jin-Cheng; Hao, Yue

2015-12-01

In this paper the trapping effects in Al2O3/In0.17Al0.83N/GaN MOS-HEMT (here, HEMT stands for high electron mobility transistor) are investigated by frequency-dependent capacitance and conductance analysis. The trap states are found at both the Al2O3/InAlN and InAlN/GaN interface. Trap states in InAlN/GaN heterostructure are determined to have mixed de-trapping mechanisms, emission, and tunneling. Part of the electrons captured in the trap states are likely to tunnel into the two-dimensional electron gas (2DEG) channel under serious band bending and stronger electric field peak caused by high Al content in the InAlN barrier, which explains the opposite voltage dependence of time constant and relation between the time constant and energy of the trap states. Project supported by the Program for National Natural Science Foundation of China (Grant Nos. 61404100 and 61306017).

Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi

2015-02-16

We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with themore » 20-nm-thick GaSb layer.« less

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Reaction of N,N'-dimethylformamide and divalent viologen molecule to generate an organic dopant for molybdenum disulfide

NASA Astrophysics Data System (ADS)

Fukui, A.; Miura, K.; Ichimiya, H.; Tsurusaki, A.; Kariya, K.; Yoshimura, T.; Ashida, A.; Fujimura, N.; Kiriya, D.

2018-05-01

Tuning the carrier concentration is essential for semiconducting materials to apply optoelectronic devices. Molybdenum disulfide (MoS2) is a semiconducting material composed of atomically thin (˜0.7 nm thickness) layers. To dope thin MoS2, instead of using conventional atom/ion injection processes, a surface charge transfer method was successfully applied. In this study, we report a simple preparation method of a molecular dopant applicable to the doping process. The method follows a previous report for producing a molecular dopant, benzyl viologen (BV) which shows electron doping to MoS2. To prepare dopant BV molecules, a reduction process with a commercially available divalent BV by sodium borohydride (NaBH4) is required; however, the reaction requires a large consumption of NaBH4. NaBH4 drastically reacts with the solvent water itself. We found a reaction process of BV in an organic solvent, N,N'-dimethylformamide (DMF), by adding a small amount of water dissolving the divalent BV. The reaction is mild (at room temperature) and is autonomous once DMF comes into contact with the divalent BV aqueous solution. The reaction can be monitored with a UV-Vis spectrometer, and kinetic analysis indicates two reaction steps between divalent/monovalent/neutral viologen isomers. The product was soluble in toluene and did not dissolve in water, indicating it is similar to the reported dopant BV. The synthesized molecule was found to act as a dopant for MoS2 by applying a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure. The process is a general method and applicable to other viologen-related dopants to tune the electronic structure of 2D materials to facilitate generating atomically thin devices.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Flexible organic transistors and circuits with extreme bending stability

NASA Astrophysics Data System (ADS)

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100μm. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5μm), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

The field effect transistor DNA biosensor based on ITO nanowires in label-free hepatitis B virus detecting compatible with CMOS technology.

PubMed

Shariati, Mohsen

2018-05-15

In this paper the field-effect transistor DNA biosensor for detecting hepatitis B virus (HBV) based on indium tin oxide nanowires (ITO NWs) in label free approach has been fabricated. Because of ITO nanowires intensive conductance and functional modified surface, the probe immobilization and target hybridization were increased strongly. The high resolution transmission electron microscopy (HRTEM) measurement showed that ITO nanowires were crystalline and less than 50nm in diameter. The single-stranded hepatitis B virus DNA (SS-DNA) was immobilized as probe on the Au-modified nanowires. The DNA targets were measured in a linear concentration range from 1fM to 10µM. The detection limit of the DNA biosensor was about 1fM. The time of the hybridization process for defined single strand was 90min. The switching ratio of the biosensor between "on" and "off" state was ~ 1.1 × 10 5 . For sensing the specificity of the biosensor, non-complementary, mismatch and complementary DNA oligonucleotide sequences were clearly discriminated. The HBV biosensor confirmed the highly satisfied specificity for differentiating complementary sequences from non-complementary and the mismatch oligonucleotides. The response time of the DNA sensor was 37s with a high reproducibility. The stability and repeatability of the DNA biosensor showed that the peak current of the biosensor retained 98% and 96% of its initial response for measurements after three and five weeks, respectively. Copyright © 2018 Elsevier B.V. All rights reserved.

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

PubMed

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

Scanning Probe Microscopy and Electrical Transport Studies of Ferroelectric Thin Films and 2D van der Waals Materials

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong

In this dissertation, I present the scanning microscopy and electrical transport studies of ferroelectric thin films and ferroic/2D van der Waals heterostructures. Based on the conducting probe atomic force microscopy and piezo-response force microscopy (PFM) studies of the static and dynamic behavior of ferroelectric domain walls (DW), we found that the ferroelectric polymer poly(vinylidene-fluoride-trifluorethylene) P(VDF-TrFE) is composed of two-dimensional (2D) ferroelectric monolayers (MLs) that are weakly coupled to each other. We also observed polarization asymmetry in epitaxial thin films of ferroelectric Pb(Zr,Ti)O3, which is attributed to the screening properties of the underlying conducting oxide. PFM studies also reveal ferroelectric relaxor-type behavior in ultrathin Sr(Zr,Ti)O3 films epitaxially deposited on Ge. We exploited scanning-probe-controlled domain patterning in a P(VDF-TrFE) top layer to induce nonvolatile modulation of the conduction characteristic of ML molybdenum disulfide (MoS2) between a transistor and a junction state. In the presence of a DW, MoS2 exhibits rectified Ids-Vds (IV) characteristics that are well described by the thermionic emission model. This approach can be applied to a wide range of van der Waals materials to design various functional homojunctions and nanostructures. We also studied the interfacial charge transfer effect between graphene and magnetoelectric Cr2O3 via electrostatic force microscopy and Kelvin probe force microscopy, which reveal p-type doping with up to 150 meV shift of the Fermi level. The graphene/Cr2O3 heterostructure is promising for developing magnetoelectric graphene transistors for spintronic applications.

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

PubMed

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

NASA Astrophysics Data System (ADS)

Shiota, Koki; Kai, Kazuho; Nagaoka, Shiro; Tsuji, Takuto; Wakahara, Akihiro; Rusop, Mohamad

2016-07-01

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

Solution-Processable Balanced Ambipolar Field-Effect Transistors Based on Carbonyl-Regulated Copolymers.

PubMed

Yang, Chengdong; Fang, Renren; Yang, Xiongfa; Chen, Ru; Gao, Jianhua; Fan, Hanghong; Li, Hongxiang; Hu, Wenping

2018-04-04

It is very important to develop ambipolar field effect transistors to construct complementary circuits. To obtain balanced hole- and electron-transport properties, one of the key issues is to regulate the energy levels of the frontier orbitals of the semiconductor materials by structural tailoring, so that they match well with the electrode Fermi levels. Five conjugated copolymers were synthesized and exhibited low LUMO energy levels and narrow bandgaps on account of the strong electron-withdrawing effect of the carbonyl groups. Polymer thin film transistors were prepared by using a solution method and exhibited high and balanced hole and electron mobility of up to 0.46 cm 2  V -1  s -1 , which suggested that these copolymers are promising ambipolar semiconductor materials. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Reversible and Precisely Controllable p/n-Type Doping of MoTe2 Transistors through Electrothermal Doping.

PubMed

Chang, Yuan-Ming; Yang, Shih-Hsien; Lin, Che-Yi; Chen, Chang-Hung; Lien, Chen-Hsin; Jian, Wen-Bin; Ueno, Keiji; Suen, Yuen-Wuu; Tsukagoshi, Kazuhito; Lin, Yen-Fu

2018-03-01

Precisely controllable and reversible p/n-type electronic doping of molybdenum ditelluride (MoTe 2 ) transistors is achieved by electrothermal doping (E-doping) processes. E-doping includes electrothermal annealing induced by an electric field in a vacuum chamber, which results in electron (n-type) doping and exposure to air, which induces hole (p-type) doping. The doping arises from the interaction between oxygen molecules or water vapor and defects of tellurium at the MoTe 2 surface, and allows the accurate manipulation of p/n-type electrical doping of MoTe 2 transistors. Because no dopant or special gas is used in the E-doping processes of MoTe 2 , E-doping is a simple and efficient method. Moreover, through exact manipulation of p/n-type doping of MoTe 2 transistors, quasi-complementary metal oxide semiconductor adaptive logic circuits, such as an inverter, not or gate, and not and gate, are successfully fabricated. The simple method, E-doping, adopted in obtaining p/n-type doping of MoTe 2 transistors undoubtedly has provided an approach to create the electronic devices with desired performance. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

NASA Astrophysics Data System (ADS)

Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Moreno-Cadenas, J. A.; Escobosa-Echavarría, A.

2011-03-01

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Measurement of the spin structure function GD1 of the deuteron and its moments at low Q2

NASA Astrophysics Data System (ADS)

Athmakur, Abhiram Goud

This thesis focuses on energy considerations in the MOSFET when we supply a bias to it. We also notice that the length of the MOSFET gets smaller and smaller then for a small release or exchange of energy that may take place in a MOS transistor which can cause a change in the temperature. We have investigated that there is a change in the temperature of the MOSFET when we supply bias to it as we keep reducing the length of the channel. The change in the temperature of the MOSFET is calculated theoretically.

Op. Amps in Power Amplification: A Laboratory Exercise on Feedback.

ERIC Educational Resources Information Center

Borcherds, P. H.

1984-01-01

To demonstrate negative feedback a power amplifier is constructed from an operational amplifier together with a complementary pair of transistors as an output stage. The amplifier is developed and tested stage by stage, and at each stage the defects apparent at the previous stage are eliminated. (JN)

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

NASA Astrophysics Data System (ADS)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena

2016-03-01

Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.

Tri-state logic circuit

NASA Technical Reports Server (NTRS)

Pryor, Richard Lee (Inventor)

1977-01-01

A line driver including a pair of complementary transistors having their conduction paths serially connected between an operating and a reference potential and their bases connected through a first switch to a signal input terminal. A second switch is connected between the common base connection and the common connection of the conduction paths. With the second switch open and the first closed, an output voltage, responsive to the input signal, corresponding to first or second binary values is obtained. When the second switch is closed and the first opened, the transistor pair is turned off, disconnecting the line driver from its load, thereby providing tri-state logic operation.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

An underlap field-effect transistor for electrical detection of influenza

NASA Astrophysics Data System (ADS)

Lee, Kwang-Won; Choi, Sung-Jin; Ahn, Jae-Hyuk; Moon, Dong-Il; Park, Tae Jung; Lee, Sang Yup; Choi, Yang-Kyu

2010-01-01

An underlap channel-embedded field-effect transistor (FET) is proposed for label-free biomolecule detection. Specifically, silica binding protein fused with avian influenza (AI) surface antigen and avian influenza antibody (anti-AI) were designed as a receptor molecule and a target material, respectively. The drain current was significantly decreased after the binding of negatively charged anti-AI on the underlap channel. A set of control experiments supports that only the biomolecules on the underlap channel effectively modulate the drain current. With the merits of a simple fabrication process, complementary metal-oxide-semiconductor compatibility, and enhanced sensitivity, the underlap FET could be a promising candidate for a chip-based biosensor.

Rylene and related diimides for organic electronics.

PubMed

Zhan, Xiaowei; Facchetti, Antonio; Barlow, Stephen; Marks, Tobin J; Ratner, Mark A; Wasielewski, Michael R; Marder, Seth R

2011-01-11

Organic electron-transporting materials are essential for the fabrication of organic p-n junctions, photovoltaic cells, n-channel field-effect transistors, and complementary logic circuits. Rylene diimides are a robust, versatile class of polycyclic aromatic electron-transport materials with excellent thermal and oxidative stability, high electron affinities, and, in many cases, high electron mobilities; they are, therefore, promising candidates for a variety of organic electronics applications. In this review, recent developments in the area of high-electron-mobility diimides based on rylenes and related aromatic cores, particularly perylene- and naphthalene-diimide-based small molecules and polymers, for application in high-performance organic field-effect transistors and photovoltaic cells are summarized and analyzed.

The study of dispersive 'b'-mode in monolayer MoS2 in temperature dependent resonant Raman scattering experiments

NASA Astrophysics Data System (ADS)

Kutrowska-Girzycka, Joanna; Jadczak, Joanna; Bryja, Leszek

2018-07-01

We report on resonant Raman scattering studies of monolayer MoS2 as a function of the excitation laser energy (1.959-2.033 eV) and temperature (T = 7-295 K). In complementary reflectivity contrast experiments we determined the temperature evolution of the A exciton and trion resonances. We focus our studies on the dispersive, second order 'b' mode related to the resonant two phonon Raman process of successive emissions of the acoustic LA and TA phonons at K points. We found that when excitation laser energy is tuned across the A exciton level this mode shifts almost linearly to lower frequency with the rate equal -83 and -71 cm-1/eV at T = 7 and 295 K, respectively, which is about two times higher rate than those reported in the previous studies of monolayer MoS2 but very close the relevant rate recorded for bulk MoS2. We interpret this effect as related to the difference of concentration of two dimensional electron gas. We also determined, using excitation with the He-Ne laser the temperature shifts of the Raman peaks of dispersive 'b' and dispersionless E‧ and A1‧ modes. We found that absolute value of the temperature coefficient of 'b' mode, equals 3.5 × 10-2 cm-1/K, is much higher than those of E‧ and A1‧ modes, equal 0.4 × 10-2 and 0.8 × 10-2 cm-1/K, respectively.

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

PubMed

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

NASA Astrophysics Data System (ADS)

Davidović, Vojkan; Danković, Danijel; Ilić, Aleksandar; Manić, Ivica; Golubović, Snežana; Djorić-Veljković, Snežana; Prijić, Zoran; Prijić, Aneta; Stojadinović, Ninoslav

2018-04-01

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Investigation of Gallium Nitride Transistor Reliability through Accelerated Life Testing and Modeling

DTIC Science & Technology

2011-12-01

Carbon Cd Cadmium CdS Cadmium Sulfide CMOS Complementary Metal Oxide Semiconductor DC Direct Current DoD Department of Defense EBL Electron...Crane Division [NAVSEA Crane], Crane, Indiana ) are Section 4.1and Section 4.3, Condition 2. Eight devices were stressed for over 1000 hours each and

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

NASA Astrophysics Data System (ADS)

Knoll, L.; Richter, S.; Nichau, A.; Trellenkamp, S.; Schäfer, A.; Wirths, S.; Blaeser, S.; Buca, D.; Bourdelle, K. K.; Zhao, Q.-T.; Mantl, S.

2014-08-01

Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78 μA/μm at VD = VG = 1.1 V is obtained.

Comparison of conductor and dielectric inks in printed organic complementary transistors

NASA Astrophysics Data System (ADS)

Ng, Tse Nga; Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Abraham, Biby; Wu, Yiliang; Veres, Janos

2014-10-01

Two types of printable conductor and a bilayer gate dielectric are evaluated for use in all-additive, inkjetprinted complementary OTFTs. The Ag nanoparticle ink based on nonpolar alkyl amine surfactant or stabilizer enables good charge injection into p-channel devices, but this ink also leaves residual stabilizer that modifies the transistor backchannel and shifts the turn-on voltage to negative values. The Ag ink based on polar solvent requires dopant modification to improve charge injection to p-channel devices, but this ink allows the OTFT turn-on voltage to be close to 0 V. The reverse trend is observed for n-channel OTFTs. For gate insulator, a bilayer dielectric is demonstrated that combines the advantages of two types of insulator materials, in which a fluoropolymer reduces dipolar disorder at the semiconductor-dielectric interface, while a high-k PVDF terpolymer dielectric facilitates high gate capacitance. The dielectric is incorporated into an inverter and a three-stage ring oscillator, and the resulting circuits were demonstrated to operate at a supply voltage as low as 2 V, with bias stress levels comparable to circuits with other types of dielectrics.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shiota, Koki, E-mail: a14510@sr.kagawa-nct.ac.jp; Kai, Kazuho; Nagaoka, Shiro, E-mail: nagaoka@es.kagawa-nct.ac.jp

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As themore » result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.« less

Patterning layer-by-layer self-assembled multilayer by lithography and its applications to thin film devices

NASA Astrophysics Data System (ADS)

Hua, Feng

Nanoparticles are exciting materials because they exhibit unique electronic, catalytic, and optical properties. As a novel and promising nanobuilding block, it attracts considerable research efforts in its integration into a wide variety of thin film devices. Nanoparticles were adsorbed onto the substrate with layer-by-layer self-assembly which becomes of great interest due to its suitability in colloid particle assembly. Without extremely high temperatures and sophisticated equipment, molecularly organized films in an exactly pre-designed order can grow on almost all the substrates in nature. Two approaches generating spatially separated patterns comprised of nanoparticles are demonstrated, as well as two approaches patterning more than one type of nonoparticle on a silicon wafer. The structure of the thin film patterned by these approaches are analyzed and considered suitable to the thin film device. Finally, the combination of lithography and layer-by-layer (lbl) self-assembly is utilized to realize the microelectronic device with functional nonoparticles. The lbl self-assembly is the way to coat the nonoparticles and the lighography to pattern them. Based on the coating and patterning technique, a MOS-capacitor, a MOS field-effect-transistor and magnetic thin film cantilever are fabricated.

Black phosphorus-monolayer MoS2 van der Waals heterojunction p-n diode.

PubMed

Deng, Yexin; Luo, Zhe; Conrad, Nathan J; Liu, Han; Gong, Yongji; Najmaei, Sina; Ajayan, Pulickel M; Lou, Jun; Xu, Xianfan; Ye, Peide D

2014-08-26

Phosphorene, a elemental 2D material, which is the monolayer of black phosphorus, has been mechanically exfoliated recently. In its bulk form, black phosphorus shows high carrier mobility (∼10,000 cm(2)/V·s) and a ∼0.3 eV direct band gap. Well-behaved p-type field-effect transistors with mobilities of up to 1000 cm(2)/V·s, as well as phototransistors, have been demonstrated on few-layer black phosphorus, showing its promise for electronics and optoelectronics applications due to its high hole mobility and thickness-dependent direct band gap. However, p–n junctions, the basic building blocks of modern electronic and optoelectronic devices, have not yet been realized based on black phosphorus. In this paper, we demonstrate a gate-tunable p–n diode based on a p-type black phosphorus/n-type monolayer MoS2 van der Waals p–n heterojunction. Upon illumination, these ultrathin p–n diodes show a maximum photodetection responsivity of 418 mA/W at the wavelength of 633 nm and photovoltaic energy conversion with an external quantum efficiency of 0.3%. These p–n diodes show promise for broad-band photodetection and solar energy harvesting.

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

PubMed Central

Rossi, Alessandro; Tanttu, Tuomo; Hudson, Fay E.; Sun, Yuxin; Möttönen, Mikko; Dzurak, Andrew S.

2015-01-01

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization. PMID:26067215

Quantitative measurements of nanoscale permittivity and conductivity using tuning-fork-based microwave impedance microscopy

NASA Astrophysics Data System (ADS)

Wu, Xiaoyu; Hao, Zhenqi; Wu, Di; Zheng, Lu; Jiang, Zhanzhi; Ganesan, Vishal; Wang, Yayu; Lai, Keji

2018-04-01

We report quantitative measurements of nanoscale permittivity and conductivity using tuning-fork (TF) based microwave impedance microscopy (MIM). The system is operated under the driving amplitude modulation mode, which ensures satisfactory feedback stability on samples with rough surfaces. The demodulated MIM signals on a series of bulk dielectrics are in good agreement with results simulated by finite-element analysis. Using the TF-MIM, we have visualized the evolution of nanoscale conductance on back-gated MoS2 field effect transistors, and the results are consistent with the transport data. Our work suggests that quantitative analysis of mesoscopic electrical properties can be achieved by near-field microwave imaging with small distance modulation.

Topography preserved microwave plasma etching for top-down layer engineering in MoS2 and other van der Waals materials.

PubMed

Varghese, Abin; Sharma, Chithra H; Thalakulam, Madhu

2017-03-17

A generic and universal layer engineering strategy for van der Waals (vW) materials, scalable and compatible with the current semiconductor technology, is of paramount importance in realizing all-two-dimensional logic circuits and to move beyond the silicon scaling limit. In this letter, we demonstrate a scalable and highly controllable microwave plasma based layer engineering strategy for MoS 2 and other vW materials. Using this technique we etch MoS 2 flakes layer-by-layer starting from an arbitrary thickness and area down to the mono- or the few-layer limit. From Raman spectroscopy, atomic force microscopy, photoluminescence spectroscopy, scanning electron microscopy and transmission electron microscopy, we confirm that the structural and morphological properties of the material have not been compromised. The process preserves the pre-etch layer topography and yields a smooth and pristine-like surface. We explore the electrical properties utilising a field effect transistor geometry and find that the mobility values of our samples are comparable to those of the pristine ones. The layer removal does not involve any reactive gasses or chemical reactions and relies on breaking the weak inter-layer vW interaction making it a generic technique for a wide spectrum of layered materials and heterostructures. We demonstrate the wide applicability of the technique by extending it to other systems such as graphene, h-BN and WSe 2 . In addition, using microwave plasma in combination with standard lithography, we illustrate a lateral patterning scheme making this process a potential candidate for large scale device fabrication in addition to layer engineering.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

NASA Astrophysics Data System (ADS)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Browning, Robert

In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the same qualities as those of the mechanically exfoliated films. Back-gated field effect transistors were created and electrical characterization was performed to determine if ALD grown films possess the same electronic properties as films produced from other methods. The tests revealed that the ALD grown films have high field effect mobility and high current on/off ratios. The WSe2 films also exhibited ambipolar electrical behavior making them a possible candidate for complementary metal-oxide semiconductor (CMOS) technology. Ab-initio density functional theory calculations were performed and compared to experimental properties of MoS2 and WSe2 films, which show that the ALD films grown in this research match theoretical predictions. The transconductance measurements from the WSe2 devices used, matched very well with the theoretical calculations, bridging the gap between experimental data and theoretical predictions. Based upon this research, ALD growth of TMD films proves to be a viable alternative for silicon based digital electronics.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Antimicrobial Properties of 2D MnO2 and MoS2 Nanomaterials Vertically Aligned on Graphene Materials and Ti3C2 MXene.

PubMed

Alimohammadi, Farbod; Sharifian Gh, Mohammad; Attanayake, Nuwan H; Thenuwara, Akila C; Gogotsi, Yury; Anasori, Babak; Strongin, Daniel R

2018-06-07

Two-dimensional (2D) nanomaterials have attracted considerable attention in biomedical and environmental applications due to their antimicrobial activity. In the interest of investigating the primary antimicrobial mode-of-action of 2D nanomaterials, we studied the antimicrobial properties of MnO 2 and MoS 2 , toward Gram-positive and Gram-negative bacteria. Bacillus subtilis and Escherichia coli bacteria were treated individually with 100 μg/mL of randomly oriented and vertically aligned nanomaterials for ∼3 h in the dark. The vertically aligned 2D MnO 2 and MoS 2 were grown on 2D sheets of graphene oxide, reduced graphene oxide, and Ti 3 C 2 MXene. Measurements to determine the viability of bacteria in the presence of the 2D nanomaterials performed by using two complementary techniques, flow cytometry, and fluorescence imaging showed that, while MnO 2 and MoS 2 nanosheets show different antibacterial activities, in both cases, Gram-positive bacteria show a higher loss in membrane integrity. Scanning electron microscopy images suggest that the 2D nanomaterials, which have a detrimental effect on bacteria viability, compromise the cell wall, leading to significant morphological changes. We propose that the peptidoglycan mesh (PM) in the bacterial wall is likely the primary target of the 2D nanomaterials. Vertically aligned 2D MnO 2 nanosheets showed the highest antimicrobial activity, suggesting that the edges of the nanosheets were likely compromising the cell walls upon contact.

Low-Dimensional Nanomaterials and Molecular Dielectrics for Radiation-Hard Electronics

NASA Astrophysics Data System (ADS)

McMorrow, Julian

The electronic materials research driving Moore's law has provided several decades of increasingly powerful yet simultaneously miniaturized computer technologies. As we approach the physical and practical limits of what can be accomplished with silicon electronics, we look to new materials to drive innovation in future electronic applications. New materials paradigms require the development of understanding from first principles to the demonstration of applications that comes with mature technologies. Semiconducting single-walled carbon nanotubes (SWCNTs), single- and few-layer molybdenum disulfide (MoS2) and self-assembled nanodielectric (SAND) gate materials have all made significant impacts in the research field of unconventional electronic materials. The materials selection, interfaces between materials, processing steps to assemble them, and their interaction with their environment all have significant bearing on the operation of the overall device. Operating in harsh radiation environments, like those of satellites orbiting the Earth, present unique challenges to the functionality and reliability of electronic devices. Because the future of space-bound electronics is often informed by the technology of terrestrial devices, a proactive approach is adopted to identify and understand the radiation response of new materials systems as they emerge and develop. The work discussed here drives the innovation and development of multiple nanomaterial based electronic technologies while simultaneously exploring their relevant radiation response mechanisms. First, collaborative efforts result in the demonstration of a SWCNT-based circuit technology that is solution processed, large-area, and compatible with flexible substrates. The statistical characterization of SWCNT transistors enables the development of robust doping and encapsulation schemes, which make the SWCNT circuits stable, scalable, and low-power. These SWCNTs are then integrated into static random access memory (SRAM) cells, an accomplishment that illustrates the technological relevance of this work by implementing a highly utilized component of modern day computing. Next, these SRAM devices demonstrate functionality as true random number generators (TRNGs), which are critical components in cryptography and encryption. The randomness of these SWCNT TRNGs is verified by a suite of statistical tests. This achievement has implications for securing data and communication in future solution-processed, large-area, flexible electronics. The unprecedented integration achieved by the underlying SWCNT doping and encapsulation motivates the study of this technology in a radiation environment. Doing so results in an understanding of the fundamental charge trapping mechanisms responsible for the radiation response in this system. The integrated nature of these devices enables, for the first time, the observation of system-level effects in a SWCNT integrated circuit technology. This technology is found to be total ionizing dose-hard, a promising result for the adoption of SWCNTs in future space-bound applications. Compared to SWCNTs, the field of MoS2 electronics is relatively nascent. As a result, studies of radiation effects in MoS2 devices focus on the fundamental mechanisms at play in the materials system. Here, we reveal the critical role of atmospheric adsorbates in the radiation effects of MoS2 transistors by measuring their response to vacuum ultraviolet radiation. These results highlight the importance of controlling the atmosphere of MoS2 devices during irradiation. Furthermore, we make recommendations for radiation-hard MoS2-based devices in the future as the technology continues to mature. One such recommendation is the incorporation of specialized dielectrics with proven radiation hardness. To this end, we address the materials integration challenge of incorporating SAND gate dielectrics on arbitrary substrates. We explore a novel approach for preparing metal substrates for SAND deposition, supporting the SAND superlattice structure and its superlative electronic properties on a metal surface. This result is critical for conducting fundamental transport studies when integrating SAND with novel semiconductor materials, as well as enabling complex circuit integration and SAND on flexible substrates. Altogether, these works drive the integration of novel nanoelectronic materials for future electronics while providing an understanding of their varying radiation response mechanisms to enable their adoption in future space-bound applications.

Wide-Temperature-Range Integrated Operational Amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

2007-01-01

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

A new expression of Ns versus Ef to an accurate control charge model for AlGaAs/GaAs

NASA Astrophysics Data System (ADS)

Bouneb, I.; Kerrour, F.

2016-03-01

Semi-conductor components become the privileged support of information and communication, particularly appreciation to the development of the internet. Today, MOS transistors on silicon dominate largely the semi-conductors market, however the diminution of transistors grid length is not enough to enhance the performances and respect Moore law. Particularly, for broadband telecommunications systems, where faster components are required. For this reason, alternative structures proposed like hetero structures IV-IV or III-V [1] have been.The most effective components in this area (High Electron Mobility Transistor: HEMT) on IIIV substrate. This work investigates an approach for contributing to the development of a numerical model based on physical and numerical modelling of the potential at heterostructure in AlGaAs/GaAs interface. We have developed calculation using projective methods allowed the Hamiltonian integration using Green functions in Schrodinger equation, for a rigorous resolution “self coherent” with Poisson equation. A simple analytical approach for charge-control in quantum well region of an AlGaAs/GaAs HEMT structure was presented. A charge-control equation, accounting for a variable average distance of the 2-DEG from the interface was introduced. Our approach which have aim to obtain ns-Vg characteristics is mainly based on: A new linear expression of Fermi-level variation with two-dimensional electron gas density in high electron mobility and also is mainly based on the notion of effective doping and a new expression of AEc

InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current

NASA Astrophysics Data System (ADS)

Peng, Yue; Han, Genquan; Wang, Hongjuan; Zhang, Chunfu; Liu, Yan; Wang, Yibo; Zhao, Shenglei; Zhang, Jincheng; Hao, Yue

2016-05-01

InN/In0.75Ga0.25N complementary heterojunction-enhanced tunneling field-effect transistors (HE-TFETs) were characterized using the numerical simulation. InN/In0.75Ga0.25N HE-TFET has an InN/In0.75Ga0.25N heterojunction located in the channel region with a distance of LT-H from the source/channel tunneling junction. We demonstrate that, for both n- and p-channel devices, HE-TFETs have a delay of onset voltage VONSET, a steeper subthreshold swing (SS), and an enhanced on-state current ION in comparison with the homo-TFETs. InN/In0.75Ga0.25N n- and p-channel HE-TFETs with a gate length LG of 25 nm and a LT-H of 5 nm achieve a 7 and 9 times ION improvement in comparison with the homo devices, respectively, at a supply voltage of 0.3 V. The performance enhancement in HE-TFETs is attributed to the modulating effect of heterojunction on band-to-band tunneling (BTBT). Because InN/In0.75Ga0.25N heterointerface shows the similar band offsets at conduction and valence bands, the InN/In0.75Ga0.25N heterojunction exhibits the improved effect on BTBT for both n- and p-channel devices. This makes InN/In0.75Ga0.25N heterojunction a promising structure for high performance complementary TFETs.

Dynamic and Tunable Threshold Voltage in Organic Electrochemical Transistors.

PubMed

Doris, Sean E; Pierre, Adrien; Street, Robert A

2018-04-01

In recent years, organic electrochemical transistors (OECTs) have found applications in chemical and biological sensing and interfacing, neuromorphic computing, digital logic, and printed electronics. However, the incorporation of OECTs in practical electronic circuits is limited by the relative lack of control over their threshold voltage, which is important for controlling the power consumption and noise margin in complementary and unipolar circuits. Here, the threshold voltage of OECTs is precisely tuned over a range of more than 1 V by chemically controlling the electrochemical potential at the gate electrode. This threshold voltage tunability is exploited to prepare inverters and amplifiers with improved noise margin and gain, respectively. By coupling the gate electrode with an electrochemical oscillator, single-transistor oscillators based on OECTs with dynamic time-varying threshold voltages are prepared. This work highlights the importance of electrochemistry at the gate electrode in determining the electrical properties of OECTs, and opens a path toward the system-level design of low-power OECT-based electronics. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

NASA Astrophysics Data System (ADS)

Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

2014-04-01

Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Dual-Mode Gas Sensor Composed of a Silicon Nanoribbon Field Effect Transistor and a Bulk Acoustic Wave Resonator: A Case Study in Freons

PubMed Central

Chang, Ye; Hui, Zhipeng; Wang, Xiayu; Qu, Hemi; Pang, Wei

2018-01-01

In this paper, we develop a novel dual-mode gas sensor system which comprises a silicon nanoribbon field effect transistor (Si-NR FET) and a film bulk acoustic resonator (FBAR). We investigate their sensing characteristics using polar and nonpolar organic compounds, and demonstrate that polarity has a significant effect on the response of the Si-NR FET sensor, and only a minor effect on the FBAR sensor. In this dual-mode system, qualitative discrimination can be achieved by analyzing polarity with the Si-NR FET and quantitative concentration information can be obtained using a polymer-coated FBAR with a detection limit at the ppm level. The complementary performance of the sensing elements provides higher analytical efficiency. Additionally, a dual mixture of two types of freons (CFC-113 and HCFC-141b) is further analyzed with the dual-mode gas sensor. Owing to the small size and complementary metal-oxide semiconductor (CMOS)-compatibility of the system, the dual-mode gas sensor shows potential as a portable integrated sensing system for the analysis of gas mixtures in the future. PMID:29370109

Dual-Mode Gas Sensor Composed of a Silicon Nanoribbon Field Effect Transistor and a Bulk Acoustic Wave Resonator: A Case Study in Freons.

PubMed

Chang, Ye; Hui, Zhipeng; Wang, Xiayu; Qu, Hemi; Pang, Wei; Duan, Xuexin

2018-01-25

In this paper, we develop a novel dual-mode gas sensor system which comprises a silicon nanoribbon field effect transistor (Si-NR FET) and a film bulk acoustic resonator (FBAR). We investigate their sensing characteristics using polar and nonpolar organic compounds, and demonstrate that polarity has a significant effect on the response of the Si-NR FET sensor, and only a minor effect on the FBAR sensor. In this dual-mode system, qualitative discrimination can be achieved by analyzing polarity with the Si-NR FET and quantitative concentration information can be obtained using a polymer-coated FBAR with a detection limit at the ppm level. The complementary performance of the sensing elements provides higher analytical efficiency. Additionally, a dual mixture of two types of freons (CFC-113 and HCFC-141b) is further analyzed with the dual-mode gas sensor. Owing to the small size and complementary metal-oxide semiconductor (CMOS)-compatibility of the system, the dual-mode gas sensor shows potential as a portable integrated sensing system for the analysis of gas mixtures in the future.

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

NASA Astrophysics Data System (ADS)

Shin, Sunhae; Rok Kim, Kyung

2015-06-01

In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

PubMed Central

Papadimitriou, Konstantinos I.; Liu, Shih-Chii; Indiveri, Giacomo; Drakakis, Emmanuel M.

2014-01-01

The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framework. The speed advantage of the proposed mathematical framework as an analysis tool is also demonstrated by a compelling comparative circuit analysis example of high order, where the GBCF and another well-known log-domain circuit analysis method are used for the determination of the input-output transfer function of the high (4th) order topology. PMID:25653579

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

PubMed Central

Boukhayma, Assim; Peizerat, Arnaud; Enz, Christian

2016-01-01

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.