Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

System-on-Chip Design and Implementation

ERIC Educational Resources Information Center

Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.

2010-01-01

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant…

Heat-driven liquid metal cooling device for the thermal management of a computer chip

NASA Astrophysics Data System (ADS)

Ma, Kun-Quan; Liu, Jing

2007-08-01

The tremendous heat generated in a computer chip or very large scale integrated circuit raises many challenging issues to be solved. Recently, liquid metal with a low melting point was established as the most conductive coolant for efficiently cooling the computer chip. Here, by making full use of the double merits of the liquid metal, i.e. superior heat transfer performance and electromagnetically drivable ability, we demonstrate for the first time the liquid-cooling concept for the thermal management of a computer chip using waste heat to power the thermoelectric generator (TEG) and thus the flow of the liquid metal. Such a device consumes no external net energy, which warrants it a self-supporting and completely silent liquid-cooling module. Experiments on devices driven by one or two stage TEGs indicate that a dramatic temperature drop on the simulating chip has been realized without the aid of any fans. The higher the heat load, the larger will be the temperature decrease caused by the cooling device. Further, the two TEGs will generate a larger current if a copper plate is sandwiched between them to enhance heat dissipation there. This new method is expected to be significant in future thermal management of a desk or notebook computer, where both efficient cooling and extremely low energy consumption are of major concern.

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

A Reduced Order Model for Whole-Chip Thermal Analysis of Microfluidic Lab-on-a-Chip Systems

PubMed Central

Wang, Yi; Song, Hongjun; Pant, Kapil

2013-01-01

This paper presents a Krylov subspace projection-based Reduced Order Model (ROM) for whole microfluidic chip thermal analysis, including conjugate heat transfer. Two key steps in the reduced order modeling procedure are described in detail, including (1) the acquisition of a 3D full-scale computational model in the state-space form to capture the dynamic thermal behavior of the entire microfluidic chip; and (2) the model order reduction using the Block Arnoldi algorithm to markedly lower the dimension of the full-scale model. Case studies using practically relevant thermal microfluidic chip are undertaken to establish the capability and to evaluate the computational performance of the reduced order modeling technique. The ROM is compared against the full-scale model and exhibits good agreement in spatiotemporal thermal profiles (<0.5% relative error in pertinent time scales) and over three orders-of-magnitude acceleration in computational speed. The salient model reusability and real-time simulation capability renders it amenable for operational optimization and in-line thermal control and management of microfluidic systems and devices. PMID:24443647

High-density, fail-in-place switches for computer and data networks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Coteus, Paul W.; Doany, Fuad E.; Hall, Shawn A.

A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

High performance flight computer developed for deep space applications

NASA Technical Reports Server (NTRS)

Bunker, Robert L.

1993-01-01

The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.

Architectures for single-chip image computing

NASA Astrophysics Data System (ADS)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Proton Upset Monte Carlo Simulation

NASA Technical Reports Server (NTRS)

O'Neill, Patrick M.; Kouba, Coy K.; Foster, Charles C.

2009-01-01

The Proton Upset Monte Carlo Simulation (PROPSET) program calculates the frequency of on-orbit upsets in computer chips (for given orbits such as Low Earth Orbit, Lunar Orbit, and the like) from proton bombardment based on the results of heavy ion testing alone. The software simulates the bombardment of modern microelectronic components (computer chips) with high-energy (.200 MeV) protons. The nuclear interaction of the proton with the silicon of the chip is modeled and nuclear fragments from this interaction are tracked using Monte Carlo techniques to produce statistically accurate predictions.

Recovery of gold from computer circuit board scrap using aqua regia.

PubMed

Sheng, Peter P; Etsell, Thomas H

2007-08-01

Computer circuit board scrap was first treated with one part concentrated nitric acid and two parts water at 70 degrees C for 1 h. This step dissolved the base metals, thereby liberating the chips from the boards. After solid-liquid separation, the chips, intermixed with some metallic flakes and tin oxide precipitate, were mechanically crushed to liberate the base and precious metals contained within the protective plastic or ceramic chip cases. The base metals in this crushed product were dissolved by leaching again with the same type of nitric acid-water solution. The remaining solid constituents, crushed chips and resin, plus solid particles of gold, were leached with aqua regia at various times and temperatures. Gold was precipitated from the leachate with ferrous sulphate.

Chips: A Tool for Developing Software Interfaces Interactively.

ERIC Educational Resources Information Center

Cunningham, Robert E.; And Others

This report provides a detailed description of Chips, an interactive tool for developing software employing graphical/computer interfaces on Xerox Lisp machines. It is noted that Chips, which is implemented as a collection of customizable classes, provides the programmer with a rich graphical interface for the creation of rich graphical…

Accelerator on a Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

England, Joel

2014-06-30

SLAC's Joel England explains how the same fabrication techniques used for silicon computer microchips allowed their team to create the new laser-driven particle accelerator chips. (SLAC Multimedia Communications)

Accelerator on a Chip

ScienceCinema

England, Joel

2018-01-16

SLAC's Joel England explains how the same fabrication techniques used for silicon computer microchips allowed their team to create the new laser-driven particle accelerator chips. (SLAC Multimedia Communications)

Architectures for Cognitive Systems

DTIC Science & Technology

2010-02-01

highly modular many- node chip was designed which addressed power efficiency to the maximum extent possible. Each node contains an Asynchronous Field...optimization to perform complex cognitive computing operations. This project focused on the design of the core and integration across a four node chip . A...follow on project will focus on creating a 3 dimensional stack of chips that is enabled by the low power usage. The chip incorporates structures to

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

Imaging without lenses: achievements and remaining challenges of wide-field on-chip microscopy

PubMed Central

Greenbaum, Alon; Luo, Wei; Su, Ting-Wei; Göröcs, Zoltán; Xue, Liang; Isikman, Serhan O; Coskun, Ahmet F; Mudanyali, Onur; Ozcan, Aydogan

2012-01-01

We discuss unique features of lens-free computational imaging tools and report some of their emerging results for wide-field on-chip microscopy, such as the achievement of a numerical aperture (NA) of ~0.8–0.9 across a field of view (FOV) of more than 20 mm2 or an NA of ~0.1 across a FOV of ~18 cm2, which corresponds to an image with more than 1.5 gigapixels. We also discuss the current challenges that these computational on-chip microscopes face, shedding light on their future directions and applications. PMID:22936170

LLNL Partners with IBM on Brain-Like Computing Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Essen, Brian

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

LLNL Partners with IBM on Brain-Like Computing Chip

ScienceCinema

Van Essen, Brian

2018-06-25

Lawrence Livermore National Laboratory (LLNL) will receive a first-of-a-kind brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a breakthrough neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses and consume the energy equivalent of a hearing aid battery – a mere 2.5 watts of power. The brain-like, neural network design of the IBM Neuromorphic System is able to infer complex cognitive tasks such as pattern recognition and integrated sensory processing far more efficiently than conventional chips.

GRAPE-5: A Special-Purpose Computer for N-Body Simulations

NASA Astrophysics Data System (ADS)

Kawai, Atsushi; Fukushige, Toshiyuki; Makino, Junichiro; Taiji, Makoto

2000-08-01

We have developed a special-purpose computer for gravitational many-body simulations, GRAPE-5. GRAPE-5 accelerates the force calculation which dominates the calculation cost of the simulation. All other calculations, such as the time integration of orbits, are performed on a general-purpose computer (host computer) connected to GRAPE-5. A GRAPE-5 board consists of eight custom pipeline chips (G5 chip) and its peak performance is 38.4 Gflops. GRAPE-5 is the successor of GRAPE-3. The differences between GRAPE-5 and GRAPE-3 are: (1) The newly developed G5 chip contains two pipelines operating at 80 MHz, while the GRAPE chip, which was used for GRAPE-3, had one at 20 MHz. The calculation speed of GRAPE-5 is 8-times faster than that of GRAPE-3. (2) The GRAPE-5 board adopted a PCI bus as the interface to the host computer instead of VME of GRAPE-3, resulting in a communication speed one order of magnitude faster. (3) In addition to the pure 1/r potential, the G5 chip can calculate forces with arbitrary cutoff functions, so that it can be applied to the Ewald or P3M methods. (4) The pairwise force calculated on GRAPE-5 is about 10-times more accurate than that on GRAPE-3. On one GRAPE-5 board, one timestep with a direct summation algorithm takes 14 (N/128 k)2 seconds. With the Barnes-Hut tree algorithm (theta = 0.75), one timestep can be done in 15 (N/106) seconds.

Wireless Interconnects for Intra-chip & Inter-chip Transmission

NASA Astrophysics Data System (ADS)

Narde, Rounak Singh

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS.

Fault-tolerant computer study. [logic designs for building block circuits

NASA Technical Reports Server (NTRS)

Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.

1981-01-01

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Compact Multimedia Systems in Multi-chip Module Technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Alkalaj, Leon

1995-01-01

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

Sustaining Moore's law with 3D chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik P.; Badaroglu, Mustafa; Chen, An

Here, rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore's law on its traditional scaling path.

Sustaining Moore's law with 3D chips

DOE PAGES

DeBenedictis, Erik P.; Badaroglu, Mustafa; Chen, An; ...

2017-08-01

Here, rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore's law on its traditional scaling path.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

PubMed Central

Indiveri, Giacomo

2008-01-01

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention. PMID:27873818

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

PubMed

Indiveri, Giacomo

2008-09-03

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Associative architecture for image processing

NASA Astrophysics Data System (ADS)

Adar, Rutie; Akerib, Avidan

1997-09-01

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

Slow Computing Simulation of Bio-plausible Control

DTIC Science & Technology

2012-03-01

information networks, neuromorphic chips would become necessary. Small unstable flying platforms currently require RTK, GPS, or Vicon closed-circuit...Visual, and IR Sensing FPGA ASIC Neuromorphic Chip Simulation Quad Rotor Robotic Insect Uniform Independent Network Single Modality Neural Network... neuromorphic Processing across parallel computational elements =0.54 N u m b e r o f c o m p u ta tio n s - No info 14 integrated circuit

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Patrick

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

Siemens, Philips megaproject to yield superchip in 5 years

NASA Astrophysics Data System (ADS)

1985-02-01

The development of computer chips using complementary metal oxide semiconductor (CMOS) memory technology is described. The management planning and marketing strategy of the Philips and Siemens corporations with regard to the memory chip are discussed.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Quantum Optics in Diamond Nanophotonic Chips

DTIC Science & Technology

2014-07-01

quantum cryptography , quantum teleportation, quantum computation. Springer-Verlag, London, UK, 2000. 8 [3] J. I. Cirac, P. Zoller, H. J. Kimble, and...AFRL-OSR-VA-TR-2014-0188 Quantum Optics in Diamond Nanophotonic Chips Dirk Englund THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK INC...Progress Report Program Manager: Dr. Gernot Pomrenke Quantum Optics in Diamond Nanophotonic Chips AFOSR Directorate: Physics and Electronics Research

Picoradio: Communication/Computation Piconodes for Sensor Networks

DTIC Science & Technology

2003-01-02

diagram of PicoNode III, or Quark node. It is made from two custom chips, Strange RF and Charm digital processor , and is complemented by a set of...the chipset comprising of Strange (analog OOK transceiver) and Charm (digital processor ) chips. 44 Figure 33: System block diagram of the Quark node...19 2.B PICONODE II - TWO-CHIP PICONODE IMPLEMENTATION ......................................... 21 2.B.1 Baseband processor (BBP

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

NASA Astrophysics Data System (ADS)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

Determining Light Transmittance Characteristics of Wood and Bark Chips

Treesearch

Douglas B. Brumm; Robert C. Radcliffe; John A. Sturos

1983-01-01

Describes compter-assisted testing for measuring light transmittance of wood and bark chips. Electronic interface permitted the computer to collect physical data accurately and efficiently and to analyze and present the data in several tabular and grapical formats

Progress in a novel architecture for high performance processing

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin

2018-04-01

The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W).

Identifying the impact of G-quadruplexes on Affymetrix 3' arrays using cloud computing.

PubMed

Memon, Farhat N; Owen, Anne M; Sanchez-Graillet, Olivia; Upton, Graham J G; Harrison, Andrew P

2010-01-15

A tetramer quadruplex structure is formed by four parallel strands of DNA/ RNA containing runs of guanine. These quadruplexes are able to form because guanine can Hoogsteen hydrogen bond to other guanines, and a tetrad of guanines can form a stable arrangement. Recently we have discovered that probes on Affymetrix GeneChips that contain runs of guanine do not measure gene expression reliably. We associate this finding with the likelihood that quadruplexes are forming on the surface of GeneChips. In order to cope with the rapidly expanding size of GeneChip array datasets in the public domain, we are exploring the use of cloud computing to replicate our experiments on 3' arrays to look at the effect of the location of G-spots (runs of guanines). Cloud computing is a recently introduced high-performance solution that takes advantage of the computational infrastructure of large organisations such as Amazon and Google. We expect that cloud computing will become widely adopted because it enables bioinformaticians to avoid capital expenditure on expensive computing resources and to only pay a cloud computing provider for what is used. Moreover, as well as financial efficiency, cloud computing is an ecologically-friendly technology, it enables efficient data-sharing and we expect it to be faster for development purposes. Here we propose the advantageous use of cloud computing to perform a large data-mining analysis of public domain 3' arrays.

Bone chip-induced rhinosinusitis.

PubMed

Reilly, Brian K; Conley, David B

2009-12-01

This case report describes both the pathophysiology and management of chronic rhinosinusitis (CRS). Specifically, we report a case of chronic maxillary rhinosinusitis with a free-floating maxillary sinus calcification (bone chip). After obtaining the computed tomography scan, the patient underwent endoscopic sinus surgery, with removal of the uncinate, enlargement of the diseased natural ostium of the maxillary sinus, and removal of the diseased bone chip. This eliminated the nidus for infection, ultimately restoring mucociliary flow.

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Computation and brain processes, with special reference to neuroendocrine systems.

PubMed

Toni, Roberto; Spaletta, Giulia; Casa, Claudia Della; Ravera, Simone; Sandri, Giorgio

2007-01-01

The development of neural networks and brain automata has made neuroscientists aware that the performance limits of these brain-like devices lies, at least in part, in their computational power. The computational basis of a. standard cybernetic design, in fact, refers to that of a discrete and finite state machine or Turing Machine (TM). In contrast, it has been suggested that a number of human cerebral activites, from feedback controls up to mental processes, rely on a mixing of both finitary, digital-like and infinitary, continuous-like procedures. Therefore, the central nervous system (CNS) of man would exploit a form of computation going beyond that of a TM. This "non conventional" computation has been called hybrid computation. Some basic structures for hybrid brain computation are believed to be the brain computational maps, in which both Turing-like (digital) computation and continuous (analog) forms of calculus might occur. The cerebral cortex and brain stem appears primary candidate for this processing. However, also neuroendocrine structures like the hypothalamus are believed to exhibit hybrid computional processes, and might give rise to computational maps. Current theories on neural activity, including wiring and volume transmission, neuronal group selection and dynamic evolving models of brain automata, bring fuel to the existence of natural hybrid computation, stressing a cooperation between discrete and continuous forms of communication in the CNS. In addition, the recent advent of neuromorphic chips, like those to restore activity in damaged retina and visual cortex, suggests that assumption of a discrete-continuum polarity in designing biocompatible neural circuitries is crucial for their ensuing performance. In these bionic structures, in fact, a correspondence exists between the original anatomical architecture and synthetic wiring of the chip, resulting in a correspondence between natural and cybernetic neural activity. Thus, chip "form" provides a continuum essential to chip "function". We conclude that it is reasonable to predict the existence of hybrid computational processes in the course of many human, brain integrating activities, urging development of cybernetic approaches based on this modelling for adequate reproduction of a variety of cerebral performances.

Application of software technology to a future spacecraft computer design

NASA Technical Reports Server (NTRS)

Labaugh, R. J.

1980-01-01

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

3D integrated superconducting qubits

NASA Astrophysics Data System (ADS)

Rosenberg, D.; Kim, D.; Das, R.; Yost, D.; Gustavsson, S.; Hover, D.; Krantz, P.; Melville, A.; Racz, L.; Samach, G. O.; Weber, S. J.; Yan, F.; Yoder, J. L.; Kerman, A. J.; Oliver, W. D.

2017-10-01

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Digital Waveguide Architectures for Virtual Musical Instruments

NASA Astrophysics Data System (ADS)

Smith, Julius O.

Digital sound synthesis has become a standard staple of modern music studios, videogames, personal computers, and hand-held devices. As processing power has increased over the years, sound synthesis implementations have evolved from dedicated chip sets, to single-chip solutions, and ultimately to software implementations within processors used primarily for other tasks (such as for graphics or general purpose computing). With the cost of implementation dropping closer and closer to zero, there is increasing room for higher quality algorithms.

Fault-Tolerant, Real-Time, Multi-Core Computer System

NASA Technical Reports Server (NTRS)

Gostelow, Kim P.

2012-01-01

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

The origins of informatics.

PubMed Central

Collen, M F

1994-01-01

This article summarizes the origins of informatics, which is based on the science, engineering, and technology of computer hardware, software, and communications. In just four decades, from the 1950s to the 1990s, computer technology has progressed from slow, first-generation vacuum tubes, through the invention of the transistor and its incorporation into microprocessor chips, and ultimately, to fast, fourth-generation very-large-scale-integrated silicon chips. Programming has undergone a parallel transformation, from cumbersome, first-generation, machine languages to efficient, fourth-generation application-oriented languages. Communication has evolved from simple copper wires to complex fiberoptic cables in computer-linked networks. The digital computer has profound implications for the development and practice of clinical medicine. PMID:7719803

DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

PubMed

Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

2017-07-18

Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

Single-Chip Microcomputer Control Of The PWM Inverter

NASA Astrophysics Data System (ADS)

Morimoto, Masayuki; Sato, Shinji; Sumito, Kiyotaka; Oshitani, Katsumi

1987-10-01

A single-chip microcomputer-based con-troller for a pulsewidth modulated 1.7 KVA inverter of an airconditioner is presented. The PWM pattern generation and the system control of the airconditioner are achieved by software of the 8-bit single-chip micro-computer. The single-chip microcomputer has the disadvantages of low processing speed and small memory capacity which can be overcome by the magnetic flux control method. The PWM pattern is generated every 90 psec. The memory capacity of the PWM look-up table is less than 2 kbytes. The simple and reliable control is realized by the software-based implementation.

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip"

NASA Astrophysics Data System (ADS)

Sokolovskiy, A. V.; Dmitriev, D. D.; Veisov, E. A.; Gladyshev, A. B.

2018-05-01

The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.

Research in Computer Simulation of Integrated Circuits.

DTIC Science & Technology

1983-07-31

mactore ftor eval -al-rto implementad am a single chip ae those s Lca we beoi ~~g 7he PT!2 software datatow macl*-re ihas nodes ’cr prr., incrastgly... chip grows, these tools are becoming increasingly importan The FTL2 system described in this paper is an interactive system for specifying concurrent...implemented on a single chip grows, theselools are becom- / r/ - --/ ing increasingly important. The FTL2 system described in this paper is an interactive

Vector computer memory bank contention

NASA Technical Reports Server (NTRS)

Bailey, D. H.

1985-01-01

A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips or else feature very large numbers of independent memory banks.

Vector computer memory bank contention

NASA Technical Reports Server (NTRS)

Bailey, David H.

1987-01-01

A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips or else feature very large numbers of independent memory banks.

Arbitrary photonic wave plate operations on chip: Realizing Hadamard, Pauli-X, and rotation gates for polarisation qubits

PubMed Central

Heilmann, René; Gräfe, Markus; Nolte, Stefan; Szameit, Alexander

2014-01-01

Chip-based photonic quantum computing is an emerging technology that promises much speedup over conventional computers at small integration volumes. Particular interest is thereby given to polarisation-encoded photonic qubits, and many protocols have been developed for this encoding. However, arbitrary wave plate operation on chip are not available so far, preventing from the implementation of integrated universal quantum computing algorithms. In our work we close this gap and present Hadamard, Pauli-X, and rotation gates of high fidelity for photonic polarisation qubits on chip by employing a reorientation of the optical axis of birefringent waveguides. The optical axis of the birefringent waveguide is rotated due to the impact of an artificial stress field created by an additional modification close to the waveguide. By adjusting this length of the defect along the waveguide, the retardation between ordinary and extraordinary field components is precisely tunable including half-wave plate and quarter-wave plate operations. Our approach demonstrates the full range control of orientation and strength of the induced birefringence and thus allows arbitrary wave plate operations without affecting the degree of polarisation or introducing additional losses to the waveguides. The implemented gates are tested with classical and quantum light. PMID:24534893

Characterization of the Serralysin-like gene of 'Ca. Liberibacter solanacearum' associated with Potato Zebra Chip disease

USDA-ARS?s Scientific Manuscript database

The non-culturable bacterium ‘Candidatus Liberibacter solanacearum’ (Lso) is the causative agent of zebra chip disease in potato. Computational analysis of the Lso genome revealed a serralysin-like gene based on conserved domains characteristic of genes encoding metalloprotease enzymes similar to se...

Special-purpose computing for dense stellar systems

NASA Astrophysics Data System (ADS)

Makino, Junichiro

2007-08-01

I'll describe the current status of the GRAPE-DR project. The GRAPE-DR is the next-generation hardware for N-body simulation. Unlike the previous GRAPE hardwares, it is programmable SIMD machine with a large number of simple processors integrated into a single chip. The GRAPE-DR chip consists of 512 simple processors and operates at the clock speed of 500 MHz, delivering the theoretical peak speed of 512/226 Gflops (single/double precision). As of August 2006, the first prototype board with the sample chip successfully passed the test we prepared. The full GRAPE-DR system will consist of 4096 chips, reaching the theoretical peak speed of 2 Pflops.

Optic nerve signals in a neuromorphic chip II: Testing and results.

PubMed

Zaghloul, Kareem A; Boahen, Kwabena

2004-04-01

Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

Around Marshall

NASA Image and Video Library

2004-02-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

An automatic chip structure optical inspection system for electronic components

NASA Astrophysics Data System (ADS)

Song, Zhichao; Xue, Bindang; Liang, Jiyuan; Wang, Ke; Chen, Junzhang; Liu, Yunhe

2018-01-01

An automatic chip structure inspection system based on machine vision is presented to ensure the reliability of electronic components. It consists of four major modules, including a metallographic microscope, a Gigabit Ethernet high-resolution camera, a control system and a high performance computer. An auto-focusing technique is presented to solve the problem that the chip surface is not on the same focusing surface under the high magnification of the microscope. A panoramic high-resolution image stitching algorithm is adopted to deal with the contradiction between resolution and field of view, caused by different sizes of electronic components. In addition, we establish a database to storage and callback appropriate parameters to ensure the consistency of chip images of electronic components with the same model. We use image change detection technology to realize the detection of chip images of electronic components. The system can achieve high-resolution imaging for chips of electronic components with various sizes, and clearly imaging for the surface of chip with different horizontal and standardized imaging for ones with the same model, and can recognize chip defects.

Andy Jenkins Builds Applications Development For Lab-on-a-Chip

NASA Technical Reports Server (NTRS)

2004-01-01

Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Computer Algorithms and Architectures for Three-Dimensional Eddy-Current Nondestructive Evaluation. Volume 3. Chapters 6-11

DTIC Science & Technology

1989-01-20

addressable memory can be loaded or off- loaded as the number crunching continues. Modem VLSI processors can often process data faster than today’s...Available DSP Chips Texas Instruments was one of the first serious manufacturers of DSP chips. With the Texas Instruments TMS310 DSP chip, modem , voice...Can handle double presicion data types. Texas Instruments TMS32010 T’s first-generation DSP design: a fixed-point DSP that has found its way into modem

Computer-assisted design/computer-assisted manufacturing zirconia implant fixed complete prostheses: clinical results and technical complications up to 4 years of function.

PubMed

Papaspyridakos, Panos; Lal, Kunal

2013-06-01

To report the clinical results and technical complications with computer-assisted design/computer-assisted manufacturing (CAD/CAM) zirconia, implant fixed complete dental prostheses (IFCDPs) after 2-4 years in function. Fourteen consecutive edentulous patients (16 edentulous arches) were included in this study. Ten of the patients were women and four were men, with an average age of 58 years (range: 35-71). Ten mandibular and six maxillary arches were restored with porcelain fused to zirconia (PFZ) IFCDPs. Of the 16 arches, 14 received one-piece and 2 received segmented two-piece IFCDPs, respectively. The mean clinical follow-up period was 3 years (range: 2-4). At the last recall appointment, biological and technical parameters of dental implant treatment were evaluated. The implant and prosthesis survival rate following prosthesis insertion was 100% up to 4-year follow-up. The prostheses in 11 of the 16 restored arches were structurally sound, exhibited favorable soft tissue response, esthetics, and patient satisfaction. Five IFCDPs (31.25%) in four patients exhibited porcelain veneer chipping. Chipping was minor in three prostheses (three patients) and was addressed intraorally with polishing (one prosthesis) or composite resin (two prostheses). One patient with maxillary and mandibular zirconia IFCDP exhibited major porcelain chipping fractures which had to be repaired in the laboratory. Function, esthetics, and patient satisfaction were not affected in three of the four fracture incidents. Median crestal bone loss was 0.1 mm (0.01-0.2 mm). The presence of parafunctional activity, the IFCDP as opposing dentition, and the absence of occlusal night guard were associated with all the incidents of ceramic chipping. CAD/CAM zirconia IFCDPs are viable prosthetic treatment after 2-4 years in function, but not without complications. The porcelain chipping/fracture was the most frequent technical complication, with a 31.25% chipping rate at the prosthesis level. Despite the technical complications, increased patient satisfaction was noted. © 2012 John Wiley & Sons A/S.

Shor's quantum factoring algorithm on a photonic chip.

PubMed

Politi, Alberto; Matthews, Jonathan C F; O'Brien, Jeremy L

2009-09-04

Shor's quantum factoring algorithm finds the prime factors of a large number exponentially faster than any other known method, a task that lies at the heart of modern information security, particularly on the Internet. This algorithm requires a quantum computer, a device that harnesses the massive parallelism afforded by quantum superposition and entanglement of quantum bits (or qubits). We report the demonstration of a compiled version of Shor's algorithm on an integrated waveguide silica-on-silicon chip that guides four single-photon qubits through the computation to factor 15.

Optical computing research

NASA Astrophysics Data System (ADS)

Goodman, Joseph W.

1987-10-01

Work Accomplished: OPTICAL INTERCONNECTIONS - the powerful interconnect abilities of optical beams have led much optimism about the possible roles for optics in solving interconnect problems at various levels of computer architecture. Examined were the powerful requirements of optical interconnects at the gate-to-gate and chip-to-chip levels. OPTICAL NEUTRAL NETWORKS - basic studies of the convergence properties on the Holfield model, based on mathematical approach - graph theory. OPTICS AND ARTIFICIAL INTELLIGENCE - review the field of optical processing and artificial intelligence, with the aim of finding areas that might be particularly attractive for future investigation(s).

Polymorphous Computing Architecture (PCA) Kernel Benchmark Measurements on the MIT Raw Microprocessor

DTIC Science & Technology

2006-06-14

Robert Graybill . A Raw hoard for the use of this project was provided by the Computer Architecture Croup at the Massachusetts Institute of Technology...simulator is presented by MIT as being an accurate model of the Raw chip, we have found that it does not accurately model the board. Our comparison...G4 processor, model 7410. with a 32 kbyte level-1 cache on-chip and a 2 Mbyte L2 cache connected through a 250 MH/ bus [12]. Each node has 256 Mbyte

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

PubMed Central

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-01

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

PubMed

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

A micro-computer based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, R.

1984-01-01

A mathematical model of magnetic variation in the continental United States (COT48) was implemented in the Ohio University LORAN C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based LORAN C receiver is possible with the help of a math chip, Am9511 which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter (M6520) is used to communicate between the 6502 based micro-computer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

A simulation-based approach for evaluating logging residue handling systems.

Treesearch

B. Bruce Bare; Benjamin A. Jayne; Brian F. Anholt

1976-01-01

Describes a computer simulation model for evaluating logging residue handling systems. The flow of resources is traced through a prespecified combination of operations including yarding, chipping, sorting, loading, transporting, and unloading. The model was used to evaluate the feasibility of converting logging residues to chips that could be used, for example, to...

Clocking and Synchronization Circuits in Multiprocessor Systems

DTIC Science & Technology

1989-04-01

18 3.4 Inter -chip Clocking Strategies...may occur when two or more of the switches make transitions at different times during the inter - val during which those inputs are being processed...increased without any fruitful computation. The sources of the inter -chip clock skew are the electromagnetic propagation delay, the buffer delay within

A computer simulation of full-tree field chipping and trucking.

Treesearch

Dennis P. Bradley; Frank E. Biltonen; Sharon A. Winsauer

1976-01-01

Describes a computerized model of a full-tree field chipping system from stump to mill using the GPSS simulation language. The program instructions reproduce the interactions, production, and costs for the various operations under given stand and operating conditions so a user can find the best way to operate his system.

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

Comparison of Classifier Architectures for Online Neural Spike Sorting.

PubMed

Saeed, Maryam; Khan, Amir Ali; Kamboh, Awais Mehmood

2017-04-01

High-density, intracranial recordings from micro-electrode arrays need to undergo Spike Sorting in order to associate the recorded neuronal spikes to particular neurons. This involves spike detection, feature extraction, and classification. To reduce the data transmission and power requirements, on-chip real-time processing is becoming very popular. However, high computational resources are required for classifiers in on-chip spike-sorters, making scalability a great challenge. In this review paper, we analyze several popular classifiers to propose five new hardware architectures using the off-chip training with on-chip classification approach. These include support vector classification, fuzzy C-means classification, self-organizing maps classification, moving-centroid K-means classification, and Cosine distance classification. The performance of these architectures is analyzed in terms of accuracy and resource requirement. We establish that the neural networks based Self-Organizing Maps classifier offers the most viable solution. A spike sorter based on the Self-Organizing Maps classifier, requires only 7.83% of computational resources of the best-reported spike sorter, hierarchical adaptive means, while offering a 3% better accuracy at 7 dB SNR.

Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

NASA Astrophysics Data System (ADS)

Shatford, R.; Karanassios, Vassili

2014-05-01

Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

On-chip optical diode based on silicon photonic crystal heterojunctions.

PubMed

Wang, Chen; Zhou, Chang-Zhu; Li, Zhi-Yuan

2011-12-19

Optical isolation is a long pursued object with fundamental difficulty in integrated photonics. As a step towards this goal, we demonstrate the design, fabrication, and characterization of on-chip wavelength-scale optical diodes that are made from the heterojunction between two different silicon two-dimensional square-lattice photonic crystal slabs with directional bandgap mismatch and different mode transitions. The measured transmission spectra show considerable unidirectional transmission behavior, in good agreement with numerical simulations. The experimental realization of on-chip optical diodes with wavelength-scale size using all-dielectric, passive, and linear silicon photonic crystal structures may help to construct on-chip optical logical devices without nonlinearity or magnetism, and would open up a road towards photonic computers.

Molecular Sticker Model Stimulation on Silicon for a Maximum Clique Problem

PubMed Central

Ning, Jianguo; Li, Yanmei; Yu, Wen

2015-01-01

Molecular computers (also called DNA computers), as an alternative to traditional electronic computers, are smaller in size but more energy efficient, and have massive parallel processing capacity. However, DNA computers may not outperform electronic computers owing to their higher error rates and some limitations of the biological laboratory. The stickers model, as a typical DNA-based computer, is computationally complete and universal, and can be viewed as a bit-vertically operating machine. This makes it attractive for silicon implementation. Inspired by the information processing method on the stickers computer, we propose a novel parallel computing model called DEM (DNA Electronic Computing Model) on System-on-a-Programmable-Chip (SOPC) architecture. Except for the significant difference in the computing medium—transistor chips rather than bio-molecules—the DEM works similarly to DNA computers in immense parallel information processing. Additionally, a plasma display panel (PDP) is used to show the change of solutions, and helps us directly see the distribution of assignments. The feasibility of the DEM is tested by applying it to compute a maximum clique problem (MCP) with eight vertices. Owing to the limited computing sources on SOPC architecture, the DEM could solve moderate-size problems in polynomial time. PMID:26075867

Apocalypse Soon? The Bug.

ERIC Educational Resources Information Center

Clyde, Anne

1999-01-01

Discussion of the Year 2000 (Y2K) problem, the computer-code problem that affects computer programs or computer chips, focuses on the impact on teacher-librarians. Topics include automated library systems, access to online information services, library computers and software, and other electronic equipment such as photocopiers and fax machines.…

Toward giga-pixel nanoscopy on a chip: a computational wide-field look at the nano-scale without the use of lenses

PubMed Central

McLeod, Euan; Luo, Wei; Mudanyali, Onur; Greenbaum, Alon

2013-01-01

The development of lensfree on-chip microscopy in the past decade has opened up various new possibilities for biomedical imaging across ultra-large fields of view using compact, portable, and cost-effective devices. However, until recently, its ability to resolve fine features and detect ultra-small particles has not rivalled the capabilities of the more expensive and bulky laboratory-grade optical microscopes. In this Frontier Review, we highlight the developments over the last two years that have enabled computational lensfree holographic on-chip microscopy to compete with and, in some cases, surpass conventional bright-field microscopy in its ability to image nano-scale objects across large fields of view, yielding giga-pixel phase and amplitude images. Lensfree microscopy has now achieved a numerical aperture as high as 0.92, with a spatial resolution as small as 225 nm across a large field of view e.g., >20 mm2. Furthermore, the combination of lensfree microscopy with self-assembled nanolenses, forming nano-catenoid minimal surfaces around individual nanoparticles has boosted the image contrast to levels high enough to permit bright-field imaging of individual particles smaller than 100 nm. These capabilities support a number of new applications, including, for example, the detection and sizing of individual virus particles using field-portable computational on-chip microscopes. PMID:23592185

Toward giga-pixel nanoscopy on a chip: a computational wide-field look at the nano-scale without the use of lenses.

PubMed

McLeod, Euan; Luo, Wei; Mudanyali, Onur; Greenbaum, Alon; Ozcan, Aydogan

2013-06-07

The development of lensfree on-chip microscopy in the past decade has opened up various new possibilities for biomedical imaging across ultra-large fields of view using compact, portable, and cost-effective devices. However, until recently, its ability to resolve fine features and detect ultra-small particles has not rivalled the capabilities of the more expensive and bulky laboratory-grade optical microscopes. In this Frontier Review, we highlight the developments over the last two years that have enabled computational lensfree holographic on-chip microscopy to compete with and, in some cases, surpass conventional bright-field microscopy in its ability to image nano-scale objects across large fields of view, yielding giga-pixel phase and amplitude images. Lensfree microscopy has now achieved a numerical aperture as high as 0.92, with a spatial resolution as small as 225 nm across a large field of view e.g., >20 mm(2). Furthermore, the combination of lensfree microscopy with self-assembled nanolenses, forming nano-catenoid minimal surfaces around individual nanoparticles has boosted the image contrast to levels high enough to permit bright-field imaging of individual particles smaller than 100 nm. These capabilities support a number of new applications, including, for example, the detection and sizing of individual virus particles using field-portable computational on-chip microscopes.

The correlation of methylation levels measured using Illumina 450K and EPIC BeadChips in blood samples

PubMed Central

Logue, Mark W; Smith, Alicia K; Wolf, Erika J; Maniates, Hannah; Stone, Annjanette; Schichman, Steven A; McGlinchey, Regina E; Milberg, William; Miller, Mark W

2017-01-01

Aim: We examined concordance of methylation levels across the Illumina Infinium HumanMethylation450 BeadChip and the Infinium MethylationEPIC BeadChip. Methods: We computed the correlation for 145 whole blood DNA samples at each of the 422,524 CpG sites measured by both chips. Results: The correlation at some sites was high (up to r = 0.95), but many sites had low correlation (55% had r < 0.20). The low correspondence between 450K and EPIC measured methylation values at many loci was largely due to the low variability in methylation values for the majority of the CpG sites in blood. Conclusion: Filtering out probes based on the observed correlation or low variability may increase reproducibility of BeadChip-based epidemiological studies. PMID:28809127

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Progress in ion torrent semiconductor chip based sequencing.

PubMed

Merriman, Barry; Rothberg, Jonathan M

2012-12-01

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An analog silicon retina with multichip configuration.

PubMed

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

Neuromorphic VLSI vision system for real-time texture segregation.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

6. VIEW OF THE BRIQUETTING PRESS AND CHIP CLEANING HOOD. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

6. VIEW OF THE BRIQUETTING PRESS AND CHIP CLEANING HOOD. SCRAPS OF ENRICHED URANIUM FROM MACHINING OPERATIONS WERE CLEANED IN A SOLVENT BATH, THEN PRESSED INTO BRIQUETTS. THE BRIQUETTS WERE USED AS FEED MATERIAL FOR THE FOUNDRY. (4/4/66) - Rocky Flats Plant, General Manufacturing, Support, Records-Central Computing, Southern portion of Plant, Golden, Jefferson County, CO

[The development of an intelligent four-channel aggregometer].

PubMed

Guan, X; Wang, M

1998-07-01

The paper introduces the hardware and software design of the instrument. We use 89C52 single-chip computer as the microprocessor to control the amplifier, AD and DA conversion chip to realize the sampling, data process, printout and supervision. The final result is printed out in form of data and aggregation curve from PP40 plotter.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Farbrication of diffractive optical elements on a Si chip by an imprint lithography using nonsymmetrical silicon mold

NASA Astrophysics Data System (ADS)

Hirai, Yoshihiko; Okano, Masato; Okuno, Takayuki; Toyota, Hiroshi; Yotsuya, Tsutomu; Kikuta, Hisao; Tanaka, Yoshio

2001-11-01

Fabrication of a fine diffractive optical element on a Si chip is demonstrated using imprint lithography. A chirped diffraction grating, which has modulated pitched pattern with curved cross section is fabricated by an electron beam lithography, where the exposure dose profile is automatically optimized by computer aided system. Using the resist pattern as an etching mask, anisotropic dry etching is performed to transfer the resist pattern profile to the Si chip. The etched Si substrate is used as a mold in the imprint lithography. The Si mold is pressed to a thin polymer (poly methyl methacrylate) on a Si chip. After releasing the mold, a fine diffractive optical pattern is successfully transferred to the thin polymer. This method is exceedingly useful for fabrication of integrated diffractive optical elements with electric circuits on a Si chip.

MIL-STD-1553B Marconi LSI chip set in a remote terminal application

NASA Astrophysics Data System (ADS)

Dimarino, A.

1982-11-01

Marconi Avionics is utilizing the MIL-STD-1553B LSI Chip Set in the SCADC Air Data Computer application to perform all of the required remote terminal MIL-STD-1553B protocol functions. Basic components of the RTU are the dual redundant chip set, CT3231 Transceivers, 256 x 16 RAM and a Z8002 microprocessor. Basic transfers are to/from the RAM command of the bus controller or Z8002 processor. During transfers from the processor to the RAM, the chip set busy bit is set for a period not exceeding 250 microseconds. When the transfer is complete, the busy bit is released and transfers to the data bus occur on command. The LSI Chip Set word count lines are used to locate each data word in the local memory and 4 mode codes are used in the application: reset remote terminal, transmit status word, transmitter shut-down, and override transmitter shutdown.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

Unraveling Quantum Annealers using Classical Hardness

PubMed Central

Martin-Mayor, Victor; Hen, Itay

2015-01-01

Recent advances in quantum technology have led to the development and manufacturing of experimental programmable quantum annealing optimizers that contain hundreds of quantum bits. These optimizers, commonly referred to as ‘D-Wave’ chips, promise to solve practical optimization problems potentially faster than conventional ‘classical’ computers. Attempts to quantify the quantum nature of these chips have been met with both excitement and skepticism but have also brought up numerous fundamental questions pertaining to the distinguishability of experimental quantum annealers from their classical thermal counterparts. Inspired by recent results in spin-glass theory that recognize ‘temperature chaos’ as the underlying mechanism responsible for the computational intractability of hard optimization problems, we devise a general method to quantify the performance of quantum annealers on optimization problems suffering from varying degrees of temperature chaos: A superior performance of quantum annealers over classical algorithms on these may allude to the role that quantum effects play in providing speedup. We utilize our method to experimentally study the D-Wave Two chip on different temperature-chaotic problems and find, surprisingly, that its performance scales unfavorably as compared to several analogous classical algorithms. We detect, quantify and discuss several purely classical effects that possibly mask the quantum behavior of the chip. PMID:26483257

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

Missileborne Artificial Vision System (MAVIS)

NASA Technical Reports Server (NTRS)

Andes, David K.; Witham, James C.; Miles, Michael D.

1994-01-01

Several years ago when INTEL and China Lake designed the ETANN chip, analog VLSI appeared to be the only way to do high density neural computing. In the last five years, however, digital parallel processing chips capable of performing neural computation functions have evolved to the point of rough equality with analog chips in system level computational density. The Naval Air Warfare Center, China Lake, has developed a real time, hardware and software system designed to implement and evaluate biologically inspired retinal and cortical models. The hardware is based on the Adaptive Solutions Inc. massively parallel CNAPS system COHO boards. Each COHO board is a standard size 6U VME card featuring 256 fixed point, RISC processors running at 20 MHz in a SIMD configuration. Each COHO board has a companion board built to support a real time VSB interface to an imaging seeker, a NTSC camera, and to other COHO boards. The system is designed to have multiple SIMD machines each performing different corticomorphic functions. The system level software has been developed which allows a high level description of corticomorphic structures to be translated into the native microcode of the CNAPS chips. Corticomorphic structures are those neural structures with a form similar to that of the retina, the lateral geniculate nucleus, or the visual cortex. This real time hardware system is designed to be shrunk into a volume compatible with air launched tactical missiles. Initial versions of the software and hardware have been completed and are in the early stages of integration with a missile seeker.

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

PubMed

Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

2011-11-01

Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

Photosensitive biosensor array system using optical addressing without an addressing circuit on array biochips

NASA Astrophysics Data System (ADS)

Ahn, Chang-Geun; Ah, Chil Seong; Kim, Tae-Youb; Park, Chan Woo; Yang, Jong-Heon; Kim, Ansoon; Sung, Gun Yong

2010-09-01

This paper introduces a photosensitive biosensor array system with a simple photodiode array that detects photocurrent changes caused by reactions between probe and target molecules. Using optical addressing, the addressing circuit on the array chip is removed for low-cost application, and real cell addressing is achieved using an externally located computer-controllable light-emitting diode array module. The fabricated biosensor array chip shows a good dynamic range of 1-100 ng/mL under prostate-specific antigen detection, with an on-chip resolution of roughly 1 ng/mL.

Very Large Scale Integration (VLSI).

ERIC Educational Resources Information Center

Yeaman, Andrew R. J.

Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

Toying with Education.

ERIC Educational Resources Information Center

Zonderman, Jon

1982-01-01

The proliferation of personal computers in home/schools and use of computer chips in educational toys has led to a rethinking of ideas about education and fun, and ways the two can combine to provide youngsters with enjoyable and profitable learning experiences. Provides examples of commercially available computer-oriented educational toys/games.…

Is Your School Y2K-OK?

ERIC Educational Resources Information Center

Bates, Martine G.

1999-01-01

The most vulnerable Y2K areas for schools are networked computers, free-standing personal computers, software, and embedded chips in utilities such as telephones and fire alarms. Expensive, time-consuming procedures and software have been developed for testing and bringing most computers into compliance. Districts need a triage prioritization…

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Compact Method for Modeling and Simulation of Memristor Devices

DTIC Science & Technology

2011-08-01

single-valued equations. 15. SUBJECT TERMS Memristor, Neuromorphic , Cognitive, Computing, Memory, Emerging Technology, Computational Intelligence 16...resistance state depends on its previous state and present electrical biasing conditions, and when combined with transistors in a hybrid chip ...computers, reconfigurable electronics and neuromorphic computing [3,4]. According to Chua [4], the memristor behaves like a linear resistor with

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

PubMed

Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

2015-02-23

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

A micro-computer-based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, Rajan

1987-01-01

A mathematical model of magnetic variation in the continental United States was implemented in the Ohio University Loran-C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based Loran-C receiver is possible with the help of a math chip which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter is used to communicate between the 6502 based microcomputer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

Scaling vectors of attoJoule per bit modulators

NASA Astrophysics Data System (ADS)

Sorger, Volker J.; Amin, Rubab; Khurgin, Jacob B.; Ma, Zhizhen; Dalir, Hamed; Khan, Sikandar

2018-01-01

Electro-optic modulation performs the conversion between the electrical and optical domain with applications in data communication for optical interconnects, but also for novel optical computing algorithms such as providing nonlinearity at the output stage of optical perceptrons in neuromorphic analog optical computing. While resembling an optical transistor, the weak light-matter-interaction makes modulators 105 times larger compared to their electronic counterparts. Since the clock frequency for photonics on-chip has a power-overhead sweet-spot around tens of GHz, ultrafast modulation may only be required in long-distance communication, not for short on-chip links. Hence, the search is open for power-efficient on-chip modulators beyond the solutions offered by foundries to date. Here, we show scaling vectors towards atto-Joule per bit efficient modulators on-chip as well as some experimental demonstrations of novel plasmonic modulators with sub-fJ/bit efficiencies. Our parametric study of placing different actively modulated materials into plasmonic versus photonic optical modes shows that 2D materials overcompensate their miniscule modal overlap by their unity-high index change. Furthermore, we reveal that the metal used in plasmonic-based modulators not only serves as an electrical contact, but also enables low electrical series resistances leading to near-ideal capacitors. We then discuss the first experimental demonstration of a photon-plasmon-hybrid graphene-based electro-absorption modulator on silicon. The device shows a sub-1 V steep switching enabled by near-ideal electrostatics delivering a high 0.05 dB V-1 μm-1 performance requiring only 110 aJ/bit. Improving on this demonstration, we discuss a plasmonic slot-based graphene modulator design, where the polarization of the plasmonic mode aligns with graphene’s in-plane dimension; where a push-pull dual-gating scheme enables 2 dB V-1 μm-1 efficient modulation allowing the device to be just 770 nm short for 3 dB small signal modulation. Lastly, comparing the switching energy of transistors to modulators shows that modulators based on emerging materials and plasmonic-silicon hybrid integration perform on-par relative to their electronic counter parts. This in turn allows for a device-enabled two orders-of-magnitude improvement of electrical-optical co-integrated network-on-chips over electronic-only architectures. The latter opens technological opportunities in cognitive computing, dynamic data-driven applications systems, and optical analog computer engines including neuromorphic photonic computing.

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Three-unit posterior zirconia-ceramic fixed dental prostheses (FDPs) veneered with layered and milled (CAD-on) veneering ceramics: 1-year follow-up of a randomized controlled clinical trial.

PubMed

Grohmann, Philipp; Bindl, Andreas; Hämmerle, Christoph; Mehl, Albert; Sailer, Irena

2015-01-01

The aim of this multicenter randomized controlled clinical trial was to test posterior zirconia-ceramic fixed dental prostheses (FDPs) veneered with a computer-aided design/computer- assisted manufacture (CAD/CAM) lithium disilicate veneering ceramic (CAD-on) and manually layered zirconia veneering ceramic with respect to survival of the FDPs, and technical and biologic outcomes. Sixty patients in need of one posterior three-unit FDP were included. The zirconia frameworks were produced with a CAD/CAM system (Cerec inLab 3D/Cerec inEOS inLab). Thirty FDPs were veneered with a CAD/CAM lithium disilicate veneering ceramic (Cad-on) (test) and 30 were veneered with a layered zirconia veneering ceramic (control). For the clinical evaluation at baseline, 6, and 12 months, the United States Public Health Service (USPHS) criteria were used. The biologic outcome was judged by comparing the plaque control record (PCR), bleeding on probing (BOP), and probing pocket depth (PPD). Data were statistically analyzed. Fifty-six patients were examined at a mean follow-up of 13.9 months. At the 1-year follow-up the survival rate was 100% in the test and in the control group. No significant differences of the technical outcomes occurred. Major chipping occurred in the control group (n = 3) and predominantly minor chipping in the test group (minor n = 2, major n = 1). No biologic problems or differences were found. Both types of zirconia-ceramic FDPs exhibited very good clinical outcomes without differences between groups. Chipping occurred in both types of FDPs at small amounts, yet the extension of the chippings differed. The test FDPs predominantly exhibited minor chipping, the control FDPs major chipping.

Address-event-based platform for bioinspired spiking systems

NASA Astrophysics Data System (ADS)

Jiménez-Fernández, A.; Luján, C. D.; Linares-Barranco, A.; Gómez-Rodríguez, F.; Rivas, M.; Jiménez, G.; Civit, A.

2007-05-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate "events" according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal computer implies to depend on software tools and operating systems that can make the system slower and un-robust. This paper addresses the problem of communicating several AER based chips to compose a powerful processing system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone (independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3 4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps).

An 81.6 μW FastICA processor for epileptic seizure detection.

PubMed

Yang, Chia-Hsiang; Shih, Yi-Hsin; Chiueh, Herming

2015-02-01

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 μW at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 × computation speedup are achieved. The performance of the chip was verified by human dataset.

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

Quantum Devices Bonded Beneath a Superconducting Shield: Part 2

NASA Astrophysics Data System (ADS)

McRae, Corey Rae; Abdallah, Adel; Bejanin, Jeremy; Earnest, Carolyn; McConkey, Thomas; Pagel, Zachary; Mariantoni, Matteo

The next-generation quantum computer will rely on physical quantum bits (qubits) organized into arrays to form error-robust logical qubits. In the superconducting quantum circuit implementation, this architecture will require the use of larger and larger chip sizes. In order for on-chip superconducting quantum computers to be scalable, various issues found in large chips must be addressed, including the suppression of box modes (due to the sample holder) and the suppression of slot modes (due to fractured ground planes). By bonding a metallized shield layer over a superconducting circuit using thin-film indium as a bonding agent, we have demonstrated proof of concept of an extensible circuit architecture that holds the key to the suppression of spurious modes. Microwave characterization of shielded transmission lines and measurement of superconducting resonators were compared to identical unshielded devices. The elimination of box modes was investigated, as well as bond characteristics including bond homogeneity and the presence of a superconducting connection.

Computation of dark frames in digital imagers

NASA Astrophysics Data System (ADS)

Widenhorn, Ralf; Rest, Armin; Blouke, Morley M.; Berry, Richard L.; Bodegom, Erik

2007-02-01

Dark current is caused by electrons that are thermally exited into the conduction band. These electrons are collected by the well of the CCD and add a false signal to the chip. We will present an algorithm that automatically corrects for dark current. It uses a calibration protocol to characterize the image sensor for different temperatures. For a given exposure time, the dark current of every pixel is characteristic of a specific temperature. The dark current of every pixel can therefore be used as an indicator of the temperature. Hot pixels have the highest signal-to-noise ratio and are the best temperature sensors. We use the dark current of a several hundred hot pixels to sense the chip temperature and predict the dark current of all pixels on the chip. Dark current computation is not a new concept, but our approach is unique. Some advantages of our method include applicability for poorly temperature-controlled camera systems and the possibility of ex post facto dark current correction.

Optimized static and video EEG rapid serial visual presentation (RSVP) paradigm based on motion surprise computation

NASA Astrophysics Data System (ADS)

Khosla, Deepak; Huber, David J.; Bhattacharyya, Rajan

2017-05-01

In this paper, we describe an algorithm and system for optimizing search and detection performance for "items of interest" (IOI) in large-sized images and videos that employ the Rapid Serial Visual Presentation (RSVP) based EEG paradigm and surprise algorithms that incorporate motion processing to determine whether static or video RSVP is used. The system works by first computing a motion surprise map on image sub-regions (chips) of incoming sensor video data and then uses those surprise maps to label the chips as either "static" or "moving". This information tells the system whether to use a static or video RSVP presentation and decoding algorithm in order to optimize EEG based detection of IOI in each chip. Using this method, we are able to demonstrate classification of a series of image regions from video with an azimuth value of 1, indicating perfect classification, over a range of display frequencies and video speeds.

Gene chips and arrays revealed: a primer on their power and their uses.

PubMed

Watson, S J; Akil, H

1999-03-01

This article provides an overview and general explanation of the rapidly developing area of gene chips and expression array technology. These are methods targeted at allowing the simultaneous study of thousands of genes or messenger RNAs under various physiological and pathological states. Their technical basis grows from the Human Genome Project. Both methods place DNA strands on glass computer chips (or microscope slides). Expression arrays start with complementary DNA (cDNA) clones derived from the EST data base, whereas Gene Chips synthesize oligonucleotides directly on the chip itself. Both are analyzed using image analysis systems, are capable of reading values from two different individuals at any one site, and can yield quantitative data for thousands of genes or mRNAs per slide. These methods promise to revolutionize molecular biology, cell biology, neuroscience and psychiatry. It is likely that this technology will radically open up our ability to study the actions and structure of the multiple genes involved in the complex genetics of brain disorders.

Cross correlation anomaly detection system

NASA Technical Reports Server (NTRS)

Micka, E. Z. (Inventor)

1975-01-01

This invention provides a method for automatically inspecting the surface of an object, such as an integrated circuit chip, whereby the data obtained by the light reflected from the surface, caused by a scanning light beam, is automatically compared with data representing acceptable values for each unique surface. A signal output provided indicated of acceptance or rejection of the chip. Acceptance is based on predetermined statistical confidence intervals calculated from known good regions of the object being tested, or their representative values. The method can utilize a known good chip, a photographic mask from which the I.C. was fabricated, or a computer stored replica of each pattern being tested.

Associative Pattern Recognition In Analog VLSI Circuits

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1995-01-01

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

Childhood Hodgkin International Prognostic Score (CHIPS) Predicts event-free survival in Hodgkin Lymphoma: A Report from the Children’s Oncology Group

PubMed Central

Schwartz, Cindy L.; Chen, Lu; McCarten, Kathleen; Wolden, Suzanne; Constine, Louis S.; Hutchison, Robert E.; de Alarcon, Pedro A.; Keller, Frank G.; Kelly, Kara M.; Trippet, Tanya A.; Voss, Stephan D.; Friedman, Debra L.

2017-01-01

Background Early response to initial chemotherapy in Hodgkin lymphoma (HL) measured by computed tomography (CT) and/or positron emission tomography (PET) after two to three cycles of chemotherapy may inform therapeutic decisions. Risk stratification at diagnosis could, however, allow earlier and potentially more efficacious treatment modifications. Patients and Methods We developed a predictive model for event-free survival (EFS) in pediatric/adolescent HL using clinical data known at diagnosis from 1103 intermediate-risk HL patients treated on Children’s Oncology Group protocol AHOD0031 with doxorubicin, bleomycin, vincristine, etoposide, prednisone, cyclophosphamide (ABVE-PC) chemotherapy and radiation. Independent predictors of EFS were identified and used to develop and validate a prognostic score (Childhood Hodgkin International Prognostic Score [CHIPS]). A training cohort was randomly selected to include approximately half of the overall cohort, with the remainder forming the validation cohort. Results Stage 4 disease, large mediastinal mass, albumin (<3.5), and fever were independent predictors of EFS that were each assigned one point in the CHIPS. Four-year EFS was 93.1% for patients with CHIPS = 0, 88.5% for patients with CHIPS = 1, 77.6% for patients with CHIPS = 2, and 69.2% for patients with CHIPS = 3. Conclusions CHIPS was highly predictive of EFS, identifying a subset (with CHIPS 2 or 3) that comprises 27% of intermediate-risk patients who have a 4-year EFS of <80% and who may benefit from early therapeutic augmentation. Furthermore, CHIPS identified higher risk patients who were not identified by early PET or CT response. CHIPS is a robust and inexpensive approach to predicting risk in patients with intermediate-risk HL that may improve ability to tailor therapy to risk factors known at diagnosis. PMID:27786406

Childhood Hodgkin International Prognostic Score (CHIPS) Predicts event-free survival in Hodgkin Lymphoma: A Report from the Children's Oncology Group.

PubMed

Schwartz, Cindy L; Chen, Lu; McCarten, Kathleen; Wolden, Suzanne; Constine, Louis S; Hutchison, Robert E; de Alarcon, Pedro A; Keller, Frank G; Kelly, Kara M; Trippet, Tanya A; Voss, Stephan D; Friedman, Debra L

2017-04-01

Early response to initial chemotherapy in Hodgkin lymphoma (HL) measured by computed tomography (CT) and/or positron emission tomography (PET) after two to three cycles of chemotherapy may inform therapeutic decisions. Risk stratification at diagnosis could, however, allow earlier and potentially more efficacious treatment modifications. We developed a predictive model for event-free survival (EFS) in pediatric/adolescent HL using clinical data known at diagnosis from 1103 intermediate-risk HL patients treated on Children's Oncology Group protocol AHOD0031 with doxorubicin, bleomycin, vincristine, etoposide, prednisone, cyclophosphamide (ABVE-PC) chemotherapy and radiation. Independent predictors of EFS were identified and used to develop and validate a prognostic score (Childhood Hodgkin International Prognostic Score [CHIPS]). A training cohort was randomly selected to include approximately half of the overall cohort, with the remainder forming the validation cohort. Stage 4 disease, large mediastinal mass, albumin (<3.5), and fever were independent predictors of EFS that were each assigned one point in the CHIPS.  Four-year EFS was 93.1% for patients with CHIPS = 0, 88.5% for patients with CHIPS = 1, 77.6% for patients with CHIPS = 2, and 69.2% for patients with CHIPS = 3. CHIPS was highly predictive of EFS, identifying a subset (with CHIPS 2 or 3) that comprises 27% of intermediate-risk patients who have a 4-year EFS of <80% and who may benefit from early therapeutic augmentation.  Furthermore, CHIPS identified higher risk patients who were not identified by early PET or CT response. CHIPS is a robust and inexpensive approach to predicting risk in patients with intermediate-risk HL that may improve ability to tailor therapy to risk factors known at diagnosis. © 2016 Wiley Periodicals, Inc.

High-Performance Computing Act of 1991. Report of the Senate Committee on Commerce, Science, and Transportation on S. 272. Senate, 102d Congress, 1st Session.

ERIC Educational Resources Information Center

Congress of the U.S., Washington, DC. Senate Committee on Commerce, Science, and Transportation.

This report discusses Senate Bill no. 272, which provides for a coordinated federal research and development program to ensure continued U.S. leadership in high-performance computing. High performance computing is defined as representing the leading edge of technological advancement in computing, i.e., the most sophisticated computer chips, the…

Chip-based microtrap arrays for cold polar molecules

NASA Astrophysics Data System (ADS)

Hou, Shunyong; Wei, Bin; Deng, Lianzhong; Yin, Jianping

2017-12-01

Compared to the atomic chip, which has been a powerful platform to perform an astonishing range of applications from rapid Bose-Einstein condensate (BEC) production to the atomic clock, the molecular chip is only in its infant stages. Recently a one-dimensional electric lattice was demonstrated to trap polar molecules on a chip. This excellent work opens up the way to building a molecular chip laboratory. Here we propose a two-dimensional (2D) electric lattice on a chip with concise and robust structure, which is formed by arrays of squared gold wires. Arrays of microtraps that originate in the microsize electrodes offer a steep gradient and thus allow for confining both light and heavy polar molecules. Theoretical analysis and numerical calculations are performed using two types of sample molecules, N D3 and SrF, to justify the possibility of our proposal. The height of the minima of the potential wells is about 10 μm above the surface of the chip and can be easily adjusted in a wide range by changing the voltages applied on the electrodes. These microtraps offer intriguing perspectives for investigating cold molecules in periodic potentials, such as quantum computing science, low-dimensional physics, and some other possible applications amenable to magnetic or optical lattice. The 2D adjustable electric lattice is expected to act as a building block for a future gas-phase molecular chip laboratory.

Design of three-phased SPWM based on AT89C52

NASA Astrophysics Data System (ADS)

Wu, Xiaorui

2018-05-01

According to the AT89C52 and the area equivalent principle, a three phase SPWM algorithm based on the 8 bit single chip is obtained. Through computer programming, three-phase SPWM wave generated by a single chip microcomputer is applied to the circuit of the static reactive power generator. The result shows that this method is feasible and can reduce the cost of SVG.

Computing Optic Flow with ArduEye Vision Sensor

DTIC Science & Technology

2013-01-01

processing algorithm that can be applied to the flight control of other robotic platforms. 15. SUBJECT TERMS Optical flow, ArduEye, vision based ...2 Figure 2. ArduEye vision chip on Stonyman breakout board connected to Arduino Mega (8) (left) and the Stonyman vision chips (7...robotic platforms. There is a significant need for small, light , less power-hungry sensors and sensory data processing algorithms in order to control the

Design of wideband solar ultraviolet radiation intensity monitoring and control system

NASA Astrophysics Data System (ADS)

Ye, Linmao; Wu, Zhigang; Li, Yusheng; Yu, Guohe; Jin, Qi

2009-08-01

According to the principle of SCM (Single Chip Microcomputer) and computer communication technique, the system is composed of chips such as ATML89C51, ADL0809, integrated circuit and sensors for UV radiation, which is designed for monitoring and controlling the UV index. This system can automatically collect the UV index data, analyze and check the history database, research the law of UV radiation in the region.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

PubMed

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip

PubMed Central

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min. PMID:23493871

Genome wide approaches to identify protein-DNA interactions.

PubMed

Ma, Tao; Ye, Zhenqing; Wang, Liguo

2018-05-29

Transcription factors are DNA-binding proteins that play key roles in many fundamental biological processes. Unraveling their interactions with DNA is essential to identify their target genes and understand the regulatory network. Genome-wide identification of their binding sites became feasible thanks to recent progress in experimental and computational approaches. ChIP-chip, ChIP-seq, and ChIP-exo are three widely used techniques to demarcate genome-wide transcription factor binding sites. This review aims to provide an overview of these three techniques including their experiment procedures, computational approaches, and popular analytic tools. ChIP-chip, ChIP-seq, and ChIP-exo have been the major techniques to study genome-wide in vivo protein-DNA interaction. Due to the rapid development of next-generation sequencing technology, array-based ChIP-chip is deprecated and ChIP-seq has become the most widely used technique to identify transcription factor binding sites in genome-wide. The newly developed ChIP-exo further improves the spatial resolution to single nucleotide. Numerous tools have been developed to analyze ChIP-chip, ChIP-seq and ChIP-exo data. However, different programs may employ different mechanisms or underlying algorithms thus each will inherently include its own set of statistical assumption and bias. So choosing the most appropriate analytic program for a given experiment needs careful considerations. Moreover, most programs only have command line interface so their installation and usage will require basic computation expertise in Unix/Linux. Copyright© Bentham Science Publishers; For any queries, please email at epub@benthamscience.org.

Acrylamide in Romanian food using HPLC-UV and a health risk assessment.

PubMed

Oroian, Mircea; Amariei, Sonia; Gutt, Gheorghe

2015-01-01

The aim of this study was to investigate the level of acrylamide from coffee, potato chips and French fries in Romanian food. According to the European Food Safety Authority, coffee beans, potato chips and French fries have the highest levels of acrylamide. For this survey, 50 samples of coffee beans, 50 samples of potato chips and 25 samples of French fries were purchased from different producers from the Romanian market. Acrylamide levels have been quantified using high-performance liquid chromatography with a diode array detector (HPLC-DAD) method, using water as mobile phase. Health risk assessment was achieved by computing the average daily intake, hazard quotient, cumulative risk, carcinogenic risk and cancer risk. For coffee, potato chips and French fries, acrylamide was not shown to pose a health risk in Romanian food.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Applications of holographic on-chip microscopy (Conference Presentation)

NASA Astrophysics Data System (ADS)

Ozcan, Aydogan

2017-02-01

My research focuses on the use of computation/algorithms to create new optical microscopy, sensing, and diagnostic techniques, significantly improving existing tools for probing micro- and nano-objects while also simplifying the designs of these analysis tools. In this presentation, I will introduce a set of computational microscopes which use lens-free on-chip imaging to replace traditional lenses with holographic reconstruction algorithms. Basically, 3D images of specimens are reconstructed from their "shadows" providing considerably improved field-of-view (FOV) and depth-of-field, thus enabling large sample volumes to be rapidly imaged, even at nanoscale. These new computational microscopes routinely generate <1-2 billion pixels (giga-pixels), where even single viruses can be detected with a FOV that is <100 fold wider than other techniques. At the heart of this leapfrog performance lie self-assembled liquid nano-lenses that are computationally imaged on a chip. The field-of-view of these computational microscopes is equal to the active-area of the sensor-array, easily reaching, for example, <20 mm^2 or <10 cm^2 by employing state-of-the-art CMOS or CCD imaging chips, respectively. In addition to this remarkable increase in throughput, another major benefit of this technology is that it lends itself to field-portable and cost-effective designs which easily integrate with smartphones to conduct giga-pixel tele-pathology and microscopy even in resource-poor and remote settings where traditional techniques are difficult to implement and sustain, thus opening the door to various telemedicine applications in global health. Through the development of similar computational imagers, I will also report the discovery of new 3D swimming patterns observed in human and animal sperm. One of this newly discovered and extremely rare motion is in the form of "chiral ribbons" where the planar swings of the sperm head occur on an osculating plane creating in some cases a helical ribbon and in some others a twisted ribbon. Shedding light onto the statistics and biophysics of various micro-swimmers' 3D motion, these results provide an important example of how biomedical imaging significantly benefits from emerging computational algorithms/theories, revolutionizing existing tools for observing various micro- and nano-scale phenomena in innovative, high-throughput, and yet cost-effective ways.

Lensfree Computational Microscopy Tools and their Biomedical Applications

NASA Astrophysics Data System (ADS)

Sencan, Ikbal

Conventional microscopy has been a revolutionary tool for biomedical applications since its invention several centuries ago. Ability to non-destructively observe very fine details of biological objects in real time enabled to answer many important questions about their structures and functions. Unfortunately, most of these advance microscopes are complex, bulky, expensive, and/or hard to operate, so they could not reach beyond the walls of well-equipped laboratories. Recent improvements in optoelectronic components and computational methods allow creating imaging systems that better fulfill the specific needs of clinics or research related biomedical applications. In this respect, lensfree computational microscopy aims to replace bulky and expensive optical components with compact and cost-effective alternatives through the use of computation, which can be particularly useful for lab-on-a-chip platforms as well as imaging applications in low-resource settings. Several high-throughput on-chip platforms are built with this approach for applications including, but not limited to, cytometry, micro-array imaging, rare cell analysis, telemedicine, and water quality screening. The lack of optical complexity in these lensfree on-chip imaging platforms is compensated by using computational techniques. These computational methods are utilized for various purposes in coherent, incoherent and fluorescent on-chip imaging platforms e.g. improving the spatial resolution, to undo the light diffraction without using lenses, localization of objects in a large volume and retrieval of the phase or the color/spectral content of the objects. For instance, pixel super resolution approaches based on source shifting are used in lensfree imaging platforms to prevent under sampling, Bayer pattern, and aliasing artifacts. Another method, iterative phase retrieval, is utilized to compensate the lack of lenses by undoing the diffraction and removing the twin image noise of in-line holograms. This technique enables recovering the complex optical field from its intensity measurement(s) by using additional constraints in iterations, such as spatial boundaries and other known properties of objects. Another computational tool employed in lensfree imaging is compressive sensing (or decoding), which is a novel method taking advantage of the fact that natural signals/objects are mostly sparse or compressible in known bases. This inherent property of objects enables better signal recovery when the number of measurement is low, even below the Nyquist rate, and increases the additive noise immunity of the system.

Calculating with light using a chip-scale all-optical abacus.

PubMed

Feldmann, J; Stegmaier, M; Gruhler, N; Ríos, C; Bhaskaran, H; Wright, C D; Pernice, W H P

2017-11-02

Machines that simultaneously process and store multistate data at one and the same location can provide a new class of fast, powerful and efficient general-purpose computers. We demonstrate the central element of an all-optical calculator, a photonic abacus, which provides multistate compute-and-store operation by integrating functional phase-change materials with nanophotonic chips. With picosecond optical pulses we perform the fundamental arithmetic operations of addition, subtraction, multiplication, and division, including a carryover into multiple cells. This basic processing unit is embedded into a scalable phase-change photonic network and addressed optically through a two-pulse random access scheme. Our framework provides first steps towards light-based non-von Neumann arithmetic.

Hardware-based Artificial Neural Networks for Size, Weight, and Power Constrained Platforms (Preprint)

DTIC Science & Technology

2012-11-01

few sensors/complex computations, and many sensors/simple computation. II. CHALLENGES WITH NANO-ENABLED NEUROMORPHIC CHIPS A wide variety of...scenarios. Neuromorphic processors, which are based on the highly parallelized computing architecture of the mammalian brain, show great promise in...in the brain. This fundamentally different approach, frequently referred to as neuromorphic computing, is thought to be better able to solve fuzzy

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, Earl A.; Lipshutz, Robert J.; Morris, Macdonald S.; Winkler, James L.

1997-01-01

An improved set of computer tools for forming arrays. According to one aspect of the invention, a computer system is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files to design and/or generate lithographic masks.

Computational imaging of sperm locomotion.

PubMed

Daloglu, Mustafa Ugur; Ozcan, Aydogan

2017-08-01

Not only essential for scientific research, but also in the analysis of male fertility and for animal husbandry, sperm tracking and characterization techniques have been greatly benefiting from computational imaging. Digital image sensors, in combination with optical microscopy tools and powerful computers, have enabled the use of advanced detection and tracking algorithms that automatically map sperm trajectories and calculate various motility parameters across large data sets. Computational techniques are driving the field even further, facilitating the development of unconventional sperm imaging and tracking methods that do not rely on standard optical microscopes and objective lenses, which limit the field of view and volume of the semen sample that can be imaged. As an example, a holographic on-chip sperm imaging platform, only composed of a light-emitting diode and an opto-electronic image sensor, has emerged as a high-throughput, low-cost and portable alternative to lens-based traditional sperm imaging and tracking methods. In this approach, the sample is placed very close to the image sensor chip, which captures lensfree holograms generated by the interference of the background illumination with the light scattered from sperm cells. These holographic patterns are then digitally processed to extract both the amplitude and phase information of the spermatozoa, effectively replacing the microscope objective lens with computation. This platform has further enabled high-throughput 3D imaging of spermatozoa with submicron 3D positioning accuracy in large sample volumes, revealing various rare locomotion patterns. We believe that computational chip-scale sperm imaging and 3D tracking techniques will find numerous opportunities in both sperm related research and commercial applications. © The Authors 2017. Published by Oxford University Press on behalf of Society for the Study of Reproduction. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

Crossbar Nanocomputer Development

DTIC Science & Technology

2012-04-01

their utilization. Areas such as neuromorphic computing, signal processing, arithmetic processing, and crossbar computing are only some of the...due to its intrinsic, network-on- chip flexibility to re-route around defects. Preliminary efforts in crossbar computing have been demonstrated by...they approach their scaling limits [2]. Other applications that memristive devices are suited for include FPGA [3], encryption [4], and neuromorphic

Cell-NPE (Numerical Performance Evaluation): Programming the IBM Cell Broadband Engine -- A General Parallelization Strategy

DTIC Science & Technology

2008-04-01

Space GmbH as follows: B. TECHNICAL PRPOPOSA/DESCRIPTION OF WORK Cell: A Revolutionary High Performance Computing Platform On 29 June 2005 [1...IBM has announced that is has partnered with Mercury Computer Systems, a maker of specialized computers . The Cell chip provides massive floating-point...the computing industry away from the traditional processor technology dominated by Intel. While in the past, the development of computing power has

GRAPE-4: A special-purpose computer for gravitational N-body problems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Makino, Junichiro; Taiji, Makoto; Ebisuzaki, Toshikazu

1995-12-01

We describe GRAPE-4, a special-purpose computer for gravitational N-body simulations. In gravitational N-body simulations, almost all computing time is spent for the calculation of interaction between particles. GRAPE-4 is a specialized hardware to calculate the interaction between particles. It is used with a general-purpose host computer that performs all calculations other than the force calculation. With this architecture, it is relatively easy to realize a massively parallel system. In 1991, we developed the GRAPE-3 system with the peak speed equivalent to 14.4 Gflops. It consists of 48 custom pipelined processors. In 1992 we started the development of GRAPE-4. The GRAPE-4more » system will consist of 1920 custom pipeline chips. Each chip has the speed of 600 Mflops, when operated on 30 MHz clock. A prototype system with two custom LSIs has been completed July 1994, and the full system is now under manufacturing.« less

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

PubMed

Chen, Guanyu; Yu, Yu; Zhang, Xinliang

2016-08-01

We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Töpper, Michael; Reichl, Herbert

2009-05-01

Technological frontiers between semiconductor technology, packaging, and system design are disappearing. Scaling down geometries [1] alone does not provide improvement of performance, less power, smaller size, and lower cost. It will require "More than Moore" [2] through the tighter integration of system level components at the package level. System-in-Package (SiP) will deliver the efficient use of three dimensions (3D) through innovation in packaging and interconnect technology. A key bottleneck to the implementation of high-performance microelectronic systems, including SiP, is the lack of lowlatency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk [3]. Obviously, the incentive for the use of photonics to overcome the challenges and leverage low-latency and highbandwidth communication will enable the vision of optical computing within next generation architectures. Supercomputers of today offer sustained performance of more than petaflops, which can be increased by utilizing optical interconnects. Next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel interconnection technologies. In this paper we will discuss a CMOS compatible underlying technology to enable next generation optical computing architectures. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Measuring Sister Chromatid Cohesion Protein Genome Occupancy in Drosophila melanogaster by ChIP-seq.

PubMed

Dorsett, Dale; Misulovin, Ziva

2017-01-01

This chapter presents methods to conduct and analyze genome-wide chromatin immunoprecipitation of the cohesin complex and the Nipped-B cohesin loading factor in Drosophila cells using high-throughput DNA sequencing (ChIP-seq). Procedures for isolation of chromatin, immunoprecipitation, and construction of sequencing libraries for the Ion Torrent Proton high throughput sequencer are detailed, and computational methods to calculate occupancy as input-normalized fold-enrichment are described. The results obtained by ChIP-seq are compared to those obtained by ChIP-chip (genomic ChIP using tiling microarrays), and the effects of sequencing depth on the accuracy are analyzed. ChIP-seq provides similar sensitivity and reproducibility as ChIP-chip, and identifies the same broad regions of occupancy. The locations of enrichment peaks, however, can differ between ChIP-chip and ChIP-seq, and low sequencing depth can splinter broad regions of occupancy into distinct peaks.

Memristor-Based Synapse Design and Training Scheme for Neuromorphic Computing Architecture

DTIC Science & Technology

2012-06-01

system level built upon the conventional Von Neumann computer architecture [2][3]. Developing the neuromorphic architecture at chip level by...SCHEME FOR NEUROMORPHIC COMPUTING ARCHITECTURE 5a. CONTRACT NUMBER FA8750-11-2-0046 5b. GRANT NUMBER N/A 5c. PROGRAM ELEMENT NUMBER 62788F 6...creation of memristor-based neuromorphic computing architecture. Rather than the existing crossbar-based neuron network designs, we focus on memristor

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, Earl A.; Morris, MacDonald S.; Winkler, James L.

1999-01-05

An improved set of computer tools for forming arrays. According to one aspect of the invention, a computer system (100) is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files (104) to design and/or generate lithographic masks (110).

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, Earl A.; Morris, MacDonald S.; Winkler, James L.

1996-01-01

An improved set of computer tools for forming arrays. According to one aspect of the invention, a computer system (100) is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files (104) to design and/or generate lithographic masks (110).

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, E.A.; Morris, M.S.; Winkler, J.L.

1999-01-05

An improved set of computer tools for forming arrays is disclosed. According to one aspect of the invention, a computer system is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files to design and/or generate lithographic masks. 14 figs.

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, E.A.; Lipshutz, R.J.; Morris, M.S.; Winkler, J.L.

1997-01-14

An improved set of computer tools for forming arrays is disclosed. According to one aspect of the invention, a computer system is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files to design and/or generate lithographic masks. 14 figs.

Computer-aided engineering system for design of sequence arrays and lithographic masks

DOEpatents

Hubbell, E.A.; Morris, M.S.; Winkler, J.L.

1996-11-05

An improved set of computer tools for forming arrays is disclosed. According to one aspect of the invention, a computer system is used to select probes and design the layout of an array of DNA or other polymers with certain beneficial characteristics. According to another aspect of the invention, a computer system uses chip design files to design and/or generate lithographic masks. 14 figs.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

What Can You Learn from a Cell Phone? Almost Anything!

ERIC Educational Resources Information Center

Prensky, Marc

2005-01-01

Today's high-end cell phones have the computing power of a mid-1990s personal computer (PC)--while consuming only one one-hundredth of the energy. Even the simplest, voice-only phones have more complex and powerful chips than the 1969 on-board computer that landed a spaceship on the moon. In the United States, it is almost universally acknowledged…

Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency

NASA Astrophysics Data System (ADS)

Wang, Shibing; Baron, Stanislas; Kachwala, Nishrin; Kallingal, Chidam; Sun, Dezheng; Shu, Vincent; Fong, Weichun; Li, Zero; Elsaid, Ahmad; Gao, Jin-Wei; Su, Jing; Ser, Jung-Hoon; Zhang, Quan; Chen, Been-Der; Howell, Rafael; Hsu, Stephen; Luo, Larry; Zou, Yi; Zhang, Gary; Lu, Yen-Wen; Cao, Yu

2018-03-01

Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time. Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO). Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy. ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges. In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

Optimal Design of Low-Density SNP Arrays for Genomic Prediction: Algorithm and Applications.

PubMed

Wu, Xiao-Lin; Xu, Jiaqi; Feng, Guofei; Wiggans, George R; Taylor, Jeremy F; He, Jun; Qian, Changsong; Qiu, Jiansheng; Simpson, Barry; Walker, Jeremy; Bauck, Stewart

2016-01-01

Low-density (LD) single nucleotide polymorphism (SNP) arrays provide a cost-effective solution for genomic prediction and selection, but algorithms and computational tools are needed for the optimal design of LD SNP chips. A multiple-objective, local optimization (MOLO) algorithm was developed for design of optimal LD SNP chips that can be imputed accurately to medium-density (MD) or high-density (HD) SNP genotypes for genomic prediction. The objective function facilitates maximization of non-gap map length and system information for the SNP chip, and the latter is computed either as locus-averaged (LASE) or haplotype-averaged Shannon entropy (HASE) and adjusted for uniformity of the SNP distribution. HASE performed better than LASE with ≤1,000 SNPs, but required considerably more computing time. Nevertheless, the differences diminished when >5,000 SNPs were selected. Optimization was accomplished conditionally on the presence of SNPs that were obligated to each chromosome. The frame location of SNPs on a chip can be either uniform (evenly spaced) or non-uniform. For the latter design, a tunable empirical Beta distribution was used to guide location distribution of frame SNPs such that both ends of each chromosome were enriched with SNPs. The SNP distribution on each chromosome was finalized through the objective function that was locally and empirically maximized. This MOLO algorithm was capable of selecting a set of approximately evenly-spaced and highly-informative SNPs, which in turn led to increased imputation accuracy compared with selection solely of evenly-spaced SNPs. Imputation accuracy increased with LD chip size, and imputation error rate was extremely low for chips with ≥3,000 SNPs. Assuming that genotyping or imputation error occurs at random, imputation error rate can be viewed as the upper limit for genomic prediction error. Our results show that about 25% of imputation error rate was propagated to genomic prediction in an Angus population. The utility of this MOLO algorithm was also demonstrated in a real application, in which a 6K SNP panel was optimized conditional on 5,260 obligatory SNP selected based on SNP-trait association in U.S. Holstein animals. With this MOLO algorithm, both imputation error rate and genomic prediction error rate were minimal.

Optimal Design of Low-Density SNP Arrays for Genomic Prediction: Algorithm and Applications

PubMed Central

Wu, Xiao-Lin; Xu, Jiaqi; Feng, Guofei; Wiggans, George R.; Taylor, Jeremy F.; He, Jun; Qian, Changsong; Qiu, Jiansheng; Simpson, Barry; Walker, Jeremy; Bauck, Stewart

2016-01-01

Low-density (LD) single nucleotide polymorphism (SNP) arrays provide a cost-effective solution for genomic prediction and selection, but algorithms and computational tools are needed for the optimal design of LD SNP chips. A multiple-objective, local optimization (MOLO) algorithm was developed for design of optimal LD SNP chips that can be imputed accurately to medium-density (MD) or high-density (HD) SNP genotypes for genomic prediction. The objective function facilitates maximization of non-gap map length and system information for the SNP chip, and the latter is computed either as locus-averaged (LASE) or haplotype-averaged Shannon entropy (HASE) and adjusted for uniformity of the SNP distribution. HASE performed better than LASE with ≤1,000 SNPs, but required considerably more computing time. Nevertheless, the differences diminished when >5,000 SNPs were selected. Optimization was accomplished conditionally on the presence of SNPs that were obligated to each chromosome. The frame location of SNPs on a chip can be either uniform (evenly spaced) or non-uniform. For the latter design, a tunable empirical Beta distribution was used to guide location distribution of frame SNPs such that both ends of each chromosome were enriched with SNPs. The SNP distribution on each chromosome was finalized through the objective function that was locally and empirically maximized. This MOLO algorithm was capable of selecting a set of approximately evenly-spaced and highly-informative SNPs, which in turn led to increased imputation accuracy compared with selection solely of evenly-spaced SNPs. Imputation accuracy increased with LD chip size, and imputation error rate was extremely low for chips with ≥3,000 SNPs. Assuming that genotyping or imputation error occurs at random, imputation error rate can be viewed as the upper limit for genomic prediction error. Our results show that about 25% of imputation error rate was propagated to genomic prediction in an Angus population. The utility of this MOLO algorithm was also demonstrated in a real application, in which a 6K SNP panel was optimized conditional on 5,260 obligatory SNP selected based on SNP-trait association in U.S. Holstein animals. With this MOLO algorithm, both imputation error rate and genomic prediction error rate were minimal. PMID:27583971

Novel Ultrahigh Vacuum System for Chip-Scale Trapped Ion Quantum Computing

NASA Astrophysics Data System (ADS)

Chen, Shaw-Pin; Trapped Team

2011-05-01

This presentation reports the experimental results of an ultrahigh vacuum (UHV) system as a scheme to implement scalable trapped-ion quantum computers that use micro-fabricated ion traps as fundamental building blocks. The novelty of this system resides in our design, material selection, mechanical liability, low complexity of assembly, and reduced signal interference between DC and RF electrodes. Our system utilizes RF isolation and onsite-filtering topologies to attenuate AC signals generated from the resonator. We use a UHV compatible printed circuit board (PCB) material to perform DC routing, while the RF high and RF ground received separated routing via wire-wrapping. The standard PCB fabrication process enabled us to implement ceramic-based filter components adjacent to the chip trap. The DC electrodes are connected to air-side electrical feed through using four 25D adaptors made with polyether ether ketone (PEEK). The assembly process of this system is straight forward and in-chamber structure is self-supporting. We report on initial testing of this concept with a linear chip trap fabricated by the Sandia National Labs.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

NASA Technical Reports Server (NTRS)

Deutsch, L. J.

1985-01-01

A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

KSC-03pd1232

NASA Image and Video Library

2003-04-24

KENNEDY SPACE CENTER, FLA. - Jim Lloyd, with the Mars Exploration Rover program, holds a computer chip with about 35,000 laser-engraved signatures of visitors to the Jet Propulsion Laboratory. The chip will be placed on the second rover to be launched to Mars (MER-1/MER-B); the first rover already has one. The signatures include those of senators, artists, and John Glenn. The identical Mars rovers are scheduled to launch June 5 and June 25 from Cape Canaveral Air Force Station.

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

An integrated microfluidic analysis microsystems with bacterial capture enrichment and in-situ impedance detection

NASA Astrophysics Data System (ADS)

Liu, Hai-Tao; Wen, Zhi-Yu; Xu, Yi; Shang, Zheng-Guo; Peng, Jin-Lan; Tian, Peng

2017-09-01

In this paper, an integrated microfluidic analysis microsystems with bacterial capture enrichment and in-situ impedance detection was purposed based on microfluidic chips dielectrophoresis technique and electrochemical impedance detection principle. The microsystems include microfluidic chip, main control module, and drive and control module, and signal detection and processing modulet and result display unit. The main control module produce the work sequence of impedance detection system parts and achieve data communication functions, the drive and control circuit generate AC signal which amplitude and frequency adjustable, and it was applied on the foodborne pathogens impedance analysis microsystems to realize the capture enrichment and impedance detection. The signal detection and processing circuit translate the current signal into impendence of bacteria, and transfer to computer, the last detection result is displayed on the computer. The experiment sample was prepared by adding Escherichia coli standard sample into chicken sample solution, and the samples were tested on the dielectrophoresis chip capture enrichment and in-situ impedance detection microsystems with micro-array electrode microfluidic chips. The experiments show that the Escherichia coli detection limit of microsystems is 5 × 104 CFU/mL and the detection time is within 6 min in the optimization of voltage detection 10 V and detection frequency 500 KHz operating conditions. The integrated microfluidic analysis microsystems laid the solid foundation for rapid real-time in-situ detection of bacteria.

When the Chips Are Down.

ERIC Educational Resources Information Center

Ashton, Ray

1995-01-01

Strips away advertising hyperbole to explain multimedia CD-ROM technology and its place in today's classrooms. Only the newest computers are adequate for multimedia CD-ROM; only 10% of all computers in schools have CD-ROM drives attached. CD-ROM drives' performance varies, installation hassles abound, and the "edutainment" market directs…

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Microfluidic Chips Controlled with Elastomeric Microvalve Arrays

PubMed Central

Li, Nianzhen; Sip, Chris; Folch, Albert

2007-01-01

Miniaturized microfluidic systems provide simple and effective solutions for low-cost point-of-care diagnostics and high-throughput biomedical assays. Robust flow control and precise fluidic volumes are two critical requirements for these applications. We have developed microfluidic chips featuring elastomeric polydimethylsiloxane (PDMS) microvalve arrays that: 1) need no extra energy source to close the fluidic path, hence the loaded device is highly portable; and 2) allow for microfabricating deep (up to 1 mm) channels with vertical sidewalls and resulting in very precise features. The PDMS microvalves-based devices consist of three layers: a fluidic layer containing fluidic paths and microchambers of various sizes, a control layer containing the microchannels necessary to actuate the fluidic path with microvalves, and a middle thin PDMS membrane that is bound to the control layer. Fluidic layer and control layers are made by replica molding of PDMS from SU-8 photoresist masters, and the thin PDMS membrane is made by spinning PDMS at specified heights. The control layer is bonded to the thin PDMS membrane after oxygen activation of both, and then assembled with the fluidic layer. The microvalves are closed at rest and can be opened by applying negative pressure (e.g., house vacuum). Microvalve closure and opening are automated via solenoid valves controlled by computer software. Here, we demonstrate two microvalve-based microfluidic chips for two different applications. The first chip allows for storing and mixing precise sub-nanoliter volumes of aqueous solutions at various mixing ratios. The second chip allows for computer-controlled perfusion of microfluidic cell cultures. The devices are easy to fabricate and simple to control. Due to the biocompatibility of PDMS, these microchips could have broad applications in miniaturized diagnostic assays as well as basic cell biology studies. PMID:18989408

Scaling the Poisson Distribution

ERIC Educational Resources Information Center

Farnsworth, David L.

2014-01-01

We derive the additive property of Poisson random variables directly from the probability mass function. An important application of the additive property to quality testing of computer chips is presented.

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

PubMed Central

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-01-01

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

PubMed

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-04-13

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Sandia PUF Analysis Tool

DOE Office of Scientific and Technical Information (OSTI.GOV)

2014-06-11

This program is a graphical user interface for measuring and performing inter-active analysis of physical unclonable functions (PUFs). It is intended for demonstration and education purposes. See license.txt for license details. The program features a PUF visualization that demonstrates how signatures differ between PUFs and how they exhibit noise over repeated measurements. A similarity scoreboard shows the user how close the current measurement is to the closest chip signatures in the database. Other metrics such as average noise and inter-chip Hamming distances are presented to the user. Randomness tests published in NIST SP 800-22 can be computed and displayed. Noisemore » and inter-chip histograms for the sample of PUFs and repeated PUF measurements can be drawn.« less

Selective attention in multi-chip address-event systems.

PubMed

Bartolozzi, Chiara; Indiveri, Giacomo

2009-01-01

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Optofluidic encapsulation and manipulation of silicon microchips using image processing based optofluidic maskless lithography and railed microfluidics.

PubMed

Chung, Su Eun; Lee, Seung Ah; Kim, Jiyun; Kwon, Sunghoon

2009-10-07

We demonstrate optofluidic encapsulation of silicon microchips using image processing based optofluidic maskless lithography and manipulation using railed microfluidics. Optofluidic maskless lithography is a dynamic photopolymerization technique of free-floating microstructures within a fluidic channel using spatial light modulator. Using optofluidic maskless lithography via computer-vision aided image processing, polymer encapsulants are fabricated for chip protection and guiding-fins for efficient chip conveying within a fluidic channel. Encapsulated silicon chips with guiding-fins are assembled using railed microfluidics, which is an efficient guiding and heterogeneous self-assembly system of microcomponents. With our technology, externally fabricated silicon microchips are encapsulated, fluidically guided and self-assembled potentially enabling low cost fluidic manipulation and assembly of integrated circuits.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murray, E.; Floether, F. F.; Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE

Fundamental to integrated photonic quantum computing is an on-chip method for routing and modulating quantum light emission. We demonstrate a hybrid integration platform consisting of arbitrarily designed waveguide circuits and single-photon sources. InAs quantum dots (QD) embedded in GaAs are bonded to a SiON waveguide chip such that the QD emission is coupled to the waveguide mode. The waveguides are SiON core embedded in a SiO{sub 2} cladding. A tuneable Mach Zehnder interferometer (MZI) modulates the emission between two output ports and can act as a path-encoded qubit preparation device. The single-photon nature of the emission was verified using themore » on-chip MZI as a beamsplitter in a Hanbury Brown and Twiss measurement.« less

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Annual Review of Progress in Applied Computational Electromagnetics (6th), Held in Monterey, California on March 19-22, 1990

DTIC Science & Technology

1990-01-01

the six fields will have two million cell locations. The table below shows the total allocation of 392 chips across fields and banks. To allow for...future growth, we allocate 16 wires for addressing both the rows and columns. eU 4 MBit locations bytes bits Chips (millions) (millions) (millions) per...sources apt to appear in most problems. If material parameters change during a run, then time must be allocated to read these constants into their

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

NASA Astrophysics Data System (ADS)

Shulaker, Max M.; Hills, Gage; Park, Rebecca S.; Howe, Roger T.; Saraswat, Krishna; Wong, H.-S. Philip; Mitra, Subhasish

2017-07-01

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Computational analysis of integrated biosensing and shear flow in a microfluidic vascular model

NASA Astrophysics Data System (ADS)

Wong, Jeremy F.; Young, Edmond W. K.; Simmons, Craig A.

2017-11-01

Fluid flow and flow-induced shear stress are critical components of the vascular microenvironment commonly studied using microfluidic cell culture models. Microfluidic vascular models mimicking the physiological microenvironment also offer great potential for incorporating on-chip biomolecular detection. In spite of this potential, however, there are few examples of such functionality. Detection of biomolecules released by cells under flow-induced shear stress is a significant challenge due to severe sample dilution caused by the fluid flow used to generate the shear stress, frequently to the extent where the analyte is no longer detectable. In this work, we developed a computational model of a vascular microfluidic cell culture model that integrates physiological shear flow and on-chip monitoring of cell-secreted factors. Applicable to multilayer device configurations, the computational model was applied to a bilayer configuration, which has been used in numerous cell culture applications including vascular models. Guidelines were established that allow cells to be subjected to a wide range of physiological shear stress while ensuring optimal rapid transport of analyte to the biosensor surface and minimized biosensor response times. These guidelines therefore enable the development of microfluidic vascular models that integrate cell-secreted factor detection while addressing flow constraints imposed by physiological shear stress. Ultimately, this work will result in the addition of valuable functionality to microfluidic cell culture models that further fulfill their potential as labs-on-chips.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip.

PubMed

Shulaker, Max M; Hills, Gage; Park, Rebecca S; Howe, Roger T; Saraswat, Krishna; Wong, H-S Philip; Mitra, Subhasish

2017-07-05

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Microprocessors: An Understandable Guide for the Classroom Teacher.

ERIC Educational Resources Information Center

Okinaka, Russell T.

A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…

High-Rate Digital Receiver Board

NASA Technical Reports Server (NTRS)

Ghuman, Parminder; Bialas, Thomas; Brambora, Clifford; Fisher, David

2004-01-01

A high-rate digital receiver (HRDR) implemented as a peripheral component interface (PCI) board has been developed as a prototype of compact, general-purpose, inexpensive, potentially mass-producible data-acquisition interfaces between telemetry systems and personal computers. The installation of this board in a personal computer together with an analog preprocessor enables the computer to function as a versatile, highrate telemetry-data-acquisition and demodulator system. The prototype HRDR PCI board can handle data at rates as high as 600 megabits per second, in a variety of telemetry formats, transmitted by diverse phase-modulation schemes that include binary phase-shift keying and various forms of quadrature phaseshift keying. Costing less than $25,000 (as of year 2003), the prototype HRDR PCI board supplants multiple racks of older equipment that, when new, cost over $500,000. Just as the development of standard network-interface chips has contributed to the proliferation of networked computers, it is anticipated that the development of standard chips based on the HRDR could contribute to reductions in size and cost and increases in performance of telemetry systems.

Computational Modeling of Ultrafast Pulse Propagation in Nonlinear Optical Materials

NASA Technical Reports Server (NTRS)

Goorjian, Peter M.; Agrawal, Govind P.; Kwak, Dochan (Technical Monitor)

1996-01-01

There is an emerging technology of photonic (or optoelectronic) integrated circuits (PICs or OEICs). In PICs, optical and electronic components are grown together on the same chip. rib build such devices and subsystems, one needs to model the entire chip. Accurate computer modeling of electromagnetic wave propagation in semiconductors is necessary for the successful development of PICs. More specifically, these computer codes would enable the modeling of such devices, including their subsystems, such as semiconductor lasers and semiconductor amplifiers in which there is femtosecond pulse propagation. Here, the computer simulations are made by solving the full vector, nonlinear, Maxwell's equations, coupled with the semiconductor Bloch equations, without any approximations. The carrier is retained in the description of the optical pulse, (i.e. the envelope approximation is not made in the Maxwell's equations), and the rotating wave approximation is not made in the Bloch equations. These coupled equations are solved to simulate the propagation of femtosecond optical pulses in semiconductor materials. The simulations describe the dynamics of the optical pulses, as well as the interband and intraband.

Performing quantum computing experiments in the cloud

NASA Astrophysics Data System (ADS)

Devitt, Simon J.

2016-09-01

Quantum computing technology has reached a second renaissance in the past five years. Increased interest from both the private and public sector combined with extraordinary theoretical and experimental progress has solidified this technology as a major advancement in the 21st century. As anticipated my many, some of the first realizations of quantum computing technology has occured over the cloud, with users logging onto dedicated hardware over the classical internet. Recently, IBM has released the Quantum Experience, which allows users to access a five-qubit quantum processor. In this paper we take advantage of this online availability of actual quantum hardware and present four quantum information experiments. We utilize the IBM chip to realize protocols in quantum error correction, quantum arithmetic, quantum graph theory, and fault-tolerant quantum computation by accessing the device remotely through the cloud. While the results are subject to significant noise, the correct results are returned from the chip. This demonstrates the power of experimental groups opening up their technology to a wider audience and will hopefully allow for the next stage of development in quantum information technology.

Special-purpose computer for holography HORN-4 with recurrence algorithm

NASA Astrophysics Data System (ADS)

Shimobaba, Tomoyoshi; Hishinuma, Sinsuke; Ito, Tomoyoshi

2002-10-01

We designed and built a special-purpose computer for holography, HORN-4 (HOlographic ReconstructioN) using PLD (Programmable Logic Device) technology. HORN computers have a pipeline architecture. We use HORN-4 as an attached processor to enhance the performance of a general-purpose computer when it is used to generate holograms using a "recurrence formulas" algorithm developed by our previous paper. In the HORN-4 system, we designed the pipeline by adopting our "recurrence formulas" algorithm which can calculate the phase on a hologram. As the result, we could integrate the pipeline composed of 21 units into one PLD chip. The units in the pipeline consists of one BPU (Basic Phase Unit) unit and twenty CU (Cascade Unit) units. These CU units can compute twenty light intensities on a hologram plane at one time. By mounting two of the PLD chips on a PCI (Peripheral Component Interconnect) universal board, HORN-4 can calculate holograms at high speed of about 42 Gflops equivalent. The cost of HORN-4 board is about 1700 US dollar. We could obtain 800×600 grids hologram from a 3D-image composed of 415 points in about 0.45 sec with the HORN-4 system.

Multicore: Fallout from a Computing Evolution

ScienceCinema

Yelick, Kathy [Director, NERSC

2017-12-09

July 22, 2008 Berkeley Lab lecture: Parallel computing used to be reserved for big science and engineering projects, but in two years that's all changed. Even laptops and hand-helds use parallel processors. Unfortunately, the software hasn't kept pace. Kathy Yelick, Director of the National Energy Research Scientific Computing Center at Berkeley Lab, describes the resulting chaos and the computing community's efforts to develop exciting applications that take advantage of tens or hundreds of processors on a single chip.

Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect.

PubMed

Liao, Chen; Hu, Shiyan

2014-03-01

Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique.

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Smartphone technology can be transformative to the deployment of lab-on-chip diagnostics.

PubMed

Erickson, David; O'Dell, Dakota; Jiang, Li; Oncescu, Vlad; Gumus, Abdurrahman; Lee, Seoho; Mancuso, Matthew; Mehta, Saurabh

2014-09-07

The rapid expansion of mobile technology is transforming the biomedical landscape. By 2016 there will be 260 M active smartphones in the US and millions of health accessories and software "apps" running off them. In parallel with this have come major technical achievements in lab-on-a-chip technology leading to incredible new biochemical sensors and molecular diagnostic devices. Despite these advancements, the uptake of lab-on-a-chip technologies at the consumer level has been somewhat limited. We believe that the widespread availability of smartphone technology and the capabilities they offer in terms of computation, communication, social networking, and imaging will be transformative to the deployment of lab-on-a-chip type technology both in the developed and developing world. In this paper we outline why we believe this is the case, the new business models that may emerge, and detail some specific application areas in which this synergy will have long term impact, namely: nutrition monitoring and disease diagnostics in limited resource settings.

Fabrication of a microfluidic Ag/AgCl reference electrode and its application for portable and disposable electrochemical microchips.

PubMed

Zhou, Jianhua; Ren, Kangning; Zheng, Yizhe; Su, Jing; Zhao, Yihua; Ryan, Declan; Wu, Hongkai

2010-09-01

This report describes a convenient method for the fabrication of a miniaturized, reliable Ag/AgCl reference electrode with nanofluidic channels acting as a salt bridge that can be easily integrated into microfluidic chips. The Ag/AgCl reference electrode shows high stability with millivolt variations. We demonstrated the application of this reference electrode in a portable microfluidic chip that is connected to a USB-port microelectrochemical station and to a computer for data collection and analysis. The low fabrication cost of the chip with the potential for mass production makes it disposable and an excellent candidate for real-world analysis and measurement. We used the chip to quantitatively analyze the concentrations of heavy metal ions (Cd(2+) and Pb(2+)) in sea water. We believe that the Ag/AgCl reference microelectrode and the portable electrochemical system will be of interest to people in microfluidics, environmental science, clinical diagnostics, and food research.

On-Chip Laser-Power Delivery System for Dielectric Laser Accelerators

NASA Astrophysics Data System (ADS)

Hughes, Tyler W.; Tan, Si; Zhao, Zhexin; Sapra, Neil V.; Leedle, Kenneth J.; Deng, Huiyang; Miao, Yu; Black, Dylan S.; Solgaard, Olav; Harris, James S.; Vuckovic, Jelena; Byer, Robert L.; Fan, Shanhui; England, R. Joel; Lee, Yun Jo; Qi, Minghao

2018-05-01

We propose an on-chip optical-power delivery system for dielectric laser accelerators based on a fractal "tree-network" dielectric waveguide geometry. This system replaces experimentally demanding free-space manipulations of the driving laser beam with chip-integrated techniques based on precise nanofabrication, enabling access to orders-of-magnitude increases in the interaction length and total energy gain for these miniature accelerators. Based on computational modeling, in the relativistic regime, our laser delivery system is estimated to provide 21 keV of energy gain over an acceleration length of 192 μ m with a single laser input, corresponding to a 108-MV/m acceleration gradient. The system may achieve 1 MeV of energy gain over a distance of less than 1 cm by sequentially illuminating 49 identical structures. These findings are verified by detailed numerical simulation and modeling of the subcomponents, and we provide a discussion of the main constraints, challenges, and relevant parameters with regard to on-chip laser coupling for dielectric laser accelerators.

Smartphone technology can be transformative to the deployment of lab-on-chip diagnostics

PubMed Central

Erickson, David; O’Dell, Dakota; Jiang, Li; Oncescu, Vlad; Gumus, Abdurrahman; Lee, Seoho; Mancuso, Matthew; Mehta, Saurabh

2014-01-01

The rapid expansion of mobile technology is transforming the biomedical landscape. By 2016 there will be 260M active smartphones in the US and millions of health accessories and software “apps” running off them. In parallel with this have come major technical achievements in lab-on-a-chip technology leading to incredible new biochemical sensors and molecular diagnostic devices. Despite these advancements, the uptake of lab-on-a-chip technologies at the consumer level has been somewhat limited. We believe that the widespread availability of smartphone technology and the capabilities they offer in terms of computation, communication, social networking, and imaging will be transformative to the deployment of lab-on-a-chip type technology both in the developed and developing world. In this paper we outline why we believe this is the case, the new business models that may emerge, and detail some specific application areas in which this synergy will have long term impact, namely: nutrition monitoring and disease diagnostics in limited resource settings. PMID:24700127

Versatile single-chip event sequencer for atomic physics experiments

NASA Astrophysics Data System (ADS)

Eyler, Edward

2010-03-01

A very inexpensive dsPIC microcontroller with internal 32-bit counters is used to produce a flexible timing signal generator with up to 16 TTL-compatible digital outputs, with a time resolution and accuracy of 50 ns. This time resolution is easily sufficient for event sequencing in typical experiments involving cold atoms or laser spectroscopy. This single-chip device is capable of triggered operation and can also function as a sweeping delay generator. With one additional chip it can also concurrently produce accurately timed analog ramps, and another one-chip addition allows real-time control from an external computer. Compared to an FPGA-based digital pattern generator, this design is slower but simpler and more flexible, and it can be reprogrammed using ordinary `C' code without special knowledge. I will also describe the use of the same microcontroller with additional hardware to implement a digital lock-in amplifier and PID controller for laser locking, including a simple graphics-based control unit. This work is supported in part by the NSF.

Titanium based flat heat pipes for computer chip cooling

NASA Astrophysics Data System (ADS)

Soni, Gaurav; Ding, Changsong; Sigurdson, Marin; Bozorgi, Payam; Piorek, Brian; MacDonald, Noel; Meinhart, Carl

2008-11-01

We are developing a highly conductive flat heat pipe (called Thermal Ground Plane or TGP) for cooling computer chips. Conventional heat pipes have circular cross sections and thus can't make good contact with chip surface. The flatness of our TGP will enable conformal contact with the chip surface and thus enhance cooling efficiency. Another limiting factor in conventional heat pipes is the capillary flow of the working fluid through a wick structure. In order to overcome this limitation we have created a highly porous wick structure on a flat titanium substrate by using micro fabrication technology. We first etch titanium to create very tall micro pillars with a diameter of 5 μm, a height of 40 μm and a pitch of 10 μm. We then grow a very fine nano structured titania (NST) hairs on all surfaces of the pillars by oxidation in H202. In this way we achieve a wick structure which utilizes multiple length scales to yield high performance wicking of water. It's capable of wicking water at an average velocity of 1 cm/s over a distance of several cm. A titanium cavity is laser-welded onto the wicking substrate and a small quantity of water is hermetically sealed inside the cavity to achieve a TGP. The thermal conductivity of our preliminary TGP was measured to be 350 W/m-K, but has the potential to be several orders of magnitude higher.

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

NASA Astrophysics Data System (ADS)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

Edge chipping and flexural resistance of monolithic ceramics☆

PubMed Central

Zhang, Yu; Lee, James J.-W.; Srikanth, Ramanathan; Lawn, Brian R.

2014-01-01

Objective Test the hypothesis that monolithic ceramics can be developed with combined esthetics and superior fracture resistance to circumvent processing and performance drawbacks of traditional all-ceramic crowns and fixed-dental-prostheses consisting of a hard and strong core with an esthetic porcelain veneer. Specifically, to demonstrate that monolithic prostheses can be produced with a much reduced susceptibility to fracture. Methods Protocols were applied for quantifying resistance to chipping as well as resistance to flexural failure in two classes of dental ceramic, microstructurally-modified zirconias and lithium disilicate glass–ceramics. A sharp indenter was used to induce chips near the edges of flat-layer specimens, and the results compared with predictions from a critical load equation. The critical loads required to produce cementation surface failure in monolithic specimens bonded to dentin were computed from established flexural strength relations and the predictions validated with experimental data. Results Monolithic zirconias have superior chipping and flexural fracture resistance relative to their veneered counterparts. While they have superior esthetics, glass–ceramics exhibit lower strength but higher chip fracture resistance relative to porcelain-veneered zirconias. Significance The study suggests a promising future for new and improved monolithic ceramic restorations, with combined durability and acceptable esthetics. PMID:24139756

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

PubMed

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

PubMed Central

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-01-01

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. PMID:28350358

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

Multi-Agent Methods for the Configuration of Random Nanocomputers

NASA Technical Reports Server (NTRS)

Lawson, John W.

2004-01-01

As computational devices continue to shrink, the cost of manufacturing such devices is expected to grow exponentially. One alternative to the costly, detailed design and assembly of conventional computers is to place the nano-electronic components randomly on a chip. The price for such a trivial assembly process is that the resulting chip would not be programmable by conventional means. In this work, we show that such random nanocomputers can be adaptively programmed using multi-agent methods. This is accomplished through the optimization of an associated high dimensional error function. By representing each of the independent variables as a reinforcement learning agent, we are able to achieve convergence must faster than with other methods, including simulated annealing. Standard combinational logic circuits such as adders and multipliers are implemented in a straightforward manner. In addition, we show that the intrinsic flexibility of these adaptive methods allows the random computers to be reconfigured easily, making them reusable. Recovery from faults is also demonstrated.

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

NASA Astrophysics Data System (ADS)

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; Del Giudice, Paolo

2015-10-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems.

PubMed

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; del Giudice, Paolo

2015-10-14

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a 'basin' of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

Parallel processing architecture for computing inverse differential kinematic equations of the PUMA arm

NASA Technical Reports Server (NTRS)

Hsia, T. C.; Lu, G. Z.; Han, W. H.

1987-01-01

In advanced robot control problems, on-line computation of inverse Jacobian solution is frequently required. Parallel processing architecture is an effective way to reduce computation time. A parallel processing architecture is developed for the inverse Jacobian (inverse differential kinematic equation) of the PUMA arm. The proposed pipeline/parallel algorithm can be inplemented on an IC chip using systolic linear arrays. This implementation requires 27 processing cells and 25 time units. Computation time is thus significantly reduced.

Multicore: Fallout From a Computing Evolution (LBNL Summer Lecture Series)

ScienceCinema

Yelick, Kathy [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). National Energy Research Scientific Computing Center (NERSC)

2018-05-07

Summer Lecture Series 2008: Parallel computing used to be reserved for big science and engineering projects, but in two years that's all changed. Even laptops and hand-helds use parallel processors. Unfortunately, the software hasn't kept pace. Kathy Yelick, Director of the National Energy Research Scientific Computing Center at Berkeley Lab, describes the resulting chaos and the computing community's efforts to develop exciting applications that take advantage of tens or hundreds of processors on a single chip.

50-GHz-spaced comb of high-dimensional frequency-bin entangled photons from an on-chip silicon nitride microresonator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Imany, Poolad; Jaramillo-Villegas, Jose A.; Odele, Ogaga D.

Quantum frequency combs from chip-scale integrated sources are promising candidates for scalable and robust quantum information processing (QIP). However, to use these quantum combs for frequency domain QIP, demonstration of entanglement in the frequency basis, showing that the entangled photons are in a coherent superposition of multiple frequency bins, is required. We present a verification of qubit and qutrit frequency-bin entanglement using an on-chip quantum frequency comb with 40 mode pairs, through a two-photon interference measurement that is based on electro-optic phase modulation. Our demonstrations provide an important contribution in establishing integrated optical microresonators as a source for high-dimensional frequency-binmore » encoded quantum computing, as well as dense quantum key distribution.« less

50-GHz-spaced comb of high-dimensional frequency-bin entangled photons from an on-chip silicon nitride microresonator

DOE PAGES

Imany, Poolad; Jaramillo-Villegas, Jose A.; Odele, Ogaga D.; ...

2018-01-18

Quantum frequency combs from chip-scale integrated sources are promising candidates for scalable and robust quantum information processing (QIP). However, to use these quantum combs for frequency domain QIP, demonstration of entanglement in the frequency basis, showing that the entangled photons are in a coherent superposition of multiple frequency bins, is required. We present a verification of qubit and qutrit frequency-bin entanglement using an on-chip quantum frequency comb with 40 mode pairs, through a two-photon interference measurement that is based on electro-optic phase modulation. Our demonstrations provide an important contribution in establishing integrated optical microresonators as a source for high-dimensional frequency-binmore » encoded quantum computing, as well as dense quantum key distribution.« less

Another expert system rule inference based on DNA molecule logic gates

NASA Astrophysics Data System (ADS)

WÄ siewicz, Piotr

2013-10-01

With the help of silicon industry microfluidic processors were invented utilizing nano membrane valves, pumps and microreactors. These so called lab-on-a-chips combined together with molecular computing create molecular-systems-ona- chips. This work presents a new approach to implementation of molecular inference systems. It requires the unique representation of signals by DNA molecules. The main part of this work includes the concept of logic gates based on typical genetic engineering reactions. The presented method allows for constructing logic gates with many inputs and for executing them at the same quantity of elementary operations, regardless of a number of input signals. Every microreactor of the lab-on-a-chip performs one unique operation on input molecules and can be connected by dataflow output-input connections to other ones.

Frequency non-degenerate phase-sensitive optical parametric amplification based on four-wave-mixing in width-modulated silicon waveguides.

PubMed

Wang, Zhaolu; Liu, Hongjun; Sun, Qibing; Huang, Nan; Li, Xuefeng

2014-12-15

A width-modulated silicon waveguide is proposed to realize non-degenerate phase sensitive optical parametric amplification. It is found that the relative phase at the input of the phase sensitive amplifier (PSA) θIn-PSA can be tuned by tailoring the width and length of the second segment of the width-modulated silicon waveguide, which will influence the gain in the parametric amplification process. The maximum gain of PSA is larger by 9 dB compared with the phase insensitive amplifier (PIA) gain, and the gain bandwidth of PSA is larger by 35 nm compared with the gain bandwidth of PIA. Our on-chip PSA can find important potential applications in highly integrated optical circuits for optical chip-to-chip communication and computers.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

A Simple and Affordable TTL Processor for the Classroom

ERIC Educational Resources Information Center

Feinberg, Dave

2007-01-01

This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

1986-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

KSC-07pd1239

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, Orbital Science technicians install a computer chip on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/Jim Grossmann

Design and Implement of Low Ripple and Quasi-digital Power Supply

NASA Astrophysics Data System (ADS)

Xiangli, Li; Yanjun, Wei; Hanhong, Qi; Yan, Ma

A switch linearity hybrid power supply based on single chip microcomputer is designed which merged the merits of the switching and linear power supply. Main circuit includes pre-regulator which works in switching mode and series regulator which works in linear mode. Two-stage regulation mode was adopted in the main circuit of the power. A single chip computer (SCM) and high resolution of series D/A and A/D converters are applied to control and measurement which achieved continuous adjustable and low ripple constant current or voltage power supply

KSC-07pd1238

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, a computer chip awaits installation on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/Jim Grossmann

KSC-03pd1231

NASA Image and Video Library

2003-04-24

KENNEDY SPACE CENTER, FLA. - Tom Shain, the MER ATLO logistics manager, holds a computer chip with about 35,000 laser-engraved signatures of visitors to the Mars Exploration Rovers at the Jet Propulsion Laboratory. He and Jim Lloyd, also with the program, will place the chip on the second rover to be launched to Mars (MER-1/MER-B); the first rover already has one. The signatures include those of senators, artists, and John Glenn. The identical Mars rovers are scheduled to launch June 5 and June 25 from Cape Canaveral Air Force Station.

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

2003-01-01

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

2004-01-01

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

Programmable neural processing on a smartdust for brain-computer interfaces.

PubMed

Yuwen Sun; Shimeng Huang; Oresko, Joseph J; Cheng, Allen C

2010-10-01

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Glossiness of Colored Papers based on Computer Graphics Model and Its Measuring Method

NASA Astrophysics Data System (ADS)

Aida, Teizo

In the case of colored papers, the color of surface effects strongly upon the gloss of its paper. The new glossiness for such a colored paper is suggested in this paper. First, using the Achromatic and Chromatic Munsell colored chips, the author obtained experimental equation which represents the relation between lightness V ( or V and saturation C ) and psychological glossiness Gph of these chips. Then, the author defined a new glossiness G for the colored papers, based on the above mentioned experimental equations Gph and Cook-Torrance's reflection model which are widely used in the filed of Computer Graphics. This new glossiness is shown to be nearly proportional to the psychological glossiness Gph. The measuring system for the new glossiness G is furthermore descrived. The measuring time for one specimen is within 1 minute.

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Spacecraft computer technology at Southwest Research Institute

NASA Technical Reports Server (NTRS)

Shirley, D. J.

1993-01-01

Southwest Research Institute (SwRI) has developed and delivered spacecraft computers for a number of different near-Earth-orbit spacecraft including shuttle experiments and SDIO free-flyer experiments. We describe the evolution of the basic SwRI spacecraft computer design from those weighing in at 20 to 25 lb and using 20 to 30 W to newer models weighing less than 5 lb and using only about 5 W, yet delivering twice the processing throughput. Because of their reduced size, weight, and power, these newer designs are especially applicable to planetary instrument requirements. The basis of our design evolution has been the availability of more powerful processor chip sets and the development of higher density packaging technology, coupled with more aggressive design strategies in incorporating high-density FPGA technology and use of high-density memory chips. In addition to reductions in size, weight, and power, the newer designs also address the necessity of survival in the harsh radiation environment of space. Spurred by participation in such programs as MSTI, LACE, RME, Delta 181, Delta Star, and RADARSAT, our designs have evolved in response to program demands to be small, low-powered units, radiation tolerant enough to be suitable for both Earth-orbit microsats and for planetary instruments. Present designs already include MIL-STD-1750 and Multi-Chip Module (MCM) technology with near-term plans to include RISC processors and higher-density MCM's. Long term plans include development of whole-core processors on one or two MCM's.

Greater trochanter chip fractures in the direct anterior approach for total hip arthroplasty.

PubMed

Homma, Yasuhiro; Baba, Tomonori; Ochi, Hironori; Ozaki, Yu; Kobayashi, Hideo; Matsumoto, Mikio; Yuasa, Takahito; Kaneko, Kazuo

2016-08-01

The direct anterior approach (DAA) for the treatment of total hip arthroplasty (THA) has gained popularity in recent years. Chip fractures of the greater trochanter are frequently seen, but the risk factors for such fractures are unknown. The study aimed to identify the risk factors for chip fractures in patients undergoing primary THA by the DAA during the surgeons' learning curve. From November 2011 to April 2015, the first experiences of three surgeons who performed 120 THAs by the DAA (120 hips; 40 cases per beginner surgeon) were included. The incidence of chip fracture of the greater trochanter, the size of the greater trochanter as measured by computed tomography, and the patients' characteristics were retrospectively investigated. After exclusion of 11 hips, the remaining 109 hips were investigated. Chip fracture of the greater trochanter was identified in 32 hips (29.4 %). Univariate analysis with and without fractures showed that the width and depth of the greater trochanter were statistically significant risk factors (p = 0.02 and p < 0.001, respectively). Multivariate analysis using a logistic regression model demonstrated that the depth of the greater trochanter was an independent risk factor for chip fracture of the greater trochanter (OR 1.725; 95 % CI 1.367-2.177; p < 0.001). The size of the greater trochanter was identified as a risk factor for chip fracture of the greater trochanter. Novice surgeons should pay attention to the size of the greater trochanter when performing THA by the DAA.

Design and Training of Limited-Interconnect Architectures

DTIC Science & Technology

1991-07-16

and signal processing. Neuromorphic (brain like) models, allow an alternative for achieving real-time operation tor such tasks, while having a...compact and robust architecture. Neuromorphic models consist of interconnections of simple computational nodes. In this approach, each node computes a...operational performance. I1. Research Objectives The research objectives were: 1. Development of on- chip local training rules specifically designed for

Neuromorphic computing with nanoscale spintronic oscillators

PubMed Central

Torrejon, Jacob; Riou, Mathieu; Araujo, Flavio Abreu; Tsunegi, Sumito; Khalsa, Guru; Querlioz, Damien; Bortolotti, Paolo; Cros, Vincent; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Stiles, M. D.; Grollier, Julie

2017-01-01

Neurons in the brain behave as non-linear oscillators, which develop rhythmic activity and interact to process information1. Taking inspiration from this behavior to realize high density, low power neuromorphic computing will require huge numbers of nanoscale non-linear oscillators. Indeed, a simple estimation indicates that, in order to fit a hundred million oscillators organized in a two-dimensional array inside a chip the size of a thumb, their lateral dimensions must be smaller than one micrometer. However, despite multiple theoretical proposals2–5, and several candidates such as memristive6 or superconducting7 oscillators, there is no proof of concept today of neuromorphic computing with nano-oscillators. Indeed, nanoscale devices tend to be noisy and to lack the stability required to process data in a reliable way. Here, we show experimentally that a nanoscale spintronic oscillator8,9 can achieve spoken digit recognition with accuracies similar to state of the art neural networks. We pinpoint the regime of magnetization dynamics leading to highest performance. These results, combined with the exceptional ability of these spintronic oscillators to interact together, their long lifetime, and low energy consumption, open the path to fast, parallel, on-chip computation based on networks of oscillators. PMID:28748930

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

MO detector (MOD): a dual-function optical modulator-detector for on-chip communication

NASA Astrophysics Data System (ADS)

Sun, Shuai; Zhang, Ruoyu; Peng, Jiaxin; Narayana, Vikram K.; Dalir, Hamed; El-Ghazawi, Tarek; Sorger, Volker J.

2018-04-01

Physical challenges at the device and interconnect level limit both network and computing energy efficiency. While photonics is being considered to address interconnect bottlenecks, optical routing is still limited by electronic circuitry, requiring substantial overhead for optical-electrical-optical conversion. Here we show a novel design of an integrated broadband photonic-plasmonic hybrid device termed MODetector featuring dual light modulation and detection function to act as an optical transceiver in the photonic network-on-chip. With over 10 dB extinction ratio and 0.8 dB insertion loss at the modulation state, this MODetector provides 0.7 W/A responsivity in the detection state with 36 ps response time. This multi-functional device: (i) eliminates OEO conversion, (ii) reduces optical losses from photodetectors when not needed, and (iii) enables cognitive routing strategies for network-on-chips.

Pathomorphism of spiral tibial fractures in computed tomography imaging.

PubMed

Guzik, Grzegorz

2011-01-01

Spiral fractures of the tibia are virtually homogeneous with regard to their pathomorphism. The differences that are seen concern the level of fracture of the fibula, and, to a lesser extent, the level of fracture of the tibia, the length of fracture cleft, and limb shortening following the trauma. While conventional radiographs provide sufficient information about the pathomorphism of fractures, computed tomography can be useful in demonstrating the spatial arrangement of bone fragments and topography of soft tissues surrounding the fracture site. Multiple cross-sectional computed tomography views of spiral fractures of the tibia show the details of the alignment of bone chips at the fracture site, axis of the tibial fracture cleft, and topography of soft tissues that are not visible on standard radiographs. A model of a spiral tibial fracture reveals periosteal stretching with increasing spiral and longitudinal displacement. The cleft in tibial fractures has a spiral shape and its line is invariable. Every spiral fracture of both crural bones results in extensive damage to the periosteum and may damage bellies of the long flexor muscle of toes, flexor hallucis longus as well as the posterior tibial muscle. Computed tomography images of spiral fractures of the tibia show details of damage that are otherwise invisible on standard radiographs. Moreover, CT images provide useful information about the spatial location of the bone chips as well as possible threats to soft tissues that surround the fracture site. Every spiral fracture of the tibia is associated with disruption of the periosteum. 1. Computed tomography images of spiral fractures of the tibia show details of damage otherwise invisible on standard radiographs, 2. The sharp end of the distal tibial chip can damage the tibialis posterior muscle, long flexor muscles of the toes and the flexor hallucis longus, 3. Every spiral fracture of the tibia is associated with disruption of the periosteum.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Design Trade-off Between Performance and Fault-Tolerance of Space Onboard Computers

NASA Astrophysics Data System (ADS)

Gorbunov, M. S.; Antonov, A. A.

2017-01-01

It is well known that there is a trade-off between performance and power consumption in onboard computers. The fault-tolerance is another important factor affecting performance, chip area and power consumption. Involving special SRAM cells and error-correcting codes is often too expensive with relation to the performance needed. We discuss the possibility of finding the optimal solutions for modern onboard computer for scientific apparatus focusing on multi-level cache memory design.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

NASA Astrophysics Data System (ADS)

Yang, Chen; Liu, LeiBo; Yin, ShouYi; Wei, ShaoJun

2014-12-01

The computational capability of a coarse-grained reconfigurable array (CGRA) can be significantly restrained due to data and context memory bandwidth bottlenecks. Traditionally, two methods have been used to resolve this problem. One method loads the context into the CGRA at run time. This method occupies very small on-chip memory but induces very large latency, which leads to low computational efficiency. The other method adopts a multi-context structure. This method loads the context into the on-chip context memory at the boot phase. Broadcasting the pointer of a set of contexts changes the hardware configuration on a cycle-by-cycle basis. The size of the context memory induces a large area overhead in multi-context structures, which results in major restrictions on application complexity. This paper proposes a Predictable Context Cache (PCC) architecture to address the above context issues by buffering the context inside a CGRA. In this architecture, context is dynamically transferred into the CGRA. Utilizing a PCC significantly reduces the on-chip context memory and the complexity of the applications running on the CGRA is no longer restricted by the size of the on-chip context memory. Data preloading is the most frequently used approach to hide input data latency and speed up the data transmission process for the data bandwidth issue. Rather than fundamentally reducing the amount of input data, the transferred data and computations are processed in parallel. However, the data preloading method cannot work efficiently because data transmission becomes the critical path as the reconfigurable array scale increases. This paper also presents a Hierarchical Data Memory (HDM) architecture as a solution to the efficiency problem. In this architecture, high internal bandwidth is provided to buffer both reused input data and intermediate data. The HDM architecture relieves the external memory from the data transfer burden so that the performance is significantly improved. As a result of using PCC and HDM, experiments running mainstream video decoding programs achieved performance improvements of 13.57%-19.48% when there was a reasonable memory size. Therefore, 1080p@35.7fps for H.264 high profile video decoding can be achieved on PCC and HDM architecture when utilizing a 200 MHz working frequency. Further, the size of the on-chip context memory no longer restricted complex applications, which were efficiently executed on the PCC and HDM architecture.

Minimum Requirements for Accurate and Efficient Real-Time On-Chip Spike Sorting

PubMed Central

Navajas, Joaquin; Barsakcioglu, Deren Y.; Eftekhar, Amir; Jackson, Andrew; Constandinou, Timothy G.; Quiroga, Rodrigo Quian

2014-01-01

Background Extracellular recordings are performed by inserting electrodes in the brain, relaying the signals to external power-demanding devices, where spikes are detected and sorted in order to identify the firing activity of different putative neurons. A main caveat of these recordings is the necessity of wires passing through the scalp and skin in order to connect intracortical electrodes to external amplifiers. The aim of this paper is to evaluate the feasibility of an implantable platform (i.e. a chip) with the capability to wirelessly transmit the neural signals and perform real-time on-site spike sorting. New Method We computationally modelled a two-stage implementation for online, robust, and efficient spike sorting. In the first stage, spikes are detected on-chip and streamed to an external computer where mean templates are created and sent back to the chip. In the second stage, spikes are sorted in real-time through template matching. Results We evaluated this procedure using realistic simulations of extracellular recordings and describe a set of specifications that optimise performance while keeping to a minimum the signal requirements and the complexity of the calculations. Comparison with Existing Methods A key bottleneck for the development of long-term BMIs is to find an inexpensive method for real-time spike sorting. Here, we simulated a solution to this problem that uses both offline and online processing of the data. Conclusions Hardware implementations of this method therefore enable low-power long-term wireless transmission of multiple site extracellular recordings, with application to wireless BMIs or closed-loop stimulation designs. PMID:24769170

Real-time visual target tracking: two implementations of velocity-based smooth pursuit

NASA Astrophysics Data System (ADS)

Etienne-Cummings, Ralph; Longo, Paul; Van der Spiegel, Jan; Mueller, Paul

1995-06-01

Two systems for velocity-based visual target tracking are presented. The first two computational layers of both implementations are composed of VLSI photoreceptors (logarithmic compression) and edge detection (difference-of-Gaussians) arrays that mimic the outer-plexiform layer of mammalian retinas. The subsequent processing layers for measuring the target velocity and to realize smooth pursuit tracking are implemented in software and at the focal plane in the two versions, respectively. One implentation uses a hybrid of a PC and a silicon retina (39 X 38 pixels) operating at 333 frames/second. The software implementation of a real-time optical flow measurement algorithm is used to determine the target velocity, and a closed-loop control system zeroes the relative velocity of the target and retina. The second implementation is a single VLSI chip, which contains a linear array of photoreceptors, edge detectors and motion detectors at the focal plane. The closed-loop control system is also included on chip. This chip realizes all the computational properties of the hybrid system. The effects of background motion, target occlusion, and disappearance are studied as a function of retinal size and spatial distribution of the measured motion vectors (i.e. foveal/peripheral and diverging/converging measurement schemes). The hybrid system, which tested successfully, tracks targets moving as fast as 3 m/s at 1.3 meters from the camera and it can compensate for external arbitrary movements in its mounting platform. The single chip version, whose circuits tested successfully, can handle targets moving at 10 m/s.

Wide-field computational imaging of pathology slides using lens-free on-chip microscopy.

PubMed

Greenbaum, Alon; Zhang, Yibo; Feizi, Alborz; Chung, Ping-Luen; Luo, Wei; Kandukuri, Shivani R; Ozcan, Aydogan

2014-12-17

Optical examination of microscale features in pathology slides is one of the gold standards to diagnose disease. However, the use of conventional light microscopes is partially limited owing to their relatively high cost, bulkiness of lens-based optics, small field of view (FOV), and requirements for lateral scanning and three-dimensional (3D) focus adjustment. We illustrate the performance of a computational lens-free, holographic on-chip microscope that uses the transport-of-intensity equation, multi-height iterative phase retrieval, and rotational field transformations to perform wide-FOV imaging of pathology samples with comparable image quality to a traditional transmission lens-based microscope. The holographically reconstructed image can be digitally focused at any depth within the object FOV (after image capture) without the need for mechanical focus adjustment and is also digitally corrected for artifacts arising from uncontrolled tilting and height variations between the sample and sensor planes. Using this lens-free on-chip microscope, we successfully imaged invasive carcinoma cells within human breast sections, Papanicolaou smears revealing a high-grade squamous intraepithelial lesion, and sickle cell anemia blood smears over a FOV of 20.5 mm(2). The resulting wide-field lens-free images had sufficient image resolution and contrast for clinical evaluation, as demonstrated by a pathologist's blinded diagnosis of breast cancer tissue samples, achieving an overall accuracy of ~99%. By providing high-resolution images of large-area pathology samples with 3D digital focus adjustment, lens-free on-chip microscopy can be useful in resource-limited and point-of-care settings. Copyright © 2014, American Association for the Advancement of Science.

Initial Performance Results on IBM POWER6

NASA Technical Reports Server (NTRS)

Saini, Subbash; Talcott, Dale; Jespersen, Dennis; Djomehri, Jahed; Jin, Haoqiang; Mehrotra, Piysuh

2008-01-01

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Chips of Hope: Neuro-Electronic Hybrids for Brain Repair

NASA Astrophysics Data System (ADS)

Ben-Jacob, Eshel

2010-03-01

The field of Neuro-Electronic Hybrids kicked off 30 years ago when researchers in the US first tweaked the technology of recording and stimulation of networks of live neurons grown in a Petri dish and interfaced with a computer via an array of electrodes. Since then, many researchers have searched for ways to imprint in neural networks new ``memories" without erasing old ones. I will describe our new generation of Neuro-Electronic Hybrids and how we succeeded to turn them into the first learning Neurochips - memory and information processing chips made of live neurons. To imprint multiple memories in our new chip we used chemical stimulation at specific locations that were selected by analyzing the networks activity in real time according to our new information encoding principle. Currently we develop new-generation of neuro chips using special carbon nano tubes (CNT). These electrodes enable to engineer the networks topology and efficient electrical interfacing with the neurons. This advance bears the promise to pave the way for building a new experimental platform for testing new drugs and developing new methods for neural networks repair and regeneration. Looking into the future, the development brings us a step closer towards the dream of Brain Repair by implementable Neuro-Electronic hybrid chips.

Testing interconnected VLSI circuits in the Big Viterbi Decoder

NASA Technical Reports Server (NTRS)

Onyszchuk, I. M.

1991-01-01

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Numerical Simulation and Performance Optimization of a Magnetophoretic Bio-separation chip

NASA Astrophysics Data System (ADS)

Golozar, Matin; Darabi, Jeff; Molki, Majid

Separation of micro/nanoparticles is important in biomedicine and biotechnology. This research presents the modeling and optimization of a magnetophoretic bio-separation chip for the isolation of biomaterials, such as circulating tumor cells (CTCs) from the peripheral blood. The chip consists of a continuous flow through microfluidic channels that contains locally engineered magnetic field gradients. The high gradient magnetic field produced by the magnets is spatially non-uniform and gives rise to an attractive force on magnetic particles that move through the flow channel. The computational model takes into account the magnetic and fluidic forces as well as the effect of the volume fraction of particles on the continuous phase. The model is used to investigate the effect of two-way particle-fluid coupling on both the capture efficiency and the flow pattern in the separation chip. The results show that the microfluidic device has the capability of separating CTCs from their native environment. Additionally, a parametric study is performed to investigate the effects of the channel height, substrate thickness, magnetic bead size, bioparticle size, and the number of beads per cell on the cell separation performance.

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

ERIC Educational Resources Information Center

Muyskens, Mark A.

1997-01-01

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

78 FR 75362 - Notice of Issuance of Final Determination Concerning Docave Computer Software

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-11

... in whole or in part of materials from another country or instrumentality, it has been substantially... programming of a foreign PROM (Programmable Read-Only Memory chip) in the United States substantially...

75 FR 44989 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-30

... following respondents: NVIDIA Corporation of Santa Clara, California; Asustek Computer, Inc. of Taipei... exclusion order and cease- and-desist orders against respondents NVIDIA Corp.; Hewlett-Packard Co.; ASUS...

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

PubMed

Stojanović, Vladimir; Ram, Rajeev J; Popović, Milos; Lin, Sen; Moazeni, Sajjad; Wade, Mark; Sun, Chen; Alloatti, Luca; Atabaki, Amir; Pavanello, Fabio; Mehta, Nandish; Bhargava, Pavan

2018-05-14

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

A scalable silicon photonic chip-scale optical switch for high performance computing systems.

PubMed

Yu, Runxiang; Cheung, Stanley; Li, Yuliang; Okamoto, Katsunari; Proietti, Roberto; Yin, Yawei; Yoo, S J B

2013-12-30

This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (>90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-of-concept routing functions on an 8 × 8 prototype fabricated using foundry services provided by OpSIS-IME.

Research on numerical control system based on S3C2410 and MCX314AL

NASA Astrophysics Data System (ADS)

Ren, Qiang; Jiang, Tingbiao

2008-10-01

With the rapid development of micro-computer technology, embedded system, CNC technology and integrated circuits, numerical control system with powerful functions can be realized by several high-speed CPU chips and RISC (Reduced Instruction Set Computing) chips which have small size and strong stability. In addition, the real-time operating system also makes the attainment of embedded system possible. Developing the NC system based on embedded technology can overcome some shortcomings of common PC-based CNC system, such as the waste of resources, low control precision, low frequency and low integration. This paper discusses a hardware platform of ENC (Embedded Numerical Control) system based on embedded processor chip ARM (Advanced RISC Machines)-S3C2410 and DSP (Digital Signal Processor)-MCX314AL and introduces the process of developing ENC system software. Finally write the MCX314AL's driver under the embedded Linux operating system. The embedded Linux operating system can deal with multitask well moreover satisfy the real-time and reliability of movement control. NC system has the advantages of best using resources and compact system with embedded technology. It provides a wealth of functions and superior performance with a lower cost. It can be sure that ENC is the direction of the future development.

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

PubMed Central

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; del Giudice, Paolo

2015-01-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases. PMID:26463272

The next generation of neural network chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Beiu, V.

There have been many national and international neural networks research initiatives: USA (DARPA, NIBS), Canada (IRIS), Japan (HFSP) and Europe (BRAIN, GALA TEA, NERVES, ELENE NERVES 2) -- just to mention a few. Recent developments in the field of neural networks, cognitive science, bioengineering and electrical engineering have made it possible to understand more about the functioning of large ensembles of identical processing elements. There are more research papers than ever proposing solutions and hardware implementations are by no means an exception. Two fields (computing and neuroscience) are interacting in ways nobody could imagine just several years ago, and --more » with the advent of new technologies -- researchers are focusing on trying to copy the Brain. Such an exciting confluence may quite shortly lead to revolutionary new computers and it is the aim of this invited session to bring to light some of the challenging research aspects dealing with the hardware realizability of future intelligent chips. Present-day (conventional) technology is (still) mostly digital and, thus, occupies wider areas and consumes much more power than the solutions envisaged. The innovative algorithmic and architectural ideals should represent important breakthroughs, paving the way towards making neural network chips available to the industry at competitive prices, in relatively small packages and consuming a fraction of the power required by equivalent digital solutions.« less

Monitoring Temperature and Fan Speed Using Ganglia and Winbond Chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCaffrey, Cattie; /SLAC

2006-09-27

Effective monitoring is essential to keep a large group of machines, like the ones at Stanford Linear Accelerator Center (SLAC), up and running. SLAC currently uses Ganglia Monitoring System to observe about 2000 machines, analyzing metrics like CPU usage and I/O rate. However, metrics essential to machine hardware health, such as temperature and fan speed, are not being monitored. Many machines have a Winbond w83782d chip which monitors three temperatures, two of which come from dual CPUs, and returns the information when the sensor command is invoked. Ganglia also provides a feature, gmetric, that allows the users to monitor theirmore » own metrics and incorporate them into the monitoring system. The programming language Perl is chosen to implement a script that invokes the sensors command, extracts the temperature and fan speed information, and calls gmetric with the appropriate arguments. Two machines were used to test the script; the two CPUs on each machine run at about 65 Celsius, which is well within the operating temperature range (The maximum safe temperature range is 77-82 Celsius for the Pentium III processors being used). Installing the script on all machines with a Winbond w83782d chip allows the SLAC Scientific Computing and Computing Services group (SCCS) to better evaluate current cooling methods.« less

Photonic band gap materials: towards an all-optical transistor

NASA Astrophysics Data System (ADS)

Florescu, Marian

2002-05-01

The transmission of information as optical signals encoded on light waves traveling through optical fibers and optical networks is increasingly moving to shorter and shorter distance scales. In the near future, optical networking is poised to supersede conventional transmission over electric wires and electronic networks for computer-to-computer communications, chip-to-chip communications, and even on-chip communications. The ever-increasing demand for faster and more reliable devices to process the optical signals offers new opportunities in developing all-optical signal processing systems (systems in which one optical signal controls another, thereby adding "intelligence" to the optical networks). All-optical switches, two-state and many-state all-optical memories, all-optical limiters, all-optical discriminators and all-optical transistors are only a few of the many devices proposed during the last two decades. The "all-optical" label is commonly used to distinguish the devices that do not involve dissipative electronic transport and require essentially no electrical communication of information. The all-optical transistor action was first observed in the context of optical bistability [1] and consists in a strong differential gain regime, in which, for small variations in the input intensity, the output intensity has a very strong variation. This analog operation is for all-optical input what transistor action is for electrical inputs.

Stream Processors

NASA Astrophysics Data System (ADS)

Erez, Mattan; Dally, William J.

Stream processors, like other multi core architectures partition their functional units and storage into multiple processing elements. In contrast to typical architectures, which contain symmetric general-purpose cores and a cache hierarchy, stream processors have a significantly leaner design. Stream processors are specifically designed for the stream execution model, in which applications have large amounts of explicit parallel computation, structured and predictable control, and memory accesses that can be performed at a coarse granularity. Applications in the streaming model are expressed in a gather-compute-scatter form, yielding programs with explicit control over transferring data to and from on-chip memory. Relying on these characteristics, which are common to many media processing and scientific computing applications, stream architectures redefine the boundary between software and hardware responsibilities with software bearing much of the complexity required to manage concurrency, locality, and latency tolerance. Thus, stream processors have minimal control consisting of fetching medium- and coarse-grained instructions and executing them directly on the many ALUs. Moreover, the on-chip storage hierarchy of stream processors is under explicit software control, as is all communication, eliminating the need for complex reactive hardware mechanisms.

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

Sensitive spin detection using an on-chip SQUID-waveguide resonator

NASA Astrophysics Data System (ADS)

Yue, G.; Chen, L.; Barreda, J.; Bevara, V.; Hu, L.; Wu, L.; Wang, Z.; Andrei, P.; Bertaina, S.; Chiorescu, I.

2017-11-01

Precise detection of spin resonance is of paramount importance to achieve coherent spin control in quantum computing. We present a setup for spin resonance measurements, which uses a dc-SQUID flux detector coupled to an antenna from a coplanar waveguide. The SQUID and the waveguide are fabricated from a 20 nm Nb thin film, allowing high magnetic field operation with the field applied parallel to the chip. We observe a resonance signal between the first and third excited states of Gd spins S = 7/2 in a CaWO4 crystal, relevant for state control in multi-level systems.

KSC-07pd1241

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, Orbital Science technicians verify that a computer chip is securely bonded to a side brace on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/George Shelton

KSC-07pd1240

NASA Image and Video Library

2007-05-17

KENNEDY SPACE CENTER, FLA. -- In the Astrotech Space Operations facility, a computer chip is bonded to a side brace on the Dawn spacecraft. The silicon chip holds the names of more than 360,000 space enthusiasts worldwide who signed up to participate in a virtual voyage to the asteroid belt and is about the size of an American five-cent coin. Dawn's mission is to explore two of the asteroid belt's most intriguing and dissimilar occupants: asteroid Vesta and the dwarf planet Ceres. Dawn is scheduled to launch June 30 from Launch Complex 17-B. Photo credit: NASA/Jim Grossmann

On the Implications of Neuroscience Research for Science Teaching and Learning: Are There Any?

ERIC Educational Resources Information Center

Lawson, Anton E.

2006-01-01

What, if anything, do teachers need to know about how the brain works to improve teaching and learning? After all, a plumber needs to know how to stop leaks--not the molecular structure of water. And one can learn how to use a computer without knowing how a computer chip works. Likewise, teachers need to know how to help students develop…

A Serial Bus Architecture for Parallel Processing Systems

DTIC Science & Technology

1986-09-01

pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more communication capacity is needed, pushing...chip. The wider the communication path the more pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more...13 2. A Suitable Architecture Sought 14 II. OPTIMUM ARCHITECTURE OF LARGE INTEGRATED A. PARTIONING SILICON FOR MAXIMUM 1? 1. Transistor

Towards energy-efficient photonic interconnects

NASA Astrophysics Data System (ADS)

Demir, Yigit; Hardavellas, Nikos

2015-03-01

Silicon photonics have emerged as a promising solution to meet the growing demand for high-bandwidth, low-latency, and energy-efficient on-chip and off-chip communication in many-core processors. However, current silicon-photonic interconnect designs for many-core processors waste a significant amount of power because (a) lasers are always on, even during periods of interconnect inactivity, and (b) microring resonators employ heaters which consume a significant amount of power just to overcome thermal variations and maintain communication on the photonic links, especially in a 3D-stacked design. The problem of high laser power consumption is particularly important as lasers typically have very low energy efficiency, and photonic interconnects often remain underutilized both in scientific computing (compute-intensive execution phases underutilize the interconnect), and in server computing (servers in Google-scale datacenters have a typical utilization of less than 30%). We address the high laser power consumption by proposing EcoLaser+, which is a laser control scheme that saves energy by predicting the interconnect activity and opportunistically turning the on-chip laser off when possible, and also by scaling the width of the communication link based on a runtime prediction of the expected message length. Our laser control scheme can save up to 62 - 92% of the laser energy, and improve the energy efficiency of a manycore processor with negligible performance penalty. We address the high trimming (heating) power consumption of the microrings by proposing insulation methods that reduce the impact of localized heating induced by highly-active components on the 3D-stacked logic die.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Guided self-assembly of magnetic beads for biomedical applications

NASA Astrophysics Data System (ADS)

Gusenbauer, Markus; Nguyen, Ha; Reichel, Franz; Exl, Lukas; Bance, Simon; Fischbacher, Johann; Özelt, Harald; Kovacs, Alexander; Brandl, Martin; Schrefl, Thomas

2014-02-01

Micromagnetic beads are widely used in biomedical applications for cell separation, drug delivery, and hyperthermia cancer treatment. Here we propose to use self-organized magnetic bead structures which accumulate on fixed magnetic seeding points to isolate circulating tumor cells. The analysis of circulating tumor cells is an emerging tool for cancer biology research and clinical cancer management including the detection, diagnosis and monitoring of cancer. Microfluidic chips for isolating circulating tumor cells use either affinity, size or density capturing methods. We combine multiphysics simulation techniques to understand the microscopic behavior of magnetic beads interacting with soft magnetic accumulation points used in lab-on-chip technologies. Our proposed chip technology offers the possibility to combine affinity and size capturing with special antibody-coated bead arrangements using a magnetic gradient field created by Neodymium Iron Boron permanent magnets. The multiscale simulation environment combines magnetic field computation, fluid dynamics and discrete particle dynamics.

Modeling selective attention using a neuromorphic analog VLSI device.

PubMed

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Shrink-film microfluidic education modules: Complete devices within minutes.

PubMed

Nguyen, Diep; McLane, Jolie; Lew, Valerie; Pegan, Jonathan; Khine, Michelle

2011-06-01

As advances in microfluidics continue to make contributions to diagnostics and life sciences, broader awareness of this expanding field becomes necessary. By leveraging low-cost microfabrication techniques that require no capital equipment or infrastructure, simple, accessible, and effective educational modules can be made available for a broad range of educational needs from middle school demonstrations to college laboratory classes. These modules demonstrate key microfluidic concepts such as diffusion and separation as well as "laboratory on-chip" applications including chemical reactions and biological assays. These modules are intended to provide an interdisciplinary hands-on experience, including chip design, fabrication of functional devices, and experiments at the microscale. Consequently, students will be able to conceptualize physics at small scales, gain experience in computer-aided design and microfabrication, and perform experiments-all in the context of addressing real-world challenges by making their own lab-on-chip devices.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

DOE and JAEA Field Trial of the Single Chip Shift Register (SCSR)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matthew R.

2016-03-23

Los Alamos National Laboratories (LANL) has recently developed a new data acquisition system for multiplicity analysis of neutron detector pulse streams. This new technology, the Single Chip Shift Register (SCSR), places the entire data acquisition system along with the communications hardware onto a single chip. This greatly simplifies the instrument and reduces the size. The SCSR is designed to be mounted into the neutron detector head alongside the instrument amplifiers. The user’s computer connects via USB directly to the neutron detector eliminating the external data acquisition electronics entirely. JAEA, through the INSEP program, asked LANL to demonstrate the functionality ofmore » the SCSR in Tokai using the JAEA Epithermal Neutron Multiplicity Counter, ENMC. In late September of 2015 LANL traveled to Tokai to install, demonstrate and uninstall the SCSR in the ENMC. This report documents the results of that field trial.« less

Computer Simulation of Replaceable Many Sider Plates (RMSP) with Enhanced Chip-Breaking Characteristics

NASA Astrophysics Data System (ADS)

Korchuganova, M.; Syrbakov, A.; Chernysheva, T.; Ivanov, G.; Gnedasch, E.

2016-08-01

Out of all common chip curling methods, a special tool face form has become the most widespread which is developed either by means of grinding or by means of profile pressing in the production process of RMSP. Currently, over 15 large tool manufacturers produce tools using instrument materials of over 500 brands. To this, we must add a large variety of tool face geometries, which purpose includes the control over form and dimensions of the chip. Taking into account all the many processed materials, specific tasks of the process planner, requirements to the quality of manufactured products, all this makes the choice of a proper tool which can perform the processing in the most effective way significantly harder. Over recent years, the nomenclature of RMSP for lathe tools with mechanical mounting has been considerably broadened by means of diversification of their faces

A deterministic guide for material and mode dependence of on-chip electro-optic modulator performance

NASA Astrophysics Data System (ADS)

Amin, Rubab; Suer, Can; Ma, Zhizhen; Sarpkaya, Ibrahim; Khurgin, Jacob B.; Agarwal, Ritesh; Sorger, Volker J.

2017-10-01

Electro-optic modulation is a key function in optical data communication and possible future optical computing engines. The performance of modulators intricately depends on the interaction between the actively modulated material and the propagating waveguide mode. While high-performing modulators were demonstrated before, the approaches were taken as ad-hoc. Here we show the first systematic investigation to incorporate a holistic analysis for high-performance and ultra-compact electro-optic modulators on-chip. We show that intricate interplay between active modulation material and optical mode plays a key role in the device operation. Based on physical tradeoffs such as index modulation, loss, optical confinement factors and slow-light effects, we find that bias-material-mode regions exist where high phase modulation and high loss (absorption) modulation is found. This work paves the way for a holistic design rule of electro-optic modulators for on-chip integration.

On-Chip High-Finesse Fabry-Perot Microcavities for Optical Sensing and Quantum Information.

PubMed

Bitarafan, Mohammad H; DeCorby, Ray G

2017-07-31

For applications in sensing and cavity-based quantum computing and metrology, open-access Fabry-Perot cavities-with an air or vacuum gap between a pair of high reflectance mirrors-offer important advantages compared to other types of microcavities. For example, they are inherently tunable using MEMS-based actuation strategies, and they enable atomic emitters or target analytes to be located at high field regions of the optical mode. Integration of curved-mirror Fabry-Perot cavities on chips containing electronic, optoelectronic, and optomechanical elements is a topic of emerging importance. Micro-fabrication techniques can be used to create mirrors with small radius-of-curvature, which is a prerequisite for cavities to support stable, small-volume modes. We review recent progress towards chip-based implementation of such cavities, and highlight their potential to address applications in sensing and cavity quantum electrodynamics.

On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

PubMed

Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

2017-07-12

Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

A Streaming Language Implementation of the Discontinuous Galerkin Method

NASA Technical Reports Server (NTRS)

Barth, Timothy; Knight, Timothy

2005-01-01

We present a Brook streaming language implementation of the 3-D discontinuous Galerkin method for compressible fluid flow on tetrahedral meshes. Efficient implementation of the discontinuous Galerkin method using the streaming model of computation introduces several algorithmic design challenges. Using a cycle-accurate simulator, performance characteristics have been obtained for the Stanford Merrimac stream processor. The current Merrimac design achieves 128 Gflops per chip and the desktop board is populated with 16 chips yielding a peak performance of 2 Teraflops. Total parts cost for the desktop board is less than $20K. Current cycle-accurate simulations for discretizations of the 3-D compressible flow equations yield approximately 40-50% of the peak performance of the Merrimac streaming processor chip. Ongoing work includes the assessment of the performance of the same algorithm on the 2 Teraflop desktop board with a target goal of achieving 1 Teraflop performance.

On-Chip High-Finesse Fabry-Perot Microcavities for Optical Sensing and Quantum Information

PubMed Central

Bitarafan, Mohammad H.; DeCorby, Ray G.

2017-01-01

For applications in sensing and cavity-based quantum computing and metrology, open-access Fabry-Perot cavities—with an air or vacuum gap between a pair of high reflectance mirrors—offer important advantages compared to other types of microcavities. For example, they are inherently tunable using MEMS-based actuation strategies, and they enable atomic emitters or target analytes to be located at high field regions of the optical mode. Integration of curved-mirror Fabry-Perot cavities on chips containing electronic, optoelectronic, and optomechanical elements is a topic of emerging importance. Micro-fabrication techniques can be used to create mirrors with small radius-of-curvature, which is a prerequisite for cavities to support stable, small-volume modes. We review recent progress towards chip-based implementation of such cavities, and highlight their potential to address applications in sensing and cavity quantum electrodynamics. PMID:28758967

Storage Media for Microcomputers.

ERIC Educational Resources Information Center

Trautman, Rodes

1983-01-01

Reviews computer storage devices designed to provide additional memory for microcomputers--chips, floppy disks, hard disks, optical disks--and describes how secondary storage is used (file transfer, formatting, ingredients of incompatibility); disk/controller/software triplet; magnetic tape backup; storage volatility; disk emulator; and…

Idea Bank.

ERIC Educational Resources Information Center

Buck, Cheryl A.; And Others

1988-01-01

Introduces 12 activities for teaching science. Includes one way to begin the school year, peristalsis demonstration, candy-coated metrics, 3-D constellations, 35-mm astrophotography, create an alien organism, jet propulsion, computer programs for pendulum calculations, plant versus animal, chocolate chip petroleum, paper rockets, and…

Soul on Silicon.

ERIC Educational Resources Information Center

Kurzweil, Raymond C.

1994-01-01

Summarizes recent advances in computer simulation and "reverse engineering" technologies, highlighting the Human Genome Project to scan the human genetic code; artificial retina chips to copy the human retina's neural organization; high-speed, high-resolution Magnetic Resonance Imaging scanners; and the virtual book. Discusses…

Mathematics, Information, and Life Sciences

DTIC Science & Technology

2012-03-05

INS • Chip -scale atomic clocks • Ad hoc networks • Polymorphic networks • Agile networks • Laser communications • Frequency-agile RF systems...FY12 BAA Bionavigation (Bio) Neuromorphic Computing (Human) Multi-scale Modeling (Math) Foundations of Information Systems (Info) BRI

75 FR 32803 - Notice of Issuance of Final Determination Concerning a GTX Mobile+ Hand Held Computer

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-09

... Programmable Read-Only Memory (``PROM'') chip, substantially transformed the PROM into a U.S. article. The... parts (such as various connectors and an Electronically Erasable Programmable Read Only Memory, or...

Sensitive Spin Detection Using An On-Chip Squid-Waveguide Resonator

NASA Astrophysics Data System (ADS)

Yue, Guang

Quantum computing gives novel way of computing using quantum mechanics, which furthers human knowledge and has exciting applications. Quantum systems with diluted spins such as rare earth ions hosted in single crystal, molecule-based magnets etc. are promising qubits candidates to form the basis of a quantum computer. High sensitivity measurement and coherent control of these spin systems are crucial for their practical usage as qubits. The micro-SQUID (direct-current micrometer-sized Superconducting QUantum Interference Device) is capable to measure magnetization of spin system with high sensitivity. For example, the micro-SQUID technique can measure magnetic moments as small as several thousand muB as shown by the study of [W. Wernsdorfer, Supercond. Sci. Technol. 22, 064013 (2009)]. Here we develop a novel on-chip setup that combines the micro-SQUID sensitivity with microwave excitation. Such setup can be used for electron spin resonance measurements or coherent control of spins utilizing the high sensitivity of micro-SQUID for signal detection. To build the setup, we studied the fabrication process of the micro-SQUID, which is made of weak-linked Josephson junctions. The SQUID as a detector is integrated on the same chip with a shorted coplanar waveguide, so that the microwave pulses can be applied through the waveguide to excite the sample for resonance measurements. The whole device is plasma etched from a thin (˜ 20nm) niobium film, so that the SQUID can work at in large in-plane magnetic fields of several tesla. In addition, computer simulations are done to find the best design of the waveguide such that the microwave excitation field is sufficiently strong and uniformly applied to the sample. The magnetization curve of Mn12 molecule-based magnet sample is measured to prove the proper working of the micro-SQUID. Electron spin resonance measurement is done on the setup for gadolinium ions diluted in a CaWO4 single crystal. The measurement shows clear evidence of the resonance signal from the 1st transition of the gadolinium ions' energy levels, which shows the setup is successfully built. Due to the high sensitivity of micro-SQUID and the ability to concentrate microwave energy in small areas of the chip, this setup can detect signals from a small number of spins (107) in a small volume (several mum 3).

Fish and chips: implementation of a neural network model into computer chips to maximize swimming efficiency in autonomous underwater vehicles.

PubMed

Blake, R W; Ng, H; Chan, K H S; Li, J

2008-09-01

Recent developments in the design and propulsion of biomimetic autonomous underwater vehicles (AUVs) have focused on boxfish as models (e.g. Deng and Avadhanula 2005 Biomimetic micro underwater vehicle with oscillating fin propulsion: system design and force measurement Proc. 2005 IEEE Int. Conf. Robot. Auto. (Barcelona, Spain) pp 3312-7). Whilst such vehicles have many potential advantages in operating in complex environments (e.g. high manoeuvrability and stability), limited battery life and payload capacity are likely functional disadvantages. Boxfish employ undulatory median and paired fins during routine swimming which are characterized by high hydromechanical Froude efficiencies (approximately 0.9) at low forward speeds. Current boxfish-inspired vehicles are propelled by a low aspect ratio, 'plate-like' caudal fin (ostraciiform tail) which can be shown to operate at a relatively low maximum Froude efficiency (approximately 0.5) and is mainly employed as a rudder for steering and in rapid swimming bouts (e.g. escape responses). Given this and the fact that bioinspired engineering designs are not obligated to wholly duplicate a biological model, computer chips were developed using a multilayer perception neural network model of undulatory fin propulsion in the knifefish Xenomystus nigri that would potentially allow an AUV to achieve high optimum values of propulsive efficiency at any given forward velocity, giving a minimum energy drain on the battery. We envisage that externally monitored information on flow velocity (sensory system) would be conveyed to the chips residing in the vehicle's control unit, which in turn would signal the locomotor unit to adopt kinematics (e.g. fin frequency, amplitude) associated with optimal propulsion efficiency. Power savings could protract vehicle operational life and/or provide more power to other functions (e.g. communications).

Generating single microwave photons in a circuit.

PubMed

Houck, A A; Schuster, D I; Gambetta, J M; Schreier, J A; Johnson, B R; Chow, J M; Frunzio, L; Majer, J; Devoret, M H; Girvin, S M; Schoelkopf, R J

2007-09-20

Microwaves have widespread use in classical communication technologies, from long-distance broadcasts to short-distance signals within a computer chip. Like all forms of light, microwaves, even those guided by the wires of an integrated circuit, consist of discrete photons. To enable quantum communication between distant parts of a quantum computer, the signals must also be quantum, consisting of single photons, for example. However, conventional sources can generate only classical light, not single photons. One way to realize a single-photon source is to collect the fluorescence of a single atom. Early experiments measured the quantum nature of continuous radiation, and further advances allowed triggered sources of photons on demand. To allow efficient photon collection, emitters are typically placed inside optical or microwave cavities, but these sources are difficult to employ for quantum communication on wires within an integrated circuit. Here we demonstrate an on-chip, on-demand single-photon source, where the microwave photons are injected into a wire with high efficiency and spectral purity. This is accomplished in a circuit quantum electrodynamics architecture, with a microwave transmission line cavity that enhances the spontaneous emission of a single superconducting qubit. When the qubit spontaneously emits, the generated photon acts as a flying qubit, transmitting the quantum information across a chip. We perform tomography of both the qubit and the emitted photons, clearly showing that both the quantum phase and amplitude are transferred during the emission. Both the average power and voltage of the photon source are characterized to verify performance of the system. This single-photon source is an important addition to a rapidly growing toolbox for quantum optics on a chip.

Biomolecular computing systems: principles, progress and potential.

PubMed

Benenson, Yaakov

2012-06-12

The task of information processing, or computation, can be performed by natural and man-made 'devices'. Man-made computers are made from silicon chips, whereas natural 'computers', such as the brain, use cells and molecules. Computation also occurs on a much smaller scale in regulatory and signalling pathways in individual cells and even within single biomolecules. Indeed, much of what we recognize as life results from the remarkable capacity of biological building blocks to compute in highly sophisticated ways. Rational design and engineering of biological computing systems can greatly enhance our ability to study and to control biological systems. Potential applications include tissue engineering and regeneration and medical treatments. This Review introduces key concepts and discusses recent progress that has been made in biomolecular computing.

WAT-on-a-chip: A physiologically relevant microfluidic system incorporating white adipose tissue

PubMed Central

Loskill, Peter; Sezhian, Thiagarajan; Tharp, Kevin; Lee-Montiel, Felipe T.; Jeeawoody, Shaheen; Reese, Willie Mae; Zushin, Pete-James H.; Stahl, Andreas; Healy, Kevin E.

2017-01-01

Organ-on-a-chip systems possess a promising future as drug screening assays and as testbeds for disease modeling in the context of both single-organ systems and multi-organ-chips. Although it comprises approximately one fourth of the body weight of a healthy human, an organ frequently overlooked in this context is white adipose tissue (WAT). WAT-on-a-chip systems are required to create safety profiles of a large number of drugs due to their interactions with adipose tissue and other organs via paracrine signals, fatty acid release, and drug levels through sequestration. We report a WAT-on-a-chip system with a footprint of less than 1 mm2 consisting of a separate media channel and WAT chamber connected via small micropores. Analogous to the in vivo blood circulation, convective transport is thereby confined to the vasculature-like structures and the tissues protected from shear stresses. Numerical and analytical modeling revealed that the flow rates in the WAT chambers are less than 1/100 of the input flow rate. Using optimized injection parameters, we were able to inject pre-adipocytes, which subsequently formed adipose tissue featuring fully functional lipid metabolism. The physiologically relevant microfluidic environment of the WAT-chip supported long term culture of the functional adipose tissue for more than two weeks. Due to its physiological, highly controlled, and computationally predictable character, the system has the potential to be a powerful tool for the study of adipose tissue associated diseases such as obesity and type 2 diabetes. PMID:28418430

GeoChip 3.0 as a high-thoughput tool for analyzing microbial community composition, structure, and functional activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Z.; Deng, Y.; Van Nostrand, J.D.

A new generation of functional gene arrays (FGAs; GeoChip 3.0) has been developed, with {approx}28,000 probes covering approximately 57,000 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance and organic contaminant degradation. GeoChip 3.0 also has several other distinct features, such as a common oligo reference standard (CORS) for data normalization and comparison, a software package for data management and future updating and the gyrB gene for phylogenetic analysis. Computational evaluation of probe specificity indicated that all designed probes would have a high specificity to their corresponding targets.more » Experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036-0.025% false-positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which showed that the structure, composition and potential activity of soil microbial communities significantly changed with the plant species diversity. As expected, GeoChip 3.0 is a high-throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning.« less

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

NASA Technical Reports Server (NTRS)

Bar-Cohen, Avram; Robinson, Franklin L.; Deisenroth, David C.

2018-01-01

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

QCDOC: A 10-teraflops scale computer for lattice QCD

NASA Astrophysics Data System (ADS)

Chen, D.; Christ, N. H.; Cristian, C.; Dong, Z.; Gara, A.; Garg, K.; Joo, B.; Kim, C.; Levkova, L.; Liao, X.; Mawhinney, R. D.; Ohta, S.; Wettig, T.

2001-03-01

The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from "QCD On a Chip".

Neuromorphic computing with nanoscale spintronic oscillators.

PubMed

Torrejon, Jacob; Riou, Mathieu; Araujo, Flavio Abreu; Tsunegi, Sumito; Khalsa, Guru; Querlioz, Damien; Bortolotti, Paolo; Cros, Vincent; Yakushiji, Kay; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Stiles, Mark D; Grollier, Julie

2017-07-26

Neurons in the brain behave as nonlinear oscillators, which develop rhythmic activity and interact to process information. Taking inspiration from this behaviour to realize high-density, low-power neuromorphic computing will require very large numbers of nanoscale nonlinear oscillators. A simple estimation indicates that to fit 10 8 oscillators organized in a two-dimensional array inside a chip the size of a thumb, the lateral dimension of each oscillator must be smaller than one micrometre. However, nanoscale devices tend to be noisy and to lack the stability that is required to process data in a reliable way. For this reason, despite multiple theoretical proposals and several candidates, including memristive and superconducting oscillators, a proof of concept of neuromorphic computing using nanoscale oscillators has yet to be demonstrated. Here we show experimentally that a nanoscale spintronic oscillator (a magnetic tunnel junction) can be used to achieve spoken-digit recognition with an accuracy similar to that of state-of-the-art neural networks. We also determine the regime of magnetization dynamics that leads to the greatest performance. These results, combined with the ability of the spintronic oscillators to interact with each other, and their long lifetime and low energy consumption, open up a path to fast, parallel, on-chip computation based on networks of oscillators.

On-chip phase-change photonic memory and computing

NASA Astrophysics Data System (ADS)

Cheng, Zengguang; Ríos, Carlos; Youngblood, Nathan; Wright, C. David; Pernice, Wolfram H. P.; Bhaskaran, Harish

2017-08-01

The use of photonics in computing is a hot topic of interest, driven by the need for ever-increasing speed along with reduced power consumption. In existing computing architectures, photonic data storage would dramatically improve the performance by reducing latencies associated with electrical memories. At the same time, the rise of `big data' and `deep learning' is driving the quest for non-von Neumann and brain-inspired computing paradigms. To succeed in both aspects, we have demonstrated non-volatile multi-level photonic memory avoiding the von Neumann bottleneck in the existing computing paradigm and a photonic synapse resembling the biological synapses for brain-inspired computing using phase-change materials (Ge2Sb2Te5).

Implantation of Autologous Cartilage Chips Improves Cartilage Repair Tissue Quality in Osteochondral Defects: A Study in Göttingen Minipigs.

PubMed

Christensen, Bjørn Borsøe; Foldager, Casper Bindzus; Olesen, Morten Lykke; Hede, Kris Chadwick; Lind, Martin

2016-06-01

Osteochondral injuries have poor endogenous healing potential, and no standard treatment has been established. The use of combined layered autologous bone and cartilage chips for treatment of osteochondral defects has shown promising short-term clinical results. This study aimed to investigate the role of cartilage chips by comparing combined layered autologous bone and cartilage chips with autologous bone implantation alone in a Göttingen minipig model. The hypothesis was that the presence of cartilage chips would improve the quality of the repair tissue. Controlled laboratory study. Twelve Göttingen minipigs received 2 osteochondral defects in each knee. The defects were randomized to autologous bone graft (ABG) combined with autologous cartilage chips (autologous dual-tissue transplantation [ADTT]) or ABG alone. Six animals were euthanized at 6 months and 6 animals were euthanized at 12 months. Follow-up evaluation consisted of histomorphometry, immunohistochemistry, semiquantitative scoring (International Cartilage Repair Society II), and computed tomography. There was significantly more hyaline cartilage in the ADTT group (25.8%) compared with the ABG group (12.8%) at 6 months after treatment. At 12 months, the fraction of hyaline cartilage in the ABG group had significantly decreased to 4.8%, whereas the fraction of hyaline cartilage in the ADTT group was unchanged (20.1%). At 6 and 12 months, there was significantly more fibrocartilage in the ADTT group (44% and 60.8%) compared with the ABG group (24.5% and 41%). The fraction of fibrous tissue was significantly lower in the ADTT group compared with the ABG group at both 6 and 12 months. The implanted cartilage chips stained >75% positive for collagen type 4 and laminin at both 6 and 12 months. Significant differences were found in a number of International Cartilage Repair Society II subcategories. The volume of the remaining bone defect significantly decreased from 6 to 12 months in both treatment groups; however, no difference in volume was found between the groups at either 6 or 12 months. The presence of cartilage chips in an osteochondral defect facilitated the formation of fibrocartilage as opposed to fibrous tissue at both 6 and 12 months posttreatment. The implanted chips were present in the defect and viable after 12 months. This study substantiates the chondrogenic role of cartilage chips in osteochondral defects. © 2016 The Author(s).

Adaptive WTA with an analog VLSI neuromorphic learning chip.

PubMed

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

Feasibility study, software design, layout and simulation of a two-dimensional fast Fourier transform machine for use in optical array interferometry

NASA Technical Reports Server (NTRS)

Boriakoff, Valentin; Chen, Wei

1990-01-01

The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Multi-user quantum key distribution with entangled photons from an AlGaAs chip

NASA Astrophysics Data System (ADS)

Autebert, C.; Trapateau, J.; Orieux, A.; Lemaître, A.; Gomez-Carbonell, C.; Diamanti, E.; Zaquine, I.; Ducci, S.

2016-12-01

In view of real-world applications of quantum information technologies, the combination of miniature quantum resources with existing fibre networks is a crucial issue. Among such resources, on-chip entangled photon sources play a central role for applications spanning quantum communications, computing and metrology. Here, we use a semiconductor source of entangled photons operating at room temperature in conjunction with standard telecom components to demonstrate multi-user quantum key distribution, a core protocol for securing communications in quantum networks. The source consists of an AlGaAs chip-emitting polarisation entangled photon pairs over a large bandwidth in the main telecom band around 1550 nm without the use of any off-chip compensation or interferometric scheme; the photon pairs are directly launched into a dense wavelength division multiplexer (DWDM) and secret keys are distributed between several pairs of users communicating through different channels. We achieve a visibility measured after the DWDM of 87% and show long-distance key distribution using a 50-km standard telecom fibre link between two network users. These results illustrate a promising route to practical, resource-efficient implementations adapted to quantum network infrastructures.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

High-Tech Conservation: Information-Age Tools Have Revolutionized the Work of Ecologists.

ERIC Educational Resources Information Center

Chiles, James R.

1992-01-01

Describes a new direction for conservation efforts influenced by the advance of the information age and the introduction of many technologically sophisticated information collecting devices. Devices include microscopic computer chips, miniature electronic components, and Earth-observation satellite. (MCO)

Old PCs: Upgrade or Abandon?

ERIC Educational Resources Information Center

Perez, Ernest

1997-01-01

Examines the practical realities of upgrading Intel personal computers in libraries, considering budgets and technical personnel availability. Highlights include adding RAM; putting in faster processor chips, including clock multipliers; new hard disks; CD-ROM speed; motherboards and interface cards; cost limits and economic factors; and…

Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light.

PubMed

Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltan; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

2017-03-09

Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm 2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light

NASA Astrophysics Data System (ADS)

Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltan; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

2017-03-01

Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

Computer Simulations: A Tool to Predict Experimental Parameters with Cold Atoms

DTIC Science & Technology

2013-04-01

Department of the Army position unless so designated by other authorized documents. Citation of manufacturer’s or trade names does not constitute an...specifically designed to work with cold atom systems and atom chips, and is already able to compute their key properties. We simulate our experimental...also allows one to choose different physics and define the interdependencies between them. It is not specifically designed for cold atom systems or

Feature extraction using extrema sampling of discrete derivatives for spike sorting in implantable upper-limb neural prostheses.

PubMed

Zamani, Majid; Demosthenous, Andreas

2014-07-01

Next generation neural interfaces for upper-limb (and other) prostheses aim to develop implantable interfaces for one or more nerves, each interface having many neural signal channels that work reliably in the stump without harming the nerves. To achieve real-time multi-channel processing it is important to integrate spike sorting on-chip to overcome limitations in transmission bandwidth. This requires computationally efficient algorithms for feature extraction and clustering suitable for low-power hardware implementation. This paper describes a new feature extraction method for real-time spike sorting based on extrema analysis (namely positive peaks and negative peaks) of spike shapes and their discrete derivatives at different frequency bands. Employing simulation across different datasets, the accuracy and computational complexity of the proposed method are assessed and compared with other methods. The average classification accuracy of the proposed method in conjunction with online sorting (O-Sort) is 91.6%, outperforming all the other methods tested with the O-Sort clustering algorithm. The proposed method offers a better tradeoff between classification error and computational complexity, making it a particularly strong choice for on-chip spike sorting.

Novel Ruggedized Packaging Technology for VCSELs

DTIC Science & Technology

2017-03-01

Novel Ruggedized Packaging Technology for VCSELs Charlie Kuznia ckuznia@ultracomm-inc.com Ultra Communications, Inc. Vista, CA, USA, 92081...n ac hieve l ow-power, E MI-immune links within hi gh-performance m ilitary computing an d sensor systems. Figure 1. Chip-scale-packaging of

Real-time encoding and compression of neuronal spikes by metal-oxide memristors

NASA Astrophysics Data System (ADS)

Gupta, Isha; Serb, Alexantrou; Khiat, Ali; Zeitler, Ralf; Vassanelli, Stefano; Prodromakis, Themistoklis

2016-09-01

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology's potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces.

Driver face tracking using semantics-based feature of eyes on single FPGA

NASA Astrophysics Data System (ADS)

Yu, Ying-Hao; Chen, Ji-An; Ting, Yi-Siang; Kwok, Ngaiming

2017-06-01

Tracking driver's face is one of the essentialities for driving safety control. This kind of system is usually designed with complicated algorithms to recognize driver's face by means of powerful computers. The design problem is not only about detecting rate but also from parts damages under rigorous environments by vibration, heat, and humidity. A feasible strategy to counteract these damages is to integrate entire system into a single chip in order to achieve minimum installation dimension, weight, power consumption, and exposure to air. Meanwhile, an extraordinary methodology is also indispensable to overcome the dilemma of low-computing capability and real-time performance on a low-end chip. In this paper, a novel driver face tracking system is proposed by employing semantics-based vague image representation (SVIR) for minimum hardware resource usages on a FPGA, and the real-time performance is also guaranteed at the same time. Our experimental results have indicated that the proposed face tracking system is viable and promising for the smart car design in the future.

A single-chip event sequencer and related microcontroller instrumentation for atomic physics research.

PubMed

Eyler, E E

2011-01-01

A 16-bit digital event sequencer with 50 ns resolution and 50 ns trigger jitter is implemented by using an internal 32-bit timer on a dsPIC30F4013 microcontroller, controlled by an easily modified program written in standard C. It can accommodate hundreds of output events, and adjacent events can be spaced as closely as 1.5 μs. The microcontroller has robust 5 V inputs and outputs, allowing a direct interface to common laboratory equipment and other electronics. A USB computer interface and a pair of analog ramp outputs can be added with just two additional chips. An optional display/keypad unit allows direct interaction with the sequencer without requiring an external computer. Minor additions also allow simple realizations of other complex instruments, including a precision high-voltage ramp generator for driving spectrum analyzers or piezoelectric positioners, and a low-cost proportional integral differential controller and lock-in amplifier for laser frequency stabilization with about 100 kHz bandwidth.

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

1997-01-01

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Real-time encoding and compression of neuronal spikes by metal-oxide memristors

PubMed Central

Gupta, Isha; Serb, Alexantrou; Khiat, Ali; Zeitler, Ralf; Vassanelli, Stefano; Prodromakis, Themistoklis

2016-01-01

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology's potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces. PMID:27666698

Towards pattern generation and chaotic series prediction with photonic reservoir computers

NASA Astrophysics Data System (ADS)

Antonik, Piotr; Hermans, Michiel; Duport, François; Haelterman, Marc; Massar, Serge

2016-03-01

Reservoir Computing is a bio-inspired computing paradigm for processing time dependent signals that is particularly well suited for analog implementations. Our team has demonstrated several photonic reservoir computers with performance comparable to digital algorithms on a series of benchmark tasks such as channel equalisation and speech recognition. Recently, we showed that our opto-electronic reservoir computer could be trained online with a simple gradient descent algorithm programmed on an FPGA chip. This setup makes it in principle possible to feed the output signal back into the reservoir, and thus highly enrich the dynamics of the system. This will allow to tackle complex prediction tasks in hardware, such as pattern generation and chaotic and financial series prediction, which have so far only been studied in digital implementations. Here we report simulation results of our opto-electronic setup with an FPGA chip and output feedback applied to pattern generation and Mackey-Glass chaotic series prediction. The simulations take into account the major aspects of our experimental setup. We find that pattern generation can be easily implemented on the current setup with very good results. The Mackey-Glass series prediction task is more complex and requires a large reservoir and more elaborate training algorithm. With these adjustments promising result are obtained, and we now know what improvements are needed to match previously reported numerical results. These simulation results will serve as basis of comparison for experiments we will carry out in the coming months.

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

NASA Technical Reports Server (NTRS)

Savich, Gregory R.

2004-01-01

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

Propagating gene expression fronts in a one-dimensional coupled system of artificial cells

NASA Astrophysics Data System (ADS)

Tayar, Alexandra M.; Karzbrun, Eyal; Noireaux, Vincent; Bar-Ziv, Roy H.

2015-12-01

Living systems employ front propagation and spatiotemporal patterns encoded in biochemical reactions for communication, self-organization and computation. Emulating such dynamics in minimal systems is important for understanding physical principles in living cells and in vitro. Here, we report a one-dimensional array of DNA compartments in a silicon chip as a coupled system of artificial cells, offering the means to implement reaction-diffusion dynamics by integrated genetic circuits and chip geometry. Using a bistable circuit we programmed a front of protein synthesis propagating in the array as a cascade of signal amplification and short-range diffusion. The front velocity is maximal at a saddle-node bifurcation from a bistable regime with travelling fronts to a monostable regime that is spatially homogeneous. Near the bifurcation the system exhibits large variability between compartments, providing a possible mechanism for population diversity. This demonstrates that on-chip integrated gene circuits are dynamical systems driving spatiotemporal patterns, cellular variability and symmetry breaking.

Electro-optic routing of photons from a single quantum dot in photonic integrated circuits

NASA Astrophysics Data System (ADS)

Midolo, Leonardo; Hansen, Sofie L.; Zhang, Weili; Papon, Camille; Schott, Rüdiger; Ludwig, Arne; Wieck, Andreas D.; Lodahl, Peter; Stobbe, Søren

2017-12-01

Recent breakthroughs in solid-state photonic quantum technologies enable generating and detecting single photons with near-unity efficiency as required for a range of photonic quantum technologies. The lack of methods to simultaneously generate and control photons within the same chip, however, has formed a main obstacle to achieving efficient multi-qubit gates and to harness the advantages of chip-scale quantum photonics. Here we propose and demonstrate an integrated voltage-controlled phase shifter based on the electro-optic effect in suspended photonic waveguides with embedded quantum emitters. The phase control allows building a compact Mach-Zehnder interferometer with two orthogonal arms, taking advantage of the anisotropic electro-optic response in gallium arsenide. Photons emitted by single self-assembled quantum dots can be actively routed into the two outputs of the interferometer. These results, together with the observed sub-microsecond response time, constitute a significant step towards chip-scale single-photon-source de-multiplexing, fiber-loop boson sampling, and linear optical quantum computing.

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

PubMed Central

Lue, Jaw-Chyng; Fang, Wai-Chi

2008-01-01

A compact integrated system-on-chip (SoC) architecture solution for robust, real-time, and on-site genetic analysis has been proposed. This microsystem solution is noise-tolerable and suitable for analyzing the weak fluorescence patterns from a PCR prepared dual-labeled DNA microchip assay. In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals. A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage. A single-channel logarithmic circuit was fabricated and characterized. A prototype ANN chip with unsupervised winner-take-all (WTA) function was designed, fabricated, and tested. An ANN learning algorithm using a novel sigmoid-logarithmic transfer function based on the supervised backpropagation (BP) algorithm is proposed for robustly recognizing low-intensity patterns. Our results show that the trained new ANN can recognize low-fluorescence patterns better than an ANN using the conventional sigmoid function. PMID:18566679

OpenSoC Fabric

DOE Office of Scientific and Technical Information (OSTI.GOV)

2014-08-21

Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by itsmore » base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric2 infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.« less

Patch-clamp amplifiers on a chip

PubMed Central

Weerakoon, Pujitha; Culurciello, Eugenio; Yang, Youshan; Santos-Sacchi, Joseph; Kindlmann, Peter J.; Sigworth, Fred J.

2010-01-01

We present the first, fully-integrated, two-channel implementation of a patch-clamp measurement system. With this “PatchChip” two simultaneous whole-cell recordings can be obtained with rms noise of 8 pA in a 10 kHz bandwidth. The capacitance and series-resistance of the electrode can be compensated up to 10 pF and 100 MΩ respectively under computer control. Recordings of hERG and Nav 1.7 currents demonstrate the system's capabilities, which are on par with large, commercial patch-clamp instrumentation. By reducing patch-clamp amplifiers to a millimeter size micro-chip, this work paves the way to the realization of massively-parallel, high-throughput patch-clamp systems for drug screening and ion-channel research. The PatchChip is implemented in a 0.5 μm silicon-on-sapphire process; its size is 3 × 3 mm2 and the power consumption is 5 mW per channel with a 3.3 V power supply. PMID:20637803

Fabrication of Circuit QED Quantum Processors, Part 1: Extensible Footprint for a Superconducting Surface Code

NASA Astrophysics Data System (ADS)

Bruno, A.; Michalak, D. J.; Poletto, S.; Clarke, J. S.; Dicarlo, L.

Large-scale quantum computation hinges on the ability to preserve and process quantum information with higher fidelity by increasing redundancy in a quantum error correction code. We present the realization of a scalable footprint for superconducting surface code based on planar circuit QED. We developed a tileable unit cell for surface code with all I/O routed vertically by means of superconducting through-silicon vias (TSVs). We address some of the challenges encountered during the fabrication and assembly of these chips, such as the quality of etch of the TSV, the uniformity of the ALD TiN coating conformal to the TSV, and the reliability of superconducting indium contact between the chips and PCB. We compare measured performance to a detailed list of specifications required for the realization of quantum fault tolerance. Our demonstration using centimeter-scale chips can accommodate the 50 qubits needed to target the experimental demonstration of small-distance logical qubits. Research funded by Intel Corporation and IARPA.

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

NASA Technical Reports Server (NTRS)

Ruiz, Ian B.; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

Graphene-on-silicon hybrid plasmonic-photonic integrated circuits.

PubMed

Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

2017-06-16

Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

Maps and Map Learning in Social Studies

ERIC Educational Resources Information Center

Bednarz, Sarah Witham; Acheson, Gillian; Bednarz, Robert S.

2006-01-01

The importance of maps and other graphic representations has become more important to geography and geographers. This is due to the development and widespread diffusion of geographic (spatial) technologies. As computers and silicon chips have become more capable and less expensive, geographic information systems (GIS), global positioning satellite…

High-density marker imputation accuracy in sixteen French cattle breeds.

PubMed

Hozé, Chris; Fouilloux, Marie-Noëlle; Venot, Eric; Guillaume, François; Dassonneville, Romain; Fritz, Sébastien; Ducrocq, Vincent; Phocas, Florence; Boichard, Didier; Croiseau, Pascal

2013-09-03

Genotyping with the medium-density Bovine SNP50 BeadChip® (50K) is now standard in cattle. The high-density BovineHD BeadChip®, which contains 777,609 single nucleotide polymorphisms (SNPs), was developed in 2010. Increasing marker density increases the level of linkage disequilibrium between quantitative trait loci (QTL) and SNPs and the accuracy of QTL localization and genomic selection. However, re-genotyping all animals with the high-density chip is not economically feasible. An alternative strategy is to genotype part of the animals with the high-density chip and to impute high-density genotypes for animals already genotyped with the 50K chip. Thus, it is necessary to investigate the error rate when imputing from the 50K to the high-density chip. Five thousand one hundred and fifty three animals from 16 breeds (89 to 788 per breed) were genotyped with the high-density chip. Imputation error rates from the 50K to the high-density chip were computed for each breed with a validation set that included the 20% youngest animals. Marker genotypes were masked for animals in the validation population in order to mimic 50K genotypes. Imputation was carried out using the Beagle 3.3.0 software. Mean allele imputation error rates ranged from 0.31% to 2.41% depending on the breed. In total, 1980 SNPs had high imputation error rates in several breeds, which is probably due to genome assembly errors, and we recommend to discard these in future studies. Differences in imputation accuracy between breeds were related to the high-density-genotyped sample size and to the genetic relationship between reference and validation populations, whereas differences in effective population size and level of linkage disequilibrium showed limited effects. Accordingly, imputation accuracy was higher in breeds with large populations and in dairy breeds than in beef breeds. More than 99% of the alleles were correctly imputed if more than 300 animals were genotyped at high-density. No improvement was observed when multi-breed imputation was performed. In all breeds, imputation accuracy was higher than 97%, which indicates that imputation to the high-density chip was accurate. Imputation accuracy depends mainly on the size of the reference population and the relationship between reference and target populations.

High-density marker imputation accuracy in sixteen French cattle breeds

PubMed Central

2013-01-01

Background Genotyping with the medium-density Bovine SNP50 BeadChip® (50K) is now standard in cattle. The high-density BovineHD BeadChip®, which contains 777 609 single nucleotide polymorphisms (SNPs), was developed in 2010. Increasing marker density increases the level of linkage disequilibrium between quantitative trait loci (QTL) and SNPs and the accuracy of QTL localization and genomic selection. However, re-genotyping all animals with the high-density chip is not economically feasible. An alternative strategy is to genotype part of the animals with the high-density chip and to impute high-density genotypes for animals already genotyped with the 50K chip. Thus, it is necessary to investigate the error rate when imputing from the 50K to the high-density chip. Methods Five thousand one hundred and fifty three animals from 16 breeds (89 to 788 per breed) were genotyped with the high-density chip. Imputation error rates from the 50K to the high-density chip were computed for each breed with a validation set that included the 20% youngest animals. Marker genotypes were masked for animals in the validation population in order to mimic 50K genotypes. Imputation was carried out using the Beagle 3.3.0 software. Results Mean allele imputation error rates ranged from 0.31% to 2.41% depending on the breed. In total, 1980 SNPs had high imputation error rates in several breeds, which is probably due to genome assembly errors, and we recommend to discard these in future studies. Differences in imputation accuracy between breeds were related to the high-density-genotyped sample size and to the genetic relationship between reference and validation populations, whereas differences in effective population size and level of linkage disequilibrium showed limited effects. Accordingly, imputation accuracy was higher in breeds with large populations and in dairy breeds than in beef breeds. More than 99% of the alleles were correctly imputed if more than 300 animals were genotyped at high-density. No improvement was observed when multi-breed imputation was performed. Conclusion In all breeds, imputation accuracy was higher than 97%, which indicates that imputation to the high-density chip was accurate. Imputation accuracy depends mainly on the size of the reference population and the relationship between reference and target populations. PMID:24004563

An evaluation of the directed flow graph methodology

NASA Technical Reports Server (NTRS)

Snyder, W. E.; Rajala, S. A.

1984-01-01

The applicability of the Directed Graph Methodology (DGM) to the design and analysis of special purpose image and signal processing hardware was evaluated. A special purpose image processing system was designed and described using DGM. The design, suitable for very large scale integration (VLSI) implements a region labeling technique. Two computer chips were designed, both using metal-nitride-oxide-silicon (MNOS) technology, as well as a functional system utilizing those chips to perform real time region labeling. The system is described in terms of DGM primitives. As it is currently implemented, DGM is inappropriate for describing synchronous, tightly coupled, special purpose systems. The nature of the DGM formalism lends itself more readily to modeling networks of general purpose processors.

The silicon-glass microreactor with embedded sensors—technology and results of preliminary qualitative tests, toward intelligent microreaction plant

NASA Astrophysics Data System (ADS)

Knapkiewicz, P.

2013-03-01

The technology and preliminary qualitative tests of silicon-glass microreactors with embedded pressure and temperature sensors are presented. The concept of microreactors for leading highly exothermic reactions, e.g. nitration of hydrocarbons, and design process-included computer-aided simulations are described in detail. The silicon-glass microreactor chip consisting of two micromixers (multistream micromixer), reaction channels, cooling/heating chambers has been proposed. The microreactor chip was equipped with a set of pressure and temperature sensors and packaged. Tests of mixing quality, pressure drops in channels, heat exchange efficiency and dynamic behavior of pressure and temperature sensors were documented. Finally, two applications were described.

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khare, Surhud; Somasekhar, Dinesh; More, Ankit

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

MBE growth of VCSELs for high volume applications

NASA Astrophysics Data System (ADS)

Jäger, Roland; Riedl, Michael C.

2011-05-01

Mass market applications like laser computer mouse or optical data transmission based on vertical-cavity surface-emitting laser (VCSEL) chips need a high over all yield including epitaxy, processing, dicing, mounting and testing. One yield limitation for VCSEL structures is the emission wavelength variation of the substrate surface area leading to the fraction on laser chips which are below or above the specification limits. For most 850 nm VCSEL products a resonator wavelength variation of ±2 nm is common. This represents an average resonator thickness variation of much less than 1% which is quite challenging to be fulfilled on the entire processed wafer surface area. A high over all yield is demonstrated on MBE grown VCSEL structures.

Optoelectronic date acquisition system based on FPGA

NASA Astrophysics Data System (ADS)

Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

2015-11-01

An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

Real-time monitoring of metabolic function in liver-on-chip microdevices tracks the dynamics of mitochondrial dysfunction

PubMed Central

Bavli, Danny; Prill, Sebastian; Ezra, Elishai; Levy, Gahl; Cohen, Merav; Vinken, Mathieu; Vanfleteren, Jan; Jaeger, Magnus; Nahmias, Yaakov

2016-01-01

Microfluidic organ-on-a-chip technology aims to replace animal toxicity testing, but thus far has demonstrated few advantages over traditional methods. Mitochondrial dysfunction plays a critical role in the development of chemical and pharmaceutical toxicity, as well as pluripotency and disease processes. However, current methods to evaluate mitochondrial activity still rely on end-point assays, resulting in limited kinetic and prognostic information. Here, we present a liver-on-chip device capable of maintaining human tissue for over a month in vitro under physiological conditions. Mitochondrial respiration was monitored in real time using two-frequency phase modulation of tissue-embedded phosphorescent microprobes. A computer-controlled microfluidic switchboard allowed contiguous electrochemical measurements of glucose and lactate, providing real-time analysis of minute shifts from oxidative phosphorylation to anaerobic glycolysis, an early indication of mitochondrial stress. We quantify the dynamics of cellular adaptation to mitochondrial damage and the resulting redistribution of ATP production during rotenone-induced mitochondrial dysfunction and troglitazone (Rezulin)-induced mitochondrial stress. We show troglitazone shifts metabolic fluxes at concentrations previously regarded as safe, suggesting a mechanism for its observed idiosyncratic effect. Our microfluidic platform reveals the dynamics and strategies of cellular adaptation to mitochondrial damage, a unique advantage of organ-on-chip technology. PMID:27044092

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications.

PubMed

Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

2016-08-11

Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure-Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron-Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

PubMed Central

Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

2016-01-01

Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure–Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods. PMID:27529225

Massively parallel information processing systems for space applications

NASA Technical Reports Server (NTRS)

Schaefer, D. H.

1979-01-01

NASA is developing massively parallel systems for ultra high speed processing of digital image data collected by satellite borne instrumentation. Such systems contain thousands of processing elements. Work is underway on the design and fabrication of the 'Massively Parallel Processor', a ground computer containing 16,384 processing elements arranged in a 128 x 128 array. This computer uses existing technology. Advanced work includes the development of semiconductor chips containing thousands of feedthrough paths. Massively parallel image analog to digital conversion technology is also being developed. The goal is to provide compact computers suitable for real-time onboard processing of images.

Computational method and system for modeling, analyzing, and optimizing DNA amplification and synthesis

DOEpatents

Vandersall, Jennifer A.; Gardner, Shea N.; Clague, David S.

2010-05-04

A computational method and computer-based system of modeling DNA synthesis for the design and interpretation of PCR amplification, parallel DNA synthesis, and microarray chip analysis. The method and system include modules that address the bioinformatics, kinetics, and thermodynamics of DNA amplification and synthesis. Specifically, the steps of DNA selection, as well as the kinetics and thermodynamics of DNA hybridization and extensions, are addressed, which enable the optimization of the processing and the prediction of the products as a function of DNA sequence, mixing protocol, time, temperature and concentration of species.

Advanced flight computer. Special study

NASA Technical Reports Server (NTRS)

Coo, Dennis

1995-01-01

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996.

Heterogeneous High Throughput Scientific Computing with APM X-Gene and Intel Xeon Phi

NASA Astrophysics Data System (ADS)

Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; Eulisse, Giulio; Knight, Robert; Muzaffar, Shahzad

2015-05-01

Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. We report our experience on software porting, performance and energy efficiency and evaluate the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).

Innovation and Competition: Conflicts over Intellectual Property Rights in New Technologies.

ERIC Educational Resources Information Center

Samuelson, Pamela

1987-01-01

Addresses conditions and concerns involved in accommodating the interests of both innovators of new technologies and the general public. Discusses the tension that exists in intellectual property law between innovators and competitors. Focuses on cases dealing with computer software and semiconductor chip designs, genetically-engineered life…

Fuzzy control of magnetic bearings

NASA Technical Reports Server (NTRS)

Feeley, J. J.; Niederauer, G. M.; Ahlstrom, D. J.

1991-01-01

The use of an adaptive fuzzy control algorithm implemented on a VLSI chip for the control of a magnetic bearing was considered. The architecture of the adaptive fuzzy controller is similar to that of a neural network. The performance of the fuzzy controller is compared to that of a conventional controller by computer simulation.

Neural network applications in telecommunications

NASA Technical Reports Server (NTRS)

Alspector, Joshua

1994-01-01

Neural network capabilities include automatic and organized handling of complex information, quick adaptation to continuously changing environments, nonlinear modeling, and parallel implementation. This viewgraph presentation presents Bellcore work on applications, learning chip computational function, learning system block diagram, neural network equalization, broadband access control, calling-card fraud detection, software reliability prediction, and conclusions.

EVALUATION OF DNA CHIPS (MICROARRAYS) FOR DETERMINING VIRULENCE FACTOR ACTIVITY RELATIONSHIPS (VFARS)

EPA Science Inventory

Computational toxicology is a rapid approach to screening for toxic effects and looking for common outcomes that can result in predictive models. The long term project will result in the development of a database of mRNA responses to known water-borne pathogens. An understanding...

77 FR 26789 - Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... patents. 73 FR 75131. The principal respondent was NVIDIA Corporation of Santa Clara, California (``NVIDIA''). Joining NVIDIA as respondents were approximately twenty of NVIDIA's customers. The Commission found a... accused products in the United States: NVIDIA; Hewlett-Packard Co. of Palo Alto, California; ASUS Computer...

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Béjanin, J. H.; Earnest, C. T.; McRae, C. R. H.; Pagel, Z.; Rinehart, J. R.; Mariantoni, M.

2018-07-01

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

International Conference on Stiff Computation Held at Park City, Utah on April 12, 13 and 14, 1982.

DTIC Science & Technology

1983-05-31

algorithm should be designed which can analyse a system description and find out for the user ~to which class of problems his system belongs... Dove...processors designed to implement aspecific solution process. yrne: IEE floating point chip design " used by INE and others is an example (Xahan)...the...hardware speciaList has designed his computer such that the paraL#L features can be addressed convenientLy and !! ’) efficientLy, and 4;) the software

A Chip in the Curtain: Computer Technology in the Soviet Union

DTIC Science & Technology

1989-03-01

authority of the tsar. British historian Lionel Kochan recounted some of the rather complicated story of religion and the tsars: The Church, because of... pseudosciences " and their study was forbidden. Stalin’s policy delayed the development of a scientific and academic foundation for the study of the computer in...leaders, the doctrine of Marx and Lenin is a matter of faith comparable to a religion in Western terms. When the General Secretary of the Soviet Union

Rapid determination of cell mass and density using digitally controlled electric field in a microfluidic chip.

PubMed

Zhao, Yuliang; Lai, Hok Sum Sam; Zhang, Guanglie; Lee, Gwo-Bin; Li, Wen Jung

2014-11-21

The density of a single cell is a fundamental property of cells. Cells in the same cycle phase have similar volume, but the differences in their mass and density could elucidate each cell's physiological state. Here we report a novel technique to rapidly measure the density and mass of a single cell using an optically induced electrokinetics (OEK) microfluidic platform. Presently, single cellular mass and density measurement devices require a complicated fabrication process and their output is not scalable, i.e., it is extremely difficult to measure the mass and density of a large quantity of cells rapidly. The technique reported here operates on a principle combining sedimentation theory, computer vision, and microparticle manipulation techniques in an OEK microfluidic platform. We will show in this paper that this technique enables the measurement of single-cell volume, density, and mass rapidly and accurately in a repeatable manner. The technique is also scalable - it allows simultaneous measurement of volume, density, and mass of multiple cells. Essentially, a simple time-controlled projected light pattern is used to illuminate the selected area on the OEK microfluidic chip that contains cells to lift the cells to a particular height above the chip's surface. Then, the cells are allowed to "free fall" to the chip's surface, with competing buoyancy, gravitational, and fluidic drag forces acting on the cells. By using a computer vision algorithm to accurately track the motion of the cells and then relate the cells' motion trajectory to sedimentation theory, the volume, mass, and density of each cell can be rapidly determined. A theoretical model of micro-sized spheres settling towards an infinite plane in a microfluidic environment is first derived and validated experimentally using standard micropolystyrene beads to demonstrate the viability and accuracy of this new technique. Next, we show that the yeast cell volume, mass, and density could be rapidly determined using this technology, with results comparable to those using the existing method suspended microchannel resonator.

Integration of Genome-Wide Computation DRE Search, AhR ChIP-chip and Gene Expression Analyses of TCDD-Elicited Responses in the Mouse Liver

PubMed Central

2011-01-01

Background The aryl hydrocarbon receptor (AhR) is a ligand-activated transcription factor (TF) that mediates responses to 2,3,7,8-tetrachlorodibenzo-p-dioxin (TCDD). Integration of TCDD-induced genome-wide AhR enrichment, differential gene expression and computational dioxin response element (DRE) analyses further elucidate the hepatic AhR regulatory network. Results Global ChIP-chip and gene expression analyses were performed on hepatic tissue from immature ovariectomized mice orally gavaged with 30 μg/kg TCDD. ChIP-chip analysis identified 14,446 and 974 AhR enriched regions (1% false discovery rate) at 2 and 24 hrs, respectively. Enrichment density was greatest in the proximal promoter, and more specifically, within ± 1.5 kb of a transcriptional start site (TSS). AhR enrichment also occurred distal to a TSS (e.g. intergenic DNA and 3' UTR), extending the potential gene expression regulatory roles of the AhR. Although TF binding site analyses identified over-represented DRE sequences within enriched regions, approximately 50% of all AhR enriched regions lacked a DRE core (5'-GCGTG-3'). Microarray analysis identified 1,896 number of TCDD-responsive genes (|fold change| ≥ 1.5, P1(t) > 0.999). Integrating this gene expression data with our ChIP-chip and DRE analyses only identified 625 differentially expressed genes that involved an AhR interaction at a DRE. Functional annotation analysis of differentially regulated genes associated with AhR enrichment identified overrepresented processes related to fatty acid and lipid metabolism and transport, and xenobiotic metabolism, which are consistent with TCDD-elicited steatosis in the mouse liver. Conclusions Details of the AhR regulatory network have been expanded to include AhR-DNA interactions within intragenic and intergenic genomic regions. Moreover, the AhR can interact with DNA independent of a DRE core suggesting there are alternative mechanisms of AhR-mediated gene regulation. PMID:21762485

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

PubMed

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks.

PubMed

Walter, Florian; Röhrbein, Florian; Knoll, Alois

2015-12-01

The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. Copyright © 2015 Elsevier Ltd. All rights reserved.

Ag2S atomic switch-based `tug of war' for decision making

NASA Astrophysics Data System (ADS)

Lutz, C.; Hasegawa, T.; Chikyow, T.

2016-07-01

For a computing process such as making a decision, a software controlled chip of several transistors is necessary. Inspired by how a single cell amoeba decides its movements, the theoretical `tug of war' computing model was proposed but not yet implemented in an analogue device suitable for integrated circuits. Based on this model, we now developed a new electronic element for decision making processes, which will have no need for prior programming. The devices are based on the growth and shrinkage of Ag filaments in α-Ag2+δS gap-type atomic switches. Here we present the adapted device design and the new materials. We demonstrate the basic `tug of war' operation by IV-measurements and Scanning Electron Microscopy (SEM) observation. These devices could be the base for a CMOS-free new computer architecture.For a computing process such as making a decision, a software controlled chip of several transistors is necessary. Inspired by how a single cell amoeba decides its movements, the theoretical `tug of war' computing model was proposed but not yet implemented in an analogue device suitable for integrated circuits. Based on this model, we now developed a new electronic element for decision making processes, which will have no need for prior programming. The devices are based on the growth and shrinkage of Ag filaments in α-Ag2+δS gap-type atomic switches. Here we present the adapted device design and the new materials. We demonstrate the basic `tug of war' operation by IV-measurements and Scanning Electron Microscopy (SEM) observation. These devices could be the base for a CMOS-free new computer architecture. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00690f

Heterogeneous high throughput scientific computing with APM X-Gene and Intel Xeon Phi

DOE PAGES

Abdurachmanov, David; Bockelman, Brian; Elmer, Peter; ...

2015-05-22

Electrical power requirements will be a constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics. Performance-per-watt is a critical metric for the evaluation of computer architectures for cost- efficient computing. Additionally, future performance growth will come from heterogeneous, many-core, and high computing density platforms with specialized processors. In this paper, we examine the Intel Xeon Phi Many Integrated Cores (MIC) co-processor and Applied Micro X-Gene ARMv8 64-bit low-power server system-on-a-chip (SoC) solutions for scientific computing applications. As a result, we report our experience on software porting, performance and energy efficiency and evaluatemore » the potential for use of such technologies in the context of distributed computing systems such as the Worldwide LHC Computing Grid (WLCG).« less

Computer software.

PubMed

Rosenthal, L E

1986-10-01

Software is the component in a computer system that permits the hardware to perform the various functions that a computer system is capable of doing. The history of software and its development can be traced to the early nineteenth century. All computer systems are designed to utilize the "stored program concept" as first developed by Charles Babbage in the 1850s. The concept was lost until the mid-1940s, when modern computers made their appearance. Today, because of the complex and myriad tasks that a computer system can perform, there has been a differentiation of types of software. There is software designed to perform specific business applications. There is software that controls the overall operation of a computer system. And there is software that is designed to carry out specialized tasks. Regardless of types, software is the most critical component of any computer system. Without it, all one has is a collection of circuits, transistors, and silicone chips.

Fabrication of universal serial bus flash disk type microfluidic chip electrophoresis and application for protein analysis under ultra low voltage

PubMed Central

Cong, Hailin; Xu, Xiaodan; Yu, Bing; Liu, Huwei

2016-01-01

A simple and effective universal serial bus (USB) flash disk type microfluidic chip electrophoresis (MCE) was developed by using poly(dimethylsiloxane) based soft lithography and dry film based printed circuit board etching techniques in this paper. The MCE had a microchannel diameter of 375 μm and an effective length of 25 mm. Equipped with a conventional online electrochemical detector, the device enabled effectively separation of bovine serum albumin, lysozyme, and cytochrome c in 80 s under the ultra low voltage from a computer USB interface. Compared with traditional capillary electrophoresis, the USB flash disk type MCE is not only portable and inexpensive but also fast with high separation efficiency. PMID:27042249

Advanced Exploration Technologies: Micro and Nano Technologies Enabling Space Missions in the 21st Century

NASA Technical Reports Server (NTRS)

Krabach, Timothy

1998-01-01

Some of the many new and advanced exploration technologies which will enable space missions in the 21st century and specifically the Manned Mars Mission are explored in this presentation. Some of these are the system on a chip, the Computed-Tomography imaging Spectrometer, the digital camera on a chip, and other Micro Electro Mechanical Systems (MEMS) technology for space. Some of these MEMS are the silicon micromachined microgyroscope, a subliming solid micro-thruster, a micro-ion thruster, a silicon seismometer, a dewpoint microhygrometer, a micro laser doppler anemometer, and tunable diode laser (TDL) sensors. The advanced technology insertion is critical for NASA to decrease mass, volume, power and mission costs, and increase functionality, science potential and robustness.

An analog VLSI chip emulating polarization vision of Octopus retina.

PubMed

Momeni, Massoud; Titus, Albert H

2006-01-01

Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

Advanced Microcomputer Service Technician. Teacher Edition.

ERIC Educational Resources Information Center

Brown, A. O., III; Fulkerson, Dan, Ed.

This manual is the second of a three-text microcomputer service and repair series. This text addresses the training needs of "chip level" technicians who work with digital troubleshooting instruments to solve the complex microcomputer problems that are sent to them from computer stores that do not have full-service facilities. The manual contains…

Preserving Tradition through Technology.

ERIC Educational Resources Information Center

Wakshul, Barbra

2001-01-01

Language is easiest to learn before age 5. The Cherokee Nation supported production of a toy that teaches young children basic Cherokee words. When figures that come with the toy are placed into it, a computer chip activates a voice speaking the name of the figure in Cherokee. Learning takes place on visual, auditory, and tactile levels. (TD)

[The study and manufacture of spinning counter for experimental animals].

PubMed

Qi, X P; Zhou, C; Liu, F J; Chen, Z; Jiang, L; Yan, Z

1997-09-01

The single-chip microcomputer technique is used in the present study of spinning counter, which has 4 observation tunnels, the spinning behave of four experiment animals can be recorded at same time. The function of this instrument has four selections according to different experiment, and the recording data can be compute processed.

Genomic imputation and evaluation using high density Holstein genotypes

USDA-ARS?s Scientific Manuscript database

Genomic evaluations for 161,341 Holsteins were computed using 311,725 of the 777,962 markers on the Illumina high-density (HD) chip. Initial edits with 1,741 HD genotypes from 5 breeds revealed that 636,967 markers were usable but that half were redundant. Usable Holstein genotypes included 1,510 an...

50 CFR 660.314 - Groundfish observer program.

Code of Federal Regulations, 2010 CFR

2010-10-01

... provided to the crew. (2) Safe conditions. Maintain safe conditions on the vessel for the protection of... to safe operation of the vessel, and provisions at §§ 600.725 and 600.746 of this chapter. (3... computer in working condition that contains a full Pentium 120 Mhz or greater capacity processing chip, at...

An Electrifying Quiz! Constructing a Printed-Circuit Board Quiz Game

ERIC Educational Resources Information Center

Calhoun, Michael J.

2005-01-01

Laptop computers, cell phones and the Apple iPod all contain transistors, IC chips, capacitors, and other electronic components. To the general public--and especially students in upper elementary and middle school grades--these components are most often very mysterious items. Yet, it is at elementary and middle school levels that scientists and…

FPGA-Based Laboratory Assignments for NoC-Based Manycore Systems

ERIC Educational Resources Information Center

Ttofis, C.; Theocharides, T.; Michael, M. K.

2012-01-01

Manycore systems have emerged as being one of the dominant architectural trends in next-generation computer systems. These highly parallel systems are expected to be interconnected via packet-based networks-on-chip (NoC). The complexity of such systems poses novel and exciting challenges in academia, as teaching their design requires the students…

Design of barrier bucket kicker control system

NASA Astrophysics Data System (ADS)

Ni, Fa-Fu; Wang, Yan-Yu; Yin, Jun; Zhou, De-Tai; Shen, Guo-Dong; Zheng, Yang-De.; Zhang, Jian-Chuan; Yin, Jia; Bai, Xiao; Ma, Xiao-Li

2018-05-01

The Heavy-Ion Research Facility in Lanzhou (HIRFL) contains two synchrotrons: the main cooler storage ring (CSRm) and the experimental cooler storage ring (CSRe). Beams are extracted from CSRm, and injected into CSRe. To apply the Barrier Bucket (BB) method on the CSRe beam accumulation, a new BB technology based kicker control system was designed and implemented. The controller of the system is implemented using an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) chip and a field-programmable gate array (FPGA) chip. Within the architecture, ARM is responsible for data presetting and floating number arithmetic processing. The FPGA computes the RF phase point of the two rings and offers more accurate control of the time delay. An online preliminary experiment on HIRFL was also designed to verify the functionalities of the control system. The result shows that the reference trigger point of two different sinusoidal RF signals for an arbitrary phase point was acquired with a matched phase error below 1° (approximately 2.1 ns), and the step delay time better than 2 ns were realized.

RASDR: Benchtop Demonstration of SDR for Radio Astronomy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, Bogdan; Oxley, Paul; Fields, David

The Society of Amateur Radio Astronomers (SARA) members present the benchtop version of RASDR, a Software Defined Radio (SDR) that is optimized for Radio Astronomy. RASDR has the potential to be a common digital receiver interface useful to many SARA members. This document describes the RASDR 0.0 , which provides digitized radio data to a backend computer through a USB 2.0 interface. A primary component of RASDR is the Lime Microsystems Femtocell chip which tunes from a 0.4-4 GHz center frequency with several selectable bandwidths from 0.75 MHz to 14 MHz. A second component is a board with a Complexmore » Programmable Logic Device (CPLD) chip that connects to the Femtocell and provides two USB connections to the backend computer. A third component is an analog balanced mixer up conversion section. Together these three components enable RASDR to tune from 0.015 MHz thru 3.8GHz of the radio frequency (RF) spectrum. We will demonstrate and discuss capabilities of the breadboard system and SARA members will be able to operate the unit hands-on throughout the workshop.« less

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

NASA Astrophysics Data System (ADS)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

Throwing computing into reverse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frank, Michael P.

For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipatemore » that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.« less

Many-core computing for space-based stereoscopic imaging

NASA Astrophysics Data System (ADS)

McCall, Paul; Torres, Gildo; LeGrand, Keith; Adjouadi, Malek; Liu, Chen; Darling, Jacob; Pernicka, Henry

The potential benefits of using parallel computing in real-time visual-based satellite proximity operations missions are investigated. Improvements in performance and relative navigation solutions over single thread systems can be achieved through multi- and many-core computing. Stochastic relative orbit determination methods benefit from the higher measurement frequencies, allowing them to more accurately determine the associated statistical properties of the relative orbital elements. More accurate orbit determination can lead to reduced fuel consumption and extended mission capabilities and duration. Inherent to the process of stereoscopic image processing is the difficulty of loading, managing, parsing, and evaluating large amounts of data efficiently, which may result in delays or highly time consuming processes for single (or few) processor systems or platforms. In this research we utilize the Single-Chip Cloud Computer (SCC), a fully programmable 48-core experimental processor, created by Intel Labs as a platform for many-core software research, provided with a high-speed on-chip network for sharing information along with advanced power management technologies and support for message-passing. The results from utilizing the SCC platform for the stereoscopic image processing application are presented in the form of Performance, Power, Energy, and Energy-Delay-Product (EDP) metrics. Also, a comparison between the SCC results and those obtained from executing the same application on a commercial PC are presented, showing the potential benefits of utilizing the SCC in particular, and any many-core platforms in general for real-time processing of visual-based satellite proximity operations missions.

VLSI design of lossless frame recompression using multi-orientation prediction

NASA Astrophysics Data System (ADS)

Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

2016-01-01

Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

Electro-optic techniques for VLSI interconnect

NASA Astrophysics Data System (ADS)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Simultaneous electrical recording of cardiac electrophysiology and contraction on chip

DOE PAGES

Qian, Fang; Huang, Chao; Lin, Yi-Dong; ...

2017-04-18

Prevailing commercialized cardiac platforms for in vitro drug development utilize planar microelectrode arrays to map action potentials, or impedance sensing to record contraction in real time, but cannot record both functions on the same chip with high spatial resolution. We report a novel cardiac platform that can record cardiac tissue adhesion, electrophysiology, and contractility on the same chip. The platform integrates two independent yet interpenetrating sensor arrays: a microelectrode array for field potential readouts and an interdigitated electrode array for impedance readouts. Together, these arrays provide real-time, non-invasive data acquisition of both cardiac electrophysiology and contractility under physiological conditions andmore » under drug stimuli. Furthermore, we cultured human induced pluripotent stem cell-derived cardiomyocytes as a model system, and used to validate the platform with an excitation–contraction decoupling chemical. Preliminary data using the platform to investigate the effect of the drug norepinephrine are combined with computational efforts. Finally, this platform provides a quantitative and predictive assay system that can potentially be used for comprehensive assessment of cardiac toxicity earlier in the drug discovery process.« less

Modelling and simulation of wood chip combustion in a hot air generator system.

PubMed

Rajika, J K A T; Narayana, Mahinsasa

2016-01-01

This study focuses on modelling and simulation of horizontal moving bed/grate wood chip combustor. A standalone finite volume based 2-D steady state Euler-Euler Computational Fluid Dynamics (CFD) model was developed for packed bed combustion. Packed bed combustion of a medium scale biomass combustor, which was retrofitted from wood log to wood chip feeding for Tea drying in Sri Lanka, was evaluated by a CFD simulation study. The model was validated by the experimental results of an industrial biomass combustor for a hot air generation system in tea industry. Open-source CFD tool; OpenFOAM was used to generate CFD model source code for the packed bed combustion and simulated along with an available solver for free board region modelling in the CFD tool. Height of the packed bed is about 20 cm and biomass particles are assumed to be spherical shape with constant surface area to volume ratio. Temperature measurements of the combustor are well agreed with simulation results while gas phase compositions have discrepancies. Combustion efficiency of the validated hot air generator is around 52.2 %.

Report on the Infinium 450k methylation array analysis workshop: April 20, 2012 UCL, London, UK.

PubMed

Morris, Tiffany; Lowe, Robert

2012-08-01

A new platform for DNA methylome analysis is Illumina's Infinium HumanMethylation450. This technology is an extension of the previous HumanMethylation27 BeadChip and allows the methylation status of 12 samples per chip and 4 to 8 chips (total of 48 to 96 samples) to be assessed simultaneously for more than 480,000 cytosines across the genome. The platform incorporates two different probe types using different assay designs (InfiniumI and InfiniumII). Although this has allowed the assessment of more CpG sites, it has also introduced technical variation between the two probe types, which has complicated the analysis process. Many groups are working on normalization methods and analysis pipelines while many others are struggling to make sense of their new data sets. This motivated the organization of a meeting held at University College London that focused solely on the analysis methods and problems related to this new platform. The meeting was attended by 125 computational and bench scientists from 11 countries. There were 10 speakers, a small poster session and a discussion session.

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

NASA Astrophysics Data System (ADS)

Kim, Jeonghun; Kim, Suki; Baek, Kwang-Hyun

This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30mm2 in 0.18µm CMOS, and the worst-case current of the total chip is 54mA.

Simultaneous electrical recording of cardiac electrophysiology and contraction on chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Fang; Huang, Chao; Lin, Yi-Dong

Prevailing commercialized cardiac platforms for in vitro drug development utilize planar microelectrode arrays to map action potentials, or impedance sensing to record contraction in real time, but cannot record both functions on the same chip with high spatial resolution. We report a novel cardiac platform that can record cardiac tissue adhesion, electrophysiology, and contractility on the same chip. The platform integrates two independent yet interpenetrating sensor arrays: a microelectrode array for field potential readouts and an interdigitated electrode array for impedance readouts. Together, these arrays provide real-time, non-invasive data acquisition of both cardiac electrophysiology and contractility under physiological conditions andmore » under drug stimuli. Furthermore, we cultured human induced pluripotent stem cell-derived cardiomyocytes as a model system, and used to validate the platform with an excitation–contraction decoupling chemical. Preliminary data using the platform to investigate the effect of the drug norepinephrine are combined with computational efforts. Finally, this platform provides a quantitative and predictive assay system that can potentially be used for comprehensive assessment of cardiac toxicity earlier in the drug discovery process.« less

Ultrasonic Vibration Assisted Grinding of Bio-ceramic Materials: Modeling, Simulation, and Experimental Investigations on Edge Chipping

NASA Astrophysics Data System (ADS)

Tesfay, Hayelom D.

Bio-ceramics are those engineered materials that find their applications in the field of biomedical engineering or medicine. They have been widely used in dental restorations, repairing bones, joint replacements, pacemakers, kidney dialysis machines, and respirators. etc. due to their physico-chemical properties, such as excellent corrosion resistance, good biocompatibility, high strength and high wear resistance. Because of their inherent brittleness and hardness nature they are difficult to machine to exact sizes and dimensions. Abrasive machining processes such as grinding is one of the most widely used manufacturing processes for bioceramics. However, the principal technical challenge resulted from these machining is edge chipping. Edge chipping is a common edge failure commonly observed during the machining of bio-ceramic materials. The presence of edge chipping on bio-ceramic products affects dimensional accuracy, increases manufacturing cost, hider their industrial applications and causes potential failure during service. To overcome these technological challenges, a new ultrasonic vibration-assisted grinding (UVAG) manufacturing method has been developed and employed in this research. The ultimate aim of this study is to develop a new cost-effective manufacturing process relevant to eliminate edge chippings in grinding of bio-ceramic materials. In this dissertation, comprehensive investigations will be carried out using experimental, theoretical, and numerical approaches to evaluate the effect of ultrasonic vibrations on edge chipping of bioceramics. Moreover, effects of nine input variables (static load, vibration frequency, grinding depth, spindle speed, grinding distance, tool speed, grain size, grain number, and vibration amplitude) on edge chipping will be studied based on the developed models. Following a description of previous research and existing approaches, a series of experimental tests on three bio-ceramic materials (Lava, partially fired Lava, and Alumina) were conducted. Based on the experimental results, analytical models for UVAG and CG (conventional grinding without ultrasonic vibration) processes were developed. As for the numerical study, an extended finite element method (XFEM) based on Virtual Crack Closure Technique (VCCT) in ABAQUS was used to model the formation of edge chippings both for UVAG and CG processes. The experimental results are compared against the numerical FEA and the analytical models. The experimental, theoretical, and computational simulation results revealed that the edge chipping size of bioceramics can be significantly reduced with the assistance of ultrasonic vibration. The investigation procedures and the results obtained in this dissertation would be used as a reference and practical guidance for choosing reasonable process variables as well as designing mathematical (analytical and numerical) models in manufacturing industries and academic institutions when the edge chippings of brittle materials are expected to be controlled.

The Design and Implementation of NASA's Advanced Flight Computing Module

NASA Technical Reports Server (NTRS)

Alkakaj, Leon; Straedy, Richard; Jarvis, Bruce

1995-01-01

This paper describes a working flight computer Multichip Module developed jointly by JPL and TRW under their respective research programs in a collaborative fashion. The MCM is fabricated by nCHIP and is packaged within a 2 by 4 inch Al package from Coors. This flight computer module is one of three modules under development by NASA's Advanced Flight Computer (AFC) program. Further development of the Mass Memory and the programmable I/O MCM modules will follow. The three building block modules will then be stacked into a 3D MCM configuration. The mass and volume of the flight computer MCM achieved at 89 grams and 1.5 cubic inches respectively, represent a major enabling technology for future deep space as well as commercial remote sensing applications.

GeoChip 3.0: A High Throughput Tool for Analyzing Microbial Community, Composition, Structure, and Functional Activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Zhili; Deng, Ye; Nostrand, Joy Van

2010-05-17

Microarray-based genomic technology has been widely used for microbial community analysis, and it is expected that microarray-based genomic technologies will revolutionize the analysis of microbial community structure, function and dynamics. A new generation of functional gene arrays (GeoChip 3.0) has been developed, with 27,812 probes covering 56,990 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance, and organic contaminant degradation. Those probes were derived from 2,744, 140, and 262 species for bacteria, archaea, and fungi, respectively. GeoChip 3.0 has several other distinct features, such as a common oligomore » reference standard (CORS) for data normalization and comparison, a software package for data management and future updating, and the gyrB gene for phylogenetic analysis. Our computational evaluation of probe specificity indicated that all designed probes had a high specificity to their corresponding targets. Also, experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036percent-0.025percent false positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which demonstrated that the structure, composition, and potential activity of soil microbial communities significantly changed with the plant species diversity. All results indicate that GeoChip 3.0 is a high throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning. To our knowledge, GeoChip 3.0 is the most comprehensive microarrays currently available for studying microbial communities associated with geobiochemical cycling, global climate change, bioenergy, agricuture, land use, ecosystem management, environmental cleanup and restoration, bioreactor systems, and human health.« less

The new landscape of parallel computer architecture

NASA Astrophysics Data System (ADS)

Shalf, John

2007-07-01

The past few years has seen a sea change in computer architecture that will impact every facet of our society as every electronic device from cell phone to supercomputer will need to confront parallelism of unprecedented scale. Whereas the conventional multicore approach (2, 4, and even 8 cores) adopted by the computing industry will eventually hit a performance plateau, the highest performance per watt and per chip area is achieved using manycore technology (hundreds or even thousands of cores). However, fully unleashing the potential of the manycore approach to ensure future advances in sustained computational performance will require fundamental advances in computer architecture and programming models that are nothing short of reinventing computing. In this paper we examine the reasons behind the movement to exponentially increasing parallelism, and its ramifications for system design, applications and programming models.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Built-in self-repair of VLSI memories employing neural nets

NASA Astrophysics Data System (ADS)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

A smartphone controlled handheld microfluidic liquid handling system.

PubMed

Li, Baichen; Li, Lin; Guan, Allan; Dong, Quan; Ruan, Kangcheng; Hu, Ronggui; Li, Zhenyu

2014-10-21

Microfluidics and lab-on-a-chip technologies have made it possible to manipulate small volume liquids with unprecedented resolution, automation and integration. However, most current microfluidic systems still rely on bulky off-chip infrastructures such as compressed pressure sources, syringe pumps and computers to achieve complex liquid manipulation functions. Here, we present a handheld automated microfluidic liquid handling system controlled by a smartphone, which is enabled by combining elastomeric on-chip valves and a compact pneumatic system. As a demonstration, we show that the system can automatically perform all the liquid handling steps of a bead-based HIV1 p24 sandwich immunoassay on a multi-layer PDMS chip without any human intervention. The footprint of the system is 6 × 10.5 × 16.5 cm, and the total weight is 829 g including battery. Powered by a 12.8 V 1500 mAh Li battery, the system consumed 2.2 W on average during the immunoassay and lasted for 8.7 h. This handheld microfluidic liquid handling platform is generally applicable to many biochemical and cell-based assays requiring complex liquid manipulation and sample preparation steps such as FISH, PCR, flow cytometry and nucleic acid sequencing. In particular, the integration of this technology with read-out biosensors may help enable the realization of the long-sought Tricorder-like handheld in vitro diagnostic (IVD) systems.

Versatile all-digital time interval measuring system

NASA Astrophysics Data System (ADS)

Vyhlidal, David; Cech, Miroslav

2011-06-01

This paper describes a design and performance of a versatile all-digital time interval measuring system. The measurement method is based on an interpolation principle. In this principle the time interval is first roughly digitized by a coarse counter driven by a high stability reference clock and the fractions between the clock periods are measured by two Time-to-Digital Converter chips TDC-GPX manufactured by Acam messelectronic. Control circuits allow programmable customization of the system to satisfy many applications such as laser range finding, event counting, or time-of-flight measurements in various physics experiments. The system has two reference clocks inputs and two independent channels for measuring start and stop events. Only one 40 MHz reference is required for the measurement. The second reference can be, for example, 1 PPS (Pulse per Second) signal from a GPS (Global Positioning System) to time tag events. Time intervals are measured using the highest resolution mode of the TDC-GPX chips. The resolution of each chip is software programmable and is PLL (Phase Locked Loop) stabilized against temperature and voltage variations. The system can achieve a timing resolution better than 15 ps rms with up to 90 kHz repetition rate. The time interval measurement range is from 0 ps up to 1 second. The power consumption of the whole system is 18 W including an embedded computer board and an LCD (Liquid Crystal Display) screen. The embedded computer controls the whole system, collects and evaluates measurement data and with the display provides a user interface. The system is implemented using commercially available components.

On-Chip Imaging of Schistosoma haematobium Eggs in Urine for Diagnosis by Computer Vision

PubMed Central

Linder, Ewert; Grote, Anne; Varjo, Sami; Linder, Nina; Lebbad, Marianne; Lundin, Mikael; Diwan, Vinod; Hannuksela, Jari; Lundin, Johan

2013-01-01

Background Microscopy, being relatively easy to perform at low cost, is the universal diagnostic method for detection of most globally important parasitic infections. As quality control is hard to maintain, misdiagnosis is common, which affects both estimates of parasite burdens and patient care. Novel techniques for high-resolution imaging and image transfer over data networks may offer solutions to these problems through provision of education, quality assurance and diagnostics. Imaging can be done directly on image sensor chips, a technique possible to exploit commercially for the development of inexpensive “mini-microscopes”. Images can be transferred for analysis both visually and by computer vision both at point-of-care and at remote locations. Methods/Principal Findings Here we describe imaging of helminth eggs using mini-microscopes constructed from webcams and mobile phone cameras. The results show that an inexpensive webcam, stripped off its optics to allow direct application of the test sample on the exposed surface of the sensor, yields images of Schistosoma haematobium eggs, which can be identified visually. Using a highly specific image pattern recognition algorithm, 4 out of 5 eggs observed visually could be identified. Conclusions/Significance As proof of concept we show that an inexpensive imaging device, such as a webcam, may be easily modified into a microscope, for the detection of helminth eggs based on on-chip imaging. Furthermore, algorithms for helminth egg detection by machine vision can be generated for automated diagnostics. The results can be exploited for constructing simple imaging devices for low-cost diagnostics of urogenital schistosomiasis and other neglected tropical infectious diseases. PMID:24340107

Cognitive science as an interface between rational and mechanistic explanation.

PubMed

Chater, Nick

2014-04-01

Cognitive science views thought as computation; and computation, by its very nature, can be understood in both rational and mechanistic terms. In rational terms, a computation solves some information processing problem (e.g., mapping sensory information into a description of the external world; parsing a sentence; selecting among a set of possible actions). In mechanistic terms, a computation corresponds to causal chain of events in a physical device (in engineering context, a silicon chip; in biological context, the nervous system). The discipline is thus at the interface between two very different styles of explanation--as the papers in the current special issue well illustrate, it explores the interplay of rational and mechanistic forces. Copyright © 2014 Cognitive Science Society, Inc.

Dual-scan technique for the customization of zirconia computer-aided design/computer-aided manufacturing frameworks.

PubMed

Andreiuolo, Rafael Ferrone; Sabrosa, Carlos Eduardo; Dias, Katia Regina H Cervantes

2013-09-01

The use of bi-layered all-ceramic crowns has continuously grown since the introduction of computer-aided design/computer-aided manufacturing (CAD/CAM) zirconia cores. Unfortunately, despite the outstanding mechanical properties of zirconia, problems related to porcelain cracking or chipping remain. One of the reasons for this is that ceramic copings are usually milled to uniform thicknesses of 0.3-0.6 mm around the whole tooth preparation. This may not provide uniform thickness or appropriate support for the veneering porcelain. To prevent these problems, the dual-scan technique demonstrates an alternative that allows the restorative team to customize zirconia CAD/CAM frameworks with adequate porcelain thickness and support in a simple manner.

Establishing a communications link between two different, incompatible, personal computers: with practical examples and illustrations and program code.

PubMed

Davidson, R W

1985-01-01

The increasing need to communicate to exchange data can be handled by personal microcomputers. The necessity for the transference of information stored in one type of personal computer to another type of personal computer is often encountered in the process of integrating multiple sources of information stored in different and incompatible computers in Medical Research and Practice. A practical example is demonstrated with two relatively inexpensive commonly used computers, the IBM PC jr. and the Apple IIe. The basic input/output (I/O) interface chip for serial communication for each computer are joined together using a Null connector and cable to form a communications link. Using BASIC (Beginner's All-purpose Symbolic Instruction Code) Computer Language and the Disk Operating System (DOS) the communications handshaking protocol and file transfer is established between the two computers. The BASIC programming languages used are Applesoft (Apple Personal Computer) and PC BASIC (IBM Personal computer).

Radiation hardened microprocessor for small payloads

NASA Technical Reports Server (NTRS)

Shah, Ravi

1993-01-01

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

The research of data acquisition system for Raman spectrometer

NASA Astrophysics Data System (ADS)

Cui, Xiao; Guo, Pan; Zhang, Yinchao; Chen, Siying; Chen, He; Chen, Wenbo

2011-11-01

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*105(S-1PW-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

Time Division Multiplexing of Semiconductor Qubits

NASA Astrophysics Data System (ADS)

Jarratt, Marie Claire; Hornibrook, John; Croot, Xanthe; Watson, John; Gardner, Geoff; Fallahi, Saeed; Manfra, Michael; Reilly, David

Readout chains, comprising resonators, amplifiers, and demodulators, are likely to be precious resources in quantum computing architectures. The potential to share readout resources is contingent on realising efficient means of time-division multiplexing (TDM) schemes that are compatible with quantum computing. Here, we demonstrate TDM using a GaAs quantum dot device with multiple charge sensors. Our device incorporates chip-level switches that do not load the impedance matching network. When used in conjunction with frequency multiplexing, each frequency tone addresses multiple time-multiplexed qubits, vastly increasing the capacity of a single readout line.

Leadership & Management for the Military Librarian. Proceedings of the Twenty-Fifth Annual Military Librarians Workshop, 14-16 October 1981

DTIC Science & Technology

1981-10-01

The congre- gation was just enthralled by this. One lady in the balcony got the call that very morning, jumped over the balcony, and shouted ...now we have satellite photographs and those are so good that when you fully enhance them by computer you can actually tell how high the waves are out...massively parallel processor being built for NASA . It consists of an arrLy of 120 by 128 of these chips. There are 16,384 computers and, of course, one

Restructurable VLSI Program

DTIC Science & Technology

1981-03-31

logic testing element and a concomitant testability criterion ideally suited to dynamic circuit applications and appro- priate for automatic computer...making connections automatically . PF is an experimental feature which provides users with only four different chip sizes (full, half, quarter, and eighth...initial solution is found constructively which is improved by pair-wise swapping. Results show, however, that the constructive initial sorter , which

The Department of Defense Very High Speed Integrated Circuit (VHSIC) Technology Availability Program Plan for the Committees on Armed Services United States Congress.

DTIC Science & Technology

1986-06-30

features of computer aided design systems and statistical quality control procedures that are generic to chip sets and processes. RADIATION HARDNESS -The...System PSP Programmable Signal Processor SSI Small Scale Integration ." TOW Tube Launched, Optically Tracked, Wire Guided TTL Transistor Transitor Logic

The Escrowed Encryption Standard: The Clipper Chip and Civil Liberties.

ERIC Educational Resources Information Center

Diamond, Ted

1994-01-01

The federal Escrowed Encryption Standard (EES) has been opposed by civil liberties advocates and the computer industry. The author argues that the standard does not threaten privacy as long as its use remains voluntary, alternative forms of encryption are allowed, and the power of government to intercept transmission is kept in check. (20…

SOLVE: a computer program for determining the maximum value of hardwood sawlogs

Treesearch

Edward L. Adams; Edward L. Adams

1972-01-01

This paper presents the SOLVE system in detail as an aid to users who might want to make changes in the program. These changes might include: (1) adapting the program to a softwood sawmill; (2) consideration of products other than chips, lumber, and sawed timber; and (3) adapting the program to new data and procedures.

Solid-state Isotopic Power Source for Computer Memory Chips

NASA Technical Reports Server (NTRS)

Brown, Paul M.

1993-01-01

Recent developments in materials technology now make it possible to fabricate nonthermal thin-film radioisotopic energy converters (REC) with a specific power of 24 W/kg and a 10 year working life at 5 to 10 watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25 percent which is two to three times greater than the 6 to 8 percent capabilities of current thermoelectric systems. Radio isotopic energy converters have the potential to meet many future space power requirements for a wide variety of applications with less mass, better efficiency, and less total area than other power conversion options. These benefits result in significant dollar savings over the projected mission lifetime.

Future computing platforms for science in a power constrained era

DOE PAGES

Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; ...

2015-12-23

Power consumption will be a key constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics (HEP). This makes performance-per-watt a crucial metric for selecting cost-efficient computing solutions. For this paper, we have done a wide survey of current and emerging architectures becoming available on the market including x86-64 variants, ARMv7 32-bit, ARMv8 64-bit, Many-Core and GPU solutions, as well as newer System-on-Chip (SoC) solutions. We compare performance and energy efficiency using an evolving set of standardized HEP-related benchmarks and power measurement techniques we have been developing. In conclusion, we evaluate the potentialmore » for use of such computing solutions in the context of DHTC systems, such as the Worldwide LHC Computing Grid (WLCG).« less

Combining on-chip synthesis of a focused combinatorial library with computational target prediction reveals imidazopyridine GPCR ligands.

PubMed

Reutlinger, Michael; Rodrigues, Tiago; Schneider, Petra; Schneider, Gisbert

2014-01-07

Using the example of the Ugi three-component reaction we report a fast and efficient microfluidic-assisted entry into the imidazopyridine scaffold, where building block prioritization was coupled to a new computational method for predicting ligand-target associations. We identified an innovative GPCR-modulating combinatorial chemotype featuring ligand-efficient adenosine A1/2B and adrenergic α1A/B receptor antagonists. Our results suggest the tight integration of microfluidics-assisted synthesis with computer-based target prediction as a viable approach to rapidly generate bioactivity-focused combinatorial compound libraries with high success rates. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FPGA accelerator for protein secondary structure prediction based on the GOR algorithm

PubMed Central

2011-01-01

Background Protein is an important molecule that performs a wide range of functions in biological systems. Recently, the protein folding attracts much more attention since the function of protein can be generally derived from its molecular structure. The GOR algorithm is one of the most successful computational methods and has been widely used as an efficient analysis tool to predict secondary structure from protein sequence. However, the execution time is still intolerable with the steep growth in protein database. Recently, FPGA chips have emerged as one promising application accelerator to accelerate bioinformatics algorithms by exploiting fine-grained custom design. Results In this paper, we propose a complete fine-grained parallel hardware implementation on FPGA to accelerate the GOR-IV package for 2D protein structure prediction. To improve computing efficiency, we partition the parameter table into small segments and access them in parallel. We aggressively exploit data reuse schemes to minimize the need for loading data from external memory. The whole computation structure is carefully pipelined to overlap the sequence loading, computing and back-writing operations as much as possible. We implemented a complete GOR desktop system based on an FPGA chip XC5VLX330. Conclusions The experimental results show a speedup factor of more than 430x over the original GOR-IV version and 110x speedup over the optimized version with multi-thread SIMD implementation running on a PC platform with AMD Phenom 9650 Quad CPU for 2D protein structure prediction. However, the power consumption is only about 30% of that of current general-propose CPUs. PMID:21342582

WDM package enabling high-bandwidth optical intrasystem interconnects for high-performance computer systems

NASA Astrophysics Data System (ADS)

Schrage, J.; Soenmez, Y.; Happel, T.; Gubler, U.; Lukowicz, P.; Mrozynski, G.

2006-02-01

From long haul, metro access and intersystem links the trend goes to applying optical interconnection technology at increasingly shorter distances. Intrasystem interconnects such as data busses between microprocessors and memory blocks are still based on copper interconnects today. This causes a bottleneck in computer systems since the achievable bandwidth of electrical interconnects is limited through the underlying physical properties. Approaches to solve this problem by embedding optical multimode polymer waveguides into the board (electro-optical circuit board technology, EOCB) have been reported earlier. The principle feasibility of optical interconnection technology in chip-to-chip applications has been validated in a number of projects. For reasons of cost considerations waveguides with large cross sections are used in order to relax alignment requirements and to allow automatic placement and assembly without any active alignment of components necessary. On the other hand the bandwidth of these highly multimodal waveguides is restricted due to mode dispersion. The advance of WDM technology towards intrasystem applications will provide sufficiently high bandwidth which is required for future high-performance computer systems: Assuming that, for example, 8 wavelength-channels with 12Gbps (SDR1) each are given, then optical on-board interconnects with data rates a magnitude higher than the data rates of electrical interconnects for distances typically found at today's computer boards and backplanes can be realized. The data rate will be twice as much, if DDR2 technology is considered towards the optical signals as well. In this paper we discuss an approach for a hybrid integrated optoelectronic WDM package which might enable the application of WDM technology to EOCB.

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

NASA Astrophysics Data System (ADS)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Fast and Precise Emulation of Stochastic Biochemical Reaction Networks With Amplified Thermal Noise in Silicon Chips.

PubMed

Kim, Jaewook; Woo, Sung Sik; Sarpeshkar, Rahul

2018-04-01

The analysis and simulation of complex interacting biochemical reaction pathways in cells is important in all of systems biology and medicine. Yet, the dynamics of even a modest number of noisy or stochastic coupled biochemical reactions is extremely time consuming to simulate. In large part, this is because of the expensive cost of random number and Poisson process generation and the presence of stiff, coupled, nonlinear differential equations. Here, we demonstrate that we can amplify inherent thermal noise in chips to emulate randomness physically, thus alleviating these costs significantly. Concurrently, molecular flux in thermodynamic biochemical reactions maps to thermodynamic electronic current in a transistor such that stiff nonlinear biochemical differential equations are emulated exactly in compact, digitally programmable, highly parallel analog "cytomorphic" transistor circuits. For even small-scale systems involving just 80 stochastic reactions, our 0.35-μm BiCMOS chips yield a 311× speedup in the simulation time of Gillespie's stochastic algorithm over COPASI, a fast biochemical-reaction software simulator that is widely used in computational biology; they yield a 15 500× speedup over equivalent MATLAB stochastic simulations. The chip emulation results are consistent with these software simulations over a large range of signal-to-noise ratios. Most importantly, our physical emulation of Poisson chemical dynamics does not involve any inherently sequential processes and updates such that, unlike prior exact simulation approaches, they are parallelizable, asynchronous, and enable even more speedup for larger-size networks.

Miniaturized devices towards an integrated lab-on-a-chip platform for DNA diagnostics

NASA Astrophysics Data System (ADS)

Kaprou, G.; Papadakis, G.; Kokkoris, G.; Papadopoulos, V.; Kefala, I.; Papageorgiou, D.; Gizeli, E.; Tserepi, A.

2015-06-01

Microfluidics is an emerging technology enabling the development of Lab-on-a-chip (LOC) systems for clinical diagnostics, drug discovery and screening, food safety and environmental analysis. LOC systems integrate and scale down one or several laboratory functions on a single chip of a few mm2 to cm2 in size, and account for many advantages on biochemical analyses, such as low sample and reagent consumption, low cost, reduced analysis time, portability and point-of-need compatibility. Currently, available nucleic acid diagnostic tests take advantage of Polymerase Chain Reaction (PCR) that allows exponential amplification of portions of nucleic acid sequences that can be used as indicators for the identification of various diseases. Here, we present a comparison between static chamber and continuous flow miniaturized PCR devices, in terms of energy consumption for devices fabricated on the same material stack, with identical sample volume and channel dimensions. The comparison is implemented by a computational study coupling heat transfer in both solid and fluid, mass conservation of species, and joule heating. Based on the conclusions of this study, we develop low-cost and fast DNA amplification devices for both PCR and isothermal amplification, and we implement them in the detection of mutations related to breast cancer. The devices are fabricated by mass production amenable technologies on printed circuit board (PCB) substrates, where copper facilitates the incorporation of on-chip microheaters, defining the thermal zones necessary for PCR or isothermal amplification methods.

Neuromorphic Computing for Very Large Test and Evaluation Data Analysis

DTIC Science & Technology

2014-05-01

analysis and utilization of newly available hardware- based artificial neural network chips. These two aspects of the program are complementary. The...neuromorphic architectures research focused on long term disruptive technologies with high risk but revolutionary potential. The hardware- based neural...today. Overall, hardware- based neural processing research allows us to study the fundamental system and architectural issues relevant for employing

Transparent Conducting Oxides for Infrared Plasmonic Waveguides: ZnO (Preprint)

DTIC Science & Technology

2014-01-15

dependence of mobility (µ) on thickness (d). 15. SUBJECT TERMS microcavity; polariton ; strong coupling; ZnO 16. SECURITY CLASSIFICATION OF: 17...dimensions below the diffraction limit. Keywords: microcavity; polariton ; strong coupling; ZnO INTRODUCTION The field of plasmonics has received...optical computing and chips, enhanced signal detectors, etc3. Surface plasmon polaritons (SPPs) are quasi-particles or excitations that result from

Systolic VLSI Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

1986-01-01

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Computational Cognition and Robust Decision Making

DTIC Science & Technology

2013-03-06

much more powerful neuromorphic chips than current state of the art. L. Chua 10 DISTRIBUTION STATEMENT A – Unclassified, Unlimited Distribution 2...Cognition Program DARPA (Gill Pratt) • Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) Program IARPA (Brad Minnery...2012 - Four projects at SNU and KAIST co-funded with AOARD DARPA SyNAPSE Program: - Design, fabrication, and demonstration of neuromorphic

User's Manual for Total-Tree Multiproduct Cruise Program

Treesearch

Alexander Clark; Thomas M. Burgan; Richard C. Field; Peter E. Dress

1985-01-01

This interactive computer program uses standard tree-cruise data to estimate the weight and volume of the total tree, saw logs, plylogs, chipping logs, pulpwood, crown firewood, and logging residue in timber stands.Input is cumulative cruise data for tree counts by d.b.h. and height. Output is in tables: board-foot volume by d.b.h.; total-tree and tree-component...

KSC-03pd1235

NASA Image and Video Library

2003-04-24

KENNEDY SPACE CENTER, FLA. - Jim Lloyd, with the Mars Exploration Rover (MER) program, places on MER-1 a computer chip with about 35,000 laser-engraved signatures of visitors to the rovers at the Jet Propulsion Laboratory. The signatures include those of senators, artists, and John Glenn. The identical Mars rovers are scheduled to launch June 5 and June 25 from Cape Canaveral Air Force Station.

High Resolution Imaging Testbed Utilizing Sodium Laser Guide Star Adaptive Optics: The Real Time Wavefront Reconstructor Computer

DTIC Science & Technology

2008-07-31

Unlike the Lyrtech, each DSP on a Bittware board offers 3 MB of on-chip memory and 3 GFLOPs of 32-bit peak processing power. Based on the performance...Each NVIDIA 8800 Ultra features 576 GFLOPS on 128 612-MHz single-precision floating-point SIMD processors, arranged in 16 clusters of eight. Each

Computer Chips and Paper Clips. Technology and Women's Employment. Volume II. Case Studies and Policy Perspectives.

ERIC Educational Resources Information Center

Hartmann, Heidi I., Ed.; And Others

This volume contains 12 papers commissioned by the Panel on Technology and Women's Employment. "Technology, Women, and Work: Policy Perspectives" (Eli Ginzberg) is an overview that provides a context for the volume. The four case studies in Part II describe the impact of information technology in the insurance industry, among bookkeepers, among…

European Science Notes Information Bulletin Reports on Current European and Middle Eastern Science

DTIC Science & Technology

1992-01-01

evclopment in the Abbey-Polymer Processing and Properties ................... 524 J, Magill Corrosion and Protection Centre at the University of...34* Software Engineering and microprocessors and communication chips. The Information Processing Systems recently announced T9000 microprocessor will...computational fluid dynamics, struc- In addition to general and special-purpose tural mechanics, partial differential equations, processing , Europe has a

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE PAGES

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

2017-02-22

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

PubMed

Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

2018-02-01

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan R.

2015-05-01

New radar applications need to perform complex algorithms and process large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression for real-time transceiver optimization are presented, they are based on a System-on-Chip architecture for Xilinx devices. This study also evaluates the performance of dedicated coprocessor as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through the high performance AXI buses, to perform floating-point operations, control the processing blocks, and communicate with external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band tested together with a low-cost channel emulator for different types of waveforms.

Real-time time-division color electroholography using a single GPU and a USB module for synchronizing reference light.

PubMed

Araki, Hiromitsu; Takada, Naoki; Niwase, Hiroaki; Ikawa, Shohei; Fujiwara, Masato; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2015-12-01

We propose real-time time-division color electroholography using a single graphics processing unit (GPU) and a simple synchronization system of reference light. To facilitate real-time time-division color electroholography, we developed a light emitting diode (LED) controller with a universal serial bus (USB) module and the drive circuit for reference light. A one-chip RGB LED connected to a personal computer via an LED controller was used as the reference light. A single GPU calculates three computer-generated holograms (CGHs) suitable for red, green, and blue colors in each frame of a three-dimensional (3D) movie. After CGH calculation using a single GPU, the CPU can synchronize the CGH display with the color switching of the one-chip RGB LED via the LED controller. Consequently, we succeeded in real-time time-division color electroholography for a 3D object consisting of around 1000 points per color when an NVIDIA GeForce GTX TITAN was used as the GPU. Furthermore, we implemented the proposed method in various GPUs. The experimental results showed that the proposed method was effective for various GPUs.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Carbon-ionogel supercapacitors for integrated microelectronics.

PubMed

Leung, Greg; Smith, Leland; Lau, Jonathan; Dunn, Bruce; Chui, Chi On

2016-01-22

To exceed the performance limits of dielectric capacitors in microelectronic circuit applications, we design and demonstrate on-chip coplanar electric double-layer capacitors (EDLCs), or supercapacitors, employing carbon-coated gold electrodes with ionogel electrolyte. The formation of carbon-coated microelectrodes is accomplished by solution processing and results in a ten-fold increase in EDLC capacitance compared to bare gold electrodes without carbon. At frequencies up to 10 Hz, an areal capacitance of 2.1 pF μm(-2) is achieved for coplanar carbon-ionogel EDLCs with 10 μm electrode gaps and 0.14 mm(2) electrode area. Our smallest devices, comprised of 5 μm electrode gaps and 80 μm(2) of active electrode area, reach areal capacitance values of ∼0.3 pF μm(-2) at frequencies up to 1 kHz, even without carbon. To our knowledge, these are the highest reported values to date for on-chip EDLCs with sub-mm(2) areas. A physical EDLC model is developed through the use of computer-aided simulations for design exploration and optimization of coplanar EDLCs. Through modeling and comparison with experimental data, we highlight the importance of reducing the electrode gap and electrolyte resistance to achieve maximum performance from on-chip EDLCs.

Improved chip design for integrated solid-phase microextraction in on-line proteomic sample preparation.

PubMed

Bergkvist, Jonas; Ekström, Simon; Wallman, Lars; Löfgren, Mikael; Marko-Varga, György; Nilsson, Johan; Laurell, Thomas

2002-04-01

A recently introduced silicon microextraction chip (SMEC), used for on-line proteomic sample preparation, has proved to facilitate the process of protein identification by sample clean up and enrichment of peptides. It is demonstrated that a novel grid-SMEC design improves the operating characteristics for solid-phase microextraction, by reducing dispersion effects and thereby improving the sample preparation conditions. The structures investigated in this paper are treated both numerically and experimentally. The numerical approach is based on finite element analysis of the microfluidic flow in the microchip. The analysis is accomplished by use of the computational fluid dynamics-module FLOTRAN in the ANSYS software package. The modeling and analysis of the previously reported weir-SMEC design indicates some severe drawbacks, that can be reduced by changing the microextraction chip geometry to the grid-SMEC design. The overall analytical performance was thereby improved and also verified by experimental work. Matrix-assisted laser desorption/ionization mass spectra of model peptides extracted from both the weir-SMEC and the new grid-SMEC support the numerical analysis results. Further use of numerical modeling and analysis of the SMEC structures is also discussed and suggested in this work.

Carbon-ionogel supercapacitors for integrated microelectronics

NASA Astrophysics Data System (ADS)

Leung, Greg; Smith, Leland; Lau, Jonathan; Dunn, Bruce; Chui, Chi On

2016-01-01

To exceed the performance limits of dielectric capacitors in microelectronic circuit applications, we design and demonstrate on-chip coplanar electric double-layer capacitors (EDLCs), or supercapacitors, employing carbon-coated gold electrodes with ionogel electrolyte. The formation of carbon-coated microelectrodes is accomplished by solution processing and results in a ten-fold increase in EDLC capacitance compared to bare gold electrodes without carbon. At frequencies up to 10 Hz, an areal capacitance of 2.1 pF μm-2 is achieved for coplanar carbon-ionogel EDLCs with 10 μm electrode gaps and 0.14 mm2 electrode area. Our smallest devices, comprised of 5 μm electrode gaps and 80 μm2 of active electrode area, reach areal capacitance values of ˜0.3 pF μm-2 at frequencies up to 1 kHz, even without carbon. To our knowledge, these are the highest reported values to date for on-chip EDLCs with sub-mm2 areas. A physical EDLC model is developed through the use of computer-aided simulations for design exploration and optimization of coplanar EDLCs. Through modeling and comparison with experimental data, we highlight the importance of reducing the electrode gap and electrolyte resistance to achieve maximum performance from on-chip EDLCs.

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

PubMed Central

Zhang, Xiang; Chen, Zhangwei

2013-01-01

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels. PMID:23459385

Fabrication of an inexpensive, implantable cooling device for reversible brain deactivation in animals ranging from rodents to primates

PubMed Central

Cooke, Dylan F.; Goldring, Adam B.; Yamayoshi, Itsukyo; Tsourkas, Phillippos; Recanzone, Gregg H.; Tiriac, Alex; Pan, Tingrui; Simon, Scott I.

2012-01-01

We have developed a compact and lightweight microfluidic cooling device to reversibly deactivate one or more areas of the neocortex to examine its functional macrocircuitry as well as behavioral and cortical plasticity. The device, which we term the “cooling chip,” consists of thin silicone tubing (through which chilled ethanol is circulated) embedded in mechanically compliant polydimethylsiloxane (PDMS). PDMS is tailored to compact device dimensions (as small as 21 mm3) that precisely accommodate the geometry of the targeted cortical area. The biocompatible design makes it suitable for both acute preparations and chronic implantation for long-term behavioral studies. The cooling chip accommodates an in-cortex microthermocouple measuring local cortical temperature. A microelectrode may be used to record simultaneous neural responses at the same location. Cortex temperature is controlled by computer regulation of the coolant flow, which can achieve a localized cortical temperature drop from 37 to 20°C in less than 3 min and maintain target temperature to within ±0.3°C indefinitely. Here we describe cooling chip fabrication and performance in mediating cessation of neural signaling in acute preparations of rodents, ferrets, and primates. PMID:22402651

Characterization and Modeling of Fine-Pitch Copper Ball Bonding on a Cu/Low- k Chip

NASA Astrophysics Data System (ADS)

Che, F. X.; Wai, L. C.; Zhang, Xiaowu; Chai, T. C.

2015-02-01

Cu ball bonding faces more challenges than Au ball bonding, for example, excessive deformation of the bond pad and damage of Cu/low- k structures, because of the much greater hardness of Cu free air balls. In this study, dynamic finite-element analysis (FEA) modeling with displacement control was developed to simulate the ball-bonding process. The three-dimensional (3D) FEA simulation results were confirmed by use of stress-measurement data, obtained by use of stress sensors built into the test chip. Stress comparison between two-dimensional (2D) and 3D FEA models showed the 2D plain strain model to be a reasonable and effective model for simulation of the ball-bonding process without loss of accuracy; it also saves computing resources. The 2D FEA model developed was then used in studies of a Cu/low- k chip to find ways of reducing Al bond pad deformation and stresses of low- k structures. The variables studied included Al pad properties, capillary geometry, bond pad design (Al pad thickness, Al pad coated with Ni layer), and the effect of ultrasonic bonding power.

RNA–protein binding kinetics in an automated microfluidic reactor

PubMed Central

Ridgeway, William K.; Seitaridou, Effrosyni; Phillips, Rob; Williamson, James R.

2009-01-01

Microfluidic chips can automate biochemical assays on the nanoliter scale, which is of considerable utility for RNA–protein binding reactions that would otherwise require large quantities of proteins. Unfortunately, complex reactions involving multiple reactants cannot be prepared in current microfluidic mixer designs, nor is investigation of long-time scale reactions possible. Here, a microfluidic ‘Riboreactor’ has been designed and constructed to facilitate the study of kinetics of RNA–protein complex formation over long time scales. With computer automation, the reactor can prepare binding reactions from any combination of eight reagents, and is optimized to monitor long reaction times. By integrating a two-photon microscope into the microfluidic platform, 5-nl reactions can be observed for longer than 1000 s with single-molecule sensitivity and negligible photobleaching. Using the Riboreactor, RNA–protein binding reactions with a fragment of the bacterial 30S ribosome were prepared in a fully automated fashion and binding rates were consistent with rates obtained from conventional assays. The microfluidic chip successfully combines automation, low sample consumption, ultra-sensitive fluorescence detection and a high degree of reproducibility. The chip should be able to probe complex reaction networks describing the assembly of large multicomponent RNPs such as the ribosome. PMID:19759214

Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography

NASA Astrophysics Data System (ADS)

Sturtevant, John L.; Liubich, Vlad; Gupta, Rachit

2016-04-01

Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target for a single design layer. Strictly speaking, this quantity is not directly measurable in the fab. What is of vital importance is the relative edge placement errors between different design layers, and in the era of multipatterning, the different constituent mask sublayers for a single design layer. The critical dimensions (CD) and overlay between two layers can be measured in the fab, and there has always been a strong emphasis on control of overlay between design layers. The progress in this realm has been remarkable, accelerated in part at least by the proliferation of multipatterning, which reduces the available overlay budget by introducing a coupling of overlay and CD errors for the target layer. Computational lithography makes possible the full-chip assessment of two-layer edge to edge distances and two-layer contact overlap area. We will investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour-to-contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic CD-overlay process window (PW) for edge placement errors. For double patterning, the interaction of 4-layer CD and overlay errors is very complex, but we illustrate that not only can full-chip verification identify potential two-layer hotspots, the optical proximity correction engine can act to mitigate such hotspots and enlarge the joint CD-overlay PW.

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bergman, Keren

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformationalmore » advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.« less

Microcontroller interface for diode array spectrometry

NASA Astrophysics Data System (ADS)

Aguo, L.; Williams, R. R.

An alternative to bus-based computer interfacing is presented using diode array spectrometry as a typical application. The new interface consists of an embedded single-chip microcomputer, known as a microcontroller, which provides all necessary digital I/O and analog-to-digital conversion (ADC) along with an unprecedented amount of intelligence. Communication with a host computer system is accomplished by a standard serial interface so this type of interfacing is applicable to a wide range of personal and minicomputers and can be easily networked. Data are acquired asynchronousty and sent to the host on command. New operating modes which have no traditional counterparts are presented.

Modelling of Molecular Structures and Properties. Proceedings of the International Meeting of Physical Chemistry on Modeling of Molecular Structures and Properties in Physical Chemistry and Biophysics Organized by the Division de Chimie Physique of the Societe Francaise de Chimie Held in Nancy, France on 11-15 September 1989

DTIC Science & Technology

1990-01-01

expert systems, "intelligent" computer-aided instruction , symbolic learning . These aspects will be discussed, focusing on the specific problems the...VLSI chips) according to preliminary specifications. Finally ES are also used in computer-aided instruction (CAI) due to their ability of... instructions to process controllers), academic teaching (for mathematics , physics, foreign language, etc.). Domains of application The different

Special purpose computer system with highly parallel pipelines for flow visualization using holography technology

NASA Astrophysics Data System (ADS)

Masuda, Nobuyuki; Sugie, Takashige; Ito, Tomoyoshi; Tanaka, Shinjiro; Hamada, Yu; Satake, Shin-ichi; Kunugi, Tomoaki; Sato, Kazuho

2010-12-01

We have designed a PC cluster system with special purpose computer boards for visualization of fluid flow using digital holographic particle tracking velocimetry (DHPTV). In this board, there is a Field Programmable Gate Array (FPGA) chip in which is installed a pipeline for calculating the intensity of an object from a hologram by fast Fourier transform (FFT). This cluster system can create 1024 reconstructed images from a 1024×1024-grid hologram in 0.77 s. It is expected that this system will contribute to the analysis of fluid flow using DHPTV.

Wireless Sensor Node for Autonomous Monitoring and Alerts in Remote Environments

NASA Technical Reports Server (NTRS)

Panangadan, Anand V. (Inventor); Monacos, Steve P. (Inventor)

2015-01-01

A method, apparatus, system, and computer program products provides personal alert and tracking capabilities using one or more nodes. Each node includes radio transceiver chips operating at different frequency ranges, a power amplifier, sensors, a display, and embedded software. The chips enable the node to operate as either a mobile sensor node or a relay base station node while providing a long distance relay link between nodes. The power amplifier enables a line-of-sight communication between the one or more nodes. The sensors provide a GPS signal, temperature, and accelerometer information (used to trigger an alert condition). The embedded software captures and processes the sensor information, provides a multi-hop packet routing protocol to relay the sensor information to and receive alert information from a command center, and to display the alert information on the display.

On-chip, photon-number-resolving, telecommunication-band detectors for scalable photonic information processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gerrits, Thomas; Lita, Adriana E.; Calkins, Brice

Integration is currently the only feasible route toward scalable photonic quantum processing devices that are sufficiently complex to be genuinely useful in computing, metrology, and simulation. Embedded on-chip detection will be critical to such devices. We demonstrate an integrated photon-number-resolving detector, operating in the telecom band at 1550 nm, employing an evanescently coupled design that allows it to be placed at arbitrary locations within a planar circuit. Up to five photons are resolved in the guided optical mode via absorption from the evanescent field into a tungsten transition-edge sensor. The detection efficiency is 7.2{+-}0.5 %. The polarization sensitivity of themore » detector is also demonstrated. Detailed modeling of device designs shows a clear and feasible route to reaching high detection efficiencies.« less

A survey of CPU-GPU heterogeneous computing techniques

DOE PAGES

Mittal, Sparsh; Vetter, Jeffrey S.

2015-07-04

As both CPU and GPU become employed in a wide range of applications, it has been acknowledged that both of these processing units (PUs) have their unique features and strengths and hence, CPU-GPU collaboration is inevitable to achieve high-performance computing. This has motivated significant amount of research on heterogeneous computing techniques, along with the design of CPU-GPU fused chips and petascale heterogeneous supercomputers. In this paper, we survey heterogeneous computing techniques (HCTs) such as workload-partitioning which enable utilizing both CPU and GPU to improve performance and/or energy efficiency. We review heterogeneous computing approaches at runtime, algorithm, programming, compiler and applicationmore » level. Further, we review both discrete and fused CPU-GPU systems; and discuss benchmark suites designed for evaluating heterogeneous computing systems (HCSs). Furthermore, we believe that this paper will provide insights into working and scope of applications of HCTs to researchers and motivate them to further harness the computational powers of CPUs and GPUs to achieve the goal of exascale performance.« less

Colt: an experiment in wormhole run-time reconfiguration

NASA Astrophysics Data System (ADS)

Bittner, Ray; Athanas, Peter M.; Musgrove, Mark

1996-10-01

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

A survey of CPU-GPU heterogeneous computing techniques

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S.

As both CPU and GPU become employed in a wide range of applications, it has been acknowledged that both of these processing units (PUs) have their unique features and strengths and hence, CPU-GPU collaboration is inevitable to achieve high-performance computing. This has motivated significant amount of research on heterogeneous computing techniques, along with the design of CPU-GPU fused chips and petascale heterogeneous supercomputers. In this paper, we survey heterogeneous computing techniques (HCTs) such as workload-partitioning which enable utilizing both CPU and GPU to improve performance and/or energy efficiency. We review heterogeneous computing approaches at runtime, algorithm, programming, compiler and applicationmore » level. Further, we review both discrete and fused CPU-GPU systems; and discuss benchmark suites designed for evaluating heterogeneous computing systems (HCSs). Furthermore, we believe that this paper will provide insights into working and scope of applications of HCTs to researchers and motivate them to further harness the computational powers of CPUs and GPUs to achieve the goal of exascale performance.« less

Microelectromechanical reprogrammable logic device.

PubMed

Hafiz, M A A; Kosuru, L; Younis, M I

2016-03-29

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

Microelectromechanical reprogrammable logic device

PubMed Central

Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

2016-01-01

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

Multicore Challenges and Benefits for High Performance Scientific Computing

DOE PAGES

Nielsen, Ida M. B.; Janssen, Curtis L.

2008-01-01

Until recently, performance gains in processors were achieved largely by improvements in clock speeds and instruction level parallelism. Thus, applications could obtain performance increases with relatively minor changes by upgrading to the latest generation of computing hardware. Currently, however, processor performance improvements are realized by using multicore technology and hardware support for multiple threads within each core, and taking full advantage of this technology to improve the performance of applications requires exposure of extreme levels of software parallelism. We will here discuss the architecture of parallel computers constructed from many multicore chips as well as techniques for managing the complexitymore » of programming such computers, including the hybrid message-passing/multi-threading programming model. We will illustrate these ideas with a hybrid distributed memory matrix multiply and a quantum chemistry algorithm for energy computation using Møller–Plesset perturbation theory.« less

Uncertain behaviours of integrated circuits improve computational performance.

PubMed

Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

2015-11-20

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

A CLIPS based personal computer hardware diagnostic system

NASA Technical Reports Server (NTRS)

Whitson, George M.

1991-01-01

Often the person designated to repair personal computers has little or no knowledge of how to repair a computer. Described here is a simple expert system to aid these inexperienced repair people. The first component of the system leads the repair person through a number of simple system checks such as making sure that all cables are tight and that the dip switches are set correctly. The second component of the system assists the repair person in evaluating error codes generated by the computer. The final component of the system applies a large knowledge base to attempt to identify the component of the personal computer that is malfunctioning. We have implemented and tested our design with a full system to diagnose problems for an IBM compatible system based on the 8088 chip. In our tests, the inexperienced repair people found the system very useful in diagnosing hardware problems.

Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

PubMed Central

Hwang, Wen-Jyi; Cheng, Shih-Chang; Cheng, Chau-Jern

2011-01-01

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system. PMID:22163688

A site oriented supercomputer for theoretical physics: The Fermilab Advanced Computer Program Multi Array Processor System (ACMAPS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nash, T.; Atac, R.; Cook, A.

1989-03-06

The ACPMAPS multipocessor is a highly cost effective, local memory parallel computer with a hypercube or compound hypercube architecture. Communication requires the attention of only the two communicating nodes. The design is aimed at floating point intensive, grid like problems, particularly those with extreme computing requirements. The processing nodes of the system are single board array processors, each with a peak power of 20 Mflops, supported by 8 Mbytes of data and 2 Mbytes of instruction memory. The system currently being assembled has a peak power of 5 Gflops. The nodes are based on the Weitek XL Chip set. Themore » system delivers performance at approximately $300/Mflop. 8 refs., 4 figs.« less

Planned development of a 3D computer based on free-space optical interconnects

NASA Astrophysics Data System (ADS)

Neff, John A.; Guarino, David R.

1994-05-01

Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

A System for Video Surveillance and Monitoring CMU VSAM Final Report

DTIC Science & Technology

1999-11-30

motion-based skeletonization, neural network , spatio-temporal salience Patterns inside image chips, spurious motion rejection, model -based... network of sensors with respect to the model coordinate system, computation of 3D geolocation estimates, and graphical display of object hypotheses...rithms have been developed. The first uses view dependent visual properties to train a neural network classifier to recognize four classes: single

A Microprocessor-Controlled Data Acquisition System for the Federal Scientific Model UA-500-1 Ubiquitous Spectrum Analyzer

DTIC Science & Technology

1976-09-01

Model AN/ UGC -59A teletype and paper-tape punch console. This unit is connected with the Intellec 8 computer and punching operations are controlled by...order to use this program, the microprocessor would have to be one of the many types on the market that make use of the INTEL 8008-1 CPD chip. The use

Full-tree utilization of southern pine and hardwoods growing on southern pine sites

Treesearch

Peter Koch

1974-01-01

in 1963, approximately 30 percent of the dry weight of above- and below-ground parts of southern pine trees ended as dry surfaced lumber or paper; the remaining 70 percent was largely unused. By 1980, computer-controlled chipping headrigs, thin-kerf saws, lamination of lumber from rotary-cut veneer, high-yield pulping processes, and more intensive use of roots, bark,...

CREE: Making the Switch

ScienceCinema

Grider, David; Palmer, John

2018-05-11

CREE, with the help of ARPA-E funding, has developed a Silicon Carbide (SIC) transistor which can be used to create solid state transformers capable of meeting the unique needs of the emerging smart grid. SIC transistors are different from common silicon computer chips in that they handle grid scale voltages with ease and their high frequency switching is well suited to the intermittent nature of renewable energy generation.

Whole-tree utilization of southern pine advanced by developments in mechanical conversion

Treesearch

P. Koch

1973-01-01

In 1963 approximately 30 percent of the dry weight of above- and below-ground parts of southern pine trees ended as dry-surfaced lumber or paper; the remaining 70 percent was largely unused. By 1980, computer-controlled chipping headrigs, thin-kerf saws, lamination of lumber from rotary-cut veneer, high-yield pulping processes, and more intensive use of roots, bark,...

Whole-tree utilization of southern pine advanced by developments in mechanical conversion

Treesearch

Peter Koch

1973-01-01

In 1963 approximately 30 percent of the dry weight of aboe- and below-ground parts of southern pine trees ended as dry-surfaced lumber or paper; the remaining 70 percent was largely unused. By 1980, computer-controlled chipping headrigs, think-kerf saws, lamination of lumber from rotary-cut veneer, high-yield pulping processes, and more intensive use of roots, bark,...

Nonvolatile Array Of Synapses For Neural Network

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1993-01-01

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors

PubMed Central

Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S.; Raimondi, Manuela T.; Gottardi, Riccardo

2016-01-01

Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized. PMID:27669413

High resolution computational on-chip imaging of biological samples using sparsity constraint (Conference Presentation)

NASA Astrophysics Data System (ADS)

Rivenson, Yair; Wu, Chris; Wang, Hongda; Zhang, Yibo; Ozcan, Aydogan

2017-03-01

Microscopic imaging of biological samples such as pathology slides is one of the standard diagnostic methods for screening various diseases, including cancer. These biological samples are usually imaged using traditional optical microscopy tools; however, the high cost, bulkiness and limited imaging throughput of traditional microscopes partially restrict their deployment in resource-limited settings. In order to mitigate this, we previously demonstrated a cost-effective and compact lens-less on-chip microscopy platform with a wide field-of-view of >20-30 mm^2. The lens-less microscopy platform has shown its effectiveness for imaging of highly connected biological samples, such as pathology slides of various tissue samples and smears, among others. This computational holographic microscope requires a set of super-resolved holograms acquired at multiple sample-to-sensor distances, which are used as input to an iterative phase recovery algorithm and holographic reconstruction process, yielding high-resolution images of the samples in phase and amplitude channels. Here we demonstrate that in order to reconstruct clinically relevant images with high resolution and image contrast, we require less than 50% of the previously reported nominal number of holograms acquired at different sample-to-sensor distances. This is achieved by incorporating a loose sparsity constraint as part of the iterative holographic object reconstruction. We demonstrate the success of this sparsity-based computational lens-less microscopy platform by imaging pathology slides of breast cancer tissue and Papanicolaou (Pap) smears.

Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors.

PubMed

Iannetti, Laura; D'Urso, Giovanna; Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S; Raimondi, Manuela T; Gottardi, Riccardo; Zunino, Paolo

Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized.

Rapid, portable and cost-effective yeast cell viability and concentration analysis using lensfree on-chip microscopy and machine learning.

PubMed

Feizi, Alborz; Zhang, Yibo; Greenbaum, Alon; Guziak, Alex; Luong, Michelle; Chan, Raymond Yan Lok; Berg, Brandon; Ozkan, Haydar; Luo, Wei; Wu, Michael; Wu, Yichen; Ozcan, Aydogan

2016-11-01

Monitoring yeast cell viability and concentration is important in brewing, baking and biofuel production. However, existing methods of measuring viability and concentration are relatively bulky, tedious and expensive. Here we demonstrate a compact and cost-effective automatic yeast analysis platform (AYAP), which can rapidly measure cell concentration and viability. AYAP is based on digital in-line holography and on-chip microscopy and rapidly images a large field-of-view of 22.5 mm 2 . This lens-free microscope weighs 70 g and utilizes a partially-coherent illumination source and an opto-electronic image sensor chip. A touch-screen user interface based on a tablet-PC is developed to reconstruct the holographic shadows captured by the image sensor chip and use a support vector machine (SVM) model to automatically classify live and dead cells in a yeast sample stained with methylene blue. In order to quantify its accuracy, we varied the viability and concentration of the cells and compared AYAP's performance with a fluorescence exclusion staining based gold-standard using regression analysis. The results agree very well with this gold-standard method and no significant difference was observed between the two methods within a concentration range of 1.4 × 10 5 to 1.4 × 10 6 cells per mL, providing a dynamic range suitable for various applications. This lensfree computational imaging technology that is coupled with machine learning algorithms would be useful for cost-effective and rapid quantification of cell viability and density even in field and resource-poor settings.

Hybrid Silicon Photonic Integration using Quantum Well Intermixing

NASA Astrophysics Data System (ADS)

Jain, Siddharth R.

With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with modulators with a 3-dB bandwidth above 25 GHz, thus demonstrating coarse wavelength division multiplexing transmitter on silicon.

Improving Coolant Effectiveness through Drill Design Optimization in Gundrilling

NASA Astrophysics Data System (ADS)

Woon, K. S.; Tnay, G. L.; Rahman, M.

2018-05-01

Effective coolant application is essential to prevent thermo-mechanical failures of gun drills. This paper presents a novel study that enhances coolant effectiveness in evacuating chips from the cutting zone using a computational fluid dynamic (CFD) method. Drag coefficients and transport behaviour over a wide range of Reynold numbers were first established through a series of vertical drop tests. With these, a CFD model was then developed and calibrated with a set of horizontal drilling tests. Using this CFD model, critical drill geometries that lead to poor chip evacuation including the nose grind contour, coolant hole configuration and shoulder dub-off angle in commercial gun drills are identified. From this study, a new design that consists a 20° inner edge, 15° outer edge, 0° shoulder dub-off and kidney-shaped coolant channel is proposed and experimentally proven to be more superior than all other commercial designs.

Temporal coding in a silicon network of integrate-and-fire neurons.

PubMed

Liu, Shih-Chii; Douglas, Rodney

2004-09-01

Spatio-temporal processing of spike trains by neuronal networks depends on a variety of mechanisms distributed across synapses, dendrites, and somata. In natural systems, the spike trains and the processing mechanisms cohere though their common physical instantiation. This coherence is lost when the natural system is encoded for simulation on a general purpose computer. By contrast, analog VLSI circuits are, like neurons, inherently related by their real-time physics, and so, could provide a useful substrate for exploring neuronlike event-based processing. Here, we describe a hybrid analog-digital VLSI chip comprising a set of integrate-and-fire neurons and short-term dynamical synapses that can be configured into simple network architectures with some properties of neocortical neuronal circuits. We show that, despite considerable fabrication variance in the properties of individual neurons, the chip offers a viable substrate for exploring real-time spike-based processing in networks of neurons.

On-chip polarimetry for high-throughput screening of nanoliter and smaller sample volumes

NASA Technical Reports Server (NTRS)

Bachmann, Brian O. (Inventor); Bornhop, Darryl J. (Inventor); Dotson, Stephen (Inventor)

2012-01-01

A polarimetry technique for measuring optical activity that is particularly suited for high throughput screening employs a chip or substrate (22) having one or more microfluidic channels (26) formed therein. A polarized laser beam (14) is directed onto optically active samples that are disposed in the channels. The incident laser beam interacts with the optically active molecules in the sample, which slightly alter the polarization of the laser beam as it passes multiple times through the sample. Interference fringe patterns (28) are generated by the interaction of the laser beam with the sample and the channel walls. A photodetector (34) is positioned to receive the interference fringe patterns and generate an output signal that is input to a computer or other analyzer (38) for analyzing the signal and determining the rotation of plane polarized light by optically active material in the channel from polarization rotation calculations.

Air Force highly integrated photonics program: development and demonstration of an optically transparent fiber optic network for avionics applications

NASA Astrophysics Data System (ADS)

Whaley, Gregory J.; Karnopp, Roger J.

2010-04-01

The goal of the Air Force Highly Integrated Photonics (HIP) program is to develop and demonstrate single photonic chip components which support a single mode fiber network architecture for use on mobile military platforms. We propose an optically transparent, broadcast and select fiber optic network as the next generation interconnect on avionics platforms. In support of this network, we have developed three principal, single-chip photonic components: a tunable laser transmitter, a 32x32 port star coupler, and a 32 port multi-channel receiver which are all compatible with demanding avionics environmental and size requirements. The performance of the developed components will be presented as well as the results of a demonstration system which integrates the components into a functional network representative of the form factor used in advanced avionics computing and signal processing applications.

A Survey of Architectural Techniques For Improving Cache Power Efficiency

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-worldmore » processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling low-power operation of caches.« less

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller.

PubMed

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADmicroC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62 kbytes of flash memory, 8 kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40 bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100 ns and a minimum time delay between successive events of approximately 9 micros. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller

NASA Astrophysics Data System (ADS)

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADμC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62kbytes of flash memory, 8kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100ns and a minimum time delay between successive events of approximately 9μs. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

Shrink-film microfluidic education modules: Complete devices within minutes

PubMed Central

Nguyen, Diep; McLane, Jolie; Lew, Valerie; Pegan, Jonathan; Khine, Michelle

2011-01-01

As advances in microfluidics continue to make contributions to diagnostics and life sciences, broader awareness of this expanding field becomes necessary. By leveraging low-cost microfabrication techniques that require no capital equipment or infrastructure, simple, accessible, and effective educational modules can be made available for a broad range of educational needs from middle school demonstrations to college laboratory classes. These modules demonstrate key microfluidic concepts such as diffusion and separation as well as “laboratory on-chip” applications including chemical reactions and biological assays. These modules are intended to provide an interdisciplinary hands-on experience, including chip design, fabrication of functional devices, and experiments at the microscale. Consequently, students will be able to conceptualize physics at small scales, gain experience in computer-aided design and microfabrication, and perform experiments—all in the context of addressing real-world challenges by making their own lab-on-chip devices. PMID:21799715

Control of coherent information via on-chip photonic-phononic emitter-receivers.

PubMed

Shin, Heedeuk; Cox, Jonathan A; Jarecki, Robert; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T

2015-03-05

Rapid progress in integrated photonics has fostered numerous chip-scale sensing, computing and signal processing technologies. However, many crucial filtering and signal delay operations are difficult to perform with all-optical devices. Unlike photons propagating at luminal speeds, GHz-acoustic phonons moving at slower velocities allow information to be stored, filtered and delayed over comparatively smaller length-scales with remarkable fidelity. Hence, controllable and efficient coupling between coherent photons and phonons enables new signal processing technologies that greatly enhance the performance and potential impact of integrated photonics. Here we demonstrate a mechanism for coherent information processing based on travelling-wave photon-phonon transduction, which achieves a phonon emit-and-receive process between distinct nanophotonic waveguides. Using this device, physics--which supports GHz frequencies--we create wavelength-insensitive radiofrequency photonic filters with frequency selectivity, narrow-linewidth and high power-handling in silicon. More generally, this emit-receive concept is the impetus for enabling new signal processing schemes.

Powerful timing generator using mono-chip timers: An application to pulsed nuclear magnetic resonance

NASA Astrophysics Data System (ADS)

Saint-Jalmes, Hervé; Barjhoux, Yves

1982-01-01

We present a 10 line-7 MHz timing generator built on a single board around two LSI timer chips interfaced to a 16-bit microcomputer. Once programmed from the host computer, this device is able to generate elaborate logic sequences on its 10 output lines without further interventions from the CPU. Powerful architecture introduces new possibilities over conventional memory-based timing simulators and word generators. Loop control on a given sequence of events, loop nesting, and various logic combinations can easily be implemented through a software interface, using a symbolic command language. Typical applications of such a device range from development, emulation, and test of integrated circuits, circuit boards, and communication systems to pulse-controlled instrumentation (radar, ultrasonic systems). A particular application to a pulsed Nuclear Magnetic Resonance (NMR) spectrometer is presented, along with customization of the device for generating four-channel radio-frequency pulses and the necessary sequence for subsequent data acquisition.

Integrated test system of infrared and laser data based on USB 3.0

NASA Astrophysics Data System (ADS)

Fu, Hui Quan; Tang, Lin Bo; Zhang, Chao; Zhao, Bao Jun; Li, Mao Wen

2017-07-01

Based on USB3.0, this paper presents the design method of an integrated test system for both infrared image data and laser signal data processing module. The core of the design is FPGA logic control, the design uses dual-chip DDR3 SDRAM to achieve high-speed laser data cache, and receive parallel LVDS image data through serial-to-parallel conversion chip, and it achieves high-speed data communication between the system and host computer through the USB3.0 bus. The experimental results show that the developed PC software realizes the real-time display of 14-bit LVDS original image after 14-to-8 bit conversion and JPEG2000 compressed image after decompression in software, and can realize the real-time display of the acquired laser signal data. The correctness of the test system design is verified, indicating that the interface link is normal.

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

On the closed form mechanistic modeling of milling: Specific cutting energy, torque, and power

NASA Astrophysics Data System (ADS)

Bayoumi, A. E.; Yücesan, G.; Hutton, D. V.

1994-02-01

Specific energy in metal cutting, defined as the energy expended in removing a unit volume of workpiece material, is formulated and determined using a previously developed closed form mechanistic force model for milling operations. Cutting power is computed from the cutting torque, cutting force, kinematics of the cutter, and the volumetric material removal rate. Closed form expressions for specific cutting energy were formulated and found to be functions of the process parameters: pressure and friction for both rake and flank surfaces and chip flow angle at the rake face of the tool. Friction is found to play a very important role in cutting torque and power. Experiments were carried out to determine the effects of feedrate, cutting speed, workpiece material, and flank wear land width on specific cutting energy. It was found that the specific cutting energy increases with a decrease in the chip thickness and with an increase in flank wear land.

Double-sided coaxial circuit QED with out-of-plane wiring

NASA Astrophysics Data System (ADS)

Rahamim, J.; Behrle, T.; Peterer, M. J.; Patterson, A.; Spring, P. A.; Tsunoda, T.; Manenti, R.; Tancredi, G.; Leek, P. J.

2017-05-01

Superconducting circuits are well established as a strong candidate platform for the development of quantum computing. In order to advance to a practically useful level, architectures are needed which combine arrays of many qubits with selective qubit control and readout, without compromising on coherence. Here, we present a coaxial circuit quantum electrodynamics architecture in which qubit and resonator are fabricated on opposing sides of a single chip, and control and readout wiring are provided by coaxial wiring running perpendicular to the chip plane. We present characterization measurements of a fabricated device in good agreement with simulated parameters and demonstrating energy relaxation and dephasing times of T1 = 4.1 μs and T2 = 5.7 μs, respectively. The architecture allows for scaling to large arrays of selectively controlled and measured qubits with the advantage of all wiring being out of the plane.

[Development of residual voltage testing equipment].

PubMed

Zeng, Xiaohui; Wu, Mingjun; Cao, Li; He, Jinyi; Deng, Zhensheng

2014-07-01

For the existing measurement methods of residual voltage which can't turn the power off at peak voltage exactly and simultaneously display waveforms, a new residual voltage detection method is put forward in this paper. First, the zero point of the power supply is detected with zero cross detection circuit and is inputted to a single-chip microcomputer in the form of pulse signal. Secend, when the zero point delays to the peak voltage, the single-chip microcomputer sends control signal to power off the relay. At last, the waveform of the residual voltage is displayed on a principal computer or oscilloscope. The experimental results show that the device designed in this paper can turn the power off at peak voltage and is able to accurately display the voltage waveform immediately after power off and the standard deviation of the residual voltage is less than 0.2 V at exactly one second and later.

Slow Controls Using the Axiom M5235BCC

NASA Astrophysics Data System (ADS)

Hague, Tyler

2008-10-01

The Forward Vertex Detector group at PHENIX plans to adopt the Axiom M5235 Business Card Controller for use as slow controls. It is also being evaluated for slow controls on FermiLab e906. This controller features the Freescale MCF5235 microprocessor. It also has three parallel buses, these being the MCU port, BUS port, and enhanced Time Processing Unit (eTPU) port. The BUS port uses a chip select module with three external chip selects to communicate with peripherals. This will be used to communicate with and configure Field Programmable Gate Arrays (FPGAs). The controller also has an Ethernet port which can use several different protocols such as TCP and UDP. This will be used to transfer files with computers on a network. The M5235 Business Card Controller will be placed in a VME crate along with VME card and a Spartan-3 FPGA.

The science of computing - Parallel computation

NASA Technical Reports Server (NTRS)

Denning, P. J.

1985-01-01

Although parallel computation architectures have been known for computers since the 1920s, it was only in the 1970s that microelectronic components technologies advanced to the point where it became feasible to incorporate multiple processors in one machine. Concommitantly, the development of algorithms for parallel processing also lagged due to hardware limitations. The speed of computing with solid-state chips is limited by gate switching delays. The physical limit implies that a 1 Gflop operational speed is the maximum for sequential processors. A computer recently introduced features a 'hypercube' architecture with 128 processors connected in networks at 5, 6 or 7 points per grid, depending on the design choice. Its computing speed rivals that of supercomputers, but at a fraction of the cost. The added speed with less hardware is due to parallel processing, which utilizes algorithms representing different parts of an equation that can be broken into simpler statements and processed simultaneously. Present, highly developed computer languages like FORTRAN, PASCAL, COBOL, etc., rely on sequential instructions. Thus, increased emphasis will now be directed at parallel processing algorithms to exploit the new architectures.

Adapting Wave-front Algorithms to Efficiently Utilize Systems with Deep Communication Hierarchies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerbyson, Darren J.; Lang, Michael; Pakin, Scott

2011-09-30

Large-scale systems increasingly exhibit a differential between intra-chip and inter-chip communication performance especially in hybrid systems using accelerators. Processorcores on the same socket are able to communicate at lower latencies, and with higher bandwidths, than cores on different sockets either within the same node or between nodes. A key challenge is to efficiently use this communication hierarchy and hence optimize performance. We consider here the class of applications that contains wavefront processing. In these applications data can only be processed after their upstream neighbors have been processed. Similar dependencies result between processors in which communication is required to pass boundarymore » data downstream and whose cost is typically impacted by the slowest communication channel in use. In this work we develop a novel hierarchical wave-front approach that reduces the use of slower communications in the hierarchy but at the cost of additional steps in the parallel computation and higher use of on-chip communications. This tradeoff is explored using a performance model. An implementation using the Reverse-acceleration programming model on the petascale Roadrunner system demonstrates a 27% performance improvement at full system-scale on a kernel application. The approach is generally applicable to large-scale multi-core and accelerated systems where a differential in system communication performance exists.« less