Flash drive memory apparatus and method

NASA Technical Reports Server (NTRS)

Hinchey, Michael G. (Inventor)

2010-01-01

A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

Computational performance of a smoothed particle hydrodynamics simulation for shared-memory parallel computing

NASA Astrophysics Data System (ADS)

Nishiura, Daisuke; Furuichi, Mikito; Sakaguchi, Hide

2015-09-01

The computational performance of a smoothed particle hydrodynamics (SPH) simulation is investigated for three types of current shared-memory parallel computer devices: many integrated core (MIC) processors, graphics processing units (GPUs), and multi-core CPUs. We are especially interested in efficient shared-memory allocation methods for each chipset, because the efficient data access patterns differ between compute unified device architecture (CUDA) programming for GPUs and OpenMP programming for MIC processors and multi-core CPUs. We first introduce several parallel implementation techniques for the SPH code, and then examine these on our target computer architectures to determine the most effective algorithms for each processor unit. In addition, we evaluate the effective computing performance and power efficiency of the SPH simulation on each architecture, as these are critical metrics for overall performance in a multi-device environment. In our benchmark test, the GPU is found to produce the best arithmetic performance as a standalone device unit, and gives the most efficient power consumption. The multi-core CPU obtains the most effective computing performance. The computational speed of the MIC processor on Xeon Phi approached that of two Xeon CPUs. This indicates that using MICs is an attractive choice for existing SPH codes on multi-core CPUs parallelized by OpenMP, as it gains computational acceleration without the need for significant changes to the source code.

In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy.

PubMed

Jaiswal, Akhilesh; Agrawal, Amogh; Roy, Kaushik

2018-04-10

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

NASA Astrophysics Data System (ADS)

Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

2016-04-01

The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

Computer memory: the LLL experience. [Octopus computer network

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fletcher, J.G.

1976-02-01

Those aspects of Octopus computer network design are reviewed that relate to memory and storage. Emphasis is placed on the difficulties and problems that arise because of the limitations of present storage devices, and indications are made of the directions in which technological advance could be of most value. (auth)

Three-terminal resistive switching memory in a transparent vertical-configuration device

NASA Astrophysics Data System (ADS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

Scientific developments of liquid crystal-based optical memory: a review

NASA Astrophysics Data System (ADS)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Scientific developments of liquid crystal-based optical memory: a review.

PubMed

Prakash, Jai; Chandran, Achu; Biradar, Ashok M

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

All-spin logic operations: Memory device and reconfigurable computing

NASA Astrophysics Data System (ADS)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Computing with volatile memristors: an application of non-pinched hysteresis

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Shevchenko, S. N.

2017-02-01

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated theoretically. We have adopted a hysteretic graphene-based field emission structure as a prototype of a volatile memristor, which is characterized by a non-pinched hysteresis loop. A memristive model of the structure is developed and used to simulate a polymorphic circuit implementing stateful logic gates, such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices, such as certain NEMS switches.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

NASA Astrophysics Data System (ADS)

Ando, K.; Fujita, S.; Ito, J.; Yuasa, S.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.; Yoda, H.

2014-05-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Novel synaptic memory device for neuromorphic computing

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; El-Amin, Ammaarah; Alexander, Kaitlyn; Rajendran, Bipin; Jha, Rashmi

2014-06-01

This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO2 material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >106 times reduction in the power consumption per learning cycle.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices.

PubMed

Shukla, Krishna Dayal; Saxena, Nishant; Manivannan, Anbarasu

2017-12-01

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag 5 In 5 Sb 60 Te 30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices

NASA Astrophysics Data System (ADS)

Shukla, Krishna Dayal; Saxena, Nishant; Manivannan, Anbarasu

2017-12-01

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag5In5Sb60Te30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

Quantum computers: Definition and implementations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Perez-Delgado, Carlos A.; Kok, Pieter

The DiVincenzo criteria for implementing a quantum computer have been seminal in focusing both experimental and theoretical research in quantum-information processing. These criteria were formulated specifically for the circuit model of quantum computing. However, several new models for quantum computing (paradigms) have been proposed that do not seem to fit the criteria well. Therefore, the question is what are the general criteria for implementing quantum computers. To this end, a formal operational definition of a quantum computer is introduced. It is then shown that, according to this definition, a device is a quantum computer if it obeys the following criteria:more » Any quantum computer must consist of a quantum memory, with an additional structure that (1) facilitates a controlled quantum evolution of the quantum memory; (2) includes a method for information theoretic cooling of the memory; and (3) provides a readout mechanism for subsets of the quantum memory. The criteria are met when the device is scalable and operates fault tolerantly. We discuss various existing quantum computing paradigms and how they fit within this framework. Finally, we present a decision tree for selecting an avenue toward building a quantum computer. This is intended to help experimentalists determine the most natural paradigm given a particular physical implementation.« less

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

A chiral-based magnetic memory device without a permanent magnet

PubMed Central

Dor, Oren Ben; Yochelis, Shira; Mathew, Shinto P.; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices. PMID:23922081

A chiral-based magnetic memory device without a permanent magnet.

PubMed

Ben Dor, Oren; Yochelis, Shira; Mathew, Shinto P; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices.

Ordering of guarded and unguarded stores for no-sync I/O

DOEpatents

Gara, Alan; Ohmacht, Martin

2013-06-25

A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.

Cryogenic Memories based on Spin-Singlet and Spin-Triplet Ferromagnetic Josephson Junctions

NASA Astrophysics Data System (ADS)

Gingrich, Eric

The last several decades have seen an explosion in the use and size of computers for scientific applications. The US Department of Energy has set an ExaScale computing goal for high performance computing that is projected to be unattainable by current CMOS computing designs. This has led to a renewed interest in superconducting computing as a means of beating these projections. One of the primary requirements of this thrust is the development of an efficient cryogenic memory. Estimates of power consumption of early Rapid Single Flux Quantum (RSFQ) memory designs are on the order of MW, far too steep for any real application. Therefore, other memory concepts are required. S/F/S Josephson Junctions, a class of device in which two superconductors (S) are separated by one or more ferromagnetic layers (F) has shown promise as a memory element. Several different systems have been proposed utilizing either the spin-singlet or spin-triplet superconducting states. This talk will discuss the concepts underpinning these devices, and the recent work done to demonstrate their feasibility. This research is supported in part by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via U.S. Army Research Office Contract W911NF-14-C-0115.

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures

PubMed Central

Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo

2018-01-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS2/PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 104 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS2 to PbS. The demonstrated MoS2 heterostructure–based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices. PMID:29770356

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures.

PubMed

Wang, Qisheng; Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo; He, Jun

2018-04-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS 2 /PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 10 4 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS 2 to PbS. The demonstrated MoS 2 heterostructure-based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices.

Local rollback for fault-tolerance in parallel computing systems

DOEpatents

Blumrich, Matthias A [Yorktown Heights, NY; Chen, Dong [Yorktown Heights, NY; Gara, Alan [Yorktown Heights, NY; Giampapa, Mark E [Yorktown Heights, NY; Heidelberger, Philip [Yorktown Heights, NY; Ohmacht, Martin [Yorktown Heights, NY; Steinmacher-Burow, Burkhard [Boeblingen, DE; Sugavanam, Krishnan [Yorktown Heights, NY

2012-01-24

A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Computer vision camera with embedded FPGA processing

NASA Astrophysics Data System (ADS)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Providing the Public with Online Access to Large Bibliographic Data Bases.

ERIC Educational Resources Information Center

Firschein, Oscar; Summit, Roger K.

DIALOG, an interactive, computer-based information retrieval language, consists of a series of computer programs designed to make use of direct access memory devices in order to provide the user with a rapid means of identifying records within a specific memory bank. Using the system, a library user can be provided access to sixteen distinct and…

Persistent Memory in Single Node Delay-Coupled Reservoir Computing.

PubMed

Kovac, André David; Koall, Maximilian; Pipa, Gordon; Toutounji, Hazem

2016-01-01

Delays are ubiquitous in biological systems, ranging from genetic regulatory networks and synaptic conductances, to predator/pray population interactions. The evidence is mounting, not only to the presence of delays as physical constraints in signal propagation speed, but also to their functional role in providing dynamical diversity to the systems that comprise them. The latter observation in biological systems inspired the recent development of a computational architecture that harnesses this dynamical diversity, by delay-coupling a single nonlinear element to itself. This architecture is a particular realization of Reservoir Computing, where stimuli are injected into the system in time rather than in space as is the case with classical recurrent neural network realizations. This architecture also exhibits an internal memory which fades in time, an important prerequisite to the functioning of any reservoir computing device. However, fading memory is also a limitation to any computation that requires persistent storage. In order to overcome this limitation, the current work introduces an extended version to the single node Delay-Coupled Reservoir, that is based on trained linear feedback. We show by numerical simulations that adding task-specific linear feedback to the single node Delay-Coupled Reservoir extends the class of solvable tasks to those that require nonfading memory. We demonstrate, through several case studies, the ability of the extended system to carry out complex nonlinear computations that depend on past information, whereas the computational power of the system with fading memory alone quickly deteriorates. Our findings provide the theoretical basis for future physical realizations of a biologically-inspired ultrafast computing device with extended functionality.

Persistent Memory in Single Node Delay-Coupled Reservoir Computing

PubMed Central

Pipa, Gordon; Toutounji, Hazem

2016-01-01

Delays are ubiquitous in biological systems, ranging from genetic regulatory networks and synaptic conductances, to predator/pray population interactions. The evidence is mounting, not only to the presence of delays as physical constraints in signal propagation speed, but also to their functional role in providing dynamical diversity to the systems that comprise them. The latter observation in biological systems inspired the recent development of a computational architecture that harnesses this dynamical diversity, by delay-coupling a single nonlinear element to itself. This architecture is a particular realization of Reservoir Computing, where stimuli are injected into the system in time rather than in space as is the case with classical recurrent neural network realizations. This architecture also exhibits an internal memory which fades in time, an important prerequisite to the functioning of any reservoir computing device. However, fading memory is also a limitation to any computation that requires persistent storage. In order to overcome this limitation, the current work introduces an extended version to the single node Delay-Coupled Reservoir, that is based on trained linear feedback. We show by numerical simulations that adding task-specific linear feedback to the single node Delay-Coupled Reservoir extends the class of solvable tasks to those that require nonfading memory. We demonstrate, through several case studies, the ability of the extended system to carry out complex nonlinear computations that depend on past information, whereas the computational power of the system with fading memory alone quickly deteriorates. Our findings provide the theoretical basis for future physical realizations of a biologically-inspired ultrafast computing device with extended functionality. PMID:27783690

Spatial light modulators and applications III; Proceedings of the Meeting, San Diego, CA, Aug. 7, 8, 1989

NASA Astrophysics Data System (ADS)

Efron, Uzi

Recent advances in the technology and applications of spatial light modulators (SLMs) are discussed in review essays by leading experts. Topics addressed include materials for SLMs, SLM devices and device technology, applications to optical data processing, and applications to artificial neural networks. Particular attention is given to nonlinear optical polymers, liquid crystals, magnetooptic SLMs, multiple-quantum-well SLMs, deformable-mirror SLMs, three-dimensional optical memories, applications of photorefractive devices to optical computing, photonic neurocomputers and learning machines, holographic associative memories, SLMs as parallel memories for optoelectronic neural networks, and coherent-optics implementations of neural-network models.

Spatial light modulators and applications III; Proceedings of the Meeting, San Diego, CA, Aug. 7, 8, 1989

NASA Technical Reports Server (NTRS)

Efron, Uzi (Editor)

1990-01-01

Recent advances in the technology and applications of spatial light modulators (SLMs) are discussed in review essays by leading experts. Topics addressed include materials for SLMs, SLM devices and device technology, applications to optical data processing, and applications to artificial neural networks. Particular attention is given to nonlinear optical polymers, liquid crystals, magnetooptic SLMs, multiple-quantum-well SLMs, deformable-mirror SLMs, three-dimensional optical memories, applications of photorefractive devices to optical computing, photonic neurocomputers and learning machines, holographic associative memories, SLMs as parallel memories for optoelectronic neural networks, and coherent-optics implementations of neural-network models.

Mass Memory Storage Devices for AN/SLQ-32(V).

DTIC Science & Technology

1985-06-01

tactical programs and libraries into the AN/UYK-19 computer , the RP-16 microprocessor, and other peripheral processors (e.g., ADLS and Band 1) will be...software must be loaded into computer memory from the 4-track magnetic tape cartridges (MTCs) on which the programs are stored. Program load begins...software. Future computer programs , which will reside in peripheral processors, include the Automated Decoy Launching System (ADLS) and Band 1. As

A Comprehensive Study on Energy Efficiency and Performance of Flash-based SSD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, Seon-Yeon; Kim, Youngjae; Urgaonkar, Bhuvan

2011-01-01

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation tomore » investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.« less

Non-volatile memory for checkpoint storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.

A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, themore » non-volatile memory is a pluggable flash memory card.« less

Two-Way Communication Using RFID Equipment and Techniques

NASA Technical Reports Server (NTRS)

Jedry, Thomas; Archer, Eric

2007-01-01

Equipment and techniques used in radio-frequency identification (RFID) would be extended, according to a proposal, to enable short-range, two-way communication between electronic products and host computers. In one example of a typical contemplated application, the purpose of the short-range radio communication would be to transfer image data from a user s digital still or video camera to the user s computer for recording and/or processing. The concept is also applicable to consumer electronic products other than digital cameras (for example, cellular telephones, portable computers, or motion sensors in alarm systems), and to a variety of industrial and scientific sensors and other devices that generate data. Until now, RFID has been used to exchange small amounts of mostly static information for identifying and tracking assets. Information pertaining to an asset (typically, an object in inventory to be tracked) is contained in miniature electronic circuitry in an RFID tag attached to the object. Conventional RFID equipment and techniques enable a host computer to read data from and, in some cases, to write data to, RFID tags, but they do not enable such additional functions as sending commands to, or retrieving possibly large quantities of dynamic data from, RFID-tagged devices. The proposal would enable such additional functions. The figure schematically depicts an implementation of the proposal for a sensory device (e.g., a digital camera) that includes circuitry that converts sensory information to digital data. In addition to the basic sensory device, there would be a controller and a memory that would store the sensor data and/or data from the controller. The device would also be equipped with a conventional RFID chipset and antenna, which would communicate with a host computer via an RFID reader. The controller would function partly as a communication interface, implementing two-way communication protocols at all levels (including RFID if needed) between the sensory device and the memory and between the host computer and the memory. The controller would perform power V

Spin transport and spin torque in antiferromagnetic devices

DOE PAGES

Zelezny, J.; Wadley, P.; Olejnik, K.; ...

2018-03-02

Ferromagnets are key materials for sensing and memory applications. In contrast, antiferromagnets which represent the more common form of magnetically ordered materials, have found less practical application beyond their use for establishing reference magnetic orientations via exchange bias. This might change in the future due to the recent progress in materials research and discoveries of antiferromagnetic spintronic phenomena suitable for device applications. Experimental demonstration of the electrical switching and detection of the Néel order open a route towards memory devices based on antiferromagnets. Apart from the radiation and magnetic-field hardness, memory cells fabricated from antiferromagnets can be inherently multilevel, whichmore » could be used for neuromorphic computing. Switching speeds attainable in antiferromagnets far exceed those of ferromagnetic and semiconductor memory technologies. Here we review the recent progress in electronic spin-transport and spin-torque phenomena in antiferromagnets that are dominantly of the relativistic quantum mechanical origin. We discuss their utility in pure antiferromagnetic or hybrid ferromagnetic/antiferromagnetic memory devices.« less

Spin transport and spin torque in antiferromagnetic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zelezny, J.; Wadley, P.; Olejnik, K.

Ferromagnets are key materials for sensing and memory applications. In contrast, antiferromagnets which represent the more common form of magnetically ordered materials, have found less practical application beyond their use for establishing reference magnetic orientations via exchange bias. This might change in the future due to the recent progress in materials research and discoveries of antiferromagnetic spintronic phenomena suitable for device applications. Experimental demonstration of the electrical switching and detection of the Néel order open a route towards memory devices based on antiferromagnets. Apart from the radiation and magnetic-field hardness, memory cells fabricated from antiferromagnets can be inherently multilevel, whichmore » could be used for neuromorphic computing. Switching speeds attainable in antiferromagnets far exceed those of ferromagnetic and semiconductor memory technologies. Here we review the recent progress in electronic spin-transport and spin-torque phenomena in antiferromagnets that are dominantly of the relativistic quantum mechanical origin. We discuss their utility in pure antiferromagnetic or hybrid ferromagnetic/antiferromagnetic memory devices.« less

Spin transport and spin torque in antiferromagnetic devices

NASA Astrophysics Data System (ADS)

Železný, J.; Wadley, P.; Olejník, K.; Hoffmann, A.; Ohno, H.

2018-03-01

Ferromagnets are key materials for sensing and memory applications. In contrast, antiferromagnets, which represent the more common form of magnetically ordered materials, have found less practical application beyond their use for establishing reference magnetic orientations via exchange bias. This might change in the future due to the recent progress in materials research and discoveries of antiferromagnetic spintronic phenomena suitable for device applications. Experimental demonstration of the electrical switching and detection of the Néel order open a route towards memory devices based on antiferromagnets. Apart from the radiation and magnetic-field hardness, memory cells fabricated from antiferromagnets can be inherently multilevel, which could be used for neuromorphic computing. Switching speeds attainable in antiferromagnets far exceed those of ferromagnetic and semiconductor memory technologies. Here, we review the recent progress in electronic spin-transport and spin-torque phenomena in antiferromagnets that are dominantly of the relativistic quantum-mechanical origin. We discuss their utility in pure antiferromagnetic or hybrid ferromagnetic/antiferromagnetic memory devices.

Ames Lab 101: Ultrafast Magnetic Switching

ScienceCinema

Wang; Jigang

2018-01-01

Ames Laboratory physicists have found a new way to switch magnetism that is at least 1000 times faster than currently used in magnetic memory technologies. Magnetic switching is used to encode information in hard drives, magnetic random access memory and other computing devices. The discovery potentially opens the door to terahertz and faster memory speeds.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Hao; Han, Lili; Lin, Peng

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE PAGES

Jiang, Hao; Han, Lili; Lin, Peng; ...

2016-06-23

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

Store-operate-coherence-on-value

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Dong; Heidelberger, Philip; Kumar, Sameer

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the receivedmore » store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.« less

Data storage technology comparisons

NASA Technical Reports Server (NTRS)

Katti, Romney R.

1990-01-01

The role of data storage and data storage technology is an integral, though conceptually often underestimated, portion of data processing technology. Data storage is important in the mass storage mode in which generated data is buffered for later use. But data storage technology is also important in the data flow mode when data are manipulated and hence required to flow between databases, datasets and processors. This latter mode is commonly associated with memory hierarchies which support computation. VLSI devices can reasonably be defined as electronic circuit devices such as channel and control electronics as well as highly integrated, solid-state devices that are fabricated using thin film deposition technology. VLSI devices in both capacities play an important role in data storage technology. In addition to random access memories (RAM), read-only memories (ROM), and other silicon-based variations such as PROM's, EPROM's, and EEPROM's, integrated devices find their way into a variety of memory technologies which offer significant performance advantages. These memory technologies include magnetic tape, magnetic disk, magneto-optic disk, and vertical Bloch line memory. In this paper, some comparison between selected technologies will be made to demonstrate why more than one memory technology exists today, based for example on access time and storage density at the active bit and system levels.

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications.

PubMed

Linn, E; Menzel, S; Ferch, S; Waser, R

2013-09-27

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications.

Realization of reliable solid-state quantum memory for photonic polarization qubit.

PubMed

Zhou, Zong-Quan; Lin, Wei-Bin; Yang, Ming; Li, Chuan-Feng; Guo, Guang-Can

2012-05-11

Faithfully storing an unknown quantum light state is essential to advanced quantum communication and distributed quantum computation applications. The required quantum memory must have high fidelity to improve the performance of a quantum network. Here we report the reversible transfer of photonic polarization states into collective atomic excitation in a compact solid-state device. The quantum memory is based on an atomic frequency comb (AFC) in rare-earth ion-doped crystals. We obtain up to 0.999 process fidelity for the storage and retrieval process of single-photon-level coherent pulse. This reliable quantum memory is a crucial step toward quantum networks based on solid-state devices.

Josephson Thermal Memory

NASA Astrophysics Data System (ADS)

Guarcello, Claudio; Solinas, Paolo; Braggio, Alessandro; Di Ventra, Massimiliano; Giazotto, Francesco

2018-01-01

We propose a superconducting thermal memory device that exploits the thermal hysteresis in a flux-controlled temperature-biased superconducting quantum-interference device (SQUID). This system reveals a flux-controllable temperature bistability, which can be used to define two well-distinguishable thermal logic states. We discuss a suitable writing-reading procedure for these memory states. The time of the memory writing operation is expected to be on the order of approximately 0.2 ns for a Nb-based SQUID in thermal contact with a phonon bath at 4.2 K. We suggest a noninvasive readout scheme for the memory states based on the measurement of the effective resonance frequency of a tank circuit inductively coupled to the SQUID. The proposed device paves the way for a practical implementation of thermal logic and computation. The advantage of this proposal is that it represents also an example of harvesting thermal energy in superconducting circuits.

A learnable parallel processing architecture towards unity of memory and computing

NASA Astrophysics Data System (ADS)

Li, H.; Gao, B.; Chen, Z.; Zhao, Y.; Huang, P.; Ye, H.; Liu, L.; Liu, X.; Kang, J.

2015-08-01

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

A learnable parallel processing architecture towards unity of memory and computing.

PubMed

Li, H; Gao, B; Chen, Z; Zhao, Y; Huang, P; Ye, H; Liu, L; Liu, X; Kang, J

2015-08-14

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named "iMemComp", where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped "iMemComp" with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on "iMemComp" can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Portable Computer Keyboard For Use With One Hand

NASA Technical Reports Server (NTRS)

Friedman, Gary L.

1992-01-01

Data-entry device held in one hand and operated with five fingers. Contains seven keys. Letters, numbers, punctuation, and cursor commands keyed into computer by pressing keys in various combinations. Device called "data egg" used where standard typewriter keyboard unusable or unavailable. Contains micro-processor and 32-Kbyte memory. Captures text and transmits it to computer. Concept extended to computer mouse. Especially useful to handicapped or bedridden people who find it difficult or impossible to operate standard keyboards.

Semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

DOEpatents

Goyal, Amit

2014-08-05

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit

2015-03-24

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

How to Use Removable Mass Storage Memory Devices

ERIC Educational Resources Information Center

Branzburg, Jeffrey

2004-01-01

Mass storage refers to the variety of ways to keep large amounts of information that are used on a computer. Over the years, the removable storage devices have grown smaller, increased in capacity, and transferred the information to the computer faster. The 8" floppy disk of the 1960s stored 100 kilobytes, or about 60 typewritten, double-spaced…

gpuSPHASE-A shared memory caching implementation for 2D SPH using CUDA

NASA Astrophysics Data System (ADS)

Winkler, Daniel; Meister, Michael; Rezavand, Massoud; Rauch, Wolfgang

2017-04-01

Smoothed particle hydrodynamics (SPH) is a meshless Lagrangian method that has been successfully applied to computational fluid dynamics (CFD), solid mechanics and many other multi-physics problems. Using the method to solve transport phenomena in process engineering requires the simulation of several days to weeks of physical time. Based on the high computational demand of CFD such simulations in 3D need a computation time of years so that a reduction to a 2D domain is inevitable. In this paper gpuSPHASE, a new open-source 2D SPH solver implementation for graphics devices, is developed. It is optimized for simulations that must be executed with thousands of frames per second to be computed in reasonable time. A novel caching algorithm for Compute Unified Device Architecture (CUDA) shared memory is proposed and implemented. The software is validated and the performance is evaluated for the well established dambreak test case.

CLOCS (Computer with Low Context-Switching Time) Architecture Reference Documents

DTIC Science & Technology

1988-05-06

Peculiarities The only state inside the central processing unit(CPU) is a program status word. All data operations are memory to memory. One result of this... to the challenge "if I whore to design RISC, this is how I would do it." The architecture was designed by Mark Davis and Bill Gallmeister. 1.2...are memory to memory. Any special devices added should be memory mapped. The program counter is even memory mapped. 1.3.1 Working storage There is no

A comprehensive approach to decipher biological computation to achieve next generation high-performance exascale computing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

James, Conrad D.; Schiess, Adrian B.; Howell, Jamie

2013-10-01

The human brain (volume=1200cm3) consumes 20W and is capable of performing > 10^16 operations/s. Current supercomputer technology has reached 1015 operations/s, yet it requires 1500m^3 and 3MW, giving the brain a 10^12 advantage in operations/s/W/cm^3. Thus, to reach exascale computation, two achievements are required: 1) improved understanding of computation in biological tissue, and 2) a paradigm shift towards neuromorphic computing where hardware circuits mimic properties of neural tissue. To address 1), we will interrogate corticostriatal networks in mouse brain tissue slices, specifically with regard to their frequency filtering capabilities as a function of input stimulus. To address 2), we willmore » instantiate biological computing characteristics such as multi-bit storage into hardware devices with future computational and memory applications. Resistive memory devices will be modeled, designed, and fabricated in the MESA facility in consultation with our internal and external collaborators.« less

{100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2012-05-15

Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

45 CFR 160.103 - Definitions.

Code of Federal Regulations, 2012 CFR

2012-10-01

..., the following definitions apply to this subchapter: Act means the Social Security Act. ANSI stands for... required documents. Electronic media means: (1) Electronic storage media including memory devices in computers (hard drives) and any removable/transportable digital memory medium, such as magnetic tape or disk...

45 CFR 160.103 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-10-01

..., the following definitions apply to this subchapter: Act means the Social Security Act. ANSI stands for... required documents. Electronic media means: (1) Electronic storage media including memory devices in computers (hard drives) and any removable/transportable digital memory medium, such as magnetic tape or disk...

45 CFR 160.103 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-10-01

..., the following definitions apply to this subchapter: Act means the Social Security Act. ANSI stands for... required documents. Electronic media means: (1) Electronic storage media including memory devices in computers (hard drives) and any removable/transportable digital memory medium, such as magnetic tape or disk...

Filamentary model in resistive switching materials

NASA Astrophysics Data System (ADS)

Jasmin, Alladin C.

2017-12-01

The need for next generation computer devices is increasing as the demand for efficient data processing increases. The amount of data generated every second also increases which requires large data storage devices. Oxide-based memory devices are being studied to explore new research frontiers thanks to modern advances in nanofabrication. Various oxide materials are studied as active layers for non-volatile memory. This technology has potential application in resistive random-access-memory (ReRAM) and can be easily integrated in CMOS technologies. The long term perspective of this research field is to develop devices which mimic how the brain processes information. To realize such application, a thorough understanding of the charge transport and switching mechanism is important. A new perspective in the multistate resistive switching based on current-induced filament dynamics will be discussed. A simple equivalent circuit of the device gives quantitative information about the nature of the conducting filament at different resistance states.

Assistive technology for memory support in dementia.

PubMed

Van der Roest, Henriëtte G; Wenborn, Jennifer; Pastink, Channah; Dröes, Rose-Marie; Orrell, Martin

2017-06-11

The sustained interest in electronic assistive technology in dementia care has been fuelled by the urgent need to develop useful approaches to help support people with dementia at home. Also the low costs and wide availability of electronic devices make it more feasible to use electronic devices for the benefit of disabled persons. Information Communication Technology (ICT) devices designed to support people with dementia are usually referred to as Assistive Technology (AT) or Electronic Assistive Technology (EAT). By using AT in this review we refer to electronic assistive devices. A range of AT devices has been developed to support people with dementia and their carers to manage their daily activities and to enhance safety, for example electronic pill boxes, picture phones, or mobile tracking devices. Many are commercially available. However, the usefulness and user-friendliness of these devices are often poorly evaluated. Although reviews of (electronic) memory aids do exist, a systematic review of studies focusing on the efficacy of AT for memory support in people with dementia is lacking. Such a review would guide people with dementia and their informal and professional carers in selecting appropriate AT devices. Primary objectiveTo assess the efficacy of AT for memory support in people with dementia in terms of daily performance of personal and instrumental activities of daily living (ADL), level of dependency, and admission to long-term care. Secondary objectiveTo assess the impact of AT on: users (autonomy, usefulness and user-friendliness, adoption of AT); cognitive function and neuropsychiatric symptoms; need for informal and formal care; perceived quality of life; informal carer burden, self-esteem and feelings of competence; formal carer work satisfaction, workload and feelings of competence; and adverse events. We searched ALOIS, the Specialised Register of the Cochrane Dementia and Cognitive Improvement Group (CDCIG), on 10 November 2016. ALOIS is maintained by the Information Specialists of the CDCIG and contains studies in the areas of dementia prevention, dementia treatment and cognitive enhancement in healthy people. We also searched the following list of databases, adapting the search strategy as necessary: Centre for Reviews and Dissemination (CRD) Databases, up to May 2016; The Collection of Computer Science Bibliographies; DBLP Computer Science Bibliography; HCI Bibliography: Human-Computer Interaction Resources; and AgeInfo, all to June 2016; PiCarta; Inspec; Springer Link Lecture Notes; Social Care Online; and IEEE Computer Society Digital Library, all to October 2016; J-STAGE: Japan Science and Technology Information Aggregator, Electronic; and Networked Computer Science Technical Reference Library (NCSTRL), both to November 2016; Computing Research Repository (CoRR) up to December 2016; and OT seeker; and ADEAR, both to February 2017. In addition, we searched Google Scholar and OpenSIGLE for grey literature. We intended to review randomised controlled trials (RCTs) and clustered randomised trials with blinded assessment of outcomes that evaluated an electronic assistive device used with the single aim of supporting memory function in people diagnosed with dementia. The control interventions could either be 'care (or treatment) as usual' or non-technological psychosocial interventions (including interventions that use non-electronic assistive devices) also specifically aimed at supporting memory. Outcome measures included activities of daily living, level of dependency, clinical and care-related outcomes (for example admission to long-term care), perceived quality of life and well-being, and adverse events resulting from the use of AT; as well as the effects of AT on carers. Two review authors independently screened all titles and abstracts identified by the search. We identified no studies which met the inclusion criteria. This review highlights the current lack of high-quality evidence to determine whether AT is effective in supporting people with dementia to manage their memory problems.

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

NASA Astrophysics Data System (ADS)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

Processing Device for High-Speed Execution of an Xrisc Computer Program

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Mills, Carl S. (Inventor)

2016-01-01

A processing device for high-speed execution of a computer program is provided. A memory module may store one or more computer programs. A sequencer may select one of the computer programs and controls execution of the selected program. A register module may store intermediate values associated with a current calculation set, a set of output values associated with a previous calculation set, and a set of input values associated with a subsequent calculation set. An external interface may receive the set of input values from a computing device and provides the set of output values to the computing device. A computation interface may provide a set of operands for computation during processing of the current calculation set. The set of input values are loaded into the register and the set of output values are unloaded from the register in parallel with processing of the current calculation set.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Computer hardware for radiologists: Part 2.

PubMed

Indrajit, Ik; Alam, A

2010-11-01

Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

Wearable Intrinsically Soft, Stretchable, Flexible Devices for Memories and Computing.

PubMed

Rajan, Krishna; Garofalo, Erik; Chiolerio, Alessandro

2018-01-27

A recent trend in the development of high mass consumption electron devices is towards electronic textiles (e-textiles), smart wearable devices, smart clothes, and flexible or printable electronics. Intrinsically soft, stretchable, flexible, Wearable Memories and Computing devices (WMCs) bring us closer to sci-fi scenarios, where future electronic systems are totally integrated in our everyday outfits and help us in achieving a higher comfort level, interacting for us with other digital devices such as smartphones and domotics, or with analog devices, such as our brain/peripheral nervous system. WMC will enable each of us to contribute to open and big data systems as individual nodes, providing real-time information about physical and environmental parameters (including air pollution monitoring, sound and light pollution, chemical or radioactive fallout alert, network availability, and so on). Furthermore, WMC could be directly connected to human brain and enable extremely fast operation and unprecedented interface complexity, directly mapping the continuous states available to biological systems. This review focuses on recent advances in nanotechnology and materials science and pays particular attention to any result and promising technology to enable intrinsically soft, stretchable, flexible WMC.

Wearable Intrinsically Soft, Stretchable, Flexible Devices for Memories and Computing

PubMed Central

Rajan, Krishna; Garofalo, Erik

2018-01-01

A recent trend in the development of high mass consumption electron devices is towards electronic textiles (e-textiles), smart wearable devices, smart clothes, and flexible or printable electronics. Intrinsically soft, stretchable, flexible, Wearable Memories and Computing devices (WMCs) bring us closer to sci-fi scenarios, where future electronic systems are totally integrated in our everyday outfits and help us in achieving a higher comfort level, interacting for us with other digital devices such as smartphones and domotics, or with analog devices, such as our brain/peripheral nervous system. WMC will enable each of us to contribute to open and big data systems as individual nodes, providing real-time information about physical and environmental parameters (including air pollution monitoring, sound and light pollution, chemical or radioactive fallout alert, network availability, and so on). Furthermore, WMC could be directly connected to human brain and enable extremely fast operation and unprecedented interface complexity, directly mapping the continuous states available to biological systems. This review focuses on recent advances in nanotechnology and materials science and pays particular attention to any result and promising technology to enable intrinsically soft, stretchable, flexible WMC. PMID:29382050

Shared prefetching to reduce execution skew in multi-threaded systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Eichenberger, Alexandre E; Gunnels, John A

Mechanisms are provided for optimizing code to perform prefetching of data into a shared memory of a computing device that is shared by a plurality of threads that execute on the computing device. A memory stream of a portion of code that is shared by the plurality of threads is identified. A set of prefetch instructions is distributed across the plurality of threads. Prefetch instructions are inserted into the instruction sequences of the plurality of threads such that each instruction sequence has a separate sub-portion of the set of prefetch instructions, thereby generating optimized code. Executable code is generated basedmore » on the optimized code and stored in a storage device. The executable code, when executed, performs the prefetches associated with the distributed set of prefetch instructions in a shared manner across the plurality of threads.« less

The Computer and Its Functions; How to Communicate with the Computer.

ERIC Educational Resources Information Center

Ward, Peggy M.

A brief discussion of why it is important for students to be familiar with computers and their functions and a list of some practical applications introduce this two-part paper. Focusing on how the computer works, the first part explains the various components of the computer, different kinds of memory storage devices, disk operating systems, and…

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

Integrating Commercial Off-The-Shelf (COTS) graphics and extended memory packages with CLIPS

NASA Technical Reports Server (NTRS)

Callegari, Andres C.

1990-01-01

This paper addresses the question of how to mix CLIPS with graphics and how to overcome PC's memory limitations by using the extended memory available in the computer. By adding graphics and extended memory capabilities, CLIPS can be converted into a complete and powerful system development tool, on the other most economical and popular computer platform. New models of PCs have amazing processing capabilities and graphic resolutions that cannot be ignored and should be used to the fullest of their resources. CLIPS is a powerful expert system development tool, but it cannot be complete without the support of a graphics package needed to create user interfaces and general purpose graphics, or without enough memory to handle large knowledge bases. Now, a well known limitation on the PC's is the usage of real memory which limits CLIPS to use only 640 Kb of real memory, but now that problem can be solved by developing a version of CLIPS that uses extended memory. The user has access of up to 16 MB of memory on 80286 based computers and, practically, all the available memory (4 GB) on computers that use the 80386 processor. So if we give CLIPS a self-configuring graphics package that will automatically detect the graphics hardware and pointing device present in the computer, and we add the availability of the extended memory that exists in the computer (with no special hardware needed), the user will be able to create more powerful systems at a fraction of the cost and on the most popular, portable, and economic platform available such as the PC platform.

Uncertain behaviours of integrated circuits improve computational performance.

PubMed

Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

2015-11-20

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

Optimized Laplacian image sharpening algorithm based on graphic processing unit

NASA Astrophysics Data System (ADS)

Ma, Tinghuai; Li, Lu; Ji, Sai; Wang, Xin; Tian, Yuan; Al-Dhelaan, Abdullah; Al-Rodhaan, Mznah

2014-12-01

In classical Laplacian image sharpening, all pixels are processed one by one, which leads to large amount of computation. Traditional Laplacian sharpening processed on CPU is considerably time-consuming especially for those large pictures. In this paper, we propose a parallel implementation of Laplacian sharpening based on Compute Unified Device Architecture (CUDA), which is a computing platform of Graphic Processing Units (GPU), and analyze the impact of picture size on performance and the relationship between the processing time of between data transfer time and parallel computing time. Further, according to different features of different memory, an improved scheme of our method is developed, which exploits shared memory in GPU instead of global memory and further increases the efficiency. Experimental results prove that two novel algorithms outperform traditional consequentially method based on OpenCV in the aspect of computing speed.

A memristor-based nonvolatile latch circuit

NASA Astrophysics Data System (ADS)

Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia, Qiangfei; Snider, Gregory S.; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2010-06-01

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Data systems and computer science space data systems: Onboard memory and storage

NASA Technical Reports Server (NTRS)

Shull, Tom

1991-01-01

The topics are presented in viewgraph form and include the following: technical objectives; technology challenges; state-of-the-art assessment; mass storage comparison; SODR drive and system concepts; program description; vertical Bloch line (VBL) device concept; relationship to external programs; and backup charts for memory and storage.

Nanoscale memory elements based on the superconductor-ferromagnet proximity effect and spin-transfer torque magnetization switching

NASA Astrophysics Data System (ADS)

Baek, Burm

Superconducting-ferromagnetic hybrid devices have potential for a practical memory technology compatible with superconducting logic circuits and may help realize energy-efficient, high-performance superconducting computers. We have developed Josephson junction devices with pseudo-spin-valve barriers. We observed changes in Josephson critical current depending on the magnetization state of the barrier (parallel or anti-parallel) through the superconductor-ferromagnet proximity effect. This effect persists to nanoscale devices in contrast to the remanent field effect. In nanopillar devices, the magnetization states of the pseudo-spin-valve barriers could also be switched with applied bias currents at 4 K, which is consistent with the spin-transfer torque effect in analogous room-temperature spin valve devices. These results demonstrate devices that combine major superconducting and spintronic effects for scalable read and write of memory states, respectively. Further challenges and proposals towards practical devices will also be discussed.In collaboration with: William Rippard, NIST - Boulder, Matthew Pufall, NIST - Boulder, Stephen Russek, NIST-Boulder, Michael Schneider, NIST - Boulder, Samuel Benz, NIST - Boulder, Horst Rogalla, NIST-Boulder, Paul Dresselhaus, NIST - Boulder

Quantum memories: emerging applications and recent advances

NASA Astrophysics Data System (ADS)

Heshami, Khabat; England, Duncan G.; Humphreys, Peter C.; Bustard, Philip J.; Acosta, Victor M.; Nunn, Joshua; Sussman, Benjamin J.

2016-11-01

Quantum light-matter interfaces are at the heart of photonic quantum technologies. Quantum memories for photons, where non-classical states of photons are mapped onto stationary matter states and preserved for subsequent retrieval, are technical realizations enabled by exquisite control over interactions between light and matter. The ability of quantum memories to synchronize probabilistic events makes them a key component in quantum repeaters and quantum computation based on linear optics. This critical feature has motivated many groups to dedicate theoretical and experimental research to develop quantum memory devices. In recent years, exciting new applications, and more advanced developments of quantum memories, have proliferated. In this review, we outline some of the emerging applications of quantum memories in optical signal processing, quantum computation and non-linear optics. We review recent experimental and theoretical developments, and their impacts on more advanced photonic quantum technologies based on quantum memories.

Quantum memories: emerging applications and recent advances.

PubMed

Heshami, Khabat; England, Duncan G; Humphreys, Peter C; Bustard, Philip J; Acosta, Victor M; Nunn, Joshua; Sussman, Benjamin J

2016-11-12

Quantum light-matter interfaces are at the heart of photonic quantum technologies. Quantum memories for photons, where non-classical states of photons are mapped onto stationary matter states and preserved for subsequent retrieval, are technical realizations enabled by exquisite control over interactions between light and matter. The ability of quantum memories to synchronize probabilistic events makes them a key component in quantum repeaters and quantum computation based on linear optics. This critical feature has motivated many groups to dedicate theoretical and experimental research to develop quantum memory devices. In recent years, exciting new applications, and more advanced developments of quantum memories, have proliferated. In this review, we outline some of the emerging applications of quantum memories in optical signal processing, quantum computation and non-linear optics. We review recent experimental and theoretical developments, and their impacts on more advanced photonic quantum technologies based on quantum memories.

Quantum memories: emerging applications and recent advances

PubMed Central

Heshami, Khabat; England, Duncan G.; Humphreys, Peter C.; Bustard, Philip J.; Acosta, Victor M.; Nunn, Joshua; Sussman, Benjamin J.

2016-01-01

Quantum light–matter interfaces are at the heart of photonic quantum technologies. Quantum memories for photons, where non-classical states of photons are mapped onto stationary matter states and preserved for subsequent retrieval, are technical realizations enabled by exquisite control over interactions between light and matter. The ability of quantum memories to synchronize probabilistic events makes them a key component in quantum repeaters and quantum computation based on linear optics. This critical feature has motivated many groups to dedicate theoretical and experimental research to develop quantum memory devices. In recent years, exciting new applications, and more advanced developments of quantum memories, have proliferated. In this review, we outline some of the emerging applications of quantum memories in optical signal processing, quantum computation and non-linear optics. We review recent experimental and theoretical developments, and their impacts on more advanced photonic quantum technologies based on quantum memories. PMID:27695198

Design and fabrication of memory devices based on nanoscale polyoxometalate clusters

NASA Astrophysics Data System (ADS)

Busche, Christoph; Vilà-Nadal, Laia; Yan, Jun; Miras, Haralampos N.; Long, De-Liang; Georgiev, Vihar P.; Asenov, Asen; Pedersen, Rasmus H.; Gadegaard, Nikolaj; Mirza, Muhammad M.; Paul, Douglas J.; Poblet, Josep M.; Cronin, Leroy

2014-11-01

Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(IV)O3)2]4- as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(V)2O6]2- moiety containing a {Se(V)-Se(V)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call `write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

Pulse width and height modulation for multi-level resistance in bi-layer TaOx based RRAM

NASA Astrophysics Data System (ADS)

Alamgir, Zahiruddin; Beckmann, Karsten; Holt, Joshua; Cady, Nathaniel C.

2017-08-01

Mutli-level switching in resistive memory devices enables a wide range of computational paradigms, including neuromorphic and cognitive computing. To this end, we have developed a bi-layer tantalum oxide based resistive random access memory device using Hf as the oxygen exchange layer. Multiple, discrete resistance levels were achieved by modulating the RESET pulse width and height, ranging from 2 kΩ to several MΩ. For a fixed pulse height, OFF state resistance was found to increase gradually with the increase in the pulse width, whereas for a fixed pulse width, the increase in the pulse height resulted in drastic changes in resistance. Resistive switching in these devices transitioned from Schottky emission in the OFF state to tunneling based conduction in the ON state, based on I-V curve fitting and temperature dependent current measurements. These devices also demonstrated endurance of more than 108 cycles with a satisfactory Roff/Ron ratio and retention greater than 104 s.

Compact Method for Modeling and Simulation of Memristor Devices

DTIC Science & Technology

2011-08-01

single-valued equations. 15. SUBJECT TERMS Memristor, Neuromorphic , Cognitive, Computing, Memory, Emerging Technology, Computational Intelligence 16...resistance state depends on its previous state and present electrical biasing conditions, and when combined with transistors in a hybrid chip ...computers, reconfigurable electronics and neuromorphic computing [3,4]. According to Chua [4], the memristor behaves like a linear resistor with

Brain-Based Devices for Neuromorphic Computer Systems

DTIC Science & Technology

2013-07-01

and Deco, G. (2012). Effective Visual Working Memory Capacity: An Emergent Effect from the Neural Dynamics in an Attractor Network. PLoS ONE 7, e42719...models, apply them to a recognition task, and to demonstrate a working memory . In the course of this work a new analytical method for spiking data was...4 3.4 Spiking Neural Model Simulation of Working Memory ..................................... 5 3.5 A Novel Method for Analysis

GPU-based Parallel Application Design for Emerging Mobile Devices

NASA Astrophysics Data System (ADS)

Gupta, Kshitij

A revolution is underway in the computing world that is causing a fundamental paradigm shift in device capabilities and form-factor, with a move from well-established legacy desktop/laptop computers to mobile devices in varying sizes and shapes. Amongst all the tasks these devices must support, graphics has emerged as the 'killer app' for providing a fluid user interface and high-fidelity game rendering, effectively making the graphics processor (GPU) one of the key components in (present and future) mobile systems. By utilizing the GPU as a general-purpose parallel processor, this dissertation explores the GPU computing design space from an applications standpoint, in the mobile context, by focusing on key challenges presented by these devices---limited compute, memory bandwidth, and stringent power consumption requirements---while improving the overall application efficiency of the increasingly important speech recognition workload for mobile user interaction. We broadly partition trends in GPU computing into four major categories. We analyze hardware and programming model limitations in current-generation GPUs and detail an alternate programming style called Persistent Threads, identify four use case patterns, and propose minimal modifications that would be required for extending native support. We show how by manually extracting data locality and altering the speech recognition pipeline, we are able to achieve significant savings in memory bandwidth while simultaneously reducing the compute burden on GPU-like parallel processors. As we foresee GPU computing to evolve from its current 'co-processor' model into an independent 'applications processor' that is capable of executing complex work independently, we create an alternate application framework that enables the GPU to handle all control-flow dependencies autonomously at run-time while minimizing host involvement to just issuing commands, that facilitates an efficient application implementation. Finally, as compute and communication capabilities of mobile devices improve, we analyze energy implications of processing speech recognition locally (on-chip) and offloading it to servers (in-cloud).

Spintronic Nanodevices for Bioinspired Computing

PubMed Central

Grollier, Julie; Querlioz, Damien; Stiles, Mark D.

2016-01-01

Bioinspired hardware holds the promise of low-energy, intelligent, and highly adaptable computing systems. Applications span from automatic classification for big data management, through unmanned vehicle control, to control for biomedical prosthesis. However, one of the major challenges of fabricating bioinspired hardware is building ultra-high-density networks out of complex processing units interlinked by tunable connections. Nanometer-scale devices exploiting spin electronics (or spintronics) can be a key technology in this context. In particular, magnetic tunnel junctions (MTJs) are well suited for this purpose because of their multiple tunable functionalities. One such functionality, non-volatile memory, can provide massive embedded memory in unconventional circuits, thus escaping the von-Neumann bottleneck arising when memory and processors are located separately. Other features of spintronic devices that could be beneficial for bioinspired computing include tunable fast nonlinear dynamics, controlled stochasticity, and the ability of single devices to change functions in different operating conditions. Large networks of interacting spintronic nanodevices can have their interactions tuned to induce complex dynamics such as synchronization, chaos, soliton diffusion, phase transitions, criticality, and convergence to multiple metastable states. A number of groups have recently proposed bioinspired architectures that include one or several types of spintronic nanodevices. In this paper, we show how spintronics can be used for bioinspired computing. We review the different approaches that have been proposed, the recent advances in this direction, and the challenges toward fully integrated spintronics complementary metal–oxide–semiconductor (CMOS) bioinspired hardware. PMID:27881881

Manycore Performance-Portability: Kokkos Multidimensional Array Library

DOE PAGES

Edwards, H. Carter; Sunderland, Daniel; Porter, Vicki; ...

2012-01-01

Large, complex scientific and engineering application code have a significant investment in computational kernels to implement their mathematical models. Porting these computational kernels to the collection of modern manycore accelerator devices is a major challenge in that these devices have diverse programming models, application programming interfaces (APIs), and performance requirements. The Kokkos Array programming model provides library-based approach to implement computational kernels that are performance-portable to CPU-multicore and GPGPU accelerator devices. This programming model is based upon three fundamental concepts: (1) manycore compute devices each with its own memory space, (2) data parallel kernels and (3) multidimensional arrays. Kernel executionmore » performance is, especially for NVIDIA® devices, extremely dependent on data access patterns. Optimal data access pattern can be different for different manycore devices – potentially leading to different implementations of computational kernels specialized for different devices. The Kokkos Array programming model supports performance-portable kernels by (1) separating data access patterns from computational kernels through a multidimensional array API and (2) introduce device-specific data access mappings when a kernel is compiled. An implementation of Kokkos Array is available through Trilinos [Trilinos website, http://trilinos.sandia.gov/, August 2011].« less

Towards a Low-Cost Remote Memory Attestation for the Smart Grid

PubMed Central

Yang, Xinyu; He, Xiaofei; Yu, Wei; Lin, Jie; Li, Rui; Yang, Qingyu; Song, Houbing

2015-01-01

In the smart grid, measurement devices may be compromised by adversaries, and their operations could be disrupted by attacks. A number of schemes to efficiently and accurately detect these compromised devices remotely have been proposed. Nonetheless, most of the existing schemes detecting compromised devices depend on the incremental response time in the attestation process, which are sensitive to data transmission delay and lead to high computation and network overhead. To address the issue, in this paper, we propose a low-cost remote memory attestation scheme (LRMA), which can efficiently and accurately detect compromised smart meters considering real-time network delay and achieve low computation and network overhead. In LRMA, the impact of real-time network delay on detecting compromised nodes can be eliminated via investigating the time differences reported from relay nodes. Furthermore, the attestation frequency in LRMA is dynamically adjusted with the compromised probability of each node, and then, the total number of attestations could be reduced while low computation and network overhead can be achieved. Through a combination of extensive theoretical analysis and evaluations, our data demonstrate that our proposed scheme can achieve better detection capacity and lower computation and network overhead in comparison to existing schemes. PMID:26307998

Towards a Low-Cost Remote Memory Attestation for the Smart Grid.

PubMed

Yang, Xinyu; He, Xiaofei; Yu, Wei; Lin, Jie; Li, Rui; Yang, Qingyu; Song, Houbing

2015-08-21

In the smart grid, measurement devices may be compromised by adversaries, and their operations could be disrupted by attacks. A number of schemes to efficiently and accurately detect these compromised devices remotely have been proposed. Nonetheless, most of the existing schemes detecting compromised devices depend on the incremental response time in the attestation process, which are sensitive to data transmission delay and lead to high computation and network overhead. To address the issue, in this paper, we propose a low-cost remote memory attestation scheme (LRMA), which can efficiently and accurately detect compromised smart meters considering real-time network delay and achieve low computation and network overhead. In LRMA, the impact of real-time network delay on detecting compromised nodes can be eliminated via investigating the time differences reported from relay nodes. Furthermore, the attestation frequency in LRMA is dynamically adjusted with the compromised probability of each node, and then, the total number of attestations could be reduced while low computation and network overhead can be achieved. Through a combination of extensive theoretical analysis and evaluations, our data demonstrate that our proposed scheme can achieve better detection capacity and lower computation and network overhead in comparison to existing schemes.

Anatomy of filamentary threshold switching in amorphous niobium oxide.

PubMed

Li, Shuai; Liu, Xinjun; Nandi, Sanjoy Kumar; Elliman, Robert Glen

2018-06-25

The threshold switching behaviour of Pt/NbOx/TiN devices is investigated as a function device area and NbOx film thickness and shown to reveal important insight into the structure of the self-assembled switching region. The devices exhibit combined selector-memory (1S1R) behavior after an initial voltage-controlled forming process, but exhibit symmetric threshold switching when the RESET and SET currents are kept below a critical value. In this mode, the threshold and hold voltages are independent of the device area and film thickness but the threshold current (power), while independent of device area, decreases with increasing film thickness. These results are shown to be consistent with a structure in which the threshold switching volume is confined, both laterally and vertically, to the region between the residual memory filament and the TiN electrode, and where the memory filament has a core-shell structure comprising a metallic core and a semiconducting shell. The veracity of this structure is demonstrated by comparing experimental results with the predictions of a simple circuit model, and more detailed finite element simulations. These results provide further insight into the structure and operation of NbOx threshold switching devices that have application in emerging memory and neuromorphic computing fields. © 2018 IOP Publishing Ltd.

RRAM-based parallel computing architecture using k-nearest neighbor classification for pattern recognition

NASA Astrophysics Data System (ADS)

Jiang, Yuning; Kang, Jinfeng; Wang, Xinan

2017-03-01

Resistive switching memory (RRAM) is considered as one of the most promising devices for parallel computing solutions that may overcome the von Neumann bottleneck of today’s electronic systems. However, the existing RRAM-based parallel computing architectures suffer from practical problems such as device variations and extra computing circuits. In this work, we propose a novel parallel computing architecture for pattern recognition by implementing k-nearest neighbor classification on metal-oxide RRAM crossbar arrays. Metal-oxide RRAM with gradual RESET behaviors is chosen as both the storage and computing components. The proposed architecture is tested by the MNIST database. High speed (~100 ns per example) and high recognition accuracy (97.05%) are obtained. The influence of several non-ideal device properties is also discussed, and it turns out that the proposed architecture shows great tolerance to device variations. This work paves a new way to achieve RRAM-based parallel computing hardware systems with high performance.

Device and method to enhance availability of cluster-based processing systems

NASA Technical Reports Server (NTRS)

Lupia, David J. (Inventor); Ramos, Jeremy (Inventor); Samson, Jr., John R. (Inventor)

2010-01-01

An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Enhancing Mobile Working Memory Training by Using Affective Feedback

ERIC Educational Resources Information Center

Schaaff, Kristina

2013-01-01

The objective of this paper is to propose a novel approach to enhance working memory (WM) training for mobile devices by using information about the arousal level of a person. By the example of an adaptive n-back task, we combine methodologies from different disciplines to tackle this challenge: mobile learning, affective computing and cognitive…

Children, Teachers and Computers. P.E.N. (Primary English Notes) 45.

ERIC Educational Resources Information Center

Moore, Tony

1984-01-01

The purpose of this focused newsletter is to give teachers who know little or nothing of computers some background on which to base further investigation and decisions. It begins by explaining what a computer is and defining such terms as software, hardware, memory, input/output devices, and disk drive. The newsletter then outlines four major uses…

Neuromorphic Computing – From Materials Research to Systems Architecture Roundtable

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schuller, Ivan K.; Stevens, Rick; Pino, Robinson

2015-10-29

Computation in its many forms is the engine that fuels our modern civilization. Modern computation—based on the von Neumann architecture—has allowed, until now, the development of continuous improvements, as predicted by Moore’s law. However, computation using current architectures and materials will inevitably—within the next 10 years—reach a limit because of fundamental scientific reasons. DOE convened a roundtable of experts in neuromorphic computing systems, materials science, and computer science in Washington on October 29-30, 2015 to address the following basic questions: Can brain-like (“neuromorphic”) computing devices based on new material concepts and systems be developed to dramatically outperform conventional CMOS basedmore » technology? If so, what are the basic research challenges for materials sicence and computing? The overarching answer that emerged was: The development of novel functional materials and devices incorporated into unique architectures will allow a revolutionary technological leap toward the implementation of a fully “neuromorphic” computer. To address this challenge, the following issues were considered: The main differences between neuromorphic and conventional computing as related to: signaling models, timing/clock, non-volatile memory, architecture, fault tolerance, integrated memory and compute, noise tolerance, analog vs. digital, and in situ learning New neuromorphic architectures needed to: produce lower energy consumption, potential novel nanostructured materials, and enhanced computation Device and materials properties needed to implement functions such as: hysteresis, stability, and fault tolerance Comparisons of different implementations: spin torque, memristors, resistive switching, phase change, and optical schemes for enhanced breakthroughs in performance, cost, fault tolerance, and/or manufacturability.« less

FPGA cluster for high-performance AO real-time control system

NASA Astrophysics Data System (ADS)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Allada, Veerendra, Benjegerdes, Troy; Bode, Brett

Commodity clusters augmented with application accelerators are evolving as competitive high performance computing systems. The Graphical Processing Unit (GPU) with a very high arithmetic density and performance per price ratio is a good platform for the scientific application acceleration. In addition to the interconnect bottlenecks among the cluster compute nodes, the cost of memory copies between the host and the GPU device have to be carefully amortized to improve the overall efficiency of the application. Scientific applications also rely on efficient implementation of the BAsic Linear Algebra Subroutines (BLAS), among which the General Matrix Multiply (GEMM) is considered as themore » workhorse subroutine. In this paper, they study the performance of the memory copies and GEMM subroutines that are critical to port the computational chemistry algorithms to the GPU clusters. To that end, a benchmark based on the NetPIPE framework is developed to evaluate the latency and bandwidth of the memory copies between the host and the GPU device. The performance of the single and double precision GEMM subroutines from the NVIDIA CUBLAS 2.0 library are studied. The results have been compared with that of the BLAS routines from the Intel Math Kernel Library (MKL) to understand the computational trade-offs. The test bed is a Intel Xeon cluster equipped with NVIDIA Tesla GPUs.« less

Materials and other needs for advanced phase change memory (Presentation Recording)

NASA Astrophysics Data System (ADS)

Sosa, Norma E.

2015-09-01

Phase change memory (PCM), with its long history, may now hold its brightest promise to date. This bright future is being fueled by the "push" from big data. PCM is a non-volatile memory technology used to create solid-state random access memory devices that operate based the resistance properties of materials. Employing the electrical resistance differences-as opposed to differences in charge stored-between the amorphous and crystalline phases of the material, PCM can store bits, namely one's and zero's. Indeed, owing to the method of storage, PCM can in fact be designed to hold multiple bits thus leading to a high-density technology twice the storage density and less than half the cost of DRAM, the main kind found in typical personal computers. It has been long known that PCM can fill a need gap that spans 3 decades in performance from DRAM to solid state drive (NAND Flash). Furthermore, PCM devices can lead to performance and reliability improvements essential to enabling significant steps forward to supporting big data centric computing. This talk will focus on the science and challenges of aggressive scaling to realize the density needed, how this scaling challenge is intertwined with materials needs for endurance into the giga-cycles, and the associated forefront research aiming to realizing multi-level functionality into these nanoscale programmable resistor devices.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Global positioning system recorder and method

DOEpatents

Hayes, D.W.; Hofstetter, K.J.; Eakle, R.F. Jr.; Reeves, G.E.

1998-12-22

A global positioning system recorder (GPSR) is disclosed in which operational parameters and recorded positional data are stored on a transferable memory element. Through this transferrable memory element, the user of the GPSR need have no knowledge of GPSR devices other than that the memory element needs to be inserted into the memory element slot and the GPSR must be activated. The use of the data element also allows for minimal downtime of the GPSR and the ability to reprogram the GPSR and download data therefrom, without having to physically attach it to another computer. 4 figs.

Global positioning system recorder and method government rights

DOEpatents

Hayes, David W.; Hofstetter, Kenneth J.; Eakle, Jr., Robert F.; Reeves, George E.

1998-01-01

A global positioning system recorder (GPSR) is disclosed in which operational parameters and recorded positional data are stored on a transferable memory element. Through this transferrable memory element, the user of the GPSR need have no knowledge of GPSR devices other than that the memory element needs to be inserted into the memory element slot and the GPSR must be activated. The use of the data element also allows for minimal downtime of the GPSR and the ability to reprogram the GPSR and download data therefrom, without having to physically attach it to another computer.

Mobile computing in critical care.

PubMed

Lapinsky, Stephen E

2007-03-01

Handheld computing devices are increasingly used by health care workers, and offer a mobile platform for point-of-care information access. Improved technology, with larger memory capacity, higher screen resolution, faster processors, and wireless connectivity has broadened the potential roles for these devices in critical care. In addition to the personal information management functions, handheld computers have been used to access reference information, management guidelines and pharmacopoeias as well as to track the educational experience of trainees. They can act as an interface with a clinical information system, providing rapid access to patient information. Despite their popularity, these devices have limitations related to their small size, and acceptance by physicians has not been uniform. In the critical care environment, the risk of transmitting microorganisms by such a portable device should always be considered.

Temperature induced complementary switching in titanium oxide resistive random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Panda, D., E-mail: dpanda@nist.edu; Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan; Simanjuntak, F. M.

2016-07-15

On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400°C induces CRRAM. Forming voltage of 4.3 V is required for this device tomore » initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 μA. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices.« less

Xyce parallel electronic simulator users guide, version 6.1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Keiter, Eric R; Mei, Ting; Russo, Thomas V.

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas; Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers; A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to developmore » new types of analysis without requiring the implementation of analysis-specific device models; Device models that are specifically tailored to meet Sandia's needs, including some radiationaware devices (for Sandia users only); and Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase-a message passing parallel implementation-which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.« less

Xyce parallel electronic simulator users' guide, Version 6.0.1.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Keiter, Eric R; Mei, Ting; Russo, Thomas V.

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to developmore » new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandias needs, including some radiationaware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.« less

Xyce parallel electronic simulator users guide, version 6.0.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Keiter, Eric R; Mei, Ting; Russo, Thomas V.

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to developmore » new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandias needs, including some radiationaware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.« less

Arranging computer architectures to create higher-performance controllers

NASA Technical Reports Server (NTRS)

Jacklin, Stephen A.

1988-01-01

Techniques for integrating microprocessors, array processors, and other intelligent devices in control systems are reviewed, with an emphasis on the (re)arrangement of components to form distributed or parallel processing systems. Consideration is given to the selection of the host microprocessor, increasing the power and/or memory capacity of the host, multitasking software for the host, array processors to reduce computation time, the allocation of real-time and non-real-time events to different computer subsystems, intelligent devices to share the computational burden for real-time events, and intelligent interfaces to increase communication speeds. The case of a helicopter vibration-suppression and stabilization controller is analyzed as an example, and significant improvements in computation and throughput rates are demonstrated.

Multipulse addressing of a Raman quantum memory: configurable beam splitting and efficient readout.

PubMed

Reim, K F; Nunn, J; Jin, X-M; Michelberger, P S; Champion, T F M; England, D G; Lee, K C; Kolthammer, W S; Langford, N K; Walmsley, I A

2012-06-29

Quantum memories are vital to the scalability of photonic quantum information processing (PQIP), since the storage of photons enables repeat-until-success strategies. On the other hand, the key element of all PQIP architectures is the beam splitter, which allows us to coherently couple optical modes. Here, we show how to combine these crucial functionalities by addressing a Raman quantum memory with multiple control pulses. The result is a coherent optical storage device with an extremely large time bandwidth product, that functions as an array of dynamically configurable beam splitters, and that can be read out with arbitrarily high efficiency. Networks of such devices would allow fully scalable PQIP, with applications in quantum computation, long distance quantum communications and quantum metrology.

Marketplace of Memory: What the Brain Fitness Technology Industry Says about Us and How We Can Do Better

ERIC Educational Resources Information Center

George, Daniel R.; Whitehouse, Peter J.

2011-01-01

In the therapeutic void created by over 20 failed Alzheimer's disease drugs during the past decade, a new marketplace of "brain fitness" technology products has emerged. Ranging from video games and computer software to mobile phone apps and hand-held devices, these commercial products promise to maintain and enhance the memory,…

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

Physical Realization of a Supervised Learning System Built with Organic Memristive Synapses

NASA Astrophysics Data System (ADS)

Lin, Yu-Pu; Bennett, Christopher H.; Cabaret, Théo; Vodenicarevic, Damir; Chabi, Djaafar; Querlioz, Damien; Jousselme, Bruno; Derycke, Vincent; Klein, Jacques-Olivier

2016-09-01

Multiple modern applications of electronics call for inexpensive chips that can perform complex operations on natural data with limited energy. A vision for accomplishing this is implementing hardware neural networks, which fuse computation and memory, with low cost organic electronics. A challenge, however, is the implementation of synapses (analog memories) composed of such materials. In this work, we introduce robust, fastly programmable, nonvolatile organic memristive nanodevices based on electrografted redox complexes that implement synapses thanks to a wide range of accessible intermediate conductivity states. We demonstrate experimentally an elementary neural network, capable of learning functions, which combines four pairs of organic memristors as synapses and conventional electronics as neurons. Our architecture is highly resilient to issues caused by imperfect devices. It tolerates inter-device variability and an adaptable learning rule offers immunity against asymmetries in device switching. Highly compliant with conventional fabrication processes, the system can be extended to larger computing systems capable of complex cognitive tasks, as demonstrated in complementary simulations.

Physical Realization of a Supervised Learning System Built with Organic Memristive Synapses.

PubMed

Lin, Yu-Pu; Bennett, Christopher H; Cabaret, Théo; Vodenicarevic, Damir; Chabi, Djaafar; Querlioz, Damien; Jousselme, Bruno; Derycke, Vincent; Klein, Jacques-Olivier

2016-09-07

Multiple modern applications of electronics call for inexpensive chips that can perform complex operations on natural data with limited energy. A vision for accomplishing this is implementing hardware neural networks, which fuse computation and memory, with low cost organic electronics. A challenge, however, is the implementation of synapses (analog memories) composed of such materials. In this work, we introduce robust, fastly programmable, nonvolatile organic memristive nanodevices based on electrografted redox complexes that implement synapses thanks to a wide range of accessible intermediate conductivity states. We demonstrate experimentally an elementary neural network, capable of learning functions, which combines four pairs of organic memristors as synapses and conventional electronics as neurons. Our architecture is highly resilient to issues caused by imperfect devices. It tolerates inter-device variability and an adaptable learning rule offers immunity against asymmetries in device switching. Highly compliant with conventional fabrication processes, the system can be extended to larger computing systems capable of complex cognitive tasks, as demonstrated in complementary simulations.

Trinary flip-flops using Savart plate and spatial light modulator for optical computation in multivalued logic

NASA Astrophysics Data System (ADS)

Ghosh, Amal K.; Basuray, Amitabha

2008-11-01

The memory devices in multi-valued logic are of most significance in modern research. This paper deals with the implementation of basic memory devices in multi-valued logic using Savart plate and spatial light modulator (SLM) based optoelectronic circuits. Photons are used here as the carrier to speed up the operations. Optical tree architecture (OTA) has been also utilized in the optical interconnection network. We have exploited the advantages of Savart plates, SLMs and OTA and proposed the SLM based high speed JK, D-type and T-type flip-flops in a trinary system.

Hardware enabled performance counters with support for operating system context switching

DOEpatents

Salapura, Valentina; Wisniewski, Robert W.

2015-06-30

A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.

Quantifying redox-induced Schottky barrier variations in memristive devices via in operando spectromicroscopy with graphene electrodes

PubMed Central

Baeumer, Christoph; Schmitz, Christoph; Marchewka, Astrid; Mueller, David N.; Valenta, Richard; Hackl, Johanna; Raab, Nicolas; Rogers, Steven P.; Khan, M. Imtiaz; Nemsak, Slavomir; Shim, Moonsub; Menzel, Stephan; Schneider, Claus Michael; Waser, Rainer; Dittmann, Regina

2016-01-01

The continuing revolutionary success of mobile computing and smart devices calls for the development of novel, cost- and energy-efficient memories. Resistive switching is attractive because of, inter alia, increased switching speed and device density. On electrical stimulus, complex nanoscale redox processes are suspected to induce a resistance change in memristive devices. Quantitative information about these processes, which has been experimentally inaccessible so far, is essential for further advances. Here we use in operando spectromicroscopy to verify that redox reactions drive the resistance change. A remarkable agreement between experimental quantification of the redox state and device simulation reveals that changes in donor concentration by a factor of 2–3 at electrode-oxide interfaces cause a modulation of the effective Schottky barrier and lead to >2 orders of magnitude change in device resistance. These findings allow realistic device simulations, opening a route to less empirical and more predictive design of future memory cells. PMID:27539213

Quantifying redox-induced Schottky barrier variations in memristive devices via in operando spectromicroscopy with graphene electrodes.

PubMed

Baeumer, Christoph; Schmitz, Christoph; Marchewka, Astrid; Mueller, David N; Valenta, Richard; Hackl, Johanna; Raab, Nicolas; Rogers, Steven P; Khan, M Imtiaz; Nemsak, Slavomir; Shim, Moonsub; Menzel, Stephan; Schneider, Claus Michael; Waser, Rainer; Dittmann, Regina

2016-08-19

The continuing revolutionary success of mobile computing and smart devices calls for the development of novel, cost- and energy-efficient memories. Resistive switching is attractive because of, inter alia, increased switching speed and device density. On electrical stimulus, complex nanoscale redox processes are suspected to induce a resistance change in memristive devices. Quantitative information about these processes, which has been experimentally inaccessible so far, is essential for further advances. Here we use in operando spectromicroscopy to verify that redox reactions drive the resistance change. A remarkable agreement between experimental quantification of the redox state and device simulation reveals that changes in donor concentration by a factor of 2-3 at electrode-oxide interfaces cause a modulation of the effective Schottky barrier and lead to >2 orders of magnitude change in device resistance. These findings allow realistic device simulations, opening a route to less empirical and more predictive design of future memory cells.

Quantifying redox-induced Schottky barrier variations in memristive devices via in operando spectromicroscopy with graphene electrodes

NASA Astrophysics Data System (ADS)

Baeumer, Christoph; Schmitz, Christoph; Marchewka, Astrid; Mueller, David N.; Valenta, Richard; Hackl, Johanna; Raab, Nicolas; Rogers, Steven P.; Khan, M. Imtiaz; Nemsak, Slavomir; Shim, Moonsub; Menzel, Stephan; Schneider, Claus Michael; Waser, Rainer; Dittmann, Regina

2016-08-01

The continuing revolutionary success of mobile computing and smart devices calls for the development of novel, cost- and energy-efficient memories. Resistive switching is attractive because of, inter alia, increased switching speed and device density. On electrical stimulus, complex nanoscale redox processes are suspected to induce a resistance change in memristive devices. Quantitative information about these processes, which has been experimentally inaccessible so far, is essential for further advances. Here we use in operando spectromicroscopy to verify that redox reactions drive the resistance change. A remarkable agreement between experimental quantification of the redox state and device simulation reveals that changes in donor concentration by a factor of 2-3 at electrode-oxide interfaces cause a modulation of the effective Schottky barrier and lead to >2 orders of magnitude change in device resistance. These findings allow realistic device simulations, opening a route to less empirical and more predictive design of future memory cells.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Pilot-Vehicle Interface

DTIC Science & Technology

1993-11-01

way is to develop a crude but working model of an entire system. The other is by developing a realistic model of the user interface , leaving out most...devices or by incorporating software for a more user -friendly interface . Automation introduces the possibility of making data entry errors. Multimode...across various human- computer interfaces . 127 a Memory: Minimize the amount of information that the user must maintain in short-term memory

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Interplay of multiple synaptic plasticity features in filamentary memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

La Barbera, Selina; Vincent, Adrien F.; Vuillaume, Dominique; Querlioz, Damien; Alibart, Fabien

2016-12-01

Bio-inspired computing represents today a major challenge at different levels ranging from material science for the design of innovative devices and circuits to computer science for the understanding of the key features required for processing of natural data. In this paper, we propose a detail analysis of resistive switching dynamics in electrochemical metallization cells for synaptic plasticity implementation. We show how filament stability associated to joule effect during switching can be used to emulate key synaptic features such as short term to long term plasticity transition and spike timing dependent plasticity. Furthermore, an interplay between these different synaptic features is demonstrated for object motion detection in a spike-based neuromorphic circuit. System level simulation presents robust learning and promising synaptic operation paving the way to complex bio-inspired computing systems composed of innovative memory devices.

Graphics Processing Units for HEP trigger systems

NASA Astrophysics Data System (ADS)

Ammendola, R.; Bauce, M.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Fantechi, R.; Fiorini, M.; Giagu, S.; Gianoli, A.; Lamanna, G.; Lonardo, A.; Messina, A.; Neri, I.; Paolucci, P. S.; Piandani, R.; Pontisso, L.; Rescigno, M.; Simula, F.; Sozzi, M.; Vicini, P.

2016-07-01

General-purpose computing on GPUs (Graphics Processing Units) is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of such devices as accelerator in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughput, the use of such devices for real-time applications in high-energy physics data acquisition and trigger systems is becoming ripe. We will discuss the use of online parallel computing on GPU for synchronous low level trigger, focusing on CERN NA62 experiment trigger system. The use of GPU in higher level trigger system is also briefly considered.

LiteNet: Lightweight Neural Network for Detecting Arrhythmias at Resource-Constrained Mobile Devices.

PubMed

He, Ziyang; Zhang, Xiaoqing; Cao, Yangjie; Liu, Zhi; Zhang, Bo; Wang, Xiaoyan

2018-04-17

By running applications and services closer to the user, edge processing provides many advantages, such as short response time and reduced network traffic. Deep-learning based algorithms provide significantly better performances than traditional algorithms in many fields but demand more resources, such as higher computational power and more memory. Hence, designing deep learning algorithms that are more suitable for resource-constrained mobile devices is vital. In this paper, we build a lightweight neural network, termed LiteNet which uses a deep learning algorithm design to diagnose arrhythmias, as an example to show how we design deep learning schemes for resource-constrained mobile devices. Compare to other deep learning models with an equivalent accuracy, LiteNet has several advantages. It requires less memory, incurs lower computational cost, and is more feasible for deployment on resource-constrained mobile devices. It can be trained faster than other neural network algorithms and requires less communication across different processing units during distributed training. It uses filters of heterogeneous size in a convolutional layer, which contributes to the generation of various feature maps. The algorithm was tested using the MIT-BIH electrocardiogram (ECG) arrhythmia database; the results showed that LiteNet outperforms comparable schemes in diagnosing arrhythmias, and in its feasibility for use at the mobile devices.

LiteNet: Lightweight Neural Network for Detecting Arrhythmias at Resource-Constrained Mobile Devices

PubMed Central

Zhang, Xiaoqing; Cao, Yangjie; Liu, Zhi; Zhang, Bo; Wang, Xiaoyan

2018-01-01

By running applications and services closer to the user, edge processing provides many advantages, such as short response time and reduced network traffic. Deep-learning based algorithms provide significantly better performances than traditional algorithms in many fields but demand more resources, such as higher computational power and more memory. Hence, designing deep learning algorithms that are more suitable for resource-constrained mobile devices is vital. In this paper, we build a lightweight neural network, termed LiteNet which uses a deep learning algorithm design to diagnose arrhythmias, as an example to show how we design deep learning schemes for resource-constrained mobile devices. Compare to other deep learning models with an equivalent accuracy, LiteNet has several advantages. It requires less memory, incurs lower computational cost, and is more feasible for deployment on resource-constrained mobile devices. It can be trained faster than other neural network algorithms and requires less communication across different processing units during distributed training. It uses filters of heterogeneous size in a convolutional layer, which contributes to the generation of various feature maps. The algorithm was tested using the MIT-BIH electrocardiogram (ECG) arrhythmia database; the results showed that LiteNet outperforms comparable schemes in diagnosing arrhythmias, and in its feasibility for use at the mobile devices. PMID:29673171

Enhanced oxygen vacancy diffusion in Ta2O5 resistive memory devices due to infinitely adaptive crystal structure

NASA Astrophysics Data System (ADS)

Jiang, Hao; Stewart, Derek A.

2016-04-01

Metal oxide resistive memory devices based on Ta2O5 have demonstrated high switching speed, long endurance, and low set voltage. However, the physical origin of this improved performance is still unclear. Ta2O5 is an important archetype of a class of materials that possess an adaptive crystal structure that can respond easily to the presence of defects. Using first principles nudged elastic band calculations, we show that this adaptive crystal structure leads to low energy barriers for in-plane diffusion of oxygen vacancies in λ phase Ta2O5. Identified diffusion paths are associated with collective motion of neighboring atoms. The overall vacancy diffusion is anisotropic with higher diffusion barriers found for oxygen vacancy movement between Ta-O planes. Coupled with the fact that oxygen vacancy formation energy in Ta2O5 is relatively small, our calculated low diffusion barriers can help explain the low set voltage in Ta2O5 based resistive memory devices. Our work shows that other oxides with adaptive crystal structures could serve as potential candidates for resistive random access memory devices. We also discuss some general characteristics for ideal resistive RAM oxides that could be used in future computational material searches.

Apple's Macintosh.

ERIC Educational Resources Information Center

Miller, Michael J.

1984-01-01

Description of the Macintosh personal, educational, and business computer produced by Apple covers cost; physical characteristics including display devices, circuit boards, and built-in features; company-produced software; third-party produced software; memory and storage capacity; word-processing features; and graphics capabilities. (MBR)

Holography and optical information processing; Proceedings of the Soviet-Chinese Joint Seminar, Bishkek, Kyrgyzstan, Sept. 21-26, 1991

NASA Astrophysics Data System (ADS)

Mikaelian, Andrei L.

Attention is given to data storage, devices, architectures, and implementations of optical memory and neural networks; holographic optical elements and computer-generated holograms; holographic display and materials; systems, pattern recognition, interferometry, and applications in optical information processing; and special measurements and devices. Topics discussed include optical immersion as a new way to increase information recording density, systems for data reading from optical disks on the basis of diffractive lenses, a new real-time optical associative memory system, an optical pattern recognition system based on a WTA model of neural networks, phase diffraction grating for the integral transforms of coherent light fields, holographic recording with operated sensitivity and stability in chalcogenide glass layers, a compact optical logic processor, a hybrid optical system for computing invariant moments of images, optical fiber holographic inteferometry, and image transmission through random media in single pass via optical phase conjugation.

Ultralow-power switching via defect engineering in germanium telluride phase-change memory devices.

PubMed

Nukala, Pavan; Lin, Chia-Chun; Composto, Russell; Agarwal, Ritesh

2016-01-25

Crystal-amorphous transformation achieved via the melt-quench pathway in phase-change memory involves fundamentally inefficient energy conversion events; and this translates to large switching current densities, responsible for chemical segregation and device degradation. Alternatively, introducing defects in the crystalline phase can engineer carrier localization effects enhancing carrier-lattice coupling; and this can efficiently extract work required to introduce bond distortions necessary for amorphization from input electrical energy. Here, by pre-inducing extended defects and thus carrier localization effects in crystalline GeTe via high-energy ion irradiation, we show tremendous improvement in amorphization current densities (0.13-0.6 MA cm(-2)) compared with the melt-quench strategy (∼50 MA cm(-2)). We show scaling behaviour and good reversibility on these devices, and explore several intermediate resistance states that are accessible during both amorphization and recrystallization pathways. Existence of multiple resistance states, along with ultralow-power switching and scaling capabilities, makes this approach promising in context of low-power memory and neuromorphic computation.

Ultralow-power switching via defect engineering in germanium telluride phase-change memory devices

PubMed Central

Nukala, Pavan; Lin, Chia-Chun; Composto, Russell; Agarwal, Ritesh

2016-01-01

Crystal–amorphous transformation achieved via the melt-quench pathway in phase-change memory involves fundamentally inefficient energy conversion events; and this translates to large switching current densities, responsible for chemical segregation and device degradation. Alternatively, introducing defects in the crystalline phase can engineer carrier localization effects enhancing carrier–lattice coupling; and this can efficiently extract work required to introduce bond distortions necessary for amorphization from input electrical energy. Here, by pre-inducing extended defects and thus carrier localization effects in crystalline GeTe via high-energy ion irradiation, we show tremendous improvement in amorphization current densities (0.13–0.6 MA cm−2) compared with the melt-quench strategy (∼50 MA cm−2). We show scaling behaviour and good reversibility on these devices, and explore several intermediate resistance states that are accessible during both amorphization and recrystallization pathways. Existence of multiple resistance states, along with ultralow-power switching and scaling capabilities, makes this approach promising in context of low-power memory and neuromorphic computation. PMID:26805748

Storing and managing information artifacts collected by information analysts using a computing device

DOEpatents

Pike, William A; Riensche, Roderick M; Best, Daniel M; Roberts, Ian E; Whyatt, Marie V; Hart, Michelle L; Carr, Norman J; Thomas, James J

2012-09-18

Systems and computer-implemented processes for storage and management of information artifacts collected by information analysts using a computing device. The processes and systems can capture a sequence of interactive operation elements that are performed by the information analyst, who is collecting an information artifact from at least one of the plurality of software applications. The information artifact can then be stored together with the interactive operation elements as a snippet on a memory device, which is operably connected to the processor. The snippet comprises a view from an analysis application, data contained in the view, and the sequence of interactive operation elements stored as a provenance representation comprising operation element class, timestamp, and data object attributes for each interactive operation element in the sequence.

Investigation of single crystal ferrite thin films

NASA Technical Reports Server (NTRS)

Mee, J. E.; Besser, P. J.; Elkins, P. E.; Glass, H. L.; Whitcomb, E. C.

1972-01-01

Materials suitable for use in magnetic bubble domain memories were developed for aerospace applications. Practical techniques for the preparation of such materials in forms required for fabrication of computer memory devices were considered. The materials studied were epitaxial films of various compositions of the gallium-substituted yttrium gadolinium iron garnet system. The major emphasis was to determine their bubble properties and the conditions necessary for growing uncracked, high quality films.

Protecting solid-state spins from a strongly coupled environment

NASA Astrophysics Data System (ADS)

Chen, Mo; Calvin Sun, Won Kyu; Saha, Kasturi; Jaskula, Jean-Christophe; Cappellaro, Paola

2018-06-01

Quantum memories are critical for solid-state quantum computing devices and a good quantum memory requires both long storage time and fast read/write operations. A promising system is the nitrogen-vacancy (NV) center in diamond, where the NV electronic spin serves as the computing qubit and a nearby nuclear spin as the memory qubit. Previous works used remote, weakly coupled 13C nuclear spins, trading read/write speed for long storage time. Here we focus instead on the intrinsic strongly coupled 14N nuclear spin. We first quantitatively understand its decoherence mechanism, identifying as its source the electronic spin that acts as a quantum fluctuator. We then propose a scheme to protect the quantum memory from the fluctuating noise by applying dynamical decoupling on the environment itself. We demonstrate a factor of 3 enhancement of the storage time in a proof-of-principle experiment, showing the potential for a quantum memory that combines fast operation with long coherence time.

An associative capacitive network based on nanoscale complementary resistive switches for memory-intensive computing

NASA Astrophysics Data System (ADS)

Kavehei, Omid; Linn, Eike; Nielen, Lutz; Tappertzhofen, Stefan; Skafidas, Efstratios; Valov, Ilia; Waser, Rainer

2013-05-01

We report on the implementation of an Associative Capacitive Network (ACN) based on the nondestructive capacitive readout of two Complementary Resistive Switches (2-CRSs). ACNs are capable of performing a fully parallel search for Hamming distances (i.e. similarity) between input and stored templates. Unlike conventional associative memories where charge retention is a key function and hence, they require frequent refresh cycles, in ACNs, information is retained in a nonvolatile resistive state and normal tasks are carried out through capacitive coupling between input and output nodes. Each device consists of two CRS cells and no selective element is needed, therefore, CMOS circuitry is only required in the periphery, for addressing and read-out. Highly parallel processing, nonvolatility, wide interconnectivity and low-energy consumption are significant advantages of ACNs over conventional and emerging associative memories. These characteristics make ACNs one of the promising candidates for applications in memory-intensive and cognitive computing, switches and routers as binary and ternary Content Addressable Memories (CAMs) and intelligent data processing.

EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

NASA Astrophysics Data System (ADS)

Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

2011-06-01

Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show that limiting the current during electroforming leads to the coexistence of two resistance switching modes in TiO2 memristive devices [2]. They also present spectromicroscopic observations and modelling results for the Joule heating during switching, providing insights into the ON/OFF switching process [3]. Researchers in Korea have examined in detail the mechanism of electronic bipolar resistance switching in the Pt/TiO2/Pt structure and show that degradation in switching performance of this system can be explained by the modified distribution of trap densities [4]. The issue also includes studies of TiO2 that demonstrate analog memory, synaptic plasticity, and spike-timing-dependent plasticity functions, work that contributes to the development of neuromorphic devices that have high efficiency and low power consumption [5]. In addition to enabling a wide range of data storage and logic applications, electroresistive non-volatile memories invite us to re-evaluate the long-held paradigms in the condensed matter physics of oxides. In the past three years, much attention has been attracted to polarization-mediated electronic transport [6, 7] and domain wall conduction [8] as the key to the next generation of electronic and spintronic devices based on ferroelectric tunnelling barriers. Typically local probe experiments are performed on an ambient scanning probe microscope platform under conditions of high voltage stresses, conditions highly conducive to electrochemical reactions. Recent experiments [9-13] suggest that ionic motion can heavily contribute to the measured responses and compete with purely physical mechanisms. Electrochemical effects can also be expected in non-ferroelectric materials such as manganites and cobaltites, as well as for thick ferroelectrics under high-field conditions, as in capacitors and tunnelling junctions where the ionic motion could be a major contributor to electric field-induced strain. Such strain, in turn, can affect the effective barrier width in tunnelling experiments, resulting in memristive ionic switching. These phenomena must be differentiated from intrinsic physical polarization switching effects. Similar analysis of solid-state electrochemistry versus physical mechanisms is also important for future research in all areas of oxide materials. In an age where miniaturised computer components can enable GPS tracking, internet access and even the remote operation of machinery from a mobile phone, there is an endearing quaintness associated with images of the large rooms rammed with wires and boxes that comprised early computers. Yet there was a time when these cumbersome devices were state of the art. When the electronic numerical integrator and computer (ENIAC) was developed it achieved speeds one thousand times faster than previous electromechanical machines, a leap in processing power that has not been achieved since. It is easy to imagine future generations looking back on the slow start up and shut down times and high energy consumption of today's computers with a similar wry smile. The articles in this special issue on non-volatile memory based on nanostructures present the very latest research into the next generation's device technology, which may eventually consign today's cutting edge electronics to the history books. References [1] Ryu S W et al 2011 Nanotechnology 22 254005 [2] Miao F, Yang J J, Borghetti J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 254007 [3] Strachan J P, Strukov D B, Borghetti J, Yang J J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 245015 [4] Kim K M, Choi B J, Lee M H, Kim G H, Song S J, Seok J Y, Yoon J H, Han S and Hwang C S 2011 Nanotechnology 22 254010 [5] Seo K et al 2011 Nanotechnology 22 254023 [6] Garcia V, Fusil S, Bouzehouane K, Enouz-Vedrenne S, Mathur N D, Barthelemy A and Bibes M 2009 Nature 460 81-4 [7] Maksymovych P, Jesse S, Yu P, Ramesh R, Baddorf A P and Kalinin S V 2009 Science 324 1421 [8] Seidel J et al 2009 Nature Mat. 8 229 [9] Tsuruoka T, Terabe K, Hasegawa T, and Aono M 2010 Nanotechnology 21 425205 [10] Waser R and Aono M 2007 Nature Mat. 6 833 [11] Sawa A 2008 Materials Today 11 28 [12] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 Nature 453 80 Changes were made to this Editorial on 16 May 2011. An author was added to the Editorial.

Realization of the Switching Mechanism in Resistance Random Access Memory™ Devices: Structural and Electronic Properties Affecting Electron Conductivity in a Hafnium Oxide-Electrode System Through First-Principles Calculations

NASA Astrophysics Data System (ADS)

Aspera, Susan Meñez; Kasai, Hideaki; Kishi, Hirofumi; Awaya, Nobuyoshi; Ohnishi, Shigeo; Tamai, Yukio

2013-01-01

The resistance random access memory (RRAM™) device, with its electrically induced nanoscale resistive switching capacity, has attracted considerable attention as a future nonvolatile memory device. Here, we propose a mechanism of switching based on an oxygen vacancy migration-driven change in the electronic properties of the transition-metal oxide film stimulated by set pulse voltages. We used density functional theory-based calculations to account for the effect of oxygen vacancies and their migration on the electronic properties of HfO2 and Ta/HfO2 systems, thereby providing a complete explanation of the RRAM™ switching mechanism. Furthermore, computational results on the activation energy barrier for oxygen vacancy migration were found to be consistent with the set and reset pulse voltage obtained from experiments. Understanding this mechanism will be beneficial to effectively realizing the materials design in these devices.

Systems and methods for performing wireless financial transactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCown, Steven Harvey

2012-07-03

A secure computing module (SCM) is configured for connection with a host device. The SCM includes a processor for performing secure processing operations, a host interface for coupling the processor to the host device, and a memory connected to the processor wherein the processor logically isolates at least some of the memory from access by the host device. The SCM also includes a proximate-field wireless communicator connected to the processor to communicate with another SCM associated with another host device. The SCM generates a secure digital signature for a financial transaction package and communicates the package and the signature tomore » the other SCM using the proximate-field wireless communicator. Financial transactions are performed from person to person using the secure digital signature of each person's SCM and possibly message encryption. The digital signatures and transaction details are communicated to appropriate financial organizations to authenticate the transaction parties and complete the transaction.« less

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same

NASA Technical Reports Server (NTRS)

Kaul, Anupama B. (Inventor); Wong, Eric W. (Inventor); Baron, Richard L. (Inventor); Epp, Larry (Inventor)

2008-01-01

Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Secure steganography designed for mobile platforms

NASA Astrophysics Data System (ADS)

Agaian, Sos S.; Cherukuri, Ravindranath; Sifuentes, Ronnie R.

2006-05-01

Adaptive steganography, an intelligent approach to message hiding, integrated with matrix encoding and pn-sequences serves as a promising resolution to recent security assurance concerns. Incorporating the above data hiding concepts with established cryptographic protocols in wireless communication would greatly increase the security and privacy of transmitting sensitive information. We present an algorithm which will address the following problems: 1) low embedding capacity in mobile devices due to fixed image dimensions and memory constraints, 2) compatibility between mobile and land based desktop computers, and 3) detection of stego images by widely available steganalysis software [1-3]. Consistent with the smaller available memory, processor capabilities, and limited resolution associated with mobile devices, we propose a more magnified approach to steganography by focusing adaptive efforts at the pixel level. This deeper method, in comparison to the block processing techniques commonly found in existing adaptive methods, allows an increase in capacity while still offering a desired level of security. Based on computer simulations using high resolution, natural imagery and mobile device captured images, comparisons show that the proposed method securely allows an increased amount of embedding capacity but still avoids detection by varying steganalysis techniques.

Storage Media for Microcomputers.

ERIC Educational Resources Information Center

Trautman, Rodes

1983-01-01

Reviews computer storage devices designed to provide additional memory for microcomputers--chips, floppy disks, hard disks, optical disks--and describes how secondary storage is used (file transfer, formatting, ingredients of incompatibility); disk/controller/software triplet; magnetic tape backup; storage volatility; disk emulator; and…

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

NMF-mGPU: non-negative matrix factorization on multi-GPU systems.

PubMed

Mejía-Roa, Edgardo; Tabas-Madrid, Daniel; Setoain, Javier; García, Carlos; Tirado, Francisco; Pascual-Montano, Alberto

2015-02-13

In the last few years, the Non-negative Matrix Factorization ( NMF ) technique has gained a great interest among the Bioinformatics community, since it is able to extract interpretable parts from high-dimensional datasets. However, the computing time required to process large data matrices may become impractical, even for a parallel application running on a multiprocessors cluster. In this paper, we present NMF-mGPU, an efficient and easy-to-use implementation of the NMF algorithm that takes advantage of the high computing performance delivered by Graphics-Processing Units ( GPUs ). Driven by the ever-growing demands from the video-games industry, graphics cards usually provided in PCs and laptops have evolved from simple graphics-drawing platforms into high-performance programmable systems that can be used as coprocessors for linear-algebra operations. However, these devices may have a limited amount of on-board memory, which is not considered by other NMF implementations on GPU. NMF-mGPU is based on CUDA ( Compute Unified Device Architecture ), the NVIDIA's framework for GPU computing. On devices with low memory available, large input matrices are blockwise transferred from the system's main memory to the GPU's memory, and processed accordingly. In addition, NMF-mGPU has been explicitly optimized for the different CUDA architectures. Finally, platforms with multiple GPUs can be synchronized through MPI ( Message Passing Interface ). In a four-GPU system, this implementation is about 120 times faster than a single conventional processor, and more than four times faster than a single GPU device (i.e., a super-linear speedup). Applications of GPUs in Bioinformatics are getting more and more attention due to their outstanding performance when compared to traditional processors. In addition, their relatively low price represents a highly cost-effective alternative to conventional clusters. In life sciences, this results in an excellent opportunity to facilitate the daily work of bioinformaticians that are trying to extract biological meaning out of hundreds of gigabytes of experimental information. NMF-mGPU can be used "out of the box" by researchers with little or no expertise in GPU programming in a variety of platforms, such as PCs, laptops, or high-end GPU clusters. NMF-mGPU is freely available at https://github.com/bioinfo-cnb/bionmf-gpu .

A self-resetting spiking phase-change neuron

NASA Astrophysics Data System (ADS)

Cobley, R. A.; Hayat, H.; Wright, C. D.

2018-05-01

Neuromorphic, or brain-inspired, computing applications of phase-change devices have to date concentrated primarily on the implementation of phase-change synapses. However, the so-called accumulation mode of operation inherent in phase-change materials and devices can also be used to mimic the integrative properties of a biological neuron. Here we demonstrate, using physical modelling of nanoscale devices and SPICE modelling of associated circuits, that a single phase-change memory cell integrated into a comparator type circuit can deliver a basic hardware mimic of an integrate-and-fire spiking neuron with self-resetting capabilities. Such phase-change neurons, in combination with phase-change synapses, can potentially open a new route for the realisation of all-phase-change neuromorphic computing.

A self-resetting spiking phase-change neuron.

PubMed

Cobley, R A; Hayat, H; Wright, C D

2018-05-11

Neuromorphic, or brain-inspired, computing applications of phase-change devices have to date concentrated primarily on the implementation of phase-change synapses. However, the so-called accumulation mode of operation inherent in phase-change materials and devices can also be used to mimic the integrative properties of a biological neuron. Here we demonstrate, using physical modelling of nanoscale devices and SPICE modelling of associated circuits, that a single phase-change memory cell integrated into a comparator type circuit can deliver a basic hardware mimic of an integrate-and-fire spiking neuron with self-resetting capabilities. Such phase-change neurons, in combination with phase-change synapses, can potentially open a new route for the realisation of all-phase-change neuromorphic computing.

Proof of Concept Study for the Design, Manufacturing, and Testing of a Patient-Specific Shape Memory Device for Treatment of Unicoronal Craniosynostosis.

PubMed

Borghi, Alessandro; Rodgers, Will; Schievano, Silvia; Ponniah, Allan; Jeelani, Owase; Dunaway, David

2018-01-01

Treatment of unicoronal craniosynostosis is a surgically challenging problem, due to the involvement of coronal suture and cranial base, with complex asymmetries of the calvarium and orbit. Several techniques for correction have been described, including surgical bony remodeling, early strip craniotomy with orthotic helmet remodeling and distraction. Current distraction devices provide unidirectional forces and have had very limited success. Nitinol is a shape memory alloy that can be programmed to the shape of a patient-specific anatomy by means of thermal treatment.In this work, a methodology to produce a nitinol patient-specific distractor is presented: computer tomography images of a 16-month-old patient with unicoronal craniosynostosis were processed to create a 3-dimensional model of his skull and define the ideal shape postsurgery. A mesh was produced from a nitinol sheet, formed to the ideal skull shape and heat treated to be malleable at room temperature. The mesh was afterward deformed to be attached to a rapid prototyped plastic skull, replica of the patient initial anatomy. The mesh/skull construct was placed in hot water to activate the mesh shape memory property: the deformed plastic skull was computed tomography scanned for comparison of its shape with the initial anatomy and with the desired shape, showing that the nitinol mesh had been able to distract the plastic skull to a shape close to the desired one.The shape-memory properties of nitinol allow for the design and production of patient-specific devices able to deliver complex, preprogrammable shape changes.

Building logical qubits in a superconducting quantum computing system

NASA Astrophysics Data System (ADS)

Gambetta, Jay M.; Chow, Jerry M.; Steffen, Matthias

2017-01-01

The technological world is in the midst of a quantum computing and quantum information revolution. Since Richard Feynman's famous `plenty of room at the bottom' lecture (Feynman, Engineering and Science23, 22 (1960)), hinting at the notion of novel devices employing quantum mechanics, the quantum information community has taken gigantic strides in understanding the potential applications of a quantum computer and laid the foundational requirements for building one. We believe that the next significant step will be to demonstrate a quantum memory, in which a system of interacting qubits stores an encoded logical qubit state longer than the incorporated parts. Here, we describe the important route towards a logical memory with superconducting qubits, employing a rotated version of the surface code. The current status of technology with regards to interconnected superconducting-qubit networks will be described and near-term areas of focus to improve devices will be identified. Overall, the progress in this exciting field has been astounding, but we are at an important turning point, where it will be critical to incorporate engineering solutions with quantum architectural considerations, laying the foundation towards scalable fault-tolerant quantum computers in the near future.

Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

DOE PAGES

Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

2014-07-22

The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diversemore » manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.« less

New World Vistas: New Models of Computation Lattice Based Quantum Computation

DTIC Science & Technology

1996-07-25

ro ns Eniac (18,000 vacuum tubes) UNIVAC II (core memory) Digital Devices magnetostrictive delay line Intel 1103 integrated circuit IBM 3340 disk...in areal size of a bit for the last fifty years since the 1946 Eniac computer. 1 Planned Research I propose to consider the feasibility of implement...tech- nology. Fiqure 1 is a log-linear plot of data for the areal size of a bit over the last fifty years (from 18,000 bits in the 1946 Eniac computer

Xyce™ Parallel Electronic Simulator Users' Guide, Version 6.5.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Keiter, Eric R.; Aadithya, Karthik V.; Mei, Ting

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to developmore » new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The information herein is subject to change without notice. Copyright © 2002-2016 Sandia Corporation. All rights reserved.« less

New Trends of Digital Data Storage in DNA

PubMed Central

2016-01-01

With the exponential growth in the capacity of information generated and the emerging need for data to be stored for prolonged period of time, there emerges a need for a storage medium with high capacity, high storage density, and possibility to withstand extreme environmental conditions. DNA emerges as the prospective medium for data storage with its striking features. Diverse encoding models for reading and writing data onto DNA, codes for encrypting data which addresses issues of error generation, and approaches for developing codons and storage styles have been developed over the recent past. DNA has been identified as a potential medium for secret writing, which achieves the way towards DNA cryptography and stenography. DNA utilized as an organic memory device along with big data storage and analytics in DNA has paved the way towards DNA computing for solving computational problems. This paper critically analyzes the various methods used for encoding and encrypting data onto DNA while identifying the advantages and capability of every scheme to overcome the drawbacks identified priorly. Cryptography and stenography techniques have been analyzed in a critical approach while identifying the limitations of each method. This paper also identifies the advantages and limitations of DNA as a memory device and memory applications. PMID:27689089

New Trends of Digital Data Storage in DNA.

PubMed

De Silva, Pavani Yashodha; Ganegoda, Gamage Upeksha

With the exponential growth in the capacity of information generated and the emerging need for data to be stored for prolonged period of time, there emerges a need for a storage medium with high capacity, high storage density, and possibility to withstand extreme environmental conditions. DNA emerges as the prospective medium for data storage with its striking features. Diverse encoding models for reading and writing data onto DNA, codes for encrypting data which addresses issues of error generation, and approaches for developing codons and storage styles have been developed over the recent past. DNA has been identified as a potential medium for secret writing, which achieves the way towards DNA cryptography and stenography. DNA utilized as an organic memory device along with big data storage and analytics in DNA has paved the way towards DNA computing for solving computational problems. This paper critically analyzes the various methods used for encoding and encrypting data onto DNA while identifying the advantages and capability of every scheme to overcome the drawbacks identified priorly. Cryptography and stenography techniques have been analyzed in a critical approach while identifying the limitations of each method. This paper also identifies the advantages and limitations of DNA as a memory device and memory applications.

GPU-accelerated computing for Lagrangian coherent structures of multi-body gravitational regimes

NASA Astrophysics Data System (ADS)

Lin, Mingpei; Xu, Ming; Fu, Xiaoyu

2017-04-01

Based on a well-established theoretical foundation, Lagrangian Coherent Structures (LCSs) have elicited widespread research on the intrinsic structures of dynamical systems in many fields, including the field of astrodynamics. Although the application of LCSs in dynamical problems seems straightforward theoretically, its associated computational cost is prohibitive. We propose a block decomposition algorithm developed on Compute Unified Device Architecture (CUDA) platform for the computation of the LCSs of multi-body gravitational regimes. In order to take advantage of GPU's outstanding computing properties, such as Shared Memory, Constant Memory, and Zero-Copy, the algorithm utilizes a block decomposition strategy to facilitate computation of finite-time Lyapunov exponent (FTLE) fields of arbitrary size and timespan. Simulation results demonstrate that this GPU-based algorithm can satisfy double-precision accuracy requirements and greatly decrease the time needed to calculate final results, increasing speed by approximately 13 times. Additionally, this algorithm can be generalized to various large-scale computing problems, such as particle filters, constellation design, and Monte-Carlo simulation.

Multiprocessor switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

2014-03-11

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

32 CFR 701.54 - Collection of fees and fee rates for technical data.

Code of Federal Regulations, 2014 CFR

2014-07-01

...) Computer search is based on the total cost of the central processing unit, input-output devices, and memory... charge for office copy up to six images)—$3.50 Each additional image—$ .10 Each typewritten page—$3.50...

32 CFR 701.54 - Collection of fees and fee rates for technical data.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) Computer search is based on the total cost of the central processing unit, input-output devices, and memory... charge for office copy up to six images)—$3.50 Each additional image—$ .10 Each typewritten page—$3.50...

Implementation of real-time digital signal processing systems

NASA Technical Reports Server (NTRS)

Narasimha, M.; Peterson, A.; Narayan, S.

1978-01-01

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Cloud-based crowd sensing: a framework for location-based crowd analyzer and advisor

NASA Astrophysics Data System (ADS)

Aishwarya, K. C.; Nambi, A.; Hudson, S.; Nadesh, R. K.

2017-11-01

Cloud computing is an emerging field of computer science to integrate and explore large and powerful computing systems and storages for personal and also for enterprise requirements. Mobile Cloud Computing is the inheritance of this concept towards mobile hand-held devices. Crowdsensing, or to be precise, Mobile Crowdsensing is the process of sharing resources from an available group of mobile handheld devices that support sharing of different resources such as data, memory and bandwidth to perform a single task for collective reasons. In this paper, we propose a framework to use Crowdsensing and perform a crowd analyzer and advisor whether the user can go to the place or not. This is an ongoing research and is a new concept to which the direction of cloud computing has shifted and is viable for more expansion in the near future.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Roy, Kaushik

2018-03-01

“Spintronics” refers to the understanding of the physics of electron spin-related phenomena. While most of the significant advancements in this field has been driven primarily by memory, recent research has demonstrated that various facets of the underlying physics of spin transport and manipulation can directly mimic the functionalities of the computational primitives in neuromorphic computation, i.e., the neurons and synapses. Given the potential of these spintronic devices to implement bio-mimetic computations at very low terminal voltages, several spin-device structures have been proposed as the core building blocks of neuromorphic circuits and systems to implement brain-inspired computing. Such an approach is expected to play a key role in circumventing the problems of ever-increasing power dissipation and hardware requirements for implementing neuro-inspired algorithms in conventional digital CMOS technology. Perspectives on spin-enabled neuromorphic computing, its status, and challenges and future prospects are outlined in this review article.

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bergman, Keren

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformationalmore » advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.« less

An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

NASA Astrophysics Data System (ADS)

Liu, Chen; Han, Runze; Zhou, Zheng; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2018-04-01

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

Interfacial interactions and their impact on redox-based resistive switching memories (ReRAMs)

NASA Astrophysics Data System (ADS)

Valov, Ilia

2017-09-01

Redox-based resistive switching memories are nowadays one of the most studied systems in both academia and industrial communities. These devices are scalable down to an almost atomic level and are supposed to be applicable not only for next-generation nonvolatile memories, but also for neuromorphic computing, alternative logic operations and selector devices. The main characteristic feature of these cells is their nano- to sub-nano dimension. This makes the control and especially prediction of their properties very challenging. One of the ways to achieve better understanding and to improve the control of these systems is to study and modify their interfaces. In this review, first the fundamentals will be discussed, as these are essential for understanding which factors control the nanoscale interface properties. Further, different types of interactions at the electrode/solid electrolyte interface reported for ECM- and VCM-type cells will be exemplarily shown. Finally, the strategies and different solutions used to modify the interfaces and overcome the existing problems on the way to more stable and reliable devices will be highlighted.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd E

2014-02-18

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Parallel Implementation of MAFFT on CUDA-Enabled Graphics Hardware.

PubMed

Zhu, Xiangyuan; Li, Kenli; Salah, Ahmad; Shi, Lin; Li, Keqin

2015-01-01

Multiple sequence alignment (MSA) constitutes an extremely powerful tool for many biological applications including phylogenetic tree estimation, secondary structure prediction, and critical residue identification. However, aligning large biological sequences with popular tools such as MAFFT requires long runtimes on sequential architectures. Due to the ever increasing sizes of sequence databases, there is increasing demand to accelerate this task. In this paper, we demonstrate how graphic processing units (GPUs), powered by the compute unified device architecture (CUDA), can be used as an efficient computational platform to accelerate the MAFFT algorithm. To fully exploit the GPU's capabilities for accelerating MAFFT, we have optimized the sequence data organization to eliminate the bandwidth bottleneck of memory access, designed a memory allocation and reuse strategy to make full use of limited memory of GPUs, proposed a new modified-run-length encoding (MRLE) scheme to reduce memory consumption, and used high-performance shared memory to speed up I/O operations. Our implementation tested in three NVIDIA GPUs achieves speedup up to 11.28 on a Tesla K20m GPU compared to the sequential MAFFT 7.015.

Programmable stream prefetch with resource optimization

DOEpatents

Boyle, Peter; Christ, Norman; Gara, Alan; Mawhinney, Robert; Ohmacht, Martin; Sugavanam, Krishnan

2013-01-08

A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine checks whether there exists valid data corresponding to the first memory address in an array if the first memory address is present and valid in the table. The engine increments a prefetching depth of a first stream that the first memory address belongs to and fetching a cache line associated with the first memory address from the at least one cache memory device if there is not yet valid data corresponding to the first memory address in the array. The engine determines whether prefetching of additional data is needed for the first stream within its prefetching depth. The engine prefetches the additional data if the prefetching is needed.

Synthesizing Biomolecule-based Boolean Logic Gates

PubMed Central

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2012-01-01

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

Synthesizing biomolecule-based Boolean logic gates.

PubMed

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2013-02-15

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Remote hardware-reconfigurable robotic camera

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

Fog computing job scheduling optimization based on bees swarm

NASA Astrophysics Data System (ADS)

Bitam, Salim; Zeadally, Sherali; Mellouk, Abdelhamid

2018-04-01

Fog computing is a new computing architecture, composed of a set of near-user edge devices called fog nodes, which collaborate together in order to perform computational services such as running applications, storing an important amount of data, and transmitting messages. Fog computing extends cloud computing by deploying digital resources at the premise of mobile users. In this new paradigm, management and operating functions, such as job scheduling aim at providing high-performance, cost-effective services requested by mobile users and executed by fog nodes. We propose a new bio-inspired optimization approach called Bees Life Algorithm (BLA) aimed at addressing the job scheduling problem in the fog computing environment. Our proposed approach is based on the optimized distribution of a set of tasks among all the fog computing nodes. The objective is to find an optimal tradeoff between CPU execution time and allocated memory required by fog computing services established by mobile users. Our empirical performance evaluation results demonstrate that the proposal outperforms the traditional particle swarm optimization and genetic algorithm in terms of CPU execution time and allocated memory.

Elucidation and Optimization of Resistive Random Access Memory Switching Behavior for Advanced Computing Applications

NASA Astrophysics Data System (ADS)

Alamgir, Zahiruddin

RRAM has recently emerged as a strong candidate for non-volatile memory (NVM). Beyond memory applications, RRAM holds promise for use in performing logic functions, mimicking neuromorphic activities, enabling multi-level switching, and as one of the key elements of hardware based encryption or signal processing systems. It has been shown previously that RRAM resistance levels can be changed by adjusting compliance current or voltage level. This characteristic makes RRAM suitable for use in setting the synaptic weight in neuromorphic computing circuits. RRAM is also considered as a key element in hardware encryption systems, to produce unique and reproducible signals. However, a key challenge to implement RRAM in these applications is significant cycle to cycle performance variability. We sought to develop RRAM that can be tuned to different resistance levels gradually, with high reliability, and low variability. To achieve this goal, we focused on elucidating the conduction mechanisms underlying the resistive switching behavior for these devices. Electrical conduction mechanisms were determined by curve fitting I-V data using different current conduction equations. Temperature studies were also performed to corroborate these data. It was found that Schottky barrier height and width modulation was one of the key parameters that could be tuned to achieve different resistance levels, and for switching resistance states, primarily via oxygen vacancy movement. Oxygen exchange layers with different electronegativity were placed between top electrode and the oxide layer of TaOx devices to determine the effect of oxygen vacancy concentrations and gradients in these devices. It was found that devices with OELs with lower electronegativity tend to yield greater separation in the OFF vs. ON state resistance levels. As an extension of this work, TaOx based RRAM with Hf as the OEL was fabricated and could be tuned to different resistance level using pulse width and height modulation, yielding excellent uniformity and reliability. These findings improve our understanding of conduction within TaO x-based RRAM devices, providing a physical basis for switching in these devices. The value of this work lies in the demonstration of devices with excellent performance and demonstrated devices constitute a significant step toward real-world applications.

Photonic Diagnostic Technique For Thin Photoactive Films

NASA Technical Reports Server (NTRS)

Thakoor, Sarita

1996-01-01

Photonic diagnostic technique developed for use in noninvasive, rapid evaluation of thin paraelectric/ferroelectric films. Method proves useful in basic research, on-line monitoring for quality control at any stage of fabrication, and development of novel optoelectronic systems. Used to predict imprint-prone memory cells, and to study time evolution of defects in ferroelectric memories during processing. Plays vital role in enabling high-density ferroelectric memory manufacturing. One potential application lies in use of photoresponse for nondestructive readout of polarization memory states in high-density, high-speed memory devices. In another application, extension of basic concept of method makes possible to develop specially tailored ferrocapacitor to act as programmable detector, wherein remanent polarization used to modulate photoresponse. Large arrays of such detectors useful in optoelectronic processing, computing, and communication.

Emulating short-term synaptic dynamics with memristive devices

NASA Astrophysics Data System (ADS)

Berdan, Radu; Vasilaki, Eleni; Khiat, Ali; Indiveri, Giacomo; Serb, Alexandru; Prodromakis, Themistoklis

2016-01-01

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

Application of a simple cerebellar model to geologic surface mapping

USGS Publications Warehouse

Hagens, A.; Doveton, J.H.

1991-01-01

Neurophysiological research into the structure and function of the cerebellum has inspired computational models that simulate information processing associated with coordination and motor movement. The cerebellar model arithmetic computer (CMAC) has a design structure which makes it readily applicable as an automated mapping device that "senses" a surface, based on a sample of discrete observations of surface elevation. The model operates as an iterative learning process, where cell weights are continuously modified by feedback to improve surface representation. The storage requirements are substantially less than those of a conventional memory allocation, and the model is extended easily to mapping in multidimensional space, where the memory savings are even greater. ?? 1991.

Review on open source operating systems for internet of things

NASA Astrophysics Data System (ADS)

Wang, Zhengmin; Li, Wei; Dong, Huiliang

2017-08-01

Internet of Things (IoT) is an environment in which everywhere and every device became smart in a smart world. Internet of Things is growing vastly; it is an integrated system of uniquely identifiable communicating devices which exchange information in a connected network to provide extensive services. IoT devices have very limited memory, computational power, and power supply. Traditional operating systems (OS) have no way to meet the needs of IoT systems. In this paper, we thus analyze the challenges of IoT OS and survey applicable open source OSs.

Li-ion synaptic transistor for low power analog computing

DOE PAGES

Fuller, Elliot J.; Gabaly, Farid El; Leonard, Francois; ...

2016-11-22

Nonvolatile redox transistors (NVRTs) based upon Li-ion battery materials are demonstrated as memory elements for neuromorphic computer architectures with multi-level analog states, “write” linearity, low-voltage switching, and low power dissipation. Simulations of back propagation using the device properties reach ideal classification accuracy. Finally, physics-based simulations predict energy costs per “write” operation of <10 aJ when scaled to 200 nm × 200 nm.

Fundamental Fortran for Social Scientists.

ERIC Educational Resources Information Center

Veldman, Donald J.

An introduction to Fortran programming specifically for social science statistical and routine data processing is provided. The first two sections of the manual describe the components of computer hardware and software. Topics include input, output, and mass storage devices; central memory; central processing unit; internal storage of data; and…

Optical memory system technology. Citations from the International Aerospace Abstracts data base

NASA Technical Reports Server (NTRS)

Zollars, G. F.

1980-01-01

Approximately 213 citations from the international literature which concern the development of the optical data storage system technology are presented. Topics covered include holographic computer storage devices, crystal, magneto, and electro-optics, imaging techniques, in addition to optical data processing and storage.

Embedded Volttron specification - benchmarking small footprint compute device for Volttron

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanyal, Jibonananda; Fugate, David L.; Woodworth, Ken

An embedded system is a small footprint computing unit that typically serves a specific purpose closely associated with measurements and control of hardware devices. These units are designed for reasonable durability and operations in a wide range of operating conditions. Some embedded systems support real-time operations and can demonstrate high levels of reliability. Many have failsafe mechanisms built to handle graceful shutdown of the device in exception conditions. The available memory, processing power, and network connectivity of these devices are limited due to the nature of their specific-purpose design and intended application. Industry practice is to carefully design the softwaremore » for the available hardware capability to suit desired deployment needs. Volttron is an open source agent development and deployment platform designed to enable researchers to interact with devices and appliances without having to write drivers themselves. Hosting Volttron on small footprint embeddable devices enables its demonstration for embedded use. This report details the steps required and the experience in setting up and running Volttron applications on three small footprint devices: the Intel Next Unit of Computing (NUC), the Raspberry Pi 2, and the BeagleBone Black. In addition, the report also details preliminary investigation of the execution performance of Volttron on these devices.« less

High performance flight computer developed for deep space applications

NASA Technical Reports Server (NTRS)

Bunker, Robert L.

1993-01-01

The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.

Accessing global data from accelerator devices

DOEpatents

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

2016-12-06

An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global data is copied from the address in the host memory space to an address in the device memory space. The address in the host memory space is obtained from the received TOC. The received TOC is updated to indicate that global data is stored at the address in the device memory space. A kernel that accesses the global data from the address in the device memory space is executed. The address in the device memory space is obtained based on contents of the updated TOC. When the executing is completed, the global data from the address in the device memory space is copied to the address in the host memory space.

Application of phase-change materials in memory taxonomy.

PubMed

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects.

Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

NASA Astrophysics Data System (ADS)

Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

Quantum memristors

DOE PAGES

Pfeiffer, P.; Egusquiza, I. L.; Di Ventra, M.; ...

2016-07-06

Technology based on memristors, resistors with memory whose resistance depends on the history of the crossing charges, has lately enhanced the classical paradigm of computation with neuromorphic architectures. However, in contrast to the known quantized models of passive circuit elements, such as inductors, capacitors or resistors, the design and realization of a quantum memristor is still missing. Here, we introduce the concept of a quantum memristor as a quantum dissipative device, whose decoherence mechanism is controlled by a continuous-measurement feedback scheme, which accounts for the memory. Indeed, we provide numerical simulations showing that memory effects actually persist in the quantummore » regime. Our quantization method, specifically designed for superconducting circuits, may be extended to other quantum platforms, allowing for memristor-type constructions in different quantum technologies. As a result, the proposed quantum memristor is then a building block for neuromorphic quantum computation and quantum simulations of non-Markovian systems.« less

[Method of file sorting for mini- and microcomputers].

PubMed

Chau, N; Legras, B; Benamghar, L; Martin, J

1983-05-01

The authors describe a new sorting method of files which belongs to the class of direct-addressing sorting methods. It makes use of a variant of the classical technique of 'virtual memory'. It is particularly well suited to mini- and micro-computers which have a small core memory (32 K words, for example) and are fitted with a direct-access peripheral device, such as a disc unit. When the file to be sorted is medium-sized (some thousand records), the running of the program essentially occurs inside the core memory and consequently, the method becomes very fast. This is very important because most medical files handled in our laboratory are in this category. However, the method is also suitable for big computers and large files; its implementation is easy. It does not require any magnetic tape unit, and it seems to us to be one of the fastest methods available.

An UV photochromic memory effect in proton-based WO3 electrochromic devices

NASA Astrophysics Data System (ADS)

Zhang, Yong; Lee, S.-H.; Mascarenhas, A.; Deb, S. K.

2008-11-01

We report an UV photochromic memory effect on a standard proton-based WO3 electrochromic device. It exhibits two memory states, associated with the colored and bleached states of the device, respectively. Such an effect can be used to enhance device performance (increasing the dynamic range), re-energize commercial electrochromic devices, and develop memory devices.

Peripheral controllers and devices--Part 1.

PubMed

Pinkert, J R; Wear, L L

1992-10-01

In this article, we looked at several peripherals, described their characteristics, and described how they are connected to computers. We included some discussions of problems caused by electrical and mechanical differences between computers and peripheral devices. During the past few years, many companies have addressed such problems. Numerous standards have been defined as a result of this work. These standards specify everything from what type of connectors will be used to the timing of electrical signals. They make it easier for peripheral manufacturers to design their devices for a wide range of computers. Peripherals and their controllers are important components of any computer system. Sometimes, however, other parts of the system, such as the control unit and main memory, receive more attention. Many engineers want to design new processors, but shy away from the design of peripherals and controllers; they consider such designs less glamorous. In reality, designs for some peripherals and their controllers can be more challenging than the design of the CPU itself. A computer without peripherals is of little use, other than as a paper weight. Until we attach peripherals to the computer, none of its power is accessible to the user. Peripherals turn computers into useful tools.

Vortical structures for nanomagnetic memory induced by dipole-dipole interaction in monolayer disks

NASA Astrophysics Data System (ADS)

Liu, Zhaosen; Ciftja, Orion; Zhang, Xichao; Zhou, Yan; Ian, Hou

2018-05-01

It is well known that magnetic domains in nanodisks can be used as storage units for computer memory. Using two quantum simulation approaches, we show here that spin vortices on magnetic monolayer nanodisks, which are chirality-free, can be induced by dipole-dipole interaction (DDI) on the disk-plane. When DDI is sufficiently strong, vortical and anti-vortical multi-domain textures can be generated simultaneously. Especially, a spin vortex can be easily created and deleted through either external magnetic or electrical signals, making them ideal to be used in nanomagnetic memory and logical devices. We demonstrate these properties in our simulations.

SkinScan©: A PORTABLE LIBRARY FOR MELANOMA DETECTION ON HANDHELD DEVICES

PubMed Central

Wadhawan, Tarun; Situ, Ning; Lancaster, Keith; Yuan, Xiaojing; Zouridakis, George

2011-01-01

We have developed a portable library for automated detection of melanoma termed SkinScan© that can be used on smartphones and other handheld devices. Compared to desktop computers, embedded processors have limited processing speed, memory, and power, but they have the advantage of portability and low cost. In this study we explored the feasibility of running a sophisticated application for automated skin cancer detection on an Apple iPhone 4. Our results demonstrate that the proposed library with the advanced image processing and analysis algorithms has excellent performance on handheld and desktop computers. Therefore, deployment of smartphones as screening devices for skin cancer and other skin diseases can have a significant impact on health care delivery in underserved and remote areas. PMID:21892382

Network Information System

DOE Office of Scientific and Technical Information (OSTI.GOV)

1996-05-01

The Network Information System (NWIS) was initially implemented in May 1996 as a system in which computing devices could be recorded so that unique names could be generated for each device. Since then the system has grown to be an enterprise wide information system which is integrated with other systems to provide the seamless flow of data through the enterprise. The system Iracks data for two main entities: people and computing devices. The following are the type of functions performed by NWIS for these two entities: People Provides source information to the enterprise person data repository for select contractors andmore » visitors Generates and tracks unique usernames and Unix user IDs for every individual granted cyber access Tracks accounts for centrally managed computing resources, and monitors and controls the reauthorization of the accounts in accordance with the DOE mandated interval Computing Devices Generates unique names for all computing devices registered in the system Tracks the following information for each computing device: manufacturer, make, model, Sandia property number, vendor serial number, operating system and operating system version, owner, device location, amount of memory, amount of disk space, and level of support provided for the machine Tracks the hardware address for network cards Tracks the P address registered to computing devices along with the canonical and alias names for each address Updates the Dynamic Domain Name Service (DDNS) for canonical and alias names Creates the configuration files for DHCP to control the DHCP ranges and allow access to only properly registered computers Tracks and monitors classified security plans for stand-alone computers Tracks the configuration requirements used to setup the machine Tracks the roles people have on machines (system administrator, administrative access, user, etc...) Allows systems administrators to track changes made on the machine (both hardware and software) Generates an adjustment history of changes on selected fields« less

Time-resolved EPR spectroscopy in a Unix environment.

PubMed

Lacoff, N M; Franke, J E; Warden, J T

1990-02-01

A computer-aided time-resolved electron paramagnetic resonance (EPR) spectrometer implemented under version 2.9 BSD Unix was developed by interfacing a Varian E-9 EPR spectrometer and a Biomation 805 waveform recorder to a PDP-11/23A minicomputer having MINC A/D and D/A capabilities. Special problems with real-time data acquisition in a multiuser, multitasking Unix environment, addressing of computer main memory for the control of hardware devices, and limitation of computer main memory were resolved, and their solutions are presented. The time-resolved EPR system and the data acquisition and analysis programs, written entirely in C, are described. Furthermore, the benefits of utilizing the Unix operating system and the C language are discussed, and system performance is illustrated with time-resolved EPR spectra of the reaction center cation in photosystem 1 of green plant photosynthesis.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

Nanoelectronics: Opportunities for future space applications

NASA Technical Reports Server (NTRS)

Frazier, Gary

1995-01-01

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Xyce Parallel Electronic Simulator Users' Guide Version 6.8

DOE Office of Scientific and Technical Information (OSTI.GOV)

Keiter, Eric R.; Aadithya, Karthik Venkatraman; Mei, Ting

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows onemore » to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase$-$ a message passing parallel implementation $-$ which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.« less

Kinetic Inductance Memory Cell and Architecture for Superconducting Computers

NASA Astrophysics Data System (ADS)

Chen, George J.

Josephson memory devices typically use a superconducting loop containing one or more Josephson junctions to store information. The magnetic inductance of the loop in conjunction with the Josephson junctions provides multiple states to store data. This thesis shows that replacing the magnetic inductor in a memory cell with a kinetic inductor can lead to a smaller cell size. However, magnetic control of the cells is lost. Thus, a current-injection based architecture for a memory array has been designed to work around this problem. The isolation between memory cells that magnetic control provides is provided through resistors in this new architecture. However, these resistors allow leakage current to flow which ultimately limits the size of the array due to power considerations. A kinetic inductance memory array will be limited to 4K bits with a read access time of 320 ps for a 1 um linewidth technology. If a power decoder could be developed, the memory architecture could serve as the blueprint for a fast (<1 ns), large scale (>1 Mbit) superconducting memory array.

Aerospace Ground Equipment for model 4080 sequence programmer. A standard computer terminal is adapted to provide convenient operator to device interface

NASA Technical Reports Server (NTRS)

Nissley, L. E.

1979-01-01

The Aerospace Ground Equipment (AGE) provides an interface between a human operator and a complete spaceborne sequence timing device with a memory storage program. The AGE provides a means for composing, editing, syntax checking, and storing timing device programs. The AGE is implemented with a standard Hewlett-Packard 2649A terminal system and a minimum of special hardware. The terminal's dual tape interface is used to store timing device programs and to read in special AGE operating system software. To compose a new program for the timing device the keyboard is used to fill in a form displayed on the screen.

Application of phase-change materials in memory taxonomy

PubMed Central

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Abstract Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects. PMID:28740557

Description of a Portable Wireless Device for High-Frequency Body Temperature Acquisition and Analysis

PubMed Central

Cuesta-Frau, David; Varela, Manuel; Aboy, Mateo; Miró-Martínez, Pau

2009-01-01

We describe a device for dual channel body temperature monitoring. The device can operate as a real time monitor or as a data logger, and has Bluetooth capabilities to enable for wireless data download to the computer used for data analysis. The proposed device is capable of sampling temperature at a rate of 1 sample per minute with a resolution of 0.01 °C . The internal memory allows for stand-alone data logging of up to 10 days. The device has a battery life of 50 hours in continuous real-time mode. In addition to describing the proposed device in detail, we report the results of a statistical analysis conducted to assess its accuracy and reproducibility. PMID:22408473

Description of a portable wireless device for high-frequency body temperature acquisition and analysis.

PubMed

Cuesta-Frau, David; Varela, Manuel; Aboy, Mateo; Miró-Martínez, Pau

2009-01-01

We describe a device for dual channel body temperature monitoring. The device can operate as a real time monitor or as a data logger, and has Bluetooth capabilities to enable for wireless data download to the computer used for data analysis. The proposed device is capable of sampling temperature at a rate of 1 sample per minute with a resolution of 0.01 °C . The internal memory allows for stand-alone data logging of up to 10 days. The device has a battery life of 50 hours in continuous real-time mode. In addition to describing the proposed device in detail, we report the results of a statistical analysis conducted to assess its accuracy and reproducibility.

Accessing global data from accelerator devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.

2016-12-06

An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global data is copied from the address in the host memory space to an address in the device memory space. The address in the host memory space is obtained from the received TOC. The received TOC is updated to indicate that global data is stored at the address in the device memory space. A kernel that accesses the global data from the address in the devicemore » memory space is executed. The address in the device memory space is obtained based on contents of the updated TOC. When the executing is completed, the global data from the address in the device memory space is copied to the address in the host memory space.« less

Self-assembled nanostructured resistive switching memory devices fabricated by templated bottom-up growth

PubMed Central

Song, Ji-Min; Lee, Jang-Sik

2016-01-01

Metal-oxide-based resistive switching memory device has been studied intensively due to its potential to satisfy the requirements of next-generation memory devices. Active research has been done on the materials and device structures of resistive switching memory devices that meet the requirements of high density, fast switching speed, and reliable data storage. In this study, resistive switching memory devices were fabricated with nano-template-assisted bottom up growth. The electrochemical deposition was adopted to achieve the bottom-up growth of nickel nanodot electrodes. Nickel oxide layer was formed by oxygen plasma treatment of nickel nanodots at low temperature. The structures of fabricated nanoscale memory devices were analyzed with scanning electron microscope and atomic force microscope (AFM). The electrical characteristics of the devices were directly measured using conductive AFM. This work demonstrates the fabrication of resistive switching memory devices using self-assembled nanoscale masks and nanomateirals growth from bottom-up electrochemical deposition. PMID:26739122

Estimation of aneurysm wall stresses created by treatment with a shape memory polymer foam device

PubMed Central

Hwang, Wonjun; Volk, Brent L.; Akberali, Farida; Singhal, Pooja; Criscione, John C.

2012-01-01

In this study, compliant latex thin-walled aneurysm models are fabricated to investigate the effects of expansion of shape memory polymer foam. A simplified cylindrical model is selected for the in-vitro aneurysm, which is a simplification of a real, saccular aneurysm. The studies are performed by crimping shape memory polymer foams, originally 6 and 8 mm in diameter, and monitoring the resulting deformation when deployed into 4-mm-diameter thin-walled latex tubes. The deformations of the latex tubes are used as inputs to physical, analytical, and computational models to estimate the circumferential stresses. Using the results of the stress analysis in the latex aneurysm model, a computational model of the human aneurysm is developed by changing the geometry and material properties. The model is then used to predict the stresses that would develop in a human aneurysm. The experimental, simulation, and analytical results suggest that shape memory polymer foams have potential of being a safe treatment for intracranial saccular aneurysms. In particular, this work suggests oversized shape memory foams may be used to better fill the entire aneurysm cavity while generating stresses below the aneurysm wall breaking stresses. PMID:21901546

Methods for operating parallel computing systems employing sequenced communications

DOEpatents

Benner, R.E.; Gustafson, J.L.; Montry, G.R.

1999-08-10

A parallel computing system and method are disclosed having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system. 15 figs.

Methods for operating parallel computing systems employing sequenced communications

DOEpatents

Benner, Robert E.; Gustafson, John L.; Montry, Gary R.

1999-01-01

A parallel computing system and method having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system.

Memory hierarchy using row-based compression

DOEpatents

Loh, Gabriel H.; O'Connor, James M.

2016-10-25

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-07

... Access Memory and Nand Flash Memory Devices and Products Containing Same; Notice of Institution of... importation, and the sale within the United States after importation of certain dynamic random access memory and NAND flash memory devices and products containing same by reason of infringement of certain claims...

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

NASA Astrophysics Data System (ADS)

Chang, S. S. L.

State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

Image change detection systems, methods, and articles of manufacture

DOEpatents

Jones, James L.; Lassahn, Gordon D.; Lancaster, Gregory D.

2010-01-05

Aspects of the invention relate to image change detection systems, methods, and articles of manufacture. According to one aspect, a method of identifying differences between a plurality of images is described. The method includes loading a source image and a target image into memory of a computer, constructing source and target edge images from the source and target images to enable processing of multiband images, displaying the source and target images on a display device of the computer, aligning the source and target edge images, switching displaying of the source image and the target image on the display device, to enable identification of differences between the source image and the target image.

SSD Market Overview

NASA Astrophysics Data System (ADS)

Wong, G.

The unparalleled cost and form factor advantages of NAND flash memory has driven 35 mm photographic film, floppy disks and one-inch hard drives to extinction. Due to its compelling price/performance characteristics, NAND Flash memory is now expanding its reach into the once-exclusive domain of hard disk drives and DRAM in the form of Solid State Drives (SSDs). Driven by the proliferation of thin and light mobile devices and the need for near-instantaneous accessing and sharing of content through the cloud, SSDs are expected to become a permanent fixture in the computing infrastructure.

Optical modular arithmetic

NASA Astrophysics Data System (ADS)

Pavlichin, Dmitri S.; Mabuchi, Hideo

2014-06-01

Nanoscale integrated photonic devices and circuits offer a path to ultra-low power computation at the few-photon level. Here we propose an optical circuit that performs a ubiquitous operation: the controlled, random-access readout of a collection of stored memory phases or, equivalently, the computation of the inner product of a vector of phases with a binary selector" vector, where the arithmetic is done modulo 2pi and the result is encoded in the phase of a coherent field. This circuit, a collection of cascaded interferometers driven by a coherent input field, demonstrates the use of coherence as a computational resource, and of the use of recently-developed mathematical tools for modeling optical circuits with many coupled parts. The construction extends in a straightforward way to the computation of matrix-vector and matrix-matrix products, and, with the inclusion of an optical feedback loop, to the computation of a weighted" readout of stored memory phases. We note some applications of these circuits for error correction and for computing tasks requiring fast vector inner products, e.g. statistical classification and some machine learning algorithms.

Scalable quantum memory in the ultrastrong coupling regime.

PubMed

Kyaw, T H; Felicetti, S; Romero, G; Solano, E; Kwek, L-C

2015-03-02

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances.

Scalable quantum memory in the ultrastrong coupling regime

PubMed Central

Kyaw, T. H.; Felicetti, S.; Romero, G.; Solano, E.; Kwek, L.-C.

2015-01-01

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances. PMID:25727251

A simple GPU-accelerated two-dimensional MUSCL-Hancock solver for ideal magnetohydrodynamics

NASA Astrophysics Data System (ADS)

Bard, Christopher M.; Dorelli, John C.

2014-02-01

We describe our experience using NVIDIA's CUDA (Compute Unified Device Architecture) C programming environment to implement a two-dimensional second-order MUSCL-Hancock ideal magnetohydrodynamics (MHD) solver on a GTX 480 Graphics Processing Unit (GPU). Taking a simple approach in which the MHD variables are stored exclusively in the global memory of the GTX 480 and accessed in a cache-friendly manner (without further optimizing memory access by, for example, staging data in the GPU's faster shared memory), we achieved a maximum speed-up of ≈126 for a 10242 grid relative to the sequential C code running on a single Intel Nehalem (2.8 GHz) core. This speedup is consistent with simple estimates based on the known floating point performance, memory throughput and parallel processing capacity of the GTX 480.

Applying a cloud computing approach to storage architectures for spacecraft

NASA Astrophysics Data System (ADS)

Baldor, Sue A.; Quiroz, Carlos; Wood, Paul

As sensor technologies, processor speeds, and memory densities increase, spacecraft command, control, processing, and data storage systems have grown in complexity to take advantage of these improvements and expand the possible missions of spacecraft. Spacecraft systems engineers are increasingly looking for novel ways to address this growth in complexity and mitigate associated risks. Looking to conventional computing, many solutions have been executed to solve both the problem of complexity and heterogeneity in systems. In particular, the cloud-based paradigm provides a solution for distributing applications and storage capabilities across multiple platforms. In this paper, we propose utilizing a cloud-like architecture to provide a scalable mechanism for providing mass storage in spacecraft networks that can be reused on multiple spacecraft systems. By presenting a consistent interface to applications and devices that request data to be stored, complex systems designed by multiple organizations may be more readily integrated. Behind the abstraction, the cloud storage capability would manage wear-leveling, power consumption, and other attributes related to the physical memory devices, critical components in any mass storage solution for spacecraft. Our approach employs SpaceWire networks and SpaceWire-capable devices, although the concept could easily be extended to non-heterogeneous networks consisting of multiple spacecraft and potentially the ground segment.

Reconfigurable logic in nanosecond Cu/GeTe/TiN filamentary memristors for energy-efficient in-memory computing.

PubMed

Jin, Miaomiao; Cheng, Long; Li, Yi; Hu, Siyu; Lu, Ke; Chen, Jia; Duan, Nian; Wang, Zhuorui; Zhou, Yaxiong; Chang, Ting-Chang; Miao, Xiangshui

2018-06-27

Owing to the capability of integrating the information storage and computing in the same physical location, in-memory computing with memristors has become a research hotspot as a promising route for non von Neumann architecture. However, it is still a challenge to develop high performance devices as well as optimized logic methodologies to realize energy-efficient computing. Herein, filamentary Cu/GeTe/TiN memristor is reported to show satisfactory properties with nanosecond switching speed (< 60 ns), low voltage operation (< 2 V), high endurance (>104 cycles) and good retention (>104 s @85℃). It is revealed that the charge carrier conduction mechanisms in high resistance and low resistance states are Schottky emission and hopping transport between the adjacent Cu clusters, respectively, based on the analysis of current-voltage behaviors and resistance-temperature characteristics. An intuitive picture is given to describe the dynamic processes of resistive switching. Moreover, based on the basic material implication (IMP) logic circuit, we proposed a reconfigurable logic method and experimentally implemented IMP, NOT, OR, and COPY logic functions. Design of a one-bit full adder with reduction in computational sequences and its validation in simulation further demonstrate the potential practical application. The results provide important progress towards understanding of resistive switching mechanism and realization of energy-efficient in-memory computing architecture. © 2018 IOP Publishing Ltd.

Ferroelectric symmetry-protected multibit memory cell

NASA Astrophysics Data System (ADS)

Baudry, Laurent; Lukyanchuk, Igor; Vinokur, Valerii M.

2017-02-01

The tunability of electrical polarization in ferroelectrics is instrumental to their applications in information-storage devices. The existing ferroelectric memory cells are based on the two-level storage capacity with the standard binary logics. However, the latter have reached its fundamental limitations. Here we propose ferroelectric multibit cells (FMBC) utilizing the ability of multiaxial ferroelectric materials to pin the polarization at a sequence of the multistable states. Employing the catastrophe theory principles we show that these states are symmetry-protected against the information loss and thus realize novel topologically-controlled access memory (TAM). Our findings enable developing a platform for the emergent many-valued non-Boolean information technology and target challenges posed by needs of quantum and neuromorphic computing.

Hardware for Accelerating N-Modular Redundant Systems for High-Reliability Computing

NASA Technical Reports Server (NTRS)

Dobbs, Carl, Sr.

2012-01-01

A hardware unit has been designed that reduces the cost, in terms of performance and power consumption, for implementing N-modular redundancy (NMR) in a multiprocessor device. The innovation monitors transactions to memory, and calculates a form of sumcheck on-the-fly, thereby relieving the processors of calculating the sumcheck in software

An Introduction to the Memristor

ERIC Educational Resources Information Center

Atkin, Keith

2013-01-01

In recent years there has been a revolution in electronics, with a variety of physical phenomena being utilized in the construction of new types of memory circuits for computer application. A device which has had an increasing role is the memristor, whose description and properties have so far had little mention in physics education. This paper…

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

Mobile high-performance computing (HPC) for synthetic aperture radar signal processing

NASA Astrophysics Data System (ADS)

Misko, Joshua; Kim, Youngsoo; Qi, Chenchen; Sirkeci, Birsen

2018-04-01

The importance of mobile high-performance computing has emerged in numerous battlespace applications at the tactical edge in hostile environments. Energy efficient computing power is a key enabler for diverse areas ranging from real-time big data analytics and atmospheric science to network science. However, the design of tactical mobile data centers is dominated by power, thermal, and physical constraints. Presently, it is very unlikely to achieve required computing processing power by aggregating emerging heterogeneous many-core processing platforms consisting of CPU, Field Programmable Gate Arrays and Graphic Processor cores constrained by power and performance. To address these challenges, we performed a Synthetic Aperture Radar case study for Automatic Target Recognition (ATR) using Deep Neural Networks (DNNs). However, these DNN models are typically trained using GPUs with gigabytes of external memories and massively used 32-bit floating point operations. As a result, DNNs do not run efficiently on hardware appropriate for low power or mobile applications. To address this limitation, we proposed for compressing DNN models for ATR suited to deployment on resource constrained hardware. This proposed compression framework utilizes promising DNN compression techniques including pruning and weight quantization while also focusing on processor features common to modern low-power devices. Following this methodology as a guideline produced a DNN for ATR tuned to maximize classification throughput, minimize power consumption, and minimize memory footprint on a low-power device.

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure.

PubMed

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-14

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 microm(2) to 200 x 200 nm(2). From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I(ON)/I(OFF) approximately 10(4)), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10,000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

Computer hardware for radiologists: Part 2

PubMed Central

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future. PMID:21423895

Energy-band engineering for tunable memory characteristics through controlled doping of reduced graphene oxide.

PubMed

Han, Su-Ting; Zhou, Ye; Yang, Qing Dan; Zhou, Li; Huang, Long-Biao; Yan, Yan; Lee, Chun-Sing; Roy, Vellaisamy A L

2014-02-25

Tunable memory characteristics are used in multioperational mode circuits where memory cells with various functionalities are needed in one combined device. It is always a challenge to obtain control over threshold voltage for multimode operation. On this regard, we use a strategy of shifting the work function of reduced graphene oxide (rGO) in a controlled manner through doping gold chloride (AuCl3) and obtained a gradient increase of rGO work function. By inserting doped rGO as floating gate, a controlled threshold voltage (Vth) shift has been achieved in both p- and n-type low voltage flexible memory devices with large memory window (up to 4 times for p-type and 8 times for n-type memory devices) in comparison with pristine rGO floating gate memory devices. By proper energy band engineering, we demonstrated a flexible floating gate memory device with larger memory window and controlled threshold voltage shifts.

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacobs-Gedrim, Robin B.; Agarwal, Sapan; Knisely, Kathrine E.

Resistive memory (ReRAM) shows promise for use as an analog synapse element in energy-efficient neural network algorithm accelerators. A particularly important application is the training of neural networks, as this is the most computationally-intensive procedure in using a neural algorithm. However, training a network with analog ReRAM synapses can significantly reduce the accuracy at the algorithm level. In order to assess this degradation, analog properties of ReRAM devices were measured and hand-written digit recognition accuracy was modeled for the training using backpropagation. Bipolar filamentary devices utilizing three material systems were measured and compared: one oxygen vacancy system, Ta-TaO x, andmore » two conducting metallization systems, Cu-SiO 2, and Ag/chalcogenide. Analog properties and conductance ranges of the devices are optimized by measuring the response to varying voltage pulse characteristics. Key analog device properties which degrade the accuracy are update linearity and write noise. Write noise may improve as a function of device manufacturing maturity, but write nonlinearity appears relatively consistent among the different device material systems and is found to be the most significant factor affecting accuracy. As a result, this suggests that new materials and/or fundamentally different resistive switching mechanisms may be required to improve device linearity and achieve higher algorithm training accuracy.« less

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator

DOE PAGES

Jacobs-Gedrim, Robin B.; Agarwal, Sapan; Knisely, Kathrine E.; ...

2017-12-01

Resistive memory (ReRAM) shows promise for use as an analog synapse element in energy-efficient neural network algorithm accelerators. A particularly important application is the training of neural networks, as this is the most computationally-intensive procedure in using a neural algorithm. However, training a network with analog ReRAM synapses can significantly reduce the accuracy at the algorithm level. In order to assess this degradation, analog properties of ReRAM devices were measured and hand-written digit recognition accuracy was modeled for the training using backpropagation. Bipolar filamentary devices utilizing three material systems were measured and compared: one oxygen vacancy system, Ta-TaO x, andmore » two conducting metallization systems, Cu-SiO 2, and Ag/chalcogenide. Analog properties and conductance ranges of the devices are optimized by measuring the response to varying voltage pulse characteristics. Key analog device properties which degrade the accuracy are update linearity and write noise. Write noise may improve as a function of device manufacturing maturity, but write nonlinearity appears relatively consistent among the different device material systems and is found to be the most significant factor affecting accuracy. As a result, this suggests that new materials and/or fundamentally different resistive switching mechanisms may be required to improve device linearity and achieve higher algorithm training accuracy.« less

Metal-organic molecular device for non-volatile memory storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radha, B., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in

Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organicmore » complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.« less

PCM-Based Durable Write Cache for Fast Disk I/O

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Zhuo; Wang, Bin; Carpenter, Patrick

2012-01-01

Flash based solid-state devices (FSSDs) have been adopted within the memory hierarchy to improve the performance of hard disk drive (HDD) based storage system. However, with the fast development of storage-class memories, new storage technologies with better performance and higher write endurance than FSSDs are emerging, e.g., phase-change memory (PCM). Understanding how to leverage these state-of-the-art storage technologies for modern computing systems is important to solve challenging data intensive computing problems. In this paper, we propose to leverage PCM for a hybrid PCM-HDD storage architecture. We identify the limitations of traditional LRU caching algorithms for PCM-based caches, and develop amore » novel hash-based write caching scheme called HALO to improve random write performance of hard disks. To address the limited durability of PCM devices and solve the degraded spatial locality in traditional wear-leveling techniques, we further propose novel PCM management algorithms that provide effective wear-leveling while maximizing access parallelism. We have evaluated this PCM-based hybrid storage architecture using applications with a diverse set of I/O access patterns. Our experimental results demonstrate that the HALO caching scheme leads to an average reduction of 36.8% in execution time compared to the LRU caching scheme, and that the SFC wear leveling extends the lifetime of PCM by a factor of 21.6.« less

Status and Prospects of ZnO-Based Resistive Switching Memory Devices

NASA Astrophysics Data System (ADS)

Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

2016-08-01

In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

Are biochips the new wave

NASA Astrophysics Data System (ADS)

Bussert, J.

1982-06-01

The possibility of microchip synthesis from molecular configurations is considered. A bistable memory element concept is described which can be independently written on and read, and which consists of a chain of transition metal atoms, a bulging ligand connecting the transition metal atoms, and two types of ligand attached to the transition metal atoms. The molecular emulation of switches, memory and interfaces is presently being investigated independently, although simultaneous synthesis of entire architectures is the ultimate goal of research. Molecular circuitry, which could incorporate 10,000 more gates into an IC chip than chemical techniques, would be of greatest immediate importance in avionics and other portable military electronics devices for which minimum size and weight are valuable. Attention is given to a computer-controlled method for the synthesis of molecular computers.

Bubble memory module for spacecraft application

NASA Technical Reports Server (NTRS)

Hayes, P. J.; Looney, K. T.; Nichols, C. D.

1985-01-01

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Reconfigurable pipelined processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saccardi, R.J.

1989-09-19

This patent describes a reconfigurable pipelined processor for processing data. It comprises: a plurality of memory devices for storing bits of data; a plurality of arithmetic units for performing arithmetic functions with the data; cross bar means for connecting the memory devices with the arithmetic units for transferring data therebetween; at least one counter connected with the cross bar means for providing a source of addresses to the memory devices; at least one variable tick delay device connected with each of the memory devices and arithmetic units; and means for providing control bits to the variable tick delay device formore » variably controlling the input and output operations thereof to selectively delay the memory devices and arithmetic units to align the data for processing in a selected sequence.« less

Operating systems. [of computers

NASA Technical Reports Server (NTRS)

Denning, P. J.; Brown, R. L.

1984-01-01

A counter operating system creates a hierarchy of levels of abstraction, so that at a given level all details concerning lower levels can be ignored. This hierarchical structure separates functions according to their complexity, characteristic time scale, and level of abstraction. The lowest levels include the system's hardware; concepts associated explicitly with the coordination of multiple tasks appear at intermediate levels, which conduct 'primitive processes'. Software semaphore is the mechanism controlling primitive processes that must be synchronized. At higher levels lie, in rising order, the access to the secondary storage devices of a particular machine, a 'virtual memory' scheme for managing the main and secondary memories, communication between processes by way of a mechanism called a 'pipe', access to external input and output devices, and a hierarchy of directories cataloguing the hardware and software objects to which access must be controlled.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2011-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2012-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

A Simple GPU-Accelerated Two-Dimensional MUSCL-Hancock Solver for Ideal Magnetohydrodynamics

NASA Technical Reports Server (NTRS)

Bard, Christopher; Dorelli, John C.

2013-01-01

We describe our experience using NVIDIA's CUDA (Compute Unified Device Architecture) C programming environment to implement a two-dimensional second-order MUSCL-Hancock ideal magnetohydrodynamics (MHD) solver on a GTX 480 Graphics Processing Unit (GPU). Taking a simple approach in which the MHD variables are stored exclusively in the global memory of the GTX 480 and accessed in a cache-friendly manner (without further optimizing memory access by, for example, staging data in the GPU's faster shared memory), we achieved a maximum speed-up of approx. = 126 for a sq 1024 grid relative to the sequential C code running on a single Intel Nehalem (2.8 GHz) core. This speedup is consistent with simple estimates based on the known floating point performance, memory throughput and parallel processing capacity of the GTX 480.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device.

PubMed

Park, Sangsu; Noh, Jinwoo; Choo, Myung-Lae; Sheri, Ahmad Muqeem; Chang, Man; Kim, Young-Bae; Kim, Chang Jung; Jeon, Moongu; Lee, Byung-Geun; Lee, Byoung Hun; Hwang, Hyunsang

2013-09-27

Efforts to develop scalable learning algorithms for implementation of networks of spiking neurons in silicon have been hindered by the considerable footprints of learning circuits, which grow as the number of synapses increases. Recent developments in nanotechnologies provide an extremely compact device with low-power consumption.In particular, nanoscale resistive switching devices (resistive random-access memory (RRAM)) are regarded as a promising solution for implementation of biological synapses due to their nanoscale dimensions, capacity to store multiple bits and the low energy required to operate distinct states. In this paper, we report the fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In addition, we first experimentally demonstrate the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point array of synapses and complementary metal-oxide-semiconductor neuron circuits. These developments open up possibilities for the development of ubiquitous ultra-dense, ultra-low-power cognitive computers.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Digital Holographic Memories

NASA Astrophysics Data System (ADS)

Hesselink, Lambertus; Orlov, Sergei S.

Optical data storage is a phenomenal success story. Since its introduction in the early 1980s, optical data storage devices have evolved from being focused primarily on music distribution, to becoming the prevailing data distribution and recording medium. Each year, billions of optical recordable and prerecorded disks are sold worldwide. Almost every computer today is shipped with a CD or DVD drive installed.

An upconverted photonic nonvolatile memory.

PubMed

Zhou, Ye; Han, Su-Ting; Chen, Xian; Wang, Feng; Tang, Yong-Bing; Roy, V A L

2014-08-21

Conventional flash memory devices are voltage driven and found to be unsafe for confidential data storage. To ensure the security of the stored data, there is a strong demand for developing novel nonvolatile memory technology for data encryption. Here we show a photonic flash memory device, based on upconversion nanocrystals, which is light driven with a particular narrow width of wavelength in addition to voltage bias. With the help of near-infrared light, we successfully manipulate the multilevel data storage of the flash memory device. These upconverted photonic flash memory devices exhibit high ON/OFF ratio, long retention time and excellent rewritable characteristics.

Microgravity

NASA Image and Video Library

1999-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

Microgravity

NASA Image and Video Library

2000-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

A portable ECG monitoring device with Bluetooth and Holter capabilities for telemedicine applications.

PubMed

Lucani, Daniel; Cataldo, Giancarlos; Cruz, Julio; Villegas, Guillermo; Wong, Sara

2006-01-01

A prototype of a portable ECG-monitoring device has been developed for clinical and non-clinical environments as part of a telemedicine system to provide remote and continuous surveillance of patients. The device can acquire, store and/or transmit ECG signals to computer-based platforms or specially configured access points (AP) with Intranet/Internet capabilities in order to reach remote monitoring stations. Acquired data can be stored in a flash memory card in FAT16 format for later recovery, or transmitted via Bluetooth or USB to a local station or AP. This data acquisition module (DAM) operates in two modes: Holter and on-line transmission.

76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-11-29

... INTERNATIONAL TRADE COMMISSION [DN 2859] Certain Dynamic Random Access Memory Devices, and.... International Trade Commission has received a complaint entitled In Re Certain Dynamic Random Access Memory... certain dynamic random access memory devices, and products containing same. The complaint names Elpida...

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Computer driven optical keratometer and method of evaluating the shape of the cornea

NASA Technical Reports Server (NTRS)

Baroth, Edmund C. (Inventor); Mouneimme, Samih A. (Inventor)

1994-01-01

An apparatus and method for measuring the shape of the cornea utilize only one reticle to generate a pattern of rings projected onto the surface of a subject's eye. The reflected pattern is focused onto an imaging device such as a video camera and a computer compares the reflected pattern with a reference pattern stored in the computer's memory. The differences between the reflected and stored patterns are used to calculate the deformation of the cornea which may be useful for pre-and post-operative evaluation of the eye by surgeons.

Method for simultaneous overlapped communications between neighboring processors in a multiple

DOEpatents

Benner, Robert E.; Gustafson, John L.; Montry, Gary R.

1991-01-01

A parallel computing system and method having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system.

Harmonic analysis of spacecraft power systems using a personal computer

NASA Technical Reports Server (NTRS)

Williamson, Frank; Sheble, Gerald B.

1989-01-01

The effects that nonlinear devices such as ac/dc converters, HVDC transmission links, and motor drives have on spacecraft power systems are discussed. The nonsinusoidal currents, along with the corresponding voltages, are calculated by a harmonic power flow which decouples and solves for each harmonic component individually using an iterative Newton-Raphson algorithm. The sparsity of the harmonic equations and the overall Jacobian matrix is used to an advantage in terms of saving computer memory space and in terms of reducing computation time. The algorithm could also be modified to analyze each harmonic separately instead of all at the same time.

Ferroelectric symmetry-protected multibit memory cell

DOE PAGES

Baudry, Laurent; Lukyanchuk, Igor; Vinokur, Valerii M.

2017-02-08

Here, the tunability of electrical polarization in ferroelectrics is instrumental to their applications in information-storage devices. The existing ferroelectric memory cells are based on the two-level storage capacity with the standard binary logics. However, the latter have reached its fundamental limitations. Here we propose ferroelectric multibit cells (FMBC) utilizing the ability of multiaxial ferroelectric materials to pin the polarization at a sequence of the multistable states. Employing the catastrophe theory principles we show that these states are symmetry-protected against the information loss and thus realize novel topologically-controlled access memory (TAM). Our findings enable developing a platform for the emergent many-valuedmore » non-Boolean information technology and target challenges posed by needs of quantum and neuromorphic computing.« less

Recent Advances on Neuromorphic Systems Using Phase-Change Materials

NASA Astrophysics Data System (ADS)

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-05-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Recent Advances on Neuromorphic Systems Using Phase-Change Materials.

PubMed

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-12-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Hao; Materials Science Program, University of Wisconsin, Madison, Wisconsin 53706; Stewart, Derek A., E-mail: derek.stewart@hgst.com

Metal oxide resistive memory devices based on Ta{sub 2}O{sub 5} have demonstrated high switching speed, long endurance, and low set voltage. However, the physical origin of this improved performance is still unclear. Ta{sub 2}O{sub 5} is an important archetype of a class of materials that possess an adaptive crystal structure that can respond easily to the presence of defects. Using first principles nudged elastic band calculations, we show that this adaptive crystal structure leads to low energy barriers for in-plane diffusion of oxygen vacancies in λ phase Ta{sub 2}O{sub 5}. Identified diffusion paths are associated with collective motion of neighboringmore » atoms. The overall vacancy diffusion is anisotropic with higher diffusion barriers found for oxygen vacancy movement between Ta-O planes. Coupled with the fact that oxygen vacancy formation energy in Ta{sub 2}O{sub 5} is relatively small, our calculated low diffusion barriers can help explain the low set voltage in Ta{sub 2}O{sub 5} based resistive memory devices. Our work shows that other oxides with adaptive crystal structures could serve as potential candidates for resistive random access memory devices. We also discuss some general characteristics for ideal resistive RAM oxides that could be used in future computational material searches.« less

Similarity between the response of memristive and memcapacitive circuits subjected to ramped voltage

NASA Astrophysics Data System (ADS)

Kanygin, Mikhail A.; Katkov, Mikhail V.; Pershin, Yuriy V.

2017-07-01

We report a similar feature in the response of resistor-memristor and capacitor-memcapacitor circuits with threshold-type memory devices driven by triangular waveform voltage. In both cases, the voltage across the memory device is stabilized during the switching of the memory device state. While in the memristive circuit this feature is observed when the applied voltage changes in one direction, the memcapacitive circuit with a ferroelectric memcapacitor demonstrates the voltage stabilization effect at both sweep directions. The discovered behavior of capacitor-memcapacitor circuit is also demonstrated experimentally. We anticipate that our observation can be used in the design of electronic circuits with emergent memory devices as well as in the identification and characterization of memory effects in threshold-type memory devices.

Memcomputing with membrane memcapacitive systems

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Traversa, F. L.; Di Ventra, M.

2015-06-01

We show theoretically that networks of membrane memcapacitive systems—capacitors with memory made out of membrane materials—can be used to perform a complete set of logic gates in a massively parallel way by simply changing the external input amplitudes, but not the topology of the network. This polymorphism is an important characteristic of memcomputing (computing with memories) that closely reproduces one of the main features of the brain. A practical realization of these membrane memcapacitive systems, using, e.g., graphene or other 2D materials, would be a step forward towards a solid-state realization of memcomputing with passive devices.

Memory and Spin Injection Devices Involving Half Metals

DOE PAGES

Shaughnessy, M.; Snow, Ryan; Damewood, L.; ...

2011-01-01

We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

Challenges and opportunities with spin-based logic

NASA Astrophysics Data System (ADS)

Perricone, Robert; Niemier, Michael; Hu, X. Sharon

2017-09-01

In this paper, we provide a short overview of efforts to process information with spin as a state variable. We highlight initial efforts in spintronics where devices concepts such as spinwaves, field coupled nanomagnets, etc. were are considered as vehicles for processing information. We also highlight more recent work where spintronic logic and memory devices are considered in the context of information processing hardware for the internet of things (IoT), and where the ability to constantly "checkpoint" processor state can support computing in environments with unreliable power supplies.

Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

NASA Technical Reports Server (NTRS)

Schwab, Andrew J. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor); Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Moyer, Stephen A. (Inventor); Klenke, Robert (Inventor)

2000-01-01

A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

PubMed

Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

2015-10-07

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Oscillatory threshold logic.

PubMed

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

Acceleration of FDTD mode solver by high-performance computing techniques.

PubMed

Han, Lin; Xi, Yanping; Huang, Wei-Ping

2010-06-21

A two-dimensional (2D) compact finite-difference time-domain (FDTD) mode solver is developed based on wave equation formalism in combination with the matrix pencil method (MPM). The method is validated for calculation of both real guided and complex leaky modes of typical optical waveguides against the bench-mark finite-difference (FD) eigen mode solver. By taking advantage of the inherent parallel nature of the FDTD algorithm, the mode solver is implemented on graphics processing units (GPUs) using the compute unified device architecture (CUDA). It is demonstrated that the high-performance computing technique leads to significant acceleration of the FDTD mode solver with more than 30 times improvement in computational efficiency in comparison with the conventional FDTD mode solver running on CPU of a standard desktop computer. The computational efficiency of the accelerated FDTD method is in the same order of magnitude of the standard finite-difference eigen mode solver and yet require much less memory (e.g., less than 10%). Therefore, the new method may serve as an efficient, accurate and robust tool for mode calculation of optical waveguides even when the conventional eigen value mode solvers are no longer applicable due to memory limitation.

A novel neural network for the synthesis of antennas and microwave devices.

PubMed

Delgado, Heriberto Jose; Thursby, Michael H; Ham, Fredric M

2005-11-01

A novel artificial neural network (SYNTHESIS-ANN) is presented, which has been designed for computationally intensive problems and applied to the optimization of antennas and microwave devices. The antenna example presented is optimized with respect to voltage standing-wave ratio, bandwidth, and frequency of operation. A simple microstrip transmission line problem is used to further describe the ANN effectiveness, in which microstrip line width is optimized with respect to line impedance. The ANNs exploit a unique number representation of input and output data in conjunction with a more standard neural network architecture. An ANN consisting of a heteroassociative memory provided a very efficient method of computing necessary geometrical values for the antenna when used in conjunction with a new randomization process. The number representation used provides significant insight into this new method of fault-tolerant computing. Further work is needed to evaluate the potential of this new paradigm.

Interactive water monitoring system accessible by cordless telephone

NASA Astrophysics Data System (ADS)

Volpicelli, Richard; Andeweg, Pierre; Hagar, William G.

1985-12-01

A battery-operated, microcomputer-controlled monitoring device linked with a cordless telephone has been developed for remote measurements. This environmental sensor is self-contained and collects and processes data according to the information sent to its on-board computer system. An RCA model 1805 microprocessor forms the basic controller with a program encoded in memory for data acquisition and analysis. Signals from analog sensing devices used to monitor the environment are converted into digital signals and stored in random access memory of the microcomputer. This remote sensing system is linked to the laboratory by means of a cordless telephone whose base unit is connected to regular telephone lines. This offshore sensing system is simply accessed by a phone call originating from a computer terminal in the laboratory. Data acquisition is initiated upon request: Information continues to be processed and stored until the computer is reprogrammed by another phone call request. Information obtained may be recalled by a phone call after the desired environmental measurements are finished or while they are in progress. Data sampling parameters may be reset at any time, including in the middle of a measurement cycle. The range of the system is limited only by existing telephone grid systems and by the transmission characteristics of the cordless phone used as a communications link. This use of a cordless telephone, coupled with the on-board computer system, may be applied to other field studies requiring data transfer between an on-site analytical system and the laboratory.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

Bridging FPGA and GPU technologies for AO real-time control

NASA Astrophysics Data System (ADS)

Perret, Denis; Lainé, Maxime; Bernard, Julien; Gratadour, Damien; Sevin, Arnaud

2016-07-01

Our team has developed a common environment for high performance simulations and real-time control of AO systems based on the use of Graphics Processors Units in the context of the COMPASS project. Such a solution, based on the ability of the real time core in the simulation to provide adequate computing performance, limits the cost of developing AO RTC systems and makes them more scalable. A code developed and validated in the context of the simulation may be injected directly into the system and tested on sky. Furthermore, the use of relatively low cost components also offers significant advantages for the system hardware platform. However, the use of GPUs in an AO loop comes with drawbacks: the traditional way of offloading computation from CPU to GPUs - involving multiple copies and unacceptable overhead in kernel launching - is not well suited in a real time context. This last application requires the implementation of a solution enabling direct memory access (DMA) to the GPU memory from a third party device, bypassing the operating system. This allows this device to communicate directly with the real-time core of the simulation feeding it with the WFS camera pixel stream. We show that DMA between a custom FPGA-based frame-grabber and a computation unit (GPU, FPGA, or Coprocessor such as Xeon-phi) across PCIe allows us to get latencies compatible with what will be needed on ELTs. As a fine-grained synchronization mechanism is not yet made available by GPU vendors, we propose the use of memory polling to avoid interrupts handling and involvement of a CPU. Network and Vision protocols are handled by the FPGA-based Network Interface Card (NIC). We present the results we obtained on a complete AO loop using camera and deformable mirror simulators.

Satellite Test of Radiation Impact on Ramtron 512K FRAM

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Sayyah, Rana; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

2009-01-01

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite. The test consists of writing and reading data with a ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is send to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test will be one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The memory devices being tested is a Ramtron Inc. 512K memory device. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

Harvesting Entropy for Random Number Generation for Internet of Things Constrained Devices Using On-Board Sensors

PubMed Central

Pawlowski, Marcin Piotr; Jara, Antonio; Ogorzalek, Maciej

2015-01-01

Entropy in computer security is associated with the unpredictability of a source of randomness. The random source with high entropy tends to achieve a uniform distribution of random values. Random number generators are one of the most important building blocks of cryptosystems. In constrained devices of the Internet of Things ecosystem, high entropy random number generators are hard to achieve due to hardware limitations. For the purpose of the random number generation in constrained devices, this work proposes a solution based on the least-significant bits concatenation entropy harvesting method. As a potential source of entropy, on-board integrated sensors (i.e., temperature, humidity and two different light sensors) have been analyzed. Additionally, the costs (i.e., time and memory consumption) of the presented approach have been measured. The results obtained from the proposed method with statistical fine tuning achieved a Shannon entropy of around 7.9 bits per byte of data for temperature and humidity sensors. The results showed that sensor-based random number generators are a valuable source of entropy with very small RAM and Flash memory requirements for constrained devices of the Internet of Things. PMID:26506357

Ion conduction in crystalline superionic solids and its applications

NASA Astrophysics Data System (ADS)

Chandra, Angesh

2014-06-01

Superionic solids an area of multidisciplinary research activity, incorporates to study the physical, chemical and technological aspects of rapid ion movements within the bulk of the special class of ionic materials. It is an emerging area of materials science, as these solids show tremendous technological scopes to develop wide variety of solid state electrochemical devices such as batteries, fuel cells, supercapacitors, sensors, electrochromic displays (ECDs), memories, etc. These devices have wide range of applicabilities viz. power sources for IC microchips to transport vehicles, novel sensors for controlling atmospheric pollution, new kind of memories for computers, smart windows/display panels, etc. The field grew with a rapid pace since then, especially with regards to designing new materials as well as to explore their device potentialities. Amongst the known superionic solids, fast Ag+ ion conducting crystalline solid electrolytes are attracted special attention due to their relatively higher room temperature conductivity as well as ease of materials handling/synthesis. Ion conduction in these electrolytes is very much interesting part of today. In the present review article, the ion conducting phenomenon and some device applications of crystalline/polycrystalline superionic solid electrolytes have been reviewed in brief. Synthesis and characterization tools have also been discussed in the present review article.

Harvesting entropy for random number generation for internet of things constrained devices using on-board sensors.

PubMed

Pawlowski, Marcin Piotr; Jara, Antonio; Ogorzalek, Maciej

2015-10-22

Entropy in computer security is associated with the unpredictability of a source of randomness. The random source with high entropy tends to achieve a uniform distribution of random values. Random number generators are one of the most important building blocks of cryptosystems. In constrained devices of the Internet of Things ecosystem, high entropy random number generators are hard to achieve due to hardware limitations. For the purpose of the random number generation in constrained devices, this work proposes a solution based on the least-significant bits concatenation entropy harvesting method. As a potential source of entropy, on-board integrated sensors (i.e., temperature, humidity and two different light sensors) have been analyzed. Additionally, the costs (i.e., time and memory consumption) of the presented approach have been measured. The results obtained from the proposed method with statistical fine tuning achieved a Shannon entropy of around 7.9 bits per byte of data for temperature and humidity sensors. The results showed that sensor-based random number generators are a valuable source of entropy with very small RAM and Flash memory requirements for constrained devices of the Internet of Things.

PACE: Power-Aware Computing Engines

DTIC Science & Technology

2005-02-01

more costly than compu- tation on our test platform, and it is memory access that dominates most lossless data compression algorithms . In fact, even...Performance and implementation concerns A compression algorithm may be implemented with many different, yet reasonable, data structures (including...Related work This section discusses data compression for low- bandwidth devices and optimizing algorithms for low energy. Though much work has gone

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

NASA Technical Reports Server (NTRS)

Kolasinski, W. A.; Koga, R.; Blake, J. B.; Brucker, G.; Pandya, P.; Petersen, E.; Price, W.

1982-01-01

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

NASA Astrophysics Data System (ADS)

Muqeet Rehman, Muhammad; Uddin Siddiqui, Ghayas; Kim, Sowon; Choi, Kyung Hyun

2017-08-01

Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al2O3) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Near-Field Thermal Radiation for Solar Thermophotovoltaics and High Temperature Thermal Logic and Memory Applications

NASA Astrophysics Data System (ADS)

Elzouka, Mahmoud

This dissertation investigates Near-Field Thermal Radiation (NFTR) applied to MEMS-based concentrated solar thermophotovoltaics (STPV) energy conversion and thermal memory and logics. NFTR is the exchange of thermal radiation energy at nano/microscale; when separation between the hot and cold objects is less than dominant radiation wavelength (˜1 mum). NFTR is particularly of interest to the above applications due to its high rate of energy transfer, exceeding the blackbody limit by orders of magnitude, and its strong dependence on separation gap size, surface nano/microstructure and material properties. Concentrated STPV system converts solar radiation to electricity using heat as an intermediary through a thermally coupled absorber/emitter, which causes STPV to have one of the highest solar-to-electricity conversion efficiency limits (85.4%). Modeling of a near-field concentrated STPV microsystem is carried out to investigate the use of STPV based solid-state energy conversion as high power density MEMS power generator. Numerical results for In 0.18Ga0.82Sb PV cell illuminated with tungsten emitter showed significant enhancement in energy transfer, resulting in output power densities as high as 60 W/cm2; 30 times higher than the equivalent far-field power density. On thermal computing, this dissertation demonstrates near-field heat transfer enabled high temperature NanoThermoMechanical memory and logics. Unlike electronics, NanoThermoMechanical memory and logic devices use heat instead of electricity to record and process data; hence they can operate in harsh environments where electronics typically fail. NanoThermoMechanical devices achieve memory and thermal rectification functions through the coupling of near-field thermal radiation and thermal expansion in microstructures, resulting in nonlinear heat transfer between two temperature terminals. Numerical modeling of a conceptual NanoThermoMechanical is carried out; results include the dynamic response under write/read cycles for a practical silicon-based device. NanoThermoMechanical rectification is achieved experimentally--for the first time--with measurements at a high temperature of 600 K, demonstrating the feasibility of NanoThermoMechanical to operate in harsh environments. The proof-of-concept device has shown a maximum rectification of 10.9%. This dissertation proposes using meshed photonic crystal structures to enhance NFTR between surfaces. Numerical results show thermal rectification as high as 2500%. Incorporating these structures in thermal memory and rectification devices will significantly enhance their functionality and performance.

Conductive bridging random access memory—materials, devices and applications

NASA Astrophysics Data System (ADS)

Kozicki, Michael N.; Barnaby, Hugh J.

2016-11-01

We present a review and primer on the subject of conductive bridging random access memory (CBRAM), a metal ion-based resistive switching technology, in the context of current research and the near-term requirements of the electronics industry in ultra-low energy devices and new computing paradigms. We include extensive discussions of the materials involved, the underlying physics and electrochemistry, the critical roles of ion transport and electrode reactions in conducting filament formation and device switching, and the electrical characteristics of the devices. Two general cation material systems are given—a fast ion chacogenide electrolyte and a lower ion mobility oxide ion conductor, and numerical examples are offered to enhance understanding of the operation of devices based on these. The effect of device conditioning on the activation energy for ion transport and consequent switching speed is discussed, as well as the mechanisms involved in the removal of the conducting bridge. The morphology of the filament and how this could be influenced by the solid electrolyte structure is described, and the electrical characteristics of filaments with atomic-scale constrictions are discussed. Consideration is also given to the thermal and mechanical environments within the devices. Finite element and compact modelling illustrations are given and aspects of CBRAM storage elements in memory circuits and arrays are included. Considerable emphasis is placed on the effects of ionizing radiation on CBRAM since this is important in various high reliability applications, and the potential uses of the devices in reconfigurable logic and neuromorphic systems is also discussed.

Resistive Random Access Memory from Materials Development fnd Engineering to Novel Encryption and Neuromorphic Applications

NASA Astrophysics Data System (ADS)

Beckmann, Karsten

Resistive random access memory (ReRAM or RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance state of ReRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse properties. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. I have developed two processes based on 100 and 300mm wafer platforms to demonstrate functional HfO2 based ReRAM devices. The first process is designed for a rapid materials engineering and device characterization, while the second is an advanced hybrid ReRAM/CMOS combination based on the IBM 65nm 10LPe process technology. The 100mm wafer efforts were used to show impacts of etch processes on ReRAM switching performance and the need for a rigorous structural evaluation of ReRAM devices before starting materials development. After an etch development, a bottom electrode comparison between the inert materials Pt, Ru and W was performed where Ru showed superior results with respect to yield and resilience against environmental impacts such as humidity over a 2-month period. A comparison of amorphous and crystalline devices showed no statistical difference in the performance with respect to random telegraph noise. This demonstrates, that the forming process fundamentally alters the crystallographic structure within and around the filament. The 300mm wafer development efforts were aimed towards implementing ReRAM in the FEOL, combined with CMOS, to yield a seamless process flow of 1 transistor 1 ReRAM structures (1T1R). This technology was customized with custom-developed tungsten metal 1 (M1) and dual tungsten/copper via 1 (V1) structures, within which the ReRAM stack is embedded. The ReRAM itself consists of an inert W bottom electrode, HfO2 based active switching layer, a Ti oxygen scavenger layer, and an inert TiN top electrode. Linear sweep and controlled pulse (down to 5 ns) based electrical characterization of 1 transistor 1 ReRAM (1T1R) elements was performed to determine key properties including endurance, reliability, and threshold voltages. We demonstrated endurance values above 1010 cycles with an average on/off ratio of 10, and pulse voltages for set/reset operation of +/-1.5V. The on-chip 1T1R structures show an excellent controllability with respect to the low and high resistive states by manipulating the peak current from 75 up to 350 mu?A resulting in 10 distinct low resistance states (LRS). Our results demonstrate that the set operation (which shifts the ReRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage resulting in a larger relative change of the ReRAM device resistance. The incremental resistance changes are ideally suited to emulate synaptic weights for future implementation into neuromorphic architectures. Switching results from these devices were also used to develop a model time-delay physical unclonable function (PUF) circuit, which showed excellent performance when compared to a pure CMOS implementation with significant improvements in uniqueness, size and accuracy.

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klymenko, M. V.; Klein, M.; Levine, R. D.

2016-07-14

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states correspondsmore » to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.« less

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

EDITORIAL: Synaptic electronics Synaptic electronics

NASA Astrophysics Data System (ADS)

Demming, Anna; Gimzewski, James K.; Vuillaume, Dominique

2013-09-01

Conventional computers excel in logic and accurate scientific calculations but make hard work of open ended problems that human brains handle easily. Even von Neumann—the mathematician and polymath who first developed the programming architecture that forms the basis of today's computers—was already looking to the brain for future developments before his death in 1957 [1]. Neuromorphic computing uses approaches that better mimic the working of the human brain. Recent developments in nanotechnology are now providing structures with very accommodating properties for neuromorphic approaches. This special issue, with guest editors James K Gimzewski and Dominique Vuillaume, is devoted to research at the serendipitous interface between the two disciplines. 'Synaptic electronics', looks at artificial devices with connections that demonstrate behaviour similar to synapses in the nervous system allowing a new and more powerful approach to computing. Synapses and connecting neurons respond differently to incident signals depending on the history of signals previously experienced, ultimately leading to short term and long term memory behaviour. The basic characteristics of a synapse can be replicated with around ten simple transistors. However with the human brain having around 1011 neurons and 1015 synapses, artificial neurons and synapses from basic transistors are unlikely to accommodate the scalability required. The discovery of nanoscale elements that function as 'memristors' has provided a key tool for the implementation of synaptic connections [2]. Leon Chua first developed the concept of the 'The memristor—the missing circuit element' in 1971 [3]. In this special issue he presents a tutorial describing how memristor research has fed into our understanding of synaptic behaviour and how they can be applied in information processing [4]. He also describes, 'The new principle of local activity, which uncovers a minuscule life-enabling "Goldilocks zone", dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge'. Also in this issue R Stanley Williams and colleagues report results from simulations that demonstrate the potential for using Mott transistors as building blocks for scalable neuristor-based integrated circuits without transistors [5]. The scalability of neural chip designs is also tackled in the design reported by Narayan Srinivasa and colleagues in the US [6]. Meanwhile Carsten Timm and Massimiliano Di Ventra describe simulations of a molecular transistor in which electrons strongly coupled to a vibrational mode lead to a Franck-Condon (FC) blockade that mimics the spiking action potentials in synaptic memory behaviour [7]. The 'atomic switches' used to demonstrate synaptic behaviour by a collaboration of researchers in California and Japan also come under further scrutiny in this issue. James K Gimzewski and colleagues consider the difference between the behaviour of an atomic switch in isolation and in a network [8]. As the authors point out, 'The work presented represents steps in a unified approach of experimentation and theory of complex systems to make atomic switch networks a uniquely scalable platform for neuromorphic computing'. Researchers in Germany [9] and Sweden [10] also report on theoretical approaches to modelling networks of memristive elements and complementary resistive switches for synaptic devices. As Vincent Derycke and colleagues in France point out, 'Actual experimental demonstrations of neural network type circuits based on non-conventional/non-CMOS memory devices and displaying function learning capabilities remain very scarce'. They describe how their work using carbon nanotubes provides a rare demonstration of actual function learning with synapses based on nanoscale building blocks [11]. However, this is far from the only experimental work reported in this issue, others include: short-term memory of TiO2-based electrochemical capacitors [12]; a neuromorphic circuit composed of a nanoscale 1-kbit resistive random-access memory (RRAM) cross-point array of synapses and complementary metal-oxide-semiconductor (CMOS) neuron circuits [13]; a WO3-x-based nanoionics device from Masakazu Aono's group with a wide scale of reprogrammable memorization functions [14]; a new spike-timing dependent plasticity scheme based on a MOS transistor as a selector and a RRAM as a variable resistance device [15]; a new hybrid memristor-CMOS neuromorphic circuit [16]; and a photo-assisted atomic switch [17]. Synaptic electronics evidently has many emerging facets, and Duygu Kuzum, Shimeng Yu, and H-S Philip Wong in the US provide a review of the field, including the materials, devices and applications [18]. In embracing the expertise acquired over thousands of years of evolution, biomimetics and bio-inspired design is a common, smart approach to technological innovation. Yet in successfully mimicking the physiological mechanisms of the human mind synaptic electronics research has a potential impact that is arguably unprecedented. That the quirks and eccentricities recently unearthed in the behaviour of nanomaterials should lend themselves so accommodatingly to emulating synaptic functions promises some very exciting developments in the field, as the articles in this special issue emphasize. References [1] von Neumann J (ed) 2012 The Computer and the Brain 3rd edn (Yale: Yale University Press) [2] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 The missing memristor found Nature 453 80-3 [3] Chua L O 1971 Memristor—the missing circuit element IEEE Trans. Circuit Theory 18 507-19 [4] Chua L O 2013 Memristor, Hodgkin-Huxley, and Edge of Chaos Nanotechnology 24 383001 [5] Pickett M D and Williams R S 2013 Phase transitions enable computational universality in neuristor-based cellular automata Nanotechnology 24 384002 [6] Cruz-Albrecht J M, Derosier T and Srinivasa N 2013 Scalable neural chip with synaptic electronics using CMOS integrated memristors Nanotechnology 24 384011 [7] Timm C and Di Ventra M 2013 Molecular neuron based on the Franck-Condon blockade Nanotechnology 24 384001 [8] Sillin H O, Aguilera R, Shieh H-H, Avizienis A V, Aono M, Stieg A Z and Gimzewski J K 2013 A theoretical and experimental study of neuromorphic atomic switch networks for reservoir computing Nanotechnology 24 384004 [9] Linn E, Menzel S, Ferch S and Waser R 2013 Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications Nanotechnology 24 384008 [10] Konkoli Z and Wendin G 2013 A generic simulator for large networks of memristive elements Nanotechnology 24 384007 [11] Gacem K, Retrouvey J-M, Chabi D, Filoramo A, Zhao W, Klein J-O and Derycke V 2013 Neuromorphic function learning with carbon nanotube-based synapses Nanotechnology 24 384013 [12] Lim H, Kim I, Kim J-S, Hwang C S and Jeong D S 2013 Short-term memory of TiO2-based electrochemical capacitors: empirical analysis with adoption of a sliding threshold Nanotechnology 24 384005 [13] Park S, Noh J, Choo M-L, Sheri A M, Chang M, Kim Y-B, Kim C J, Jeon M, Lee B-G, Lee B H and Hwang H 2013 Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device Nanotechnology 24 384009 [14] Yang R, Terabe K, Yao Y, Tsuruoka T, Hasegawa T, Gimzewski J K and Aono M 2013 Synaptic plasticity and memory functions achieved in WO3-x-based nanoionics device by using principle of atomic switch operation Nanotechnology 24 384002 [15] Ambrogio S, Balatti S, Nardi F, Facchinetti S and Ielmini D 2013 Spike-timing dependent plasticity in a transistor-selected resistive switching memory Nanotechnology 24 384012 [16] Indiveria G, Linares-Barranco B, Legenstein R, Deligeorgis G and Prodromakise T 2013 Integration of nanoscale memristor synapses in neuromorphic computing architectures Nanotechnology 24 384010 [17] Hino T, Hasegawa T, Tanaka H, Tsuruoka T, Terabe K, Ogawa T and Aono M 2013 Volatile and nonvolatile selective switching of a photo-assited initialized atomic switch Nanotechnology 24 384006 [18] Kuzum D, Yu S and Wong H-S P 2013 Synaptic electronics: materials, devices and applications Nanotechnology 24 382001

Coherent Dynamics of a Hybrid Quantum Spin-Mechanical Oscillator System

NASA Astrophysics Data System (ADS)

Lee, Kenneth William, III

A fully functional quantum computer must contain at least two important components: a quantum memory for storing and manipulating quantum information and a quantum data bus to securely transfer information between quantum memories. Typically, a quantum memory is composed of a matter system, such as an atom or an electron spin, due to their prolonged quantum coherence. Alternatively, a quantum data bus is typically composed of some propagating degree of freedom, such as a photon, which can retain quantum information over long distances. Therefore, a quantum computer will likely be a hybrid quantum device, consisting of two or more disparate quantum systems. However, there must be a reliable and controllable quantum interface between the memory and bus in order to faithfully interconvert quantum information. The current engineering challenge for quantum computers is scaling the device to large numbers of controllable quantum systems, which will ultimately depend on the choice of the quantum elements and interfaces utilized in the device. In this thesis, we present and characterize a hybrid quantum device comprised of single nitrogen-vacancy (NV) centers embedded in a high quality factor diamond mechanical oscillator. The electron spin of the NV center is a leading candidate for the realization of a quantum memory due to its exceptional quantum coherence times. On the other hand, mechanical oscillators are highly sensitive to a wide variety of external forces, and have the potential to serve as a long-range quantum bus between quantum systems of disparate energy scales. These two elements are interfaced through crystal strain generated by vibrations of the mechanical oscillator. Importantly, a strain interface allows for a scalable architecture, and furthermore, opens the door to integration into a larger quantum network through coupling to an optical interface. There are a few important engineering challenges associated with this device. First, there have been no previous demonstrations of a strain-mediated spin-mechanical interface and hence the system is largely uncharacterized. Second, fabricating high quality diamond mechanical oscillators is difficult due to the robust and chemically inert nature of diamond. Finally, engineering highly coherent NV centers with a coherent optical interface in nanostructured diamond remains an outstanding challenge. In this thesis, we theoretically and experimentally address each of these challenges, and show that with future improvements, this device is suitable for future quantum-enabled applications. First, we theoretically and experimentally demonstrate a dynamic, strain-mediated coupling between the spin and orbital degrees of freedom of the NV center and the driven mechanical motion of a single-crystal diamond cantilever. We employ Ramsey interferometry to demonstrate coherent, mechanical driving of the NV spin evolution. Using this interferometry technique, we present the first demonstration of nanoscale strain imaging, and quantitatively characterize the previously unknown spin-strain coupling constants. Next, we use the driven motion of the cantilever to perform deterministic control of the frequency and polarization dependence of the optical transitions of the NV center. Importantly, this experiment constitutes the first demonstration of on-chip control of both the frequency and polarization state of a single photon produced by a quantum emitter. In the final experiment, we use mechanical driving to engineer a series of spin ``clock" states and demonstrate a significant increase in the spin coherence time of the NV center. We conclude this thesis with a theoretical discussion of prospective applications for this device, including generation of non-classical mechanical states and spin-spin entanglement, as well as an evaluation of the current limitations of our devices, including a possible avenues for improvement to reach the regime of strong spin-phonon coupling.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

Method and apparatus of parallel computing with simultaneously operating stream prefetching and list prefetching engines

DOEpatents

Boyle, Peter A.; Christ, Norman H.; Gara, Alan; Mawhinney, Robert D.; Ohmacht, Martin; Sugavanam, Krishnan

2012-12-11

A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.

A Vision-Based System for Object Identification and Information Retrieval in a Smart Home

NASA Astrophysics Data System (ADS)

Grech, Raphael; Monekosso, Dorothy; de Jager, Deon; Remagnino, Paolo

This paper describes a hand held device developed to assist people to locate and retrieve information about objects in a home. The system developed is a standalone device to assist persons with memory impairments such as people suffering from Alzheimer's disease. A second application is object detection and localization for a mobile robot operating in an ambient assisted living environment. The device relies on computer vision techniques to locate a tagged object situated in the environment. The tag is a 2D color printed pattern with a detection range and a field of view such that the user may point from a distance of over 1 meter.

Titanium oxide nonvolatile memory device and its application

NASA Astrophysics Data System (ADS)

Wang, Wei

In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be explained by thermal dissolution model, and bipolar switching by local redox reaction model. Since it is generally agreed that the memory switching of TiOx NVM devices is based on conductive filaments, reusability of these conductive filaments becomes an intriguing issue to determine the memory device's endurance. A 1X3 cross-point test structure is built to investigate whether conductive filaments can be reused after RESET. It is found that the conductive filament is destroyed during unipolar switching, while can be reused during bipolar switching. The result is a good indication that bipolar switching should have better endurance than unipolar switching. Finally a novel application of the two-terminal resistive switching NVM devices is demonstrated. To reduce SRAM leakage power, we propose a nonvolatile SRAM cell with two back-up NVM devices. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty in this approach. Only a slight performance penalty is expected.

The architecture of tomorrow's massively parallel computer

NASA Technical Reports Server (NTRS)

Batcher, Ken

1987-01-01

Goodyear Aerospace delivered the Massively Parallel Processor (MPP) to NASA/Goddard in May 1983, over three years ago. Ever since then, Goodyear has tried to look in a forward direction. There is always some debate as to which way is forward when it comes to supercomputer architecture. Improvements to the MPP's massively parallel architecture are discussed in the areas of data I/O, memory capacity, connectivity, and indirect (or local) addressing. In I/O, transfer rates up to 640 megabytes per second can be achieved. There are devices that can supply the data and accept it at this rate. The memory capacity can be increased up to 128 megabytes in the ARU and over a gigabyte in the staging memory. For connectivity, there are several different kinds of multistage networks that should be considered.

Optically programmable electron spin memory using semiconductor quantum dots.

PubMed

Kroutvar, Miro; Ducommun, Yann; Heiss, Dominik; Bichler, Max; Schuh, Dieter; Abstreiter, Gerhard; Finley, Jonathan J

2004-11-04

The spin of a single electron subject to a static magnetic field provides a natural two-level system that is suitable for use as a quantum bit, the fundamental logical unit in a quantum computer. Semiconductor quantum dots fabricated by strain driven self-assembly are particularly attractive for the realization of spin quantum bits, as they can be controllably positioned, electronically coupled and embedded into active devices. It has been predicted that the atomic-like electronic structure of such quantum dots suppresses coupling of the spin to the solid-state quantum dot environment, thus protecting the 'spin' quantum information against decoherence. Here we demonstrate a single electron spin memory device in which the electron spin can be programmed by frequency selective optical excitation. We use the device to prepare single electron spins in semiconductor quantum dots with a well defined orientation, and directly measure the intrinsic spin flip time and its dependence on magnetic field. A very long spin lifetime is obtained, with a lower limit of about 20 milliseconds at a magnetic field of 4 tesla and at 1 kelvin.

Bulk heterojunction polymer memory devices with reduced graphene oxide as electrodes.

PubMed

Liu, Juqing; Yin, Zongyou; Cao, Xiehong; Zhao, Fei; Lin, Anping; Xie, Linghai; Fan, Quli; Boey, Freddy; Zhang, Hua; Huang, Wei

2010-07-27

A unique device structure with a configuration of reduced graphene oxide (rGO) /P3HT:PCBM/Al has been designed for the polymer nonvolatile memory device. The current-voltage (I-V) characteristics of the fabricated device showed the electrical bistability with a write-once-read-many-times (WORM) memory effect. The memory device exhibits a high ON/OFF ratio (10(4)-10(5)) and low switching threshold voltage (0.5-1.2 V), which are dependent on the sheet resistance of rGO electrode. Our experimental results confirm that the carrier transport mechanisms in the OFF and ON states are dominated by the thermionic emission current and ohmic current, respectively. The polarization of PCBM domains and the localized internal electrical field formed among the adjacent domains are proposed to explain the electrical transition of the memory device.

Xyce Parallel Electronic Simulator : users' guide, version 2.0.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoekstra, Robert John; Waters, Lon J.; Rankin, Eric Lamont

2004-06-01

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator capable of simulating electrical circuits at a variety of abstraction levels. Primarily, Xyce has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability the current state-of-the-art in the following areas: {sm_bullet} Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). Note that this includes support for most popular parallel and serial computers. {sm_bullet} Improved performance for allmore » numerical kernels (e.g., time integrator, nonlinear and linear solvers) through state-of-the-art algorithms and novel techniques. {sm_bullet} Device models which are specifically tailored to meet Sandia's needs, including many radiation-aware devices. {sm_bullet} A client-server or multi-tiered operating model wherein the numerical kernel can operate independently of the graphical user interface (GUI). {sm_bullet} Object-oriented code design and implementation using modern coding practices that ensure that the Xyce Parallel Electronic Simulator will be maintainable and extensible far into the future. Xyce is a parallel code in the most general sense of the phrase - a message passing of computing platforms. These include serial, shared-memory and distributed-memory parallel implementation - which allows it to run efficiently on the widest possible number parallel as well as heterogeneous platforms. Careful attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. One feature required by designers is the ability to add device models, many specific to the needs of Sandia, to the code. To this end, the device package in the Xyce These input formats include standard analytical models, behavioral models look-up Parallel Electronic Simulator is designed to support a variety of device model inputs. tables, and mesh-level PDE device models. Combined with this flexible interface is an architectural design that greatly simplifies the addition of circuit models. One of the most important feature of Xyce is in providing a platform for computational research and development aimed specifically at the needs of the Laboratory. With Xyce, Sandia now has an 'in-house' capability with which both new electrical (e.g., device model development) and algorithmic (e.g., faster time-integration methods) research and development can be performed. Ultimately, these capabilities are migrated to end users.« less

A CFD Heterogeneous Parallel Solver Based on Collaborating CPU and GPU

NASA Astrophysics Data System (ADS)

Lai, Jianqi; Tian, Zhengyu; Li, Hua; Pan, Sha

2018-03-01

Since Graphic Processing Unit (GPU) has a strong ability of floating-point computation and memory bandwidth for data parallelism, it has been widely used in the areas of common computing such as molecular dynamics (MD), computational fluid dynamics (CFD) and so on. The emergence of compute unified device architecture (CUDA), which reduces the complexity of compiling program, brings the great opportunities to CFD. There are three different modes for parallel solution of NS equations: parallel solver based on CPU, parallel solver based on GPU and heterogeneous parallel solver based on collaborating CPU and GPU. As we can see, GPUs are relatively rich in compute capacity but poor in memory capacity and the CPUs do the opposite. We need to make full use of the GPUs and CPUs, so a CFD heterogeneous parallel solver based on collaborating CPU and GPU has been established. Three cases are presented to analyse the solver’s computational accuracy and heterogeneous parallel efficiency. The numerical results agree well with experiment results, which demonstrate that the heterogeneous parallel solver has high computational precision. The speedup on a single GPU is more than 40 for laminar flow, it decreases for turbulent flow, but it still can reach more than 20. What’s more, the speedup increases as the grid size becomes larger.

Practical experimental certification of computational quantum gates using a twirling procedure.

PubMed

Moussa, Osama; da Silva, Marcus P; Ryan, Colm A; Laflamme, Raymond

2012-08-17

Because of the technical difficulty of building large quantum computers, it is important to be able to estimate how faithful a given implementation is to an ideal quantum computer. The common approach of completely characterizing the computation process via quantum process tomography requires an exponential amount of resources, and thus is not practical even for relatively small devices. We solve this problem by demonstrating that twirling experiments previously used to characterize the average fidelity of quantum memories efficiently can be easily adapted to estimate the average fidelity of the experimental implementation of important quantum computation processes, such as unitaries in the Clifford group, in a practical and efficient manner with applicability in current quantum devices. Using this procedure, we demonstrate state-of-the-art coherent control of an ensemble of magnetic moments of nuclear spins in a single crystal solid by implementing the encoding operation for a 3-qubit code with only a 1% degradation in average fidelity discounting preparation and measurement errors. We also highlight one of the advances that was instrumental in achieving such high fidelity control.

Systems and methods to control multiple peripherals with a single-peripheral application code

DOEpatents

Ransom, Ray M.

2013-06-11

Methods and apparatus are provided for enhancing the BIOS of a hardware peripheral device to manage multiple peripheral devices simultaneously without modifying the application software of the peripheral device. The apparatus comprises a logic control unit and a memory in communication with the logic control unit. The memory is partitioned into a plurality of ranges, each range comprising one or more blocks of memory, one range being associated with each instance of the peripheral application and one range being reserved for storage of a data pointer related to each peripheral application of the plurality. The logic control unit is configured to operate multiple instances of the control application by duplicating one instance of the peripheral application for each peripheral device of the plurality and partitioning a memory device into partitions comprising one or more blocks of memory, one partition being associated with each instance of the peripheral application. The method then reserves a range of memory addresses for storage of a data pointer related to each peripheral device of the plurality, and initializes each of the plurality of peripheral devices.

Roads towards fault-tolerant universal quantum computation

NASA Astrophysics Data System (ADS)

Campbell, Earl T.; Terhal, Barbara M.; Vuillot, Christophe

2017-09-01

A practical quantum computer must not merely store information, but also process it. To prevent errors introduced by noise from multiplying and spreading, a fault-tolerant computational architecture is required. Current experiments are taking the first steps toward noise-resilient logical qubits. But to convert these quantum devices from memories to processors, it is necessary to specify how a universal set of gates is performed on them. The leading proposals for doing so, such as magic-state distillation and colour-code techniques, have high resource demands. Alternative schemes, such as those that use high-dimensional quantum codes in a modular architecture, have potential benefits, but need to be explored further.

Roads towards fault-tolerant universal quantum computation.

PubMed

Campbell, Earl T; Terhal, Barbara M; Vuillot, Christophe

2017-09-13

A practical quantum computer must not merely store information, but also process it. To prevent errors introduced by noise from multiplying and spreading, a fault-tolerant computational architecture is required. Current experiments are taking the first steps toward noise-resilient logical qubits. But to convert these quantum devices from memories to processors, it is necessary to specify how a universal set of gates is performed on them. The leading proposals for doing so, such as magic-state distillation and colour-code techniques, have high resource demands. Alternative schemes, such as those that use high-dimensional quantum codes in a modular architecture, have potential benefits, but need to be explored further.

Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing.

PubMed

Kuzum, Duygu; Jeyasingh, Rakesh G D; Lee, Byoungil; Wong, H-S Philip

2012-05-09

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption.

The biological microprocessor, or how to build a computer with biological parts

PubMed Central

Moe-Behrens, Gerd HG

2013-01-01

Systemics, a revolutionary paradigm shift in scientific thinking, with applications in systems biology, and synthetic biology, have led to the idea of using silicon computers and their engineering principles as a blueprint for the engineering of a similar machine made from biological parts. Here we describe these building blocks and how they can be assembled to a general purpose computer system, a biological microprocessor. Such a system consists of biological parts building an input / output device, an arithmetic logic unit, a control unit, memory, and wires (busses) to interconnect these components. A biocomputer can be used to monitor and control a biological system. PMID:24688733

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

NASA Astrophysics Data System (ADS)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (<=30 ns), excellent endurance (~1012 cycles), stability (>106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

A flexible nonvolatile resistive switching memory device based on ZnO film fabricated on a foldable PET substrate.

PubMed

Sun, Bai; Zhang, Xuejiao; Zhou, Guangdong; Yu, Tian; Mao, Shuangsuo; Zhu, Shouhui; Zhao, Yong; Xia, Yudong

2018-06-15

In this work, a flexible resistive switching memory device based on ZnO film was fabricated using a foldable Polyethylene terephthalate (PET) film as substrate while Ag and Ti acts top and bottom electrode. Our as-prepared device represents an outstanding nonvolatile memory behavior with good "write-read-erase-read" stability at room temperature. Finally, a physical model of Ag conductive filament is constructed to understanding the observed memory characteristics. The work provides a new way for the preparation of flexible memory devices based on ZnO films, and especially provides an experimental basis for the exploration of high-performance and portable nonvolatile resistance random memory (RRAM). Copyright © 2018 Elsevier Inc. All rights reserved.

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

NASA Technical Reports Server (NTRS)

Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

2018-01-01

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

A malicious pattern detection engine for embedded security systems in the Internet of Things.

PubMed

Oh, Doohwan; Kim, Deokho; Ro, Won Woo

2014-12-16

With the emergence of the Internet of Things (IoT), a large number of physical objects in daily life have been aggressively connected to the Internet. As the number of objects connected to networks increases, the security systems face a critical challenge due to the global connectivity and accessibility of the IoT. However, it is difficult to adapt traditional security systems to the objects in the IoT, because of their limited computing power and memory size. In light of this, we present a lightweight security system that uses a novel malicious pattern-matching engine. We limit the memory usage of the proposed system in order to make it work on resource-constrained devices. To mitigate performance degradation due to limitations of computation power and memory, we propose two novel techniques, auxiliary shifting and early decision. Through both techniques, we can efficiently reduce the number of matching operations on resource-constrained systems. Experiments and performance analyses show that our proposed system achieves a maximum speedup of 2.14 with an IoT object and provides scalable performance for a large number of patterns.

A Component-Based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations

PubMed Central

Mak, Terrence S. T.; Rachmuth, Guy; Lam, Kai-Pui; Poon, Chi-Sang

2008-01-01

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field Programmable Gate Array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the AMPA and NMDA synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired. PMID:17190033

Oscillatory Threshold Logic

PubMed Central

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

Impacts of Co doping on ZnO transparent switching memory device characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Simanjuntak, Firman Mangasa; Wei, Kung-Hwa; Prasad, Om Kumar

2016-05-02

The resistive switching characteristics of indium tin oxide (ITO)/Zn{sub 1−x}Co{sub x}O/ITO transparent resistive memory devices were investigated. An appropriate amount of cobalt dopant in ZnO resistive layer demonstrated sufficient memory window and switching stability. In contrast, pure ZnO devices demonstrated a poor memory window, and using an excessive dopant concentration led to switching instability. To achieve suitable memory performance, relying only on controlling defect concentrations is insufficient; the grain growth orientation of the resistive layer must also be considered. Stable endurance with an ON/OFF ratio of more than one order of magnitude during 5000 cycles confirmed that the Co-doped ZnOmore » device is a suitable candidate for resistive random access memory application. Additionally, fully transparent devices with a high transmittance of up to 90% at wavelength of 550 nm have been fabricated.« less

A floating-point/multiple-precision processor for airborne applications

NASA Technical Reports Server (NTRS)

Yee, R.

1982-01-01

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Flexible non-volatile memory devices based on organic semiconductors

NASA Astrophysics Data System (ADS)

Cosseddu, Piero; Casula, Giulia; Lai, Stefano; Bonfiglio, Annalisa

2015-09-01

The possibility of developing fully organic electronic circuits is critically dependent on the ability to realize a full set of electronic functionalities based on organic devices. In order to complete the scene, a fundamental element is still missing, i.e. reliable data storage. Over the past few years, a considerable effort has been spent on the development and optimization of organic polymer based memory elements. Among several possible solutions, transistor-based memories and resistive switching-based memories are attracting a great interest in the scientific community. In this paper, a route for the fabrication of organic semiconductor-based memory devices with performances beyond the state of the art is reported. Both the families of organic memories will be considered. A flexible resistive memory based on a novel combination of materials is presented. In particular, high retention time in ambient conditions are reported. Complementary, a low voltage transistor-based memory is presented. Low voltage operation is allowed by an hybrid, nano-sized dielectric, which is also responsible for the memory effect in the device. Thanks to the possibility of reproducibly fabricating such device on ultra-thin substrates, high mechanical stability is reported.

Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

NASA Technical Reports Server (NTRS)

MacLeond, Todd C.; Sims, W. Herb; Varnavas,Kosta A.; Ho, Fat D.

2011-01-01

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

The future of memory

NASA Astrophysics Data System (ADS)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

A High Performance Micro Channel Interface for Real-Time Industrial Image Processing

Treesearch

Thomas H. Drayer; Joseph G. Tront; Richard W. Conners

1995-01-01

Data collection and transfer devices are critical to the performance of any machine vision system. The interface described in this paper collects image data from a color line scan camera and transfers the data obtained into the system memory of a Micro Channel-based host computer. A maximum data transfer rate of 20 Mbytes/sec can be achieved using the DMA capabilities...

Overview of Probe-based Storage Technologies

NASA Astrophysics Data System (ADS)

Wang, Lei; Yang, Ci Hui; Wen, Jing; Gong, Si Di; Peng, Yuan Xiu

2016-07-01

The current world is in the age of big data where the total amount of global digital data is growing up at an incredible rate. This indeed necessitates a drastic enhancement on the capacity of conventional data storage devices that are, however, suffering from their respective physical drawbacks. Under this circumstance, it is essential to aggressively explore and develop alternative promising mass storage devices, leading to the presence of probe-based storage devices. In this paper, the physical principles and the current status of several different probe storage devices, including thermo-mechanical probe memory, magnetic probe memory, ferroelectric probe memory, and phase-change probe memory, are reviewed in details, as well as their respective merits and weakness. This paper provides an overview of the emerging probe memories potentially for next generation storage device so as to motivate the exploration of more innovative technologies to push forward the development of the probe storage devices.

Overview of Probe-based Storage Technologies.

PubMed

Wang, Lei; Yang, Ci Hui; Wen, Jing; Gong, Si Di; Peng, Yuan Xiu

2016-12-01

The current world is in the age of big data where the total amount of global digital data is growing up at an incredible rate. This indeed necessitates a drastic enhancement on the capacity of conventional data storage devices that are, however, suffering from their respective physical drawbacks. Under this circumstance, it is essential to aggressively explore and develop alternative promising mass storage devices, leading to the presence of probe-based storage devices. In this paper, the physical principles and the current status of several different probe storage devices, including thermo-mechanical probe memory, magnetic probe memory, ferroelectric probe memory, and phase-change probe memory, are reviewed in details, as well as their respective merits and weakness. This paper provides an overview of the emerging probe memories potentially for next generation storage device so as to motivate the exploration of more innovative technologies to push forward the development of the probe storage devices.

Memory effects in a Al/Ti:HfO2/CuPc metal-oxide-semiconductor device

NASA Astrophysics Data System (ADS)

Tripathi, Udbhav; Kaur, Ramneek

2016-05-01

Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO2) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.

A Strategy to Design High-Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials.

PubMed

Hwang, Bohee; Lee, Jang-Sik

2017-08-01

The demand for high memory density has increased due to increasing needs of information storage, such as big data processing and the Internet of Things. Organic-inorganic perovskite materials that show nonvolatile resistive switching memory properties have potential applications as the resistive switching layer for next-generation memory devices, but, for practical applications, these materials should be utilized in high-density data-storage devices. Here, nanoscale memory devices are fabricated by sequential vapor deposition of organolead halide perovskite (OHP) CH 3 NH 3 PbI 3 layers on wafers perforated with 250 nm via-holes. These devices have bipolar resistive switching properties, and show low-voltage operation, fast switching speed (200 ns), good endurance, and data-retention time >10 5 s. Moreover, the use of sequential vapor deposition is extended to deposit CH 3 NH 3 PbI 3 as the memory element in a cross-point array structure. This method to fabricate high-density memory devices could be used for memory cells that occupy large areas, and to overcome the scaling limit of existing methods; it also presents a way to use OHPs to increase memory storage capacity. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Active holographic interconnects for interfacing volume storage

NASA Astrophysics Data System (ADS)

Domash, Lawrence H.; Schwartz, Jay R.; Nelson, Arthur R.; Levin, Philip S.

1992-04-01

In order to achieve the promise of terabit/cm3 data storage capacity for volume holographic optical memory, two technological challenges must be met. Satisfactory storage materials must be developed and the input/output architectures able to match their capacity with corresponding data access rates must also be designed. To date the materials problem has received more attention than devices and architectures for access and addressing. Two philosophies of parallel data access to 3-D storage have been discussed. The bit-oriented approach, represented by recent work on two-photon memories, attempts to store bits at local sites within a volume without affecting neighboring bits. High speed acousto-optic or electro- optic scanners together with dynamically focused lenses not presently available would be required. The second philosophy is that volume optical storage is essentially holographic in nature, and that each data write or read is to be distributed throughout the material volume on the basis of angle multiplexing or other schemes consistent with the principles of holography. The requirements for free space optical interconnects for digital computers and fiber optic network switching interfaces are also closely related to this class of devices. Interconnects, beamlet generators, angle multiplexers, scanners, fiber optic switches, and dynamic lenses are all devices which may be implemented by holographic or microdiffractive devices of various kinds, which we shall refer to collectively as holographic interconnect devices. At present, holographic interconnect devices are either fixed holograms or spatial light modulators. Optically or computer generated holograms (submicron resolution, 2-D or 3-D, encoding 1013 bits, nearly 100 diffraction efficiency) can implement sophisticated mathematical design principles, but of course once fabricated they cannot be changed. Spatial light modulators offer high speed programmability but have limited resolution (512 X 512 pixels, encoding about 106 bits of data) and limited diffraction efficiency. For any application, one must choose between high diffractive performance and programmability.

Radio-nuclide mixture identification using medium energy resolution detectors

DOEpatents

Nelson, Karl Einar

2013-09-17

According to one embodiment, a method for identifying radio-nuclides includes receiving spectral data, extracting a feature set from the spectral data comparable to a plurality of templates in a template library, and using a branch and bound method to determine a probable template match based on the feature set and templates in the template library. In another embodiment, a device for identifying unknown radio-nuclides includes a processor, a multi-channel analyzer, and a memory operatively coupled to the processor, the memory having computer readable code stored thereon. The computer readable code is configured, when executed by the processor, to receive spectral data, to extract a feature set from the spectral data comparable to a plurality of templates in a template library, and to use a branch and bound method to determine a probable template match based on the feature set and templates in the template library.

Correlation analysis between the current fluctuation characteristics and the conductive filament morphology of HfO2-based memristor

NASA Astrophysics Data System (ADS)

Li, Yi; Yin, Kang-Sheng; Zhang, Mei-Yun; Cheng, Long; Lu, Ke; Long, Shi-Bing; Zhou, Yaxiong; Wang, Zhuorui; Xue, Kan-Hao; Liu, Ming; Miao, Xiang-Shui

2017-11-01

Memristors are attracting considerable interest for their prospective applications in nonvolatile memory, neuromorphic computing, and in-memory computing. However, the nature of resistance switching is still under debate, and current fluctuation in memristors is one of the critical concerns for stable performance. In this work, random telegraph noise (RTN) as the indication of current instabilities in distinct resistance states of the Pt/Ti/HfO2/W memristor is thoroughly investigated. Standard two-level digital-like RTN, multilevel current instabilities with non-correlation/correlation defects, and irreversible current transitions are observed and analyzed. The dependence of RTN on the resistance and read bias reveals that the current fluctuation depends strongly on the morphology and evolution of the conductive filament composed of oxygen vacancies. Our results link the current fluctuation behaviors to the evolution of the conductive filament and will guide continuous optimization of memristive devices.

Representing exact number visually using mental abacus.

PubMed

Frank, Michael C; Barner, David

2012-02-01

Mental abacus (MA) is a system for performing rapid and precise arithmetic by manipulating a mental representation of an abacus, a physical calculation device. Previous work has speculated that MA is based on visual imagery, suggesting that it might be a method of representing exact number nonlinguistically, but given the limitations on visual working memory, it is unknown how MA structures could be stored. We investigated the structure of the representations underlying MA in a group of children in India. Our results suggest that MA is represented in visual working memory by splitting the abacus into a series of columns, each of which is independently stored as a unit with its own detailed substructure. In addition, we show that the computations of practiced MA users (but not those of control participants) are relatively insensitive to verbal interference, consistent with the hypothesis that MA is a nonlinguistic format for exact numerical computation.

High performance nonvolatile memory devices based on Cu2-xSe nanowires

NASA Astrophysics Data System (ADS)

Wu, Chun-Yan; Wu, Yi-Liang; Wang, Wen-Jian; Mao, Dun; Yu, Yong-Qiang; Wang, Li; Xu, Jun; Hu, Ji-Gang; Luo, Lin-Bao

2013-11-01

We report on the rational synthesis of one-dimensional Cu2-xSe nanowires (NWs) via a solution method. Electrical analysis of Cu2-xSe NWs based memory device exhibits a stable and reproducible bipolar resistive switching behavior with a low set voltage (0.3-0.6 V), which can enable the device to write and erase data efficiently. Remarkably, the memory device has a record conductance switching ratio of 108, much higher than other devices ever reported. At last, a conducting filaments model is introduced to account for the resistive switching behavior. The totality of this study suggests that the Cu2-xSe NWs are promising building blocks for fabricating high-performance and low-consumption nonvolatile memory devices.

A memory efficient implementation scheme of Gauss error function in a Laguerre-Volterra network for neuroprosthetic devices

NASA Astrophysics Data System (ADS)

Li, Will X. Y.; Cui, Ke; Zhang, Wei

2017-04-01

Cognitive neural prosthesis is a manmade device which can be used to restore or compensate for lost human cognitive modalities. The generalized Laguerre-Volterra (GLV) network serves as a robust mathematical underpinning for the development of such prosthetic instrument. In this paper, a hardware implementation scheme of Gauss error function for the GLV network targeting reconfigurable platforms is reported. Numerical approximations are formulated which transform the computation of nonelementary function into combinational operations of elementary functions, and memory-intensive look-up table (LUT) based approaches can therefore be circumvented. The computational precision can be made adjustable with the utilization of an error compensation scheme, which is proposed based on the experimental observation of the mathematical characteristics of the error trajectory. The precision can be further customizable by exploiting the run-time characteristics of the reconfigurable system. Compared to the polynomial expansion based implementation scheme, the utilization of slice LUTs, occupied slices, and DSP48E1s on a Xilinx XC6VLX240T field-programmable gate array has decreased by 94.2%, 94.1%, and 90.0%, respectively. While compared to the look-up table based scheme, 1.0 ×1017 bits of storage can be spared under the maximum allowable error of 1.0 ×10-3 . The proposed implementation scheme can be employed in the study of large-scale neural ensemble activity and in the design and development of neural prosthetic device.

Temperature and field-dependent transport measurements in continuously tunable tantalum oxide memristors expose the dominant state variable

NASA Astrophysics Data System (ADS)

Graves, Catherine E.; Dávila, Noraica; Merced-Grafals, Emmanuelle J.; Lam, Si-Ty; Strachan, John Paul; Williams, R. Stanley

2017-03-01

Applications of memristor devices are quickly moving beyond computer memory to areas of analog and neuromorphic computation. These applications require the design of devices with different characteristics from binary memory, such as a large tunable range of conductance. A complete understanding of the conduction mechanisms and their corresponding state variable(s) is crucial for optimizing performance and designs in these applications. Here we present measurements of low bias I-V characteristics of 6 states in a Ta/ tantalum-oxide (TaOx)/Pt memristor spanning over 2 orders of magnitude in conductance and temperatures from 100 K to 500 K. Our measurements show that the 300 K device conduction is dominated by a temperature-insensitive current that varies with non-volatile memristor state, with an additional leakage contribution from a thermally-activated current channel that is nearly independent of the memristor state. We interpret these results with a parallel conduction model of Mott hopping and Schottky emission channels, fitting the voltage and temperature dependent experimental data for all memristor states with only two free parameters. The memristor conductance is linearly correlated with N, the density of electrons near EF participating in the Mott hopping conduction, revealing N to be the dominant state variable for low bias conduction in this system. Finally, we show that the Mott hopping sites can be ascribed to oxygen vacancies, where the local oxygen vacancy density responsible for critical hopping pathways controls the memristor conductance.

Xyce parallel electronic simulator : users' guide.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mei, Ting; Rankin, Eric Lamont; Thornquist, Heidi K.

2011-05-01

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). Note that this includes support for most popular parallel and serial computers; (2) Improved performance for all numerical kernels (e.g., time integrator, nonlinear and linear solvers) through state-of-the-artmore » algorithms and novel techniques. (3) Device models which are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only); and (4) Object-oriented code design and implementation using modern coding practices that ensure that the Xyce Parallel Electronic Simulator will be maintainable and extensible far into the future. Xyce is a parallel code in the most general sense of the phrase - a message passing parallel implementation - which allows it to run efficiently on the widest possible number of computing platforms. These include serial, shared-memory and distributed-memory parallel as well as heterogeneous platforms. Careful attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The development of Xyce provides a platform for computational research and development aimed specifically at the needs of the Laboratory. With Xyce, Sandia has an 'in-house' capability with which both new electrical (e.g., device model development) and algorithmic (e.g., faster time-integration methods, parallel solver algorithms) research and development can be performed. As a result, Xyce is a unique electrical simulation capability, designed to meet the unique needs of the laboratory.« less

Brownmillerite thin films as fast ion conductors for ultimate-performance resistance switching memory.

PubMed

Acharya, Susant Kumar; Jo, Janghyun; Raveendra, Nallagatlla Venkata; Dash, Umasankar; Kim, Miyoung; Baik, Hionsuck; Lee, Sangik; Park, Bae Ho; Lee, Jae Sung; Chae, Seung Chul; Hwang, Cheol Seong; Jung, Chang Uk

2017-07-27

An oxide-based resistance memory is a leading candidate to replace Si-based flash memory as it meets the emerging specifications for future memory devices. The non-uniformity in the key switching parameters and low endurance in conventional resistance memory devices are preventing its practical application. Here, a novel strategy to overcome the aforementioned challenges has been unveiled by tuning the growth direction of epitaxial brownmillerite SrFeO 2.5 thin films along the SrTiO 3 [111] direction so that the oxygen vacancy channels can connect both the top and bottom electrodes rather directly. The controlled oxygen vacancy channels help reduce the randomness of the conducting filament (CF). The resulting device displayed high endurance over 10 6 cycles, and a short switching time of ∼10 ns. In addition, the device showed very high uniformity in the key switching parameters for device-to-device and within a device. This work demonstrates a feasible example for improving the nanoscale device performance by controlling the atomic structure of a functional oxide layer.

Creating a transducer electronic datasheet using I2C serial EEPROM memory and PIC32-based microcontroller development board

NASA Astrophysics Data System (ADS)

Croitoru, Bogdan; Tulbure, Adrian; Abrudean, Mihail; Secara, Mihai

2015-02-01

The present paper describes a software method for creating / managing one type of Transducer Electronic Datasheet (TEDS) according to IEEE 1451.4 standard in order to develop a prototype of smart multi-sensor platform (with up to ten different analog sensors simultaneously connected) with Plug and Play capabilities over ETHERNET and Wi-Fi. In the experiments were used: one analog temperature sensor, one analog light sensor, one PIC32-based microcontroller development board with analog and digital I/O ports and other computing resources, one 24LC256 I2C (Inter Integrated Circuit standard) serial Electrically Erasable Programmable Read Only Memory (EEPROM) memory with 32KB available space and 3 bytes internal buffer for page writes (1 byte for data and 2 bytes for address). It was developed a prototype algorithm for writing and reading TEDS information to / from I2C EEPROM memories using the standard C language (up to ten different TEDS blocks coexisting in the same EEPROM device at once). The algorithm is able to write and read one type of TEDS: transducer information with standard TEDS content. A second software application, written in VB.NET platform, was developed in order to access the EEPROM sensor information from a computer through a serial interface (USB).

Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

2017-12-01

Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

General purpose programmable accelerator board

DOEpatents

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

76 FR 4375 - In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-25

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-683] In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... the United States after importation of certain MLC flash memory devices and products containing same...

Storing quantum information in spins and high-sensitivity ESR

NASA Astrophysics Data System (ADS)

Morton, John J. L.; Bertet, Patrice

2018-02-01

Quantum information, encoded within the states of quantum systems, represents a novel and rich form of information which has inspired new types of computers and communications systems. Many diverse electron spin systems have been studied with a view to storing quantum information, including molecular radicals, point defects and impurities in inorganic systems, and quantum dots in semiconductor devices. In these systems, spin coherence times can exceed seconds, single spins can be addressed through electrical and optical methods, and new spin systems with advantageous properties continue to be identified. Spin ensembles strongly coupled to microwave resonators can, in principle, be used to store the coherent states of single microwave photons, enabling so-called microwave quantum memories. We discuss key requirements in realising such memories, including considerations for superconducting resonators whose frequency can be tuned onto resonance with the spins. Finally, progress towards microwave quantum memories and other developments in the field of superconducting quantum devices are being used to push the limits of sensitivity of inductively-detected electron spin resonance. The state-of-the-art currently stands at around 65 spins per √{ Hz } , with prospects to scale down to even fewer spins.

Computational Analysis of Advanced Shape-Memory Alloy Devices Through a Robust Modeling Framework

NASA Astrophysics Data System (ADS)

Scalet, Giulia; Conti, Michele; Auricchio, Ferdinando

2017-06-01

Shape-memory alloys (SMA) provide significant advantages in various industrial fields, but their manufacturing and commercialization are currently hindered. This is attributed mainly to the poor knowledge of material behavior and the lack of standards in its mechanical characterization. SMA products are usually developed by trial-and-error testing to address specific design requirements, thus increasing costs and time. The development of simulation tools offers a possible solution to assist engineers and designers and allows to better understand SMA transformation phenomena. Accordingly, the purpose of the present paper is to numerically analyze and predict the response of spring-like actuators and septal occluders, which are industrial components exploiting the shape-memory and pseudoelastic properties of SMAs, respectively. The methodology includes two main stages: the implementation of the three-dimensional phenomenological model known as Souza- Auricchio model and the finite element modeling of the device. A discussion about the steps of each stage, as parameter identification and model generalizations, is provided. Validation results are presented through a comparison with the results of a performed experimental campaign. The framework proves good prediction capabilities and allows to reduce the number of experimental tests in the future.

Storing quantum information in spins and high-sensitivity ESR.

PubMed

Morton, John J L; Bertet, Patrice

2018-02-01

Quantum information, encoded within the states of quantum systems, represents a novel and rich form of information which has inspired new types of computers and communications systems. Many diverse electron spin systems have been studied with a view to storing quantum information, including molecular radicals, point defects and impurities in inorganic systems, and quantum dots in semiconductor devices. In these systems, spin coherence times can exceed seconds, single spins can be addressed through electrical and optical methods, and new spin systems with advantageous properties continue to be identified. Spin ensembles strongly coupled to microwave resonators can, in principle, be used to store the coherent states of single microwave photons, enabling so-called microwave quantum memories. We discuss key requirements in realising such memories, including considerations for superconducting resonators whose frequency can be tuned onto resonance with the spins. Finally, progress towards microwave quantum memories and other developments in the field of superconducting quantum devices are being used to push the limits of sensitivity of inductively-detected electron spin resonance. The state-of-the-art currently stands at around 65 spins per Hz, with prospects to scale down to even fewer spins. Copyright © 2017. Published by Elsevier Inc.

A Thrombus Generation Model Applied to Aneurysms Treated with Shape Memory Polymer Foam and Metal Coils

NASA Astrophysics Data System (ADS)

Horn, John; Ortega, Jason; Hartman, Jonathan; Maitland, Duncan

2015-11-01

To prevent their rupture, intracranial aneurysms are often treated with endovascular metal coils which fill the aneurysm sac and isolate it from the arterial flow. Despite its widespread use, this method can result in suboptimal outcomes leading to aneurysm recurrence. Recently, shape memory polymer foam has been proposed as an alternative aneurysm filler. In this work, a computational model has been developed to predict thrombus formation in blood in response to such cardiovascular implantable devices. The model couples biofluid and biochemical phenomena present as the blood interacts with a device and stimulates thrombus formation. This model is applied to simulations of both metal coil and shape memory polymer foam treatments within an idealized 2D aneurysm geometry. Using the predicted thrombus responses, the performance of these treatments is evaluated and compared. The results suggest that foam-treated aneurysms may fill more quickly and more completely with thrombus than coil-filled aneurysms, potentially leading to improved long-term aneurysm healing. This work was performed in part under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344.

A non-destructive crossbar architecture of multi-level memory-based resistor

NASA Astrophysics Data System (ADS)

Sahebkarkhorasani, Seyedmorteza

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6mum to 22 mum. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Carrier transport mechanisms of nonvolatile write-once-read-many-times memory devices with InP-ZnS core-shell nanoparticles embedded in a polymethyl methacrylate layer

NASA Astrophysics Data System (ADS)

Ham, Jung Hoon; Oh, Do Hyun; Cho, Sung Hwan; Jung, Jae Hun; Kim, Tae Whan; Ryu, Eui Dock; Kim, Sang Wook

2009-03-01

Current-voltage (I-V) curves at 300 K for Al/InP-ZnS nanoparticles embedded in a polymethyl methacrylate layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. From the I-V curves, the ON/OFF ratio for the device with InP-ZnS nanoparticles was significantly larger than that for the device without InP-ZnS nanoparticles, indicative of the existence of charge capture in the InP nanoparticles. The estimated retention time of the ON state for the WORM memory device was more than 10 years. The carrier transport mechanisms for the WORM memory devices are described by using several models to fit the experimental I-V data.

Method and apparatus for managing access to a memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik

A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operationalmore » memory layout reduces an amount of energy consumed by the processor to perform the computing job.« less

Giant Electroresistance in Edge Metal-Insulator-Metal Tunnel Junctions Induced by Ferroelectric Fringe Fields

PubMed Central

Jung, Sungchul; Jeon, Youngeun; Jin, Hanbyul; Lee, Jung-Yong; Ko, Jae-Hyeon; Kim, Nam; Eom, Daejin; Park, Kibog

2016-01-01

An enormous amount of research activities has been devoted to developing new types of non-volatile memory devices as the potential replacements of current flash memory devices. Theoretical device modeling was performed to demonstrate that a huge change of tunnel resistance in an Edge Metal-Insulator-Metal (EMIM) junction of metal crossbar structure can be induced by the modulation of electric fringe field, associated with the polarization reversal of an underlying ferroelectric layer. It is demonstrated that single three-terminal EMIM/Ferroelectric structure could form an active memory cell without any additional selection devices. This new structure can open up a way of fabricating all-thin-film-based, high-density, high-speed, and low-power non-volatile memory devices that are stackable to realize 3D memory architecture. PMID:27476475

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

Resonant tunneling based graphene quantum dot memristors.

PubMed

Pan, Xuan; Skafidas, Efstratios

2016-12-08

In this paper, we model two-terminal all graphene quantum dot (GQD) based resistor-type memory devices (memristors). The resistive switching is achieved by resonant electron tunneling. We show that parallel GQDs can be used to create multi-state memory circuits. The number of states can be optimised with additional voltage sources, whilst the noise margin for each state can be controlled by appropriately choosing the branch resistance. A three-terminal GQD device configuration is also studied. The addition of an isolated gate terminal can be used to add further or modify the states of the memory device. The proposed devices provide a promising route towards volatile memory devices utilizing only atomically thin two-dimensional graphene.

Molecular controlled of quantum nano systems

NASA Astrophysics Data System (ADS)

Paltiel, Yossi

2014-03-01

A century ago quantum mechanics created a conceptual revolution whose fruits are now seen in almost any aspect of our day-to-day life. Lasers, transistors and other solid state and optical devices represent the core technology of current computers, memory devices and communication systems. However, all these examples do not exploit fully the quantum revolution as they do not take advantage of the coherent wave-like properties of the quantum wave function. Controlled coherent system and devices at ambient temperatures are challenging to realize. We are developing a novel nano tool box with control coupling between the quantum states and the environment. This tool box that combines nano particles with organic molecules enables the integration of quantum properties with classical existing devices at ambient temperatures. The nano particles generate the quantum states while the organic molecules control the coupling and therefore the energy, charge, spin, or quasi particle transfer between the layers. Coherent effects at ambient temperatures can be measured in the strong coupling regime. In the talk I will present our nano tool box and show studies of charge transfer, spin transfer and energy transfer in the hybrid layers as well as collective transfer phenomena. These enable the realization of room temperature operating quantum electro optical devices. For example I will present in details, our recent development of a new type of chiral molecules based magnetless universal memory exploiting selective spin transfer.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Weaves as an Interconnection Fabric for ASIM's and Nanosatellites

NASA Technical Reports Server (NTRS)

Gorlick, Michael M.

1995-01-01

Many of the micromachines under consideration require computer support, indeed, one of the appeals of this technology is the ability to intermix mechanical, optical, analog, and digital devices on the same substrate. The amount of computer power is rarely an issue, the sticking point is the complexity of the software required to make effective use of these devices. Micromachines are the nano-technologist's equivalent of 'golden screws'. In other words, they will be piece parts in larger assemblages. For example, a nano-satellite may be composed of stacked silicon wafers where each wafer contains hundreds to thousands of micromachines, digital controllers, general purpose computers, memories, and high-speed bus interconnects. Comparatively few of these devices will be custom designed, most will be stock parts selected from libraries and catalogs. The novelty will lie in the interconnections. For example, a digital accelerometer may be a component part in an adaptive suspension, a monitoring element embedded in the wrapper of a package, or a portion of the smart skin of a launch vehicle. In each case, this device must inter-operate with other devices and probes for the purposes of command, control, and communication. We propose a software technology called 'weaves' that will permit large collections of micromachines and their attendant computers to freely intercommunicate while preserving modularity, transparency, and flexibility. Weaves are composed of networks of communicating software components. The network, and the components comprising it, may be changed even while the software, and the devices it controls, are executing. This unusual degree of software plasticity permits micromachines to dynamically adapt the software to changing conditions and allows system engineers to rapidly and inexpensively develop special purpose software by assembling stock software components in custom configurations.

A Fast lattice-based polynomial digital signature system for m-commerce

NASA Astrophysics Data System (ADS)

Wei, Xinzhou; Leung, Lin; Anshel, Michael

2003-01-01

The privacy and data integrity are not guaranteed in current wireless communications due to the security hole inside the Wireless Application Protocol (WAP) version 1.2 gateway. One of the remedies is to provide an end-to-end security in m-commerce by applying application level security on top of current WAP1.2. The traditional security technologies like RSA and ECC applied on enterprise's server are not practical for wireless devices because wireless devices have relatively weak computation power and limited memory compared with server. In this paper, we developed a lattice based polynomial digital signature system based on NTRU's Polynomial Authentication and Signature Scheme (PASS), which enabled the feasibility of applying high-level security on both server and wireless device sides.

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Preface to ISIF 2009 special issue of Journal of Applied Physics : science and technology of integrated functionalities.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Auciello, O.; Dey, S.; Paz de Araujo, C.

2011-05-01

The science and technology of ferroelectric thin films and their applications have attracted many researchers and experienced tremendous progress in the past 20 years. The recent worldwide increase in commercial applications of ferroelectric devices such as smart cards based on nonvolatile ferroelectric random access memories is a symbol of both the maturity and the acceptance of the technology. The 21st International Symposium on Integrated Ferroelectrics (ISIF 2009), held on September 22 to October 2, 2009 in Colorado Springs, CO, provided a forum for the academic and national laboratories research community and industry to present and share their new findings, achievements,more » and opinions on integrated ferroelectrics and their applications. The International Symposium on Integrated Ferroelectrics hosted the ISIF 2009. This was the first year where the ISIF held the conference in its new format under the name of International Symposium on Integrated Functionalities. The General Chairs of the ISIF in consultation with the Advisory Board and the ISIF community decided to revise the focus of the conference in order to broaden the scope to the science and technology of multifunctional materials and devices. This decision was taken in view that a new paradigm in materials, materials integration, and devices is emerging with a view to the development of a new generation of micro- and nanoscale multifunctional devices. The program included three plenary presentations on diverse topics such as 'The Role of Nonvolatile Memory in Ubiquitous Computing,' 'Ferroelectrics and High Density Memory Technology,' 'Nanoscale Ferroelectrics and Interfaces: Size Effects,' four tutorial lectures on diverse topics, such as 'Magnetic Memory Applications,' 'Ferroelectrics and Ferroelectric Devices,' 'Challenges for High-K Dielectrics on High Mobility Channels,' 'Solar Cell Materials,' one poster session, and eight oral sessions. Thanks to the great efforts made by the ISIF organization committee and the session chairs, the conference successfully achieved its objectives and the work presented reflected very well the most recent advances of integrated ferroelectrics and their applications, as well as advances in other areas related to the new theme of Integrated Functionalities. Many aspects of ferroelectric, piezoelectric, high-K dielectric, magnetic, and phase change materials, including the science and technology of these materials in thin film form, integration with other thin film materials (metals or oxide electrodes), and fabrication of micro- and nanostructures based on these heterostructure layers, and device architecture and physics, were addressed from the experimental point of view. Work on theory and computer simulations of the mentioned materials and devices were discussed also with a view to the promising applications to multifunctional devices. In addition, the ISIF 2009 featured discussions of alternative nonvolatile memory concepts and materials, such as phase change memories, research on multiferroics and magnetoelectric materials, ferroelectric photovoltaics, and new directions on the science of perovskites such as biomolecular/polarizable interfaces, and bio-ferroelectric and other oxide interfaces. Following the standard submission and peer review process of Journal of Applied Physics, the selected papers presented in ISIF 2009 in Colorado Springs are published in this special issue. We believe that the papers in this special issue represent the forefront contributions to ISIF 2009 in the various areas of fundamental and applied science of integrated ferroelectrics and functionalities and their applications. We would like to take this opportunity to thank the following organizations and companies for their support and sponsorship for ISIF 2009, namely: Aixact Systems GMBH, Radiant Technologies, Symetrix Corporation, and Taylor and Francis Publishers. We would also like to thank the conference and session chairs, advisory and organizing committee members for their hard work that resulted in a very successful ISIF 2009, now in its new future-looking modality of Integrated Functionalities.« less

Biomaterial-based Memory Device Development by Conducting Metallic DNA

DTIC Science & Technology

2013-05-28

time. Therefore, we have created a multiple-states memory system . This is the first multi-states resistance memory device by using bio-nanowire of the...world. Based on this achievement, logic device and application will be developed in the near future, too. Moreover, by using Ni-DNA detection system ...ions in DNA can change the resistance of Ni-DNA by applying different polar bias and time. Therefore, we have created a multiple-states memory system

Discrete-state phasor neural networks

NASA Astrophysics Data System (ADS)

Noest, André J.

1988-08-01

An associative memory network with local variables assuming one of q equidistant positions on the unit circle (q-state phasors) is introduced, and its recall behavior is solved exactly for any q when the interactions are sparse and asymmetric. Such models can describe natural or artifical networks of (neuro-)biological, chemical, or electronic limit-cycle oscillators with q-fold instead of circular symmetry, or similar optical computing devices using a phase-encoded data representation.

Smart Cards and remote entrusting

NASA Astrophysics Data System (ADS)

Aussel, Jean-Daniel; D'Annoville, Jerome; Castillo, Laurent; Durand, Stephane; Fabre, Thierry; Lu, Karen; Ali, Asad

Smart cards are widely used to provide security in end-to-end communication involving servers and a variety of terminals, including mobile handsets or payment terminals. Sometime, end-to-end server to smart card security is not applicable, and smart cards must communicate directly with an application executing on a terminal, like a personal computer, without communicating with a server. In this case, the smart card must somehow trust the terminal application before performing some secure operation it was designed for. This paper presents a novel method to remotely trust a terminal application from the smart card. For terminals such as personal computers, this method is based on an advanced secure device connected through the USB and consisting of a smart card bundled with flash memory. This device, or USB dongle, can be used in the context of remote untrusting to secure portable applications conveyed in the dongle flash memory. White-box cryptography is used to set the secure channel and a mechanism based on thumbprint is described to provide external authentication when session keys need to be renewed. Although not as secure as end-to-end server to smart card security, remote entrusting with smart cards is easy to deploy for mass-market applications and can provide a reasonable level of security.

Splash, pop, sizzle: Information processing with phononic computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sklan, Sophia R.

2015-05-15

Phonons, the quanta of mechanical vibration, are important to the transport of heat and sound in solid materials. Recent advances in the fundamental control of phonons (phononics) have brought into prominence the potential role of phonons in information processing. In this review, the many directions of realizing phononic computing and information processing are examined. Given the relative similarity of vibrational transport at different length scales, the related fields of acoustic, phononic, and thermal information processing are all included, as are quantum and classical computer implementations. Connections are made between the fundamental questions in phonon transport and phononic control and themore » device level approach to diodes, transistors, memory, and logic. .« less

Electro-optical processing of phased array data

NASA Technical Reports Server (NTRS)

Casasent, D.

1973-01-01

An on-line spatial light modulator for application as the input transducer for a real-time optical data processing system is described. The use of such a device in the analysis and processing of radar data in real time is reported. An interface from the optical processor to a control digital computer was designed, constructed, and tested. The input transducer, optical system, and computer interface have been operated in real time with real time radar data with the input data returns recorded on the input crystal, processed by the optical system, and the output plane pattern digitized, thresholded, and outputted to a display and storage in the computer memory. The correlation of theoretical and experimental results is discussed.

Space and power efficient hybrid counters array

DOEpatents

Gara, Alan G [Mount Kisco, NY; Salapura, Valentina [Chappaqua, NY

2009-05-12

A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.

Space and power efficient hybrid counters array

DOEpatents

Gara, Alan G.; Salapura, Valentina

2010-03-30

A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.

The Science of Computing: Virtual Memory

NASA Technical Reports Server (NTRS)

Denning, Peter J.

1986-01-01

In the March-April issue, I described how a computer's storage system is organized as a hierarchy consisting of cache, main memory, and secondary memory (e.g., disk). The cache and main memory form a subsystem that functions like main memory but attains speeds approaching cache. What happens if a program and its data are too large for the main memory? This is not a frivolous question. Every generation of computer users has been frustrated by insufficient memory. A new line of computers may have sufficient storage for the computations of its predecessor, but new programs will soon exhaust its capacity. In 1960, a longrange planning committee at MIT dared to dream of a computer with 1 million words of main memory. In 1985, the Cray-2 was delivered with 256 million words. Computational physicists dream of computers with 1 billion words. Computer architects have done an outstanding job of enlarging main memories yet they have never kept up with demand. Only the shortsighted believe they can.

An enhanced technique for mobile cloudlet offloading with reduced computation using compression in the cloud

NASA Astrophysics Data System (ADS)

Moro, A. C.; Nadesh, R. K.

2017-11-01

The cloud computing paradigm has transformed the way we do business in today’s world. Services on cloud have come a long way since just providing basic storage or software on demand. One of the fastest growing factor in this is mobile cloud computing. With the option of offloading now available to mobile users, mobile users can offload entire applications onto cloudlets. With the problems regarding availability and limited-storage capacity of these mobile cloudlets, it becomes difficult to decide for the mobile user when to use his local memory or the cloudlets. Hence, we take a look at a fast algorithm that decides whether the mobile user should go for cloudlet or rely on local memory based on an offloading probability. We have partially implemented the algorithm which decides whether the task can be carried out locally or given to a cloudlet. But as it becomes a burden on the mobile devices to perform the complete computation, so we look to offload this on to a cloud in our paper. Also further we use a file compression technique before sending the file onto the cloud to further reduce the load.

Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer

DOEpatents

Bhanot, Gyan V [Princeton, NJ; Chen, Dong [Croton-On-Hudson, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

2012-01-10

The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via "all-to-all" distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates efficient utilization of the network thereby efficiently implementing the multidimensional FFT. The "all-to-all" re-distribution of array elements is further efficiently implemented in applications other than the multidimensional FFT on the distributed-memory parallel supercomputer.

Efficient implementation of a multidimensional fast fourier transform on a distributed-memory parallel multi-node computer

DOEpatents

Bhanot, Gyan V [Princeton, NJ; Chen, Dong [Croton-On-Hudson, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

2008-01-01

The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via "all-to-all" distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates efficient utilization of the network thereby efficiently implementing the multidimensional FFT. The "all-to-all" re-distribution of array elements is further efficiently implemented in applications other than the multidimensional FFT on the distributed-memory parallel supercomputer.

Electrical studies of Ge4Sb1Te5 devices for memory applications

NASA Astrophysics Data System (ADS)

Sangeetha, B. G.; Shylashree, N.

2018-05-01

In this paper, the Ge4Sb1Te5 thin film device preparation and electrical studies for memory devices were carried out. The device was deposited using vapor-evaporation technique. RESET to SET state switching was shown using current-voltage characterization. The current-voltage characterization shows the switching between SET to RESET state and it was found that it requires a low energy for transition. Switching between amorphous to crystalline nature was studied using resistance-voltage characteristics. The endurance showed the effective use of this composition for memory device.

Intermediate memory devices

NASA Technical Reports Server (NTRS)

Basalayev, G. V.; Kmet, A. B.; Rakov, M. A.; Tarasevich, V. A.

1974-01-01

Several methods of transfer and processing of data whose practical implementation requires operational memory devices are described. Devices incorporating multistable elements are proposed and their main parameters are given. The possibility of using the proposed devices for storing information for transmission in space radio communications channels is examined.

Charge Carrier Transport Mechanism Based on Stable Low Voltage Organic Bistable Memory Device.

PubMed

Ramana, V V; Moodley, M K; Kumar, A B V Kiran; Kannan, V

2015-05-01

A solution processed two terminal organic bistable memory device was fabricated utilizing films of polymethyl methacrylate PMMA/ZnO/PMMA on top of ITO coated glass. Electrical characterization of the device structure showed that the two terminal device exhibited favorable switching characteristics with an ON/OFF ratio greater than 1 x 10(4) when the voltage was swept between - 2 V and +3 V. The device maintained its state after removal of the bias voltage. The device did not show degradation after a 1-h retention test at 120 degrees C. The memory functionality was consistent even after fifty cycles of operation. The charge transport switching mechanism is discussed on the basis of carrier transport mechanism and our analysis of the data shows that the charge carrier trans- port mechanism of the device during the writing process can be explained by thermionic emission (TE) and space-charge-limited-current (SCLC) mechanism models while erasing process could be explained by the FN tunneling mechanism. This demonstration provides a class of memory devices with the potential for low-cost, low-power consumption applications, such as a digital memory cell.

High Density Memory Based on Quantum Device Technology

NASA Technical Reports Server (NTRS)

vanderWagt, Paul; Frazier, Gary; Tang, Hao

1995-01-01

We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baudry, Laurent; Lukyanchuk, Igor; Vinokur, Valerii M.

Here, the tunability of electrical polarization in ferroelectrics is instrumental to their applications in information-storage devices. The existing ferroelectric memory cells are based on the two-level storage capacity with the standard binary logics. However, the latter have reached its fundamental limitations. Here we propose ferroelectric multibit cells (FMBC) utilizing the ability of multiaxial ferroelectric materials to pin the polarization at a sequence of the multistable states. Employing the catastrophe theory principles we show that these states are symmetry-protected against the information loss and thus realize novel topologically-controlled access memory (TAM). Our findings enable developing a platform for the emergent many-valuedmore » non-Boolean information technology and target challenges posed by needs of quantum and neuromorphic computing.« less

Optical backplane interconnect switch for data processors and computers

NASA Technical Reports Server (NTRS)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Workflow of the Grover algorithm simulation incorporating CUDA and GPGPU

NASA Astrophysics Data System (ADS)

Lu, Xiangwen; Yuan, Jiabin; Zhang, Weiwei

2013-09-01

The Grover quantum search algorithm, one of only a few representative quantum algorithms, can speed up many classical algorithms that use search heuristics. No true quantum computer has yet been developed. For the present, simulation is one effective means of verifying the search algorithm. In this work, we focus on the simulation workflow using a compute unified device architecture (CUDA). Two simulation workflow schemes are proposed. These schemes combine the characteristics of the Grover algorithm and the parallelism of general-purpose computing on graphics processing units (GPGPU). We also analyzed the optimization of memory space and memory access from this perspective. We implemented four programs on CUDA to evaluate the performance of schemes and optimization. Through experimentation, we analyzed the organization of threads suited to Grover algorithm simulations, compared the storage costs of the four programs, and validated the effectiveness of optimization. Experimental results also showed that the distinguished program on CUDA outperformed the serial program of libquantum on a CPU with a speedup of up to 23 times (12 times on average), depending on the scale of the simulation.

Blood leakage detection during dialysis therapy based on fog computing with array photocell sensors and heteroassociative memory model

PubMed Central

Wu, Jian-Xing; Huang, Ping-Tzan; Li, Chien-Ming

2018-01-01

Blood leakage and blood loss are serious life-threatening complications occurring during dialysis therapy. These events have been of concerns to both healthcare givers and patients. More than 40% of adult blood volume can be lost in just a few minutes, resulting in morbidities and mortality. The authors intend to propose the design of a warning tool for the detection of blood leakage/blood loss during dialysis therapy based on fog computing with an array of photocell sensors and heteroassociative memory (HAM) model. Photocell sensors are arranged in an array on a flexible substrate to detect blood leakage via the resistance changes with illumination in the visible spectrum of 500–700 nm. The HAM model is implemented to design a virtual alarm unit using electricity changes in an embedded system. The proposed warning tool can indicate the risk level in both end-sensing units and remote monitor devices via a wireless network and fog/cloud computing. The animal experimental results (pig blood) will demonstrate the feasibility. PMID:29515815

Blood leakage detection during dialysis therapy based on fog computing with array photocell sensors and heteroassociative memory model.

PubMed

Wu, Jian-Xing; Huang, Ping-Tzan; Lin, Chia-Hung; Li, Chien-Ming

2018-02-01

Blood leakage and blood loss are serious life-threatening complications occurring during dialysis therapy. These events have been of concerns to both healthcare givers and patients. More than 40% of adult blood volume can be lost in just a few minutes, resulting in morbidities and mortality. The authors intend to propose the design of a warning tool for the detection of blood leakage/blood loss during dialysis therapy based on fog computing with an array of photocell sensors and heteroassociative memory (HAM) model. Photocell sensors are arranged in an array on a flexible substrate to detect blood leakage via the resistance changes with illumination in the visible spectrum of 500-700 nm. The HAM model is implemented to design a virtual alarm unit using electricity changes in an embedded system. The proposed warning tool can indicate the risk level in both end-sensing units and remote monitor devices via a wireless network and fog/cloud computing. The animal experimental results (pig blood) will demonstrate the feasibility.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

A synaptic device built in one diode-one resistor (1D-1R) architecture with intrinsic SiOx-based resistive switching memory

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Pan, Chih-Hung; Chang, Kuan-Chang; Tsai, Tsung-Ming; Chang, Ting-Chang; Sze, Simon M.; Lee, Jack C.

2016-04-01

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO2-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)2 defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology.

The Spin Torque Lego - from spin torque nano-devices to advanced computing architectures

NASA Astrophysics Data System (ADS)

Grollier, Julie

2013-03-01

Spin transfer torque (STT), predicted in 1996, and first observed around 2000, brought spintronic devices to the realm of active elements. A whole class of new devices, based on the combined effects of STT for writing and Giant Magneto-Resistance or Tunnel Magneto-Resistance for reading has emerged. The second generation of MRAMs, based on spin torque writing : the STT-RAM, is under industrial development and should be out on the market in three years. But spin torque devices are not limited to binary memories. We will rapidly present how the spin torque effect also allows to implement non-linear nano-oscillators, spin-wave emitters, controlled stochastic devices and microwave nano-detectors. What is extremely interesting is that all these functionalities can be obtained using the same materials, the exact same stack, simply by changing the device geometry and its bias conditions. So these different devices can be seen as Lego bricks, each brick with its own functionality. During this talk, I will show how spin torque can be engineered to build new bricks, such as the Spintronic Memristor, an artificial magnetic nano-synapse. I will then give hints on how to assemble these bricks in order to build novel types of computing architectures, with a special focus on neuromorphic circuits. Financial support by the European Research Council Starting Grant NanoBrain (ERC 2010 Stg 259068) is acknowledged.

Ferroelectric Memory Devices and a Proposed Standardized Test System Design

DTIC Science & Technology

1992-06-01

positive clock transition. This provides automatic data protection in case of power loss. The device is being evaluated for applications such as automobile ...systems requiring nonvolatile memory and as these systems become more complex, the demand for reprogrammable nonvolatile memory increases. The...complexity and cost in making conventional nonvolatile memory reprogrammable also increases, so the potential for using ferroelectric memory as a replacement

Guide wire extension for shape memory polymer occlusion removal devices

DOEpatents

Maitland, Duncan J [Pleasant Hill, CA; Small, IV, Ward; Hartman, Jonathan [Sacramento, CA

2009-11-03

A flexible extension for a shape memory polymer occlusion removal device. A shape memory polymer instrument is transported through a vessel via a catheter. A flexible elongated unit is operatively connected to the distal end of the shape memory polymer instrument to enhance maneuverability through tortuous paths en route to the occlusion.

76 FR 80964 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-12-27

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-821] Certain Dynamic Random Access Memory... importation, and the sale within the United States after importation of certain dynamic random access memory... certain dynamic random access memory devices, and products containing same that infringe one or more of...

Electronic device aspects of neural network memories

NASA Technical Reports Server (NTRS)

Lambe, J.; Moopenn, A.; Thakoor, A. P.

1985-01-01

The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

Solution-processed flexible NiO resistive random access memory device

NASA Astrophysics Data System (ADS)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

2018-01-01

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies.

PubMed

Kim, Jeremie S; Senol Cali, Damla; Xin, Hongyi; Lee, Donghyuk; Ghose, Saugata; Alser, Mohammed; Hassan, Hasan; Ergin, Oguz; Alkan, Can; Mutlu, Onur

2018-05-09

Seed location filtering is critical in DNA read mapping, a process where billions of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to identify genomic variants of the donor. State-of-the-art read mappers 1) quickly generate possible mapping locations for seeds (i.e., smaller segments) within each read, 2) extract reference sequences at each of the mapping locations, and 3) check similarity between each read and its associated reference sequences with a computationally-expensive algorithm (i.e., sequence alignment) to determine the origin of the read. A seed location filter comes into play before alignment, discarding seed locations that alignment would deem a poor match. The ideal seed location filter would discard all poor match locations prior to alignment such that there is no wasted computation on unnecessary alignments. We propose a novel seed location filtering algorithm, GRIM-Filter, optimized to exploit 3D-stacked memory systems that integrate computation within a logic layer stacked under memory layers, to perform processing-in-memory (PIM). GRIM-Filter quickly filters seed locations by 1) introducing a new representation of coarse-grained segments of the reference genome, and 2) using massively-parallel in-memory operations to identify read presence within each coarse-grained segment. Our evaluations show that for a sequence alignment error tolerance of 0.05, GRIM-Filter 1) reduces the false negative rate of filtering by 5.59x-6.41x, and 2) provides an end-to-end read mapper speedup of 1.81x-3.65x, compared to a state-of-the-art read mapper employing the best previous seed location filtering algorithm. GRIM-Filter exploits 3D-stacked memory, which enables the efficient use of processing-in-memory, to overcome the memory bandwidth bottleneck in seed location filtering. We show that GRIM-Filter significantly improves the performance of a state-of-the-art read mapper. GRIM-Filter is a universal seed location filter that can be applied to any read mapper. We hope that our results provide inspiration for new works to design other bioinformatics algorithms that take advantage of emerging technologies and new processing paradigms, such as processing-in-memory using 3D-stacked memory devices.

Write once read many memory device from Tris-8 (-hydroxyquinoline) aluminum and Indium tin oxide nano particles

NASA Astrophysics Data System (ADS)

Aneesh, J.; Predeep, P.

2011-10-01

Consequent to the fast increase in data storage requirements new materials and device structures are explored in a war footing. Organic memory devices are attracting lot of interest among the researchers and are becoming a hot topic of investigations. This study is an attempt to develop a tri-layer organic memory device using indium tin oxide (ITO) nanoparticles as charge trapping middle layer between tris-8(-hydroxyquinoline)aluminum (Alq3) layers employing spin coating technique. Device switching is studied by applying a current-voltage (I-V) sweep. On increasing the applied bias the device switched from the initial high resistance (OFF) state to a low resistance (ON) state at a switch on voltage of around 4 V. ON/OFF ratio is of the order of 100 at a read voltage of 2 V. The device is found to remain in the low resistance state on further scans, showing the applicability of this device as a write once read many times (WORM) memory.

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

Paging memory from random access memory to backing storage in a parallel computer

DOEpatents

Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

2013-05-21

Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

A Malicious Pattern Detection Engine for Embedded Security Systems in the Internet of Things

PubMed Central

Oh, Doohwan; Kim, Deokho; Ro, Won Woo

2014-01-01

With the emergence of the Internet of Things (IoT), a large number of physical objects in daily life have been aggressively connected to the Internet. As the number of objects connected to networks increases, the security systems face a critical challenge due to the global connectivity and accessibility of the IoT. However, it is difficult to adapt traditional security systems to the objects in the IoT, because of their limited computing power and memory size. In light of this, we present a lightweight security system that uses a novel malicious pattern-matching engine. We limit the memory usage of the proposed system in order to make it work on resource-constrained devices. To mitigate performance degradation due to limitations of computation power and memory, we propose two novel techniques, auxiliary shifting and early decision. Through both techniques, we can efficiently reduce the number of matching operations on resource-constrained systems. Experiments and performance analyses show that our proposed system achieves a maximum speedup of 2.14 with an IoT object and provides scalable performance for a large number of patterns. PMID:25521382

Organic memory device with self-assembly monolayered aptamer conjugated nanoparticles

NASA Astrophysics Data System (ADS)

Oh, Sewook; Kim, Minkeun; Kim, Yejin; Jung, Hunsang; Yoon, Tae-Sik; Choi, Young-Jin; Jung Kang, Chi; Moon, Myeong-Ju; Jeong, Yong-Yeon; Park, In-Kyu; Ho Lee, Hyun

2013-08-01

An organic memory structure using monolayered aptamer conjugated gold nanoparticles (Au NPs) as charge storage nodes was demonstrated. Metal-pentacene-insulator-semiconductor device was adopted for the non-volatile memory effect through self assembly monolayer of A10-aptamer conjugated Au NPs, which was formed on functionalized insulator surface with prostate-specific membrane antigen protein. The capacitance versus voltage (C-V) curves obtained for the monolayered Au NPs capacitor exhibited substantial flat-band voltage shift (ΔVFB) or memory window of 3.76 V under (+/-)7 V voltage sweep. The memory device format can be potentially expanded to a highly specific capacitive sensor for the aptamer-specific biomolecule detection.

Terahertz electrical writing speed in an antiferromagnetic memory

PubMed Central

Kašpar, Zdeněk; Campion, Richard P.; Baumgartner, Manuel; Sinova, Jairo; Kužel, Petr; Müller, Melanie; Kampfrath, Tobias

2018-01-01

The speed of writing of state-of-the-art ferromagnetic memories is physically limited by an intrinsic gigahertz threshold. Recently, realization of memory devices based on antiferromagnets, in which spin directions periodically alternate from one atomic lattice site to the next has moved research in an alternative direction. We experimentally demonstrate at room temperature that the speed of reversible electrical writing in a memory device can be scaled up to terahertz using an antiferromagnet. A current-induced spin-torque mechanism is responsible for the switching in our memory devices throughout the 12-order-of-magnitude range of writing speeds from hertz to terahertz. Our work opens the path toward the development of memory-logic technology reaching the elusive terahertz band. PMID:29740601

Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

PubMed Central

Stöckel, Andreas; Jenzen, Christoph; Thies, Michael; Rückert, Ulrich

2017-01-01

Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP). Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output. PMID:28878642

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing

NASA Astrophysics Data System (ADS)

Rao, Feng; Ding, Keyuan; Zhou, Yuxing; Zheng, Yonghui; Xia, Mengjiao; Lv, Shilong; Song, Zhitang; Feng, Songlin; Ronneberger, Ider; Mazzarello, Riccardo; Zhang, Wei; Ma, Evan

2017-12-01

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge2Sb2Te5). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb2Te3) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Electrical reliability, multilevel data storage and mechanical stability of MoS2-PMMA nanocomposite-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Bhattacharjee, Snigdha; Sarkar, Pranab Kumar; Prajapat, Manoj; Roy, Asim

2017-07-01

Molybdenum disulfide (MoS2) is of great interest for its applicability in various optoelectronic devices. Here we report the resistive switching properties of polymethylmethacrylate embedding MoS2 nano-crystals. The devices are developed on an ITO-coated PET substrate with copper as the top electrode. Systematic evaluation of resistive switching parameters, on the basis of MoS2 content, suggests non-volatile memory characteristics. A decent ON/OFF ratio, high retention time and long endurance of 3  ×  103, 105 s and 105 cycles are respectively recorded in a device with 1 weight percent (wt%) of MoS2. The bending cyclic measurements confirm the flexibility of the memory devices with good electrical reliability as well as mechanical stability. In addition, multilevel storage has been demonstrated by controlling the current compliance and span of voltage sweeping in the memory device.

Cognitive memory.

PubMed

Widrow, Bernard; Aragon, Juan Carlos

2013-05-01

Regarding the workings of the human mind, memory and pattern recognition seem to be intertwined. You generally do not have one without the other. Taking inspiration from life experience, a new form of computer memory has been devised. Certain conjectures about human memory are keys to the central idea. The design of a practical and useful "cognitive" memory system is contemplated, a memory system that may also serve as a model for many aspects of human memory. The new memory does not function like a computer memory where specific data is stored in specific numbered registers and retrieval is done by reading the contents of the specified memory register, or done by matching key words as with a document search. Incoming sensory data would be stored at the next available empty memory location, and indeed could be stored redundantly at several empty locations. The stored sensory data would neither have key words nor would it be located in known or specified memory locations. Sensory inputs concerning a single object or subject are stored together as patterns in a single "file folder" or "memory folder". When the contents of the folder are retrieved, sights, sounds, tactile feel, smell, etc., are obtained all at the same time. Retrieval would be initiated by a query or a prompt signal from a current set of sensory inputs or patterns. A search through the memory would be made to locate stored data that correlates with or relates to the prompt input. The search would be done by a retrieval system whose first stage makes use of autoassociative artificial neural networks and whose second stage relies on exhaustive search. Applications of cognitive memory systems have been made to visual aircraft identification, aircraft navigation, and human facial recognition. Concerning human memory, reasons are given why it is unlikely that long-term memory is stored in the synapses of the brain's neural networks. Reasons are given suggesting that long-term memory is stored in DNA or RNA. Neural networks are an important component of the human memory system, and their purpose is for information retrieval, not for information storage. The brain's neural networks are analog devices, subject to drift and unplanned change. Only with constant training is reliable action possible. Good training time is during sleep and while awake and making use of one's memory. A cognitive memory is a learning system. Learning involves storage of patterns or data in a cognitive memory. The learning process for cognitive memory is unsupervised, i.e. autonomous. Copyright © 2013 Elsevier Ltd. All rights reserved.

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2014-12-08

Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative ofmore » the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.« less

Securing resource constraints embedded devices using elliptic curve cryptography

NASA Astrophysics Data System (ADS)

Tam, Tony; Alfasi, Mohamed; Mozumdar, Mohammad

2014-06-01

The use of smart embedded device has been growing rapidly in recent time because of miniaturization of sensors and platforms. Securing data from these embedded devices is now become one of the core challenges both in industry and research community. Being embedded, these devices have tight constraints on resources such as power, computation, memory, etc. Hence it is very difficult to implement traditional Public Key Cryptography (PKC) into these resource constrained embedded devices. Moreover, most of the public key security protocols requires both public and private key to be generated together. In contrast with this, Identity Based Encryption (IBE), a public key cryptography protocol, allows a public key to be generated from an arbitrary string and the corresponding private key to be generated later on demand. While IBE has been actively studied and widely applied in cryptography research, conventional IBE primitives are also computationally demanding and cannot be efficiently implemented on embedded system. Simplified version of the identity based encryption has proven its competence in being robust and also satisfies tight budget of the embedded platform. In this paper, we describe the choice of several parameters for implementing lightweight IBE in resource constrained embedded sensor nodes. Our implementation of IBE is built using elliptic curve cryptography (ECC).

DOE-EPSCoR Final Report Period: September 1, 2008- August 31, 2016

DOE Office of Scientific and Technical Information (OSTI.GOV)

Katiyar, Ram; Gomez, M.; Morell, G.

In this project, multifunctional nanostructured spintronic and magnetoelectric materials were investigated by experimental and computational efforts for applications in energy efficient electronic systems that integrate functionalities and thus have the potential to enable a new generation of faster responding devices and increased integration densities. The team systematically investigated transition metal (TM)-doped ZnO nanostructures, silicide nanorods, magnetoelectric oxides, and ferroelectric/ferromagnetic heterostructures. In what follows, we report the progress made by researchers during the above period in developing and understanding of 1) Spintronics nanostructures; 2) Resistive switching phenomenon in oxides for memory devices; 3) Magnetoelectric multiferroics; 4) Novel high-k gate oxides formore » logic devices; 5) Two dimensional (2D) materials; and 6) Theoretical studies in the above fields.« less

Nanogap-Engineerable Electromechanical System for Ultralow Power Memory.

PubMed

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei; Chu, Weiguo; Zhou, Haiqing; Sun, Lianfeng

2018-02-01

Nanogap engineering of low-dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub-5 nm nanogaped single-walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10 -19 J bit -1 ), ON/OFF ratio of 10 5 , stable switching ON operations, and over 30 h retention time in ambient conditions.

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

NASA Astrophysics Data System (ADS)

Valentini, L.; Cardinali, M.; Fortunati, E.; Kenny, J. M.

2014-10-01

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

Azurin/CdSe-ZnS-Based Bio-Nano Hybrid Structure for Nanoscale Resistive Memory Device.

PubMed

Yagati, Ajay Kumar; Lee, Taek; Choi, Jeong-Woo

2017-07-15

In the present study, we propose a method for bio-nano hybrid formation by coupling a redox metalloprotein, Azurin, with CdSe-ZnS quantum dot for the development of a nanoscale resistive memory device. The covalent interaction between the two nanomaterials enables a strong and effective binding to form an azurin/CdSe-ZnS hybrid, and also enabled better controllability to couple with electrodes to examine the memory function properties. Morphological and optical properties were performed to confirm both hybrid formations and also their individual components. Current-Voltage (I-V) measurements on the hybrid nanostructures exhibited bistable current levels towards the memory function device, that and those characteristics were unnoticeable on individual nanomaterials. The hybrids showed good retention characteristics with high stability and durability, which is a promising feature for future nanoscale memory devices.

Nanogap‐Engineerable Electromechanical System for Ultralow Power Memory

PubMed Central

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei

2017-01-01

Abstract Nanogap engineering of low‐dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub‐5 nm nanogaped single‐walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10−19 J bit−1), ON/OFF ratio of 105, stable switching ON operations, and over 30 h retention time in ambient conditions. PMID:29619307

Electrically Variable Resistive Memory Devices

NASA Technical Reports Server (NTRS)

Liu, Shangqing; Wu, Nai-Juan; Ignatiev, Alex; Charlson, E. J.

2010-01-01

Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

Fast Initialization of Bubble-Memory Systems

NASA Technical Reports Server (NTRS)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1986-01-01

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

PubMed

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

NASA Astrophysics Data System (ADS)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-07-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

Garnet Random-Access Memory

NASA Technical Reports Server (NTRS)

Katti, Romney R.

1995-01-01

Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

Development of Curie point switching for thin film, random access, memory device

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Tchernev, D. I.

1967-01-01

Managanese bismuthide films are used in the development of a random access memory device of high packing density and nondestructive readout capability. Memory entry is by Curie point switching using a laser beam. Readout is accomplished by microoptical or micromagnetic scanning.

Inserting Thienyl Linkers into Conjugated Molecules for Efficient Multilevel Electronic Memory: A New Understanding of Charge-Trapping in Organic Materials.

PubMed

Li, Yang; Li, Hua; He, Jinghui; Xu, Qingfeng; Li, Najun; Chen, Dongyun; Lu, Jianmei

2016-03-18

The practical application of organic memory devices requires low power consumption and reliable device quality. Herein, we report that inserting thienyl units into D-π-A molecules can improve these parameters by tuning the texture of the film. Theoretical calculations revealed that introducing thienyl π bridges increased the planarity of the molecular backbone and extended the D-A conjugation. Thus, molecules with more thienyl spacers showed improved stacking and orientation in the film state relative to the substrates. The corresponding sandwiched memory devices showed enhanced ternary memory behavior, with lower threshold voltages and better repeatability. The conductive switching and variation in the performance of the memory devices were interpreted by using an extended-charge-trapping mechanism. Our study suggests that judicious molecular engineering can facilitate control of the orientation of the crystallite in the solid state to achieve superior multilevel memory performance. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide

NASA Astrophysics Data System (ADS)

Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

2009-04-01

We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 × 10-13-1.0 × 10-14 S cm-1. The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 1010. Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 1011. The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices.

Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide.

PubMed

Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

2009-04-01

We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 x 10(-13)-1.0 x 10(-14) S cm(-1). The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 10(10). Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 10(11). The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices.

Implementation methodology for interoperable personal health devices with low-voltage low-power constraints.

PubMed

Martinez-Espronceda, Miguel; Martinez, Ignacio; Serrano, Luis; Led, Santiago; Trigo, Jesús Daniel; Marzo, Asier; Escayola, Javier; Garcia, José

2011-05-01

Traditionally, e-Health solutions were located at the point of care (PoC), while the new ubiquitous user-centered paradigm draws on standard-based personal health devices (PHDs). Such devices place strict constraints on computation and battery efficiency that encouraged the International Organization for Standardization/IEEE11073 (X73) standard for medical devices to evolve from X73PoC to X73PHD. In this context, low-voltage low-power (LV-LP) technologies meet the restrictions of X73PHD-compliant devices. Since X73PHD does not approach the software architecture, the accomplishment of an efficient design falls directly on the software developer. Therefore, computational and battery performance of such LV-LP-constrained devices can even be outperformed through an efficient X73PHD implementation design. In this context, this paper proposes a new methodology to implement X73PHD into microcontroller-based platforms with LV-LP constraints. Such implementation methodology has been developed through a patterns-based approach and applied to a number of X73PHD-compliant agents (including weighing scale, blood pressure monitor, and thermometer specializations) and microprocessor architectures (8, 16, and 32 bits) as a proof of concept. As a reference, the results obtained in the weighing scale guarantee all features of X73PHD running over a microcontroller architecture based on ARM7TDMI requiring only 168 B of RAM and 2546 B of flash memory.

Optimization of Microelectronic Devices for Sensor Applications

NASA Technical Reports Server (NTRS)

Cwik, Tom; Klimeck, Gerhard

2000-01-01

The NASA/JPL goal to reduce payload in future space missions while increasing mission capability demands miniaturization of active and passive sensors, analytical instruments and communication systems among others. Currently, typical system requirements include the detection of particular spectral lines, associated data processing, and communication of the acquired data to other systems. Advances in lithography and deposition methods result in more advanced devices for space application, while the sub-micron resolution currently available opens a vast design space. Though an experimental exploration of this widening design space-searching for optimized performance by repeated fabrication efforts-is unfeasible, it does motivate the development of reliable software design tools. These tools necessitate models based on fundamental physics and mathematics of the device to accurately model effects such as diffraction and scattering in opto-electronic devices, or bandstructure and scattering in heterostructure devices. The software tools must have convenient turn-around times and interfaces that allow effective usage. The first issue is addressed by the application of high-performance computers and the second by the development of graphical user interfaces driven by properly developed data structures. These tools can then be integrated into an optimization environment, and with the available memory capacity and computational speed of high performance parallel platforms, simulation of optimized components can proceed. In this paper, specific applications of the electromagnetic modeling of infrared filtering, as well as heterostructure device design will be presented using genetic algorithm global optimization methods.

Optical memories in digital computing

NASA Technical Reports Server (NTRS)

Alford, C. O.; Gaylord, T. K.

1979-01-01

High capacity optical memories with relatively-high data-transfer rate and multiport simultaneous access capability may serve as basis for new computer architectures. Several computer structures that might profitably use memories are: a) simultaneous record-access system, b) simultaneously-shared memory computer system, and c) parallel digital processing structure.

Low latency counter event indication

DOEpatents

Gara, Alan G [Mount Kisco, NY; Salapura, Valentina [Chappaqua, NY

2008-09-16

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

Low latency counter event indication

DOEpatents

Gara, Alan G.; Salapura, Valentina

2010-08-24

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Resistive switching behaviors of Au/pentacene/Si-nanowire arrays/heavily doped n-type Si devices for memory applications

NASA Astrophysics Data System (ADS)

Tsao, Hou-Yen; Lin, Yow-Jon

2014-02-01

The fabrication of memory devices based on the Au/pentacene/heavily doped n-type Si (n+-Si), Au/pentacene/Si nanowires (SiNWs)/n+-Si, and Au/pentacene/H2O2-treated SiNWs/n+-Si structures and their resistive switching characteristics were reported. A pentacene memory structure using SiNW arrays as charge storage nodes was demonstrated. The Au/pentacene/SiNWs/n+-Si devices show hysteresis behavior. H2O2 treatment may lead to the hysteresis degradation. However, no hysteresis-type current-voltage characteristics were observed for Au/pentacene/n+-Si devices, indicating that the resistive switching characteristic is sensitive to SiNWs and the charge trapping effect originates from SiNWs. The concept of nanowires within the organic layer opens a promising direction for organic memory devices.

Solution-Processed Carbon Nanotube True Random Number Generator.

PubMed

Gaviria Rojas, William A; McMorrow, Julian J; Geier, Michael L; Tang, Qianying; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

2017-08-09

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

Real-time autocorrelator for fluorescence correlation spectroscopy based on graphical-processor-unit architecture: method, implementation, and comparative studies

NASA Astrophysics Data System (ADS)

Laracuente, Nicholas; Grossman, Carl

2013-03-01

We developed an algorithm and software to calculate autocorrelation functions from real-time photon-counting data using the fast, parallel capabilities of graphical processor units (GPUs). Recent developments in hardware and software have allowed for general purpose computing with inexpensive GPU hardware. These devices are more suited for emulating hardware autocorrelators than traditional CPU-based software applications by emphasizing parallel throughput over sequential speed. Incoming data are binned in a standard multi-tau scheme with configurable points-per-bin size and are mapped into a GPU memory pattern to reduce time-expensive memory access. Applications include dynamic light scattering (DLS) and fluorescence correlation spectroscopy (FCS) experiments. We ran the software on a 64-core graphics pci card in a 3.2 GHz Intel i5 CPU based computer running Linux. FCS measurements were made on Alexa-546 and Texas Red dyes in a standard buffer (PBS). Software correlations were compared to hardware correlator measurements on the same signals. Supported by HHMI and Swarthmore College

Portable telepathology: methods and tools.

PubMed

Alfaro, Luis; Roca, Ma José

2008-07-15

Telepathology is becoming easier to implement in most pathology departments. In fact e-mail image transmit can be done from almost any pathologist as a simplistic telepathology system. We tried to develop a way to improve capabilities of communication among pathologists with the idea that the system should be affordable for everybody. We took the premise that any pathology department would have microscopes and computers with Internet connection, and selected a few elements to convert them into a telepathology station. Needs were reduced to a camera to collect images, a universal microscope adapter for the camera, a device to connect the camera to the computer, and a software for the remote image transmit. We found out a microscope adapter (MaxView Plus) that allowed us connect almost any domestic digital camera to any microscope. The video out signal from the camera was sent to the computer through an Aver Media USB connector. At last, we selected a group of portable applications that were assembled into a USB memory device. Portable applications are computer programs that can be carried generally on USB flash drives, but also in any other portable device, and used on any (Windows) computer without installation. Besides, when unplugging the device, none of personal data is left behind. We selected open-source applications, and based the pathology image transmission to VLC Media Player due to its functionality as streaming server, portability and ease of use and configuration. Audio transmission was usually done through normal phone lines. We also employed alternative videoconferencing software, SightSpeed for bi-directional image transmission from microscopes, and conventional cameras allowing visual communication and also image transmit from gross pathology specimens. All these elements allowed us to install and use a telepathology system in a few minutes, fully prepared for real time image broadcast.

Portable telepathology: methods and tools

PubMed Central

Alfaro, Luis; Roca, Ma José

2008-01-01

Telepathology is becoming easier to implement in most pathology departments. In fact e-mail image transmit can be done from almost any pathologist as a simplistic telepathology system. We tried to develop a way to improve capabilities of communication among pathologists with the idea that the system should be affordable for everybody. We took the premise that any pathology department would have microscopes and computers with Internet connection, and selected a few elements to convert them into a telepathology station. Needs were reduced to a camera to collect images, a universal microscope adapter for the camera, a device to connect the camera to the computer, and a software for the remote image transmit. We found out a microscope adapter (MaxView Plus) that allowed us connect almost any domestic digital camera to any microscope. The video out signal from the camera was sent to the computer through an Aver Media USB connector. At last, we selected a group of portable applications that were assembled into a USB memory device. Portable applications are computer programs that can be carried generally on USB flash drives, but also in any other portable device, and used on any (Windows) computer without installation. Besides when unplugging the device, none of personal data is left behind. We selected open-source applications, and based the pathology image transmission to VLC Media Player due to its functionality as streaming server, portability and ease of use and configuration. Audio transmission was usually done through normal phone lines. We also employed alternative videoconferencing software, SightSpeed for bi-directional image transmission from microscopes, and conventional cameras allowing visual communication and also image transmit from gross pathology specimens. All these elements allowed us to install and use a telepathology system in a few minutes, fully prepared for real time image broadcast. PMID:18673507

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

The utilization of parallel processing in solving the inviscid form of the average-passage equation system for multistage turbomachinery

NASA Technical Reports Server (NTRS)

Mulac, Richard A.; Celestina, Mark L.; Adamczyk, John J.; Misegades, Kent P.; Dawson, Jef M.

1987-01-01

A procedure is outlined which utilizes parallel processing to solve the inviscid form of the average-passage equation system for multistage turbomachinery along with a description of its implementation in a FORTRAN computer code, MSTAGE. A scheme to reduce the central memory requirements of the program is also detailed. Both the multitasking and I/O routines referred to in this paper are specific to the Cray X-MP line of computers and its associated SSD (Solid-state Storage Device). Results are presented for a simulation of a two-stage rocket engine fuel pump turbine.

Thickness effect of nickel oxide thin films on associated solution-processed write-once-read-many-times memory devices

NASA Astrophysics Data System (ADS)

Wang, Xiao Lin; Liu, Zhen; Wen, Chao; Liu, Yang; Wang, Hong Zhe; Chen, T. P.; Zhang, Hai Yan

2018-06-01

With self-prepared nickel acetate based solution, NiO thin films with different thicknesses have been fabricated by spin coating followed by thermal annealing. By forming a two-terminal Ag/NiO/ITO structure on glass, write-once-read-many-times (WORM) memory devices are realized. The WORM memory behavior is based on a permanent switching from an initial high-resistance state (HRS) to an irreversible low-resistance state (LRS) under the application of a writing voltage, due to the formation of a solid bridge across Ag and ITO electrodes by conductive filaments (CFs). The memory performance is investigated as a function of the NiO film thickness, which is determined by the number of spin-coated NiO layers. For devices with 4 and 6 NiO layers, data retention up to 104 s and endurance of 103 reading operations in the measurement range have been obtained with memory window maintained above four orders for both HRS and LRS. Before and after writing, the devices show the hopping and ohmic conduction behaviors, respectively, confirming that the CF formation could be the mechanism responsible for writing in the WORM memory devices.

Reducing power consumption during execution of an application on a plurality of compute nodes

DOEpatents

Archer, Charles J.; Blocksome, Michael A.; Peters, Amanda E.; Ratterman, Joseph D.; Smith, Brian E.

2013-09-10

Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: powering up, during compute node initialization, only a portion of computer memory of the compute node, including configuring an operating system for the compute node in the powered up portion of computer memory; receiving, by the operating system, an instruction to load an application for execution; allocating, by the operating system, additional portions of computer memory to the application for use during execution; powering up the additional portions of computer memory allocated for use by the application during execution; and loading, by the operating system, the application into the powered up additional portions of computer memory.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Valentini, L., E-mail: luca.valentini@unipg.it; Cardinali, M.; Fortunati, E.

2014-10-13

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electricmore » field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.« less

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Investigation of fast initialization of spacecraft bubble memory systems

NASA Technical Reports Server (NTRS)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1984-01-01

Bubble domain technology offers significant improvement in reliability and functionality for spacecraft onboard memory applications. In considering potential memory systems organizations, minimization of power in high capacity bubble memory systems necessitates the activation of only the desired portions of the memory. In power strobing arbitrary memory segments, a capability of fast turn on is required. Bubble device architectures, which provide redundant loop coding in the bubble devices, limit the initialization speed. Alternate initialization techniques are investigated to overcome this design limitation. An initialization technique using a small amount of external storage is demonstrated.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

Radiation Test Challenges for Scaled Commerical Memories

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

2007-01-01

As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

Recent Advances of Flexible Data Storage Devices Based on Organic Nanoscaled Materials.

PubMed

Zhou, Li; Mao, Jingyu; Ren, Yi; Han, Su-Ting; Roy, Vellaisamy A L; Zhou, Ye

2018-03-01

Following the trend of miniaturization as per Moore's law, and facing the strong demand of next-generation electronic devices that should be highly portable, wearable, transplantable, and lightweight, growing endeavors have been made to develop novel flexible data storage devices possessing nonvolatile ability, high-density storage, high-switching speed, and reliable endurance properties. Nonvolatile organic data storage devices including memory devices on the basis of floating-gate, charge-trapping, and ferroelectric architectures, as well as organic resistive memory are believed to be favorable candidates for future data storage applications. In this Review, typical information on device structure, memory characteristics, device operation mechanisms, mechanical properties, challenges, and recent progress of the above categories of flexible data storage devices based on organic nanoscaled materials is summarized. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

[A monitor of the biomechanical cardiac activity].

PubMed

Masloboev, Iu P; Okhritskiĭ, A A; Prilutskiĭ, D A; Selishchev, S V

2004-01-01

A monitor of the biomechanical cardiac activity is described, which was elaborated on the basis of the accelerometer sensor and sigma-delta ADC for the purpose of registering the ballistocardiograms and seismocardiograms. The device ensures a non-stop signal recording for as long as 8 hours with the data being preserved in an inbuilt memory. Data are fed to the computer through the USB port. An algorithm is suggested for recordings processing by using the neuron-net technologies.

Hierarchically Self-Assembled Block Copolymer Blends for Templating Hollow Phase-Change Nanostructures with an Extremely Low Switching Current

DOE PAGES

Park, Woon Ik; Kim, Jong Min; Jeong, Jae Won; ...

2015-03-17

Phase change memory (PCM) is one of the most promising candidates for next-generation nonvolatile memory devices because of its high speed, excellent reliability, and outstanding scalability. But, the high switching current of PCM devices has been a critical hurdle to realize low-power operation. Although one solution is to reduce the switching volume of the memory, the resolution limit of photolithography hinders further miniaturization of device dimensions. Here, we employed unconventional self-assembly geometries obtained from blends of block copolymers (BCPs) to form ring-shaped hollow PCM nanostructures with an ultrasmall contact area between a phase-change material (Ge 2Sb 2Te 5) and amore » heater (TiN) electrode. The high-density (approximately 0.1 terabits per square inch) PCM nanoring arrays showed extremely small switching current of 2-3 mu A. Furthermore, the relatively small reset current of the ring-shaped PCM compared to the pillar-shaped devices is attributed to smaller switching volume, which is well supported by electro-thermal simulation results. Our approach may also be extended to other nonvolatile memory device applications such as resistive switching memory and magnetic storage devices, where the control of nanoscale geometry can significantly affect device performances.« less

Efficient Machine Learning Approach for Optimizing Scientific Computing Applications on Emerging HPC Architectures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arumugam, Kamesh

Efficient parallel implementations of scientific applications on multi-core CPUs with accelerators such as GPUs and Xeon Phis is challenging. This requires - exploiting the data parallel architecture of the accelerator along with the vector pipelines of modern x86 CPU architectures, load balancing, and efficient memory transfer between different devices. It is relatively easy to meet these requirements for highly structured scientific applications. In contrast, a number of scientific and engineering applications are unstructured. Getting performance on accelerators for these applications is extremely challenging because many of these applications employ irregular algorithms which exhibit data-dependent control-ow and irregular memory accesses. Furthermore,more » these applications are often iterative with dependency between steps, and thus making it hard to parallelize across steps. As a result, parallelism in these applications is often limited to a single step. Numerical simulation of charged particles beam dynamics is one such application where the distribution of work and memory access pattern at each time step is irregular. Applications with these properties tend to present significant branch and memory divergence, load imbalance between different processor cores, and poor compute and memory utilization. Prior research on parallelizing such irregular applications have been focused around optimizing the irregular, data-dependent memory accesses and control-ow during a single step of the application independent of the other steps, with the assumption that these patterns are completely unpredictable. We observed that the structure of computation leading to control-ow divergence and irregular memory accesses in one step is similar to that in the next step. It is possible to predict this structure in the current step by observing the computation structure of previous steps. In this dissertation, we present novel machine learning based optimization techniques to address the parallel implementation challenges of such irregular applications on different HPC architectures. In particular, we use supervised learning to predict the computation structure and use it to address the control-ow and memory access irregularities in the parallel implementation of such applications on GPUs, Xeon Phis, and heterogeneous architectures composed of multi-core CPUs with GPUs or Xeon Phis. We use numerical simulation of charged particles beam dynamics simulation as a motivating example throughout the dissertation to present our new approach, though they should be equally applicable to a wide range of irregular applications. The machine learning approach presented here use predictive analytics and forecasting techniques to adaptively model and track the irregular memory access pattern at each time step of the simulation to anticipate the future memory access pattern. Access pattern forecasts can then be used to formulate optimization decisions during application execution which improves the performance of the application at a future time step based on the observations from earlier time steps. In heterogeneous architectures, forecasts can also be used to improve the memory performance and resource utilization of all the processing units to deliver a good aggregate performance. We used these optimization techniques and anticipation strategy to design a cache-aware, memory efficient parallel algorithm to address the irregularities in the parallel implementation of charged particles beam dynamics simulation on different HPC architectures. Experimental result using a diverse mix of HPC architectures shows that our approach in using anticipation strategy is effective in maximizing data reuse, ensuring workload balance, minimizing branch and memory divergence, and in improving resource utilization.« less

Techniques and devices to restore cognition

PubMed Central

Serruya, Mijail Demian; Kahana, Michael J.

2011-01-01

Executive planning, the ability to direct and sustain attention, language and several types of memory may be compromised by conditions such as stroke, traumatic brain injury, cancer, autism, cerebral palsy and Alzheimer’s disease. No medical devices are currently available to help restore these cognitive functions. Recent findings about the neurophysiology of these conditions in humans coupled with progress in engineering devices to treat refractory neurological conditions imply that the time has arrived to consider the design and evaluation of a new class of devices. Like their neuromotor counterparts, neurocognitive prostheses might sense or modulate neural function in a non-invasive manner or by means of implanted electrodes. In order to paint a vision for future device development, it is essential to first review what can be achieved using behavioral and external modulatory techniques. While non-invasive approaches might strengthen a patient’s remaining intact cognitive abilities, neurocognitive prosthetics comprised of direct brain–computer interfaces could in theory physically reconstitute and augment the substrate of cognition itself. PMID:18539345

An assessment of memristor intrinsic fluctuations: a measurement of single atomic motion

NASA Astrophysics Data System (ADS)

Borghetti, Julien; Yang, J. Joshua; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2010-03-01

Memristors provides electrically tunable resistance for upcoming non-volatile memory and future neuromorphic computing. One of the key benefits of such a device is its scalability, which can be demonstrated from an architectural perspective as well as from a fundamental physics limit. 4D addressing schemes utilizing cross bar structures that can be stacked several layers high above the chip embodies unlimited addressing space. On the other limit, the basic operating principles of memristive devices allow one to reach storage of information in a single atom. In this report of nanoscale (sub 50nm) devices, we detect single atom fluctuations, which would then represent the ultimate limit for noise sources thus delineating the boundary conditions for circuit design. We show that electrically induced individual atom migrations do not affect the overall device atomic configuration until a critical bias where a single local fluctuation triggers a general atomic reconfiguration. This instability illustrates the robustness of the device non-volatility upon small electrical stress.

Miniature Wireless BioSensor for Remote Endoscopic Monitoring

NASA Astrophysics Data System (ADS)

Nemiroski, Alex; Brown, Keith; Issadore, David; Westervelt, Robert; Thompson, Chris; Obstein, Keith; Laine, Michael

2009-03-01

We have built a miniature wireless biosensor with fluorescence detection capability that explores the miniaturization limit for a self-powered sensor device assembled from the latest off-the-shelf technology. The device is intended as a remote medical sensor to be inserted endoscopically and remainin a patient's gastrointestinal tract for a period of weeks, recording and transmitting data as necessary. A sensing network may be formed by using multiple such devices within the patient, routing information to an external receiver that communicates through existing mobilephone networks to relay data remotely. By using a monolithic IC chip with integrated processor, memory, and 2.4 GHz radio,combined with a photonic sensor and miniature battery, we have developed a fully functional computing device in a form factorcompliantwith insertion through the narrowest endoscopic channels (less than 3mm x 3mm x 20mm). We envision similar devices with various types of sensors to be used in many different areas of the human body.

Characteristics of Reduced Graphene Oxide Quantum Dots for a Flexible Memory Thin Film Transistor.

PubMed

Kim, Yo-Han; Lee, Eun Yeol; Lee, Hyun Ho; Seo, Tae Seok

2017-05-17

Reduced graphene oxide quantum dot (rGOQD) devices in formats of capacitor and thin film transistor (TFT) were demonstrated and examined as the first trial to achieve nonambipolar channel property. In addition, through a gold nanoparticle (Au NP) layer embedded between the rGOQD active channel and dielectric layer, memory capacitor and TFT performances were realized by capacitance-voltage (C-V) hysteresis and gate program, erase, and reprogram biases. First, capacitor structure of the rGOQD memory device was constructed to examine memory charging effect featured in hysteretic C-V behavior with a 30 nm dielectric layer of cross-linked poly(vinyl alcohol). For the intervening Au NP charging layer, self-assembled monolayer (SAM) formation of the Au NP was executed to utilize electrostatic interaction by a dip-coating process under ambient environments with a conformal fabrication uniformity. Second, the rGOQD memory TFT device was also constructed in the same format of the Au NPs SAMs on a flexible substrate. Characteristics of the rGOQD TFT output showed novel saturation curves unlike typical graphene-based TFTs. However, The rGOQD TFT device reveals relatively low on/off ratio of 10 1 and mobility of 5.005 cm 2 /V·s. For the memory capacitor, the flat-band voltage shift (ΔV FB ) was measured as 3.74 V for ±10 V sweep, and for the memory TFT, the threshold voltage shift (ΔV th ) by the Au NP charging was detected as 7.84 V. In summary, it was concluded that the rGOQD memory device could accomplish an ideal graphene-based memory performance, which could have provided a wide memory window and saturated output characteristics.

Low-power resistive random access memory by confining the formation of conducting filaments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang, Yi-Jen; Lee, Si-Chen, E-mail: sclee@ntu.edu.tw; Shen, Tzu-Hsien

2016-06-15

Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO{sub x}/silver nanoparticles/TiO{sub x}/AlTiO{sub x}, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistancemore » state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO{sub x} layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.« less

Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shinde, Sachin M.; Tanemura, Masaki; Kalita, Golap, E-mail: kalita.golap@nitech.ac.jp

2014-12-07

Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material asmore » well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.« less

Storage and retrieval of large digital images

DOEpatents

Bradley, J.N.

1998-01-20

Image compression and viewing are implemented with (1) a method for performing DWT-based compression on a large digital image with a computer system possessing a two-level system of memory and (2) a method for selectively viewing areas of the image from its compressed representation at multiple resolutions and, if desired, in a client-server environment. The compression of a large digital image I(x,y) is accomplished by first defining a plurality of discrete tile image data subsets T{sub ij}(x,y) that, upon superposition, form the complete set of image data I(x,y). A seamless wavelet-based compression process is effected on I(x,y) that is comprised of successively inputting the tiles T{sub ij}(x,y) in a selected sequence to a DWT routine, and storing the resulting DWT coefficients in a first primary memory. These coefficients are periodically compressed and transferred to a secondary memory to maintain sufficient memory in the primary memory for data processing. The sequence of DWT operations on the tiles T{sub ij}(x,y) effectively calculates a seamless DWT of I(x,y). Data retrieval consists of specifying a resolution and a region of I(x,y) for display. The subset of stored DWT coefficients corresponding to each requested scene is determined and then decompressed for input to an inverse DWT, the output of which forms the image display. The repeated process whereby image views are specified may take the form an interaction with a computer pointing device on an image display from a previous retrieval. 6 figs.

Storage and retrieval of large digital images

DOEpatents

Bradley, Jonathan N.

1998-01-01

Image compression and viewing are implemented with (1) a method for performing DWT-based compression on a large digital image with a computer system possessing a two-level system of memory and (2) a method for selectively viewing areas of the image from its compressed representation at multiple resolutions and, if desired, in a client-server environment. The compression of a large digital image I(x,y) is accomplished by first defining a plurality of discrete tile image data subsets T.sub.ij (x,y) that, upon superposition, form the complete set of image data I(x,y). A seamless wavelet-based compression process is effected on I(x,y) that is comprised of successively inputting the tiles T.sub.ij (x,y) in a selected sequence to a DWT routine, and storing the resulting DWT coefficients in a first primary memory. These coefficients are periodically compressed and transferred to a secondary memory to maintain sufficient memory in the primary memory for data processing. The sequence of DWT operations on the tiles T.sub.ij (x,y) effectively calculates a seamless DWT of I(x,y). Data retrieval consists of specifying a resolution and a region of I(x,y) for display. The subset of stored DWT coefficients corresponding to each requested scene is determined and then decompressed for input to an inverse DWT, the output of which forms the image display. The repeated process whereby image views are specified may take the form an interaction with a computer pointing device on an image display from a previous retrieval.

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

NASA Technical Reports Server (NTRS)

Besser, P. J.

1976-01-01

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Device and methods for writing and erasing analog information in small memory units via voltage pulses

DOEpatents

El Gabaly Marquez, Farid; Talin, Albert Alec

2018-04-17

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Short-term memory to long-term memory transition in a nanoscale memristor.

PubMed

Chang, Ting; Jo, Sung-Hyun; Lu, Wei

2011-09-27

"Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories. © 2011 American Chemical Society

The potential of multi-port optical memories in digital computing

NASA Technical Reports Server (NTRS)

Alford, C. O.; Gaylord, T. K.

1975-01-01

A high-capacity memory with a relatively high data transfer rate and multi-port simultaneous access capability may serve as the basis for new computer architectures. The implementation of a multi-port optical memory is discussed. Several computer structures are presented that might profitably use such a memory. These structures include (1) a simultaneous record access system, (2) a simultaneously shared memory computer system, and (3) a parallel digital processing structure.

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

From dead leaves to sustainable organic resistive switching memory.

PubMed

Sun, Bai; Zhu, Shouhui; Mao, Shuangsuo; Zheng, Pingping; Xia, Yudong; Yang, Feng; Lei, Ming; Zhao, Yong

2018-03-01

An environmental-friendly, sustainable, pollution-free, biodegradable, flexible and wearable electronic device hold advanced potential applications. Here, an organic resistive switching memory device with Ag/Leaves/Ti/PET structure on a flexible polyethylene terephthalate (PET) substrate was fabricated for the first time. We observed an obvious resistive switching memory characteristic with large switching resistance ratio and stable cycle performance at room temperature. This work demonstrates that leaves, a useless waste, can be properly treated to make useful devices. Furthermore, the as-fabricated devices can be degraded naturally without damage to the environment. Copyright © 2017 Elsevier Inc. All rights reserved.

Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

NASA Astrophysics Data System (ADS)

Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

2018-05-01

A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

Composition-dependent nanoelectronics of amido-phenazines: non-volatile RRAM and WORM memory devices.

PubMed

Maiti, Dilip K; Debnath, Sudipto; Nawaz, Sk Masum; Dey, Bapi; Dinda, Enakhi; Roy, Dipanwita; Ray, Sudipta; Mallik, Abhijit; Hussain, Syed A

2017-10-17

A metal-free three component cyclization reaction with amidation is devised for direct synthesis of DFT-designed amido-phenazine derivative bearing noncovalent gluing interactions to fabricate organic nanomaterials. Composition-dependent organic nanoelectronics for nonvolatile memory devices are discovered using mixed phenazine-stearic acid (SA) nanomaterials. We discovered simultaneous two different types of nonmagnetic and non-moisture sensitive switching resistance properties of fabricated devices utilizing mixed organic nanomaterials: (a) sample-1(8:SA = 1:3) is initially off, turning on at a threshold, but it does not turn off again with the application of any voltage, and (b) sample-2 (8:SA = 3:1) is initially off, turning on at a sharp threshold and off again by reversing the polarity. No negative differential resistance is observed in either type. These samples have different device implementations: sample-1 is attractive for write-once-read-many-times memory devices, such as novel non-editable database, archival memory, electronic voting, radio frequency identification, sample-2 is useful for resistive-switching random access memory application.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

PubMed Central

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-01-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

Smart photodetector arrays for error control in page-oriented optical memory

NASA Astrophysics Data System (ADS)

Schaffer, Maureen Elizabeth

1998-12-01

Page-oriented optical memories (POMs) have been proposed to meet high speed, high capacity storage requirements for input/output intensive computer applications. This technology offers the capability for storage and retrieval of optical data in two-dimensional pages resulting in high throughput data rates. Since currently measured raw bit error rates for these systems fall several orders of magnitude short of industry requirements for binary data storage, powerful error control codes must be adopted. These codes must be designed to take advantage of the two-dimensional memory output. In addition, POMs require an optoelectronic interface to transfer the optical data pages to one or more electronic host systems. Conventional charge coupled device (CCD) arrays can receive optical data in parallel, but the relatively slow serial electronic output of these devices creates a system bottleneck thereby eliminating the POM advantage of high transfer rates. Also, CCD arrays are "unintelligent" interfaces in that they offer little data processing capabilities. The optical data page can be received by two-dimensional arrays of "smart" photo-detector elements that replace conventional CCD arrays. These smart photodetector arrays (SPAs) can perform fast parallel data decoding and error control, thereby providing an efficient optoelectronic interface between the memory and the electronic computer. This approach optimizes the computer memory system by combining the massive parallelism and high speed of optics with the diverse functionality, low cost, and local interconnection efficiency of electronics. In this dissertation we examine the design of smart photodetector arrays for use as the optoelectronic interface for page-oriented optical memory. We review options and technologies for SPA fabrication, develop SPA requirements, and determine SPA scalability constraints with respect to pixel complexity, electrical power dissipation, and optical power limits. Next, we examine data modulation and error correction coding for the purpose of error control in the POM system. These techniques are adapted, where possible, for 2D data and evaluated as to their suitability for a SPA implementation in terms of BER, code rate, decoder time and pixel complexity. Our analysis shows that differential data modulation combined with relatively simple block codes known as array codes provide a powerful means to achieve the desired data transfer rates while reducing error rates to industry requirements. Finally, we demonstrate the first smart photodetector array designed to perform parallel error correction on an entire page of data and satisfy the sustained data rates of page-oriented optical memories. Our implementation integrates a monolithic PN photodiode array and differential input receiver for optoelectronic signal conversion with a cluster error correction code using 0.35-mum CMOS. This approach provides high sensitivity, low electrical power dissipation, and fast parallel correction of 2 x 2-bit cluster errors in an 8 x 8 bit code block to achieve corrected output data rates scalable to 102 Gbps in the current technology increasing to 1.88 Tbps in 0.1-mum CMOS.

LABORATORY PROCESS CONTROLLER USING NATURAL LANGUAGE COMMANDS FROM A PERSONAL COMPUTER

NASA Technical Reports Server (NTRS)

Will, H.

1994-01-01

The complex environment of the typical research laboratory requires flexible process control. This program provides natural language process control from an IBM PC or compatible machine. Sometimes process control schedules require changes frequently, even several times per day. These changes may include adding, deleting, and rearranging steps in a process. This program sets up a process control system that can either run without an operator, or be run by workers with limited programming skills. The software system includes three programs. Two of the programs, written in FORTRAN77, record data and control research processes. The third program, written in Pascal, generates the FORTRAN subroutines used by the other two programs to identify the user commands with the user-written device drivers. The software system also includes an input data set which allows the user to define the user commands which are to be executed by the computer. To set the system up the operator writes device driver routines for all of the controlled devices. Once set up, this system requires only an input file containing natural language command lines which tell the system what to do and when to do it. The operator can make up custom commands for operating and taking data from external research equipment at any time of the day or night without the operator in attendance. This process control system requires a personal computer operating under MS-DOS with suitable hardware interfaces to all controlled devices. The program requires a FORTRAN77 compiler and user-written device drivers. This program was developed in 1989 and has a memory requirement of about 62 Kbytes.

EDITORIAL: Nanomemory: information and ingenuity Nanomemory: information and ingenuity

NASA Astrophysics Data System (ADS)

Demming, Anna

2013-04-01

The age of information has placed unprecedented demands on data storage. In response, a rich hub of research activity has erupted in the search for new types of memory with improved capacity and data processing speed [1, 2]. There has even been progress in mimicking the subtleties of how the human neural system remembers and forgets with artificial synaptic devices [3, 4]. Yet many challenges remain. As researchers at Brigham Young University in the US point out, 'Current data storage technologies have limitations that prevent their use in archival data storage applications'. Anthony C Pearson and colleagues look at the potential role of graphene in data storage solutions. Graphene's wide range of extraordinary properties has recommended it for a number of applications. This issue reports how it can form the basis of nanofuses that may be used for permanent, write-once-read-many (WORM) data storage devices [5]. Leon Chua's forecast of 'Memristor—the missing circuit element' [6] and the subsequent demonstration of memristance in nanoscale systems by researchers at HP Labs [7] triggered a surge of studies investigating the application of memristor devices in non-volatile memory [8]. In fact these structures may have a still broader impact in nanotechnology. At the nanoscale statistical variations in defect concentrations give rise to vast differences in behaviour, and device variability and ageing can be profound. These characteristics led George Snider to observe, 'Nanodevices are crummy', when considering their application in conventional Boolean logic systems [9]. Yet Snider's grim assessment was merely a prologue to an insightful recount of simulations demonstrating how to side-step a number of nanotechnology's main challenges by using self-organizing networks based on memristive devices. Similar fault tolerance is demonstrated in the organic-nanoparticle transistors developed by researchers at the University of Lille, who demonstrate a weighting behaviour that mimics aspects of synaptic functions that may be key to implementing neuromorphic computing [10]. Developments in this field show increasingly more sophisticated imitation of human neural processing with analogue memory functionality [3] and circuits that both learn and forget [4]. Keep an eye out for the Nanotechnology special issue on synaptic electronics later this year with guest editors James Gimzewski from the University of California, Los Angeles, and Dominique Vuillaume from the University of Lille, for a one-stop update on the latest cutting edge developments in this field. Graphene has demonstrated excellent potential in a number of applications from supercapacitors [11] to photomechanical actuators [12]. However, so far its potential in memory has been notably less explored. In this issue Anthony C Pearson and colleagues at Brigham Young University report how they fabricate graphene 'bow-tie' structures for fuses and program them though thermal oxidation [5]. As the researchers point out graphene's low atomic mobility, high chemical resistance to oxidation and excellent electrical conductivity make it well suited as archival data storage fuse material. They also highlight a number of attractive attributes in the devices as a whole: 'graphene WORM devices can be read and written electronically, can potentially have the very high data densities of flash memory, appear to be highly stable in both the on and off states, have a high on/off current ratio, and can be programmed with low voltages and powers'. In fuses an electrical connection is destroyed by an applied voltage. The process sounds destructive yet fuses are incredibly useful. Edison once famously commented, 'Just because something does not do what you planned it to do does not mean it is useless' [13]. There are synergies of this philosophy throughout nanotechnology research where apparently awkward behaviour is put to good use. Adding the dynamical nature of nanodevices to the list of obstacles to scalability, Snider rounded up his assessment, 'So we are faced with the challenge of computing with devices that are not only crummy, but dynamical as well'. Yet it was that dynamic behaviour that he went on to exploit in his demonstration of robust self-organizing networks using memristor devices. Successful research is by nature continually revealing behaviour that is unexpected or unusual. The work described here is just some of the many examples of how successful development in research does not tolerate the unexpected, but embraces it. References [1] Waser R and Aono M 2007 Nanoionics-based resistive switching memories Nature Mater 6 833-40 [2] Vontobel P O, Robinett W, Kuekes P J, Stewart D R, Straznicky J and Stanley Williams R 2009 Writing to and reading from a nano-scale crossbar memory based on memristors Nanotechnology 20 425204 [3] Seo K et al 2011 Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device Nanotechnology 22 254023 [4] Yang R, Terabe K, Liu G, Tsuruoka T, Hasegawa T, Gimzewski J K and Aono M 2012 On-demand nanodevice with electrical and neuromorphic multifunction realized by local ion migration ACS Nano 6 9515-20 [5] Pearson A C, Jamieson S, Linford M R, Lunt B M and Davis R C 2013 Oxidation of graphene 'bow tie' nanofuses for permanent, write-once-read-many data storage devices Nanotechnology 24 135202 [6]Chua L O 1971 Memristor—the missing circuit element IEEE Trans. Circuit Theory 18 507-19 [7] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 The missing memristor found Nature 453 80-3 [8] Non-volatile memory based on nanostructures http://iopscience.iop.org/0957-4484/22/25 [9] Snider G S 2007 Self-organized computation with unreliable, memristive nanodevices Nanotechnology 18 365202 [10] Alibart F, Pieutin S, Guérin D, Novembre C, Lenfant S, Lmimouni K, Gamrat C and Vuillaume D 2010 An organic nanoparticle transistor behaving as a biological spiking synapse Adv. Funct. Mater 20 330-7 [11] Bose S, Kim N H, Kuila T, Lau K-T and Lee J H 2011 Electrochemical performance of a graphene-polypyrrole nanocomposite as a supercapacitor electrode Nanotechnology 22 295202 [12] Loomis J, King B, Burkhead T, Xu P, Bessler N, Terentjev E and Panchapakesan B 2012 Graphene-nanoplatelet-based photomechanical actuators Nanotechnology 23 045501 [13] Finn C A 2001 Artifacts: An Archaeologist's Year in Silicon Valley (Cambridge, MA: MIT Press)

Impact of electrically formed interfacial layer and improved memory characteristics of IrOx/high-κx/W structures containing AlOx, GdOx, HfOx, and TaOx switching materials.

PubMed

Prakash, Amit; Maikap, Siddheswar; Banerjee, Writam; Jana, Debanjan; Lai, Chao-Sung

2013-09-06

Improved switching characteristics were obtained from high-κ oxides AlOx, GdOx, HfOx, and TaOx in IrOx/high-κx/W structures because of a layer that formed at the IrOx/high-κx interface under external positive bias. The surface roughness and morphology of the bottom electrode in these devices were observed by atomic force microscopy. Device size was investigated using high-resolution transmission electron microscopy. More than 100 repeatable consecutive switching cycles were observed for positive-formatted memory devices compared with that of the negative-formatted devices (only five unstable cycles) because it contained an electrically formed interfacial layer that controlled 'SET/RESET' current overshoot. This phenomenon was independent of the switching material in the device. The electrically formed oxygen-rich interfacial layer at the IrOx/high-κx interface improved switching in both via-hole and cross-point structures. The switching mechanism was attributed to filamentary conduction and oxygen ion migration. Using the positive-formatted design approach, cross-point memory in an IrOx/AlOx/W structure was fabricated. This cross-point memory exhibited forming-free, uniform switching for >1,000 consecutive dc cycles with a small voltage/current operation of ±2 V/200 μA and high yield of >95% switchable with a large resistance ratio of >100. These properties make this cross-point memory particularly promising for high-density applications. Furthermore, this memory device also showed multilevel capability with a switching current as low as 10 μA and a RESET current of 137 μA, good pulse read endurance of each level (>105 cycles), and data retention of >104 s at a low current compliance of 50 μA at 85°C. Our improvement of the switching characteristics of this resistive memory device will aid in the design of memory stacks for practical applications.

Parallel design of JPEG-LS encoder on graphics processing units

NASA Astrophysics Data System (ADS)

Duan, Hao; Fang, Yong; Huang, Bormin

2012-01-01

With recent technical advances in graphic processing units (GPUs), GPUs have outperformed CPUs in terms of compute capability and memory bandwidth. Many successful GPU applications to high performance computing have been reported. JPEG-LS is an ISO/IEC standard for lossless image compression which utilizes adaptive context modeling and run-length coding to improve compression ratio. However, adaptive context modeling causes data dependency among adjacent pixels and the run-length coding has to be performed in a sequential way. Hence, using JPEG-LS to compress large-volume hyperspectral image data is quite time-consuming. We implement an efficient parallel JPEG-LS encoder for lossless hyperspectral compression on a NVIDIA GPU using the computer unified device architecture (CUDA) programming technology. We use the block parallel strategy, as well as such CUDA techniques as coalesced global memory access, parallel prefix sum, and asynchronous data transfer. We also show the relation between GPU speedup and AVIRIS block size, as well as the relation between compression ratio and AVIRIS block size. When AVIRIS images are divided into blocks, each with 64×64 pixels, we gain the best GPU performance with 26.3x speedup over its original CPU code.

Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis

NASA Astrophysics Data System (ADS)

Younis, Adnan; Chu, Dewei; Li, Sean

2015-09-01

Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device’s retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective.

Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis

PubMed Central

Younis, Adnan; Chu, Dewei; Li, Sean

2015-01-01

Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device’s retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective. PMID:26324073

Operation mode switchable charge-trap memory based on few-layer MoS2

NASA Astrophysics Data System (ADS)

Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-03-01

Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Virtex-5QV Self Scrubber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojahn, Christopher K.

2015-10-20

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

Application of graphene oxide-poly (vinyl alcohol) polymer nanocomposite for memory devices

NASA Astrophysics Data System (ADS)

Kaushal, Jyoti; Kaur, Ravneet; Sharma, Jadab; Tripathi, S. K.

2018-05-01

Significant attention has been gained by polymer nanocomposites because of their possible demands in future electronic memory devices. In the present work, device based on Graphene Oxide (GO) and polyvinyl alcohol (PVA) has been made and examined for the memory device application. The prepared Graphene oxide (GO) and GO-PVA nanocomposite (NC) has been characterized by X-ray Diffraction (XRD). GO nanosheets show the diffraction peak at 2θ = 11.60° and the interlayer spacing of 0.761 nm. The XRD of GO-PVA NC shows the diffraction peak at 2θ =18.56°. The fabricated device shows bipolar switching behavior having ON/OFF current ratio ˜102. The Write-Read-Erase-Read (WRER) cycles test shows that the Al/GO-PVA/Ag device has good stability and repeatability.

Implementing ISO/IEEE 11073: proposal of two different strategic approaches.

PubMed

Martínez-Espronceda, M; Serrano, L; Martínez, I; Escayola, J; Led, S; Trigo, J; García, J

2008-01-01

This paper explains the challenges encountered during the ISO/IEEE 11073 standard implementation process. The complexity of the standard and the consequent heavy requirements, which have not encouraged software engineers to adopt the standard. The developing complexity evaluation drives us to propose two possible implementation strategies that cover almost all possible use cases and eases handling the standard by non-expert users. The first one is focused on medical devices (MD) and proposes a low-memory and low-processor usage technique. It is based on message patterns that allow simple functions to generate ISO/IEEE 11073 messages and to process them easily. In this way a framework for MDs can be obtained. Second one is focused on more powerful machines such as data loggers or gateways (aka. computer engines (CE)), which do not have the MDs' memory and processor usage constraints. For CEs a more intelligent and adaptative Plug&Play (P&P) solution is provided. It consists on a general platform that can access to any device supported by the standard. Combining both strategies will cut developing time for applications based on ISO/EEE 11073.

Ising formulation of associative memory models and quantum annealing recall

NASA Astrophysics Data System (ADS)

Santra, Siddhartha; Shehab, Omar; Balu, Radhakrishnan

2017-12-01

Associative memory models, in theoretical neuro- and computer sciences, can generally store at most a linear number of memories. Recalling memories in these models can be understood as retrieval of the energy minimizing configuration of classical Ising spins, closest in Hamming distance to an imperfect input memory, where the energy landscape is determined by the set of stored memories. We present an Ising formulation for associative memory models and consider the problem of memory recall using quantum annealing. We show that allowing for input-dependent energy landscapes allows storage of up to an exponential number of memories (in terms of the number of neurons). Further, we show how quantum annealing may naturally be used for recall tasks in such input-dependent energy landscapes, although the recall time may increase with the number of stored memories. Theoretically, we obtain the radius of attractor basins R (N ) and the capacity C (N ) of such a scheme and their tradeoffs. Our calculations establish that for randomly chosen memories the capacity of our model using the Hebbian learning rule as a function of problem size can be expressed as C (N ) =O (eC1N) , C1≥0 , and succeeds on randomly chosen memory sets with a probability of (1 -e-C2N) , C2≥0 with C1+C2=(0.5-f ) 2/(1 -f ) , where f =R (N )/N , 0 ≤f ≤0.5 , is the radius of attraction in terms of the Hamming distance of an input probe from a stored memory as a fraction of the problem size. We demonstrate the application of this scheme on a programmable quantum annealing device, the D-wave processor.

Automatic disease diagnosis using optimised weightless neural networks for low-power wearable devices

PubMed Central

Edla, Damodar Reddy; Kuppili, Venkatanareshbabu; Dharavath, Ramesh; Beechu, Nareshkumar Reddy

2017-01-01

Low-power wearable devices for disease diagnosis are used at anytime and anywhere. These are non-invasive and pain-free for the better quality of life. However, these devices are resource constrained in terms of memory and processing capability. Memory constraint allows these devices to store a limited number of patterns and processing constraint provides delayed response. It is a challenging task to design a robust classification system under above constraints with high accuracy. In this Letter, to resolve this problem, a novel architecture for weightless neural networks (WNNs) has been proposed. It uses variable sized random access memories to optimise the memory usage and a modified binary TRIE data structure for reducing the test time. In addition, a bio-inspired-based genetic algorithm has been employed to improve the accuracy. The proposed architecture is experimented on various disease datasets using its software and hardware realisations. The experimental results prove that the proposed architecture achieves better performance in terms of accuracy, memory saving and test time as compared to standard WNNs. It also outperforms in terms of accuracy as compared to conventional neural network-based classifiers. The proposed architecture is a powerful part of most of the low-power wearable devices for the solution of memory, accuracy and time issues. PMID:28868148

Efficient Numeric and Geometric Computations using Heterogeneous Shared Memory Architectures

DTIC Science & Technology

2017-10-04

Report: Efficient Numeric and Geometric Computations using Heterogeneous Shared Memory Architectures The views, opinions and/or findings contained in this...Chapel Hill Title: Efficient Numeric and Geometric Computations using Heterogeneous Shared Memory Architectures Report Term: 0-Other Email: dm...algorithms for scientific and geometric computing by exploiting the power and performance efficiency of heterogeneous shared memory architectures . These

Adaptive sampler

DOEpatents

Watson, B.L.; Aeby, I.

1980-08-26

An adaptive data compression device for compressing data is described. The device has a frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

In-memory interconnect protocol configuration registers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cheng, Kevin Y.; Roberts, David A.

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mappingmore » decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.« less

Internode data communications in a parallel computer

DOEpatents

Archer, Charles J.; Blocksome, Michael A.; Miller, Douglas R.; Parker, Jeffrey J.; Ratterman, Joseph D.; Smith, Brian E.

2013-09-03

Internode data communications in a parallel computer that includes compute nodes that each include main memory and a messaging unit, the messaging unit including computer memory and coupling compute nodes for data communications, in which, for each compute node at compute node boot time: a messaging unit allocates, in the messaging unit's computer memory, a predefined number of message buffers, each message buffer associated with a process to be initialized on the compute node; receives, prior to initialization of a particular process on the compute node, a data communications message intended for the particular process; and stores the data communications message in the message buffer associated with the particular process. Upon initialization of the particular process, the process establishes a messaging buffer in main memory of the compute node and copies the data communications message from the message buffer of the messaging unit into the message buffer of main memory.

Internode data communications in a parallel computer

DOEpatents

Archer, Charles J; Blocksome, Michael A; Miller, Douglas R; Parker, Jeffrey J; Ratterman, Joseph D; Smith, Brian E

2014-02-11

Internode data communications in a parallel computer that includes compute nodes that each include main memory and a messaging unit, the messaging unit including computer memory and coupling compute nodes for data communications, in which, for each compute node at compute node boot time: a messaging unit allocates, in the messaging unit's computer memory, a predefined number of message buffers, each message buffer associated with a process to be initialized on the compute node; receives, prior to initialization of a particular process on the compute node, a data communications message intended for the particular process; and stores the data communications message in the message buffer associated with the particular process. Upon initialization of the particular process, the process establishes a messaging buffer in main memory of the compute node and copies the data communications message from the message buffer of the messaging unit into the message buffer of main memory.

Metrology of deep trench etched memory structures using 3D scatterometry

NASA Astrophysics Data System (ADS)

Reinig, Peter; Dost, Rene; Moert, Manfred; Hingst, Thomas; Mantz, Ulrich; Moffitt, Jasen; Shakya, Sushil; Raymond, Christopher J.; Littau, Mike

2005-05-01

Scatterometry is receiving considerable attention as an emerging optical metrology in the silicon industry. One area of progress in deploying these powerful measurements in process control is performing measurements on real device structures, as opposed to limiting scatterometry measurements to periodic structures, such as line-space gratings, placed in the wafer scribe. In this work we will discuss applications of 3D scatterometry to the measurement of advanced trench memory devices. This is a challenging and complex scatterometry application that requires exceptionally high-performance computational abilities. In order to represent the physical device, the relatively tall structures require a high number of slices in the rigorous coupled wave analysis (RCWA) theoretical model. This is complicated further by the presence of an amorphous silicon hard mask on the surface, which is highly sensitive to reflectance scattering and therefore needs to be modeled in detail. The overall structure is comprised of several layers, with the trenches presenting a complex bow-shape sidewall that must be measured. Finally, the double periodicity in the structures demands significantly greater computational capabilities. Our results demonstrate that angular scatterometry is sensitive to the key parameters of interest. The influence of further model parameters and parameter cross correlations have to be carefully taken into account. Profile results obtained by non-library optimization methods compare favorably with cross-section SEM images. Generating a model library suitable for process control, which is preferred for precision, presents numerical throughput challenges. Details will be discussed regarding library generation approaches and strategies for reducing the numerical overhead. Scatterometry and SEM results will be compared, leading to conclusions about the feasibility of this advanced application.

NAS technical summaries: Numerical aerodynamic simulation program, March 1991 - February 1992

NASA Technical Reports Server (NTRS)

1992-01-01

NASA created the Numerical Aerodynamic Simulation (NAS) Program in 1987 to focus resources on solving critical problems in aeroscience and related disciplines by utilizing the power of the most advanced supercomputers available. The NAS Program provides scientists with the necessary computing power to solve today's most demanding computational fluid dynamics problems and serves as a pathfinder in integrating leading-edge supercomputing technologies, thus benefiting other supercomputer centers in Government and industry. This report contains selected scientific results from the 1991-92 NAS Operational Year, March 4, 1991 to March 3, 1992, which is the fifth year of operation. During this year, the scientific community was given access to a Cray-2 and a Cray Y-MP. The Cray-2, the first generation supercomputer, has four processors, 256 megawords of central memory, and a total sustained speed of 250 million floating point operations per second. The Cray Y-MP, the second generation supercomputer, has eight processors and a total sustained speed of one billion floating point operations per second. Additional memory was installed this year, doubling capacity from 128 to 256 megawords of solid-state storage-device memory. Because of its higher performance, the Cray Y-MP delivered approximately 77 percent of the total number of supercomputer hours used during this year.