Science.gov

Sample records for correct hardware design

  1. Hardware

    NASA Technical Reports Server (NTRS)

    1999-01-01

    The full complement of EDOMP investigations called for a broad spectrum of flight hardware ranging from commercial items, modified for spaceflight, to custom designed hardware made to meet the unique requirements of testing in the space environment. In addition, baseline data collection before and after spaceflight required numerous items of ground-based hardware. Two basic categories of ground-based hardware were used in EDOMP testing before and after flight: (1) hardware used for medical baseline testing and analysis, and (2) flight-like hardware used both for astronaut training and medical testing. To ensure post-landing data collection, hardware was required at both the Kennedy Space Center (KSC) and the Dryden Flight Research Center (DFRC) landing sites. Items that were very large or sensitive to the rigors of shipping were housed permanently at the landing site test facilities. Therefore, multiple sets of hardware were required to adequately support the prime and backup landing sites plus the Johnson Space Center (JSC) laboratories. Development of flight hardware was a major element of the EDOMP. The challenges included obtaining or developing equipment that met the following criteria: (1) compact (small size and light weight), (2) battery-operated or requiring minimal spacecraft power, (3) sturdy enough to survive the rigors of spaceflight, (4) quiet enough to pass acoustics limitations, (5) shielded and filtered adequately to assure electromagnetic compatibility with spacecraft systems, (6) user-friendly in a microgravity environment, and (7) accurate and efficient operation to meet medical investigative requirements.

  2. Extravehicular Activity training and hardware design considerations

    NASA Technical Reports Server (NTRS)

    Thuot, Pierre J.; Harbaugh, Gregory J.

    1993-01-01

    Designing hardware that can be successfully operated by EVA astronauts for EVA tasks required to assemble and maintain Space Station Freedom requires a thorough understanding of human factors and of the capabilities and limitations of the space-suited astronaut, as well as of the effect of microgravity environment on the crew member's capabilities and on the overhead associated with EVA. This paper describes various training methods and facilities that are being designed for training EVA astronauts for Space Station assembly and maintenance, taking into account the above discussed factors. Particular attention is given to the user-friendly hardware design for EVA and to recent EVA flight experience.

  3. Space hardware designs, volume 1

    NASA Technical Reports Server (NTRS)

    Meyer, Rudolf X.; Cribbs, Richard; Honda, Mark; Ma, Christina; Robson, Christopher

    1994-01-01

    The design of a solar sail space vehicle with a novel sail deployment mechanism is described. The sail is triangular in shape and is deployed and stabilized by three miniature spacecraft, one at each corner of the triangle. A concept demonstrator for a spherical microrover for the exploration of a planetary surface is described. Lastly, laboratory experiments have been conducted to study the migration of thin oil films on metal surfaces in the presence of a thermal gradient.

  4. Digital Hardware Design Teaching: An Alternative Approach

    ERIC Educational Resources Information Center

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  5. Shuttle mission simulator hardware conceptual design report

    NASA Technical Reports Server (NTRS)

    Burke, J. F.

    1973-01-01

    The detailed shuttle mission simulator hardware requirements are discussed. The conceptual design methods, or existing technology, whereby those requirements will be fulfilled are described. Information of a general nature on the total design problem plus specific details on how these requirements are to be satisfied are reported. The configuration of the simulator is described and the capabilities for various types of training are identified.

  6. Microprocessor Design Using Hardware Description Language

    ERIC Educational Resources Information Center

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  7. Design guidelines for robotically serviceable hardware

    NASA Technical Reports Server (NTRS)

    Gordon, Scott A.

    1988-01-01

    Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

  8. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

  9. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discuss the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of the population, n, and the number of generations required for the population to converge, ngen, based on L, the length of the programming string. We show that the processing time of the computer becomes negligible for intrinsic EHW since the selection/crossover/mutation steps are only done once per generation, suggesting there is room for use of more complex evolutionary algorithms m intrinsic EHW. F i y , we review the state of the practice and discuss the notion of a system design approach for intrinsic EHW.

  10. Employing ISRU Models to Improve Hardware Design

    NASA Technical Reports Server (NTRS)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  11. The Art of Space Flight Exercise Hardware: Design and Implementation

    NASA Technical Reports Server (NTRS)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  12. Automated Hardware Design via Evolutionary Search

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Colombano, Silvano P.

    2000-01-01

    The goal of this research is to investigate the application of evolutionary search to the process of automated engineering design. Evolutionary search techniques involve the simulation of Darwinian mechanisms by computer algorithms. In recent years, such techniques have attracted much attention because they are able to tackle a wide variety of difficult problems and frequently produce acceptable solutions. The results obtained are usually functional, often surprising, and typically "messy" because the algorithms are told to concentrate on the overriding objective and not elegance or simplicity. advantages. First, faster design cycles translate into time and, hence, cost savings. Second, automated design techniques can be made to scale well and hence better deal with increasing amounts of design complexity. Third, design quality can increase because design properties can be specified a priori. For example, size and weight specifications of a device, smaller and lighter than the best known design, might be optimized by the automated design technique. The domain of electronic circuit design is an advantageous platform in which to study automated design techniques because it is a rich design space that is well understood, permitting human-created designs to be compared to machine- generated designs. developed for circuit design was to automatically produce high-level integrated electronic circuit designs whose properties permit physical implementation in silicon. This process entailed designing an effective evolutionary algorithm and solving a difficult multiobjective optimization problem. FY 99 saw many accomplishments in this effort.

  13. Hardware Design and Implementation of IP-over-1394 Protocol Stack and Its Evaluation

    NASA Astrophysics Data System (ADS)

    Abe, Kôki; Hassan, Mohd Yusairi Bin Abu

    This paper describes the hardware design of core functions of the Internet protocol IP over IEEE1394 interface (IP over 1394) and its implementation on an FPGA. The design was evaluated by counting the number of FPGA logic elements required for the implementation. Using a system clock of 49.152MHz, we verified that packets sent from an application on top of the protocol stack were correctly received by the other protocol stack via the IEEE1394 port at a transfer rate of 400 Mbps. We also verified the communication behaviors of the design with an isochronous resource manager to reserve a channel prior to data transmissions. The hardware cost of the core IP layer was less than that of the link layer. The evaluation results will help the IP-over-1394 designers explore quantitatively various spectrum of the software/hardware design alternatives.

  14. Magnetic resonance elastography hardware design: a survey.

    PubMed

    Tse, Z T H; Janssen, H; Hamed, A; Ristic, M; Young, I; Lamperth, M

    2009-05-01

    Magnetic resonance elastography (MRE) is an emerging technique capable of measuring the shear modulus of tissue. A suspected tumour can be identified by comparing its properties with those of tissues surrounding it; this can be achieved even in deep-lying areas as long as mechanical excitation is possible. This would allow non-invasive methods for cancer-related diagnosis in areas not accessible with conventional palpation. An actuating mechanism is required to generate the necessary tissue displacements directly on the patient in the scanner and three different approaches, in terms of actuator action and position, exist to derive stiffness measurements. However, the magnetic resonance (MR) environment places considerable constraints on the design of such devices, such as the possibility of mutual interference between electrical components, the scanner field, and radio frequency pulses, and the physical space restrictions of the scanner bore. This paper presents a review of the current solutions that have been developed for MRE devices giving particular consideration to the design criteria including the required vibration frequency and amplitude in different applications, the issue of MR compatibility, actuation principles, design complexity, and scanner synchronization issues. The future challenges in this field are also described.

  15. Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

    NASA Technical Reports Server (NTRS)

    Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

    2013-01-01

    This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

  16. Design Tools for Reconfigurable Hardware in Orbit (RHinO)

    NASA Technical Reports Server (NTRS)

    French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

    2004-01-01

    The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

  17. Energy Efficient Engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Burrus, D. L.; Chahrour, C. A.; Foltz, H. L.; Sabla, P. E.; Seto, S. P.; Taylor, J. R.

    1984-01-01

    The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

  18. Hardware Design of the Energy Efficient Fall Detection Device

    NASA Astrophysics Data System (ADS)

    Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

    2016-04-01

    Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

  19. Hardware Design Improvements to the Major Constituent Analyzer

    NASA Technical Reports Server (NTRS)

    Combs, Scott; Schwietert, Daniel; Anaya, Marcial; DeWolf, Shannon; Merrill, Dave; Gardner, Ben D.; Thoresen, Souzan; Granahan, John; Belcher, Paul; Matty, Chris

    2011-01-01

    The Major Constituent Analyzer (MCA) onboard the International Space Station (ISS) is designed to monitor the major constituents of the ISS's internal atmosphere. This mass spectrometer based system is an integral part of the Environmental Control and Life Support System (ECLSS) and is a primary tool for the management of ISS atmosphere composition. As a part of NASA Change Request CR10773A, several alterations to the hardware have been made to accommodate improved MCA logistics. First, the ORU 08 verification gas assembly has been modified to allow the verification gas cylinder to be installed on orbit. The verification gas is an essential MCA consumable that requires periodic replenishment. Designing the cylinder for subassembly transport reduces the size and weight of the maintained item for launch. The redesign of the ORU 08 assembly includes a redesigned housing, cylinder mounting apparatus, and pneumatic connection. The second hardware change is a redesigned wiring harness for the ORU 02 analyzer. The ORU 02 electrical connector interface was damaged in a previous on-orbit installation, and this necessitated the development of a temporary fix while a more permanent solution was developed. The new wiring harness design includes flexible cable as well as indexing fasteners and guide-pins, and provides better accessibility during the on-orbit maintenance operation. This presentation will describe the hardware improvements being implemented for MCA as well as the expected improvement to logistics and maintenance.

  20. HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

    NASA Technical Reports Server (NTRS)

    Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

    2005-01-01

    An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

  1. IDEAS and App Development Internship in Hardware and Software Design

    NASA Technical Reports Server (NTRS)

    Alrayes, Rabab D.

    2016-01-01

    In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

  2. Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

    NASA Technical Reports Server (NTRS)

    Gonzalez, Stefanie M.

    2010-01-01

    The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

  3. A hardware Kalman-based offset estimator for nonuniformity correction on IRFPA

    NASA Astrophysics Data System (ADS)

    Contreras, Javier; Redlich, Rodolfo; Figueroa, Miguel; Torres, Sergio

    2012-10-01

    This paper presents a digital hardware filter that estimates the nonuniformity (NU) noise in an Infrared Focal Plane Array (IRFPA) and corrects it in real time. Implementing the algorithm in hardware results in a fast, compact, low-power nonuniformity correction (NUC) system that can be embedded into an intelligent imager at a very low cost. Because it does not use an external reference, our NUC circuit works in real time during normal operation, and can track parameter drift over time. Our NUC system models NU noise as a spatially regular source of additive noise, uses a Kalman filter to estimate the offset in each detector of the array and applies an inverse model to recover the original information captured by the detector. The NUC board uses a low-cost Xilinx Spartan 3E XC3S500E FPGA operating at 75MHz. The NUC circuit consumes 17.3mW of dynamic power and uses only 10% of the logic resources of the FPGA. Despite ignoring the multiplicative effects of nonuniformity, our NUC circuit reaches a Peak Signal-to-Noise Ratio (PSNR) of 35dB in under 50 frames, referenced to two-point calibration using black bodies. This performance lies within 0.35dB of a double-precision Matlab implementation of the algorithm. Without the bandwidth limitations currently imposed by the external RAM that stores the offset estimations, our circuit can correct 320x240-pixel video at up to 1,254 frames per second.

  4. Hardware accelerator design for tracking in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

  5. Modular implementation of a digital hardware design automation system

    NASA Astrophysics Data System (ADS)

    Masud, M.

    An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

  6. Design Time Optimization for Hardware Watermarking Protection of HDL Designs

    PubMed Central

    Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

    2015-01-01

    HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

  7. Hardware design and implementation of the closed-orbit feedback system at APS

    SciTech Connect

    Barr, D.; Chung, Youngjoo

    1996-10-01

    The Advanced Photon Source (APS) storage ring will utilize a closed-orbit feedback system in order to produce a more stable beam. The specified orbit measurement resolution is 25 microns for global feedback and 1 micron for local feedback. The system will sample at 4 kHz and provide a correction bandwidth of 100 Hz. At this bandwidth, standard rf BPMs will provide a resolution of 0.7 micron, while specialized miniature BPMs positioned on either side of the insertion devices for local feedback will provide a resolution of 0.2 micron (1). The measured BPM noise floor for standard BPMs is 0.06 micron per root hertz mA. Such a system has been designed, simulated, and tested on a small scale (2). This paper covers the actual hardware design and layout of the entire closed-loop system. This includes commercial hardware components, in addition to many components designed and built in-house. The paper will investigate the large-scale workings of all these devices, as well as an overall view of each piece of hardware used.

  8. Hardware accelerator design for change detection in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Chaudhury, Santanu; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

  9. Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

    NASA Technical Reports Server (NTRS)

    Shah, A. M.; Shiva, S. G.

    1981-01-01

    The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

  10. Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

  11. Energy efficient engine: fan test hardware detailed design report

    SciTech Connect

    Sullivan, T.J.

    1980-10-01

    A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

  12. Energy efficient engine: Fan test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Sullivan, T. J.

    1980-01-01

    A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

  13. Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

    PubMed Central

    Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

    2014-01-01

    In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. PMID:24672292

  14. RF control hardware design for CYCIAE-100 cyclotron

    NASA Astrophysics Data System (ADS)

    Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-01

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  15. Design of Test Support Hardware for Advanced Space Suits

    NASA Technical Reports Server (NTRS)

    Watters, Jeffrey A.; Rhodes, Richard

    2013-01-01

    As a member of the Space Suit Assembly Development Engineering Team, I designed and built test equipment systems to support the development of the next generation of advanced space suits. During space suit testing it is critical to supply the subject with two functions: (1) cooling to remove metabolic heat, and (2) breathing air to pressurize the space suit. The objective of my first project was to design, build, and certify an improved Space Suit Cooling System for manned testing in a 1-G environment. This design had to be portable and supply a minimum cooling rate of 2500 BTU/hr. The Space Suit Cooling System is a robust, portable system that supports very high metabolic rates. It has a highly adjustable cool rate and is equipped with digital instrumentation to monitor the flowrate and critical temperatures. It can supply a variable water temperature down to 34 deg., and it can generate a maximum water flowrate of 2.5 LPM. My next project was to design and build a Breathing Air System that was capable of supply facility air to subjects wearing the Z-2 space suit. The system intakes 150 PSIG breathing air and regulates it to two operating pressures: 4.3 and 8.3 PSIG. It can also provide structural capabilities at 1.5x operating pressure: 6.6 and 13.2 PSIG, respectively. It has instrumentation to monitor flowrate, as well as inlet and outlet pressures. The system has a series of relief valves to fully protect itself in case of regulator failure. Both projects followed a similar design methodology. The first task was to perform research on existing concepts to develop a sufficient background knowledge. Then mathematical models were developed to size components and simulate system performance. Next, mechanical and electrical schematics were generated and presented at Design Reviews. After the systems were approved by the suit team, all the hardware components were specified and procured. The systems were then packaged, fabricated, and thoroughly tested. The next step

  16. Pyroshock Simulation Systems: Are We Correctly Qualifying Flight Hardware for Pyroshock Environments?

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Nayeri, Reza; Kern, Dennis L.

    2009-01-01

    There are several methods of shock testing that are commonly used by the aerospace industry to qualify flight hardware to pyroshock environments. In some cases the shock results and in particular the shock response spectra computed from these tests were interpreted in such a way as to satisfy the testing requirements and were often considered successful for flight hardware qualification. However, close scrutiny of these acquired shock data suggest gross violation of the pyroshock qualification requirements. There are several issues, both in terms of the shock generation mechanisms and the shock signature acquisition and analysis that have led to improper qualification of flight hardware. In this paper some factors contributing to the misinterpretation of the shock data are reviewed. First, issues with the hardware fixturing and instrumentation that may lead to incorrect shock testing are discussed. Second, issues facing the shock simulation systems and pyrotechnic testing are reviewed. Finally, issues pertaining to the data acquisition and analysis are briefly discussed.

  17. Functional design specification for Stowage List And Hardware Tracking System (SLAHTS). [space shuttles

    NASA Technical Reports Server (NTRS)

    Keltner, D. J.

    1975-01-01

    This functional design specification defines the total systems approach to meeting the requirements stated in the Detailed Requirements Document for Stowage List and Hardware Tracking System for the space shuttle program. The stowage list and hardware tracking system is identified at the system and subsystem level with each subsystem defined as a function of the total system.

  18. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  19. Designing Epistemologically Correct Science Narratives

    ERIC Educational Resources Information Center

    Sachin, Datt; Poovaiah, Ravi

    2012-01-01

    In recent years use of narratives for teaching science at secondary school level has gained impetus. This paper deals with the problem of designing narratives for teaching scientific concept. The central issue of the problem of designing narratives for carrying scientific information is that science belongs to the domain of objective observation…

  20. Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

  1. Design of coupling resistor networks for neural network hardware

    NASA Astrophysics Data System (ADS)

    Barkan, Ozdal; Smith, W. R.; Persky, George

    1990-06-01

    The specification of an artificial neural network includes (1) the transformation relating each neuron's output voltage to its input voltage, and (2) a set of coupling weight factors expressing the input voltage of any neuron as a linear combination of the output voltages of other neurons. In analog VLSI chips for direct hardware implementation of these networks, neurons are often represented by amplifier elements (e.g. operational amplifiers or opamps), and resistors or active transconductances are used to couple signals from the outputs of certain neurons to the inputs of other neurons. Each coupling conductance is proportional to a single, corresponding coupling weight only under the following 'ideal' conditions: (1) each opamp has negligible output impedance, and (2) the input voltage of each opamp is developed across a low-resistance sampling resistor that is not loaded by the opamp itself. By contrast, the output impedance of a practical opamp may not be negligible in comparison to that of the high-fan network that it drives, and the sampling resistances on the opamp inputs cannot be arbitrarily low lest the input voltages be corrupted by unavoidable opamp input voltage offsets.

  2. Energy efficient engine low-pressure compressor component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Michael, C. J.; Halle, J. E.

    1981-01-01

    The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

  3. Design methodology for optimal hardware implementation of wavelet transform domain algorithms

    NASA Astrophysics Data System (ADS)

    Johnson-Bey, Charles; Mickens, Lisa P.

    2005-05-01

    The work presented in this paper lays the foundation for the development of an end-to-end system design methodology for implementing wavelet domain image/video processing algorithms in hardware using Xilinx field programmable gate arrays (FPGAs). With the integration of the Xilinx System Generator toolbox, this methodology will allow algorithm developers to design and implement their code using the familiar MATLAB/Simulink development environment. By using this methodology, algorithm developers will not be required to become proficient in the intricacies of hardware design, thus reducing the design cycle and time-to-market.

  4. Multiple IMU system hardware interface design, volume 2

    NASA Technical Reports Server (NTRS)

    Landey, M.; Brown, D.

    1975-01-01

    The design of each system component is described. Emphasis is placed on functional requirements unique in this system, including data bus communication, data bus transmitters and receivers, and ternary-to-binary torquing decision logic. Mechanization drawings are presented.

  5. A Parameterized Design Framework for Hardware Implementation of Particle Filters

    DTIC Science & Technology

    2008-03-01

    explore differ- ent design options for implementing two different particle filtering applications on field-programmable gate arrays ( FPGAs ), and we present...associated results on trade-offs between area ( FPGA resource requirements) and execution speed. Index Terms — Field programmable gate arrays, Parallel...programmable gate arrays ( FPGAs ) is proposed to enable comprehensive design space exploration of the whole system with attention to the interaction

  6. Performance/price estimates for cortex-scale hardware: a design space exploration.

    PubMed

    Zaveri, Mazad S; Hammerstrom, Dan

    2011-04-01

    In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering.

  7. Energy efficient engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Zeisser, M. H.; Greene, W.; Dubiel, D. J.

    1982-01-01

    The combustor for the Energy Efficient Engine is an annular, two-zone component. As designed, it either meets or exceeds all program goals for performance, safety, durability, and emissions, with the exception of oxides of nitrogen. When compared to the configuration investigated under the NASA-sponsored Experimental Clean Combustor Program, which was used as a basis for design, the Energy Efficient Engine combustor component has several technology advancements. The prediffuser section is designed with short, strutless, curved-walls to provide a uniform inlet airflow profile. Emissions control is achieved by a two-zone combustor that utilizes two types of fuel injectors to improve fuel atomization for more complete combustion. The combustor liners are a segmented configuration to meet the durability requirements at the high combustor operating pressures and temperatures. Liner cooling is accomplished with a counter-parallel FINWALL technique, which provides more effective heat transfer with less coolant.

  8. Operational experience and design recommendations for teleoperated flight hardware

    NASA Technical Reports Server (NTRS)

    Burgess, T. W.; Kuban, D. P.; Hankins, W. W.; Mixon, R. W.

    1988-01-01

    Teleoperation (remote manipulation) will someday supplement/minimize astronaut extravehicular activity in space to perform such tasks as satellite servicing and repair, and space station construction and servicing. This technology is being investigated by NASA with teleoperation of two space-related tasks having been demonstrated at the Oak Ridge National Lab. The teleoperator experiments are discussed and the results of these experiments are summarized. The related equipment design recommendations are also presented. In addition, a general discussion of equipment design for teleoperation is also presented.

  9. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    NASA Astrophysics Data System (ADS)

    Yeh, Chi-Tsai; Wang, Chun-Hao; Huang, Ing-Jer; Wong, Weng-Fai

    2011-12-01

    Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  10. Co-design of software and hardware to implement remote sensing algorithms

    SciTech Connect

    Theiler, J. P.; Frigo, J.; Gokhale, M.; Szymanski, J. J.

    2001-01-01

    Both for offline searches through large data archives and for onboard computation at the sensor head, there is a growing need for ever-more rapid processing of remote sensing data. For many algorithms of use in remote sensing, the bulk of the processing takes place in an 'inner loop' with a large number of simple operations. For these algorithms, dramatic speedups can often be obtained with specialized hardware. The difficulty and expense of digital design continues to limit applicability of this approach, but the development of new design tools is making this approach more feasible, and some notable successes have been reported. On the other hand, it is often the case that processing can also be accelerated by adopting a more sophisticated algorithm design. Unfortunately, a more sophisticated algorithm is much harder to implement in hardware, so these approaches are often at odds with each other. With careful planning, however, it is sometimes possible to combine software and hardware design in such a way that each complements the other, and the final implementation achieves speedup that would not have been possible with a hardware-only or a software-only solution. We will in particular discuss the co-design of software and hardware to achieve substantial speedup of algorithms for multispectral image segmentation and for endmember identification.

  11. Conceptual Hardware Design for the Drama Service Channel Controller.

    DTIC Science & Technology

    1983-05-01

    likely at another site, is performed within the controller. Any of a variety of technologies could be used to implement the service channel controller...The technology selected for presentation in this report is based on statistical multiplexing. To provide a comparison, an implementation using fixed...from production, the design presented herein would be unworkable. A redesign using available technology would be very difficult. Vendor literature for

  12. Hardware Design and Testing of SUPERball, A Modular Tensegrity Robot

    NASA Technical Reports Server (NTRS)

    Sabelhaus, Andrew P.; Bruce, Jonathan; Caluwaerts, Ken; Chen, Yangxin; Lu, Dizhou; Liu, Yuejia; Agogino, Adrian K.; SunSpiral, Vytas; Agogino, Alice M.

    2014-01-01

    We are developing a system of modular, autonomous "tensegrity end-caps" to enable the rapid exploration of untethered tensegrity robot morphologies and functions. By adopting a self-contained modular approach, different end-caps with various capabilities (such as peak torques, or motor speeds), can be easily combined into new tensegrity robots composed of rods, cables, and actuators of different scale (such as in length, mass, peak loads, etc). As a first step in developing this concept, we are in the process of designing and testing the end-caps for SUPERball (Spherical Underactuated Planetary Exploration Robot), a project at the Dynamic Tensegrity Robotics Lab (DTRL) within NASA Ames's Intelligent Robotics Group. This work discusses the evolving design concepts and test results that have gone into the structural, mechanical, and sensing aspects of SUPERball. This representative tensegrity end-cap design supports robust and repeatable untethered mobility tests of the SUPERball, while providing high force, high displacement actuation, with a low-friction, compliant cabling system.

  13. The LSST calibration hardware system design and development

    NASA Astrophysics Data System (ADS)

    Ingraham, Patrick; Stubbs, Christopher W.; Claver, Charles; Lupton, Robert; Araujo, Constanza; Liang, Ming; Andrew, John; Barr, Jeff; Brannon, Kairn; Coughlin, Michael; Fisher-Lavine, Merlin; Gressler, William; Sebag, Jacques; Thomas, Sandrine; Wiecha, Oliver; Yoachim, Peter

    2016-08-01

    The Large Synoptic Survey Telescope (LSST) is currently under construction and upon completion will perform precision photometry over the visible sky at a 3-day cadence. To meet the stringent relative photometry goals, LSST will employ multiple calibration systems to measure and compensate for systematic errors. This paper describes the design and development of these systems including: a dedicated calibration telescope and spectrograph to measure the atmospheric transmission function, a collimated beam projector to characterize the spatial dependence of the LSST transmission function and an at-field screen illumination system to measure the high-frequency variations in the global system response function.

  14. Hardware and circuit design of a vibrational cleaner

    NASA Astrophysics Data System (ADS)

    Fhong Soon, Chin; Thong, Kok Tung; Sek Tee, Kian; Nayan, Nafarizal; Khairul Ahmad, Mohd; Nurashikin Nordin, Anis

    2016-11-01

    Microtissue can be grown on soft substrates of hydrogel or liquid crystal gel. These gels are adherent to the microtissues and they may interfere fluorescence imaging as background noise due to their absorbance property. A microfluidic vibrational cleaner with polydimethylsiloxane (PDMS) microfluidic chip platform was proposed and developed to remove the residual gel of liquid crystal adhered to the microtissues. The microtissues were placed in a microfluidic chip attaching to a microfluidic vibrational platform. In the system design, two motorised vibrators vibrating attached to a microfluidic platform and generating vibration signals at 148 Hz and 0.89 Grms to clean the microtissues. The acceleration of the vibration increased gradually from 0 to 0.96 Grms when the duty cycle of PWM pulses increased from 50 - 90%. It dropped slightly to 0.89 Grms at 100% duty cycle. Irrigation water valve was designed to control the fluid flow from water pump during cleaning process. Water pumps were included to flush the channels of the microfluidic device. The signals in controlling the pump, motor and valve were linearly proportional to the duty cycles of the pulse width modulation signals generated from a microcontroller.

  15. OpenPET Hardware, Firmware, Software, and Board Design Files

    SciTech Connect

    Abu-Nimeh, Faisal; Choong, Woon-Sengq; Moses, William W.; Peng, Qiyu

    2016-03-29

    OpenPET is an open source, flexible, high-performance, and modular data acquisition system for a variety of applications. The OpenPET electronics are capable of reading analog voltage or current signals from a wide variety of sensors. The electronics boards make extensive use of field programmable gate arrays (FPGAs) to provide flexibility and scalability. Firmware and software for the FPGAs and computer are used to control and acquire data from the system. The command and control flow is similar to the data flow, however, the commands are initiated from the computer similar to a tree topology (i.e., from top-to-bottom). Each node in the tree discovers its parent and children, and all addresses are configured accordingly. A user (or a script) initiates a command from the computer. This command will be translated and encoded to the corresponding child (e.g., SB, MB, DB, etc.). Consecutively, each node will pass the command to its corresponding child(ren) by looking at the destination address. Finally, once the command reaches its desired destination(s) the corresponding node(s) execute(s) the command and send(s) a reply, if required. All the firmware, software, and the electronics board design files are distributed through the OpenPET website (http://openpet.lbl.gov).

  16. Rapid resorption of calcium sulfate and hardware failure following corrective radius osteotomy: 2 case reports.

    PubMed

    Jepegnanam, Thilak S; von Schroeder, Herbert P

    2012-03-01

    Bone substitutes are being increasingly used and may avert the need for autogenous bone graft in orthopedic surgery. Thus it is important to note complications that occur with them to better understand the limitations. We report on early mechanical failure of injectable calcium sulfate leading to implant failure in 2 elderly patients who had corrective osteotomies for malunited distal radius fractures. We hypothesize that these occurred because there was inadequate new bone formation to replace the resorbing bone substitute. We advise caution when using bone substitutes in patients with expected delayed fracture healing.

  17. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    PubMed

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

  18. Study of the adaptability of existing hardware designs to a Pioneer Saturn/Uranus probe

    NASA Technical Reports Server (NTRS)

    1973-01-01

    The basic concept of designing a scientific entry probe for the expected range of environments at Saturn or Uranus and making the probe compatible with the interface constraints of the Pioneer spacecraft was investigated for launches in the early 1980's. It was found that the amount of hardware commonality between that used in the Pioneer Venus program and that for the Saturn/Uranus probe was approximately 85%. It is recommended that additional development studies be conducted to improve the hardware definitions of the probe design for the following: heat shield, battery, nose cap jettisoning, and thermal control insulation.

  19. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits.

    PubMed

    Kapit, Eliot

    2016-04-15

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T_{1} and T_{2} using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity.

  20. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    2016-04-01

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T1 and T2 using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity.

  1. Design Considerations in Development of Minicomputer-Based Computer Aided Instructional Hardware Systems.

    ERIC Educational Resources Information Center

    Wells, C. H.

    A minicomputer-based computer-assisted instructional (CAI) system was designed at the University of Texas Medical Branch in an attempt to lower both the excessive hardware costs and the inordinate amount of time required for the preparation of each hour of instructional material associated with traditional CAI systems. A prototype system with an…

  2. The design of flight hardware: Organizational and technical ideas from the MITRE/WPI Shuttle Program

    NASA Technical Reports Server (NTRS)

    Looft, F. J.

    1986-01-01

    The Mitre Corporation of Bedford Mass. and the Worcester Polytechnic Institute are developing several experiments for a future Shuttle flight. Several design practices for the development of the electrical equipment for the flight hardware have been standardized. Some of the ideas are presented, not as hard and fast rules but rather in the interest of stimulating discussions for sharing such ideas.

  3. Test Hardware Design for Flightlike Operation of Advanced Stirling Convertors (ASC-E3)

    NASA Technical Reports Server (NTRS)

    Oriti, Salvatore M.

    2012-01-01

    NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

  4. A Comprehensive Reliability Methodology for Assessing Risk of Reusing Failed Hardware Without Corrective Actions with and Without Redundancy

    NASA Technical Reports Server (NTRS)

    Putcha, Chandra S.; Mikula, D. F. Kip; Dueease, Robert A.; Dang, Lan; Peercy, Robert L.

    1997-01-01

    This paper deals with the development of a reliability methodology to assess the consequences of using hardware, without failure analysis or corrective action, that has previously demonstrated that it did not perform per specification. The subject of this paper arose from the need to provide a detailed probabilistic analysis to calculate the change in probability of failures with respect to the base or non-failed hardware. The methodology used for the analysis is primarily based on principles of Monte Carlo simulation. The random variables in the analysis are: Maximum Time of Operation (MTO) and operation Time of each Unit (OTU) The failure of a unit is considered to happen if (OTU) is less than MTO for the Normal Operational Period (NOP) in which this unit is used. NOP as a whole uses a total of 4 units. Two cases are considered. in the first specialized scenario, the failure of any operation or system failure is considered to happen if any of the units used during the NOP fail. in the second specialized scenario, the failure of any operation or system failure is considered to happen only if any two of the units used during the MOP fail together. The probability of failure of the units and the system as a whole is determined for 3 kinds of systems - Perfect System, Imperfect System 1 and Imperfect System 2. in a Perfect System, the operation time of the failed unit is the same as that of the MTO. In an Imperfect System 1, the operation time of the failed unit is assumed as 1 percent of the MTO. In an Imperfect System 2, the operation time of the failed unit is assumed as zero. in addition, simulated operation time of failed units is assumed as 10 percent of the corresponding units before zero value. Monte Carlo simulation analysis is used for this study. Necessary software has been developed as part of this study to perform the reliability calculations. The results of the analysis showed that the predicted change in failure probability (P(sub F)) for the

  5. Object oriented design (OOD) in real-time hardware-in-the-loop (HWIL) simulations

    NASA Astrophysics Data System (ADS)

    Morris, Joe; Richard, Henri; Lowman, Alan; Youngren, Rob

    2006-05-01

    Using Object Oriented Design (OOD) concepts in AMRDEC's Hardware-in-the Loop (HWIL) real-time simulations allows the user to interchange parts of the simulation to meet test requirements. A large-scale three-spectral band simulator connected via a high speed reflective memory ring for time-critical data transfers to PC controllers connected by non real-time Ethernet protocols is used to separate software objects from logical entities close to their respective controlled hardware. Each standalone object does its own dynamic initialization, real-time processing, and end of run processing; therefore it can be easily maintained and updated. A Resource Allocation Program (RAP) is also utilized along with a device table to allocate, organize, and document the communication protocol between the software and hardware components. A GUI display program lists all allocations and deallocations of HWIL memory and hardware resources. This interactive program is also used to clean up defunct allocations of dead processes. Three examples are presented using the OOD and RAP concepts. The first is the control of an ACUTRONICS built three-axis flight table using the same control for calibration and real-time functions. The second is the transportability of a six-degree-of-freedom (6-DOF) simulation from an Onyx residence to a Linux-PC. The third is the replacement of the 6-DOF simulation with a replay program to drive the facility with archived run data for demonstration or analysis purposes.

  6. The design and hardware implementation of a low-power real-time seizure detection algorithm.

    PubMed

    Raghunathan, Shriram; Gupta, Sumeet K; Ward, Matthew P; Worth, Robert M; Roy, Kaushik; Irazoqui, Pedro P

    2009-10-01

    Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 +/- 0.02% and 88.9 +/- 0.01% (mean +/- SE(alpha = 0.05)), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

  7. Rapid prototyping of an automated video surveillance system: a hardware-software co-design approach

    NASA Astrophysics Data System (ADS)

    Ngo, Hau T.; Rakvic, Ryan N.; Broussard, Randy P.; Ives, Robert W.

    2011-06-01

    FPGA devices with embedded DSP and memory blocks, and high-speed interfaces are ideal for real-time video processing applications. In this work, a hardware-software co-design approach is proposed to effectively utilize FPGA features for a prototype of an automated video surveillance system. Time-critical steps of the video surveillance algorithm are designed and implemented in the FPGAs logic elements to maximize parallel processing. Other non timecritical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Pre-tested and verified video and interface functions from a standard video framework are utilized to significantly reduce development and verification time. Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon Streaming video protocol. Other data control interfaces are achieved by connecting hardware controllers to a Nios-II processor using Altera's Avalon Memory Mapped protocol.

  8. Skylab SO71/SO72 circadian periodicity experiment. [experimental design and checkout of hardware

    NASA Technical Reports Server (NTRS)

    Fairchild, M. K.; Hartmann, R. A.

    1973-01-01

    The circadian rhythm hardware activities from 1965 through 1973 are considered. A brief history of the programs leading to the development of the combined Skylab SO71/SO72 Circadian Periodicity Experiment (CPE) is given. SO71 is the Skylab experiment number designating the pocket mouse circadian experiment, and SO72 designates the vinegar gnat circadian experiment. Final design modifications and checkout of the CPE, integration testing with the Apollo service module CSM 117 and the launch preparation and support tasks at Kennedy Space Center are reported.

  9. Corona streamer onset as an optimization criterion for design of high voltage hardware on transmission lines

    SciTech Connect

    Pedrow, P.D.; Olsen, R.G.

    1996-12-31

    To design hardware for compact high voltage lines it is necessary to predict conditions for which corona streamers are initiated. Existing techniques for optimizing hardware shape and calculating streamer onset are based on corona measurements in a coaxial geometry that uses concentric cylinders for electrodes. Peek`s law shows that the formation of corona streamers is related not only to electric field but also to surface curvature. It is not clear that Peek`s law (developed in a coaxial geometry for which radius of curvature in the axial direction is infinite) is appropriate for designing hardware surfaces which are defined at any point by two finite radii of curvature. In this work the authors seek a corona onset criterion for these more general surfaces which reduces to Peeks law in the limit that one of the radii of curvature is infinite. An existing electrostatic code is being modified to allow for iterative optimization of electrode shapes based on results of previous field calculations. Experimental corona performance testing of electrode shapes will take place in an air-filled chamber with ac voltage as high as 100 kV rms. Experiments will be used to evaluate various electrode shapes designed by the trial optimization criterion.

  10. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    SciTech Connect

    Kaiser, Alex; Williams, Samuel; Madduri, Kamesh; Ibrahim, Khaled; Bailey, David; Demmel, James; Strohmaier, Erich

    2010-04-01

    Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

  11. A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications.

    PubMed

    Raghunathan, Shriram; Gupta, Sumeet K; Markandeya, Himanshu S; Roy, Kaushik; Irazoqui, Pedro P

    2010-10-30

    Implantable neural prostheses that deliver focal electrical stimulation upon demand are rapidly emerging as an alternate therapy for roughly a third of the epileptic patient population that is medically refractory. Seizure detection algorithms enable feedback mechanisms to provide focally and temporally specific intervention. Real-time feasibility and computational complexity often limit most reported detection algorithms to implementations using computers for bedside monitoring or external devices communicating with the implanted electrodes. A comparison of algorithms based on detection efficacy does not present a complete picture of the feasibility of the algorithm with limited computational power, as is the case with most battery-powered applications. We present a two-dimensional design optimization approach that takes into account both detection efficacy and hardware cost in evaluating algorithms for their feasibility in an implantable application. Detection features are first compared for their ability to detect electrographic seizures from micro-electrode data recorded from kainate-treated rats. Circuit models are then used to estimate the dynamic and leakage power consumption of the compared features. A score is assigned based on detection efficacy and the hardware cost for each of the features, then plotted on a two-dimensional design space. An optimal combination of compared features is used to construct an algorithm that provides maximal detection efficacy per unit hardware cost. The methods presented in this paper would facilitate the development of a common platform to benchmark seizure detection algorithms for comparison and feasibility analysis in the next generation of implantable neuroprosthetic devices to treat epilepsy.

  12. Hardware design for a cable-free fully insertable wireless laparoscopic robotic camera.

    PubMed

    Ning Li; Mancini, Gregory J; Jindong Tan

    2016-08-01

    The field of insertable laparoscopic robotic camera is gaining increasing attentions from researchers, surgeons, and also patients. Although many insertable laparoscope prototypes have been introduced, few of them get rid of the encumbrance tethering cable. In this paper, we proposed a hardware architecture for a magnetic actuated robotic surgical (MARS) camera, which facilitates a cable-free fully insertable laparoscopic surgical robotic camera with adequate in-vivo mobility. Modular design and preliminary test of on-board functional payloads have shown feasibility of a cable-free insertable wireless laparoscopic surgical camera based on off-the-shelf electronics and industrial wireless standards operating in ISM frequency bands at 2.4GHz. Potential improvements for laparoscopic surgery benefited from this hardware architecture include more dexterous in-vivo camera mobility and intuitive closed-loop robotic camera control.

  13. Thermal Performance of a Customized Multilayer Insulation (MLI). Design and Fabrication of Test Facility Hardware

    NASA Technical Reports Server (NTRS)

    Leonhard, K. E.

    1975-01-01

    The design, fabrication, and assembly of hardware for testing the performance of a customized multilayer insulation are discussed. System components described include the thermal payload simulator, the modified cryoshroud, and a tank back pressure control device designed to maintain a constant liquid boiling point during the thermal evaluation of the multilayer insulation. The thermal payload simulator will provide a constant temperature surface in the range of 20.5 to 417K (37 to 750R) for the insulated tank to view. The cryoshroud was modified to establish a low temperature black body cavity while limiting liquid hydrogen usage to a minimum feasible rate.

  14. A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

    PubMed

    Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

    2009-01-01

    For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

  15. AirSTAR Hardware and Software Design for Beyond Visual Range Flight Research

    NASA Technical Reports Server (NTRS)

    Laughter, Sean; Cox, David

    2016-01-01

    The National Aeronautics and Space Administration (NASA) Airborne Subscale Transport Aircraft Research (AirSTAR) Unmanned Aerial System (UAS) is a facility developed to study the flight dynamics of vehicles in emergency conditions, in support of aviation safety research. The system was upgraded to have its operational range significantly expanded, going beyond the line of sight of a ground-based pilot. A redesign of the airborne flight hardware was undertaken, as well as significant changes to the software base, in order to provide appropriate autonomous behavior in response to a number of potential failures and hazards. Ground hardware and system monitors were also upgraded to include redundant communication links, including ADS-B based position displays and an independent flight termination system. The design included both custom and commercially available avionics, combined to allow flexibility in flight experiment design while still benefiting from tested configurations in reversionary flight modes. A similar hierarchy was employed in the software architecture, to allow research codes to be tested, with a fallback to more thoroughly validated flight controls. As a remotely piloted facility, ground systems were also developed to ensure the flight modes and system state were communicated to ground operations personnel in real-time. Presented in this paper is a general overview of the concept of operations for beyond visual range flight, and a detailed review of the airborne hardware and software design. This discussion is held in the context of the safety and procedural requirements that drove many of the design decisions for the AirSTAR UAS Beyond Visual Range capability.

  16. Design and control of compliant tensegrity robots through simulation and hardware validation

    PubMed Central

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity (‘tensile–integrity’) structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

  17. Design and control of compliant tensegrity robots through simulation and hardware validation.

    PubMed

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-09-06

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ('tensile-integrity') structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation.

  18. Design and Control of Compliant Tensegrity Robots Through Simulation and Hardware Validation

    NASA Technical Reports Server (NTRS)

    Caluwaerts, Ken; Despraz, Jeremie; Iscen, Atil; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; Sunspiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center has developed and validated two different software environments for the analysis, simulation, and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ("tensile-integrity") structures have unique physical properties which make them ideal for interaction with uncertain environments. Yet these characteristics, such as variable structural compliance, and global multi-path load distribution through the tension network, make design and control of bio-inspired tensegrity robots extremely challenging. This work presents the progress in using these two tools in tackling the design and control challenges. The results of this analysis includes multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures. The current hardware prototype of a six-bar tensegrity, code-named ReCTeR, is presented in the context of this validation.

  19. Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

    NASA Technical Reports Server (NTRS)

    French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

    2005-01-01

    The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

  20. Combined Cycle Engine Large-Scale Inlet for Mode Transition Experiments: System Identification Rack Hardware Design

    NASA Technical Reports Server (NTRS)

    Thomas, Randy; Stueber, Thomas J.

    2013-01-01

    The System Identification (SysID) Rack is a real-time hardware-in-the-loop data acquisition (DAQ) and control instrument rack that was designed and built to support inlet testing in the NASA Glenn Research Center 10- by 10-Foot Supersonic Wind Tunnel. This instrument rack is used to support experiments on the Combined-Cycle Engine Large-Scale Inlet for Mode Transition Experiment (CCE? LIMX). The CCE?LIMX is a testbed for an integrated dual flow-path inlet configuration with the two flow paths in an over-and-under arrangement such that the high-speed flow path is located below the lowspeed flow path. The CCE?LIMX includes multiple actuators that are designed to redirect airflow from one flow path to the other; this action is referred to as "inlet mode transition." Multiple phases of experiments have been planned to support research that investigates inlet mode transition: inlet characterization (Phase-1) and system identification (Phase-2). The SysID Rack hardware design met the following requirements to support Phase-1 and Phase-2 experiments: safely and effectively move multiple actuators individually or synchronously; sample and save effector control and position sensor feedback signals; automate control of actuator positioning based on a mode transition schedule; sample and save pressure sensor signals; and perform DAQ and control processes operating at 2.5 KHz. This document describes the hardware components used to build the SysID Rack including their function, specifications, and system interface. Furthermore, provided in this document are a SysID Rack effectors signal list (signal flow); system identification experiment setup; illustrations indicating a typical SysID Rack experiment; and a SysID Rack performance overview for Phase-1 and Phase-2 experiments. The SysID Rack described in this document was a useful tool to meet the project objectives.

  1. The role of hardware in learning engineering fundamentals: An empirical study of engineering design and product analysis activity

    NASA Astrophysics Data System (ADS)

    Brereton, Margot Felicity

    A series of short engineering exercises and design projects was created to help students learn to apply abstract knowledge to physical experiences with hardware. The exercises involved designing machines from kits of materials and dissecting and analyzing familiar household products. Students worked in teams. During the activities students brought their knowledge of engineering fundamentals to bear. Videotape analysis was used to identify and characterize the ways in which hardware contributed to learning fundamental concepts. Structural and qualitative analyses of videotaped activities were undertaken. Structural analysis involved counting the references to theory and hardware and the extent of interleaving of references in activity. The analysis found that there was much more discussion linking fundamental concepts to hardware in some activities than in others. The analysis showed that the interleaving of references to theory and hardware in activity is observable and quantifiable. Qualitative analysis was used to investigate the dialog linking concepts and hardware. Students were found to advance their designs and their understanding of engineering fundamentals through a negotiation process in which they pitted abstract concepts against hardware behavior. Through this process students sorted out theoretical assumptions and causal relations. In addition they discovered design assumptions, functional connections and physical embodiments of abstract concepts in hardware, developing a repertoire of familiar hardware components and machines. Hardware was found to be integral to learning, affecting the course of inquiry and the dynamics of group interaction. Several case studies are presented to illustrate the processes at work. The research illustrates the importance of working across the boundary between abstractions and experiences with hardware in order to learn engineering and physical sciences. The research findings are: (a) the negotiation process by which

  2. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  3. A Hardware Design For Topographical Classification Of Pixels In An Image

    NASA Astrophysics Data System (ADS)

    Salari, Ezzatollah; Bumrungthum, Paisit

    1988-10-01

    The gray level geographical structure (GLGS) is a simple method to represent the local intensity variation of an image in symbolic description. This representation can be used in higher level image processing in subsequent steps. The advent of VLSI microelectronic technology has led to the idea of implementing the GLGS directly in hardware. A two dimensional pipelined systolic pixel classification array is proposed in this paper. In the design, each pair of processing elements processes the data in a pipelined fashion and the data in each pair of processing elements is processed in a parallel fashion to further enhance the system performance.

  4. Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

    NASA Astrophysics Data System (ADS)

    Lata Murotiya, Sneh; Gupta, Anu

    2016-05-01

    This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

  5. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain.

    PubMed

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-08-04

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture.

  6. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain

    PubMed Central

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-01-01

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture. PMID:27527180

  7. Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.; Shah, A. M.

    1980-01-01

    The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

  8. Preliminary design of flight hardware for two-phase fluid research

    NASA Technical Reports Server (NTRS)

    Hustvedt, D. C.; Oonk, R. L.

    1982-01-01

    This study defined the preliminary designs of flight software for the Space Shuttle Orbiter for three two-phase fluid research experiments: (1) liquid reorientation - to study the motion of liquid in tanks subjected to small accelerations; (2) pool boiling - to study low-gravity boiling from horizontal cylinders; and (3) flow boiling - to study low-gravity forced flow boiling heat transfer and flow phenomena in a heated horizontal tube. The study consisted of eight major tasks: reassessment of the existing experiment designs, assessment of the Spacelab facility approach, assessment of the individual carry-on approach, selection of the preferred approach, preliminary design of flight hardware, safety analysis, preparation of a development plan, estimates of detailed design, fabrication and ground testing costs. The most cost effective design approach for the experiments is individual carry-ons in the Orbiter middeck. The experiments were designed to fit into one or two middeck lockers. Development schedules for the detailed design, fabrication and ground testing ranged from 15 1/2 to 18 months. Minimum costs (in 1981 dollars) ranged from $463K for the liquid reorientation experiment to $998K for the pool boiling experiment.

  9. Design of a terminal node controller hardware for CubeSat tracking applications

    NASA Astrophysics Data System (ADS)

    Ahmad, Y. A.; Nazim, N. J.; Yuhaniz, S. S.

    2016-10-01

    CubeSats enable low-cost experiment and missions to be performed by universities and research institution in space. CubeSats for research use UHF and VHF communication for its tracking and telemetry applications. The current practice of a CubeSat communication is to modify radio amateur's Terminal Node Controller (TNC) to enable data to be received in the ground station. The objective of this research is to design a hardware specifically for use as a TNC for CubeSat tracking applications. A TNC is developed as an interface to the terminal and to serve as data packetization platform. The modem is integrated with a microcontroller unit (MCU) and an audio amplifier to enable the audio signals to be smoothened, amplified and interfaced with the radio. The modem, MCU and audio amplifier circuitry are designed and integrated to form a TNC platform suitable for CubeSat communication.

  10. Acoustical Testing Laboratory Developed to Support the Low-Noise Design of Microgravity Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Cooper, Beth A.

    2001-01-01

    The NASA John H. Glenn Research Center at Lewis Field has designed and constructed an Acoustical Testing Laboratory to support the low-noise design of microgravity space flight hardware. This new laboratory will provide acoustic emissions testing and noise control services for a variety of customers, particularly for microgravity space flight hardware that must meet International Space Station limits on noise emissions. These limits have been imposed by the space station to support hearing conservation, speech communication, and safety goals as well as to prevent noise-induced vibrations that could impact microgravity research data. The Acoustical Testing Laboratory consists of a 23 by 27 by 20 ft (height) convertible hemi/anechoic chamber and separate sound-attenuating test support enclosure. Absorptive 34-in. fiberglass wedges in the test chamber provide an anechoic environment down to 100 Hz. A spring-isolated floor system affords vibration isolation above 3 Hz. These criteria, along with very low design background levels, will enable the acquisition of accurate and repeatable acoustical measurements on test articles, up to a full space station rack in size, that produce very little noise. Removable floor wedges will allow the test chamber to operate in either a hemi/anechoic or anechoic configuration, depending on the size of the test article and the specific test being conducted. The test support enclosure functions as a control room during normal operations but, alternatively, may be used as a noise-control enclosure for test articles that require the operation of noise-generating test support equipment.

  11. Structural Design Requirements and Factors of Safety for Spaceflight Hardware: For Human Spaceflight. Revision A

    NASA Technical Reports Server (NTRS)

    Bernstein, Karen S.; Kujala, Rod; Fogt, Vince; Romine, Paul

    2011-01-01

    This document establishes the structural requirements for human-rated spaceflight hardware including launch vehicles, spacecraft and payloads. These requirements are applicable to Government Furnished Equipment activities as well as all related contractor, subcontractor and commercial efforts. These requirements are not imposed on systems other than human-rated spacecraft, such as ground test articles, but may be tailored for use in specific cases where it is prudent to do so such as for personnel safety or when assets are at risk. The requirements in this document are focused on design rather than verification. Implementation of the requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each structural item for the applicable requirements. The SVP may also document unique verifications that meet or exceed these requirements with NASA Technical Authority approval.

  12. Final Scientific/Technical Report for "Enabling Exascale Hardware and Software Design through Scalable System Virtualization"

    SciTech Connect

    Dinda, Peter August

    2015-03-17

    This report describes the activities, findings, and products of the Northwestern University component of the "Enabling Exascale Hardware and Software Design through Scalable System Virtualization" project. The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems software for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3

  13. Streamlined design and self reliant hardware for active control of precision space structures

    NASA Technical Reports Server (NTRS)

    Hyland, David C.; King, James A.; Phillips, Douglas J.

    1994-01-01

    Precision space structures may require active vibration control to satisfy critical performance requirements relating to line-of-sight pointing accuracy and the maintenance of precise, internal alignments. In order for vibration control concepts to become operational, it is necessary that their benefits be practically demonstrated in large scale ground-based experiments. A unique opportunity to carry out such demonstrations on a wide variety of experimental testbeds was provided by the NASA Control-Structure Integration (CSI) Guest Investigator (GI) Program. This report surveys the experimental results achieved by the Harris Corporation GI team on both Phases 1 and 2 of the program and provides a detailed description of Phase 2 activities. The Phase 1 results illustrated the effectiveness of active vibration control for space structures and demonstrated a systematic methodology for control design, implementation test. In Phase 2, this methodology was significantly streamlined to yield an on-site, single session design/test capability. Moreover, the Phase 2 research on adaptive neural control techniques made significant progress toward fully automated, self-reliant space structure control systems. As a further thrust toward productized, self-contained vibration control systems, the Harris Phase II activity concluded with experimental demonstration of new vibration isolation hardware suitable for a wide range of space-flight and ground-based commercial applications.The CSI GI Program Phase 1 activity was conducted under contract NASA1-18872, and the Phase 2 activity was conducted under NASA1-19372.

  14. Space Technology 5: Changing the Mission Design without Changing the Hardware

    NASA Technical Reports Server (NTRS)

    Carlisle, Candace C.; Webb, Evan H.; Slavin, James A.

    2005-01-01

    The Space Technology 5 (ST-5) Project is part of NASA's New Millennium Program. The validation objectives are to demonstrate the research-quality science capability of the ST-5 spacecraft; to operate the three spacecraft as a constellation; and to design, develop, test and flight-validate three capable micro-satellites with new technologies. A three-month flight demonstration phase is planned, beginning in March 2006. This year, the mission was re-planned for a Pegasus XL dedicated launch into an elliptical polar orbit (instead of the Originally-planned Geosynchronous Transfer Orbit.) The re-plan allows the mission to achieve the same high-level technology validation objectives with a different launch vehicle. The new mission design involves a revised science validation strategy, a new orbit and different communication strategy, while minimizing changes to the ST-5 spacecraft itself. The constellation operations concepts have also been refined. While the system engineers, orbit analysts, and operations teams were re-planning the mission, the implementation team continued to make progress on the flight hardware. Most components have been delivered, and the first spacecraft is well into integration and test.

  15. Modeling and Compensation Design for a Power Hardware-in-the-Loop Simulation of an AC Distribution System

    SciTech Connect

    Ainsworth, Nathan; Hariri, Ali; Prabakar, Kumaraguru; Pratt, Annabelle; Baggu, Murali

    2016-11-21

    Power hardware-in-the-loop (PHIL) simulation, where actual hardware under text is coupled with a real-time digital model in closed loop, is a powerful tool for analyzing new methods of control for emerging distributed power systems. However, without careful design and compensation of the interface between the simulated and actual systems, PHIL simulations may exhibit instability and modeling inaccuracies. This paper addresses issues that arise in the PHIL simulation of a hardware battery inverter interfaced with a simulated distribution feeder. Both the stability and accuracy issues are modeled and characterized, and a methodology for design of PHIL interface compensation to ensure stability and accuracy is presented. The stability and accuracy of the resulting compensated PHIL simulation is then shown by experiment.

  16. Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm

    NASA Astrophysics Data System (ADS)

    Charoensak, Charayaphan; Sattar, Farook

    2005-12-01

    Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multisensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkola's BSS algorithm for audio signals based on ICA (independent component analysis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented. Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given.

  17. Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

    PubMed Central

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-01-01

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

  18. Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

    PubMed

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-10-16

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

  19. Simulation verification techniques study: Simulation self test hardware design and techniques report

    NASA Technical Reports Server (NTRS)

    1974-01-01

    The final results are presented of the hardware verification task. The basic objectives of the various subtasks are reviewed along with the ground rules under which the overall task was conducted and which impacted the approach taken in deriving techniques for hardware self test. The results of the first subtask and the definition of simulation hardware are presented. The hardware definition is based primarily on a brief review of the simulator configurations anticipated for the shuttle training program. The results of the survey of current self test techniques are presented. The data sources that were considered in the search for current techniques are reviewed, and results of the survey are presented in terms of the specific types of tests that are of interest for training simulator applications. Specifically, these types of tests are readiness tests, fault isolation tests and incipient fault detection techniques. The most applicable techniques were structured into software flows that are then referenced in discussions of techniques for specific subsystems.

  20. Energy Efficient Engine: High-pressure compressor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Howe, David C.; Marchant, R. D.

    1988-01-01

    The objective of the NASA Energy Efficient Engine program is to identify and verify the technology required to achieve significant reductions in fuel consumption and operating cost for future commercial gas turbine engines. The design and analysis is documented of the high pressure compressor which was tested as part of the Pratt and Whitney effort under the Energy Efficient Engine program. This compressor was designed to produce a 14:1 pressure ratio in ten stages with an adiabatic efficiency of 88.2 percent in the flight propulsion system. The corresponding expected efficiency for the compressor component test rig is 86.5 percent. Other performance goals are a surge margin of 20 percent, a corrected flow rate of 35.2 kg/sec (77.5 lb/sec), and a life of 20,000 missions and 30,000 hours. Low loss, highly loaded airfoils are used to increase efficiency while reducing the parts count. Active clearance control and case trenches in abradable strips over the blade tips are included in the compressor component design to further increase the efficiency potential. The test rig incorporates variable geometry stator vanes in all stages to permit maximum flexibility in developing stage-to-stage matching. This provision precluded active clearance control on the rear case of the test rig. Both the component and rig designs meet or exceed design requirements with the exception of life goals, which will be achievable with planned advances in materials technology.

  1. A parallel algorithm for error correction in high-throughput short-read data on CUDA-enabled graphics hardware.

    PubMed

    Shi, Haixiang; Schmidt, Bertil; Liu, Weiguo; Müller-Wittig, Wolfgang

    2010-04-01

    Emerging DNA sequencing technologies open up exciting new opportunities for genome sequencing by generating read data with a massive throughput. However, produced reads are significantly shorter and more error-prone compared to the traditional Sanger shotgun sequencing method. This poses challenges for de novo DNA fragment assembly algorithms in terms of both accuracy (to deal with short, error-prone reads) and scalability (to deal with very large input data sets). In this article, we present a scalable parallel algorithm for correcting sequencing errors in high-throughput short-read data so that error-free reads can be available before DNA fragment assembly, which is of high importance to many graph-based short-read assembly tools. The algorithm is based on spectral alignment and uses the Compute Unified Device Architecture (CUDA) programming model. To gain efficiency we are taking advantage of the CUDA texture memory using a space-efficient Bloom filter data structure for spectrum membership queries. We have tested the runtime and accuracy of our algorithm using real and simulated Illumina data for different read lengths, error rates, input sizes, and algorithmic parameters. Using a CUDA-enabled mass-produced GPU (available for less than US$400 at any local computer outlet), this results in speedups of 12-84 times for the parallelized error correction, and speedups of 3-63 times for both sequential preprocessing and parallelized error correction compared to the publicly available Euler-SR program. Our implementation is freely available for download from http://cuda-ec.sourceforge.net .

  2. Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks

    NASA Technical Reports Server (NTRS)

    Lee, Y. H.; Shin, K. G.

    1982-01-01

    A fault-tolerant multiprocessor with a rollback recovery mechanism is discussed. The rollback mechanism is based on the hardware recovery block which is a hardware equivalent to the software recovery block. The hardware recovery block is constructed by consecutive state-save operations and several state-save units in every processor and memory module. When a fault is detected, the multiprocessor reconfigures itself to replace the faulty component and then the process originally assigned to the faulty component retreats to one of the previously saved states in order to resume fault-free execution. A mathematical model is proposed to calculate both the coverage of multi-step rollback recovery and the risk of restart. A performance evaluation in terms of task execution time is also presented.

  3. The design of a hardware testing system for the D Zero Detector

    SciTech Connect

    Angstadt, R.; Johnson, M.; Martin, M.; Matulik, M.; Utes, M.

    1991-11-01

    Testing a system as large as the D Zero data acquisition system is difficult. This paper describes the use of IBM compatible personal computers in a hardware test system that can run on any size system from an engineer`s test bench to the entire subsystem in the D Zero Detector. The test system uses a PC to VME bus interface for the local testing and the Token Ring network for more global testing. This system has been implemented for several different hardware systems in D Zero.

  4. Hardware-Algorithms Co-Design and Implementation of an Analog-to-Information Converter for Biosignals Based on Compressed Sensing.

    PubMed

    Pareschi, Fabio; Albertini, Pierluigi; Frattini, Giovanni; Mangia, Mauro; Rovatti, Riccardo; Setti, Gianluca

    2016-02-01

    We report the design and implementation of an Analog-to-Information Converter (AIC) based on Compressed Sensing (CS). The system is realized in a CMOS 180 nm technology and targets the acquisition of bio-signals with Nyquist frequency up to 100 kHz. To maximize performance and reduce hardware complexity, we co-design hardware together with acquisition and reconstruction algorithms. The resulting AIC outperforms previously proposed solutions mainly thanks to two key features. First, we adopt a novel method to deal with saturations in the computation of CS measurements. This allows no loss in performance even when 60% of measurements saturate. Second, the system is able to adapt itself to the energy distribution of the input by exploiting the so-called rakeness to maximize the amount of information contained in the measurements. With this approach, the 16 measurement channels integrated into a single device are expected to allow the acquisition and the correct reconstruction of most biomedical signals. As a case study, measurements on real electrocardiograms (ECGs) and electromyograms (EMGs) show signals that these can be reconstructed without any noticeable degradation with a compression rate, respectively, of 8 and 10.

  5. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  6. Design of the high-speed framing, FEC, and interleaving hardware used in a 5.4km free-space optical communication experiment

    NASA Astrophysics Data System (ADS)

    Greco, Joseph A.

    2009-08-01

    The forward error correction (FEC) and interleaver realizations used in a 5.4 km horizontal-path link experiment incorporated several unique elements that were specifically tailored to address turbulence-induced fading. To facilitate optimization studies, this hardware was designed to afford a high degree of flexibility in the FEC code structure and interleaver length. An essential aspect of this structure was the standards-compliant client interface, which provided seamless connectivity to fiber-based terrestrial networks. Through the use of an OTU1 (2.667 Gbaud) architecture with nonstandard interleaving, error-free transmission was achieved in the presence of strong scintillation that produced fade events that frequently exceeded 10 ms in duration. This work was sponsored by the Department of Defense, RRCO DDR&E, under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

  7. Hardware design and implementation of fast DOA estimation method based on multicore DSP

    NASA Astrophysics Data System (ADS)

    Guo, Rui; Zhao, Yingxiao; Zhang, Yue; Lin, Qianqiang; Chen, Zengping

    2016-10-01

    In this paper, we present a high-speed real-time signal processing hardware platform based on multicore digital signal processor (DSP). The real-time signal processing platform shows several excellent characteristics including high performance computing, low power consumption, large-capacity data storage and high speed data transmission, which make it able to meet the constraint of real-time direction of arrival (DOA) estimation. To reduce the high computational complexity of DOA estimation algorithm, a novel real-valued MUSIC estimator is used. The algorithm is decomposed into several independent steps and the time consumption of each step is counted. Based on the statistics of the time consumption, we present a new parallel processing strategy to distribute the task of DOA estimation to different cores of the real-time signal processing hardware platform. Experimental results demonstrate that the high processing capability of the signal processing platform meets the constraint of real-time direction of arrival (DOA) estimation.

  8. Optimal two-stage enrichment design correcting for biomarker misclassification.

    PubMed

    Zang, Yong; Guo, Beibei

    2015-11-26

    The enrichment design is an important clinical trial design to detect the treatment effect of the molecularly targeted agent (MTA) in personalized medicine. Under this design, patients are stratified into marker-positive and marker-negative subgroups based on their biomarker statuses and only the marker-positive patients are enrolled into the trial and randomized to receive either the MTA or a standard treatment. As the biomarker plays a key role in determining the enrollment of the trial, a misclassification of the biomarker can induce substantial bias, undermine the integrity of the trial, and seriously affect the treatment evaluation. In this paper, we propose a two-stage optimal enrichment design that utilizes the surrogate marker to correct for the biomarker misclassification. The proposed design is optimal in the sense that it maximizes the probability of correctly classifying each patient's biomarker status based on the surrogate marker information. In addition, after analytically deriving the bias caused by the biomarker misclassification, we develop a likelihood ratio test based on the EM algorithm to correct for such bias. We conduct comprehensive simulation studies to investigate the operating characteristics of the optimal design and the results confirm the desirable performance of the proposed design.

  9. Study of orbit correction for eRHIC FFAG design

    SciTech Connect

    Liu, C.; Hao, Y.; Litvinenko, V.; Meot, F.; Minty, M.; Ptitsyn, V.; Trbojevic, D.

    2015-05-03

    The unique feature of the orbits in the eRHIC Fixed Field Alternating Gradient (FFAG) design is that multiple accelerating and decelerating bunches pass through the same magnets with different horizontal offsets. Therefore, it is critical for the eRHIC FFAG to correct multiple orbits in the same vacuum pipe for better spin transmission and alignment of colliding beams. In this report, the effects on orbits from multiple error sources will be studied. The orbit correction method will be described and results will be presented.

  10. Design and hardware-in-loop implementation of collision avoidance algorithms for heavy commercial road vehicles

    NASA Astrophysics Data System (ADS)

    Rajaram, Vignesh; Subramanian, Shankar C.

    2016-07-01

    An important aspect from the perspective of operational safety of heavy road vehicles is the detection and avoidance of collisions, particularly at high speeds. The development of a collision avoidance system is the overall focus of the research presented in this paper. The collision avoidance algorithm was developed using a sliding mode controller (SMC) and compared to one developed using linear full state feedback in terms of performance and controller effort. Important dynamic characteristics such as load transfer during braking, tyre-road interaction, dynamic brake force distribution and pneumatic brake system response were considered. The effect of aerodynamic drag on the controller performance was also studied. The developed control algorithms have been implemented on a Hardware-in-Loop experimental set-up equipped with the vehicle dynamic simulation software, IPG/TruckMaker®. The evaluation has been performed for realistic traffic scenarios with different loading and road conditions. The Hardware-in-Loop experimental results showed that the SMC and full state feedback controller were able to prevent the collision. However, when the discrepancies in the form of parametric variations were included, the SMC provided better results in terms of reduced stopping distance and lower controller effort compared to the full state feedback controller.

  11. Groundwater modeling in RCRA assessment, corrective action design and evaluation

    SciTech Connect

    Rybak, I.; Henley, W.

    1995-12-31

    Groundwater modeling was conducted to design, implement, modify, and terminate corrective action at several RCRA sites in EPA Region 4. Groundwater flow, contaminant transport and unsaturated zone air flow models were used depending on the complexity of the site and the corrective action objectives. Software used included Modflow, Modpath, Quickflow, Bioplume 2, and AIR3D. Site assessment data, such as aquifer properties, site description, and surface water characteristics for each facility were used in constructing the models and designing the remedial systems. Modeling, in turn, specified additional site assessment data requirements for the remedial system design. The specific purpose of computer modeling is discussed with several case studies. These consist, among others, of the following: evaluation of the mechanism of the aquifer system and selection of a cost effective remedial option, evaluation of the capture zone of a pumping system, prediction of the system performance for different and difficult hydrogeologic settings, evaluation of the system performance, and trouble-shooting for the remedial system operation. Modeling is presented as a useful tool for corrective action system design, performance, evaluation, and trouble-shooting. The case studies exemplified the integration of diverse data sources, understanding the mechanism of the aquifer system, and evaluation of the performance of alternative remediation systems in a cost-effective manner. Pollutants of concern include metals and PAHs.

  12. Performance analysis on wideband-interference cancellation based on detailed hardware design

    NASA Astrophysics Data System (ADS)

    Mohamed, Jama

    Use of a stretch waveform in a jamming environment with closely spaced objects such as surface vessels or fighter aircraft is presented. Adaptive cancellation in the sub-banding architecture improves the system cancellation ratio on large sub-array digital receiver systems. Detailed hardware models that capture key system requirements are described. Key model components are system aperture, receive chain with beamforming and digital data processing elements. The model takes error levels at array elements (e.g., quantization and beam pointing), digital receiver (e.g., amplitude and phase errors, time-delays, and aperture dispersions). System performance is evaluated via high-fidelity models and is characterized by the computing system's cancellation ratio.

  13. Parallel transmission RF pulse design for eddy current correction at ultra high field

    NASA Astrophysics Data System (ADS)

    Zheng, Hai; Zhao, Tiejun; Qian, Yongxian; Ibrahim, Tamer; Boada, Fernando

    2012-08-01

    Multidimensional spatially selective RF pulses have been used in MRI applications such as B1 and B0 inhomogeneities mitigation. However, the long pulse duration has limited their practical applications. Recently, theoretical and experimental studies have shown that parallel transmission can effectively shorten pulse duration without sacrificing the quality of the excitation pattern. Nonetheless, parallel transmission with accelerated pulses can be severely impeded by hardware and/or system imperfections. One of such imperfections is the effect of the eddy current field. In this paper, we first show the effects of the eddy current field on the excitation pattern and then report an RF pulse the design method to correct eddy current fields caused by the RF coil and the gradient system. Experimental results on a 7 T human eight-channel parallel transmit system show substantial improvements on excitation patterns with the use of eddy current correction. Moreover, the proposed model-based correction method not only demonstrates comparable excitation patterns as the trajectory measurement method, but also significantly improves time efficiency.

  14. Hardware description languages

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  15. Design of a hyperstable 60-subunit protein dodecahedron. [corrected].

    PubMed

    Hsia, Yang; Bale, Jacob B; Gonen, Shane; Shi, Dan; Sheffler, William; Fong, Kimberly K; Nattermann, Una; Xu, Chunfu; Huang, Po-Ssu; Ravichandran, Rashmi; Yi, Sue; Davis, Trisha N; Gonen, Tamir; King, Neil P; Baker, David

    2016-07-07

    The dodecahedron [corrected] is the largest of the Platonic solids, and icosahedral protein structures are widely used in biological systems for packaging and transport. There has been considerable interest in repurposing such structures for applications ranging from targeted delivery to multivalent immunogen presentation. The ability to design proteins that self-assemble into precisely specified, highly ordered icosahedral structures would open the door to a new generation of protein containers with properties custom-tailored to specific applications. Here we describe the computational design of a 25-nanometre icosahedral nanocage that self-assembles from trimeric protein building blocks. The designed protein was produced in Escherichia coli, and found by electron microscopy to assemble into a homogenous population of icosahedral particles nearly identical to the design model. The particles are stable in 6.7 molar guanidine hydrochloride at up to 80 degrees Celsius, and undergo extremely abrupt, but reversible, disassembly between 2 molar and 2.25 molar guanidinium thiocyanate. The dodecahedron [corrected] is robust to genetic fusions: one or two copies of green fluorescent protein (GFP) can be fused to each of the 60 subunits to create highly fluorescent ‘standard candles’ for use in light microscopy, and a designed protein pentamer can be placed in the centre of each of the 20 pentameric faces to modulate the size of the entrance/exit channels of the cage. Such robust and customizable nanocages should have considerable utility in targeted drug delivery, vaccine design and synthetic biology.

  16. Design of nanophotonic circuits for autonomous subsystem quantum error correction

    NASA Astrophysics Data System (ADS)

    Kerckhoff, J.; Pavlichin, D. S.; Chalabi, H.; Mabuchi, H.

    2011-05-01

    We reapply our approach to designing nanophotonic quantum memories in order to formulate an optical network that autonomously protects a single logical qubit against arbitrary single-qubit errors. Emulating the nine-qubit Bacon-Shor subsystem code, the network replaces the traditionally discrete syndrome measurement and correction steps by continuous, time-independent optical interactions and coherent feedback of unitarily processed optical fields.

  17. An introduction to the BANNING design automation system for shuttle microelectronic hardware development

    NASA Technical Reports Server (NTRS)

    Mcgrady, W. J.

    1979-01-01

    The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

  18. Parameterized hardware description as object oriented hardware model implementation

    NASA Astrophysics Data System (ADS)

    Drabik, Pawel K.

    2010-09-01

    The paper introduces novel model for design, visualization and management of complex, highly adaptive hardware systems. The model settles component oriented environment for both hardware modules and software application. It is developed on parameterized hardware description research. Establishment of stable link between hardware and software, as a purpose of designed and realized work, is presented. Novel programming framework model for the environment, named Graphic-Functional-Components is presented. The purpose of the paper is to present object oriented hardware modeling with mentioned features. Possible model implementation in FPGA chips and its management by object oriented software in Java is described.

  19. Petite Amateur Naval Satellite Spacecraft Digital Control System: A Hardware Design

    DTIC Science & Technology

    1993-03-01

    1 A. GENERAL .................................... 1 B. REDUNDANCY ................................ 1 C. DESIGN REQUIREMENTS OF A CONTROL BOARD...6 A. GENERAL .................................... 6 B. DESIGN IMPLEMENTATION OF A CONTROL BOARD ....... 6 1. Intel M80C186 CHMOS...Desirable Features ........................... 8 (1) Clock Generator Circuit .................... 8 (2) Two Independent Direct Memory Access (DMA

  20. Conformal dome aberration correction by designing the inner surface

    NASA Astrophysics Data System (ADS)

    Zhang, Wang; Chen, Shouqian; Fan, Zhigang

    2016-12-01

    The ray transmission models of optical domes were established, and the characteristics of the rays while passing through a hemispherical dome and a conformal dome were comparatively analysed. Acquiring the minimum deviated angles from the inner surface of the conformal dome was then determined to be the designing goal for reducing the dynamic aberrations. Based on this, the inner surface of the conformal dome was optimized and thus, the dynamic aberrations were reduced. Finally, a completely cooled conformal optical system was designed. The results show that the optical system have produced good imaging quality within all the fields of regard, which further illustrates that designing the inner surface of a conformal dome is an effective method for aberration correction.

  1. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    NASA Astrophysics Data System (ADS)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  2. Converting Paper into Hardware: A Status of the TEMPO Instrument Design and Manufacturing

    NASA Astrophysics Data System (ADS)

    Nicks, D. K., Jr.; Flittner, D. E.; Chance, K.; Liu, X.; Al-Saadi, J. A.; Pennington, W. F.; Suleiman, R. M.; Rosenbaum, D. M.; Canova, B.; Baker, B.; Lasnik, J.

    2015-12-01

    The Tropospheric Emissions: Monitoring of Pollution (TEMPO) instrument is part of NASA's Earth Venture Instrument (EVI) program, and will be the first hosted payload sensor to make tropospheric gas observations from geostationary (GEO) orbit using an ultraviolet/visible spectrometer. The instrument is designed to provide key trace gas measurements important to understanding tropospheric air pollution chemistry. The baseline design measures ozone (O3), nitrogen dioxide (NO2), and formaldehyde (H2CO). The TEMPO instrument will provide hourly daylight measurements of these trace gases on urban-regional spatial scales. These remote sensing measurements augment current ground-based air quality measurements and will offer improvements in air quality modeling and prediction. The TEMPO project has completed its confirmation review as well as the Critical Design Review (CDR). The updated TEMPO design, instrument performance estimates and technical challenges will be presented.

  3. Design requirements for SRB production control system. Volume 3: Package evaluation, modification and hardware

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software package evaluation was designed to analyze commercially available, field-proven, production control or manufacturing resource planning management technology and software package. The analysis was conducted by comparing SRB production control software requirements and conceptual system design to software package capabilities. The methodology of evaluation and the findings at each stage of evaluation are described. Topics covered include: vendor listing; request for information (RFI) document; RFI response rate and quality; RFI evaluation process; and capabilities versus requirements.

  4. Acoustic Treatment Design Scaling Methods. Volume 3; Test Plans, Hardware, Results, and Evaluation

    NASA Technical Reports Server (NTRS)

    Yu, J.; Kwan, H. W.; Echternach, D. K.; Kraft, R. E.; Syed, A. A.

    1999-01-01

    The ability to design, build, and test miniaturized acoustic treatment panels on scale-model fan rigs representative of the full-scale engine provides not only a cost-savings, but an opportunity to optimize the treatment by allowing tests of different designs. To be able to use scale model treatment as a full-scale design tool, it is necessary that the designer be able to reliably translate the scale model design and performance to an equivalent full-scale design. The primary objective of the study presented in this volume of the final report was to conduct laboratory tests to evaluate liner acoustic properties and validate advanced treatment impedance models. These laboratory tests include DC flow resistance measurements, normal incidence impedance measurements, DC flow and impedance measurements in the presence of grazing flow, and in-duct liner attenuation as well as modal measurements. Test panels were fabricated at three different scale factors (i.e., full-scale, half-scale, and one-fifth scale) to support laboratory acoustic testing. The panel configurations include single-degree-of-freedom (SDOF) perforated sandwich panels, SDOF linear (wire mesh) liners, and double-degree-of-freedom (DDOF) linear acoustic panels.

  5. Hardware and software design for an electromagnetic induction tomography (EMT) system for high contrast metal process applications

    NASA Astrophysics Data System (ADS)

    Ma, X.; Peyton, A. J.; Higson, S. R.; Lyons, A.; Dickinson, S. J.

    2006-01-01

    This paper presents the latest development of an EMT system designed for use in the metal production industry such as imaging molten steel flow profiles during continuous casting. The system that has been developed is based on a commercial data acquisition board residing in a PC host computer and programmed in the LabView graphical language. The paper reviews the new EMT hardware electronics and software. The noise effects and the detectability limits of the system are given in the paper followed by the system sensitivity map analysis. Optimal image reconstructions, including the simultaneous iterative reconstruction technique (SIRT) and non-iterative Tikhonov regularization, truncated singular value decomposition (TSVD), are also discussed and applied for the system. The system has been demonstrated in real time (10 frames s-1 for 5 kHz excitation) with test phantoms that represent typical metal flow profiles such as central, annular stream and multiple streams.

  6. Hardly Hardware

    ERIC Educational Resources Information Center

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  7. Design, Development, and Testing of a UAV Hardware-in-the-Loop Testbed for Aviation and Airspace Prognostics Research

    NASA Technical Reports Server (NTRS)

    Kulkarni, Chetan; Teubert, Chris; Gorospe, George; Burgett, Drew; Quach, Cuong C.; Hogge, Edward

    2016-01-01

    The airspace is becoming more and more complicated, and will continue to do so in the future with the integration of Unmanned Aerial Vehicles (UAVs), autonomy, spacecraft, other forms of aviation technology into the airspace. The new technology and complexity increases the importance and difficulty of safety assurance. Additionally, testing new technologies on complex aviation systems & systems of systems can be very difficult, expensive, and sometimes unsafe in real life scenarios. Prognostic methodology provides an estimate of the health and risks of a component, vehicle, or airspace and knowledge of how that will change over time. That measure is especially useful in safety determination, mission planning, and maintenance scheduling. The developed testbed will be used to validate prediction algorithms for the real-time safety monitoring of the National Airspace System (NAS) and the prediction of unsafe events. The framework injects flight related anomalies related to ground systems, routing, airport congestion, etc. to test and verify algorithms for NAS safety. In our research work, we develop a live, distributed, hardware-in-the-loop testbed for aviation and airspace prognostics along with exploring further research possibilities to verify and validate future algorithms for NAS safety. The testbed integrates virtual aircraft using the X-Plane simulator and X-PlaneConnect toolbox, UAVs using onboard sensors and cellular communications, and hardware in the loop components. In addition, the testbed includes an additional research framework to support and simplify future research activities. It enables safe, accurate, and inexpensive experimentation and research into airspace and vehicle prognosis that would not have been possible otherwise. This paper describes the design, development, and testing of this system. Software reliability, safety and latency are some of the critical design considerations in development of the testbed. Integration of HITL elements in

  8. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  9. The J-2X Upper Stage Engine: From Design to Hardware

    NASA Technical Reports Server (NTRS)

    Byrd, Thomas

    2010-01-01

    NASA is well on its way toward developing a new generation of launch vehicles to support of national space policy to retire the Space Shuttle fleet, complete the International Space Station, and return to the Moon as the first step in resuming this nation s exploration of deep space. The Constellation Program is developing the launch vehicles, spacecraft, surface systems, and ground systems to support those plans. Two launch vehicles will support those ambitious plans the Ares I and Ares V. (Figure 1) The J-2X Upper Stage Engine is a critical element of both of these new launchers. This paper will provide an overview of the J-2X design background, progress to date in design, testing, and manufacturing. The Ares I crew launch vehicle will lift the Orion crew exploration vehicle and up to four astronauts into low Earth orbit (LEO) to rendezvous with the space station or the first leg of mission to the Moon. The Ares V cargo launch vehicle is designed to lift a lunar lander into Earth orbit where it will be docked with the Orion spacecraft, and provide the thrust for the trans-lunar journey. While these vehicles bear some visual resemblance to the 1960s-era Saturn vehicles that carried astronauts to the Moon, the Ares vehicles are designed to carry more crew and more cargo to more places to carry out more ambitious tasks than the vehicles they succeed. The government/industry team designing the Ares rockets is mining a rich history of technology and expertise from the Shuttle, Saturn and other programs and seeking commonality where feasible between the Ares crew and cargo rockets as a way to minimize risk, shorten development times, and live within the budget constraints of its original guidance.

  10. Preliminary control law and hardware designs for a ride quality augmentation system for commuter aircraft. Phase 2

    NASA Technical Reports Server (NTRS)

    Davis, D. J.; Linse, D. J.; Suikat, R.; Entz, D. P.

    1986-01-01

    The continued investigation of the design of Ride Quality Augmentation Systems (RQAS) for commuter aircraft is described. The purpose of these RQAS is the reduction of the vertical and lateral acceleration response of the aircraft due to atmospheric turbulence by the application of active control. The current investigations include the refinement of the sample data feedback control laws based on the control-rate-weighting and output-weighting optimal control design techniqes. These control designs were evaluated using aircraft time simulations driven by Dryden spectra turbulence. Fixed gain controllers were tested throughout the aircrft operating envelope. The preliminary design of the hardware modifications necessary to implement and test the RQAS on a commuter aircraft is included. These include a separate surface elevator and the flap modifications to provide both direct lift and roll control. A preliminary failure mode investigation was made for the proposed configuration. The results indicate that vertical acceleration reductions of 45% and lateral reductions of more than 50% are possible. A fixed gain controller appears to be feasible with only minor response degradation.

  11. Skylab biomedical hardware development

    NASA Technical Reports Server (NTRS)

    Huffstetler, W. J., Jr.; Lem, J. D.

    1974-01-01

    The development of hardware to support biomedical experimentation and operations in the Skylab vehicle presented unique technical problems. Designs were required to enable the accurate measurement of many varied physiological parameters and to compensate for zero g such that uninhibited equipment operation would be possible. Because of problems that occurred during the orbital workshop launch, special tests were run and new equipment was designed and built for use by the first Skylab crew. Design concepts used in the development of hardware to support cardiovascular, pulmonary, vestibular, body, and specimen mass measuring experiments are discussed. Additionally, major problem areas and the corresponding design solutions, as well as knowledge gained that will be pertinent for future life sciences hardware development, are presented.

  12. The Effect of Predicted Vehicle Displacement on Ground Crew Task Performance and Hardware Design

    NASA Technical Reports Server (NTRS)

    Atencio, Laura Ashley; Reynolds, David W.

    2011-01-01

    NASA continues to explore new launch vehicle concepts that will carry astronauts to low- Earth orbit to replace the soon-to-be retired Space Transportation System (STS) shuttle. A tall vertically stacked launch vehicle (> or =300 ft) is exposed to the natural environment while positioned on the launch pad. Varying directional winds and vortex shedding cause the vehicle to sway in an oscillating motion. Ground crews working high on the tower and inside the vehicle during launch preparations will be subjected to this motion while conducting critical closeout tasks such as mating fluid and electrical connectors and carrying heavy objects. NASA has not experienced performing these tasks in such environments since the Saturn V, which was serviced from a movable (but rigid) service structure; commercial launchers are likewise attended by a service structure that moves away from the vehicle for launch. There is concern that vehicle displacement may hinder ground crew operations, impact the ground system designs, and ultimately affect launch availability. The vehicle sway assessment objective is to replicate predicted frequencies and displacements of these tall vehicles, examine typical ground crew tasks, and provide insight into potential vehicle design considerations and ground crew performance guidelines. This paper outlines the methodology, configurations, and motion testing performed while conducting the vehicle displacement assessment that will be used as a Technical Memorandum for future vertically stacked vehicle designs.

  13. Energy efficient engine high pressure turbine test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Halila, E. E.; Lenahan, D. T.; Thomas, T. T.

    1982-01-01

    The high pressure turbine configuration for the Energy Efficient Engine is built around a two-stage design system. Moderate aerodynamic loading for both stages is used to achieve the high level of turbine efficiency. Flowpath components are designed for 18,000 hours of life, while the static and rotating structures are designed for 36,000 hours of engine operation. Both stages of turbine blades and vanes are air-cooled incorporating advanced state of the art in cooling technology. Direct solidification (DS) alloys are used for blades and one stage of vanes, and an oxide dispersion system (ODS) alloy is used for the Stage 1 nozzle airfoils. Ceramic shrouds are used as the material composition for the Stage 1 shroud. An active clearance control (ACC) system is used to control the blade tip to shroud clearances for both stages. Fan air is used to impinge on the shroud casing support rings, thereby controlling the growth rate of the shroud. This procedure allows close clearance control while minimizing blade tip to shroud rubs.

  14. Design and implementation of a new real-time frequency sensor used as hardware countermeasure.

    PubMed

    Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

    2013-09-04

    A new digital countermeasure against attacks related to the clock frequency is presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 mm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation-VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack.

  15. Design and Implementation of a New Real-Time Frequency Sensor Used as Hardware Countermeasure

    PubMed Central

    Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

    2013-01-01

    A new digital countermeasure against attacks related to the clock frequency is –presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 μm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation—VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack. PMID:24008285

  16. Designing an Ergonomically Correct CNC Workstation on a Shoe String Budget.

    ERIC Educational Resources Information Center

    Lightner, Stan

    2001-01-01

    Describes research to design and construct ergonomically correct work stations for Computer Numerical Control machine tools. By designing ergonomically correct work stations, industrial technology teachers help protect students from repetitive motion injuries. (Contains 12 references.) (JOW)

  17. Design and Implementation of a Hardware Channel Board for Holographic Data Storage

    NASA Astrophysics Data System (ADS)

    Yoon, Pilsang; Kim, Haksun; Park, Jooyoun; Jung, Heungsang; Park, Gwitae

    2009-03-01

    A channel board has been designed, manufactured, and used for real-time recording and reading processes. The channel coding and decoding algorithms were implemented on Xilinx field-programmable gate array (FPGA) devices. For fast data transmission between the channel board and personal computer (PC), a universal serial bus (USB) 2.0 interface is installed in the channel board. The firmware and device driver for USB interface achieved a transfer rate of 34 Mbyte/s. A holographic data storage system records a video stream, which was successfully retrieved and reconstructed without error.

  18. Hardware-Based Non-Optimum Factors for Launch Vehicle Structural Design

    NASA Technical Reports Server (NTRS)

    Wu, K. Chauncey; Cerro, Jeffrey A.

    2010-01-01

    During aerospace vehicle conceptual and preliminary design, empirical non-optimum factors are typically applied to predicted structural component weights to account for undefined manufacturing and design details. Non-optimum factors are developed here for 32 aluminum-lithium 2195 orthogrid panels comprising the liquid hydrogen tank barrel of the Space Shuttle External Tank using measured panel weights and manufacturing drawings. Minimum values for skin thickness, axial and circumferential blade stiffener thickness and spacing, and overall panel thickness are used to estimate individual panel weights. Panel non-optimum factors computed using a coarse weights model range from 1.21 to 1.77, and a refined weights model (including weld lands and skin and stiffener transition details) yields non-optimum factors of between 1.02 and 1.54. Acreage panels have an average 1.24 non-optimum factor using the coarse model, and 1.03 with the refined version. The observed consistency of these acreage non-optimum factors suggests that relatively simple models can be used to accurately predict large structural component weights for future launch vehicles.

  19. The design and fabrication of the Centaur neutral buoyancy trainer and related hardware

    NASA Technical Reports Server (NTRS)

    Ware, Alan S.; Hollingsworth, Michael

    1986-01-01

    Two full scale mockups of the Centaur upper stage were designed, fabricated and delivered to NASA. One was the Centaur Weightless Environment Training Facility (WETF) trainer and the other was the Centaur 1-G mockup. The Centaur upper stage booster is designed to carry the spacecraft Galileo to Jupiter, and the spacecraft Ulysses to an orbit around the Sun after launch from the Space Shuttle. The flight vehicle has several Extravehicular Activity (EVA) contingency tasks that require crew training. This need for crew training generated the requirement for the Centaur WETF crew trainer, which is high fidelity in areas of expected crew interface. During the production of the Centaur WETF crew trainer, the need for a jumper cable from Centaur to the Orbiter was identified. This EVA contingency task would be the installation of a cable from the Orbiter cargo bay sill to various command data boxes on Centaur to allow crew control deployment should a failure occur. This task required the upgrading of volumetric boxes on the trainer to a high fidelity configuration including electrical connector installation and cable routing.

  20. Design and Hardware-in-the-Loop Implementation of Optimal Canonical Maneuvers for an Autonomous Planetary Aerial Vehicle

    DTIC Science & Technology

    2012-12-01

    Execution with Selected Hardware .............................7 2. Model Fidelity Level... Function and Limits ..............................................................37 6. Time and Node Number Selection...103 B. FUTURE IMRPOVEMENTS

  1. Final Report: Enabling Exascale Hardware and Software Design through Scalable System Virtualization

    SciTech Connect

    Bridges, Patrick G.

    2015-02-01

    In this grant, we enhanced the Palacios virtual machine monitor to increase its scalability and suitability for addressing exascale system software design issues. This included a wide range of research on core Palacios features, large-scale system emulation, fault injection, perfomrance monitoring, and VMM extensibility. This research resulted in large number of high-impact publications in well-known venues, the support of a number of students, and the graduation of two Ph.D. students and one M.S. student. In addition, our enhanced version of the Palacios virtual machine monitor has been adopted as a core element of the Hobbes operating system under active DOE-funded research and development.

  2. Design of software and hardware components for a six-degrees of freedom optical position sensor

    SciTech Connect

    Garcia, F.N.

    1997-06-01

    This report summarizes the evaluation of a fully compatible and operational data acquisition system for a six-degrees of freedom optical sensor (SixDOF). The SixDOF, developed at Lawrence Livermore National Laboratory by Charles Vann, is capable of tracking an object`s position in all its six degrees of freedom without any datum specification by means of two reflective surfaces mounted on the object. To make the SixDOF operational and thus validate its underlying physics, a signal processing system has been designed so that information from the sensor is transferred accurately and efficiently to a computer. In addition, a six-degrees of freedom positioning stage has been built in efforts to calibrate the sensor in real time. A crucial design constraint is the necessity to build the complete data acquisition system so that it be small and most importantly portable. The prototype of the SixDOF system proved to be capable of crudely detecting changes in the position of an object in all six spatial degrees of freedom. An accuracy of around 0.5 mm is estimated presently even though the position of the two reflectors on the object is seen to significantly influence the accuracy of the sensor. The resolution of the sensor is not quite understood yet because of uncertainties in the actual spot size of the laser, however, field of the view has been seen to increase as the resolution decreases. The decoupling (calibration) of the sensor data proved to be rather successful although some coupling still exists. This coupling, however, is almost certain to come from the crudeness in the alignment of the optics within the sensor.

  3. A novel software and conceptual design of the hardware platform for intensity modulated radiation therapy

    SciTech Connect

    Nguyen, Dan; Ruan, Dan; O’Connor, Daniel; Woods, Kaley; Low, Daniel A.; Sheng, Ke; Boucher, Salime

    2016-02-15

    Purpose: To deliver high quality intensity modulated radiotherapy (IMRT) using a novel generalized sparse orthogonal collimators (SOCs), the authors introduce a novel direct aperture optimization (DAO) approach based on discrete rectangular representation. Methods: A total of seven patients—two glioblastoma multiforme, three head & neck (including one with three prescription doses), and two lung—were included. 20 noncoplanar beams were selected using a column generation and pricing optimization method. The SOC is a generalized conventional orthogonal collimators with N leaves in each collimator bank, where N = 1, 2, or 4. SOC degenerates to conventional jaws when N = 1. For SOC-based IMRT, rectangular aperture optimization (RAO) was performed to optimize the fluence maps using rectangular representation, producing fluence maps that can be directly converted into a set of deliverable rectangular apertures. In order to optimize the dose distribution and minimize the number of apertures used, the overall objective was formulated to incorporate an L2 penalty reflecting the difference between the prescription and the projected doses, and an L1 sparsity regularization term to encourage a low number of nonzero rectangular basis coefficients. The optimization problem was solved using the Chambolle–Pock algorithm, a first-order primal–dual algorithm. Performance of RAO was compared to conventional two-step IMRT optimization including fluence map optimization and direct stratification for multileaf collimator (MLC) segmentation (DMS) using the same number of segments. For the RAO plans, segment travel time for SOC delivery was evaluated for the N = 1, N = 2, and N = 4 SOC designs to characterize the improvement in delivery efficiency as a function of N. Results: Comparable PTV dose homogeneity and coverage were observed between the RAO and the DMS plans. The RAO plans were slightly superior to the DMS plans in sparing critical structures. On average, the maximum and

  4. A novel software and conceptual design of the hardware platform for intensity modulated radiation therapy

    PubMed Central

    Nguyen, Dan; Ruan, Dan; O’Connor, Daniel; Woods, Kaley; Low, Daniel A.; Boucher, Salime; Sheng, Ke

    2016-01-01

    Purpose: To deliver high quality intensity modulated radiotherapy (IMRT) using a novel generalized sparse orthogonal collimators (SOCs), the authors introduce a novel direct aperture optimization (DAO) approach based on discrete rectangular representation. Methods: A total of seven patients—two glioblastoma multiforme, three head & neck (including one with three prescription doses), and two lung—were included. 20 noncoplanar beams were selected using a column generation and pricing optimization method. The SOC is a generalized conventional orthogonal collimators with N leaves in each collimator bank, where N = 1, 2, or 4. SOC degenerates to conventional jaws when N = 1. For SOC-based IMRT, rectangular aperture optimization (RAO) was performed to optimize the fluence maps using rectangular representation, producing fluence maps that can be directly converted into a set of deliverable rectangular apertures. In order to optimize the dose distribution and minimize the number of apertures used, the overall objective was formulated to incorporate an L2 penalty reflecting the difference between the prescription and the projected doses, and an L1 sparsity regularization term to encourage a low number of nonzero rectangular basis coefficients. The optimization problem was solved using the Chambolle–Pock algorithm, a first-order primal–dual algorithm. Performance of RAO was compared to conventional two-step IMRT optimization including fluence map optimization and direct stratification for multileaf collimator (MLC) segmentation (DMS) using the same number of segments. For the RAO plans, segment travel time for SOC delivery was evaluated for the N = 1, N = 2, and N = 4 SOC designs to characterize the improvement in delivery efficiency as a function of N. Results: Comparable PTV dose homogeneity and coverage were observed between the RAO and the DMS plans. The RAO plans were slightly superior to the DMS plans in sparing critical structures. On average, the maximum and

  5. Reducing NPR 7120.5D to Practice: Transitioning from Design Reviews to the SIR Hardware Review

    NASA Technical Reports Server (NTRS)

    Taylor, Randall

    2011-01-01

    The Gravity Recovery And Interior Laboratory (GRAIL) mission was the first Jet Propulsion Laboratory (JPL) project initiated under NASA's revised rules for space flight project management, NPR 7120.5D, "NASA Space Flight Program and Project Management Requirements." NASA selected GRAIL through a competitive Announcement of Opportunity process and funded its Phase B Preliminary Design effort. The team's first major milestone was a JPL institutional milestone, the Project Mission System Review (PMSR), which proved an excellent tune-up for the end-of-Phase-B NASA life-cycle review, the Preliminary Design Review (PDR). Building on JPL experience on the Prometheus and Juno projects, the team successfully organized for and conducted these reviews on an aggressive schedule. For the Project Critical Design Review (CDR), lessons learned from the PDR and updated Standing Review Board (SRB) practices from the Agency were factored into the review preparation effort. Additionally, the review was held at the Principal Investigator's institution, the Massachusetts Institute of Technology, rather than at the project management center (JPL), which necessitated additional cross-country coordination steps. The PMSR, PDR, and CDR were design reviews and largely paper-oriented. For the System Integration Review (SIR), the project needed to transition to a hardware review and deal with paper in a very different manner. While many of the practices employed for the design reviews were modified and retained (e.g., review preparation team, gate products management, pre-reviews, SRB coordination), the review agenda, presentation style, and slide templates were significantly changed. A key success factor concerned the handling of project open paper, which was succinctly and effectively communicated to the SRB in presentations.This paper provides a brief overview of the GRAIL mission and its project management challenges, provides a detailed description of project SIR preparation and execution

  6. The role of the asymptotic dynamics in the design of FPGA-based hardware implementations of gIF-type neural networks.

    PubMed

    Rostro-Gonzalez, Horacio; Cessac, Bruno; Girau, Bernard; Torres-Huitzil, Cesar

    2011-01-01

    This paper presents a numerical analysis of the role of asymptotic dynamics in the design of hardware-based implementations of the generalised integrate-and-fire (gIF) neuron models. These proposed implementations are based on extensions of the discrete-time spiking neuron model, which was introduced by Soula et al., and have been implemented on Field Programmable Gate Array (FPGA) devices using fixed-point arithmetic. Mathematical studies conducted by Cessac have evidenced the existence of three main regimes (neural death, periodic and chaotic regimes) in the activity of such neuron models. These activity regimes are characterised in hardware by considering a precision analysis in the design of an architecture for an FPGA-based implementation. The proposed approach, although based on gIF neuron models and FPGA hardware, can be extended to more complex neuron models as well as to different in silico implementations.

  7. The cell pattern correction through design-based metrology

    NASA Astrophysics Data System (ADS)

    Kim, Yonghyeon; Lee, Kweonjae; Chang, Jinman; Kim, Taeheon; Han, Daehan; Lee, Kyusun; Hong, Aeran; Kang, Jinyoung; Choi, Bumjin; Lee, Joosung; Yeom, Kyehee; Lee, Jooyoung; Hong, Hyeongsun; Lee, Kyupil; Jin, Gyoyoung

    2015-03-01

    Starting with the sub 2Xnm node, the process window becomes smaller and tighter than before. Pattern related error budget is required for accurate critical-dimension control of Cell layers. Therefore, lithography has been faced with its various difficulties, such as weird distribution, overlay error, patterning difficulty etc. The distribution of cell pattern and overlay management are the most important factors in DRAM field. We had been experiencing that the fatal risk is caused by the patterns located in the tail of the distribution. The overlay also induces the various defect sources and misalignment issues. Even though we knew that these elements are important, we could not classify the defect type of Cell patterns. Because there is no way to gather massive small pattern CD samples in cell unit block and to compare layout with cell patterns by the CD-SEM. The CD- SEM is used in order to gather these data through high resolution, but CD-SEM takes long time to inspect and extract data because it measures the small FOV. (Field Of View) However, the NGR(E-beam tool) provides high speed with large FOV and high resolution. Also, it's possible to measure an accurate overlay between the target layout and cell patterns because they provide DBM. (Design Based Metrology) By using massive measured data, we extract the result that it is persuasive by applying the various analysis techniques, as cell distribution and defects, the pattern overlay error correction etc. We introduce how to correct cell pattern, by using the DBM measurement, and new analysis methods.

  8. Corrections.

    PubMed

    2015-07-01

    Lai Y-S, Biedermann P, Ekpo UF, et al. Spatial distribution of schistosomiasis and treatment needs in sub-Saharan Africa: a systematic review and geostatistical analysis. Lancet Infect Dis 2015; published online May 22. http://dx.doi.org/10.1016/S1473-3099(15)00066-3—Figure 1 of this Article should have contained a box stating ‘100 references added’ with an arrow pointing inwards, rather than a box stating ‘199 records excluded’, and an asterisk should have been added after ‘1473 records extracted into GNTD’. Additionally, the positioning of the ‘§ and ‘†’ footnotes has been corrected in table 1. These corrections have been made to the online version as of June 4, 2015.

  9. Correction.

    PubMed

    2016-02-01

    In the article by Guessous et al (Guessous I, Pruijm M, Ponte B, Ackermann D, Ehret G, Ansermot N, Vuistiner P, Staessen J, Gu Y, Paccaud F, Mohaupt M, Vogt B, Pechère-Bertschi A, Martin PY, Burnier M, Eap CB, Bochud M. Associations of ambulatory blood pressure with urinary caffeine and caffeine metabolite excretions. Hypertension. 2015;65:691–696. doi: 10.1161/HYPERTENSIONAHA.114.04512), which published online ahead of print December 8, 2014, and appeared in the March 2015 issue of the journal, a correction was needed.One of the author surnames was misspelled. Antoinette Pechère-Berstchi has been corrected to read Antoinette Pechère-Bertschi.The authors apologize for this error.

  10. On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.; Guo, X.

    2002-01-01

    This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.

  11. Hardware-software-co-design of parallel and distributed systems using a behavioural programming and multi-process model with high-level synthesis

    NASA Astrophysics Data System (ADS)

    Bosse, Stefan

    2011-05-01

    A new design methodology for parallel and distributed embedded systems is presented using the behavioural hardware compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes (CSP) with an extensive set of interprocess-communication primitives and guarded atomic actions. The programming language and the compiler-based synthesis process enables the design of constrained power- and resourceaware embedded systems with pure Register-Transfer-Logic (RTL) efficiently mapped to FPGA and ASIC technologies. Concurrency is modelled explicitly on control- and datapath level. Additionally, concurrency on data-path level can be automatically explored and optimized by different schedulers. The CSP programming model can be synthesized to hardware (SoC) and software (C,ML) models and targets. A common source for both hardware and software implementation with identical functional behaviour is used. Processes and objects of the entire design can be distributed on different hardware and software platforms, for example, several FPGA components and software executed on several microprocessors, providing a parallel and distributed system. Intersystem-, interprocess-, and object communication is automatically implemented with serial links, not visible on programming level. The presented design methodology has the benefit of high modularity, freedom of choice of target technologies, and system architecture. Algorithms can be well matched to and distributed on different suitable execution platforms and implementation technologies, using a unique programming model, providing a balance of concurrency and resource complexity. An extended case study of a communication protocol used in high-density sensor-actuator networks should demonstrate and compare the design of a hardware and software target. The communication protocol is suited for high-density intra-and interchip networks.

  12. NASA HUNCH Hardware

    NASA Technical Reports Server (NTRS)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  13. Correction

    NASA Astrophysics Data System (ADS)

    1998-12-01

    Alleged mosasaur bite marks on Late Cretaceous ammonites are limpet (patellogastropod) home scars Geology, v. 26, p. 947 950 (October 1998) This article had the following printing errors: p. 947, Abstract, line 11, “sepia” should be “septa” p. 947, 1st paragraph under Introduction, line 2, “creep” should be “deep” p. 948, column 1, 2nd paragraph, line 7, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 1, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 5, “19774” should be “1977)” p. 949, column 1, 4th paragraph, line 7, “in particular” should be “In particular” CORRECTION Mammalian community response to the latest Paleocene thermal maximum: An isotaphonomic study in the northern Bighorn Basin, Wyoming Geology, v. 26, p. 1011 1014 (November 1998) An error appeared in the References Cited. The correct reference appears below: Fricke, H. C., Clyde, W. C., O'Neil, J. R., and Gingerich, P. D., 1998, Evidence for rapid climate change in North America during the latest Paleocene thermal maximum: Oxygen isotope compositions of biogenic phosphate from the Bighorn Basin (Wyoming): Earth and Planetary Science Letters, v. 160, p. 193 208.

  14. A novel visual hardware behavioral language

    NASA Technical Reports Server (NTRS)

    Li, Xueqin; Cheng, H. D.

    1992-01-01

    Most hardware behavioral languages just use texts to describe the behavior of the desired hardware design. This is inconvenient for VLSI designers who enjoy using the schematic approach. The proposed visual hardware behavioral language has the ability to graphically express design information using visual parallel models (blocks), visual sequential models (processes) and visual data flow graphs (which consist of primitive operational icons, control icons, and Data and Synchro links). Thus, the proposed visual hardware behavioral language can not only specify hardware concurrent and sequential functionality, but can also visually expose parallelism, sequentiality, and disjointness (mutually exclusive operations) for the hardware designers. That would make the hardware designers capture the design ideas easily and explicitly using this visual hardware behavioral language.

  15. Satellite Communication Hardware Emulation System (SCHES)

    NASA Technical Reports Server (NTRS)

    Kaplan, Ted

    1993-01-01

    Satellite Communication Hardware Emulator System (SCHES) is a powerful simulator that emulates the hardware used in TDRSS links. SCHES is a true bit-by-bit simulator that models communications hardware accurately enough to be used as a verification mechanism for actual hardware tests on user spacecraft. As a credit to its modular design, SCHES is easily configurable to model any user satellite communication link, though some development may be required to tailor existing software to user specific hardware.

  16. One Shot to an Asteroid- MASCOT and the Design of an Exclusively Primary Battery Powered Small Spacecraft in Hardware Design Examples and Operations Considerations

    NASA Astrophysics Data System (ADS)

    Grundmann, Jan Thimo; Biele, Jens; Findlay, Ross; Fredon, Stephane; Ho, Tra-Mi; Krause, Christian; Ulamec, Stephan; Ziach, Christian

    2014-08-01

    The Mobile Asteroid Surface Scout, MASCOT, is a small, 11 kg mobile asteroid lander for the Japanese space probe HAYABUSA-2. It carries four science instruments, a redundant command chain, and a mobility mechanism. On-asteroid power is provided by a Li-SOCl2 primary battery, interplanetary cruise power and thermal control by umbilical connection. The power subsystem manages the activation of MASCOT. It uses a mixed configuration of isolated and non-isolated, redundant and non-redundant supply lines to stay within tight system constraints. Due to the short project timeline, extensive and early testing of integrated hardware was used, often combining off-the-shelf available designs and units of different maturity levels. An overview, progress and lessons learned are shown.

  17. Modeling Attitude Variance in Small UAS’s for Acoustic Signature Simplification Using Experimental Design in a Hardware-in-the-Loop Simulation

    DTIC Science & Technology

    2015-03-26

    MODELING ATTITUDE VARIANCE IN SMALL UAS’S FOR ACOUSTIC SIGNATURE SIMPLIFICATION USING EXPERIMENTAL...and is not subject to copyright protection in the United States. AFIT-ENS-MS-15-M-110 MODELING ATTITUDE VARIANCE IN SMALL UAS’S FOR ACOUSTIC ...IN SMALL UAS’S FOR ACOUSTIC SIGNATURE SIMPLIFICATION USING EXPERIMENTAL DESIGN IN A HARDWARE-IN-THE-LOOP SIMULATION Mitchell N. Gillespie

  18. Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework

    NASA Astrophysics Data System (ADS)

    Butt, Shahzad Ahmad; Mancini, Stéphane; Rousseau, Frédéric; Lavagno, Luciano

    2014-09-01

    The pseudo-log image transform belongs to a class of image processing kernels that generate memory references which are nonlinear functions of loop indices. Due to the nonlinearity of the memory references, the usual design methodologies do not allow efficient hardware implementation for nonlinear kernels. For optimized hardware implementation, these kernels require the creation of a customized memory hierarchy and efficient data/memory management strategy. We present the design and real-time hardware implementation of a pseudo-log image transform IP (hardware image processing engine) using a memory management framework. The framework generates a controller which efficiently manages input data movement in the form of tiles between off-chip main memory, on-chip memory, and the core processing unit. The framework can jointly optimize the memory hierarchy and the tile computation schedule to reduce on-chip memory requirements, to maximize throughput, and to increase data reuse for reducing off-chip memory bandwidth requirements. The algorithmic C++ description of the pseudo-log kernel is profiled in the framework to generate an enhanced description with a customized memory hierarchy. The enhanced description of the kernel is then used for high-level synthesis (HLS) to perform architectural design space exploration in order to find an optimal implementation under given performance constraints. The optimized register transfer level implementation of the IP generated after HLS is used for performance estimation. The performance estimation is done in a simulation framework to characterize the IP with different external off-chip memory latencies and a variety of data transfer policies. Experimental results show that the designed IP can be used for real-time implementation and that the generated memory hierarchy is capable of feeding the IP with a sufficiently high bandwidth even in the presence of long external memory latencies.

  19. New Designs for Correctional Education and Training Programs.

    ERIC Educational Resources Information Center

    McCollum, Sylvia G.

    1973-01-01

    The challenge confronting creative educators concerned with using the correctional experience in positive ways is to structure an educational delivery system which takes into account the wide range of individual differences among people whose only common denominator is "serving time." Inherent is the problem of staff and public resistance to…

  20. 78 FR 32988 - Core Principles and Other Requirements for Designated Contract Markets; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-03

    ... Markets; Correction AGENCY: Commodity Futures Trading Commission. ACTION: Final rule; correction. SUMMARY... Other Requirements for Designated Contract Markets by inserting a missing instruction to add Appendix C... and Other Requirements for Designated Contract Markets (77 FR 36612, June 19, 2012). The final...

  1. Hardware Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  2. Sterilization of space hardware.

    NASA Technical Reports Server (NTRS)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  3. Door Hardware and Installations; Carpentry: 901894.

    ERIC Educational Resources Information Center

    Dade County Public Schools, Miami, FL.

    The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

  4. 78 FR 15755 - Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-12

    ... corrects an incorrect Agency Wide Document Management System Accession Number contained in the... header: NRC's Agencywide Documents Access and Management System (ADAMS), change sentence, Section 3.8.3... COMMISSION Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction...

  5. System Design for Detection and Correction of Spelling Errors in Scientific and Scholarly Text.

    ERIC Educational Resources Information Center

    Pollock, Joseph J.; Zamora, Antonio

    1984-01-01

    Describes system design proposed by the Spelling Error Detection Correction Project (SPEEDCOP) at Chemical Abstracts Service. Highlights include principles of detection/correction system; spelling error detection (the dictionary, suffix normalization, bypassing specialized word classes, document-level frequency threshold); spelling error…

  6. Factors Influencing the Design, Establishment, Administration, and Governance of Correctional Education for Females

    ERIC Educational Resources Information Center

    Ellis, Johnica; McFadden, Cheryl; Colaric, Susan

    2008-01-01

    This article summarizes the results of a study conducted to investigate factors influencing the organizational design, establishment, administration, and governance of correctional education for females. The research involved interviews with correctional and community college administrators and practitioners representing North Carolina female…

  7. 75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-01

    ... Manufacturing A Including On-Site Leased Workers From TAC Worldwide, GDA Technologies, Inc., Manpower, Ion..., GDA Technologies, Inc., Manpower, Ion Design, Design Solutions, Inc., Veriseo, SilconElite and Micro... Technologies, Inc., Manpower, Ion Design, Design Solutions, Inc., Veriseo, SiliconElite and MicroLogic,...

  8. Hardware Review: What Hardware Should We Buy?

    ERIC Educational Resources Information Center

    Tinker, Robert

    1984-01-01

    Discusses trends and changes in hardware production. For example Sinclair/Timex has stopped mass marketing its computers while others (such as the IBM junior) has finally made its appearance. Strongly advises schools to re-evaluate their hardware purchasing programs in light of these and other changes. (JN)

  9. The Space Operations Simulation Center (SOSC) and Closed-loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    D'Souza, Christopher; Milenkovich, Zoran; Wilson, Zachary; Huich, David; Bendle, John; Kibler, Angela

    2011-01-01

    The Space Operations Simulation Center (SOSC) at the Lockheed Martin (LM) Waterton Campus in Littleton, Colorado is a dynamic test environment focused on Autonomous Rendezvous and Docking (AR&D) development testing and risk reduction activities. The SOSC supports multiple program pursuits and accommodates testing Guidance, Navigation, and Control (GN&C) algorithms for relative navigation, hardware testing and characterization, as well as software and test process development. The SOSC consists of a high bay (60 meters long by 15.2 meters wide by 15.2 meters tall) with dual six degree-of-freedom (6DOF) motion simulators and a single fixed base 6DOF robot. The large testing area (maximum sensor-to-target effective range of 60 meters) allows for large-scale, flight-like simulations of proximity maneuvers and docking events. The facility also has two apertures for access to external extended-range outdoor target test operations. In addition, the facility contains four Mission Operations Centers (MOCs) with connectivity to dual high bay control rooms and a data/video interface room. The high bay is rated at Class 300,000 (. 0.5 m maximum particles/m3) cleanliness and includes orbital lighting simulation capabilities.

  10. The telescope control of the ASTRI SST-2M prototype for the Cherenkov telescope Array: hardware and software design architecture

    NASA Astrophysics Data System (ADS)

    Antolini, Elisa; Cascone, Enrico; Schwarz, Joseph; Stringhetti, Luca; Tanci, Claudio; Tosti, Gino; Aisa, Damiano; Aisa, Simone; Bagaglia, Marco; Busatta, Andrea; Campeggi, Carlo; Cefala, Marco; Farnesini, Lucio; Giacomel, Stefano; Marchiori, Gianpiero; Marcuzzi, Enrico; Nucciarelli, Giuliano; Piluso, Antonfranco

    2014-07-01

    ASTRI (Astrofisica con Specchi a Tecnologia Replicante Italiana) is a flagship project of the Italian Ministry of Research and led by the Italian National Institute of Astrophysics (INAF). One of its aims is to develop, within the Cherenkov Telescope Array (CTA) framework, an end-to-end small-sized telescope prototype in a dual-mirror configuration (SST-2M) in order to investigate the energy range E ~ 1-100 TeV. A long-term goal of the ASTRI program is the production of an ASTRI/CTA mini-array composed of seven SST-2M telescopes. The prototype, named ASTRI SST-2M, is seen as a standalone system that needs only network and power connections to work. The software system that is being developed to control the prototype is the base for the Mini-Array Software System (MASS), which has the task to make possible the operation of both the ASTRI SST-2M prototype and the ASTRI/CTA mini-array. The scope of this contribution is to give an overview of the hardware and software architecture adopted for the ASTRI SST- 2M prototype, showing how to apply state of the art industrial technologies to telescope control and monitoring systems.

  11. Energy efficient engine: Turbine intermediate case and low-pressure turbine component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Leach, K.; Thulin, R. D.; Howe, D. C.

    1982-01-01

    A four stage, low pressure turbine component has been designed to power the fan and low pressure compressor system in the Energy Efficient Engine. Designs for a turbine intermediate case and an exit guide vane assembly also have been established. The components incorporate numerous technology features to enhance efficiency, durability, and performance retention. These designs reflect a positive step towards improving engine fuel efficiency on a component level. The aerodynamic and thermal/mechanical designs of the intermediate case and low pressure turbine components are presented and described. An overview of the predicted performance of the various component designs is given.

  12. Constructing Hardware in a Scale Embedded Language

    SciTech Connect

    Bachan, John

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

  13. Open-source hardware for medical devices

    PubMed Central

    2016-01-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device. PMID:27158528

  14. Growth and development of Arabidopsis in the Advanced Biological Research System (ABRS) hardware designed for the International Space Station

    NASA Astrophysics Data System (ADS)

    Savidge, Rodney

    Wild type (Col 0) Arabidopsis thaliana were grown in a growth chamber within the single mid-deck sized Advanced Biological Research System (ABRS) spaceflight hardware developed by NASA Kennedy Space Center. Before beginning this experiment, the plants, each rooted in individual transferable tubes containing nutrients, were cultivated hydroponically on halfstrength Hoagland's solution beneath either LED lighting similar to that provided by the ABRS growth chamber or white fluorescent lighting. The leaves of the basal whorl of plants pre-grown in ABRS lighting were small and purplish at the start of the experiment, whereas those under fluorescent lighting were larger and green. The plants were transferred to the ABRS soon after their inflorescence axes had started to elongate, and thereafter they were maintained under preset conditions (22 o C, approximately 1500 ppm CO2 , predominantly 125 µmol m-2 s-1 PAR) with pulses of water provided at 1-3 d intervals (as needed) to the module into which the root tubes were inserted. That module was pre-treated with half-strength Hoagland's nutrient solution on day 0, but no additional nutrients were provided the plants thereafter. Strong primary growth of all inflorescence stems occurred soon after initiating the ABRS experiment, and the plants began forming an overarching canopy of flowering stems beneath the LED lighting module within two weeks. After 38 days the root module was littered with seeds, siliques and abscised leaves, but all plants remained alive. Plants pre-grown in ABRS lighting were more advanced toward senescence, and leaves and stems of plants pre-grown in fluorescent lighting although greener were also acquiring a purplish hue. Microscopy revealed that the flowering stems achieved no secondary growth; however, progressive inward conversion of pith parenchyma into sclerenchyma cells did occur resulting in the inflorescence stems becoming abnormally woody.

  15. The design and use of an error correction information system for NASTRAN

    NASA Technical Reports Server (NTRS)

    Rosser, D. C., Jr.

    1974-01-01

    Error Correction Information System (ECIS) is a system for a two-way transmittal of NASTRAN maintenance information via a data base stored on a nationwide accessible computer. ECIS consists of two data bases. The first data base is used for comments, reporting NASTRAN Software Problem Reports (SPR's) and bookkeeping information which can be updated by the user or the NASTRAN Office. The second data base is used by the NSMO to store all SPR information and updates. The hardware needed by an accessing user is any desktop computer terminal and a telephone to communicate with the central computer. The instruction format is an engineering oriented language and requires less than an hour to obtain a working knowledge of its functions.

  16. Aspherical surfaces design for extreme ultraviolet lithographic objective with correction of thermal aberration

    NASA Astrophysics Data System (ADS)

    Liu, Yan; Li, Yanqiu

    2016-09-01

    At present, few projection objectives for extreme ultraviolet (EUV) lithography pay attention to correct thermal aberration in optical design phase, which would lead to poor image quality in a practical working environment. We present an aspherical modification method for helping the EUV lithographic objective additionally correct the thermal aberration. Based on the thermal aberration and deformation predicted by integrated optomechanical analysis, the aspherical surfaces in an objective are modified by an iterative algorithm. The modified aspherical surfaces could correct the thermal aberration and maintain the initial high image quality in a practical working environment. A six-mirror EUV lithographic objective with 0.33-numerical aperture is taken as an example to illustrate the presented method. The results show that the thermal aberration can be corrected effectively, and the image quality of the thermally deformed system is improved to the initial design level, which proves the availability of the method.

  17. Application of acoustic surface wave filter-beam lead component technology to deep space multimission hardware design

    NASA Technical Reports Server (NTRS)

    Kermode, A. W.; Boreham, J. F.

    1974-01-01

    This paper discusses the utilization of acoustic surface wave filters, beam lead components, and thin film metallized ceramic substrate technology as applied to the design of deep space, long-life, multimission transponder. The specific design to be presented is for a second mixer local oscillator module, operating at frequencies as high as 249 MHz.

  18. Modular hardware synthesis using an HDL. [Hardware Description Language

    NASA Technical Reports Server (NTRS)

    Covington, J. A.; Shiva, S. G.

    1981-01-01

    Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

  19. CLASSICAL AREAS OF PHENOMENOLOGY: Conformal optical design with combination of static and dynamic aberration corrections

    NASA Astrophysics Data System (ADS)

    Li, Yan; Li, Lin; Huang, Yi-Fan; Liu, Jia-Guo

    2009-02-01

    Conformal domes that are shaped to meet aerodynamic requirements can increase range and speed for the host platform. Because these domes typically deviate greatly from spherical surface descriptions, a variety of aberrations are induced which vary with the field-of-regard (FOR) angle. A system for correcting optical aberrations created by a conformal dome has an outer surface and an inner surface. Optimizing the inner surface is regard as static aberration correction. A deformable mirror is placed at the position of the secondary mirror in the two-mirror all reflective imaging system, which is the dynamic aberration correction. An ellipsoidal MgF2 conformal dome with a fineness ratio of 1.0 is designed as an example. The FOR angle is 0°- 30°, and the design wavelength is 4 μm. After the optimization at 7 zoom positions by using the design tools Code V, the root-mean-square (RMS) spot size is reduced to approximately 0.99 to 1.48 times the diffraction limit. The design results show that the performances of the conformal optical systems can be greatly improved by the combination of the static correction and the dynamic correction.

  20. Customized schematic eye model for refraction correction design based on ocular wavefront and corneal topography measurements

    NASA Astrophysics Data System (ADS)

    Curatu, Eugene O.; Pettit, George H.; Campin, John A.

    2002-06-01

    The subject of this paper relates to the ocular optical design and vision analysis of refractive correction of the eye. After the purpose statement and the assumption list, the concept of the schematic eye matching a particular (measured) wavefront is introduced. This concept is based on the fact that the ocular wavefront, together with the corneal topography, can be seen as the mathematical global representation of the eye working in monochromatic light and having a foveal vision. The discussed design technique, including an iterative optimization method, could be applied in any ocular correction that utilizes cornea topography and/or ocular wavefront, e.g. contact lens or intra-corneal implant. However, the application this paper refers to is the ocular refractive correction by a procedure using the LADARVISION. It consists of surgical removal and subsequent replacement of a corneal flap on a stromal surface whose shape has been changed by laser ablation of the tissue. Subsequent sections of this paper are dedicated to establishing the limits of possible refractive correction, the influences of the flap and corneal topography into the refractive correction calculation. Finally a realistic evaluation of the results and a list of possible developments of this new optical design method are discussed.

  1. Design of macro-filter-lens with simultaneous chromatic and geometric aberration correction.

    PubMed

    Prasad, Dilip K; Brown, Michael S

    2014-01-01

    A macro-filter-lens design that can correct for chromatic and geometric aberrations simultaneously while providing for a long focal length is presented. The filter is easy to fabricate since it involves two spherical surfaces and a planar surface. Chromatic aberration correction is achieved by making all the rays travel the same optical distance inside the filter element (negative meniscus). Geometric aberration is corrected for by the lens element (plano-convex), which makes the output rays parallel to the optic axis. This macro-filter-lens design does not need additional macro lenses and it provides an inexpensive and optically good (aberration compensated) solution for macro imaging of objects not placed close to the camera.

  2. Towards composition of verified hardware devices

    NASA Technical Reports Server (NTRS)

    Schubert, E. Thomas; Levitt, K.; Cohen, G. C.

    1991-01-01

    Computers are being used where no affordable level of testing is adequate. Safety and life critical systems must find a replacement for exhaustive testing to guarantee their correctness. Through a mathematical proof, hardware verification research has focused on device verification and has largely ignored system composition verification. To address these deficiencies, we examine how the current hardware verification methodology can be extended to verify complete systems.

  3. The Space Operations Simulation Center (SOSC) and Closed-Loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    Milenkovic, Zoran; DSouza, Christopher; Huish, David; Bendle, John; Kibler, Angela

    2012-01-01

    The exploration goals of Orion / MPCV Project will require a mature Rendezvous, Proximity Operations and Docking (RPOD) capability. Ground testing autonomous docking with a next-generation sensor such as the Vision Navigation Sensor (VNS) is a critical step along the path of ensuring successful execution of autonomous RPOD for Orion. This paper will discuss the testing rationale, the test configuration, the test limitations and the results obtained from tests that have been performed at the Lockheed Martin Space Operations Simulation Center (SOSC) to evaluate and mature the Orion RPOD system. We will show that these tests have greatly increased the confidence in the maturity of the Orion RPOD design, reduced some of the latent risks and in doing so validated the design philosophy of the Orion RPOD system. This paper is organized as follows: first, the objectives of the test are given. Descriptions of the SOSC facility, and the Orion RPOD system and associated components follow. The details of the test configuration of the components in question are presented prior to discussing preliminary results of the tests. The paper concludes with closing comments.

  4. Bias Corrections for Standardized Effect Size Estimates Used with Single-Subject Experimental Designs

    ERIC Educational Resources Information Center

    Ugille, Maaike; Moeyaert, Mariola; Beretvas, S. Natasha; Ferron, John M.; Van den Noortgate, Wim

    2014-01-01

    A multilevel meta-analysis can combine the results of several single-subject experimental design studies. However, the estimated effects are biased if the effect sizes are standardized and the number of measurement occasions is small. In this study, the authors investigated 4 approaches to correct for this bias. First, the standardized effect…

  5. Visualizing the Future of Research on Post Secondary Correctional Education: Designs, Data, and Deliverables

    ERIC Educational Resources Information Center

    Wheeldon, J.

    2011-01-01

    Providing post-secondary education in correctional settings has emerged as one of the best ways to reduce recidivism, save taxpayer dollars, and promote post release employment and community reintegration. While a number of studies exist, this paper argues persistent challenges connected to research design, data collection, and the communication…

  6. Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

    SciTech Connect

    Morrison, R.E.; Robinson, S.H.

    1991-01-01

    A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander. 5 refs., 8 figs., 2 tabs.

  7. Thermal Hardware for the Thermal Analyst

    NASA Technical Reports Server (NTRS)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  8. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  9. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 2 2011-01-01 2011-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  10. Computer hardware description languages - A tutorial

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  11. Correction of magnetooptic device phase errors in optical correlators through filter design modifications

    NASA Technical Reports Server (NTRS)

    Downie, John D.; Reid, Max B.; Hine, Butler P.

    1991-01-01

    We address the problem of optical phase errors in an optical correlator introduced by the input and filter plane spatial light modulators. Specifically, we study a laboratory correlator with magnetooptic spatial light modulator (MOSLM) devices. We measure and characterize the phase errors, analyze their effects on the correlation process, and discuss a means of correction through a design modification of the binary phase-only optical filter function. The phase correction technique is found to produce correlation results close to those of an error-free correlator.

  12. Novel Principles and Techniques to Create a Natural Design in Female Hairline Correction Surgery

    PubMed Central

    2015-01-01

    Abstract Background: Female hairline correction surgery is becoming increasingly popular. However, no guidelines or methods of female hairline design have been introduced to date. Methods: The purpose of this study was to create an initial framework based on the novel principles of female hairline design and then use artistic ability and experience to fine tune this framework. An understanding of the concept of 5 areas (frontal area, frontotemporal recess area, temporal peak, infratemple area, and sideburns) and 5 points (C, A, B, T, and S) is required for female hairline correction surgery (the 5A5P principle). The general concepts of female hairline correction surgery and natural design methods are, herein, explained with a focus on the correlations between these 5 areas and 5 points. Results: A natural and aesthetic female hairline can be created with application of the above-mentioned concepts. Conclusion: The 5A5P principle of forming the female hairline is very useful in female hairline correction surgery. PMID:26894014

  13. Creating state of the art, next-generation Virtual Reality exposure therapies for anxiety disorders using consumer hardware platforms: design considerations and future directions.

    PubMed

    Lindner, Philip; Miloff, Alexander; Hamilton, William; Reuterskiöld, Lena; Andersson, Gerhard; Powers, Mark B; Carlbring, Per

    2017-03-08

    Decades of research and more than 20 randomized controlled trials show that Virtual Reality exposure therapy (VRET) is effective in reducing fear and anxiety. Unfortunately, few providers or patients have had access to the costly and technical equipment previously required. Recent technological advances in the form of consumer Virtual Reality (VR) systems (e.g. Oculus Rift and Samsung Gear), however, now make widespread use of VRET in clinical settings and as self-help applications possible. In this literature review, we detail the current state of VR technology and discuss important therapeutic considerations in designing self-help and clinician-led VRETs, such as platform choice, exposure progression design, inhibitory learning strategies, stimuli tailoring, gamification, virtual social learning and more. We illustrate how these therapeutic components can be incorporated and utilized in VRET applications, taking full advantage of the unique capabilities of virtual environments, and showcase some of these features by describing the development of a consumer-ready, gamified self-help VRET application for low-cost commercially available VR hardware. We also raise and discuss challenges in the planning, development, evaluation, and dissemination of VRET applications, including the need for more high-quality research. We conclude by discussing how new technology (e.g. eye-tracking) can be incorporated into future VRETs and how widespread use of VRET self-help applications will enable collection of naturalistic "Big Data" that promises to inform learning theory and behavioral therapy in general.

  14. Method of glass selection for color correction in optical system design.

    PubMed

    de Albuquerque, Bráulio Fonseca Carneiro; Sasian, Jose; de Sousa, Fabiano Luis; Montes, Amauri Silva

    2012-06-18

    A method of glass selection for the design of optical systems with reduced chromatic aberration is presented. This method is based on the unification of two previously published methods adding new contributions and using a multi-objective approach. This new method makes it possible to select sets of compatible glasses suitable for the design of super-apochromatic optical systems. As an example, we present the selection of compatible glasses and the effective designs for all-refractive optical systems corrected in five spectral bands, with central wavelengths going from 485 nm to 1600 nm.

  15. Motion compensation in digital subtraction angiography using graphics hardware.

    PubMed

    Deuerling-Zheng, Yu; Lell, Michael; Galant, Adam; Hornegger, Joachim

    2006-07-01

    An inherent disadvantage of digital subtraction angiography (DSA) is its sensitivity to patient motion which causes artifacts in the subtraction images. These artifacts could often reduce the diagnostic value of this technique. Automated, fast and accurate motion compensation is therefore required. To cope with this requirement, we first examine a method explicitly designed to detect local motions in DSA. Then, we implement a motion compensation algorithm by means of block matching on modern graphics hardware. Both methods search for maximal local similarity by evaluating a histogram-based measure. In this context, we are the first who have mapped an optimizing search strategy on graphics hardware while paralleling block matching. Moreover, we provide an innovative method for creating histograms on graphics hardware with vertex texturing and frame buffer blending. It turns out that both methods can effectively correct the artifacts in most case, as the hardware implementation of block matching performs much faster: the displacements of two 1024 x 1024 images can be calculated at 3 frames/s with integer precision or 2 frames/s with sub-pixel precision. Preliminary clinical evaluation indicates that the computation with integer precision could already be sufficient.

  16. Efficient Architecture for Spike Sorting in Reconfigurable Hardware

    PubMed Central

    Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

    2013-01-01

    This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation. PMID:24189331

  17. Comparison of classical methods for blade design and the influence of tip correction on rotor performance

    NASA Astrophysics Data System (ADS)

    Sørensen, J. N.; Okulov, V. L.; Mikkelsen, R. F.; Naumov, I. V.; Litvinov, I. V.

    2016-09-01

    The classical blade-element/momentum (BE/M) method, which is used together with different types of corrections (e.g. the Prandtl or Glauert tip correction), is today the most basic tool in the design of wind turbine rotors. However, there are other classical techniques based on a combination of the blade-element approach and lifting-line (BE/LL) methods, which are less used by the wind turbine community. The BE/LL method involves different interpretations for rotors with finite or infinite numbers of blades and different assumptions with respect to the optimum circulation distribution. In the present study we compare the performance and the resulting design of the BE/M method by Glauert [1] and the BE/LL method by Betz [2] for finite as well as for infinite-bladed rotors, corrected for finiteness through the tip correction. In the first part of the paper, expressions are given for the optimum design, including blade plan forms and local pitch distributions. The comparison shows that the resulting geometry of the rotor depends on the method used, but that the differences mainly exist in the inner part of the blade and at relatively small tip speed ratios (TSR<5). An important conclusion is that an infinite-bladed approach combined with a tip correction results in a geometry which is nearly identical to a geometry generated from a finite-bladed approach. Next, the results from an experimental investigation on the influence on rotor performances of the tip correction on two different rotors are presented. Employing BE/M without the tip correction (“Glauert rotor”) and BE/LL with the Goldstein's circulation (“Betz rotor”) two different 3-bladed rotors were designed and manufactured. The two rotors were investigated experimentally in a water flume to compare their performance at different tip speed ratios and pitch angles. As a result of the comparison it was found that the Betz rotor had the best performance.

  18. Computer-aided design and custom-made guide in corrective osteotomy for complex femoral deformity.

    PubMed

    Chai, Wei; Xu, Meng; Zhang, Guo-qiang; Zhang, Li-hai; Gou, Wen-long; Ni, Ming; Chen, Ji-ying

    2013-06-01

    Preoperative planning of corrective osteotomy with traditional radiography has limitations in regards to determining the ideal osteotomy location and orientation in three-dimensional femoral deformities. Though a successful operation can be planned preoperatively, intraoperative contingencies might adhere to the procedural plan in the performance of operation. To efficiently perform a planned procedure, proposed is a design to implement three-dimensional reconstruction photography, based on computer-tomography (CT) scan. A custom-made guide was designed to navigate the osteotomy as planned, and additionally, a personalized intramedullary nail was used for fixation after osteotomy. Three-dimensional (3D) photography of deformed femur was established based on the CT dataset and transferred into 3D photography processing software for further planning. Osteotomy planes were designed and adjusted at deformity sites to correct the 3D deformities. The methodology of a custom-made osteotomy guide was introduced in femoral corrective osteotomy, for the first time, to navigate the operation as planned. After the virtual osteotomy and reduction of bone segments, the parameters of a custom-made intramedullary nail were measured for manufacturing. Findings Virtual operation in computer shows complete correction of the 3D deformity. The osteotomy guide, obtained by rapid-prototyping techniques, navigates mimicking surgery on rapid-prototyping model of the involved femur as planned. Internal fixation was achieved using the custom-made intramedullary nail. Interpretation three-dimensional visualization introduces an advantage in preoperative planning for corrective osteotomy of 3D femoral deformity, and the custom-made osteotomy guide is crucial to realize such a deliberate plan during the actual procedures. The internal fixator, such as an intramedullary nail, can be modified or personalized for fixation in unique cases.

  19. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    NASA Technical Reports Server (NTRS)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  20. Secure Hardware Design for Trust

    DTIC Science & Technology

    2014-03-01

    approach. The Grain VHDL code was obtained from [13] and implemented in the same fashion as shown in Figure 5. Approved for Public Release...CRC implementation for USB token protocol was chosen was the main candidate. The VHDL source code was generated from [14] using the standard CRC5

  1. Hardware-Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  2. Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

    NASA Technical Reports Server (NTRS)

    Moore, J. Strother

    1992-01-01

    Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

  3. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    SciTech Connect

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  4. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    Inertial Upper Stage (IUS) and DoD Communication Interface Unit (CIU) communication system design, hardware specifications, and interfaces were evaluated to determine their compatibility with the Orbiter payload communication and data handling equipment and the Orbiter network communication equipment.

  5. Progress in the spectacle correction of presbyopia. Part 1: Design and development of progressive lenses.

    PubMed

    Meister, Darryl J; Fisher, Scott W

    2008-05-01

    Most of the commercial advances in the spectacle correction of presbyopia continue to occur in progressive lens design, which has been the focus of intense research and development over the past 60 years by major spectacle lens manufacturers. While progressive lens design and manufacturing techniques have advanced at a steady pace, recent progress in 'free-form' lens surfacing has opened up many exciting possibilities that will in all likelihood bring about a paradigm shift in the current model of progressive lens fabrication and distribution. The first installment of this two-part series will review the fundamental optical principles and early development work associated with progressive lenses.

  6. A front-end ASIC design for non-uniformity correction

    NASA Astrophysics Data System (ADS)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  7. Applying a Genetic Algorithm to Reconfigurable Hardware

    NASA Technical Reports Server (NTRS)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  8. Hardware removal - extremity

    MedlinePlus

    ... enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help fix a broken bone ... SW, Hotchkiss RN, Pederson WC, Kozin SH, Cohen MS, eds. Green's Operative Hand Surgery . 7th ed. Philadelphia, ...

  9. Initial Hardware Development Schedule

    NASA Technical Reports Server (NTRS)

    Culpepper, William X.

    1991-01-01

    The hardware development schedule for the Common Lunar Lander's (CLLs) tracking system is presented. Among the topics covered are the following: historical perspective, solution options, industry contacts, and the rationale for selection.

  10. Design of respiration averaged CT for attenuation correction of the PET data from PET/CT

    SciTech Connect

    Chi, Pai-Chun Melinda; Mawlawi, Osama; Nehmeh, Sadek A.; Erdi, Yusuf E.; Balter, Peter A.; Luo, Dershan; Mohan, Radhe; Pan Tinsu

    2007-06-15

    images only at the four significant phases for the ACT can reduce radiation dose to 1/3 of the current 4DCT dose; however, the implementation of this approach requires additional hardware that is not standard equipment on PET/CT scanners. In the cine approach, we recommend a duration of 6{+-}1 s in order to include variations of respiratory patterns in a larger population. This approach can be easily implemented because cine acquisition mode is available on all GE PET/CT scanners. The CT dose in the cine approach can be reduced to approximately 5 mGy by using the lowest mA setting (10 mA), while still maintaining good quality CT data for PET attenuation correction. In our scanning protocol, the ACT is only acquired if respiration-induced misregistration is observed (determined before the PET scan is completed), and therefore patients do not receive unnecessary CT radiation dose.

  11. Formal hardware verification of digital circuits

    NASA Technical Reports Server (NTRS)

    Joyce, J.; Seger, C.-J.

    1991-01-01

    The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

  12. Effective safety measures with tests followed by design correction for aerospace structures

    NASA Astrophysics Data System (ADS)

    Matsumura, Taiki

    Analytical and computational prediction tools enable us to design aircraft and spacecraft components with high degree of confidence. While the accuracy of such predictions has been improved over the years, uncertainty continues to be added by new materials and new technology introduced in order to improve performance. This requires us to have reality checks, such as tests, in order to make sure that the prediction tools are reliable enough to ensure safety. While tests can reveal unsafe designs and lead to design correction, these tests are very costly. Therefore, it is important to manage such a design-test-correction cycle effectively. In this dissertation, we consider three important test stages in the lifecycle of an aviation system. First, we dealt with characterization tests that reveal failure modes of new materials or new geometrical arrangements. We investigated the challenge associated with getting the best characterization with a limited number of tests. We have found that replicating tests to attenuate the effect of noise in observation is not necessary because some surrogate models can serve as a noise filter without having replicated data. Instead, we should focus on exploring the design space with different structural configurations in order to discover unknown failure modes. Next, we examined post-design tests for design acceptance followed by possible redesign. We looked at the question of how to balance the desire for better performance achieved by redesign against the cost of redesign. We proposed a design optimization framework that provides tradeoff information between the expected performance improvement by redesign and the probability of redesign, equivalent to the cost of redesign. We also demonstrated that the proposed method can reduce the performance loss due to a conservative reliability estimate. The ultimate test, finally, is whether the structures do not fail in flight. Once an accident occurs, an accident investigation takes place

  13. Microbiologic assay of space hardware.

    NASA Technical Reports Server (NTRS)

    Favero, M. S.

    1971-01-01

    Review of the procedures used in the microbiological examination of space hardware. The general procedure for enumerating aerobic and anaerobic microorganisms and spores is outlined. Culture media and temperature-time cycles used for incubation are reviewed, along with assay systems designed for the enumeration of aerobic and anaerobic spores. The special problems which are discussed are involved in the precise and accurate enumeration of microorganisms on surfaces and in the neutralization of viable organisms buried inside solid materials that could be released to a planet's surface if the solid should be fractured. Special attention is given to sampling procedures including also the indirect techniques of surface assays of space hardware such as those using detachable or fallout strips. Some data on comparative levels of microbial contamination on lunar and planetary spacecraft are presented.

  14. Prime focus wide-field corrector designs with lossless atmospheric dispersion correction

    SciTech Connect

    Saunders, Will; Gillingham, Peter; Smith, Greg; Kent, Steve; Doel, Peter

    2014-07-18

    Wide-Field Corrector designs are presented for the Blanco and Mayall telescopes, the CFHT and the AAT. The designs are Terezibh-style, with 5 or 6 lenses, and modest negative optical power. They have 2.2-3 degree fields of view, with curved and telecentric focal surfaces suitable for fiber spectroscopy. Some variants also allow wide-field imaging, by changing the last WFC element. Apart from the adaptation of the Terebizh design for spectroscopy, the key feature is a new concept for a 'Compensating Lateral Atmospheric Dispersion Corrector', with two of the lenses being movable laterally by small amounts. This provides excellent atmospheric dispersion correction, without any additional surfaces or absorption. A novel and simple mechanism for providing the required lens motions is proposed, which requires just 3 linear actuators for each of the two moving lenses.

  15. Design and progress toward a multi-conjugate adaptive optics system for distributed aberration correction

    SciTech Connect

    Baker, K; Olivier, S; Tucker, J; Silva, D; Gavel, D; Lim, R; Gratrix, E

    2004-08-17

    This article investigates the use of a multi-conjugate adaptive optics system to improve the field-of-view for the system. The emphasis of this research is to develop techniques to improve the performance of optical systems with applications to horizontal imaging. The design and wave optics simulations of the proposed system are given. Preliminary results from the multi-conjugate adaptive optics system are also presented. The experimental system utilizes a liquid-crystal spatial light modulator and an interferometric wave-front sensor for correction and sensing of the phase aberrations, respectively.

  16. Space shuttle main engine hardware simulation

    NASA Technical Reports Server (NTRS)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  17. Computer hardware fault administration

    DOEpatents

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  18. 34 CFR 403.100 - What are the requirements for designating a State corrections educational agency to administer...

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... corrections educational agency to administer the Programs for Criminal Offenders? 403.100 Section 403.100... ADULT EDUCATION, DEPARTMENT OF EDUCATION STATE VOCATIONAL AND APPLIED TECHNOLOGY EDUCATION PROGRAM What... § 403.100 What are the requirements for designating a State corrections educational agency to...

  19. Testing of hardware implementation of infrared image enhancing algorithm

    NASA Astrophysics Data System (ADS)

    Dulski, R.; Sosnowski, T.; PiÄ tkowski, T.; Trzaskawka, P.; Kastek, M.; Kucharz, J.

    2012-10-01

    The interpretation of IR images depends on radiative properties of observed objects and surrounding scenery. Skills and experience of an observer itself are also of great importance. The solution to improve the effectiveness of observation is utilization of algorithm of image enhancing capable to improve the image quality and the same effectiveness of object detection. The paper presents results of testing the hardware implementation of IR image enhancing algorithm based on histogram processing. Main issue in hardware implementation of complex procedures for image enhancing algorithms is high computational cost. As a result implementation of complex algorithms using general purpose processors and software usually does not bring satisfactory results. Because of high efficiency requirements and the need of parallel operation, the ALTERA's EP2C35F672 FPGA device was used. It provides sufficient processing speed combined with relatively low power consumption. A digital image processing and control module was designed and constructed around two main integrated circuits: a FPGA device and a microcontroller. Programmable FPGA device performs image data processing operations which requires considerable computing power. It also generates the control signals for array readout, performs NUC correction and bad pixel mapping, generates the control signals for display module and finally executes complex image processing algorithms. Implemented adaptive algorithm is based on plateau histogram equalization. Tests were performed on real IR images of different types of objects registered in different spectral bands. The simulations and laboratory experiments proved the correct operation of the designed system in executing the sophisticated image enhancement.

  20. Development of robotics facility docking test hardware

    NASA Technical Reports Server (NTRS)

    Loughead, T. E.; Winkler, R. V.

    1984-01-01

    Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

  1. Removal of broken hardware.

    PubMed

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful.

  2. Hardware Removal after Osseous Free Flap Reconstruction

    PubMed Central

    Day, Kristine E.; Desmond, Renee; Magnuson, J. Scott; Carroll, William R.; Rosenthal, Eben L.

    2015-01-01

    Objective Identifying risk factors for hardware removal in patients undergoing mandibular reconstruction with vascularized osseous free flaps remains a challenge. The purpose of this study is to identify potential risk factors, including osteocutaneous radial forearm versus fibular flap, for need for removal and to describe the fate of implanted hardware. Study Design Case series with chart review. Setting Academic tertiary care medical center. Subjects and Methods Two hundred thirteen patients undergoing 227 vascularized osseous mandibular reconstructions between the years 2004 and 2012. Data were compiled through a manual chart review, and patients incurring hardware removals were identified. Results Thirty-four of 213 evaluable vascularized osseous free flaps (16%) underwent surgical removal of hardware. The average length of time to removal was 16.2 months (median 10 months), with the majority of removals occurring within the first year. Osteocutaneous radial forearm free flaps (OCRFFF) incurred a slightly higher percentage of hardware removals (9.9%) compared to fibula flaps (6.1%). Partial removal was performed in 8 of 34 cases, and approximately 38% of these required additional surgery for removal. Conclusion Hardware removal was associated with continued tobacco use after mandibular reconstruction (P = .03). Removal of the supporting hardware most commonly occurs from infection or exposure in the first year. In the majority of cases the bone is well healed and the problem resolves with removal. PMID:24201061

  3. Safe to Fly: Certifying COTS Hardware for Spaceflight

    NASA Technical Reports Server (NTRS)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  4. DCSP hardware maintenance system

    SciTech Connect

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  5. Design and real time implementation of single phase boost power factor correction converter.

    PubMed

    Bouafassa, Amar; Rahmani, Lazhar; Mekhilef, Saad

    2015-03-01

    This paper presents a real time implementation of the single-phase power factor correction (PFC) AC-DC boost converter. A combination of higher order sliding mode controller based on super twisting algorithm and predictive control techniques are implemented to improve the performance of the boost converter. Due to the chattering effects, the higher order sliding mode control (HOSMC) is designed. Also, the predictive technique is modified taking into account the large computational delays. The robustness of the controller is verified conducting simulation in MATLAB, the results show good performances in both steady and transient states. An experiment is conducted through a test bench based on dSPACE 1104. The experimental results proved that the proposed controller enhanced the performance of the converter under different parameters variations.

  6. The Design of Flux-Corrected Transport (FCT) Algorithms for Structured Grids

    NASA Astrophysics Data System (ADS)

    Zalesak, Steven T.

    A given flux-corrected transport (FCT) algorithm consists of three components: (1) a high order algorithm to which it reduces in smooth parts of the flow; (2) a low order algorithm to which it reduces in parts of the flow devoid of smoothness; and (3) a flux limiter which calculates the weights assigned to the high and low order fluxes in various regions of the flow field. One way of optimizing an FCT algorithm is to optimize each of these three components individually. We present some of the ideas that have been developed over the past 30 years toward this end. These include the use of very high order spatial operators in the design of the high order fluxes, non-clipping flux limiters, the appropriate choice of constraint variables in the critical flux-limiting step, and the implementation of a "failsafe" flux-limiting strategy. This chapter confines itself to the design of FCT algorithms for structured grids, using a finite volume formalism, for this is the area with which the present author is most familiar. The reader will find excellent material on the design of FCT algorithms for unstructured grids, using both finite volume and finite element formalisms, in the chapters by Professors Löhner, Baum, Kuzmin, Turek, and Möller in the present volume.

  7. RRFC hardware operation manual

    SciTech Connect

    Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

    1996-05-01

    The Research Reactor Fuel Counter (RRFC) system was developed to assay the {sup 235}U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the {sup 235}U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics.

  8. Hardware development process for Human Research facility applications

    NASA Astrophysics Data System (ADS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. .

  9. Method for Automated Bone Shape Correction within Bone Distraction Procedure

    NASA Astrophysics Data System (ADS)

    Blynskiy, F. Yu

    2016-01-01

    The method for automated bone shape correction within bone distraction procedure is presented. High precision deformation angle measurement is provided by the software for X- Ray images processing. Special BDC v.1.0.1. application is designed. The purpose of the BDC is modeling of the bone geometry structure to calculate the appropriate distraction forces. The correction procedure control is realized by the hardware of the distraction system.

  10. Exascale Hardware Architectures Working Group

    SciTech Connect

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.

  11. A CLIPS based personal computer hardware diagnostic system

    NASA Technical Reports Server (NTRS)

    Whitson, George M.

    1991-01-01

    Often the person designated to repair personal computers has little or no knowledge of how to repair a computer. Described here is a simple expert system to aid these inexperienced repair people. The first component of the system leads the repair person through a number of simple system checks such as making sure that all cables are tight and that the dip switches are set correctly. The second component of the system assists the repair person in evaluating error codes generated by the computer. The final component of the system applies a large knowledge base to attempt to identify the component of the personal computer that is malfunctioning. We have implemented and tested our design with a full system to diagnose problems for an IBM compatible system based on the 8088 chip. In our tests, the inexperienced repair people found the system very useful in diagnosing hardware problems.

  12. Design and Implementation of an Online Auxiliary System for Correcting Japanese Composition

    ERIC Educational Resources Information Center

    Liu, Yuqin; Jiang, Guohai; Han, Lanling; Lin, Mingxing

    2013-01-01

    In language learning, error correction information given by teachers for student compositions is of great value in both teaching and learning. However, in traditional paper-based error correction mode, error correction information is easily lost and cannot be fed back to students systematically. The aim of this research is to provide maximum…

  13. Design and simulation of e-calendar system circuits

    NASA Astrophysics Data System (ADS)

    Liu, Li-jun

    2015-02-01

    The digital calendar circuits controlled by 80C52 have been designed based on Proteus simulation software. The whole design process is made of three parts: hardware circuits, software programming and software simulation. Finally, it shows that the circuit design of hardware and software is correct through Proteus software simulation. The method of circuit design is systematic and practical, which will provide certain design ideas and reference value for display circuit in the future.

  14. Human Centered Hardware Modeling and Collaboration

    NASA Technical Reports Server (NTRS)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  15. Circulation control lift generation experiment: Hardware development

    NASA Technical Reports Server (NTRS)

    Panontin, T. L.

    1985-01-01

    A circulation control airfoil and its accompanying hardware were developed to allow the investigation of lift generation that is independent of airfoil angle of attack and relative flow velocity. The test equipment, designed for use in a water tunnel, includes the blown airfoil, the support systems for both flow visualization and airfoil load measurement, and the fluid control system, which utilizes hydraulic technology. The primary design tasks, the selected solutions, and the unforseen problems involved in the development of these individual components of hardware are described.

  16. Characterization and correction of spherical aberration due to glass substrate in the design and fabrication of Fresnel zone lenses.

    PubMed

    Vijayakumar, A; Bhattacharya, S

    2013-08-20

    As with a conventional lens, a Fresnel zone lens (FZL) can be used to image objects at infinity or nearby. In the latter case, the FZL converts a diverging spherical wavefront into a converging spherical wavefront. The glass substrate on which the FZL is fabricated introduces spherical aberration resulting in a shift of the image plane and blurring of the image. Two novel schemes for correction of this spherical aberration are proposed and studied in this paper. To demonstrate them, FZLs are designed with and without aberration correction. They are fabricated using electron beam direct writing. The devices are evaluated and the accuracy of the proposed aberration correction schemes is validated.

  17. Optimization of system parameters for modulator design in x-ray scatter correction using primary modulation

    NASA Astrophysics Data System (ADS)

    Gao, Hewei; Zhu, Lei; Fahrig, Rebecca

    2010-04-01

    The impact of the system parameters of the modulator on X-ray scatter correction using primary modulation is studied and an optimization of the modulator design is presented. Recently, a promising scatter correction method for X-ray computed tomography (CT) that uses a checkerboard pattern of attenuating blockers (primary modulator) placed between the X-ray source and the object has been developed and experimentally verified. The blocker size, d, and the blocker transmission factor, α, are critical to the performance of the primary modulation method. In this work, an error caused by aliasing of primary whose magnitude depends on the choices of d and α, and the scanned object, is set as the object function to be minimized, with constraints including the X-ray focal spot, the physical size of the detector element, and the noise level. The optimization is carried out in two steps. In the first step, d is chosen as small as possible but should meet a lower-bound condition. In the second step, α should be selected to balance the error level in the scatter estimation and the noise level in the reconstructed image. The lower bound of d on our tabletop CT system is 0.83 mm. Numerical simulations suggest 0.6 < α < 0.8 is appropriate. Using a Catphan 600 phantom, a copper modulator (d = 0.89 mm, α = 0.70) expectedly outperforms an aluminum modulator (d = 2.83 mm, α = 0.90). With the aluminum modulator, our method reduces the average error of CT number in selected contrast rods from 371.4 to 25.4 Hounsfield units (HU) and enhances the contrast to noise ratio (CNR) from 10.9 to 17.2; when the copper modulator is used, the error is further reduced to 21.9 HU and the CNR is further increased to 19.2.

  18. GRASS Hardware Configurations Guide

    DTIC Science & Technology

    1989-03-01

    portability rather than limit users to a single brand of hardware. Within GRASS, there are many processor inten- sive functions. Therefore, processor...Expansion Unit 2,000 558 RR13 2 60 MB. 1 4V tape drive 1.233 SYSI,2 2-User Licene N, C Total $ 26,710 $ 23,290 IhLs erem is not supplij, bv ,un Nficrosyterms...DOS world there are a ’arge number of vendors that can supply you with the basic 386 personal computer that wili work in place of the brand of computer

  19. Mir hardware heritage

    NASA Technical Reports Server (NTRS)

    Portree, David S. F.

    1995-01-01

    The heritage of the major Mir complex hardware elements is described. These elements include Soyuz-TM and Progress-M; the Kvant, Kvant 2, and Kristall modules; and the Mir base block. Configuration changes and major mission events of the Salyut 6, Salyut 7, and Mir multiport space stations are described in detail for the period 1977-1994. A comparative chronology of U.S. and Soviet/Russian manned spaceflight is also given for that period. The 68 illustrations include comparative scale drawings of U.S. and Russian spacecraft as well as sequential drawings depicting missions and mission events.

  20. Computer program for design of two-dimensional supersonic turbine rotor blades with boundary-layer correction

    NASA Technical Reports Server (NTRS)

    Goldman, L. J.; Scullin, V. J.

    1971-01-01

    A FORTRAN 4 computer program for the design of two-dimensional supersonic rotor blade sections corrected for boundary-layer displacement thickness is presented. The ideal rotor is designed by the method of characteristics to produce vortex flow within the blade passage. The boundary-layer parameters are calculated by Cohen and Reshotoko's method for laminar flow and Sasman and Cresci's method for turbulent flow. The program input consists essentially of the blade surface Mach number distribution and total flow conditions. The primary output is the corrected blade profile and the boundary-layer parameters.

  1. Ripple FPN reduced algorithm based on temporal high-pass filter and hardware implementation

    NASA Astrophysics Data System (ADS)

    Li, Yiyang; Li, Shuo; Zhang, Zhipeng; Jin, Weiqi; Wu, Lei; Jin, Minglei

    2016-11-01

    Cooled infrared detector arrays always suffer from undesired Ripple Fixed-Pattern Noise (FPN) when observe the scene of sky. The Ripple Fixed-Pattern Noise seriously affect the imaging quality of thermal imager, especially for small target detection and tracking. It is hard to eliminate the FPN by the Calibration based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified space low-pass and temporal high-pass nonuniformity correction algorithm using adaptive time domain threshold (THP&GM). The threshold is designed to significantly reduce ghosting artifacts. We test the algorithm on real infrared in comparison to several previously published methods. This algorithm not only can effectively correct common FPN such as Stripe, but also has obviously advantage compared with the current methods in terms of detail protection and convergence speed, especially for Ripple FPN correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA). The hardware implementation of the algorithm based on FPGA has two advantages: (1) low resources consumption, and (2) small hardware delay (less than 20 lines). The hardware has been successfully applied in actual system.

  2. Defining and Enforcing Hardware Security Requirements

    DTIC Science & Technology

    2011-12-01

    26. Suffix implication example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. Checker automaton example...Programmable Gate Array FSM Finite State Machine HDL Hardware Design Language IBM International Business Machines Corporation IC Integrated Circuit IEEE...notes, “almost all Field Programmable Gate Arrays (FPGAs) are now made at foundries outside the U.S., about 80 percent of them in Taiwan. Defense

  3. Robustness in Digital Hardware

    NASA Astrophysics Data System (ADS)

    Woods, Roger; Lightbody, Gaye

    The growth in electronics has probably been the equivalent of the Industrial Revolution in the past century in terms of how much it has transformed our daily lives. There is a great dependency on technology whether it is in the devices that control travel (e.g., in aircraft or cars), our entertainment and communication systems, or our interaction with money, which has been empowered by the onset of Internet shopping and banking. Despite this reliance, there is still a danger that at some stage devices will fail within the equipment's lifetime. The purpose of this chapter is to look at the factors causing failure and address possible measures to improve robustness in digital hardware technology and specifically chip technology, giving a long-term forecast that will not reassure the reader!

  4. Architectural Support for Detection and Recovery using Hardware Wrappers

    DTIC Science & Technology

    2013-04-01

    SECRYPT 2011, Seville, Spain 2011. 5. A. Baumgarten, M. Steffen, M. Clausman, and J. Zambreno. "A Case Study in Hardware Trojan Design and...AFRL-OSR-VA-TR-2013-0204 Architectural Support for Detection and Recovery using Hardware Wrappers Bhagirath Narahari Rahul...Include area code) 02-26-2013 FINAL REPORT March 1, 2009 - Nov 30, 2012 Architectural Support for Detection and Recovery using Hardware Wrappers

  5. Magnetic Field Apparatus (MFA) Hardware Test

    NASA Technical Reports Server (NTRS)

    Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

    1999-01-01

    The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

  6. Codem: software/hardware codesign for embedded multicore systems supporting hardware services

    NASA Astrophysics Data System (ADS)

    Wang, Chao; Li, Xi; Zhou, Xuehai; Nedjah, Nadia; Wang, Aili

    2015-01-01

    Efficient software/hardware codesign is posing significant challenges to embedded systems. This paper proposes Codem, a software/hardware codesign flow for embedded systems, which models both processors and Intellectual Property (IP) cores as services. Tasks are regarded as abstract instructions which can be scheduled to IP cores for parallel execution automatically. In order to guide the hardware implementations of the hot spot functions, this paper incorporates a novel hot spot-based profiling technique to observe the hot spot functions while the application is being simulated. Furthermore, based on the hot spot of various applications, an adaptive mapping algorithm is presented to partition the application into multiple software/hardware tasks. We test the profiling-based design flow with classic Sort applications. Experimental results demonstrate that Codem can efficiently help researchers to identify the hot spots, and also outline a new direction to combine profiling techniques with state-of-the-art reconfigurable computing platforms for specific task acceleration.

  7. Hardware multiplier processor

    DOEpatents

    Pierce, P.E.

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  8. Hardware multiplier processor

    DOEpatents

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  9. The Microcomputer in the Library: II. Hardware and Operating Systems.

    ERIC Educational Resources Information Center

    Leggate, Peter; Dyer, Hilary

    1985-01-01

    This second in a series of six articles introducing microcomputer applications in smaller libraries describes the main microcomputer hardware components--processors, internal and external memory, buses, printers, communications, hardware. Importance of ergonomic factors in equipment design, multi-user and network configurations, and the role of…

  10. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    ERIC Educational Resources Information Center

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  11. Hardware Removal in Craniomaxillofacial Trauma

    PubMed Central

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  12. Economic impact of syndesmosis hardware removal.

    PubMed

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system.

  13. Fine figure correction and other applications using novel MRF fluid designed for ultra-low roughness

    NASA Astrophysics Data System (ADS)

    Maloney, Chris; Oswald, Eric S.; Dumas, Paul

    2015-10-01

    An increasing number of technologies require ultra-low roughness (ULR) surfaces. Magnetorheological Finishing (MRF) is one of the options for meeting the roughness specifications for high-energy laser, EUV and X-ray applications. A novel MRF fluid, called C30, has been developed to finish surfaces to ULR. This novel MRF fluid is able to achieve <1.5Å RMS roughness on fused silica and other materials, but has a lower material removal rate with respect to other MRF fluids. As a result of these properties, C30 can also be used for applications in addition to finishing ULR surfaces. These applications include fine figure correction, figure correcting extremely soft materials and removing cosmetic defects. The effectiveness of these new applications is explored through experimental data. The low removal rate of C30 gives MRF the capability to fine figure correct low amplitude errors that are usually difficult to correct with higher removal rate fluids. The ability to figure correct extremely soft materials opens up MRF to a new realm of materials that are difficult to polish. C30 also offers the ability to remove cosmetic defects that often lead to failure during visual quality inspections. These new applications for C30 expand the niche in which MRF is typically used for.

  14. CHeCS Commanding Hardware

    NASA Technical Reports Server (NTRS)

    Moore, Jamie

    2010-01-01

    This slide presentation reviews the Crew Health Care System (CHeCS) commanding hardware. It includes information on the hardware status, commanding plan, and command training status with specific information the EV-CPDS 2 and 3, TEPC, MEC, and T2

  15. Flight Avionics Hardware Roadmap

    NASA Technical Reports Server (NTRS)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  16. The design of the control algorithm for corrective manufacturing of 5 axis machining centre

    NASA Astrophysics Data System (ADS)

    Beneš, J.; Procháska, F.; Matoušek, O.

    2016-11-01

    The work deals with the creation of correction data when generating spherical and aspherical surfaces. Generation is performed on the converted 5-axis milling machine, for which it is necessary to generate control programs. In the process of generating surfaces may be formed random errors. Hence the need to measure workpieces, and errors corrected. There is thus solved a measurement of generated surface on coordinate measuring machine Mitutoyo LEGEX 744 and draft methods of data processing by using polynomial of nth order. The measured data are processed by Matlab, specifically CFTool module. This method is further tested and subsequently the experiment evaluated.

  17. Design and commissioning of an aberration-corrected ultrafast spin-polarized low energy electron microscope with multiple electron sources.

    PubMed

    Wan, Weishi; Yu, Lei; Zhu, Lin; Yang, Xiaodong; Wei, Zheng; Liu, Jefferson Zhe; Feng, Jun; Kunze, Kai; Schaff, Oliver; Tromp, Ruud; Tang, Wen-Xin

    2016-12-27

    We describe the design and commissioning of a novel aberration-corrected low energy electron microscope (AC-LEEM). A third magnetic prism array (MPA) is added to the standard AC-LEEM with two prism arrays, allowing the incorporation of an ultrafast spin-polarized electron source alongside the standard cold field emission electron source, without degrading spatial resolution. The high degree of symmetries of the AC-LEEM are utilized while we design the electron optics of the ultrafast spin-polarized electron source, so as to minimize the deleterious effect of time broadening, while maintaining full control of electron spin. A spatial resolution of 2nm and temporal resolution of 10ps (ps) are expected in the future time resolved aberration-corrected spin-polarized LEEM (TR-AC-SPLEEM). The commissioning of the three-prism AC-LEEM has been successfully finished with the cold field emission source, with a spatial resolution below 2nm.

  18. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    PubMed

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  19. Support for Diagnosis of Custom Computer Hardware

    NASA Technical Reports Server (NTRS)

    Molock, Dwaine S.

    2008-01-01

    The Coldfire SDN Diagnostics software is a flexible means of exercising, testing, and debugging custom computer hardware. The software is a set of routines that, collectively, serve as a common software interface through which one can gain access to various parts of the hardware under test and/or cause the hardware to perform various functions. The routines can be used to construct tests to exercise, and verify the operation of, various processors and hardware interfaces. More specifically, the software can be used to gain access to memory, to execute timer delays, to configure interrupts, and configure processor cache, floating-point, and direct-memory-access units. The software is designed to be used on diverse NASA projects, and can be customized for use with different processors and interfaces. The routines are supported, regardless of the architecture of a processor that one seeks to diagnose. The present version of the software is configured for Coldfire processors on the Subsystem Data Node processor boards of the Solar Dynamics Observatory. There is also support for the software with respect to Mongoose V, RAD750, and PPC405 processors or their equivalents.

  20. Computer hardware for radiologists: Part I.

    PubMed

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  1. Transistor Level Circuit Experiments using Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  2. Using the FLUKA Monte Carlo Code to Simulate the Interactions of Ionizing Radiation with Matter to Assist and Aid Our Understanding of Ground Based Accelerator Testing, Space Hardware Design, and Secondary Space Radiation Environments

    NASA Technical Reports Server (NTRS)

    Reddell, Brandon

    2015-01-01

    Designing hardware to operate in the space radiation environment is a very difficult and costly activity. Ground based particle accelerators can be used to test for exposure to the radiation environment, one species at a time, however, the actual space environment cannot be duplicated because of the range of energies and isotropic nature of space radiation. The FLUKA Monte Carlo code is an integrated physics package based at CERN that has been under development for the last 40+ years and includes the most up-to-date fundamental physics theory and particle physics data. This work presents an overview of FLUKA and how it has been used in conjunction with ground based radiation testing for NASA and improve our understanding of secondary particle environments resulting from the interaction of space radiation with matter.

  3. Design and mathematical analysis of a three-mirror X-ray telescope based on ATM S-056 X-ray telescope hardware

    NASA Technical Reports Server (NTRS)

    Foreman, J. W., Jr.; Cardone, J. M.

    1973-01-01

    The mathematical design of the aspheric third mirror for the three-mirror X-ray telescope (TMXRT) is presented, along with the imaging characteristics of the telescope obtained by a ray trace analysis. The present design effort has been directed entirely toward obtaining an aspheric third mirror which will be compatible with existing S-056 paraboloidal-hyperboloidal mirrors. This compatability will facilitate the construction of a prototype model of the TMXRT, since it will only be necessary to fabricate one new mirror in order to obtain a working model.

  4. Explosive-actuated valve design concept that eliminates blow-by. [for the TOPS spacecraft trajectory correction propulsion subsystem

    NASA Technical Reports Server (NTRS)

    Hagler, R., Jr.

    1974-01-01

    A method of evaluating the normally open normally closed, explosive actuated valves that were selected for use in the trajectory correction propulsion subsystem of the Thermoelectric Outer Planet Spacecraft (TOPS) program is presented. The design philosophy which determined the requirements for highly reliable valves that could provide the performance capability during long duration (10 year) missions to the outer planets is discussed. The techniques that were used to fabricate the valves and manifold ten valves into an assembly with the capability of five propellant-flow initiation/isolation sequences are described. The test program, which was conducted to verify valve design requirements, is outlined and the more significant results are shown.

  5. Manipulation hardware for microgravity research

    SciTech Connect

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. ); Rohn, D.A. . Lewis Research Center); Miller, J.H. )

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  6. Hardware problems encountered in solar heating and cooling systems

    NASA Technical Reports Server (NTRS)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  7. NDAS Hardware Translation Layer Development

    NASA Technical Reports Server (NTRS)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  8. Capabilities and constraints of typical space flight hardware

    NASA Technical Reports Server (NTRS)

    Koudelka, John M.

    1993-01-01

    The Space Experiments Division is in the business of performing ground based low gravity testing and designing experiment hardware for space flight on the Space Shuttle and in the future, Space Station Freedom. As witnessed in combustion work, the reduction of gravity brings forward previously negligible processes and parameters. In a similar manner, the design of experiments for microgravity operation aboard the Space Shuttle must consider parameters that are often not factors for laboratory hardware.

  9. Hardware Index to Permutation Converter

    DTIC Science & Technology

    2012-05-01

    Hardware Index to Permutation Converter J. T. Butler T. Sasao Department of Electrical and Computer Engineering Department of Computer Science...generates a permutation in response to an index. Since there are n! n-element permutations , the index ranges from 0 to n! − 1. Such a circuit is needed...in the hardware implementation of unique- permutation hash functions to specify how parallel machines interact through a shared memory. Such a circuit

  10. Cognitive Processing Hardware Elements

    DTIC Science & Technology

    2005-01-31

    approach . It is too early now to decide on final cognitive memory architecture. We must have a great deal more experi- ence with applications and know of...system is contemplated, a memory system that may also serve as a model for many aspects of human memory. The cognitive memory design would be able to store...correlates with or relates to the present real-time sensory inputs. The search would be done by a retrieval system that makes use of autoassociative

  11. Low cost design of microprocessor EDAC circuit

    NASA Astrophysics Data System (ADS)

    Li, Hao; Lixin, Yu; Heping, Peng; Wei, Zhuang

    2015-11-01

    An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.

  12. Hardware-Efficient Monitoring of I/O Signals

    NASA Technical Reports Server (NTRS)

    Driscoll, Kevin R.; Hall, Brendan; Paulitsch, Michael

    2009-01-01

    In this invention, command and monitor functionality is moved between the two independent pieces of hardware, in which one had been dedicated to command and the other had been dedicated to monitor, such that some command and some monitor functionality appears in each. The only constraint is that the monitor for signal cannot be in the same hardware as the command I/O it is monitoring. The splitting of the command outputs between independent pieces of hardware may require some communication between them, i.e. an intra-switch trunk line. This innovation reduces the amount of wasted hardware and allows the two independent pieces of hardware to be designed identically in order to save development costs.

  13. VME rollback hardware for time warp multiprocessor systems

    NASA Technical Reports Server (NTRS)

    Robb, Michael J.; Buzzell, Calvin A.

    1992-01-01

    The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

  14. Correction of facial and mandibular asymmetry using a computer aided design/computer aided manufacturing prefabricated titanium implant.

    PubMed

    Watson, Jason; Hatamleh, Muhanad; Alwahadni, Ahed; Srinivasan, Dilip

    2014-05-01

    Patients with significant craniofacial asymmetry may have functional problems associated with their occlusion and aesthetic concerns related to the imbalance in soft and hard tissue profiles. This report details a case of facial asymmetry secondary to left mandible angle deficiency due to undergoing previous radiotherapy. We describe the correction of the bony deformity using computer aided design/computer aided manufacturing custom-made titanium onlay using novel direct metal laser sintering. The direct metal laser sintering onlay proved a very accurate operative fit and showed a good aesthetic correction of the bony defect with no reported complications postoperatively. It is a useful low-morbidity technique, and there is no resorption or associated donor-site complications.

  15. Digital Hardware Architecture Implementation

    DTIC Science & Technology

    1993-02-15

    ergonomic design mechanical mouse that requires no mouse pad. i Its 1 /O capabilities include a 4MB/s SCSI- 11 interface, a high-throughput Ethernet ...Snated. The Frame Sta- 62 612 4 1 1 tus (FS) byte contains the SD AC FC IDESTI SRC IINFORMATION FCS ED FS5s A and C flags, which are used for...alternate topologies. 3.1.2.5 FDDI Bridges and Routers When migrating from IEEE 802 networks such as 10Mbps Ethernet and 16 Mbps Token ring to LANs

  16. Improving Arecibo Observatory's Hardware

    NASA Astrophysics Data System (ADS)

    Van Rooy, Paula; Whitlow, Dana; Seymour, Andrew

    2017-01-01

    The Puerto-rican Ultimate Pulsar Processing Instrument (PUPPI) is a key backend for time-domain observations at Arecibo Observatory. PUPPI enables pulsar timing used for gravitational wave studies, single pulse studies of pulsars, searches for new pulsars, and allows in depth studies of Fast Radio Bursts (FRBs). Unfortunately, PUPPI is presently restricted to only certain Arecibo receivers due to its input frequency and bandwidth requirements. Here we present the design process, building, bench testing, and updates on the implementation of a one-channel breadboard of a new frequency mixer at the Arecibo Observatory. The function of the frequency mixer design is to translate a 1.1-1.9 GHz band to 0.8 - 1.6 GHz band, where PUPPI samples the data at the second Nyquist zone. When this seemingly simple device is fully implemented, it will allow for the further expansion of the abilities of PUPPI. Mainly it will expand PUPPI's frequency agility to higher frequencies from 4 to 10 GHz, by enabling it to work with many more of Arecibo's receivers. We hope this becomes particularly useful, now that a FRB has been detected at these higher frequencies. The Arecibo Observatory is operated by SRI International under a cooperative agreement with the National Science Foundation (AST-1100968), and in alliance with Ana G. Méndez-Universidad Metropolitana, and the Universities Space Research Association. The Arecibo Observatory REU is funded under grant AST-1559849 to Universidad Metropolitana

  17. FUGM hardware operation manual

    SciTech Connect

    Wenz, T.R.; Menlove, H.O.; Halbig, J.K.

    1997-05-01

    This manual describes the detector design features, performance, and operating characteristics of the Fugen reactor gate monitor for monitoring fresh and spent fuel transfers between the core and storage ponds. This system consists of two monitors located at each end of the transfer chute. The larger monitor contains two {sup 3}He tubes, two fission chambers, and two ion chambers. The smaller monitor, used for direction of motion redundancy, contains two ion chambers. All detectors provide information for identifying the type, fresh or spent UOX or MOX fuel, and direction of the fuel transfer. The gamma-ray and neutron detector (GRAND-3) electronics package supplies power to the radiation sensors and collects the radiation data for storage on a laptop computer. The system is designed to operate unattended with data collection by the inspectors occurring on 90-day time intervals. This manual also includes radiation data for the six types of fuel transfers and equipment transfers along with the direction of motion information collected during the installation at the Fugen reactor.

  18. Reconfigurable Hardware Adapts to Changing Mission Demands

    NASA Technical Reports Server (NTRS)

    2003-01-01

    A new class of computing architectures and processing systems, which use reconfigurable hardware, is creating a revolutionary approach to implementing future spacecraft systems. With the increasing complexity of electronic components, engineers must design next-generation spacecraft systems with new technologies in both hardware and software. Derivation Systems, Inc., of Carlsbad, California, has been working through NASA s Small Business Innovation Research (SBIR) program to develop key technologies in reconfigurable computing and Intellectual Property (IP) soft cores. Founded in 1993, Derivation Systems has received several SBIR contracts from NASA s Langley Research Center and the U.S. Department of Defense Air Force Research Laboratories in support of its mission to develop hardware and software for high-assurance systems. Through these contracts, Derivation Systems began developing leading-edge technology in formal verification, embedded Java, and reconfigurable computing for its PF3100, Derivational Reasoning System (DRS ), FormalCORE IP, FormalCORE PCI/32, FormalCORE DES, and LavaCORE Configurable Java Processor, which are designed for greater flexibility and security on all space missions.

  19. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    SciTech Connect

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  20. Design and implementation of laser target simulator in hardware-in-the-loop simulation system based on LabWindows/CVI and RTX

    NASA Astrophysics Data System (ADS)

    Tong, Qiujie; Wang, Qianqian; Li, Xiaoyang; Shan, Bin; Cui, Xuntai; Li, Chenyu; Peng, Zhong

    2016-11-01

    In order to satisfy the requirements of the real-time and generality, a laser target simulator in semi-physical simulation system based on RTX+LabWindows/CVI platform is proposed in this paper. Compared with the upper-lower computers simulation platform architecture used in the most of the real-time system now, this system has better maintainability and portability. This system runs on the Windows platform, using Windows RTX real-time extension subsystem to ensure the real-time performance of the system combining with the reflective memory network to complete some real-time tasks such as calculating the simulation model, transmitting the simulation data, and keeping real-time communication. The real-time tasks of simulation system run under the RTSS process. At the same time, we use the LabWindows/CVI to compile a graphical interface, and complete some non-real-time tasks in the process of simulation such as man-machine interaction, display and storage of the simulation data, which run under the Win32 process. Through the design of RTX shared memory and task scheduling algorithm, the data interaction between the real-time tasks process of RTSS and non-real-time tasks process of Win32 is completed. The experimental results show that this system has the strongly real-time performance, highly stability, and highly simulation accuracy. At the same time, it also has the good performance of human-computer interaction.

  1. Design and Benchmarking of a Network-In-the-Loop Simulation for Use in a Hardware-In-the-Loop System

    NASA Technical Reports Server (NTRS)

    Aretskin-Hariton, Eliot D.; Thomas, George Lindsey; Culley, Dennis E.; Kratz, Jonathan L.

    2017-01-01

    Distributed engine control (DEC) systems alter aircraft engine design constraints be- cause of fundamental differences in the input and output communication between DEC and centralized control architectures. The change in the way communication is implemented may create new optimum engine-aircraft configurations. This paper continues the exploration of digital network communication by demonstrating a Network-In-the-Loop simulation at the NASA Glenn Research Center. This simulation incorporates a real-time network protocol, the Engine Area Distributed Interconnect Network Lite (EADIN Lite), with the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) software. The objective of this study is to assess digital control network impact to the control system. Performance is evaluated relative to a truth model for large transient maneuvers and a typical flight profile for commercial aircraft. Results show that a decrease in network bandwidth from 250 Kbps (sampling all sensors every time step) to 40 Kbps, resulted in very small differences in control system performance.

  2. MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

    NASA Technical Reports Server (NTRS)

    Crossin, Kent R.

    2005-01-01

    The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

  3. 77 FR 16661 - Tuberculosis in Cattle and Bison; State and Zone Designations; NM; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-22

    ... Inspection Service 9 CFR Part 77 Tuberculosis in Cattle and Bison; State and Zone Designations; NM... tuberculosis regulations by establishing two separate zones with different tuberculosis risk classifications... INFORMATION CONTACT: Dr. C. William Hench, Senior Staff Veterinarian, National Tuberculosis...

  4. Improved design of subcritical and supercritical cascades using complex characteristics and boundary layer correction

    NASA Technical Reports Server (NTRS)

    Sanz, J. M.

    1983-01-01

    The method of complex characteristics and hodograph transformation for the design of shockless airfoils was extended to design supercritical cascades with high solidities and large inlet angles. This capability was achieved by introducing a conformal mapping of the hodograph domain onto an ellipse and expanding the solution in terms of Tchebycheff polynomials. A computer code was developd based on this idea. A number of airfoils designed with the code are presented. Various supercritical and subcritical compressor, turbine and propeller sections are shown. The lag-entrainment method for the calculation of a turbulent boundary layer was incorporated to the inviscid design code. The results of this calculation are shown for the airfoils described. The elliptic conformal transformation developed to map the hodograph domain onto an ellipse can be used to generate a conformal grid in the physical domain of a cascade of airfoils with open trailing edges with a single transformation. A grid generated with this transformation is shown for the Korn airfoil.

  5. Hardware cleanliness methodology and certification

    NASA Technical Reports Server (NTRS)

    Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

    1995-01-01

    Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

  6. Hardware implementation of an electrostatic MEMS-actuator linearization

    NASA Astrophysics Data System (ADS)

    Mair, F.; Egretzberger, M.; Kugi, A.

    2011-06-01

    In this paper, an electrostatic actuator linearization will be introduced, which is based on an existing hardware-efficient iterative square root algorithm. The algorithm is solely based on add and shift operations while just needing n/2 iterations for an n bit wide input signal. As a practical example, the nonlinear input transformation will be utilized for the design of the primary mode controller of a capacitive MEMS gyroscope and an implementation of the algorithm in the Verilog hardware description language will be instantiated. Finally, measurement results will validate the feasibility of the presented control concept and its hardware implementation.

  7. The JPL telerobot operator control station. Part 1: Hardware

    NASA Technical Reports Server (NTRS)

    Kan, Edwin P.; Tower, John T.; Hunka, George W.; Vansant, Glenn J.

    1989-01-01

    The Operator Control Station of the Jet Propulsion Laboratory (JPL)/NASA Telerobot Demonstrator System provides the man-machine interface between the operator and the system. It provides all the hardware and software for accepting human input for the direct and indirect (supervised) manipulation of the robot arms and tools for task execution. Hardware and software are also provided for the display and feedback of information and control data for the operator's consumption and interaction with the task being executed. The hardware design, system architecture, and its integration and interface with the rest of the Telerobot Demonstrator System are discussed.

  8. Optimal Design for Nonperiodic Fine Grating Structure Controlled by Proximity Correction with Electron-Beam Lithography

    NASA Astrophysics Data System (ADS)

    Okano, Masato; Hirai, Yoshihiko; Kikuta, Hisao

    2007-02-01

    We describe a method for designing nonperiodic fine grating structures such as a small F-number diffractive cylindrical lens, to be fabricated by direct-writing electron-beam lithography. The design is based on a resist development simulator for estimating a proximity effect of electron dose and the finite difference time domain (FDTD) method for simulating an electromagnetic field. The surface profile and electron dose distribution are simultaneously optimized to obtain the high diffraction efficiency. For the design of a diffractive lens of 50 μm width and 25 μm focal length, the calculated diffraction efficiency is 49% for 650-nm-wavelength light, which is slightly lower than that of a diffractive lens profile optimized by electromagnetic analysis without restrictions on fabrication limits.

  9. 78 FR 28291 - Unblocking of 1 Individual Designated Pursuant to Executive Order 13572; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-14

    ... Persons with Respect to Human Rights Abuses in Syria'' from the list of Specially Designated Nationals and... Abuses in Syria,'' (the ``Order'') pursuant to, inter alia, the International Emergency Economic Powers....a. KUZBARI, Ahmad Nabil; a.k.a. KUZBARI, Nabil R.); DOB 20 Sep 1936; POB Damascus, Syria;...

  10. Improved design of subcritical and supercritical cascades using complex characteristics and boundary-layer correction

    NASA Technical Reports Server (NTRS)

    Sanz, J. M.

    1984-01-01

    The method of complex characteristics and hodograph transformation for the design of shockless airfoils was extended to design supercritical cascades with high solidities and large inlet angles. This capability was achieved by introducing a conformal mapping of the hodograph domain onto an ellipse and expanding the solution in terms of Tchebycheff polynomials. A computer code was developed based on this idea. A number of airfoils designed with the code are presented. Various supercritical and subcritical compressor, turbine and propeller sections are shown. The lag-entrainment method for the calculation of a turbulent boundary layer was incorporated to the inviscid design code. The results of this calculation are shown for the airfoils described. The elliptic conformal transformation developed to map the hodograph domain onto an ellipse can be used to generate a conformal grid in the physical domain of a cascade of airfoils with open trailing edges with a single transformation. A grid generated with this transformation is shown for the Korn airfoil. Previously announced in STAR as N83-24474

  11. Reconfigurable Hardware for Compressing Hyperspectral Image Data

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

    2010-01-01

    High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

  12. Hardware Evolution of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

  13. Modulator design for x-ray scatter correction using primary modulation: Material selection

    SciTech Connect

    Gao Hewei; Zhu Lei; Fahrig, Rebecca

    2010-08-15

    Purpose: An optimal material selection for primary modulator is proposed in order to minimize beam hardening of the modulator in x-ray cone-beam computed tomography (CBCT). Recently, a measurement-based scatter correction method using primary modulation has been developed and experimentally verified. In the practical implementation, beam hardening of the modulator blocker is a limiting factor because it causes inconsistency in the primary signal and therefore degrades the accuracy of scatter correction. Methods: This inconsistency can be purposely assigned to the effective transmission factor of the modulator whose variation as a function of object filtration represents the magnitude of beam hardening of the modulator. In this work, the authors show that the variation reaches a minimum when the K-edge of the modulator material is near the mean energy of the system spectrum. Accordingly, an optimal material selection can be carried out in three steps. First, estimate and evaluate the polychromatic spectrum for a given x-ray system including both source and detector; second, calculate the mean energy of the spectrum and decide the candidate materials whose K-edge energies are near the mean energy; third, select the optimal material from the candidates after considering both the magnitude of beam hardening and the physical and chemical properties. Results: A tabletop x-ray CBCT system operated at 120 kVp is used to validate the material selection method in both simulations and experiments, from which the optimal material for this x-ray system is then chosen. With the transmission factor initially being 0.905 and 0.818, simulations show that erbium provides the least amount of variation as a function of object filtrations (maximum variations are 2.2% and 4.3%, respectively, only one-third of that for copper). With different combinations of aluminum and copper filtrations (simulating a range of object thicknesses), measured overall variations are 2.5%, 1.0%, and 8

  14. Line array transmission sources for SPECT attenuation correction: design and reconstruction

    NASA Astrophysics Data System (ADS)

    Hawman, E. G.; Rempel, T. D.; Vija, A. H.; Engdahl, J. C.

    2005-04-01

    Correction for non-uniform attenuation in SPECT generally requires measurements of radiation transmittance through the patient and reconstruction of the data to form an attenuation image, or mu-map. For nuclear cardiac studies it useful if the emission and transmission data for each projection view can be acquired simultaneously using non-overlapping energy windows. This simplifies the registration of the emission and transmission data. Large area transmission sources are desirable to avoid data truncation; however, 2D-planar liquid sources are cumbersome and extended solid area sources of Gd-153 or Am-247 are impractical. Co-57 sheet sources present spectral overlap problems for imaging of Tc-99m tracers. With Gd-153 line arrays, one can achieve the benefits of 2D-planar sources, low truncation and simultaneous emission/transmission measurements, using lightweight static mechanical attachments to the SPECT camera system. A new method is proposed to determine optimal positions for the lines of the transmission array based on maximizing the entropy of the transmitted flux through the patient. Transmission reconstruction using parallel beam filtered back-projection yields attenuation maps with poor spatial resolution and significant aliasing effects. The degradations of image quality become worse as the angular separations of the lines as seen by the detector increase. To improve the reconstruction of line array transmission data a maximum likelihood modified gradient algorithm was derived. The algorithm takes into account emission-to-transmission down scatter as well as the overlapping of radiation patterns of the individual lines. Ordered subset versions of algorithms are explored. Image quality is assessed with simulations based on an attenuation map derived from CT.

  15. Design of microcamera for field curvature and distortion correction in monocentric multiscale foveated imaging system

    NASA Astrophysics Data System (ADS)

    Wu, Xiongxiong; Wang, Xiaorui; Zhang, Jianlei; Yuan, Ying; Chen, Xiaoxiang

    2017-04-01

    To realize large field of view (FOV) and high-resolution dynamic gaze of the moving target, this paper proposes the monocentric multiscale foveated (MMF) imaging system based on monocentric multiscale design and foveated imaging. First we present the MMF imaging system concept. Then we analyze large field curvature and distortion of the secondary image when the spherical intermediate image produced by the primary monocentric objective lens is relayed by the microcameras. Further a type of zoom endoscope objective lens is selected as the initial structure and optimized to minimize the field curvature and distortion with ZEMAX optical design software. The simulation results show that the maximum field curvature in full field of view is below 0.25 mm and the maximum distortion in full field of view is below 0.6%, which can meet the requirements of the microcamera in the proposed MMF imaging system. In addition, a simple doublet is used to design the foveated imaging system. Results of the microcamera together with the foveated imager compose the results of the whole MMF imaging system.

  16. Design of splints based on the NiTi alloy for the correction of joint deformities in the fingers

    PubMed Central

    2010-01-01

    Background The proximal interphalange joint (PIP) is fundamental for the functional nature of the hand. The contracture in flexion of the PIP, secondary to traumatisms or illnesses leads to an important functional loss. The use of correcting splints is the common procedure for treating this problem. Its functioning is based on the application of a small load and a prolonged stress which can be dynamic, static progressive or static serial. It is important that the therapist has a splint available which can release a constant and sufficient force to correct the contracture in flexion. Nowadays NiTi is commonly used in bio-engineering, due to its superelastical characteristics. The experience of the authors in the design of other devices based on the NiTi alloy, makes it possible to carry out a new design in this work - the production of a finger splint for the treatment of the contracture in flexion of the PIP joint. Methods Commercial orthosis have been characterized using a universal INSTRON 5565 machine. A computational simulation of the proposed design has been conducted, reproducing its performance and using a model "ad hoc" for the NiTi material. Once the parameters have been adjusted, the design is validated using the same type of test as those carried out on commercial orthosis. Results and Discussion For commercial splint the recovering force falls to excessively low values as the angle increases. Angle curves for different lengths and thicknesses of the proposed design have been obtained, with a practically constant recovering force value over a wide range of angles that vary between 30° and 150° in every case. Then the whole treatment is possible with only one splint, and without the need of progressive replacements as the joint recovers. Conclusions A new model of splint based on NiTi alloy has been designed, simulated and tested comparing its behaviour with two of the most regularly used splints. Its uses is recommended instead of other dynamic

  17. ROMPS critical design review. Volume 1: Hardware

    NASA Technical Reports Server (NTRS)

    Dobbs, M. E.

    1992-01-01

    Topics concerning the Robot-Operated Material Processing in Space (ROMPS) Program are presented in viewgraph form and include the following: a systems overview; servocontrol and servomechanisms; testbed and simulation results; system V controller; robot module; furnace module; SCL experiment supervisor; SCL script sample processing control; SCL experiment supervisor fault handling; block diagrams; hitchhiker interfaces; battery systems; watchdog timers; mechanical/thermal systems; and fault conditions and recovery.

  18. Design and Hardware Implementation of Neural Systems.

    DTIC Science & Technology

    1991-12-15

    orientation specificity in a neuron network for visual image decomposition. AIP Conference on Neuronal Networks for Computing, Snowbird, Utah, April, 1989...P. and Blackman, D. Orientation tuning and orientation specificity in a neuron network for visual image decomposition. AIP Conference on Neuronal ... Networks for Computing, Snowbird, Utah, April, 1989. Mueller, P., Neural computation of pattern primitives, (Abstract) AIP Conference, Snowbird, Utah

  19. Microcomputer Hardware. Energy Technology Series.

    ERIC Educational Resources Information Center

    Technical Education Research Centre-Southwest, Waco, TX.

    This course in microcomputer hardware is one of 16 courses in the Energy Technology Series developed for an Energy Conservation-and-Use Technology curriculum. Intended for use in two-year postsecondary technical institutions to prepare technicians for employment, the courses are also useful in industry for updating employees in company-sponsored…

  20. Hardware Selection: A Nontechnical Approach.

    ERIC Educational Resources Information Center

    Kiteka, Sebastian F.

    Presented in nontechnical language, this guide suggests criteria for the selection of three computer hardware essentials--a microcomputer, a monitor, and a printer. Factors to be considered in selecting the microcomputer are identified and discussed, including what the computer is to be used for, dealer support, software availability, modem…

  1. A successful 3D seismic survey in the ``no-data zone,`` offshore Mississippi delta: Survey design and refraction static correction processing

    SciTech Connect

    Carvill, C.; Faris, N.; Chambers, R.

    1996-12-31

    This is a success story of survey design and refraction static correction processing of a large 3D seismic survey in the South Pass area of the Mississippi delta. In this transition zone, subaqueous mudflow gullies and lobes of the delta, in various states of consolidation and gas saturation, are strong absorbers of seismic energy. Seismic waves penetrating the mud are severely restricted in bandwidth and variously delayed by changes in mud velocity and thickness. Using a delay-time refraction static correction method, the authors find compensation for the various delays, i.e., static corrections, commonly vary 150 ms over a short distance. Application of the static corrections markedly improves the seismic stack volume. This paper shows that intelligent survey design and delay-time refraction static correction processing economically eliminate the historic no data status of this area.

  2. Optical design considerations when imaging the fundus with an adaptive optics correction

    NASA Astrophysics Data System (ADS)

    Wang, Weiwei; Campbell, Melanie C. W.; Kisilak, Marsha L.; Boyd, Shelley R.

    2008-06-01

    Adaptive Optics (AO) technology has been used in confocal scanning laser ophthalmoscopes (CSLO) which are analogous to confocal scanning laser microscopes (CSLM) with advantages of real-time imaging, increased image contrast, a resistance to image degradation by scattered light, and improved optical sectioning. With AO, the instrumenteye system can have low enough aberrations for the optical quality to be limited primarily by diffraction. Diffraction-limited, high resolution imaging would be beneficial in the understanding and early detection of eye diseases such as diabetic retinopathy. However, to maintain diffraction-limited imaging, sufficient pixel sampling over the field of view is required, resulting in the need for increased data acquisition rates for larger fields. Imaging over smaller fields may be a disadvantage with clinical subjects because of fixation instability and the need to examine larger areas of the retina. Reduction in field size also reduces the amount of light sampled per pixel, increasing photon noise. For these reasons, we considered an instrument design with a larger field of view. When choosing scanners to be used in an AOCSLO, the ideal frame rate should be above the flicker fusion rate for the human observer and would also allow user control of targets projected onto the retina. In our AOCSLO design, we have studied the tradeoffs between field size, frame rate and factors affecting resolution. We will outline optical approaches to overcome some of these tradeoffs and still allow detection of the earliest changes in the fundus in diabetic retinopathy.

  3. Hardware Development Process for Human Research Facility Applications

    NASA Technical Reports Server (NTRS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

  4. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    The DOD and NASA inertial upper stage communication system design, hardware specifications and interfaces were analyzed to determine their compatibility with the Orbiter payload communications equipment (Payload Interrogator, Payload Signal Processors, Communications Interface Unit, and the Orbiter operational communications equipment (the S-Band and Ku-band systems). Topics covered include (1) IUS/shuttle Orbiter communications interface definition; (2) Orbiter avionics equipment serving the IUS; (3) IUS communication equipment; (4) IUS/shuttle Orbiter RF links; (5) STDN/TDRS S-band related activities; and (6) communication interface unit/Orbiter interface issues. A test requirement plan overview is included.

  5. Open Hardware for CERN's accelerator control systems

    NASA Astrophysics Data System (ADS)

    van der Bij, E.; Serrano, J.; Wlostowski, T.; Cattin, M.; Gousiou, E.; Alvarez Sanchez, P.; Boccardi, A.; Voumard, N.; Penacoba, G.

    2012-01-01

    The accelerator control systems at CERN will be upgraded and many electronics modules such as analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on the FPGA Mezzanine Card, PCI Express and VME64x standards while the Wishbone specification is used as a system on a chip bus. To attract partners, the projects are developed in an `Open' fashion. Within this Open Hardware project new ways of working with industry are being evaluated and it has been proven that industry can be involved at all stages, from design to production and support.

  6. Workmanship Challenges for NASA Mission Hardware

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette

    2010-01-01

    This slide presentation reviews several challenges in workmanship for NASA mission hardware development. Several standards for NASA workmanship exist, that are required for all programs, projects, contracts and subcontracts. These Standards contain our best known methods for avoiding past assembly problems and defects. These best practices may not be available if suppliers are used who are not compliant with them. Compliance includes having certified operators and inspectors. Some examples of problems that have occured from the lack of requirements flow-down to contractors are reviewed. The presentation contains a detailed example of the challenge in regards to The Packaging "Design" Dilemma.

  7. INTEGRATED MONITORING HARDWARE DEVELOPMENTS AT LOS ALAMOS

    SciTech Connect

    R. PARKER; J. HALBIG; ET AL

    1999-09-01

    The hardware of the integrated monitoring system supports a family of instruments having a common internal architecture and firmware. Instruments can be easily configured from application-specific personality boards combined with common master-processor and high- and low-voltage power supply boards, and basic operating firmware. The instruments are designed to function autonomously to survive power and communication outages and to adapt to changing conditions. The personality boards allow measurement of gross gammas and neutrons, neutron coincidence and multiplicity, and gamma spectra. In addition, the Intelligent Local Node (ILON) provides a moderate-bandwidth network to tie together instruments, sensors, and computers.

  8. Monte Carlo-based diode design for correction-less small field dosimetry.

    PubMed

    Charles, P H; Crowe, S B; Kairn, T; Knight, R T; Hill, B; Kenny, J; Langton, C M; Trapp, J V

    2013-07-07

    Due to their small collecting volume, diodes are commonly used in small field dosimetry. However, the relative sensitivity of a diode increases with decreasing small field size. Conversely, small air gaps have been shown to cause a significant decrease in the sensitivity of a detector as the field size is decreased. Therefore, this study uses Monte Carlo simulations to look at introducing air upstream to diodes such that they measure with a constant sensitivity across all field sizes in small field dosimetry. Varying thicknesses of air were introduced onto the upstream end of two commercial diodes (PTW 60016 photon diode and PTW 60017 electron diode), as well as a theoretical unenclosed silicon chip using field sizes as small as 5 mm × 5 mm. The metric D(w,Q)/D(Det,Q) used in this study represents the ratio of the dose to a point of water to the dose to the diode active volume, for a particular field size and location. The optimal thickness of air required to provide a constant sensitivity across all small field sizes was found by plotting D(w,Q)/D(Det,Q) as a function of introduced air gap size for various field sizes, and finding the intersection point of these plots. That is, the point at which D(w,Q)/D(Det,Q) was constant for all field sizes was found. The optimal thickness of air was calculated to be 3.3, 1.15 and 0.10 mm for the photon diode, electron diode and unenclosed silicon chip, respectively. The variation in these results was due to the different design of each detector. When calculated with the new diode design incorporating the upstream air gap, k(f(clin),f(msr))(Q(clin),Q(msr)) was equal to unity to within statistical uncertainty (0.5%) for all three diodes. Cross-axis profile measurements were also improved with the new detector design. The upstream air gap could be implanted on the commercial diodes via a cap consisting of the air cavity surrounded by water equivalent material. The results for the unclosed silicon chip show that an ideal small

  9. Monte Carlo-based diode design for correction-less small field dosimetry

    NASA Astrophysics Data System (ADS)

    Charles, P. H.; Crowe, S. B.; Kairn, T.; Knight, R. T.; Hill, B.; Kenny, J.; Langton, C. M.; Trapp, J. V.

    2013-07-01

    Due to their small collecting volume, diodes are commonly used in small field dosimetry. However, the relative sensitivity of a diode increases with decreasing small field size. Conversely, small air gaps have been shown to cause a significant decrease in the sensitivity of a detector as the field size is decreased. Therefore, this study uses Monte Carlo simulations to look at introducing air upstream to diodes such that they measure with a constant sensitivity across all field sizes in small field dosimetry. Varying thicknesses of air were introduced onto the upstream end of two commercial diodes (PTW 60016 photon diode and PTW 60017 electron diode), as well as a theoretical unenclosed silicon chip using field sizes as small as 5 mm × 5 mm. The metric \\frac{{D_{w,Q} }}{{D_{Det,Q} }} used in this study represents the ratio of the dose to a point of water to the dose to the diode active volume, for a particular field size and location. The optimal thickness of air required to provide a constant sensitivity across all small field sizes was found by plotting \\frac{{D_{w,Q} }}{{D_{Det,Q} }} as a function of introduced air gap size for various field sizes, and finding the intersection point of these plots. That is, the point at which \\frac{{D_{w,Q} }}{{D_{Det,Q} }} was constant for all field sizes was found. The optimal thickness of air was calculated to be 3.3, 1.15 and 0.10 mm for the photon diode, electron diode and unenclosed silicon chip, respectively. The variation in these results was due to the different design of each detector. When calculated with the new diode design incorporating the upstream air gap, k_{Q_{clin} ,Q_{msr} }^{f_{clin} ,f_{msr} } was equal to unity to within statistical uncertainty (0.5%) for all three diodes. Cross-axis profile measurements were also improved with the new detector design. The upstream air gap could be implanted on the commercial diodes via a cap consisting of the air cavity surrounded by water equivalent material. The

  10. Mapping of topological quantum circuits to physical hardware.

    PubMed

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-04-11

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  11. CASIS Fact Sheet: Hardware and Facilities

    NASA Technical Reports Server (NTRS)

    Solomon, Michael R.; Romero, Vergel

    2016-01-01

    Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

  12. Hardware acceleration of image recognition through a visual cortex model

    NASA Astrophysics Data System (ADS)

    Rice, Kenneth L.; Taha, Tarek M.; Vutsinas, Christopher N.

    2008-09-01

    Recent findings in neuroscience have led to the development of several new models describing the processes in the neocortex. These models excel at cognitive applications such as image analysis and movement control. This paper presents a hardware architecture to speed up image content recognition through a recently proposed model of the visual cortex. The system is based on a set of parallel computation nodes implemented in an FPGA. The design was optimized for hardware by reducing the data storage requirements, and removing the need for multiplies and divides. The reconfigurable logic hardware implementation running at 121 MHz provided a speedup of 148 times over a 2 GHz AMD Opteron processor. The results indicate the feasibility of specialized hardware to accelerate larger biological scale implementations of the model.

  13. Open Source Hardware for DIY Environmental Sensing

    NASA Astrophysics Data System (ADS)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  14. Hardware Support for Software Debugging

    DTIC Science & Technology

    2011-05-01

    Architecture • Concurrency Debugging - ReEnact • Conclusions Cost of Software Defects • Financial Costs • In a study by NIST in 2002 it was found that... ReEnact • Leverages modified Thread-Level Speculation (TLS) hardware • Create partial orderings of threads in a multithreaded program using...logical vector clocks • Using these orderings, ReEnact is able to detect and often repair data race conditions in a multithreaded program • Experiments

  15. Hunting for hardware changes in data centres

    NASA Astrophysics Data System (ADS)

    Coelho dos Santos, M.; Steers, I.; Szebenyi, I.; Xafi, A.; Barring, O.; Bonfillou, E.

    2012-12-01

    With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

  16. UniBoard: generic hardware for radio astronomy signal processing

    NASA Astrophysics Data System (ADS)

    Hargreaves, J. E.

    2012-09-01

    UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

  17. Apollo Guidance, Navigation, and Control (GNC) Hardware Overview

    NASA Technical Reports Server (NTRS)

    Interbartolo, Michael

    2009-01-01

    This viewgraph presentation reviews basic guidance, navigation and control (GNC) concepts, examines the Command and Service Module (CSM) and Lunar Module (LM) GNC organization and discusses the primary GNC and the CSM Stabilization and Control System (SCS), as well as other CSM-specific hardware. The LM Abort Guidance System (AGS), Control Electronics System (CES) and other LM-specific hardware are also addressed. Three subsystems exist on each vehicle: the computer subsystem (CSS), the inertial subsystem (ISS) and the optical subsystem (OSS). The CSS and ISS are almost identical between CSM and LM and each is designed to operate independently. CSM SCS hardware are highlighted, including translation control, rotation controls, gyro assemblies, a gyro display coupler and flight director attitude indicators. The LM AGS hardware are also highlighted and include the abort electronics assembly and the abort sensor assembly; while the LM CES hardware includes the attitude controller assembly, thrust/translation controller assemblies and the ascent engine arming assemble. Other common hardware including the Orbital Rate Display - Earth and Lunar (ORDEAL) and the Crewman Optical Alignment Sight (COAS), a docking aid, are also highlighted.

  18. On the use of inexact, pruned hardware in atmospheric modelling

    PubMed Central

    Düben, Peter D.; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V.; Palmer, T. N.

    2014-01-01

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models. PMID:24842031

  19. Evaluation of next generation hardware for lithography processing

    NASA Astrophysics Data System (ADS)

    Shimoaoki, T.; Enomoto, M.; Nafus, K.; Marumoto, H.; Kosugi, H.; Mallmann, J.; Maas, R.; Verspaget, C.; van der Heijden, E.; Wang, S.

    2010-04-01

    This work is the summary of improvements in processing capability implemented and tested on the LITHIUS ProTM -i / TWINSCANTM XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

  20. Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

    NASA Technical Reports Server (NTRS)

    Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

    2003-01-01

    Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

  1. Effects of the preventive and corrective adjustments in economical designs for online process control for attributes with misclassification errors

    NASA Astrophysics Data System (ADS)

    Quinino, Roberto C.; Ho, Linda Lee

    2010-01-01

    The procedure for online process control by attributes consists of inspecting a single item at every m produced items. It is decided on the basis of the inspection result whether the process is in-control (the conforming fraction is stable) or out-of-control (the conforming fraction is decreased, for example). Most articles about online process control have cited the stoppage of the production process for an adjustment when the inspected item is non-conforming (then the production is restarted in-control, here denominated as corrective adjustment). Moreover, the articles related to this subject do not present semi-economical designs (which may yield high quantities of non-conforming items), as they do not include a policy of preventive adjustments (in such case no item is inspected), which can be more economical, mainly if the inspected item can be misclassified. In this article, the possibility of preventive or corrective adjustments in the process is decided at every m produced item. If a preventive adjustment is decided upon, then no item is inspected. On the contrary, the m-th item is inspected; if it conforms, the production goes on, otherwise, an adjustment takes place and the process restarts in-control. This approach is economically feasible for some practical situations and the parameters of the proposed procedure are determined minimizing an average cost function subject to some statistical restrictions (for example, to assure a minimal level-fixed in advance-of conforming items in the production process). Numerical examples illustrate the proposal.

  2. Extensible Hardware Architecture for Mobile Robots

    NASA Technical Reports Server (NTRS)

    Park, Eric; Kobayashi, Linda; Lee, Susan Y.

    2005-01-01

    The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

  3. Hardware and software reliability estimation using simulations

    NASA Technical Reports Server (NTRS)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  4. Efficient BinDCT hardware architecture exploration and implementation on FPGA.

    PubMed

    Ben Abdelali, Abdessalem; Chatti, Ichraf; Hannachi, Marwa; Mtibaa, Abdellatif

    2016-11-01

    This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

  5. Solid-Liquid Interface Characterization Hardware

    NASA Technical Reports Server (NTRS)

    Peters, Palmer N.

    2000-01-01

    The objective is to develop enabling technology to characterize the solid-liquid interface during directional solidification to unprecedented levels with real-time measurement hardware. Existing x-ray imaging hardware is combined with compact Seebeck furnaces and thermal profiling hardware, under development, to accomplish the measurements. Furnace thermal profiles are continuously measured in addition to the sample characteristics.

  6. GENI: Grid Hardware and Software

    SciTech Connect

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  7. Design study of Software-Implemented Fault-Tolerance (SIFT) computer

    NASA Technical Reports Server (NTRS)

    Wensley, J. H.; Goldberg, J.; Green, M. W.; Kutz, W. H.; Levitt, K. N.; Mills, M. E.; Shostak, R. E.; Whiting-Okeefe, P. M.; Zeidler, H. M.

    1982-01-01

    Software-implemented fault tolerant (SIFT) computer design for commercial aviation is reported. A SIFT design concept is addressed. Alternate strategies for physical implementation are considered. Hardware and software design correctness is addressed. System modeling and effectiveness evaluation are considered from a fault-tolerant point of view.

  8. Electronic processing and control system with programmable hardware

    NASA Technical Reports Server (NTRS)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  9. Correction of a skeletal Class II malocclusion with severe crowding by a specially designed rapid maxillary expander.

    PubMed

    Wang, Honghong; Feng, Jing; Lu, Peijun; Shen, Gang

    2015-02-01

    To correct an Angle Class II malocclusion or to create spaces in the maxillary arch by nonextraction treatment, distal movement of the maxillary molars is required. Various modalities for distalizing the buccal segment have been reported. Conventional extraoral appliances can be used to obtain maximum anchorage. However, many patients reject headgear wear because of social and esthetic concerns, and the success of this treatment depends on patient compliance. Intraoral appliances, such as repelling magnets, nickel-titanium coils, pendulum appliance, Jones jig appliance, distal jet appliance, and modified Nance appliance, have been introduced to distalize the molars with little or no patient cooperation. However, intraoral appliances can result in anchorage loss of the anterior teeth and distal tipping of the maxillary molars. In this case report, we introduce a diversified rapid maxillary expansion appliance that was custom designed and fabricated for the treatment of a growing girl with a skeletal Class II malocclusion and severe crowding from a totally lingually positioned lateral incisor. The appliance concomitantly expanded the maxilla transversely and retracted the buccal segment sagittally, distalizing the maxillary molars to reach a Class I relationship and creating the spaces to displace the malpositioned lateral incisor. The uniqueness of this special diversified rapid maxillary expansion appliance was highlighted by a series of reconstructions and modifications at different stages of the treatment to reinforce the anchorage.

  10. Hardware-efficient low-power image processing system for wireless capsule endoscopy.

    PubMed

    Turcza, Pawel; Duplaga, Mariusz

    2013-11-01

    This paper presents the design of a hardware-efficient, low-power image processing system for next-generation wireless endoscopy. The presented system is composed of a custom CMOS image sensor, a dedicated image compressor, a forward error correction (FEC) encoder protecting radio transmitted data against random and burst errors, a radio data transmitter, and a controller supervising all operations of the system. The most significant part of the system is the image compressor. It is based on an integer version of a discrete cosine transform and a novel, low complexity yet efficient, entropy encoder making use of an adaptive Golomb-Rice algorithm instead of Huffman tables. The novel hardware-efficient architecture designed for the presented system enables on-the-fly compression of the acquired image. Instant compression, together with elimination of the necessity of retransmitting erroneously received data by their prior FEC encoding, significantly reduces the size of the required memory in comparison to previous systems. The presented system was prototyped in a single, low-power, 65-nm field programmable gate arrays (FPGA) chip. Its power consumption is low and comparable to other application-specific-integrated-circuits-based systems, despite FPGA-based implementation.

  11. Field-programmable gate array-based hardware architecture for high-speed camera with KAI-0340 CCD image sensor

    NASA Astrophysics Data System (ADS)

    Wang, Hao; Yan, Su; Zhou, Zuofeng; Cao, Jianzhong; Yan, Aqi; Tang, Linao; Lei, Yangjie

    2013-08-01

    We present a field-programmable gate array (FPGA)-based hardware architecture for high-speed camera which have fast auto-exposure control and colour filter array (CFA) demosaicing. The proposed hardware architecture includes the design of charge coupled devices (CCD) drive circuits, image processing circuits, and power supply circuits. CCD drive circuits transfer the TTL (Transistor-Transistor-Logic) level timing Sequences which is produced by image processing circuits to the timing Sequences under which CCD image sensor can output analog image signals. Image processing circuits convert the analog signals to digital signals which is processing subsequently, and the TTL timing, auto-exposure control, CFA demosaicing, and gamma correction is accomplished in this module. Power supply circuits provide the power for the whole system, which is very important for image quality. Power noises effect image quality directly, and we reduce power noises by hardware way, which is very effective. In this system, the CCD is KAI-0340 which is can output 210 full resolution frame-per-second, and our camera can work outstandingly in this mode. The speed of traditional auto-exposure control algorithms to reach a proper exposure level is so slow that it is necessary to develop a fast auto-exposure control method. We present a new auto-exposure algorithm which is fit high-speed camera. Color demosaicing is critical for digital cameras, because it converts a Bayer sensor mosaic output to a full color image, which determines the output image quality of the camera. Complexity algorithm can acquire high quality but cannot implement in hardware. An low-complexity demosaicing method is presented which can implement in hardware and satisfy the demand of quality. The experiment results are given in this paper in last.

  12. Product Assurance for Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Monroe, Mike

    1995-01-01

    This report contains information about the tasks I have completed and the valuable experience I have gained at NASA. The report is divided into two different sections followed by a program summary sheet. The first section describes the two reports I have completed for the Office of Mission Assurance (OMA). I describe the approach and the resources and facilities used to complete each report. The second section describes my experience working in the Receipt Inspection/Quality Assurance Lab (RI/QA). The first report described is a Product Assurance Plan for the Gas Permeable Polymer Materials (GPPM) mission. The purpose of the Product Assurance Plan is to define the various requirements which are to be met through completion of the GPPM mission. The GPPM experiment is a space payload which will be flown in the shuttle's SPACEHAB module. The experiment will use microgravity to enable production of complex polymeric gas permeable materials. The second report described in the first section is a Fracture Analysis for the Mir Environmental Effects Payload (MEEP). The Fracture Analysis report is a summary of the fracture control classifications for all structural elements of the MEEP. The MEEP hardware consists of four experiment carriers, each of which contains an experiment container holding a passive experiment. The MEEP hardware will be attached to the cargo bay of the space shuttle. It will be transferred by Extravehicular Activity and mounted on the Mir space station. The second section of this report describes my experiences in the RVQA lab. I listed the different equipment I used at the lab and their functions. I described the extensive inspection process that must be completed for spaceflight hardware. Included, at the end of this section, are pictures of most of the equipment used in the lab. There is a summary sheet located at the end of this report. It briefly describes the valuable experience I have gained at NASA this summer and what I will be able to take

  13. Neural Networks Based Approach to Enhance Space Hardware Reliability

    NASA Technical Reports Server (NTRS)

    Zebulum, Ricardo S.; Thakoor, Anilkumar; Lu, Thomas; Franco, Lauro; Lin, Tsung Han; McClure, S. S.

    2011-01-01

    This paper demonstrates the use of Neural Networks as a device modeling tool to increase the reliability analysis accuracy of circuits targeted for space applications. The paper tackles a number of case studies of relevance to the design of Flight hardware. The results show that the proposed technique generates more accurate models than the ones regularly used to model circuits.

  14. Fastener Retention Requirements and Practices in Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Dasgupta, Rajib

    2004-01-01

    This presentation reviews the requirements for safety critical fasteners in spaceflight hardware. Included in the presentation are design guidelines and information for Locking Helicoils, key locked inserts and thinwalled inserts, self locking screws and bolts. locknuts, and a locking adhesives, Loctite and Vibratite.

  15. Combine Security and Safety with the Right Door Hardware.

    ERIC Educational Resources Information Center

    Olmstead, Patrick R.

    1999-01-01

    Discusses how door design and construction can add safety and security to educational facilities. Exit device variations, and electromagnetic locks and access control are explored. Also discussed are inexpensive ways to improve the safety and security profiles of a building using door hardware. (GR)

  16. The Certification of Environmental Chambers for Testing Flight Hardware

    NASA Technical Reports Server (NTRS)

    Fields, Keith

    2009-01-01

    The JPL chamber certification process for ensuring that test chambers used to test flight hardware meet a minimum standard is critical to the safety of the hardware and personnel. Past history as demonstrated that this process is important due to the catastrophic incidents that could occur if the chamber is not set up correctly. Environmental testing is one of the last phases in the development of a subsystem, and it typically occurs just before integration of flight hardware into the fully assembled flight system. A seemingly insignificant -miscalculation or missed step can necessitate rebuilding or replacing a subsystem due to over-testing or damage from the test chamber. Conversely, under-testing might fail to detect weaknesses that might cause failure when the hardware is in service. This paper describes the process that identifies the many variables that comprise the testing scenario and screening of as built chambers, the training of qualified operators, and a general "what-to-look-for" in minimum standards.

  17. The Certification of Environmental Chambers for Testing Flight Hardware

    NASA Technical Reports Server (NTRS)

    Fields, Keith

    2010-01-01

    The JPL chamber certification process for ensuring that test chambers used to test flight hardware meet a minimum standard is critical to the safety of the hardware and personnel. Past history has demonstrated that this process is important due to the catastrophic incidents that could occur if the chamber is not set up correctly. Environmental testing is one of the last phases in the development of a subsystem, and it typically occurs just before integration of flight hardware into the fully assembled flight system. A seemingly insignificant -miscalculation or missed step can necessitate rebuilding or replacing a subsystem due to over-testing or damage from the test chamber. Conversely, under-testing might fail to detect weaknesses that might cause failure when the hardware is in service. This paper describes the process that identifies the many variables that comprise the testing scenario and screening of as built chambers, the training of qualified operators, and a general "what-to-look-for" in minimum standards.

  18. A Computer Scientist’s Evaluation of Publically Available Hardware Trojan Benchmarks

    DTIC Science & Technology

    2015-09-01

    application-specific integrated circuit COTS commercial off-the-shelf DEF design exchange file DSP digital signal processor FPGA field-programmable gate...is a deliberate alteration to a piece of electronic hardware that causes that device, under certain conditions, to display undocumented...functionality. Hardware Trojans may be added to varying items of hardware, including application-specific integrated circuits (ASICs), digital signal

  19. Space biology initiative program definition review. Trade study 3: Hardware miniaturization versus cost

    NASA Technical Reports Server (NTRS)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Herbert, Frank J.; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The optimum hardware miniaturization level with the lowest cost impact for space biology hardware was determined. Space biology hardware and/or components/subassemblies/assemblies which are the most likely candidates for application of miniaturization are to be defined and relative cost impacts of such miniaturization are to be analyzed. A mathematical or statistical analysis method with the capability to support development of parametric cost analysis impacts for levels of production design miniaturization are provided.

  20. Surface moisture measurement system hardware acceptance test report

    SciTech Connect

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  1. Low-power hardware for neural spike compression in BMIs.

    PubMed

    Lapolli, Ângelo C; Coppa, Bertrand; Héliot, Rodolphe

    2013-01-01

    Within brain-machine interface systems, cortically implanted microelectrode arrays and associated hardware have a low-power budget for data sampling, processing, and transmission. Recent studies have shown the feasibility of data transmission rate reduction using compressed sensing on detected neural spikes. They provide power savings while maintaining clustering and classification abilities. We propose and analyze here a low-power hardware implementation for spike detection and compression. The resulting integrated circuit, designed in CMOS 65 nm technology, consumes 2.83 µW and provides 97% of data rate reduction.

  2. Design for the correction system of the real time nonuniformity of large area-array CCD image

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Li, Chunmei; Lei, Ning

    2012-10-01

    With the robust thriving of aviation cameras and remote sensing technology, the linear-array CCD (charge-coupled device) and area CCD have developed toward large area CCD, which has a broad coverage and avoids the difficulty in jointing small area CCDs in addition to improving time resolution. However, due to the high amount of pixels and channels of large area CCD, photo-response non-uniformity (PRNU) is severe. In this paper, a real time non-uniformity correction system is introduced for a sort of large area full frame transfer CCD. First, the correction algorithm is elaborated according to CCD's working principle. Secondly, due to the high number of pixels and correction coefficient, ordinary chip memory cannot meet the requirement. The combination of external flash memory and DDR described in the paper satisfies large capacity memory and rapid real time correction. The methods and measurement steps for obtaining correction factors are provided simultaneously. At the end, an imaging test is made. The non-uniformity of the image is reduced to 0.38 % from the pre-correction 2.96 %, achieving an obvious reduction of non-uniformity. The result shows that the real time non-uniformity correction system can meet the demands of large area-array CCD.

  3. Hardware friendly adaptive support-weight approach for stereo matching

    NASA Astrophysics Data System (ADS)

    Hou, Zuoxun; Han, Pei; Zhang, Hongwei; An, Ran

    2016-10-01

    In this paper, the hardware friendly adaptive support-weight approach is proposed to simplify the weight calculation process of the standard approach, which employs the support region to simplify the calculation of the similarity and uses the fixed distance dependent weight to present the proximity. In addition, the complete stereo matching algorithm and the hardware structure for FPGA implementation compatible with the approach is proposed. The experimental results show that the algorithm produces the disparity map accurately in different illumination conditions and different scenes, and its processing average bad pixel rate is only 6.65% for the standard test images of the Middlebury database, which is approximate to the performance of the standard adaptive support-weight approach. The proposed hardware structure provides a basis for design and implementation of real-time accurate stereo matching FPGA system.

  4. Development of Enhanced Avionics Flight Hardware Selection Process

    NASA Technical Reports Server (NTRS)

    Smith, K.; Watson, G. L.

    2003-01-01

    The primary objective of this research was to determine the processes and feasibility of using commercial off-the-shelf PC104 hardware for flight applications. This would lead to a faster, better, and cheaper approach to low-budget programs as opposed to the design, procurement. and fabrication of space flight hardware. This effort will provide experimental evaluation with results of flight environmental testing. Also, a method and/or suggestion used to bring test hardware up to flight standards will be given. Several microgravity programs, such as the Equiaxed Dendritic Solidification Experiment, Self-Diffusion in Liquid Elements, and various other programs, are interested in PC104 environmental testing to establish the limits of this technology.

  5. High-Speed Isolation Board for Flight Hardware Testing

    NASA Technical Reports Server (NTRS)

    Yamamoto, Clifford K.; Goodpasture, Richard L.

    2011-01-01

    There is a need to provide a portable and cost-effective galvanic isolation between ground support equipment and flight hardware such that any unforeseen voltage differential between ground and power supplies is eliminated. An interface board was designed for use between the ground support equipment and the flight hardware that electrically isolates all input and output signals and faithfully reproduces them on each side of the interface. It utilizes highly integrated multi-channel isolating devices to minimize size and reduce assembly time. This single-board solution provides appropriate connector hardware and breakout of required flight signals to individual connectors as needed for various ground support equipment. The board utilizes multi-channel integrated circuits that contain transformer coupling, thereby allowing input and output signals to be isolated from one another while still providing high-fidelity reproduction of the signal up to 90 MHz. The board also takes in a single-voltage power supply input from the ground support equipment and in turn provides a transformer-derived isolated voltage supply to power the portion of the circuitry that is electrically connected to the flight hardware. Prior designs used expensive opto-isolated couplers that were required for each signal to isolate and were time-consuming to assemble. In addition, these earlier designs were bulky and required a 2U rack-mount enclosure. The new design is smaller than a piece of 8.5 11-in. (.22 28-mm) paper and can be easily hand-carried where needed. The flight hardware in question is based on a lineage of existing software-defined radios (SDRs) that utilize a common interface connector with many similar input-output signals present. There are currently four to five variations of this SDR, and more upcoming versions are planned based on the more recent design.

  6. The Application of Acoustic Measurements and Audio Recordings for Diagnosis of In-Flight Hardware Anomalies

    NASA Technical Reports Server (NTRS)

    Welsh, David; Denham, Samuel; Allen, Christopher

    2011-01-01

    In many cases, an initial symptom of hardware malfunction is unusual or unexpected acoustic noise. Many industries such as automotive, heating and air conditioning, and petro-chemical processing use noise and vibration data along with rotating machinery analysis techniques to identify noise sources and correct hardware defects. The NASA/Johnson Space Center Acoustics Office monitors the acoustic environment of the International Space Station (ISS) through periodic sound level measurement surveys. Trending of the sound level measurement survey results can identify in-flight hardware anomalies. The crew of the ISS also serves as a "detection tool" in identifying unusual hardware noises; in these cases the spectral analysis of audio recordings made on orbit can be used to identify hardware defects that are related to rotating components such as fans, pumps, and compressors. In this paper, three examples of the use of sound level measurements and audio recordings for the diagnosis of in-flight hardware anomalies are discussed: identification of blocked inter-module ventilation (IMV) ducts, diagnosis of abnormal ISS Crew Quarters rack exhaust fan noise, and the identification and replacement of a defective flywheel assembly in the Treadmill with Vibration Isolation (TVIS) hardware. In each of these examples, crew time was saved by identifying the off nominal component or condition that existed and in directing in-flight maintenance activities to address and correct each of these problems.

  7. Electronic hardware implementations of neutral networks

    NASA Technical Reports Server (NTRS)

    Thakoor, A. P.; Moopenn, A.; Lambe, John; Khanna, S. K.

    1987-01-01

    This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

  8. Hardware Implementation of Singular Value Decomposition

    NASA Astrophysics Data System (ADS)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  9. Environmental testing for new SOFIA flight hardware

    NASA Astrophysics Data System (ADS)

    Lachenmann, Michael; Wolf, Jürgen; Strecker, Rainer; Weckenmann, Benedikt; Trimpe, Fritz; Hall, Helen J.

    2014-07-01

    New flight hardware for the Stratospheric Observatory for Infrared Astronomy (SOFIA) has to be tested to prove its safety and functionality and to measure its performance under flight conditions. Although it is not expected to experience critical issues inside the pressurized cabin with close-to-normal conditions, all equipment has to be tested for safety margins in case of a decompression event and/or for unusual high temperatures, e.g. inside an electronic unit caused by a malfunction as well as unusual high ambient temperatures inside the cabin, when the aircraft is parked in a desert. For equipment mounted on the cavity side of the telescope, stratospheric conditions apply, i.e., temperatures from -40 °C to -60°C and an air pressure of about 0.1 bar. Besides safety aspects as not to endanger personnel or equipment, new hardware inside the cavity has to function and to perform to specifications under such conditions. To perform these tests, an environmental test laboratory was set up at the SOFIA Science Center at the NASA Ames Research Center, including a thermal vacuum chamber, temperature measurement equipment, and a control and data logging workstation. This paper gives an overview of the test and measurement equipment, shows results from the commissioning and characterization of the thermal vacuum chamber, and presents examples of the component tests that were performed so far. To test the focus position stability of optics when cooling them to stratospheric temperatures, an auto-collimation device has been developed. We will present its design and results from measurements on commercial off-the-shelf optics as candidates for the new Wide Field Imager for SOFIA as an example.

  10. Evaluating Varied Label Designs for Use with Medical Devices: Optimized Labels Outperform Existing Labels in the Correct Selection of Devices and Time to Select

    PubMed Central

    Seo, Do Chan; Ladoni, Moslem; Brunk, Eric; Becker, Mark W.

    2016-01-01

    Purpose Effective standardization of medical device labels requires objective study of varied designs. Insufficient empirical evidence exists regarding how practitioners utilize and view labeling. Objective Measure the effect of graphic elements (boxing information, grouping information, symbol use and color-coding) to optimize a label for comparison with those typical of commercial medical devices. Design Participants viewed 54 trials on a computer screen. Trials were comprised of two labels that were identical with regard to graphics, but differed in one aspect of information (e.g., one had latex, the other did not). Participants were instructed to select the label along a given criteria (e.g., latex containing) as quickly as possible. Dependent variables were binary (correct selection) and continuous (time to correct selection). Participants Eighty-nine healthcare professionals were recruited at Association of Surgical Technologists (AST) conferences, and using a targeted e-mail of AST members. Results Symbol presence, color coding and grouping critical pieces of information all significantly improved selection rates and sped time to correct selection (α = 0.05). Conversely, when critical information was graphically boxed, probability of correct selection and time to selection were impaired (α = 0.05). Subsequently, responses from trials containing optimal treatments (color coded, critical information grouped with symbols) were compared to two labels created based on a review of those commercially available. Optimal labels yielded a significant positive benefit regarding the probability of correct choice ((P<0.0001) LSM; UCL, LCL: 97.3%; 98.4%, 95.5%)), as compared to the two labels we created based on commercial designs (92.0%; 94.7%, 87.9% and 89.8%; 93.0%, 85.3%) and time to selection. Conclusions Our study provides data regarding design factors, namely: color coding, symbol use and grouping of critical information that can be used to significantly enhance

  11. Life Sciences Division Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Yost, B.

    1999-01-01

    The Ames Research Center (ARC) is responsible for the development, integration, and operation of non-human life sciences payloads in support of NASA's Gravitational Biology and Ecology (GB&E) program. To help stimulate discussion and interest in the development and application of novel technologies for incorporation within non-human life sciences experiment systems, three hardware system models will be displayed with associated graphics/text explanations. First, an Animal Enclosure Model (AEM) will be shown to communicate the nature and types of constraints physiological researchers must deal with during manned space flight experiments using rodent specimens. Second, a model of the Modular Cultivation System (MCS) under development by ESA will be presented to highlight technologies that may benefit cell-based research, including advanced imaging technologies. Finally, subsystems of the Cell Culture Unit (CCU) in development by ARC will also be shown. A discussion will be provided on candidate technology requirements in the areas of specimen environmental control, biotelemetry, telescience and telerobotics, and in situ analytical techniques and imaging. In addition, an overview of the Center for Gravitational Biology Research facilities will be provided.

  12. Analyzing the scaling of connectivity in neuromorphic hardware and in models of neural networks.

    PubMed

    Partzsch, Johannes; Schüffny, René

    2011-06-01

    In recent years, neuromorphic hardware systems have significantly grown in size. With more and more neurons and synapses integrated in such systems, the neural connectivity and its configurability have become crucial design constraints. To tackle this problem, we introduce a generic extended graph description of connection topologies that allows a systematical analysis of connectivity in both neuromorphic hardware and neural network models. The unifying nature of our approach enables a close exchange between hardware and models. For an existing hardware system, the optimally matched network model can be extracted. Inversely, a hardware architecture may be fitted to a particular model network topology with our description method. As a further strength, the extended graph can be used to quantify the amount of configurability for a certain network topology. This is a hardware design variable that has widely been neglected, mainly because of a missing analysis method. To condense our analysis results, we develop a classification for the scaling complexity of network models and neuromorphic hardware, based on the total number of connections and the configurability. We find a gap between several models and existing hardware, making these hardware systems either impossible or inefficient to use for scaled-up network models. In this respect, our analysis results suggest models with locality in their connections as promising approach for tackling this scaling gap.

  13. Round Girls in Square Computers: Feminist Perspectives on the Aesthetics of Computer Hardware.

    ERIC Educational Resources Information Center

    Carr-Chellman, Alison A.; Marra, Rose M.; Roberts, Shari L.

    2002-01-01

    Considers issues related to computer hardware, aesthetics, and gender. Explores how gender has influenced the design of computer hardware and how these gender-driven aesthetics may have worked to maintain, extend, or alter gender distinctions, roles, and stereotypes; discusses masculine media representations; and presents an alternative model.…

  14. An Analysis of Hardware Requirements for Airborne Tactical Mesh Networking Nodes

    DTIC Science & Technology

    2005-03-01

    Global PAGES Information Grid, MANET, Wireless, OLSR, Sensor Networks, Tactical 53 Network Topology, Single Board Computer , PC/104, Tern UAV 16. PRICE...21 A . HARDWARE .......................................... 21 1. Single Board Computer ........................ 21 2. Compact Flash...logical choice was to base an improved design on the PC/104 standard for embedded PC architecture. A. HARDWARE 1. Single Board Computer Embedded

  15. Rapid space hardware development through computer-automated testing

    SciTech Connect

    Masters, D.S.; Ruud, K.K.

    1997-10-01

    FORTE, the Fast On-Orbit Recording of Transient Events small satellite designed and built by Los Alamos and Sandia National Laboratories, is scheduled for launch in August, 1997. In the spirit of {open_quotes}better, cheaper, faster{close_quotes} satellites, the RF experiment hardware (receiver and trigger sub-systems) necessitated rapid prototype testing and characterization in the development of space-flight components. This was accomplished with the assembly of engineering model hardware prior to construction of flight hardware and the design of component-specific, PC-based software control libraries. Using the LabVIEW{reg_sign} graphical programming language, together with off-the-shelf PC digital I/O and GPIB interface cards, hardware control and complete automation of test equipment was possible from one PC. Because the receiver and trigger sub-systems employed complex functions for signal discrimination and transient detection, thorough validation of all functions and illumination of any faults were priorities. These methods were successful in accelerating the development and characterization of space-flight components prior to integration and allowed more complete data to be gathered than could have been accomplished without automation. Additionally, automated control of input signal sources was carried over from bench-level to system-level with the use of networked Linux workstation utilizing a GPIB interface.

  16. Bias correction of risk estimates in vaccine safety studies with rare adverse events using a self-controlled case series design.

    PubMed

    Zeng, Chan; Newcomer, Sophia R; Glanz, Jason M; Shoup, Jo Ann; Daley, Matthew F; Hambidge, Simon J; Xu, Stanley

    2013-12-15

    The self-controlled case series (SCCS) method is often used to examine the temporal association between vaccination and adverse events using only data from patients who experienced such events. Conditional Poisson regression models are used to estimate incidence rate ratios, and these models perform well with large or medium-sized case samples. However, in some vaccine safety studies, the adverse events studied are rare and the maximum likelihood estimates may be biased. Several bias correction methods have been examined in case-control studies using conditional logistic regression, but none of these methods have been evaluated in studies using the SCCS design. In this study, we used simulations to evaluate 2 bias correction approaches-the Firth penalized maximum likelihood method and Cordeiro and McCullagh's bias reduction after maximum likelihood estimation-with small sample sizes in studies using the SCCS design. The simulations showed that the bias under the SCCS design with a small number of cases can be large and is also sensitive to a short risk period. The Firth correction method provides finite and less biased estimates than the maximum likelihood method and Cordeiro and McCullagh's method. However, limitations still exist when the risk period in the SCCS design is short relative to the entire observation period.

  17. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib....

  18. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib....

  19. Tinker's Toys: Lessons from Bank Street: Hardware.

    ERIC Educational Resources Information Center

    Tinker, Robert

    1985-01-01

    Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

  20. Returned Solar Max hardware degradation study results

    NASA Technical Reports Server (NTRS)

    Triolo, Jack J.; Ousley, Gilbert W.

    1989-01-01

    The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized.

  1. Hardware survey for the avionics test bed

    NASA Technical Reports Server (NTRS)

    Cobb, J. M.

    1981-01-01

    A survey of maor hardware items that could possibly be used in the development of an avionics test bed for space shuttle attached or autonomous large space structures was conducted in NASA Johnson Space Center building 16. The results of the survey are organized to show the hardware by laboratory usage. Computer systems in each laboratory are described in some detail.

  2. An evaluation of Skylab habitability hardware

    NASA Technical Reports Server (NTRS)

    Stokes, J.

    1974-01-01

    For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

  3. TH-C-BRB-01: Open Source Hardware: General Overview.

    PubMed

    Therriault-Proulx, F

    2016-06-01

    By definition, Open Source Hardware (OSH) is "hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design". The advantages of OSH are multiple and the movement has been growing exponentially over the last couple years, leading to the spread and evolution of 3D printing technologies, the creation of affordable and easy to use micro-controller boards (Arduino, Raspberry Pi, etc.), as well as a plurality of other "hands-on"/DIY projects. As we have seen over the past few years with 3D printing, where the number of projects benefiting clinical practice as grown significantly, the highly educated and technology savvy Medical Physics community is positioned to take advantage of and benefit from paradigm-shifting movements. Sharing of knowledge, know-how, and technology can be a key factor in furthering the impact medical physicists can have. Whether it is to develop phantoms, applicators, detector holders or devices based on the use of motors and sensors, sharing design files significantly enables further development. Because these designs would be massively peer-reviewed through their online publication, improvements would be made, and the creators of the design would be rewarded with an increase number of citation of their work. A curated database of software and hardware projects can be an invaluable to the field, but a critical mass of contributors is likely needed to guarantee the most impact. This symposium will discuss the benefits and hurdles for such an endeavor.

  4. The Effect of Written Corrective Feedback on Grammatical Accuracy of EFL Students: An Improvement over Previous Unfocused Designs

    ERIC Educational Resources Information Center

    Khanlarzadeh, Mobin; Nemati, Majid

    2016-01-01

    The effectiveness of written corrective feedback (WCF) in the improvement of language learners' grammatical accuracy has been a topic of interest in SLA studies for the past couple of decades. The present study reports the findings of a three-month study investigating the effect of direct unfocused WCF on the grammatical accuracy of elementary…

  5. FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

    NASA Astrophysics Data System (ADS)

    Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

    Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

  6. Evolvable Hardware for Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason; Globus, Al; Hornby, Gregory; Larchev, Gregory; Kraus, William

    2004-01-01

    This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

  7. Benchmarking hypercube hardware and software

    NASA Technical Reports Server (NTRS)

    Grunwald, Dirk C.; Reed, Daniel A.

    1986-01-01

    It was long a truism in computer systems design that balanced systems achieve the best performance. Message passing parallel processors are no different. To quantify the balance of a hypercube design, an experimental methodology was developed and the associated suite of benchmarks was applied to several existing hypercubes. The benchmark suite includes tests of both processor speed in the absence of internode communication and message transmission speed as a function of communication patterns.

  8. Use of Heritage Hardware on MPCV Exploration Flight Test One

    NASA Technical Reports Server (NTRS)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  9. Measuring Auroral and Arctic Ozone Using Student Made Hardware

    NASA Astrophysics Data System (ADS)

    Pina, M.

    2015-12-01

    This project is twofold to test the feasibility of student made hardware and teach students more about atmospheric instrumentation by providing students with education and materials, instructing them in design and building of hardware, and testing the hardware against commercial models in terms of weight, cost, and features. The Gaseous Compounds team of the University of Houston Undergraduate Student Instrument Project (USIP) selected the parts and the students of the team are assembling the payload. The payload will launch on a latex balloon in Houston and Fairbanks, Alaska. The instrument will gather data on the concentration of certain gases in the atmosphere as well as a meteorological profile of the atmosphere. The students plan to have the instrument collect and transmit data on carbon monoxide, nitric oxide, nitrogen dioxide, and ozone, as well as temperature, humidity, and barometric pressure. The data will also be stored on an SD card as a backup in case transmission fails. These payloads will fly at night and day to get an accurate vertical profile of the atmosphere and these results will be tested against the results of commercial hardware with the same capabilities.

  10. 77 FR 33388 - Designation for the Topeka, KS; Cedar Rapids, IA; Minot, ND; and Cincinnati, OH Areas; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ...; ] DEPARTMENT OF AGRICULTURE Designation for the Topeka, KS; Cedar Rapids, IA; Minot, ND; and Cincinnati, OH... Designation for the Topeka, KS; Cedar Rapids, IA; Minot, ND; and Cincinnati, OH Areas. The document...

  11. Hardware Testing for the Optical PAyload for Lasercomm Science (OPALS)

    NASA Technical Reports Server (NTRS)

    Slagle, Amanda

    2011-01-01

    Hardware for several subsystems of the proposed Optical PAyload for Lasercomm Science (OPALS), including the gimbal and avionics, was tested. Microswitches installed on the gimbal were evaluated to verify that their point of actuation would remain within the acceptable range even if the switches themselves move slightly during launch. An inspection of the power board was conducted to ensure that all power and ground signals were isolated, that polarized components were correctly oriented, and that all components were intact and securely soldered. Initial testing on the power board revealed several minor problems, but once they were fixed the power board was shown to function correctly. All tests and inspections were documented for future use in verifying launch requirements.

  12. Nimble Compiler Environment for Agile Hardware. Volume 1

    DTIC Science & Technology

    2001-10-01

    programs to be compiled directly into custom silicon or reconfigurable architectures. Some other novel hardware synthesis systems compile Java 24, Matlab ...appreciable acceleration in some compute intensive applications. Such systems have been very difficult to program though and thus have not been explo ited...for their benefits. The problem is the lack of an appropriate design environment for system engineers like those typically found in digital signal

  13. Optical Properties of Nanosatellite Hardware

    NASA Technical Reports Server (NTRS)

    Finckenor, M. M.; Coker, R. F.

    2014-01-01

    Over the last decade, a number of very small satellites have been launched into space. These have been called nanosatellites (generally of a weight between 1 and 10 kg) or picosatellites (weight <1 kg). This also includes CubeSats, which are based on 10-cm cube units. With the addition of the Japanese Experiment Module (JEM) Small Satellite Orbital Deployer (J-SSOD) to the International Space Station (ISS), CubeSats are easily cycled through the JEM airlock and deployed into space (fig. 1). The number of CubeSats launched since 2003 was approaching 100 at the time of publication, and the authors expect this trend in research to continue, particularly for high school and college flight experiments. Because these spacecraft are so small, there is usually no allowance for shielding or active heating or cooling of the avionics and other hardware. Parts that are usually ignored in the thermal analysis of larger spacecraft may contribute significantly to the heat load of a tiny satellite. In addition, many small satellites have commercial-off-the-shelf (COTS) components. To reduce costs, many providers of COTS components do not include the optical and physical parameters necessary for accurate thermal analysis. Marshall Space Flight Center participated in the development and analysis of the Space Missile Defense Command-Operational Nanosatellite Effect (SMDC-ONE) and the Edison Demonstration of Smallsat Networks (EDSN) nanosatellites. These optical property measurements are documented here in hopes that they may benefit future nanosatellite and picosatellite programs and aid thermal analysis to ensure project goals are met, with the understanding that material properties may vary by vendor, batch, manufacturing process, and preflight handling. Where possible, complementary data are provided from ground simulations of the space environment and flight experiments, such as the Materials on International Space Station Experiment (MISSE) series. NASA gives no recommendation

  14. SUMC-DV hardware manual

    NASA Technical Reports Server (NTRS)

    Feller, A.

    1972-01-01

    The assembly, the physical and electrical characteristics, and the basic electrical tests of the Space Ultrareliable Modular Computer Demonstration Vehicle (SUMC-DV), are described. The descriptions include: (1) the packaging concepts, physical assembly, design and fabrication using design automation techniques of 10 different types of custom CMOS LSI arrays; (2) the fabrication and testing of the various components including the LSI arrays; (3) the hierarchy of the memory complement and the clock generation and distribution system; (4) system testing techniques; and (5) the procedure employed in the electrical checkout of the system.

  15. FPGA based implementation of hardware diagnostic layer for local trigger of BAC calorimeter for ZEUS detector

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.

    2004-07-01

    The paper describes design and construction of hardware diagnostics layer dedicated to the local trigger of the Backing Calorimeter (BAC). The BAC is a part of the ZEUS experiment in DESY, Hamburg. A general characteristic of the hardware of BAC trigger was presented. The design of hardware diagnostic and calibration sub-systems for BAC trigger bases on the continuous monitoring of consecutive electronic and photonic blocks. The monitoring process is performed via the specialized tests. The standardized diagnostic components were realized in the algorithmic and parameterized description in AHDL. There were presented the implementation results in ALTERA ACEX chips.

  16. Rapid Production of Composite Prototype Hardware

    NASA Technical Reports Server (NTRS)

    DeLay, T. K.

    2000-01-01

    The objective of this research was to provide a mechanism to cost-effectively produce composite hardware prototypes. The task was to take a hands-on approach to developing new technologies that could benefit multiple future programs.

  17. Hardware device binding and mutual authentication

    DOEpatents

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  18. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  19. IDD Archival Hardware Architecture and Workflow

    SciTech Connect

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  20. Optical design of a novel instrument that uses the Hartmann-Shack sensor and Zernike polynomials to measure and simulate customized refraction correction surgery outcomes and patient satisfaction

    NASA Astrophysics Data System (ADS)

    Yasuoka, Fatima M. M.; Matos, Luciana; Cremasco, Antonio; Numajiri, Mirian; Marcato, Rafael; Oliveira, Otavio G.; Sabino, Luis G.; Castro N., Jarbas C.; Bagnato, Vanderlei S.; Carvalho, Luis A. V.

    2016-03-01

    An optical system that conjugates the patient's pupil to the plane of a Hartmann-Shack (HS) wavefront sensor has been simulated using optical design software. And an optical bench prototype is mounted using mechanical eye device, beam splitter, illumination system, lenses, mirrors, mirrored prism, movable mirror, wavefront sensor and camera CCD. The mechanical eye device is used to simulate aberrations of the eye. From this device the rays are emitted and travelled by the beam splitter to the optical system. Some rays fall on the camera CCD and others pass in the optical system and finally reach the sensor. The eye models based on typical in vivo eye aberrations is constructed using the optical design software Zemax. The computer-aided outcomes of each HS images for each case are acquired, and these images are processed using customized techniques. The simulated and real images for low order aberrations are compared using centroid coordinates to assure that the optical system is constructed precisely in order to match the simulated system. Afterwards a simulated version of retinal images is constructed to show how these typical eyes would perceive an optotype positioned 20 ft away. Certain personalized corrections are allowed by eye doctors based on different Zernike polynomial values and the optical images are rendered to the new parameters. Optical images of how that eye would see with or without corrections of certain aberrations are generated in order to allow which aberrations can be corrected and in which degree. The patient can then "personalize" the correction to their own satisfaction. This new approach to wavefront sensing is a promising change in paradigm towards the betterment of the patient-physician relationship.

  1. Scaling Retro-Commissioning to Small Commercial Buildings: A Turnkey Automated Hardware-Software Solution

    SciTech Connect

    Lin, Guanjing; Granderson, J.; Brambley, Michael R.

    2015-07-01

    In the United States, small commercial buildings represent 51% of total floor space of all commercial buildings and consume nearly 3 quadrillion Btu (3.2 quintillion joule) of site energy annually, presenting an enormous opportunity for energy savings. Retro-commissioning (RCx), the process through which professional energy service providers identify and correct operational problems, has proven to be a cost-effective means to achieve median energy savings of 16%. However, retro-commissioning is not typically conducted at scale throughout the commercial stock. Very few small commercial buildings are retro-commissioned because utility expenses are relatively modest, margins are tighter, and capital for improvements is limited. In addition, small buildings do not have in-house staff with the expertise to identify improvement opportunities. In response, a turnkey hardware-software solution was developed to enable cost-effective, monitoring-based RCx of small commercial buildings. This highly tailored solution enables non-commissioning providers to identify energy and comfort problems, as well as associated cost impacts and remedies. It also facilitates scale by offering energy service providers the means to streamline their existing processes and reduce costs by more than half. The turnkey RCx sensor suitcase consists of two primary components: a suitcase of sensors for short-term building data collection that guides users through the process of deploying and retrieving their data and a software application that automates analysis of sensor data, identifies problems and generates recommendations. This paper presents the design and testing of prototype models, including descriptions of the hardware design, analysis algorithms, performance testing, and plans for dissemination.

  2. Considerations in Selecting Microcomputers for Instructional Design.

    ERIC Educational Resources Information Center

    Matthews, John I.

    1981-01-01

    Suggestions are made for choosing microcomputers for instructional design. Elements discussed include hardware (system components, selection procedures, operations and hardware); equipment suppliers; software development (database management, simulation); and implementation (acquisition of hardware, probable difficulties). (CT)

  3. Process Assured Corrective Action- Human-in-the-Loop Case Studies

    NASA Astrophysics Data System (ADS)

    Frechette, A.; Trujillo, M.; Evetts, S.; Sundblad, P.; Damann, V.; Fuglesang, C.; Herd, A.

    2010-09-01

    Operations on the International Space Station(ISS) are achieved through varying degrees of direct(on-orbit crew) and remote(ground-based operations teams) activity. Crew activities are undertaken following predefined and trained procedures. On ground, teams undertake rehearsed operational protocols and remote commanding based on the data received from on-orbit hardware(via tele-command and telemetry displays). One particular aspect of ISS operations, where the crew member forms a direct part of the system operations and the source of data collection, requires them to be the subjects of experimentation for data collection. These experiments(payloads) require additional considerations for Human-in-the-Loop(HITL) testing. It is regular practice that in parallel with on-orbit hardware operations, ground-based hardware is operating(in advance of, in time equivalence to or lagging behind) providing predictive data, replicating on-orbit operations, or allowing for corrections relative to actual on-orbit operations(respectively). For experimental physiology hardware and countermeasure device this presents specific challenges, as the normal ground-based parallel operations are not always an exact, "flight like", replica of the flight hardware. Furthermore, ground-based HITL operations must occur prior to flight with representative subjects as the actual crew member is often fully engaged with mission preparation training activities. In the context of corrective action, opportunities have been found to exist for process improvements in the application of Human Factors(HF) engineering standards and HITL simulations, in support of the design development for safety and mission assurance. The specific case studies highlighted, whilst limited in number, have provided detailed proposals to implement procedures for HITL simulation and usability testing during physiology hardware and countermeasure device development. The inclusion of HITL and usability testing in representative

  4. Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

    PubMed

    Minho Won; Albalawi, Hassan; Xin Li; Thomas, Donald E

    2014-01-01

    This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.

  5. Use of CCSDS Packets Over SpaceWire to Control Hardware

    NASA Technical Reports Server (NTRS)

    Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

    2012-01-01

    For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

  6. Hardware demonstration of high-speed networks for satellite applications.

    SciTech Connect

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  7. VEG-01: Veggie Hardware Verification Testing

    NASA Technical Reports Server (NTRS)

    Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

    2013-01-01

    The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

  8. Summary of multi-core hardware and programming model investigations

    SciTech Connect

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  9. Outline of a fast hardware implementation of Winograd's DFT algorithm

    NASA Technical Reports Server (NTRS)

    Zohar, S.

    1980-01-01

    The main characteristics of the discrete Fourier transform (DFT) algorithm considered by Winograd (1976) is a significant reduction in the number of multiplications. Its primary disadvantage is a higher structural complexity. It is, therefore, difficult to translate the reduced number of multiplications into faster execution of the DFT by means of a software implementation of the algorithm. For this reason, a hardware implementation is considered in the current study, taking into account a design based on the algorithm prescription discussed by Zohar (1979). The hardware implementation of a FORTRAN subroutine is proposed, giving attention to a pipelining scheme in which 5 consecutive data batches are being operated on simultaneously, each batch undergoing one of 5 processing phases.

  10. Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

    NASA Astrophysics Data System (ADS)

    Hasan, M. A.; Reaz, M. B. I.

    2012-01-01

    The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

  11. Environmental Conditions for Space Flight Hardware: A Survey

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette; Lee, Brandon

    2005-01-01

    Interest in generalization of the physical environment experienced by NASA hardware from the natural Earth environment (on the launch pad), man-made environment on Earth (storage acceptance an d qualification testing), the launch environment, and the space environment, is ed to find commonality among our hardware in an effort to reduce cost and complexity. NASA is entering a period of increase in its number of planetary missions and it is important to understand how our qualification requirements will evolve with and track these new environments. Environmental conditions are described for NASA projects in several ways for the different periods of the mission life cycle. At the beginning, the mission manager defines survivability requirements based on the mission length, orbit, launch date, launch vehicle, and other factors . such as the use of reactor engines. Margins are then applied to these values (temperature extremes, vibration extremes, radiation tolerances, etc,) and a new set of conditions is generalized for design requirements. Mission assurance documents will then assign an additional margin for reliability, and a third set of values is provided for during testing. A fourth set of environmental condition values may evolve intermittently from heritage hardware that has been tested to a level beyond the actual mission requirement. These various sets of environment figures can make it quite confusing and difficult to capture common hardware environmental requirements. Environmental requirement information can be found in a wide variety of places. The most obvious is with the individual projects. We can easily get answers to questions about temperature extremes being used and radiation tolerance goals, but it is more difficult to map the answers to the process that created these requirements: for design, for qualification, and for actual environment with no margin applied. Not everyone assigned to a NASA project may have that kind of insight, as many have

  12. Overlapped checkpointing with hardware assist

    SciTech Connect

    Mitchell, Christopher J; Nunez, James A; Wang, Jun

    2009-01-01

    We present a new approach to handling the demanding I/O workload incurred during checkpoint writes encountered in High Performance Computing. Prior efforts to improve performance have been primarily bound by mechanical limitations of the hard drive. Our research surpasses this limitation by providing a method to: (1) write checkpoint data to a high-speed, non-volatile buffer, and (2) asynchronously write this data to permanent storage while resuming computation. This removes the hard drive from the critical data path because our I/O node based buffers isolate the compute nodes from the storage servers. This solution is feasible because of industry declines in cost for high-capacity, non-volatile storage technologies. Testing was conducted on a small-scale cluster to prove the design, and then scaled at Los Alamos National Laboratory. Results show a definitive speedup factor for select workloads over writing directly to a typical global parallel file system; the Panasas ActiveScale File System.

  13. Proposed Space Flight Experiment Hardware

    NASA Technical Reports Server (NTRS)

    2003-01-01

    The primary thrust for this plan is to develop design tools and fundamental understanding that are timely and consistent with the goal of the various exploration initiatives. The plan will utilize ISS facilities, such as the Fluids Integrated Rack (FIR) and the Microgravity Science Glovebox (MSG). A preliminary flow schematic of Two-Phase Flow Facility (T(phi)FFy) which would utilize FIR is shown in Figure 3. MSG can be utilized to use the Boiling eXperiment Facility (BXF) and Contact Line Dynamics Experiment (CLiDE) Facility. The T(phi)FFy system would have multiple test sections whereby different configurations of heat exchangers could be used to study boiling and condensation phenomena. The test sections would be instrumented for pressure drop, void fraction, heat fluxes, temperatures, high-speed imaging and other diagnostics. Besides a high-speed data acquisition system with a large data storage capability, telemetry could be used to update control and test parameters and download limited amounts of data. In addition, there would be multiple accumulators that could be used to investigate system stability and fluid management issues. The system could accommodate adiabatic tests through either the space station nitrogen supply or have an experiment-specific compressor to pressurize a sufficient amount of air or other non-condensable gas for reuse as the supply bottle is depleted.

  14. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    NASA Astrophysics Data System (ADS)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  15. Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

    NASA Astrophysics Data System (ADS)

    Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

    2016-11-01

    The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

  16. Mental Health in Corrections: An Overview for Correctional Staff.

    ERIC Educational Resources Information Center

    Sowers, Wesley; Thompson, Kenneth; Mullins, Stephen

    This volume is designed to provide corrections practitioners with basic staff training on the needs of those with mental illness and impairments in our correctional systems. Chapter titles are: (1) "Mental Illness in the Correctional Setting"; (2) "Substance Use Disorders"; (3) "Problems with Mood"; (4) "Problems…

  17. Preparing the hardware of the CMS Electromagnetic Calorimeter control and safety systems for LHC Run 2

    NASA Astrophysics Data System (ADS)

    Holme, O.; Adzic, P.; Di Calafiori, D.; Cirkovic, P.; Dissertori, G.; Djambazov, L.; Jovanovic, D.; Lustermann, W.; Zelepoukine, S.

    2016-01-01

    The Detector Control System of the CMS Electromagnetic Calorimeter has undergone significant improvements during the first LHC Long Shutdown. Based on the experience acquired during the first period of physics data taking of the LHC, several hardware projects were carried out to improve data accuracy, to minimise the impact of failures and to extend remote control possibilities in order to accelerate recovery from problematic situations. This paper outlines the hardware of the detector control and safety systems and explains in detail the requirements, design and commissioning of the new hardware projects.

  18. Management of a CFD organization in support of space hardware development

    NASA Technical Reports Server (NTRS)

    Schutzenhofer, L. A.; Mcconnaughey, P. K.; Mcconnaughey, H. V.; Wang, T. S.

    1991-01-01

    The management strategy of NASA-Marshall's CFD branch in support of space hardware development and code validation implements various elements of total quality management. The strategy encompasses (1) a teaming strategy which focuses on the most pertinent problem, (2) quick-turnaround analysis, (3) the evaluation of retrofittable design options through sensitivity analysis, and (4) coordination between the chief engineer and the hardware contractors. Advanced-technology concepts are being addressed via the definition of technology-development projects whose products are transferable to hardware programs and the integration of research activities with industry, government agencies, and universities, on the basis of the 'consortium' concept.

  19. Multimode guidance project low frequency ECM simulator: Hardware description

    NASA Astrophysics Data System (ADS)

    Kaye, H. M.

    1982-10-01

    The Multimode Guidance(MMG) Project, part of the Army/Navy Area Defense SAM Technology Prototyping Program, was established to conduct a feasibility demonstration of multimode guidance concepts. Prototype guidance units for advanced, long range missiles are being built and tested under MMG Project sponsorship. The Johns Hopkins University Applied Physics Laboratory has been designated as Government Agent for countermeasures for this project. In support of this effort, a family of computer-controlled ECM simulators is being developed for validation of contractor's multimode guidance prototype designs. The design of the Low Frequency ECM Simulator is documented in two volumes. This report, Volume A, describes the hardware design of the simulator; Volume B describes the software design. This computer-controlled simulator can simulate up to six surveillance frequency jammers in B through F bands and will be used to evaluate the performance of home-on-jamming guidance modes in multiple jammer environments.

  20. Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

    PubMed

    Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

    2012-06-01

    Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

  1. 77 FR 42500 - Designation of a Class of Employees for Addition to the Special Exposure Cohort; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-19

    ... give notice of a decision to designate a class of employees from the Feed Materials Production Center (FMPC) in Fernald, Ohio, also known as the Fernald Environmental Management Project (FEMP), as an... worked at the Feed Materials Production Center (FMPC) in Fernald, Ohio, from January 1, 1968...

  2. Onboard utilization of ground control points for image correction. Volume 3: Ground control point simulation software design

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software developed to simulate the ground control point navigation system is described. The Ground Control Point Simulation Program (GCPSIM) is designed as an analysis tool to predict the performance of the navigation system. The system consists of two star trackers, a global positioning system receiver, a gyro package, and a landmark tracker.

  3. Corrective work.

    ERIC Educational Resources Information Center

    Hill, Leslie A.

    1978-01-01

    Discusses some general principles for planning corrective instruction and exercises in English as a second language, and follows with examples from the areas of phonemics, phonology, lexicon, idioms, morphology, and syntax. (IFS/WGA)

  4. Language of CTO interventions - Focus on hardware.

    PubMed

    Mishra, Sundeep

    2016-01-01

    The knowledge of variety of chronic total occlusion (CTO) hardware and the ability to use them represents the key to success of any CTO interventions. However, the multiplicity of CTO hardware and their physical character and the terminology used by experts create confusion in the mind of an average interventional cardiologist, particularly a beginner in this field. This knowledge is available but is scattered. We aim to classify and compare the currently used devices based on their properties focusing on how physical character of each device can be utilized in a specific situation, thus clarifying and simplifying the technical discourse.

  5. Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

    NASA Technical Reports Server (NTRS)

    1990-01-01

    This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

  6. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  7. Weight and the Future of Space Flight Hardware Cost Modeling

    NASA Technical Reports Server (NTRS)

    Prince, Frank A.

    2003-01-01

    Weight has been used as the primary input variable for cost estimating almost as long as there have been parametric cost models. While there are good reasons for using weight, serious limitations exist. These limitations have been addressed by multi-variable equations and trend analysis in models such as NAFCOM, PRICE, and SEER; however, these models have not be able to address the significant time lags that can occur between the development of similar space flight hardware systems. These time lags make the cost analyst's job difficult because insufficient data exists to perform trend analysis, and the current set of parametric models are not well suited to accommodating process improvements in space flight hardware design, development, build and test. As a result, people of good faith can have serious disagreement over the cost for new systems. To address these shortcomings, new cost modeling approaches are needed. The most promising approach is process based (sometimes called activity) costing. Developing process based models will require a detailed understanding of the functions required to produce space flight hardware combined with innovative approaches to estimating the necessary resources. Particularly challenging will be the lack of data at the process level. One method for developing a model is to combine notional algorithms with a discrete event simulation and model changes to the total cost as perturbations to the program are introduced. Despite these challenges, the potential benefits are such that efforts should be focused on developing process based cost models.

  8. Efficient Execution of Recursive Programs on Commodity Vector Hardware

    SciTech Connect

    Ren, Bin; Jo, Youngjoon; Krishnamoorthy, Sriram; Agrawal, Kunal; Kulkarni, Milind

    2015-06-13

    The pursuit of computational efficiency has led to the proliferation of throughput-oriented hardware, from GPUs to increasingly-wide vector units on commodity processors and accelerators. This hardware is designed to efficiently execute data-parallel computations in a vectorized manner. However, many algorithms are more naturally expressed as divide-and-conquer, recursive, task-parallel computations; in the absence of data parallelism, it seems that such algorithms are not well-suited to throughput-oriented architectures. This paper presents a set of novel code transformations that expose the data-parallelism latent in recursive, task-parallel programs. These transformations facilitate straightforward vectorization of task-parallel programs on commodity hardware. We also present scheduling policies that maintain high utilization of vector resources while limiting space usage. Across several task-parallel benchmarks, we demonstrate both efficient vector resource utilization and substantial speedup on chips using Intel's SSE4.2 vector units as well as accelerators using Intel's AVX512 units.

  9. Advanced Technology Development: Solid-Liquid Interface Characterization Hardware

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Characterizing the solid-liquid interface during directional solidification is key to understanding and improving material properties. The goal of this Advanced Technology Development (ATD) has been to develop hardware, which will enable real-time characterization of practical materials, such as aluminum (Al) alloys, to unprecedented levels. Required measurements include furnace and sample temperature gradients, undercooling at the growing interface, interface shape, or morphology, and furnace translation and sample growth rates (related). These and other parameters are correlated with each other and time. A major challenge was to design and develop all of the necessary hardware to measure the characteristics, nearly simultaneously, in a smaller integral furnace compatible with existing X-ray Transmission Microscopes, XTMs. Most of the desired goals have been accomplished through three generations of Seebeck furnace brassboards, several varieties of film thermocouple arrays, heaters, thermal modeling of the furnaces, and data acquisition and control (DAC) software. Presentations and publications have resulted from these activities, and proposals to use this hardware for further materials studies have been submitted as sequels to this last year of the ATD.

  10. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

    PubMed

    Ly, Daniel Le; Chow, Paul

    2010-11-01

    Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

  11. Advances in metered dose inhaler technology: hardware development.

    PubMed

    Stein, Stephen W; Sheth, Poonam; Hodson, P David; Myrdal, Paul B

    2014-04-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering valve capable of delivering a consistent amount of drug with each dose delivered, an actuator mouthpiece that atomizes the formulation and serves as a conduit to deliver the aerosol to the patient, and often an indicating mechanism that provides information to the patient on the number of doses remaining. This review focuses on the current state-of-the-art of MDI hardware and includes discussion of enhancements made to the device's core subsystems. In addition, technologies that aid the correct use of MDIs will be discussed. These include spacers, valved holding chambers, and breath-actuated devices. Many of the improvements discussed in this article increase the ability of MDI systems to meet regulatory specifications. Innovations that enhance the functionality of MDIs continue to be balanced by the fact that a key advantage of MDI systems is their low cost per dose. The expansion of the health care market in developing countries and the increased focus on health care costs in many developed countries will ensure that MDIs remain a cost-effective crucial delivery system for treating pulmonary conditions for many years to come.

  12. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry

    NASA Astrophysics Data System (ADS)

    Wang, Xin; Yang, James N.; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-01

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm2. The results showed that the rod increased the dose to water by ˜6% at the water-rod interface because of electron backscattering and decreased the dose by ˜7% in the shadow of the rod because of photon attenuation. The Pinnacle3 treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm-3 was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm-3 (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm-3 to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  13. A beta-mixture quantile normalization method for correcting probe design bias in Illumina Infinium 450 k DNA methylation data

    PubMed Central

    Teschendorff, Andrew E.; Marabita, Francesco; Lechner, Matthias; Bartlett, Thomas; Tegner, Jesper; Gomez-Cabrero, David; Beck, Stephan

    2013-01-01

    Motivation: The Illumina Infinium 450 k DNA Methylation Beadchip is a prime candidate technology for Epigenome-Wide Association Studies (EWAS). However, a difficulty associated with these beadarrays is that probes come in two different designs, characterized by widely different DNA methylation distributions and dynamic range, which may bias downstream analyses. A key statistical issue is therefore how best to adjust for the two different probe designs. Results: Here we propose a novel model-based intra-array normalization strategy for 450 k data, called BMIQ (Beta MIxture Quantile dilation), to adjust the beta-values of type2 design probes into a statistical distribution characteristic of type1 probes. The strategy involves application of a three-state beta-mixture model to assign probes to methylation states, subsequent transformation of probabilities into quantiles and finally a methylation-dependent dilation transformation to preserve the monotonicity and continuity of the data. We validate our method on cell-line data, fresh frozen and paraffin-embedded tumour tissue samples and demonstrate that BMIQ compares favourably with two competing methods. Specifically, we show that BMIQ improves the robustness of the normalization procedure, reduces the technical variation and bias of type2 probe values and successfully eliminates the type1 enrichment bias caused by the lower dynamic range of type2 probes. BMIQ will be useful as a preprocessing step for any study using the Illumina Infinium 450 k platform. Availability: BMIQ is freely available from http://code.google.com/p/bmiq/. Contact: a.teschendorff@ucl.ac.uk Supplementary information: Supplementary data are available at Bioinformatics online PMID:23175756

  14. Simultaneous-Frequency Nonlinear Radar: Hardware Simulation

    DTIC Science & Technology

    2015-08-01

    Army Research Laboratory Simultaneous-Frequency Nonlinear Radar : Hardware Simulation by Gregory J Mazzaro, Kenneth I Ranney, Kyle A Gallagher...distribution unlimited. NOTICES Disclaimers The findings in this report are not to be construed as an official Department of the Army position

  15. Postflight hardware evaluation (RSRM-29, STS-54)

    NASA Astrophysics Data System (ADS)

    1993-09-01

    This document is the final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-29 flight set. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64221), represents a summary of the RSRM-29 hardware evaluation. Disassembly evaluation photograph numbers are logged in TWA-1990. The RSRM-29 flight set disassembly evaluations described in this document were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on September 9, 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  16. Hardware Acceleration of Sparse Cognitive Algorithms

    DTIC Science & Technology

    2016-05-01

    15. SUBJECT TERMS Cortical Algorithms; Machine Learning ; Hardware; VLSI; ASIC 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT: SAR...Approved for public release; distribution unlimited. Table of Contents Section Page List of Figures... integrated circuit (ASIC) in which certain parameters can be changed at compile time and/or run time. However, it can only run one version of the

  17. Hardware Implementation of Serially Concatenated PPM Decoder

    NASA Technical Reports Server (NTRS)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  18. Evolvable hardware: genetic search in a physical realm

    NASA Astrophysics Data System (ADS)

    Raichman, Nadav; Segev, Ronen; Ben-Jacob, Eshel

    2003-08-01

    The application of evolution-inspired strategies to hardware design and circuit self-configuration leads to the concept of evolvable hardware (EHW). EHW refers to self-configuration of electronic hardware by evolutionary/genetic algorithms (EA and GA, respectively). Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing for EHW. Here we applied an evolutionary algorithm on a configurable digital FPGA chip in order to evolve analog-behavior circuits. Though the configurable chip is explicitly built for digital designs, analog circuits were successfully evolved by allowing feedback routings and by disabling the general clock. The results were unconventional circuits that were well fitted both to the task for which the circuits were evolved, and to the environment in which the evolution took place. We analyzed the morphotype (configuration) changes in circuit size and circuit operation through evolutionary time. The results showed that the evolved circuit structure had two distinct areas: an active area in which signal processing took place and a surrounding neutral area. The active area of the evolved circuits was small in size, but complex in structure. Results showed that the active area may grow during evolution, indicating that progress is achieved through the addition of units taken from the neutral area. Monitor views of the circuit outputs through evolution indicate that several distinct stages occurred in which evolution evolved. This is in accordance with the plots of fitness that show a progressive climb in a stair-like manner. Competitive studies were also performed of evolutions with various population sizes. Results showed that the smaller the size of the evolved population, the faster was the evolutionary process. This was attributed to the high degeneracy in gene variance within the large population, resulting in a futile search.

  19. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  20. Design and Performance Characteristics of the ORNL Advanced Microscopy Laboratory and JEOL 2200FS-AC Aberration-Corrected STEM/TEM

    SciTech Connect

    Allard Jr, Lawrence Frederick; Blom, Douglas Allen; O'Keefe, Michael A.; Mishina, Satoshi

    2005-01-01

    To achieve the highest performance with today's generation of aberration-corrected electron microscopes, it is increasingly evident that the environment of the facility in which the microscope is installed must be considered an integral component of the microscopy program. Such instruments are the world's best detectors of the influence of parameters such as alternating magnetic fields, floor vibrations, acoustic vibrations, airflow, and temperature and pressure fluctuations. At ORNL, the new Advanced Microscopy Laboratory (AML) has recently been completed, with two aberration-corrected instruments installed, and two more planned in the near future to fill the 4-laboratory building. Design criteria for the facility include the following: magnetic fields below 0.1mG rms in all directions, floor vibrations below 1{mu}m/sec, air flow less than 5cm/sec horizontally, temperature stability {+-}0.2 C/hr, and provision for instrument operation from an adjacent control room to minimize the influence of the operator on instrument performance. The JEOL 2200FS-AC, being installed as of this writing, has demonstrated a TEM information limit of 0.9 {angstrom}. This is the limit expected given the measured instrument parameters (HT and OL power supply stabilities, beam energy spread, etc.), and illustrates that the environmental influences are not adversely affecting the instrument performance. However, in STEM high-angle annular dark-field (HA-ADF) mode, images of a thin Si crystal in <1 1 0> zone axis orientation, after primary aberrations in the illuminating beam were optimally corrected, showed a significant vibration effect.

  1. Parallel Processing with Digital Signal Processing Hardware and Software

    NASA Technical Reports Server (NTRS)

    Swenson, Cory V.

    1995-01-01

    The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

  2. Hardware-in-the-loop simulation and energy optimization of cardiac pacemakers.

    PubMed

    Barker, Chris; Kwiatkowska, Marta; Mereacre, Alexandru; Paoletti, Nicola; Patane, Andrea

    2015-01-01

    Implantable cardiac pacemakers are medical devices that can monitor and correct abnormal heart rhythms. To provide the necessary safety assurance for pacemaker software, both testing and verification of the code, as well as testing the entire pacemaker hardware in the loop, is necessary. In this paper, we present a hardware testbed that enables detailed hardware-in-the-loop simulation and energy optimisation of pacemaker algorithms with respect to a heart model. Both the heart and the pacemaker models are encoded in Simulink/Stateflow™ and translated into executable code, with the pacemaker executed directly on the microcontroller. We evaluate the usefulness of the testbed by developing a parameter synthesis algorithm which optimises the timing parameters based on power measurements acquired in real-time. The experiments performed on real measurements successfully demonstrate that the testbed is capable of energy minimisation in real-time and obtains safe pacemaker timing parameters.

  3. What is the 'correct' formulation of the linearised Navier-Stokes equations for designing feedback flow control systems?

    NASA Astrophysics Data System (ADS)

    Dellar, Oliver; Jones, Bryn; ACSE Collaboration

    2016-11-01

    The use of feedback control is looking increasingly attractive as a means of reducing the pressure drag which acts upon bluff body vehicles such as heavy goods vehicles, and thus reducing both fuel consumption and CO2 emissions. Motivated by the need to efficiently obtain low-order models of such flows in order to utilise model based control theory, we consider the effect on system dynamics of basing the plant model on different formulations of the linearised Navier-Stokes equations. The dynamics of a single computational node's subsystem which arises upon spatial discretisation of the governing equations in both primitive variables and pressure Poisson equation formulations are considered, revealing fundamental differences at the nodal level. The effects of these differences on system dynamics at the full fluid flow system level are exemplified by considering the corresponding formulations of a two-dimensional channel flow, subjected to a number different of boundary conditions. This ultimately reveals which formulations of the governing equations are suitable for feedback control design, and which should be avoided.

  4. Open source hardware and software platform for robotics and artificial intelligence applications

    NASA Astrophysics Data System (ADS)

    Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

    2016-02-01

    Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

  5. A configurable-hardware document-similarity classifier to detect web attacks.

    SciTech Connect

    Ulmer, Craig D.; Gokhale, Maya

    2010-04-01

    This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to reconfigurable hardware. The TFIDF classifier is used to detect web attacks in HTTP data. In our reconfigurable hardware approach, we design a streaming, real-time classifier by simplifying an existing sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. We have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires two orders of magnitude less memory than the original algorithm. At 166MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.

  6. Jitter Correction

    NASA Technical Reports Server (NTRS)

    Waegell, Mordecai J.; Palacios, David M.

    2011-01-01

    Jitter_Correct.m is a MATLAB function that automatically measures and corrects inter-frame jitter in an image sequence to a user-specified precision. In addition, the algorithm dynamically adjusts the image sample size to increase the accuracy of the measurement. The Jitter_Correct.m function takes an image sequence with unknown frame-to-frame jitter and computes the translations of each frame (column and row, in pixels) relative to a chosen reference frame with sub-pixel accuracy. The translations are measured using a Cross Correlation Fourier transformation method in which the relative phase of the two transformed images is fit to a plane. The measured translations are then used to correct the inter-frame jitter of the image sequence. The function also dynamically expands the image sample size over which the cross-correlation is measured to increase the accuracy of the measurement. This increases the robustness of the measurement to variable magnitudes of inter-frame jitter

  7. Hardware for a real-time multiprocessor simulator

    NASA Technical Reports Server (NTRS)

    Blech, R. A.; Arpasi, D. J.

    1984-01-01

    The hardware for a real time multiprocessor simulator (RTMPS) developed at the NASA Lewis Research Center is described. The RTMPS is a multiple microprocessor system used to investigate the application of parallel processing concepts to real time simulation. It is designed to provide flexible data exchange paths between processors by using off the shelf microcomputer boards and minimal customized interfacing. A dedicated operator interface allows easy setup of the simulator and quick interpreting of simulation data. Simulations for the RTMPS are coded in a NASA designed real time multiprocessor language (RTMPL). This language is high level and geared to the multiprocessor environment. A real time multiprocessor operating system (RTMPOS) has also been developed that provides a user friendly operator interface. The RTMPS and supporting software are currently operational and are being evaluated at Lewis. The results of this evaluation will be used to specify the design of an optimized parallel processing system for real time simulation of dynamic systems.

  8. Research on starlight hardware-in-the-loop simulator

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Gao, Yang; Qu, Huiyang; Liu, Dongfang; Du, Huijie; Lei, Jie

    2016-10-01

    The starlight navigation is considered to be one of the most important methods for spacecraft navigation. Starlight simulation system is a high-precision system with large fields of view, designed to test the starlight navigation sensor performance on the ground. A complete hardware-in-the-loop simulation of the system has been built. The starlight simulator is made up of light source, light source controller, light filter, LCD, collimator and control computer. LCD is the key display component of the system, and is installed at the focal point of the collimator. For the LCD cannot emit light itself, so light source and light source power controller is specially designed for the brightness demanded by the LCD. Light filter is designed for the dark background which is also needed in the simulation.

  9. An update on SCARLET hardware development and flight programs

    NASA Technical Reports Server (NTRS)

    Jones, P. Alan; Murphy, David M.; Piszczor, Michael F.; Allen, Douglas M.

    1995-01-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the 'array level' and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  10. An update on SCARLET hardware development and flight programs

    SciTech Connect

    Jones, P.A.; Murphy, D.M.; Piszczor, M.F.; Allen, D.M. |

    1995-10-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the `array level` and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  11. Quantum annealing correction with minor embedding

    NASA Astrophysics Data System (ADS)

    Vinci, Walter; Albash, Tameem; Paz-Silva, Gerardo; Hen, Itay; Lidar, Daniel A.

    2015-10-01

    Quantum annealing provides a promising route for the development of quantum optimization devices, but the usefulness of such devices will be limited in part by the range of implementable problems as dictated by hardware constraints. To overcome constraints imposed by restricted connectivity between qubits, a larger set of interactions can be approximated using minor embedding techniques whereby several physical qubits are used to represent a single logical qubit. However, minor embedding introduces new types of errors due to its approximate nature. We introduce and study quantum annealing correction schemes designed to improve the performance of quantum annealers in conjunction with minor embedding, thus leading to a hybrid scheme defined over an encoded graph. We argue that this scheme can be efficiently decoded using an energy minimization technique provided the density of errors does not exceed the per-site percolation threshold of the encoded graph. We test the hybrid scheme using a D-Wave Two processor on problems for which the encoded graph is a two-level grid and the Ising model is known to be NP-hard. The problems we consider are frustrated Ising model problem instances with "planted" (a priori known) solutions. Applied in conjunction with optimized energy penalties and decoding techniques, we find that this approach enables the quantum annealer to solve minor embedded instances with significantly higher success probability than it would without error correction. Our work demonstrates that quantum annealing correction can and should be used to improve the robustness of quantum annealing not only for natively embeddable problems but also when minor embedding is used to extend the connectivity of physical devices.

  12. Verifying Dissolution Of Wax From Hardware Surfaces

    NASA Technical Reports Server (NTRS)

    Montoya, Benjamina G.

    1995-01-01

    Wax removed by cleaning solvent revealed by cooling solution with liquid nitrogen. Such improved procedure and test needed in case of hardware that must be protected by wax during machining or plating but required to be free of wax during subsequent use. Improved cleaning procedure and test take less than 5 minutes. Does not require special skill or equipment and performs at cleaning site. In addition, enables recovery of all cleaning solvent.

  13. Hardware-Independent Proofs of Numerical Programs

    NASA Technical Reports Server (NTRS)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  14. Testing Microshutter Arrays Using Commercial FPGA Hardware

    NASA Technical Reports Server (NTRS)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  15. Fast Hardware Implementation Of The DOLP Transform

    NASA Astrophysics Data System (ADS)

    Waltz, Frederick M.

    1988-03-01

    The Difference-of-Low-Pass (DOLP) Transform uses a hierarchy of bandpass filters to perform size discrimination and pattern matching of objects and features in a visual field. Like the Discrete Fourier Transform (DFT), it "sorts" entities according to their size or spatial frequencies; but unlike the DFT, it also retains positional information.This positional information is essential for the very common industrial web inspection problem in which a "flaw map" must be produced - mere flaw detection (as provided by the DFT) is not enough. The DOLP Transform is usually implemented using finite-impulse-response difference-of-Gaussian (DOG) filters of progressively increasing kernel size. Various potential industrial applications have been described and demonstrated, but implementations have been hampered by the heavy computational burden involved in the generation of the Transform. This paper describes a fast implementation of Crowley's resampled DOLP Transform using commercially-available board-level hardware. With a moderate investment in hardware modules, a nine-band DOLP Transform can be computed for a 485 by 512 image in about one second. Additional hardware modules could be added to bring the speed up to 30 complete 9-band Transforms per second, if desired. Additional bands beyond the first nine, while seldom needed, require very little additional time, because the image has been repeatedly resampled down to a small size.

  16. "Greenbook Algorithms and Hardware Needs Analysis"

    SciTech Connect

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  17. Three- and four-body corrected fragment molecular orbital calculations with a novel subdividing fragmentation method applicable to structure-based drug design.

    PubMed

    Watanabe, Chiduru; Fukuzawa, Kaori; Okiyama, Yoshio; Tsukamoto, Takayuki; Kato, Akifumi; Tanaka, Shigenori; Mochizuki, Yuji; Nakano, Tatsuya

    2013-04-01

    We develop an inter-fragment interaction energy (IFIE) analysis based on the three- and four-body corrected fragment molecular orbital (FMO3 and FMO4) method to evaluate the interactions of functional group units in structure-based drug design context. The novel subdividing fragmentation method for a ligand (in units of their functional groups) and amino acid residues (in units of their main and side chains) enables us to understand the ligand-binding mechanism in more detail without sacrificing chemical accuracy of the total energy and IFIEs by using the FMO4 method. We perform FMO4 calculations with the second order Møller-Plesset perturbation theory for an estrogen receptor (ER) and the 17β-estradiol (EST) complex using the proposed fragmentation method and assess the interaction for each ligand-binding site by the FMO4-IFIE analysis. When the steroidal EST is divided into two functional units including "A ring" and "D ring", respectively, the FMO4-IFIE analysis reveals their binding affinity with surrounding fragments of the amino acid residues; the "A ring" of EST has polarization interaction with the main chain of Thr347 and two hydrogen bonds with the side chains of Glu353 and Arg394; the "D ring" of EST has a hydrogen bond with the side chain of His524. In particular, the CH/π interactions of the "A ring" of EST with the side chains of Leu387 and Phe404 are easily identified in cooperation with the CHPI program. The FMO4-IFIE analysis using our novel subdividing fragmentation method, which provides higher resolution than the conventional IFIE analysis in units of ligand and each amino acid reside in the framework of two-body approximation, is a useful tool for revealing ligand-binding mechanism and would be applicable to rational drug design such as structure-based drug design and fragment-based drug design.

  18. The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

    NASA Astrophysics Data System (ADS)

    Kathiara, Jainik

    There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

  19. A hardware fast tracker for the ATLAS trigger

    NASA Astrophysics Data System (ADS)

    Asbah, Nedaa

    2016-09-01

    The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

  20. A hardware overview of the RHIC LLRF platform

    SciTech Connect

    Hayes, T.; Smith, K.S.

    2011-03-28

    The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

  1. Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

    PubMed Central

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

  2. Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

    NASA Technical Reports Server (NTRS)

    Tobbe, Patrick; Matras, Alex; Walker, David; Wilson, Heath; Fulton, Chris; Alday, Nathan; Betts, Kevin; Hughes, Ryan; Turbe, Michael

    2009-01-01

    The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented.

  3. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 1, Activation measurements and comparison with calculations for spent fuel assembly hardware

    SciTech Connect

    Luksic, A.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1. 5 refs., 4 figs., 21 tabs.

  4. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 3, Calculated activity profiles of spent nuclear fuel assembly hardware for boiling water reactors

    SciTech Connect

    Short, S.M.; Luksic, A.T.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly that is also radioactive and required disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volume 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  5. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 2, Calculated activity profiles of spent nuclear fuel assembly hardware for pressurized water reactors

    SciTech Connect

    Short, S.M.; Luksic, A.T.; Lotz, T.L.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report present a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from Laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  6. Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

    NASA Technical Reports Server (NTRS)

    Bickford, Mark; Srivas, Mandayam

    1991-01-01

    Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

  7. Ultra-low noise miniaturized neural amplifier with hardware averaging

    NASA Astrophysics Data System (ADS)

    Dweiri, Yazan M.; Eggers, Thomas; McCallum, Grant; Durand, Dominique M.

    2015-08-01

    Objective. Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (<3 μVrms 700 Hz-7 kHz), thereby requiring a baseline noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Approach. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. Main results. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating <1.5 μVrms total recording baseline noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. Significance. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the

  8. Hardware Implementation of a Bilateral Subtraction Filter

    NASA Technical Reports Server (NTRS)

    Huertas, Andres; Watson, Robert; Villalpando, Carlos; Goldberg, Steven

    2009-01-01

    A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for

  9. Using Innovative Techniques for Manufacturing Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, Erin M.; Reynolds, David C.; Eddleman, David E.; Hardin, Andy

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using the Workhorse Gas Generator (WHGG) test setup at MSFC?s East Test Area test stand 116, the duct was subject to extreme J-2X gas generator environments and endured a total of 538 seconds of hot-fire time. The duct survived the testing and was inspected after the test. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  10. Using Innovative Technologies for Manufacturing Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  11. Defining Exercise Performance Metrics for Flight Hardware Development

    NASA Technical Reports Server (NTRS)

    Beyene, Nahon M.

    2004-01-01

    The space industry has prevailed over numerous design challenges in the spirit of exploration. Manned space flight entails creating products for use by humans and the Johnson Space Center has pioneered this effort as NASA's center for manned space flight. NASA Astronauts use a suite of flight exercise hardware to maintain strength for extravehicular activities and to minimize losses in muscle mass and bone mineral density. With a cycle ergometer, treadmill, and the Resistive Exercise Device available on the International Space Station (ISS), the Space Medicine community aspires to reproduce physical loading schemes that match exercise performance in Earth s gravity. The resistive exercise device presents the greatest challenge with the duty of accommodating 20 different exercises and many variations on the core set of exercises. This paper presents a methodology for capturing engineering parameters that can quantify proper resistive exercise performance techniques. For each specified exercise, the method provides engineering parameters on hand spacing, foot spacing, and positions of the point of load application at the starting point, midpoint, and end point of the exercise. As humans vary in height and fitness levels, the methodology presents values as ranges. In addition, this method shows engineers the proper load application regions on the human body. The methodology applies to resistive exercise in general and is in use for the current development of a Resistive Exercise Device. Exercise hardware systems must remain available for use and conducive to proper exercise performance as a contributor to mission success. The astronauts depend on exercise hardware to support extended stays aboard the ISS. Future plans towards exploration of Mars and beyond acknowledge the necessity of exercise. Continuous improvement in technology and our understanding of human health maintenance in space will allow us to support the exploration of Mars and the future of space

  12. Benchmarking Model Variants in Development of a Hardware-in-the-Loop Simulation System

    NASA Technical Reports Server (NTRS)

    Aretskin-Hariton, Eliot D.; Zinnecker, Alicia M.; Kratz, Jonathan L.; Culley, Dennis E.; Thomas, George L.

    2016-01-01

    Distributed engine control architecture presents a significant increase in complexity over traditional implementations when viewed from the perspective of system simulation and hardware design and test. Even if the overall function of the control scheme remains the same, the hardware implementation can have a significant effect on the overall system performance due to differences in the creation and flow of data between control elements. A Hardware-in-the-Loop (HIL) simulation system is under development at NASA Glenn Research Center that enables the exploration of these hardware dependent issues. The system is based on, but not limited to, the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k). This paper describes the step-by-step conversion from the self-contained baseline model to the hardware in the loop model, and the validation of each step. As the control model hardware fidelity was improved during HIL system development, benchmarking simulations were performed to verify that engine system performance characteristics remained the same. The results demonstrate the goal of the effort; the new HIL configurations have similar functionality and performance compared to the baseline C-MAPSS40k system.

  13. Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

    NASA Technical Reports Server (NTRS)

    Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

    2014-01-01

    Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-watt radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center (GRC). While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA GRC. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

  14. Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

    NASA Technical Reports Server (NTRS)

    Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

    2015-01-01

    Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

  15. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    NASA Technical Reports Server (NTRS)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  16. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2015-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  17. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2014-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink(R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  18. A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

    NASA Technical Reports Server (NTRS)

    Childress-Thompson, Rhonda; Thomas, Dale; Farrington, Phillip

    2016-01-01

    Within the space flight community, reusability has taken center stage as the new buzzword. In order for reusable hardware to be competitive with its expendable counterpart, two major elements must be closely scrutinized. First, recovery and refurbishment costs must be lower than the development and acquisition costs. Additionally, the reliability for reused hardware must remain the same (or nearly the same) as "first use" hardware. Therefore, it is imperative that a systematic approach be established to enhance the development of reusable systems. However, before the decision can be made on whether it is more beneficial to reuse hardware or to replace it, the parameters that are needed to deem hardware worthy of reuse must be identified. For reusable hardware to be successful, the factors that must be considered are reliability (integrity, life, number of uses), operability (maintenance, accessibility), and cost (procurement, retrieval, refurbishment). These three factors are essential to the successful implementation of reusability while enabling the ability to meet performance goals. Past and present strategies and attempts at reuse within the space industry will be examined to identify important attributes of reusability that can be used to evaluate hardware when contemplating reusable versus expendable options. This paper will examine why reuse must be stated as an initial requirement rather than included as an afterthought in the final design. Late in the process, changes in the overall objective/purpose of components typically have adverse effects that potentially negate the benefits. A methodology for assessing the viability of reusing hardware will be presented by using the Space Shuttle Main Engine (SSME) to validate the approach. Because reliability, operability, and costs are key drivers in making this critical decision, they will be used to assess requirements for reuse as applied to components of the SSME.

  19. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia Mae; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2014-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (40,000 pound force thrust) (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink (R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL

  20. The Impact of Flight Hardware Scavenging on Space Logistics

    NASA Technical Reports Server (NTRS)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  1. Summary of materials and hardware performance on LDEF

    NASA Technical Reports Server (NTRS)

    Dursch, Harry; Pippin, Gary; Teichman, Lou

    1993-01-01

    A wide variety of materials and experiment support hardware were flown on the Long Duration Exposure Facility (LDEF). Postflight testing has determined the effects of the almost 6 years of low-earth orbit (LEO) exposure on this hardware. An overview of the results are presented. Hardware discussed includes adhesives, fasteners, lubricants, data storage systems, solar cells, seals, and the LDEF structure. Lessons learned from the testing and analysis of LDEF hardware is also presented.

  2. Loads and Structural Dynamics Requirements for Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Schultz, Kenneth P.

    2011-01-01

    The purpose of this document is to establish requirements relating to the loads and structural dynamics technical discipline for NASA and commercial spaceflight launch vehicle and spacecraft hardware. Requirements are defined for the development of structural design loads and recommendations regarding methodologies and practices for the conduct of load analyses are provided. As such, this document represents an implementation of NASA STD-5002. Requirements are also defined for structural mathematical model development and verification to ensure sufficient accuracy of predicted responses. Finally, requirements for model/data delivery and exchange are specified to facilitate interactions between Launch Vehicle Providers (LVPs), Spacecraft Providers (SCPs), and the NASA Technical Authority (TA) providing insight/oversight and serving in the Independent Verification and Validation role. In addition to the analysis-related requirements described above, a set of requirements are established concerning coupling phenomena or other interaction between structural dynamics and aerodynamic environments or control or propulsion system elements. Such requirements may reasonably be considered structure or control system design criteria, since good engineering practice dictates consideration of and/or elimination of the identified conditions in the development of those subsystems. The requirements are included here, however, to ensure that such considerations are captured in the design space for launch vehicles (LV), spacecraft (SC) and the Launch Abort Vehicle (LAV). The requirements in this document are focused on analyses to be performed to develop data needed to support structural verification. As described in JSC 65828, Structural Design Requirements and Factors of Safety for Spaceflight Hardware, implementation of the structural verification requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each

  3. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry.

    PubMed

    Wang, Xin; Yang, James N; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-07

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm(2). The results showed that the rod increased the dose to water by ∼6% at the water-rod interface because of electron backscattering and decreased the dose by ∼7% in the shadow of the rod because of photon attenuation. The Pinnacle(3) treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm(-3) was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm(-3) (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm(-3) to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  4. DDL:Digital systems design language

    NASA Technical Reports Server (NTRS)

    Shival, S. G.

    1980-01-01

    Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

  5. CHeCS: International Space Station Medical Hardware Catalog

    NASA Technical Reports Server (NTRS)

    2008-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  6. Is Hardware Removal Recommended after Ankle Fracture Repair?

    PubMed Central

    Jung, Hong-Geun; Kim, Jin-Il; Park, Jae-Yong; Park, Jong-Tae; Eom, Joon-Sang

    2016-01-01

    The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients' daily activities. This study was conducted on 80 consecutive cases (78 patients) treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6) and decreased to 1.3 (range 0 to 6) after removal. 58 (72.5%) patients experienced improved ankle stiffness and 65 (81.3%) less discomfort while walking on uneven ground and 63 (80.8%) patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal. PMID:27819005

  7. Computer hardware for radiologists: Part 2

    PubMed Central

    Indrajit, IK; Alam, A

    2010-01-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future. PMID:21423895

  8. Computer hardware for radiologists: Part 2.

    PubMed

    Indrajit, Ik; Alam, A

    2010-11-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

  9. Effect of color visualization and display hardware on the visual assessment of pseudocolor medical images

    PubMed Central

    Zabala-Travers, Silvina; Choi, Mina; Cheng, Wei-Chung

    2015-01-01

    Purpose: Even though the use of color in the interpretation of medical images has increased significantly in recent years, the ad hoc manner in which color is handled and the lack of standard approaches have been associated with suboptimal and inconsistent diagnostic decisions with a negative impact on patient treatment and prognosis. The purpose of this study is to determine if the choice of color scale and display device hardware affects the visual assessment of patterns that have the characteristics of functional medical images. Methods: Perfusion magnetic resonance imaging (MRI) was the basis for designing and performing experiments. Synthetic images resembling brain dynamic-contrast enhanced MRI consisting of scaled mixtures of white, lumpy, and clustered backgrounds were used to assess the performance of a rainbow (“jet”), a heated black-body (“hot”), and a gray (“gray”) color scale with display devices of different quality on the detection of small changes in color intensity. The authors used a two-alternative, forced-choice design where readers were presented with 600 pairs of images. Each pair consisted of two images of the same pattern flipped along the vertical axis with a small difference in intensity. Readers were asked to select the image with the highest intensity. Three differences in intensity were tested on four display devices: a medical-grade three-million-pixel display, a consumer-grade monitor, a tablet device, and a phone. Results: The estimates of percent correct show that jet outperformed hot and gray in the high and low range of the color scales for all devices with a maximum difference in performance of 18% (confidence intervals: 6%, 30%). Performance with hot was different for high and low intensity, comparable to jet for the high range, and worse than gray for lower intensity values. Similar performance was seen between devices using jet and hot, while gray performance was better for handheld devices. Time of performance was

  10. A building block for hardware belief networks

    PubMed Central

    Behin-Aein, Behtash; Diep, Vinh; Datta, Supriyo

    2016-01-01

    Belief networks represent a powerful approach to problems involving probabilistic inference, but much of the work in this area is software based utilizing standard deterministic hardware based on the transistor which provides the gain and directionality needed to interconnect billions of them into useful networks. This paper proposes a transistor like device that could provide an analogous building block for probabilistic networks. We present two proof-of-concept examples of belief networks, one reciprocal and one non-reciprocal, implemented using the proposed device which is simulated using experimentally benchmarked models. PMID:27443521

  11. FORTE hardware-in-loop simulation

    SciTech Connect

    Ruud, K.K.; Murray, H.S.; Moore, T.K.

    1997-12-01

    Fast On-Orbit Recording of Transient Events (FORTE) is a small, low Earth orbit satellite scheduled for launch in August 1997. FORTE is a momentum-biased, gravity-gradient stabilized spacecraft. This paper describes the use of a hardware-in-loop simulator, developed by Ithaco Inc. and Los Alamos National Laboratory, in performing FORTE mission simulations. Scenarios studied include separation, acquisition on orbit, control system parameter sensitivity studies, sensor noise simulations, antenna deployment and momentum desaturation. Use of the simulator to refine control algorithms and sequences is also described.

  12. Cathode side hardware for carbonate fuel cells

    DOEpatents

    Xu, Gengfu; Yuh, Chao-Yi

    2011-04-05

    Carbonate fuel cathode side hardware having a thin coating of a conductive ceramic formed from one of Perovskite AMeO.sub.3, wherein A is at least one of lanthanum and a combination of lanthanum and strontium and Me is one or more of transition metals, lithiated NiO (Li.sub.xNiO, where x is 0.1 to 1) and X-doped LiMeO.sub.2, wherein X is one of Mg, Ca, and Co.

  13. Available hardware for automated entry control

    SciTech Connect

    Holmes, J.P.

    1990-11-01

    Automated entry control has become an increasingly important issue at facilities where budget constraints are limiting options for manned entry control points. Three questions are immediately raised when automated entry control is considered: What hardware is available How much does it cost How effective is it in maintaining security Ongoing work at Sandia National Labs is attempting to answer these questions and establish a data base for use by facility security managers working the problem of how to maintain security on a limited budget. 14 refs.

  14. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    NASA Technical Reports Server (NTRS)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  15. Analysis of systems hardware flown on LDEF: New findings and comparison to other retrieved spacecraft hardware

    NASA Technical Reports Server (NTRS)

    Dursch, Harry; Bohnhoff-Hlavacek, Gail; Blue, Donald; Hansen, Patricia

    1995-01-01

    The Long Duration Exposure Facility (LDEF) was retrieved in 1990 after spending 69 months in low-earth-orbit (LEO). A wide variety of mechanical, electrical, thermal, and optical systems, subsystems, and components were flown on LDEF. The Systems Special Investigation Group (Systems SIG) was formed by NASA to investigate the effects of the 69 month exposure on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware. This report is the Systems SIG final report which updates earlier findings and compares LDEF systems findings to results from other retrieved spacecraft hardware such as Hubble Space Telescope. Also included are sections titled (1) Effects of Long Duration Space Exposure on Optical Scatter, (2) Contamination Survey of LDEF, and (3) Degradation of Optical Materials in Space.

  16. Data Applicability of Heritage and New Hardware for Launch Vehicle System Reliability Models

    NASA Technical Reports Server (NTRS)

    Al Hassan Mohammad; Novack, Steven

    2015-01-01

    Many launch vehicle systems are designed and developed using heritage and new hardware. In most cases, the heritage hardware undergoes modifications to fit new functional system requirements, impacting the failure rates and, ultimately, the reliability data. New hardware, which lacks historical data, is often compared to like systems when estimating failure rates. Some qualification of applicability for the data source to the current system should be made. Accurately characterizing the reliability data applicability and quality under these circumstances is crucial to developing model estimations that support confident decisions on design changes and trade studies. This presentation will demonstrate a data-source classification method that ranks reliability data according to applicability and quality criteria to a new launch vehicle. This method accounts for similarities/dissimilarities in source and applicability, as well as operating environments like vibrations, acoustic regime, and shock. This classification approach will be followed by uncertainty-importance routines to assess the need for additional data to reduce uncertainty.

  17. Implementation of neural network hardware based on a floating point operation in an FPGA

    NASA Astrophysics Data System (ADS)

    Kim, Jeong-Seob; Jung, Seul

    2007-12-01

    This paper presents a hardware design and implementation of the radial basis function (RBF) neural network (NN) by the hardware description language. Due to its nonlinear characteristics, it is very difficult to implement for a system with integer-based operation. To develop nonlinear functions such sigmoid functions or exponential functions, floating point operations are required. The exponential function is designed based on the 32bit single-precision floating-point format. In addition, to update weights in the network, the back-propagation algorithm is also implemented in the hardware. Most operations are performed in the floating-point based arithmetic unit and accomplished sequentially by the instruction order stored in ROM. The NN is implemented and tested on the Altera FPGA "Cyclone2 EP2C70F672C8" for nonlinear classifications.

  18. First Light with the NRAO Transient Event Capture Hardware

    NASA Astrophysics Data System (ADS)

    Langston, Glen; Rumberg, B.; Brandt, P.

    2007-12-01

    The design, implementation and testing of the first NRAO Event Capture data acquisition system is presented. The NRAO in Green Bank is developing a set of new data acquisition systems based on the U.C. Berkeley CASPER IBOB/ADC/BEE2 hardware. We describe the hardware configuration and initial experiences with the development system. We present first astronomical tests of the Event Capture system, using the 43m telescope (140ft). These observations were carried out at 900 MHz. The observations were made on 2007 July 8 and 9 towards the Crab pulsar, the galactic center, the Moon and two test observations while the 43m was pointed at Zenith (straight up). The Event Capture is one of several on-going FPGA based data acquisition projects being implemented for the Robert C. Byrd Green Bank Telescope (GBT) and for the 43m telescopes. The NRAO Configurable Instrument Collaboration for Agile Data Acquisition (CICADA) program is described at: http://wikio.nrao.edu/bin/view/CICADA

  19. A modular suite of hardware enabling spaceflight cell culture research

    NASA Technical Reports Server (NTRS)

    Hoehn, Alexander; Klaus, David M.; Stodieck, Louis S.

    2004-01-01

    BioServe Space Technologies, a NASA Research Partnership Center (RPC), has developed and operated various middeck payloads launched on 23 shuttle missions since 1991 in support of commercial space biotechnology projects. Modular cell culture systems are contained within the Commercial Generic Bioprocessing Apparatus (CGBA) suite of flight-qualified hardware, compatible with Space Shuttle, SPACEHAB, Spacelab and International Space Station (ISS) EXPRESS Rack interfaces. As part of the CGBA family, the Isothermal Containment Module (ICM) incubator provides thermal control, data acquisition and experiment manipulation capabilities, including accelerometer launch detection for automated activation and thermal profiling for culture incubation and sample preservation. The ICM can accommodate up to 8 individually controlled temperature zones. Command and telemetry capabilities allow real-time downlink of data and video permitting remote payload operation and ground control synchronization. Individual cell culture experiments can be accommodated in a variety of devices ranging from 'microgravity test tubes' or standard 100 mm Petri dishes, to complex, fed-batch bioreactors with automated culture feeding, waste removal and multiple sample draws. Up to 3 levels of containment can be achieved for chemical fixative addition, and passive gas exchange can be provided through hydrophobic membranes. Many additional options exist for designing customized hardware depending on specific science requirements.

  20. Combined hardware and software models of reliability and availability for configuration with redundant hardware

    NASA Astrophysics Data System (ADS)

    Xu, Bin; Yao, Yiping

    This paper consists of three parts; in the first part, the development of combined hardware and software reliability analysis methods is summarized. In the second part, the prerequisite of modeling and two combined HW/SW reliability and availability models are presented. While the theoretical analytical model is based on Markov renewal processes, the numerical model is based on Markov processes. In the third part, the numerical model has been used to analyze the HW/SW reliability and availability for Fly-By-Wire flight control system configuration with redundant hardware in numerical quantities.

  1. Space biology initiative program definition review. Trade study 2: Prototype utilization in the development of space biology hardware

    NASA Technical Reports Server (NTRS)

    Jackson, L. Neal; Crenshaw, John, Sr.; Schulze, Arthur E.; Wood, H. J., Jr.

    1989-01-01

    The objective was to define the factors which space flight hardware developers and planners should consider when determining: (1) the number of hardware units required to support program; (2) design level of the units; and (3) most efficient means of utilization of the units. The analysis considered technology risk, maintainability, reliability, and safety design requirements for achieving the delivery of highest quality flight hardware. Relative cost impacts of the utilization of prototyping were identified. The development of Space Biology Initiative research hardware will involve intertwined hardware/software activities. Experience has shown that software development can be an expensive portion of a system design program. While software prototyping could imply the development of a significantly different end item, an operational system prototype must be considered to be a combination of software and hardware. Hundreds of factors were identified that could be considered in determining the quantity and types of prototypes that should be constructed. In developing the decision models, these factors were combined and reduced by approximately ten-to-one in order to develop a manageable structure based on the major determining factors. The Baseline SBI hardware list of Appendix D was examined and reviewed in detail; however, from the facts available it was impossible to identify the exact types and quantities of prototypes required for each of these items. Although the factors that must be considered could be enumerated for each of these pieces of equipment, the exact status and state of development of the equipment is variable and uncertain at this time.

  2. A two-step atomizer system using a transversely heated furnace with Zeeman background correction: Design and first solid sampling applications

    NASA Astrophysics Data System (ADS)

    Friese, K.-Ch.; Huang, M. D.; Schlemmer, G.; Krivan, V.

    2006-09-01

    A two-step-atomizer consisting of a transversely heated graphite atomization tube and a movable vaporizer graphite cup is described. The atomizer is placed between the poles of an electromagnetic field providing longitudinal Zeeman-effect background correction capability. The tube and the cup are heated by independent power supplies enabling the performance of atomic absorption measurements at temporally and spatially isothermal conditions. The design of the vaporizer provides several advantageous features including direct introduction of solid and liquid samples with extremely low contamination risk and a sampling volume of up to 105 μl. The performance of this system was assessed by analysis of the bovine liver NIST SRM 1577b and of a well characterized titanium dioxide material. Calibration curves for quantification were recorded by using aqueous standards. In comparison of the results obtained by this method with the certified values and with the results of independent methods, excellent to reasonable agreement was achieved. For the elements Fe, K, Mg, Mn, Na and Zn in titanium dioxide, the achievable limits of detection were between 60 pg g - 1 (Mg) and 0.7 ng g - 1 (Fe).

  3. ISS Logistics Hardware Disposition and Metrics Validation

    NASA Technical Reports Server (NTRS)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  4. Software and hardware infrastructure for research in electrophysiology

    PubMed Central

    Mouček, Roman; Ježek, Petr; Vařeka, Lukáš; Řondík, Tomáš; Brůha, Petr; Papež, Václav; Mautner, Pavel; Novotný, Jiří; Prokop, Tomáš; Štěbeták, Jan

    2014-01-01

    As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly. This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research. After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software. PMID:24639646

  5. Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware

    PubMed Central

    Srinivasa, Narayan; Stepp, Nigel D.; Cruz-Albrecht, Jose

    2015-01-01

    Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that can exhibit adaptive behaviors. Several designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoiding it. PMID:26648839

  6. A CORRECTION.

    PubMed

    Johnson, D

    1940-03-22

    IN a recently published volume on "The Origin of Submarine Canyons" the writer inadvertently credited to A. C. Veatch an excerpt from a submarine chart actually contoured by P. A. Smith, of the U. S. Coast and Geodetic Survey. The chart in question is Chart IVB of Special Paper No. 7 of the Geological Society of America entitled "Atlantic Submarine Valleys of the United States and the Congo Submarine Valley, by A. C. Veatch and P. A. Smith," and the excerpt appears as Plate III of the volume fist cited above. In view of the heavy labor involved in contouring the charts accompanying the paper by Veatch and Smith and the beauty of the finished product, it would be unfair to Mr. Smith to permit the error to go uncorrected. Excerpts from two other charts are correctly ascribed to Dr. Veatch.

  7. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    NASA Astrophysics Data System (ADS)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  8. 77 FR 72199 - Technical Corrections; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-05

    ... COMMISSION 10 CFR Part 171 RIN 3150-AJ16 Technical Corrections; Correction AGENCY: Nuclear Regulatory... corrections, including updating the street address for the Region I office, correcting authority citations and... rule. DATES: The correction is effective on December 5, 2012. FOR FURTHER INFORMATION CONTACT:...

  9. Movable Ground Based Recovery System for Reuseable Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Sarver, George L. (Inventor)

    2013-01-01

    A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

  10. Design and Testing of Hardware Improvements of an Acoustic Sounder.

    DTIC Science & Technology

    1985-06-01

    transmision factor of the transducer. The equation from Reference 4 for the transmission factor of a catenoidal horn is Th1 (16)Th = 1 -(foil) 2...differences between the hyperbolic and exponential functions are so small that the 0.01 centimeter machining accuracy of the milling lathe producing the...mold was crafted on a machining lathe from the dimensions in Appendix B. Next a layer of gel coat was applied over a silicon mol~d release onto which

  11. Implementing Strategic Management of Producibility in Military Hardware Design

    DTIC Science & Technology

    1985-05-01

    production life. Maximum producibility can not be reached unless it is nee Figura 5 considered prior to commencing production. The cost savings...from your publica ion will be greatfully acknowledged in my thesis and any possible follow on journal articles or presentations. Si ncer’el y. -12

  12. Essential SpaceWire Hardware Capabilities for a Robust Network

    NASA Technical Reports Server (NTRS)

    Birmingham, Michael; Krimchansky, Alexander; Anderson, William; Lombardi, Matthew

    2016-01-01

    The Geostationary Operational Environmental Satellite R-Series Program (GOES-R) mission is a joint program between National Oceanic & Atmospheric Administration (NOAA) and National Aeronautics & Space Administration (NASA) Goddard Space Flight Center (GSFC). GOES-R project selected SpaceWire as the best solution to satisfy the desire for simple and flexible instrument to spacecraft command and telemetry communications. GOES-R development and integration is complete and the observatory is scheduled for launch October 2016. The spacecraft design was required to support redundant SpaceWire links for each instrument side, as well as to route the fewest number of connections through a Slip Ring Assembly necessary to support Solar pointing instruments. The final design utilized two different router designs. The SpaceWire standard alone does not ensure the most practical or reliable network. On GOES-R a few key hardware capabilities were identified that merit serious consideration for future designs. Primarily these capabilities address persistent port stalls and the prevention of receive buffer overflows. Workarounds were necessary to overcome shortcomings that could be avoided in future designs if they utilize the capabilities, discussed in this paper, above and beyond the requirements of the SpaceWire standard.

  13. HOP: (Hardware Viewed as Objects and Processes). A Process Model for Synchronous Hardware Systems

    DTIC Science & Technology

    1988-01-01

    that was based on an abstract data type view of hardware systems into a new, simple, and deterministic process model that we have invented. Our process ... model is inspired by the works of Mil82, Mil83, and Hoa85. Secondly it is believed that not only should an HSL be founded in mathematical principles

  14. Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

    PubMed Central

    Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

    2011-01-01

    Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

  15. Hardware-Efficient Bilateral Filtering for Stereo Matching.

    PubMed

    Yang, Qingxiong

    2014-05-01

    This paper presents a new bilateral filtering method specially designed for practical stereo vision systems. Parallel algorithms are preferred in these systems due to the real-time performance requirement. Edge-preserving filters like the bilateral filter have been demonstrated to be very effective for high-quality local stereo matching. A hardware-efficient bilateral filter is thus proposed in this paper. When moved to an NVIDIA GeForce GTX 580 GPU, it can process a one megapixel color image at around 417 frames per second. This filter can be directly used for cost aggregation required in any local stereo matching algorithm. Quantitative evaluation shows that it outperforms all the other local stereo methods both in terms of accuracy and speed on Middlebury benchmark. It ranks 12th out of over 120 methods on Middlebury data sets, and the average runtime (including the matching cost computation, occlusion handling, and post processing) is only 15 milliseconds (67 frames per second).

  16. Fault Tolerant Characteristics of Artificial Neural Network Electronic Hardware

    NASA Technical Reports Server (NTRS)

    Zee, Frank

    1995-01-01

    The fault tolerant characteristics of analog-VLSI artificial neural network (with 32 neurons and 532 synapses) chips are studied by exposing them to high energy electrons, high energy protons, and gamma ionizing radiations under biased and unbiased conditions. The biased chips became nonfunctional after receiving a cumulative dose of less than 20 krads, while the unbiased chips only started to show degradation with a cumulative dose of over 100 krads. As the total radiation dose increased, all the components demonstrated graceful degradation. The analog sigmoidal function of the neuron became steeper (increase in gain), current leakage from the synapses progressively shifted the sigmoidal curve, and the digital memory of the synapses and the memory addressing circuits began to gradually fail. From these radiation experiments, we can learn how to modify certain designs of the neural network electronic hardware without using radiation-hardening techniques to increase its reliability and fault tolerance.

  17. The computer scene generation for star simulator hardware-in-the-loop simulation

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Yu, Hong; Du, Huijie; Lei, Jie

    2011-08-01

    The star sensor simulation system is used to test the star sensor performance on the ground, which is designed for star identification and spacecraft attitude determination of the spacecraft. The computer star scene based on the astronomical star chat is generated for hardware-in-the-loop simulation of the star sensor simulation system using by OpenGL.

  18. Danny Weber, a student experimenter, discusses experiment hardware for STS-7

    NASA Technical Reports Server (NTRS)

    1983-01-01

    Danny Weber, a student from Cornell University, discusses the hardware for an experiment he devised, with Astronaut Norman E. Thagard, STS-7 mission specialist. The experiment is entitled 'Effect of weightlessness on arthritis'. The cage and monitoring equipment shown are designed to use rats as the subjects for the study. Weber was attending Hunter College High School when he submitted the experiment.

  19. The Microwave Anisotropy Probe (MAP): Guidance, Navigation, and Control Hardware Suite

    NASA Technical Reports Server (NTRS)

    Ward, David K.; Davis, Gary T.; Bauer, Frank H. (Technical Monitor)

    2002-01-01

    The Microwave Anisotropy Probe (MAP) was launched June 30, 2001 to create an all-sky map of the Cosmic Microwave Background. The mission's hardware suite included two Lockheed Martin AST-201 star trackers, two Kearfott Two-Axis Rate Assemblies (TARAs) mounted to provide X, Y and redundant Z-axis rates, two Adcole Digital Sun Sensor (DSS) heads sharing one set of electronics, twelve Adcole Coarse Sun Sensor (CSS) eyes, three Ithaco E-sized Reaction Wheel Assemblies (RWAs), and a Propulsion Subsystem that employed eight PRIMEX Rocket Engine Modules (REMs). This hardware has allowed MAP to meet its various Orbit and Attitude Control Requirements, including performing a complex zero-momentum scan, meeting its attitude determination requirements, and maintaining a trajectory that places MAP in a lissajous orbit around the second Sun-Earth Lagrange point (L2) via phasing loops and a lunar gravity assist. Details of MAP's attitude determination, attitude control, and trajectory design are presented separately. This paper will focus on the performance of the hardware components mentioned above, as well as the significant lessons learned through the use of these components. An emphasis will be placed on spacecraft design modifications that were needed to accommodate existing hardware designs into the MAP Observatory design.

  20. A comparison of hardware description languages. [describing digital systems structure and behavior to a computer

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1978-01-01

    Several high level languages which evolved over the past few years for describing and simulating the structure and behavior of digital systems, on digital computers are assessed. The characteristics of the four prominent languages (CDL, DDL, AHPL, ISP) are summarized. A criterion for selecting a suitable hardware description language for use in an automatic integrated circuit design environment is provided.