Pulse width modulated push-pull driven parallel resonant converter with active free-wheel

DOEpatents

Reass, William A.; Schrank, Louis

2004-06-22

An apparatus and method for high frequency alternating power generation to control kilowatts of supplied power in microseconds. The present invention includes a means for energy storage, push-pull switching means, control electronics, transformer means, resonant circuitry and means for excess energy recovery, all in electrical communication. A push-pull circuit works synchronously with a force commutated free-wheel transistor to provide current pulses to a transformer. A change in the conduction angle of the push-pull circuit changes the amount of energy coupled into the transformer's secondary oscillating circuit, thereby altering the induced secondary resonating voltage. At the end of each pulse, the force commutated free-wheel transistor causes residual excess energy in the primary circuit to be transmitted back to the storage capacitor for later use.

Reconfigurable Drive Current System

NASA Technical Reports Server (NTRS)

Alhorn, Dean C. (Inventor); Dutton, Kenneth R. (Inventor); Howard, David E. (Inventor); Smith, Dennis A. (Inventor)

2017-01-01

A reconfigurable drive current system includes drive stages, each of which includes a high-side transistor and a low-side transistor in a totem pole configuration. A current monitor is coupled to an output of each drive stage. Input channels are provided to receive input signals. A processor is coupled to the input channels and to each current monitor for generating at least one drive signal using at least one of the input signals and current measured by at least one of the current monitors. A pulse width modulation generator is coupled to the processor and each drive stage for varying the drive signals as a function of time prior to being supplied to at least one of the drive stages.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

ELECTRONIC INTEGRATING CIRCUIT

DOEpatents

Englemann, R.H.

1963-08-20

An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Damage effect and mechanism of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

NASA Astrophysics Data System (ADS)

Xiao-Wen, Xi; Chang-Chun, Chai; Gang, Zhao; Yin-Tang, Yang; Xin-Hai, Yu; Yang, Liu

2016-04-01

The damage effect and mechanism of the electromagnetic pulse (EMP) on the GaAs pseudomorphic high electron mobility transistor (PHEMT) are investigated in this paper. By using the device simulation software, the distributions and variations of the electric field, the current density and the temperature are analyzed. The simulation results show that there are three physical effects, i.e., the forward-biased effect of the gate Schottky junction, the avalanche breakdown, and the thermal breakdown of the barrier layer, which influence the device current in the damage process. It is found that the damage position of the device changes with the amplitude of the step voltage pulse. The damage appears under the gate near the drain when the amplitude of the pulse is low, and it also occurs under the gate near the source when the amplitude is sufficiently high, which is consistent with the experimental results. Project supported by the National Basic Research Program of China (Grant No. 2014CB339900), and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (CAEP) (Grant No. 2015-0214.XY.K).

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

Switching Characteristics of a 4H-SiC Based Bipolar Junction Transistor to 200 C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.

2006-01-01

Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from room to 200 C. All testing was done in a pulse mode at low duty cycle (approx.0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of 7 V. These base drive signals were implemented by 850 V, gated power pulsers, having rise-times of roughly 10 ns, or less. Base charge sweep-out with a 7 V negative pulse did not produce the large reverse base current pulse seen in a comparably rated Si-based BJT. This may be due to a very low charge storage time. The decay of the collector current was more linear than its exponential-like rise. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 Omega non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 80 to 94 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 34 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 72 to 84 ns with the 7 V sweep-out.

Channel layer thickness dependence of In-Ti-Zn-O thin-film transistors fabricated using pulsed laser deposition

NASA Astrophysics Data System (ADS)

Zhang, Q.; Shan, F. K.; Liu, G. X.; Liu, A.; Lee, W. J.; Shin, B. C.

2014-05-01

Amorphous indium-titanium-zinc-oxide (ITZO) thin-film transistors (TFTs) with various channel thicknesses were fabricated at room temperature by using pulsed laser deposition. The channel layer thickness (CLT) dependence of the TFTs was investigated. All the ITZO thin films were amorphous, and the surface roughnesses decreased slightly first and then increased with increasing CLT. With increasing CLT from 35 to 140 nm, the on/off current ratio and the field-effect mobility increased, and the subthreshold swing decreased. The TFT with a CLT of 210 nm exhibited the worst performance, while the ITZO TFT with a CLT of 140 nm exhibited the best performance with a subthreshold voltage of 2.86 V, a mobility of 53.9 cm2V-1s-1, a subthreshold swing of 0.29 V/decade and an on/off current ratio of 109.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor

NASA Astrophysics Data System (ADS)

Yang, Paul; Kim, Hyung Jun; Zheng, Hong; Beom, Geon Won; Park, Jong-Sung; Kang, Chi Jung; Yoon, Tae-Sik

2017-06-01

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor.

PubMed

Yang, Paul; Jun Kim, Hyung; Zheng, Hong; Won Beom, Geon; Park, Jong-Sung; Jung Kang, Chi; Yoon, Tae-Sik

2017-06-02

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

High-voltage, high-current, solid-state closing switch

DOE Office of Scientific and Technical Information (OSTI.GOV)

Focia, Ronald Jeffrey

2017-08-22

A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications.

A hybrid pulse combining topology utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer.

PubMed

Li, Jiangtao; Zhao, Zheng; Sun, Yi; Liu, Yuhao; Ren, Ziyuan; He, Jiaxin; Cao, Hui; Zheng, Minjun

2017-03-01

Numerous applications driven by pulsed voltage require pulses to be with high amplitude, high repetitive frequency, and narrow width, which could be satisfied by utilizing avalanche transistors. The output improvement is severely limited by power capacities of transistors. Pulse combining is an effective approach to increase the output amplitude while still adopting conventional pulse generating modules. However, there are drawbacks in traditional topologies including the saturation tendency of combining efficiency and waveform oscillation. In this paper, a hybrid pulse combining topology was adopted utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer. The factors affecting the combining efficiency were determined including the output time synchronization of Marx circuits, and the quantity and position of magnetic cores. The numbers of the parallel modules and the stages were determined by the output characteristics of each combining method. Experimental results illustrated the ability of generating pulses with 2-14 kV amplitude, 7-11 ns width, and a maximum 10 kHz repetitive rate on a matched 50-300 Ω resistive load. The hybrid topology would be a convinced pulse combining method for similar nanosecond pulse generators based on the solid-state switches.

A hybrid pulse combining topology utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer

NASA Astrophysics Data System (ADS)

Li, Jiangtao; Zhao, Zheng; Sun, Yi; Liu, Yuhao; Ren, Ziyuan; He, Jiaxin; Cao, Hui; Zheng, Minjun

2017-03-01

Numerous applications driven by pulsed voltage require pulses to be with high amplitude, high repetitive frequency, and narrow width, which could be satisfied by utilizing avalanche transistors. The output improvement is severely limited by power capacities of transistors. Pulse combining is an effective approach to increase the output amplitude while still adopting conventional pulse generating modules. However, there are drawbacks in traditional topologies including the saturation tendency of combining efficiency and waveform oscillation. In this paper, a hybrid pulse combining topology was adopted utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer. The factors affecting the combining efficiency were determined including the output time synchronization of Marx circuits, and the quantity and position of magnetic cores. The numbers of the parallel modules and the stages were determined by the output characteristics of each combining method. Experimental results illustrated the ability of generating pulses with 2-14 kV amplitude, 7-11 ns width, and a maximum 10 kHz repetitive rate on a matched 50-300 Ω resistive load. The hybrid topology would be a convinced pulse combining method for similar nanosecond pulse generators based on the solid-state switches.

PULSE COUNTER

DOEpatents

Trumbo, D.E.

1959-02-10

A transistorized pulse-counting circuit adapted for use with nuclear radiation detecting detecting devices to provide a small, light weight portable counter is reported. The small size and low power requirements of the transistor are of particular value in this instance. The circuit provides an adjustable count scale with a single transistor which is triggered by the accumulated charge on a storage capacitor.

Electron emission controller with pulsed heating of filament

NASA Astrophysics Data System (ADS)

Durakiewicz, Tomasz

1996-11-01

A novel circuit has been invented for the versatile and safe stabilization of the electron emission current (Ie) produced by a hot filament in mass spectrometers or in ionization gauges. The voltage signal, which is directly proportional to Ie, is provided to the inverting input of a comparator, whereas the noninverting input is connected to the reference voltage. In addition to the commonly used negative feedback loop, a positive feedback loop was introduced by siting a resistor between the noninverting input and the output of the comparator, which results in a pulsation of the filament voltage. The pulses are rectangular, so that the power dissipated by the transistor in the filament power supply circuit is radically reduced. To refine the switching action of the transistor, the output of the comparator is connected through a capacitor to the transistor gate. A concise discussion of the phase shift between Ie, the filament temperature Tf, and the filament voltage Vf, including time constants for different modes of power dissipation, is included.

Pulse oximeter using a gain-modulated avalanche photodiode operated in a pseudo lock-in light detection mode

NASA Astrophysics Data System (ADS)

Miyata, Tsuyoshi; Iwata, Tetsuo; Araki, Tsutomu

2006-01-01

We propose a reflection-type pulse oximeter, which employs two pairs of a light-emitting diode (LED) and a gated avalanche photodiode (APD). One LED is a red one with an emission wavelength λ = 635 nm and the other is a near-infrared one with that λ = 945 nm, which are both driven with a pulse mode at a frequency f (=10 kHz). Superposition of a transistor-transistor-logic (TTL) gate pulse on a direct-current (dc) bias, which is set so as not exceeding the breakdown voltage of each APD, makes the APD work in a gain-enhanced operation mode. Each APD is gated at a frequency 2f (=20 kHz) and its output signal is fed into a laboratory-made lock-in amplifier that works in synchronous with the pulse modulation signal of each LED at a frequency f (=10 kHz). A combination of the gated APD and the lock-in like signal detection scheme is useful for the reflection-type pulse oximeter thanks to the capability of detecting a weak signal against a large background (BG) light.

Paired-pulse facilitation achieved in protonic/electronic hybrid indium gallium zinc oxide synaptic transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Li Qiang, E-mail: guoliqiang@ujs.edu.cn; Ding, Jian Ning; Huang, Yu Kai

2015-08-15

Neuromorphic devices with paired pulse facilitation emulating that of biological synapses are the key to develop artificial neural networks. Here, phosphorus-doped nanogranular SiO{sub 2} electrolyte is used as gate dielectric for protonic/electronic hybrid indium gallium zinc oxide (IGZO) synaptic transistor. In such synaptic transistors, protons within the SiO{sub 2} electrolyte are deemed as neurotransmitters of biological synapses. Paired-pulse facilitation (PPF) behaviors for the analogous information were mimicked. The temperature dependent PPF behaviors were also investigated systematically. The results indicate that the protonic/electronic hybrid IGZO synaptic transistors would be promising candidates for inorganic synapses in artificial neural network applications.

Optical pulse generation in a transistor laser via intra-cavity photon-assisted tunneling and excess base carrier redistribution

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, M.; Iverson, E. W.; Wang, C. Y.

2015-11-02

For a direct-gap semiconductor (e.g., a p-n junction), photon-assisted tunneling is known to exhibit a high nonlinear absorption. In a transistor laser, as discussed here, the coherent photons generated at the quantum well interact with the collector junction field and “assist” electron tunneling from base to collector, thus resulting in the nonlinear modulation of the laser and the realization of optical pulse generation. 1 and 2 GHz optical pulses are demonstrated in the transistor laser using collector voltage control.

The use of harmonic analysis to investigate processes in irradiated transistor structures

NASA Astrophysics Data System (ADS)

Gnap, A. K.; Zaliubovskii, I. I.; Dakhov, V. M.; Pelikhatyi, N. M.; Filippenko, V. E.

A theoretical model is developed for analyzing the behavior of transistor structures under irradiation by high-energy particles. Specifically, attention is given to the operation of a transistor switch under irradiation by 2-MeV neutrons. The proposed approach involves the replacement of the actual voltage pulse by a trapezoidal pulse, and the application of harmonic analysis to the latter. The parameters of the actual pulse can then be determined from an analysis of the constant component of the signal and the value of one of its harmonics.

Fabrication of InGaN thin-film transistors using pulsed sputtering deposition.

PubMed

Itoh, Takeki; Kobayashi, Atsushi; Ueno, Kohei; Ohta, Jitsuo; Fujioka, Hiroshi

2016-07-07

We report the first demonstration of operational InGaN-based thin-film transistors (TFTs) on glass substrates. The key to our success was coating the glass substrate with a thin amorphous layer of HfO2, which enabled a highly c-axis-oriented growth of InGaN films using pulsed sputtering deposition. The electrical characteristics of the thin films were controlled easily by varying their In content. The optimized InGaN-TFTs exhibited a high on/off ratio of ~10(8), a field-effect mobility of ~22 cm(2) V(-1) s(-1), and a maximum current density of ~30 mA/mm. These results lay the foundation for developing high-performance electronic devices on glass substrates using group III nitride semiconductors.

Driver Circuit For High-Power MOSFET's

NASA Technical Reports Server (NTRS)

Letzer, Kevin A.

1991-01-01

Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

NASA Technical Reports Server (NTRS)

Niedra, Janis M.

2006-01-01

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

A Simple Constant-Current Neural Stimulator With Accurate Pulse-Amplitude Control

DTIC Science & Technology

2001-10-25

STIMULATOR The block diagram of the proposed neurostimulator is displayed in Figure 1. It consists of a pair of transformers followed by full-bridge...to 6%. Pulse-repetition ranges from 1Hz to 10Hz. Figure 1. Block diagram of the neurostimulator Voltage Regulator T 1 Astable T 2 V/I...discrete transistors. For explanatory reasons, the neurostimulator schematic is split into three main elements: the oscillator, the output V/I converter

VERNIER CHRONOTRON UTILIZING AT LEAST TWO SHORTED DELAY LINES

DOEpatents

Rufer, R.P.

1964-02-25

An improved vernier chronotron featuring pulse-forming circuits of a ringing'' or back and forth'' oscillatory type is described. A delay line shorted at both ends together with transistor circuitry to introduce a pulse into that line and also to provide reinforcement of the pulse as it oscillates between the pulse-reflective extremities is provided. A transistorized coincidence circuit is also provided. Enhanced measurement of time intervals in the nanosecond range is afforded. (AEC)

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

An innovative high-power constant-current pulsed-arc power-supply for a high-density pulsed-arc-plasma ion-source using a LaB6-filament.

PubMed

Ueno, A; Oguri, H; Ikegami, K; Namekawa, Y; Ohkoshi, K; Tokuchi, A

2010-02-01

An innovative high-power constant-current (CC) pulsed-arc (PA) power-supply (PS) indispensable for a high-density PA plasma ion-source using a lanthanum hexaboride (LaB(6)) filament was devised by combining a constant-voltage (CV) PA-PS, which is composed of an insulated gate bipolar transistor (IGBT) switch, a CV direct-current (dc) PS and a 270 mF capacitor with a CC-PA-PS, which is composed of an IGBT-switch, a CC-dc-PS and a 400 microH inductor, through the inductor. The hybrid-CC-PA-PS succeeded in producing a flat arc-pulse with a peak power of 56 kW (400 A x 140 V) and a duty factor of more than 1.5% (600 micros x 25 Hz) for Japan Proton Accelerator Research Complex (J-PARC) H(-) ion-source stably. It also succeeded in shortening the 99% rising-time of the arc-pulse-current to about 20 micros and tilting up or down the arc-pulse-current arbitrarily and almost linearly by changing the setting voltage of its CV-dc-PS.

Method of making self-aligned lightly-doped-drain structure for MOS transistors

DOEpatents

Weiner, Kurt H.; Carey, Paul G.

2001-01-01

A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

Analysis of SET pulses propagation probabilities in sequential circuits

NASA Astrophysics Data System (ADS)

Cai, Shuo; Yu, Fei; Yang, Yiqun

2018-05-01

As the feature size of CMOS transistors scales down, single event transient (SET) has been an important consideration in designing logic circuits. Many researches have been done in analyzing the impact of SET. However, it is difficult to consider numerous factors. We present a new approach for analyzing the SET pulses propagation probabilities (SPPs). It considers all masking effects and uses SET pulses propagation probabilities matrices (SPPMs) to represent the SPPs in current cycle. Based on the matrix union operations, the SPPs in consecutive cycles can be calculated. Experimental results show that our approach is practicable and efficient.

Digital control of a direct current converter for a hybrid vehicle

NASA Astrophysics Data System (ADS)

Hernandez, Juan Manuel

The nonlinear feedback loops permitting the large signal control of pulse width modulators in direct current converters are discussed. A digital feedback loop on a converter controlling the coupling of a direct current machine is described. It is used in the propulsion of a hybrid vehicle (thermal-electric) with regenerative braking. The protection of the power switches is also studied. An active protection of the MOST bipolar transistor association is proposed.

A light-stimulated synaptic transistor with synaptic plasticity and memory functions based on InGaZnO{sub x}–Al{sub 2}O{sub 3} thin film structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, H. K.; Chen, T. P., E-mail: echentp@ntu.edu.sg; Liu, P.

In this work, a synaptic transistor based on the indium gallium zinc oxide (IGZO)–aluminum oxide (Al{sub 2}O{sub 3}) thin film structure, which uses ultraviolet (UV) light pulses as the pre-synaptic stimulus, has been demonstrated. The synaptic transistor exhibits the behavior of synaptic plasticity like the paired-pulse facilitation. In addition, it also shows the brain's memory behaviors including the transition from short-term memory to long-term memory and the Ebbinghaus forgetting curve. The synapse-like behavior and memory behaviors of the transistor are due to the trapping and detrapping processes of the holes, which are generated by the UV pulses, at the IGZO/Al{submore » 2}O{sub 3} interface and/or in the Al{sub 2}O{sub 3} layer.« less

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

PubMed

Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

2016-04-26

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

High Performance 0.1 μm GaAs Pseudomorphic High Electron Mobility Transistors with Si Pulse-Doped Cap Layer for 77 GHz Car Radar Applications

NASA Astrophysics Data System (ADS)

Kim, Sungwon; Noh, Hunhee; Jang, Kyoungchul; Lee, JaeHak; Seo, Kwangseok

2005-04-01

In this study, 0.1 μm double-recessed T-gate GaAs pseudomorphic high electron mobility transistors (PHEMT’s), in which an InGaAs layer and a Si pulse-doped layer in the cap structure are inserted, have been successfully fabricated. This cap structure improves ohmic contact. The ohmic contact resistance is as small as 0.07 Ωmm, consequently the source resistance is reduced by about 20% compared to that of a conventional cap structure. This device shows good DC and microwave performance such as an extrinsic transconductance of 620 mS/mm, a maximum saturated drain current of 780 mA/mm, a cut-off frequency fT of 140 GHz and a maximum oscillation frequency of 260 GHz. The reverse breakdown is 5.7 V at a gate current density of 1 mA/mm. The maximum available gain is about 7 dB at 77 GHz. It is well suited for car radar monolithic microwave integrated circuits (MMICs).

A pulsed load model and its impact on a synchronous-rectifier system

NASA Astrophysics Data System (ADS)

Hou, Pengfei; Xu, Ye; Li, Jianke; Wang, Jinquan; Zhang, Haitao; Yan, Jun; Wang, Chunming; Chen, Jingjing

2017-02-01

The pulsed load has become a developing trend of power loading. Unlike traditional loads, pulsed loads with current abrupt and repeated charges will result in unstable Microgrid operations because of their small capacity and inertia. In this paper, an Average Magnitude Sum Function (AMSF) is proposed to calculate the frequency of the grid, and based on AMSF, the Relative Deviation Rate (RDR) that characterises the impact of pulsed load on the AC side of the grid is defined and its calculation process is described in detail. In addition, the system dynamic characteristics under a pulsed load are analysed using an Insulated Gate Bipolar Transistor (IGBT) to control the on/off state of the resistive load for simulating a pulsed load. Finally, the transient characteristics of a synchronous-rectifier system with a pulsed load are studied and validated experimentally.

Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

DTIC Science & Technology

2015-02-01

executed with SolidWorks Flow Simulation , a computational fluid-dynamics code. The graph in Fig. 2 shows the timing and amplitudes of power pulses...defined a convective flow of air perpendicular to the bottom surface of the mounting plate, with a velocity of 10 ft/s. The thermal simulations were...Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors. I. Analytical modeling of time-dependent characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Cramer, T.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

Metal-oxide-semiconductor (MOS) transistors fabricated with pentacene thin films were characterized by temperature-dependent current-voltage (I-V) characteristics, time-dependent current measurements, and admittance spectroscopy. The channel mobility shows almost linear variation with temperature, suggesting that only shallow traps are present in the semiconductor and at the oxide/semiconductor interface. The admittance spectra feature a broad peak, which can be modeled as the sum of a continuous distribution of relaxation times. The activation energy of this peak is comparable to the polaron binding energy in pentacene. The absence of trap signals in the admittance spectra confirmed that both the semiconductor and the oxide/semiconductor interface have negligible density of deep traps, likely owing to the passivation of SiO2 before pentacene growth. Nevertheless, current instabilities were observed in time-dependent current measurements following the application of gate-voltage pulses. The corresponding activation energy matches the energy of a hole trap in SiO2. We show that hole trapping in the oxide can explain both the temperature and the time dependences of the current instabilities observed in pentacene MOS transistors. The combination of these experimental techniques allows us to derive a comprehensive model for charge transport in hybrid architectures where trapping processes occur at various time and length scales.

A Novel Transcranial Magnetic Stimulator Inducing Near Rectangular Pulses with Controllable Pulse Width (cTMS)

PubMed Central

Jalinous, Reza; Lisanby, Sarah H.

2013-01-01

A novel transcranial magnetic stimulation (TMS) device with controllable pulse width (PW) and near rectangular pulse shape (cTMS) is described. The cTMS device uses an insulated gate bipolar transistor (IGBT) with appropriate snubbers to switch coil currents up to 7 kA, enabling PW control from 5 μs to over 100 μs. The near-rectangular induced electric field pulses use 22–34% less energy and generate 67–72% less coil heating compared to matched conventional cosine pulses. CTMS is used to stimulate rhesus monkey motor cortex in vivo with PWs of 20 to 100 μs, demonstrating the expected decrease of threshold pulse amplitude with increasing PW. The technological solutions used in the cTMS prototype can expand functionality, and reduce power consumption and coil heating in TMS, enhancing its research and therapeutic applications. PMID:18232369

Origin of switching current transients in TIPS-pentacene based organic thin-film transistor with polymer dielectric

NASA Astrophysics Data System (ADS)

Singh, Subhash; Mohapatra, Y. N.

2017-06-01

We have investigated switch-on drain-source current transients in fully solution-processed thin film transistors based on 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) using cross-linked poly-4-vinylphenol as a dielectric. We show that the nature of the transient (increasing or decreasing) depends on both the temperature and the amplitude of the switching pulse at the gate. The isothermal transients are analyzed spectroscopically in a time domain to extract the degree of non-exponentiality and its possible origin in trap kinetics. We propose a phenomenological model in which the exchange of electrons between interfacial ions and traps controls the nature of the drain current transients dictated by the Fermi level position. The origin of interfacial ions is attributed to the essential fabrication step of UV-ozone treatment of the dielectric prior to semiconductor deposition.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-01

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states.

PubMed

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-27

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Study of current collapse by quiescent-bias-stresses in rf-plasma assisted MBE grown AlGaN/GaN high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Arulkumaran, S.; Ng, G. I.; Lee, C. H.; Liu, Z. H.; Radhakrishnan, K.; Dharmarasu, N.; Sun, Z.

2010-11-01

Studies on the influence of quiescent-gate ( Vgs0) and quiescent-drain ( Vds0) bias stresses in rf-plasma MBE grown AlGaN/GaN high-electron-mobility transistors (HEMTs) were performed. The increase of drain current ( ID) collapse by quiescent-bias-stress in AlGaN/GaN HEMTs were observed using pulsed (pulse width = 200 ns; pulse period = 1 ms) IDS- VDS characteristics. The Si 3N 4 passivation suppressed about 80% ID collapse in quiescent-bias-point stressed HEMTs. The remaining 20% ID collapse were not suppressed which may be coming from buffer-related traps. However, more than 10% of ID collapse suppression was observed on un-stressed or fresh-HEMTs. Similarly, improved cut-off frequency ( fT), maximum oscillation frequency ( fmax) and device output power ( Pout) values were also observed on the un-stressed HEMTs. The Si 3N 4 passivation completely suppressed the ID collapse in un-stressed or fresh-HEMTs which leads to 70% improvement in fT and 60% improvement in the device Pout. The Si 3N 4 passivation did not completely suppress ID collapse in the quiescent-bias stressed-HEMTs. This may be due to the generation of additional surface-related traps in the HEMTs by quiescent-bias-stresses.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

TRANSISTORIZED RADIATION MEASURING APPARATUS FOR $gamma$-RAYS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Beug, L.; Rudack, G.

1961-06-24

It is often necessary to measure the content of containers which for various reasons cannot be opened or inspected visually, but the gamma rays emitted by certain radioisotopes can be used for these measuring purposes because they can penetrate iron walls of from 2 to 100 mm thickness. A level gage is described which consists of a measuring table, a radiation source, a radiation detector, a transformer which converts the incident rays in electric current, a discriminator, a recording device, and an adequate current supply. In principle, there are 2 different measuring methods: one uses 2 counting tubes and determinesmore » the level by the difference method, while the other uses only one tube which has been calibrated with a standard source. Several circuit diagrams used in the construction of the devices are discussed. The use of transistors instead of electron tubes is advantageous because they are more compact, sturdier, less dependent on temperature, have a longer life time, and are more economical. A table shows the characteristic properties of one radiation measuring device: 100 pulses/sec, 200 mu amp, -20 deg -+50 deg C, 500-5000 OMEGA , 12w, counting duration 10/sup 10/ pulses. (OID)« less

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Controlling light by light with an optical event horizon.

PubMed

Demircan, A; Amiranashvili, Sh; Steinmeyer, G

2011-04-22

A novel concept for an all-optical transistor is proposed and verified numerically. This concept relies on cross-phase modulation between a signal and a control pulse. Other than previous approaches, the interaction length is extended by temporally locking control and the signal pulse in an optical event horizon, enabling continuous modification of the central wavelength, energy, and duration of a signal pulse by an up to sevenfold weaker control pulse. Moreover, if the signal pulse is a soliton it may maintain its solitonic properties during the switching process. The proposed all-optical switching concept fulfills all criteria for a useful optical transistor in [Nat. Photon. 4, 3 (2010)], in particular, fan-out and cascadability, which have previously proven as the most difficult to meet.

Proton irradiation of MgO- or Sc 2O 3 passivated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Luo, B.; Ren, F.; Allums, K. K.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Dwivedi, R.; Fogarty, T. N.; Wilkins, R.; Fitch, R. C.; Gillespie, J. K.; Jenkins, T. J.; Dettmer, R.; Sewell, J.; Via, G. D.; Crespo, A.; Baca, A. G.; Shul, R. J.

2003-06-01

AlGaN/GaN high electron mobility transistors with either MgO or Sc 2O 3 surface passivation were irradiated with 40 MeV protons at a dose of 5×10 9 cm -2. While both forward and reverse bias current were decreased in the devices as a result of decreases in channel doping and introduction of generation-recombination centers, there was no significant change observed in gate lag measurements. By sharp contrast, unpassivated devices showed significant decreases in drain current under pulsed conditions for the same proton dose. These results show the effectiveness of the oxide passivation in mitigating the effects of surface states present in the as-grown structures and also of surface traps created by the proton irradiation.

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications.

PubMed

Merced-Grafals, Emmanuelle J; Dávila, Noraica; Ge, Ning; Williams, R Stanley; Strachan, John Paul

2016-09-09

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10(6) cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.

Development of a tester for evaluation of prototype thermal cells and batteries

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guidotti, R.A.

1994-10-01

A tester was developed to evaluate prototype thermal cells and batteries--especially high-voltage units--under a wide range of constant-current and constant-resistance discharge conditions. Programming of the steady-state and pulsing conditions was by software control or by hardware control via an external pulse generator. The tester was assembled from primarily Hewlett-Packard (H-P) instrumentation and was operated under H-P`s Rocky Mountain Basic (RMB). Constant-current electronic loads rated up to 4 kW (400 V at up to 100 A) were successfully used with the setup. For testing under constant-resistance conditions, power metal-oxide field-effect transistors (MOSFETs) controlled by a programmable pulse generator were used tomore » switch between steady-state and pulse loads. The pulses were digitized at up to a 50 kHz rate (20 {mu} s/pt) using high-speed DVMs; steady-state voltages were monitored with standard DVMs. This paper describes several of the test configurations used and discusses the limitations of each. Representative data are presented for a number of the test conditions.« less

Optimized power simulation of AlGaN/GaN HEMT for continuous wave and pulse applications

NASA Astrophysics Data System (ADS)

Tiwat, Pongthavornkamol; Lei, Pang; Xinhua, Wang; Sen, Huang; Guoguo, Liu; Tingting, Yuan; Xinyu, Liu

2015-07-01

An optimized modeling method of 8 × 100 μm AlGaN/GaN-based high electron mobility transistor (HEMT) for accurate continuous wave (CW) and pulsed power simulations is proposed. Since the self-heating effect can occur during the continuous operation, the power gain from the continuous operation significantly decreases when compared to a pulsed power operation. This paper extracts power performances of different device models from different quiescent biases of pulsed current-voltage (I-V) measurements and compared them in order to determine the most suitable device model for CW and pulse RF microwave power amplifier design. The simulated output power and gain results of the models at Vgs = -3.5 V, Vds = 30 V with a frequency of 9.6 GHz are presented. Project supported by the National Natural Science Foundation of China (No. 61204086).

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Engineering Design Handbook: Reliable Military Electronics

DTIC Science & Technology

1976-01-15

p. 30. CBS-Hytron: "I..ow-o::stPower Trall8istors," E1a::Drnic Design, 1 Nov. 1956, p. 24. Chang, C. M.: "An NPN High-Power Fast Germanium Col:e...34Monovibrator Has Fast Recovery Time," Electronics, Dec. 1957, p. 158. Carlson, A W. : "Junction Transistor Counters," EledronicDesign, 1 March 1957, p. 28...Method Makes Fast Pulses in Transistor Circuits," Electronic Design, 28 May 1958, p. 44. Stassior, R. A : "Pulse Applications cf a Diffused-Meltback

Methods of high current magnetic field generator for transcranial magnetic stimulation application

NASA Astrophysics Data System (ADS)

Bouda, N. R.; Pritchard, J.; Weber, R. J.; Mina, M.

2015-05-01

This paper describes the design procedures and underlying concepts of a novel High Current Magnetic Field Generator (HCMFG) with adjustable pulse width for transcranial magnetic stimulation applications. This is achieved by utilizing two different switching devices, the MOSFET and insulated gate bipolar transistor (IGBT). Results indicate that currents as high as ±1200 A can be generated with inputs of +/-20 V. Special attention to tradeoffs between field generators utilizing IGBT circuits (HCMFG1) and MOSFET circuits (HCMFG2) was considered. The theory of operation, design, experimental results, and electronic setup are presented and analyzed.

Methods of high current magnetic field generator for transcranial magnetic stimulation application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bouda, N. R., E-mail: nybouda@iastate.edu; Pritchard, J.; Weber, R. J.

This paper describes the design procedures and underlying concepts of a novel High Current Magnetic Field Generator (HCMFG) with adjustable pulse width for transcranial magnetic stimulation applications. This is achieved by utilizing two different switching devices, the MOSFET and insulated gate bipolar transistor (IGBT). Results indicate that currents as high as ±1200 A can be generated with inputs of +/−20 V. Special attention to tradeoffs between field generators utilizing IGBT circuits (HCMFG{sub 1}) and MOSFET circuits (HCMFG{sub 2}) was considered. The theory of operation, design, experimental results, and electronic setup are presented and analyzed.

Transient electro-thermal characterization of Si-Ge heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Sahoo, Amit Kumar; Weiß, Mario; Fregonese, Sébastien; Malbert, Nathalie; Zimmer, Thomas

2012-08-01

In this paper, a comprehensive evaluation of the transient self-heating in microwave heterojunction bipolar transistors (HBTs) have been carried out through simulations and measurements. Three dimensional thermal TCAD simulations have been performed to investigate precisely the influence of backend metallization on transient thermal behavior of a submicron SiGe:C BiCMOS technology with fT and fmax of 230 GHz and 290 GHz, respectively. Transient variation of Collector current caused by self-heating is obtained through pulse measurements. For thermal characterization, different electro-thermal networks have been employed at the temperature node of HiCuM compact model. Thermal parameters have been extracted by means of compact model simulation using a scalable transistor library. It has been shown that, the conventional R-C thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement.

The 5-kW arcjet power electronics

NASA Technical Reports Server (NTRS)

Gruber, R. P.; Gott, R. W.; Haag, T. W.

1989-01-01

The initial design and evaluation of a 5 kW arcjet power electronics breadboard which as been integrated with a modified 1 kW design laboratory arcjet is presented. A single stage, 5 kW full bridge, pulse width modulated (PWM), power converter was developed which was phase shift regulated. The converter used metal oxide semiconductor field effect transistor (MOSFET) power switches and incorporated current mode control and an integral arcjet pulse ignition circuit. The unoptimized power efficiency was 93.5 and 93.9 percent at 5 kW and 50A output at input voltages of 130 and 150V, respectively. Line and load current regulation at 50A output was within one percent. The converter provided up to 6.6 kW to the arcjet with simulated ammonia used as a propellant.

Solid-state X-band Combiner Study

NASA Technical Reports Server (NTRS)

Pitzalis, O., Jr.; Russell, K. J.

1979-01-01

The feasibility of developing solid-state amplifiers at 4 and 10 GHz for application in spacecraft altimeters was studied. Bipolar-transistor, field-effect-transistor, and Impatt-diode amplifier designs based on 1980 solid-state technology are investigated. Several output power levels of the pulsed, low-duty-factor amplifiers are considered at each frequency. Proposed transistor and diode amplifier designs are illustrated in block diagrams. Projections of size, weight, and primary power requirements are given for each design.

flexTMS--a novel repetitive transcranial magnetic stimulation device with freely programmable stimulus currents.

PubMed

Gattinger, Norbert; Moessnang, Georg; Gleich, Bernhard

2012-07-01

Transcranial magnetic stimulation (TMS) is able to noninvasively excite neuronal populations due to brief magnetic field pulses. The efficiency and the characteristics of stimulation pulse shapes influence the physiological effect of TMS. However, commercial devices allow only a minimum of control of different pulse shapes. Basically, just sinusoidal and monophasic pulse shapes with fixed pulse widths are available. Only few research groups work on TMS devices with controllable pulse parameters such as pulse shape or pulse width. We describe a novel TMS device with a full-bridge circuit topology incorporating four insulated-gate bipolar transistor (IGBT) modules and one energy storage capacitor to generate arbitrary waveforms. This flexible TMS (flexTMS ) device can generate magnetic pulses which can be adjusted with respect to pulse width, polarity, and intensity. Furthermore, the equipment allows us to set paired pulses with a variable interstimulus interval (ISI) from 0 to 20 ms with a step size of 10  μs. All user-defined pulses can be applied continually with repetition rates up to 30 pulses per second (pps) or, respectively, up to 100 pps in theta burst mode. Offering this variety of flexibility, flexTMS will allow the enhancement of existing TMS paradigms and novel research applications.

Injection deep level transient spectroscopy: An improved method for measuring capture rates of hot carriers in semiconductors

DOE PAGES

Fleming, R. M.; Seager, C. H.; Lang, D. V.; ...

2015-07-02

In this study, an improved method for measuring the cross sections for carrier trapping at defects in semiconductors is described. This method, a variation of deep level transient spectroscopy(DLTS) used with bipolar transistors, is applied to hot carrier trapping at vacancy-oxygen, carbon-oxygen, and three charge states of divacancy centers (V 2) in n- and p-type silicon. Unlike standard DLTS, we fill traps by injecting carriers into the depletion region of a bipolar transistor diode using a pulse of forward bias current applied to the adjacent diode. We show that this technique is capable of accurately measuring a wide range ofmore » capture cross sections at varying electric fields due to the control of the carrier density it provides. Because this technique can be applied to a variety of carrier energy distributions, it should be valuable in modeling the effect of radiation-induced generation-recombination currents in bipolar devices.« less

Synaptic plasticity and oscillation at zinc tin oxide/silver oxide interfaces

NASA Astrophysics Data System (ADS)

Murdoch, Billy J.; McCulloch, Dougal G.; Partridge, James G.

2017-02-01

Short-term plasticity, long-term potentiation, and pulse interval dependent plasticity learning/memory functions have been observed in junctions between amorphous zinc-tin-oxide and silver-oxide. The same junctions exhibited current-controlled negative differential resistance and when connected in an appropriate circuit, they behaved as relaxation oscillators. These oscillators produced voltage pulses suitable for device programming. Transmission electron microscopy, energy dispersive X-ray spectroscopy, and electrical measurements suggest that the characteristics of these junctions arise from Ag+/O- electromigration across a highly resistive interface layer. With memory/learning functions and programming spikes provided in a single device structure, arrays of similar devices could be used to form transistor-free neuromorphic circuits.

Hybrid circuit achieves pulse regeneration with low power drain

NASA Technical Reports Server (NTRS)

Cancro, C. A.

1965-01-01

Hybrid tunnel diode-transistor circuit provides a solid-state, low power drain pulse regenerator, frequency limiter, or gated oscillator. When the feedback voltage exceeds the input voltage, the circuit functions as a pulse normalizer or a frequency limiter. If the circuit is direct coupled, it functions as a gated oscillator.

An Inexpensive Fast-Light Detector for Student Laboratories

ERIC Educational Resources Information Center

Sanders, Steven G.; and others

1969-01-01

An optical dectector consisting of a high-speed PIN diode and a transistor was evaluated for use in student experiments with a pulsed-ruby laser. Pulses with 36-nsec risetimes were clearly resolved. (LC)

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Integration of Organic Electrochemical and Field-Effect Transistors for Ultraflexible, High Temporal Resolution Electrophysiology Arrays.

PubMed

Lee, Wonryung; Kim, Dongmin; Rivnay, Jonathan; Matsuhisa, Naoji; Lonjaret, Thomas; Yokota, Tomoyuki; Yawo, Hiromu; Sekino, Masaki; Malliaras, George G; Someya, Takao

2016-11-01

Integration of organic electrochemical transistors and organic field-effect transistors is successfully realized on a 600 nm thick parylene film toward an electrophysiology array. A single cell of an integrated device and a 2 × 2 electrophysiology array succeed in detecting electromyogram with local stimulation of the motor nerve bundle of a transgenic rat by a laser pulse. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transistor-based interface circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2007-02-13

Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Determination of intrinsic mobility of a bilayer oxide thin-film transistor by pulsed I-V method

NASA Astrophysics Data System (ADS)

Woo, Hyunsuk; Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2017-04-01

Amorphous oxide semiconductor thin-film transistors (TFT) have been considered as outstanding switch devices owing to their high mobility. However, because of their amorphous channel material with a certain level of density of states, a fast transient charging effect in an oxide TFT occurs, leading to an underestimation of the mobility value. In this paper, the effects of the fast charging of high-performance bilayer oxide semiconductor TFTs on mobility are examined in order to determine an accurate mobility extraction method. In addition, an approach based on a pulse I D -V G measurement method is proposed to determine the intrinsic mobility value. Even with the short pulse I D -V G measurement, a certain level of fast transient charge trapping cannot be avoided as long as the charge-trap start time is shorter than the pulse rising time. Using a pulse-amplitude-dependent threshold voltage characterization method, we estimated a correction factor for the apparent mobility, thus allowing us to determine the intrinsic mobility.

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Deformable Organic Nanowire Field-Effect Transistors.

PubMed

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

InN thin-film transistors fabricated on polymer sheets using pulsed sputtering deposition at room temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lye, Khe Shin; Kobayashi, Atsushi; Ueno, Kohei

Indium nitride (InN) is potentially suitable for the fabrication of high performance thin-film transistors (TFTs) because of its high electron mobility and peak electron velocity. However, InN is usually grown using a high temperature growth process, which is incompatible with large-area and lightweight TFT substrates. In this study, we report on the room temperature growth of InN films on flexible polyimide sheets using pulsed sputtering deposition. In addition, we report on the fabrication of InN-based TFTs on flexible polyimide sheets and the operation of these devices.

Flexible Ionic-Electronic Hybrid Oxide Synaptic TFTs with Programmable Dynamic Plasticity for Brain-Inspired Neuromorphic Computing.

PubMed

John, Rohit Abraham; Ko, Jieun; Kulkarni, Mohit R; Tiwari, Naveen; Chien, Nguyen Anh; Ing, Ng Geok; Leong, Wei Lin; Mathews, Nripan

2017-08-01

Emulation of biological synapses is necessary for future brain-inspired neuromorphic computational systems that could look beyond the standard von Neuman architecture. Here, artificial synapses based on ionic-electronic hybrid oxide-based transistors on rigid and flexible substrates are demonstrated. The flexible transistors reported here depict a high field-effect mobility of ≈9 cm 2 V -1 s -1 with good mechanical performance. Comprehensive learning abilities/synaptic rules like paired-pulse facilitation, excitatory and inhibitory postsynaptic currents, spike-time-dependent plasticity, consolidation, superlinear amplification, and dynamic logic are successfully established depicting concurrent processing and memory functionalities with spatiotemporal correlation. The results present a fully solution processable approach to fabricate artificial synapses for next-generation transparent neural circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

NASA Astrophysics Data System (ADS)

He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

2017-04-01

In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

Programmable, automated transistor test system

NASA Technical Reports Server (NTRS)

Truong, L. V.; Sundburg, G. R.

1986-01-01

A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.

Trigger Circuit.

DTIC Science & Technology

A wire of Nitinol can be stretched up to a given amount and will remain in this stretched state until heated to a critical temperature. When heated...circuit of this invention provides a current pulse for the required time period to heat the Nitinol wire to its critical temperature to thereby restore the...wire to its original length. The circuit includes a high power transistor which is gated on for a controlled time to provide the required power to heat the Nitinol wire to its critical temperature. (Author)

Spectroscopic Studies of Lead Oxide in a Flow Tube.

DTIC Science & Technology

1984-12-03

anode current, 0.1 V/nA. The digital is a photon counting output giving square wave pulses for photons detected using Transistor Transitor Logic (TTL...Broida (17), and, Dorko and Ritchey (9; 21) are the only researchers to give a statistical analy- sis of their data. The data reported in this work and...The large number of bands (271) used in the calculations provides a good statistical average of the data. The con- stants for the D and E states are

High current, high bandwidth laser diode current driver

NASA Technical Reports Server (NTRS)

Copeland, David J.; Zimmerman, Robert K., Jr.

1991-01-01

A laser diode current driver has been developed for free space laser communications. The driver provides 300 mA peak modulation current and exhibits an optical risetime of less than 400 ps. The current and optical pulses are well behaved and show minimal ringing. The driver is well suited for QPPM modulation at data rates up to 440 Mbit/s. Much previous work has championed current steering circuits; in contrast, the present driver is a single-ended on/off switch. This results in twice the power efficiency as a current steering driver. The driver electrical efficiency for QPPM data is 34 percent. The high speed switch is realized with a Ku-band GaAsFET transistor, with a suitable pre-drive circuit, on a hybrid microcircuit adjacent to the laser diode.

Investigation of a pulsed current annealing method in reusing MOSFET dosimeters for in vivo IMRT dosimetry.

PubMed

Luo, Guang-Wen; Qi, Zhen-Yu; Deng, Xiao-Wu; Rosenfeld, Anatoly

2014-05-01

To explore the feasibility of pulsed current annealing in reusing metal oxide semiconductor field-effect transistor (MOSFET) dosimeters for in vivo intensity modulated radiation therapy (IMRT) dosimetry. Several MOSFETs were irradiated at d(max) using a 6 MV x-ray beam with 5 V on the gate and annealed with zero bias at room temperature. The percentage recovery of threshold voltage shift during multiple irradiation-annealing cycles was evaluated. Key dosimetry characteristics of the annealed MOSFET such as the dosimeter's sensitivity, reproducibility, dose linearity, and linearity of response within the dynamic range were investigated. The initial results of using the annealed MOSFETs for IMRT dosimetry practice were also presented. More than 95% of threshold voltage shift can be recovered after 24-pulse current continuous annealing in 16 min. The mean sensitivity degradation was found to be 1.28%, ranging from 1.17% to 1.52%, during multiple annealing procedures. Other important characteristics of the annealed MOSFET remained nearly consistent before and after annealing. Our results showed there was no statistically significant difference between the annealed MOSFETs and their control samples in absolute dose measurements for IMRT QA (p = 0.99). The MOSFET measurements agreed with the ion chamber results on an average of 0.16% ± 0.64%. Pulsed current annealing provides a practical option for reusing MOSFETs to extend their operational lifetime. The current annealing circuit can be integrated into the reader, making the annealing procedure fully automatic.

A 5 kA pulsed power supply for inductive and plasma loads in large volume plasma device.

PubMed

Srivastava, P K; Singh, S K; Sanyasi, A K; Awasthi, L M; Mattoo, S K

2016-07-01

This paper describes 5 kA, 12 ms pulsed power supply for inductive load of Electron Energy Filter (EEF) in large volume plasma device. The power supply is based upon the principle of rapid sourcing of energy from the capacitor bank (2.8 F/200 V) by using a static switch, comprising of ten Insulated Gate Bipolar Transistors (IGBTs). A suitable mechanism is developed to ensure equal sharing of current and uniform power distribution during the operation of these IGBTs. Safe commutation of power to the EEF is ensured by the proper optimization of its components and by the introduction of over voltage protection (>6 kV) using an indigenously designed snubber circuit. Various time sequences relevant to different actions of power supply, viz., pulse width control and repetition rate, are realized through optically isolated computer controlled interface.

A 5 kA pulsed power supply for inductive and plasma loads in large volume plasma device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Srivastava, P. K., E-mail: pkumar@ipr.res.in; Singh, S. K.; Sanyasi, A. K.

This paper describes 5 kA, 12 ms pulsed power supply for inductive load of Electron Energy Filter (EEF) in large volume plasma device. The power supply is based upon the principle of rapid sourcing of energy from the capacitor bank (2.8 F/200 V) by using a static switch, comprising of ten Insulated Gate Bipolar Transistors (IGBTs). A suitable mechanism is developed to ensure equal sharing of current and uniform power distribution during the operation of these IGBTs. Safe commutation of power to the EEF is ensured by the proper optimization of its components and by the introduction of over voltagemore » protection (>6 kV) using an indigenously designed snubber circuit. Various time sequences relevant to different actions of power supply, viz., pulse width control and repetition rate, are realized through optically isolated computer controlled interface.« less

Current control circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2005-03-15

Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Single event burnout sensitivity of embedded field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koga, R.; Crain, S.H.; Crawford, K.B.

Observations of single event burnout (SEB) in embedded field effect transistors are reported. Both SEB and other single event effects are presented for several pulse width modulation and high frequency devices. The microscope has been employed to locate and to investigate the damaged areas. A model of the damage mechanism based on the results so obtained is described.

Single event burnout sensitivity of embedded field effect transistors

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, S. H.; Crawford, K. B.; Yu, P.; Gordon, M. J.

1999-12-01

Observations of single event burnout (SEB) in embedded field effect transistors are reported. Both SEB and other single event effects are presented for several pulse width modulation and high frequency devices. The microscope has been employed to locate and to investigate the damaged areas. A model of the damage mechanism based on the results so obtained is described.

Novel ultrasensitive plasmonic detector of terahertz pulses enhanced by femtosecond optical pulses

NASA Astrophysics Data System (ADS)

Shur, M.; Rudin, S.; Rupper, G.; Muraviev, A.

2016-09-01

Plasmonic Field Effect Transistor detectors (first proposed in 1996) have emerged as superior room temperature terahertz (THz) detectors. Recent theoretical and experimental results showed that such detectors are capable of subpicosecond resolution. Their sensitivity can be greatly enhanced by applying the DC drain-to-source current that increases the responsivity due to the enhanced non-linearity of the device but also adds 1/f noise. We now propose, and demonstrate a dramatic responsivity enhancement of these plasmonic THz pulse detectors by applying a femtosecond optical laser pulse superimposed on the THz pulse. The proposed physical mechanism links the enhanced detection to the superposition of the THz pulse field and the rectified optical field. A femtosecond pulse generates a large concentration of the electron-hole pairs shorting the drain and source contacts and, therefore, determining the moment of time when the THz induced charge starts discharging into the transmission line connecting the FET to an oscilloscope. This allows for scanning the THz pulse with the strongly enhanced sensitivity and/or for scanning the response waveform after the THz pulse is over. The experimental results obtained using AlGaAs/InGaAs deep submicron HEMTs are in good agreement with this mechanism. This new technique could find numerous imaging, sensing, and quality control applications.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Design of power electronics for TVC EMA systems

NASA Technical Reports Server (NTRS)

Nelms, R. Mark

1993-01-01

The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Hsien; Chou, Wu-Ching, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw; Chang, Ting-Chang, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw

2014-10-21

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of themore » surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.« less

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE PAGES

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; ...

2014-11-26

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Analysis of the damage threshold of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

NASA Astrophysics Data System (ADS)

Xi, Xiao-Wen; Chai, Chang-Chun; Liu, Yang; Yang, Yin-Tang; Fan, Qing-Yang; Shi, Chun-Lei

2016-08-01

An electromagnetic pulse (EMP)-induced damage model based on the internal damage mechanism of the GaAs pseudomorphic high electron mobility transistor (PHEMT) is established in this paper. With this model, the relationships among the damage power, damage energy, pulse width and signal amplitude are investigated. Simulation results show that the pulse width index from the damage power formula obtained here is higher than that from the empirical formula due to the hotspot transferring in the damage process of the device. It is observed that the damage energy is not a constant, which decreases with the signal amplitude increasing, and then changes little when the signal amplitude reaches up to a certain level. Project supported by the National Basic Research Program of China (Grant No. 2014CB339900) and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (CAEP) (Grant No. 2015-0214.XY.K).

RADIATION-MEASURING SYSTEMS OF SOVIET ROCKETS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vakulov, P.V.; Goryunov, N.N.; Logachev, Yu.I.

1961-11-01

The second and third Sputniks and all Soviet space rockets and spaceship- satellites were equipped with radiationmeasuring systems comprising scintillation and gasdischarge counters and shaping, amplification, and scaling circuits. The scintillation counters use photomultipliers having either 40 x 40 Nal(Tl) or 20 x 20 Csl(Tl) cylindrical crystals. Both types have a gain of ~5.10/sup 4/. The highvoltage battery supplies voltages to the photomultipliers without the use of voltage dividers. Pulses from the 11th, 9th, and 8th dynodes are used for counting the number of particles which produce energy yields from the crystal exceeding ~50 and 500 kev and 5 Mev,more » respectively. Fourstage transistor amplifiers with an over-all gain of ~100 are used for amplification of the counting pulses. The trigger-discriminator, together with the amplifier, is capable of counting (2.5 -- 3.0) x 10/sup 5/ pulses/sec and of insuring a threshold stability of 10% at ambient temperatures of --30 to +50 deg C and voltage variations of plus or minus 20%. Ionization is measured from the current of the 7th dynode and the photomultiplier collector, which permits readings as low as 10/sup -10/ amp to be made by the method of charge storage (in the capacitor) with subsequent discharge through a neon tube. A gas-disoharge counter with 50 mg/cm/sup 2/ stainless-steel walls, operating at 400 v, also measures ionization. Before coming to the scaling circuit, the 50 v negative pulses from this counter pass through a transistor amplifier which changes their polarity and reduces their duration to 8 to 10 mu sec. (OTS)« less

A 7.8 kV nanosecond pulse generator with a 500 Hz repetition rate

NASA Astrophysics Data System (ADS)

Lin, M.; Liao, H.; Liu, M.; Zhu, G.; Yang, Z.; Shi, P.; Lu, Q.; Sun, X.

2018-04-01

Pseudospark switches are widely used in pulsed power applications. In this paper, we present the design and performance of a 500 Hz repetition rate high-voltage pulse generator to drive TDI-series pseudospark switches. A high-voltage pulse is produced by discharging an 8 μF capacitor through a primary windings of a setup isolation transformer using a single metal-oxide-semiconductor field-effect transistor (MOSFET) as a control switch. In addition, a self-break spark gap is used to steepen the pulse front. The pulse generator can deliver a high-voltage pulse with a peak trigger voltage of 7.8 kV, a peak trigger current of 63 A, a full width at half maximum (FWHM) of ~30 ns, and a rise time of 5 ns to the trigger pin of the pseudospark switch. During burst mode operation, the generator achieved up to a 500 Hz repetition rate. Meanwhile, we also provide an AC heater power circuit for heating a H2 reservoir. This pulse generator can be used in circuits with TDI-series pseudospark switches with either a grounded cathode or with a cathode electrically floating operation. The details of the circuits and their implementation are described in the paper.

Improved transistorized AC motor controller for battery powered urban electric passenger vehicles

NASA Technical Reports Server (NTRS)

Peak, S. C.

1982-01-01

An ac motor controller for an induction motor electric vehicle drive system was designed, fabricated, tested, evaluated, and cost analyzed. A vehicle performance analysis was done to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of ac motor and ac controller requirements. The power inverter is a three-phase bridge using power Darlington transistors. The induction motor was optimized for use with an inverter power source. The drive system has a constant torque output to base motor speed and a constant horsepower output to maximum speed. A gear shifting transmission is not required. The ac controller was scaled from the base 20 hp (41 hp peak) at 108 volts dec to an expanded horsepower and battery voltage range. Motor reversal was accomplished by electronic reversal of the inverter phase sequence. The ac controller can also be used as a boost chopper battery charger. The drive system was tested on a dynamometer and results are presented. The current-controlled pulse width modulation control scheme yielded improved motor current waveforms. The ac controller favors a higher system voltage.

Field-effect transistors as electrically controllable nonlinear rectifiers for the characterization of terahertz pulses

NASA Astrophysics Data System (ADS)

Lisauskas, Alvydas; Ikamas, Kestutis; Massabeau, Sylvain; Bauer, Maris; ČibiraitÄ--, DovilÄ--; Matukas, Jonas; Mangeney, Juliette; Mittendorff, Martin; Winnerl, Stephan; Krozer, Viktor; Roskos, Hartmut G.

2018-05-01

We propose to exploit rectification in field-effect transistors as an electrically controllable higher-order nonlinear phenomenon for the convenient monitoring of the temporal characteristics of THz pulses, for example, by autocorrelation measurements. This option arises because of the existence of a gate-bias-controlled super-linear response at sub-threshold operation conditions when the devices are subjected to THz radiation. We present measurements for different antenna-coupled transistor-based THz detectors (TeraFETs) employing (i) AlGaN/GaN high-electron-mobility and (ii) silicon CMOS field-effect transistors and show that the super-linear behavior in the sub-threshold bias regime is a universal phenomenon to be expected if the amplitude of the high-frequency voltage oscillations exceeds the thermal voltage. The effect is also employed as a tool for the direct determination of the speed of the intrinsic TeraFET response which allows us to avoid limitations set by the read-out circuitry. In particular, we show that the build-up time of the intrinsic rectification signal of a patch-antenna-coupled CMOS detector changes from 20 ps in the deep sub-threshold voltage regime to below 12 ps in the vicinity of the threshold voltage.

Polarization-mediated Debye-screening of surface potential fluctuations in dual-channel AlN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Deen, David A.; Miller, Ross A.; Osinsky, Andrei V.; Downey, Brian P.; Storm, David F.; Meyer, David J.; Scott Katzer, D.; Nepal, Neeraj

2016-12-01

A dual-channel AlN/GaN/AlN/GaN high electron mobility transistor (HEMT) architecture is proposed, simulated, and demonstrated that suppresses gate lag due to surface-originated trapped charge. Dual two-dimensional electron gas (2DEG) channels are utilized such that the top 2DEG serves as an equipotential that screens potential fluctuations resulting from surface trapped charge. The bottom channel serves as the transistor's modulated channel. Two device modeling approaches have been performed as a means to guide the device design and to elucidate the relationship between the design and performance metrics. The modeling efforts include a self-consistent Poisson-Schrodinger solution for electrostatic simulation as well as hydrodynamic three-dimensional device modeling for three-dimensional electrostatics, steady-state, and transient simulations. Experimental results validated the HEMT design whereby homo-epitaxial growth on free-standing GaN substrates and fabrication of the same-wafer dual-channel and recessed-gate AlN/GaN HEMTs have been demonstrated. Notable pulsed-gate performance has been achieved by the fabricated HEMTs through a gate lag ratio of 0.86 with minimal drain current collapse while maintaining high levels of dc and rf performance.

Probing the Quantum States of a Single Atom Transistor at Microwave Frequencies.

PubMed

Tettamanzi, Giuseppe Carlo; Hile, Samuel James; House, Matthew Gregory; Fuechsle, Martin; Rogge, Sven; Simmons, Michelle Y

2017-03-28

The ability to apply gigahertz frequencies to control the quantum state of a single P atom is an essential requirement for the fast gate pulsing needed for qubit control in donor-based silicon quantum computation. Here, we demonstrate this with nanosecond accuracy in an all epitaxial single atom transistor by applying excitation signals at frequencies up to ≈13 GHz to heavily phosphorus-doped silicon leads. These measurements allow the differentiation between the excited states of the single atom and the density of states in the one-dimensional leads. Our pulse spectroscopy experiments confirm the presence of an excited state at an energy ≈9 meV, consistent with the first excited state of a single P donor in silicon. The relaxation rate of this first excited state to the ground state is estimated to be larger than 2.5 GHz, consistent with theoretical predictions. These results represent a systematic investigation of how an atomically precise single atom transistor device behaves under radio frequency excitations.

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

Universal power transistor base drive control unit

DOEpatents

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Universal power transistor base drive control unit

DOEpatents

Gale, A.R.; Gritter, D.J.

1988-06-07

A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

Characterization of edge oscillation in a traveling-wave field-effect transistor.

PubMed

Narahara, Koichi

2013-07-01

In this study, we characterize the oscillating pulse edges developed in a traveling-wave field-effect transistor (TWFET). Recently, it has been found that a stable shock front can develop on a TWFET, which can travel in one direction only. Once the reflected pulse edge at the far end is transmitted to the input, the shock front develops and begins to travel on the device again. This process establishes a permanent edge oscillation. This paper discusses the device setup necessary to excite such oscillations and how pulse edges oscillate on a TWFET. By applying the phase reduction scheme to the transmission equations of a TWFET, we obtain phase sensitivity, which appropriately explains the measured spatial dependence of the locking range in frequency. Moreover, multiple oscillating edges can develop simultaneously, which are mutually synchronized. The dynamics of these multiple edges are also described.

Module failure isolation circuit for paralleled inverters. [preventing system failure during power conditioning for spacecraft applications

NASA Technical Reports Server (NTRS)

Nagano, S. (Inventor)

1979-01-01

A module failure isolation circuit is described which senses and averages the collector current of each paralled inverter power transistor and compares the collector current of each power transistor the average collector current of all power transistors to determine when the sensed collector current of a power transistor in any one inverter falls below a predetermined ratio of the average collector current. The module associated with any transistor that fails to maintain a current level above the predetermined radio of the average collector current is then shut off. A separate circuit detects when there is no load, or a light load, to inhibit operation of the isolation circuit during no load or light load conditions.

Chinese-English Automation and Computer Technology Dictionary. Volume I.

DTIC Science & Technology

1979-12-01

erjiguan dian- I-i ,f. transistored bridge 22 qiao bandaoti fangdaqi ’p ) semiconductor amplifier 23 bandaoti jiguangqi ’- ., semiconductor laser 24...semidefinite operator 21 banduchu maichong ’t: v half-read pulse 22 banduishu biaodu t L, N hIs semilogarithmic scale 23 banfanshu seminorm (math.) 24...semilinear 16 banxie maichong ’k half-write pulse ; 17 write half- pulse banxieru maichong ’p , half-write pulse 18 banxu kongjJan ’V ;’ J partially ordered

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Wan, Xiang; Shi, Yi; Wan, Qing

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Simulation of thermal management in AlGaN/GaN HEMTs with integrated diamond heat spreaders

NASA Astrophysics Data System (ADS)

Wang, A.; Tadjer, M. J.; Calle, F.

2013-05-01

We investigated the impact of diamond heat spreading layers on the performance of AlGaN/GaN high-electron-mobility-transistors (HEMTs). A finite element method was used to simulate the thermal and electrical characteristics of the devices under dc and pulsed operation conditions. The results show that the device performance can be improved significantly by optimized heat spreading, an effect strongly dependent on the lateral thermal conductivity of the initial several micrometers of diamond deposition. Of crucial importance is the proximity of the diamond layer to the heat source, which makes this method advantageous over other thermal management procedures, especially for the device in pulsed operation. In this case, the self-heating effect can be suppressed, and it is not affected by either the substrate or its thermal boundary resistance at the GaN/substrate at wider pulses. The device with a 5 µm diamond layer can present 10.5% improvement of drain current, and the self-heating effect can be neglected for a 100 ns pulse width at 1 V gate and 20 V drain voltage.

Streamers and their applications

NASA Astrophysics Data System (ADS)

Pemen, A. J. M.

2011-10-01

In this invited lecture we give an overview of our 15 years of experience on streamer plasma research. Efforts are directed to integrating the competence areas of plasma physics, pulsed power technology and chemical processing. The current status is the development of a large scale pulsed corona system for gas treatment. Applications on biogas conditioning, VOC removal, odor abatement and control of traffic emissions have been demonstrated. Detailed research on electrical and chemical processes resulted in a boost of efficiencies. Energy transfer efficiency to the plasma was raised to above 90%. Simultaneous improvement of the plasma chemistry resulted in a highly efficient radical generation: O-radical production up to 50% of the theoretical maximum has been achieved. A major challenge in pulsed power driven streamers is to unravel, understand and ultimately control the complex interactions between the transient plasma, electrical circuits, and process. Even more a challenge is to yield electron energies that fit activation energies of the process. We will discuss our ideas on adjusting pulsed power waveforms and plasma reactor settings to obtain more controlled catalytic processing: the ``Chemical Transistor'' concept.

Analysis of High Power IGBT Short Circuit Failures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pappas, G.

2005-02-11

The Next Linear Collider (NLC) accelerator proposal at SLAC requires a highly efficient and reliable, low cost, pulsed-power modulator to drive the klystrons. A solid-state induction modulator has been developed at SLAC to power the klystrons; this modulator uses commercial high voltage and high current Insulated Gate Bipolar Transistor (IGBT) modules. Testing of these IGBT modules under pulsed conditions was very successful; however, the IGBTs failed when tests were performed into a low inductance short circuit. The internal electrical connections of a commercial IGBT module have been analyzed to extract self and mutual partial inductances for the main current pathsmore » as well as for the gate structure. The IGBT module, together with the partial inductances, has been modeled using PSpice. Predictions for electrical paths that carry the highest current correlate with the sites of failed die under short circuit tests. A similar analysis has been carried out for a SLAC proposal for an IGBT module layout. This paper discusses the mathematical model of the IGBT module geometry and presents simulation results.« less

Systematic Destruction of Electronic Parts for Aid in Electronic Failure Analysis

NASA Technical Reports Server (NTRS)

Decker, S. E.; Rolin, T. D.; McManus, P. D.

2012-01-01

NASA analyzes electrical, electronic, and electromechanical (EEE) parts used in space vehicles to understand failure modes of these components. Operational amplifiers and transistors are two examples of EEE parts critical to NASA missions that can fail due to electrical overstress (EOS). EOS is the result of voltage or current over time conditions that exceeds a component s specification limit. The objective of this study was to provide known voltage pulses over well-defined time intervals to determine the type and extent of damage imparted to the device. The amount of current was not controlled but measured so that pulse energy was determined. The damage was ascertained electrically using curve trace plots and optically using various metallographic techniques. The resulting data can be used to build a database of physical evidence to compare to damaged components removed from flight avionics. The comparison will provide the avionics failure analyst necessary information about voltage and times that caused flight or test failures when no other electrical data is available.

Controllable pulse parameter transcranial magnetic stimulator with enhanced circuit topology and pulse shaping

NASA Astrophysics Data System (ADS)

Peterchev, Angel V.; DʼOstilio, Kevin; Rothwell, John C.; Murphy, David L.

2014-10-01

Objective. This work aims at flexible and practical pulse parameter control in transcranial magnetic stimulation (TMS), which is currently very limited in commercial devices. Approach. We present a third generation controllable pulse parameter device (cTMS3) that uses a novel circuit topology with two energy-storage capacitors. It incorporates several implementation and functionality advantages over conventional TMS devices and other devices with advanced pulse shape control. cTMS3 generates lower internal voltage differences and is implemented with transistors with a lower voltage rating than prior cTMS devices. Main results. cTMS3 provides more flexible pulse shaping since the circuit topology allows four coil-voltage levels during a pulse, including approximately zero voltage. The near-zero coil voltage enables snubbing of the ringing at the end of the pulse without the need for a separate active snubber circuit. cTMS3 can generate powerful rapid pulse sequences (\\lt 10 ms inter pulse interval) by increasing the width of each subsequent pulse and utilizing the large capacitor energy storage, allowing the implementation of paradigms such as paired-pulse and quadripulse TMS with a single pulse generation circuit. cTMS3 can also generate theta (50 Hz) burst stimulation with predominantly unidirectional electric field pulses. The cTMS3 device functionality and output strength are illustrated with electrical output measurements as well as a study of the effect of pulse width and polarity on the active motor threshold in ten healthy volunteers. Significance. The cTMS3 features could extend the utility of TMS as a research, diagnostic, and therapeutic tool.

Controllable pulse parameter transcranial magnetic stimulator with enhanced circuit topology and pulse shaping

PubMed Central

D’Ostilio, Kevin; Rothwell, John C; Murphy, David L

2014-01-01

Objective This work aims at flexible and practical pulse parameter control in transcranial magnetic stimulation (TMS), which is currently very limited in commercial devices. Approach We present a third generation controllable pulse parameter device (cTMS3) that uses a novel circuit topology with two energy-storage capacitors. It incorporates several implementation and functionality advantages over conventional TMS devices and other devices with advanced pulse shape control. cTMS3 generates lower internal voltage differences and is implemented with transistors with lower voltage rating than prior cTMS devices. Main results cTMS3 provides more flexible pulse shaping since the circuit topology allows four coil-voltage levels during a pulse, including approximately zero voltage. The near-zero coil voltage enables snubbing of the ringing at the end of the pulse without the need for a separate active snubber circuit. cTMS3 can generate powerful rapid pulse sequences (<10 ms inter pulse interval) by increasing the width of each subsequent pulse and utilizing the large capacitor energy storage, allowing the implementation of paradigms such as paired-pulse and quadripulse TMS with a single pulse generation circuit. cTMS3 can also generate theta (50 Hz) burst stimulation with predominantly unidirectional electric field pulses. The cTMS3 device functionality and output strength are illustrated with electrical output measurements as well as a study of the effect of pulse width and polarity on the active motor threshold in 10 healthy volunteers. Significance The cTMS3 features could extend the utility of TMS as a research, diagnostic, and therapeutic tool. PMID:25242286

Self-protecting transistor oscillator for treating animal tissues

DOEpatents

Doss, James D.

1980-01-01

A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

NASA Astrophysics Data System (ADS)

Sometani, Mitsuru; Okamoto, Mitsuo; Hatakeyama, Tetsuo; Iwahashi, Yohei; Hayashi, Mariko; Okamoto, Dai; Yano, Hiroshi; Harada, Shinsuke; Yonezawa, Yoshiyuki; Okumura, Hajime

2018-04-01

We investigated methods of measuring the threshold voltage (V th) shift of 4H-silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) under positive DC, negative DC, and AC gate bias stresses. A fast measurement method for V th shift under both positive and negative DC stresses revealed the existence of an extremely large V th shift in the short-stress-time region. We then examined the effect of fast V th shifts on drain current (I d) changes within a pulse under AC operation. The fast V th shifts were suppressed by nitridation. However, the I d change within one pulse occurred even in commercially available SiC MOSFETs. The correlation between I d changes within one pulse and V th shifts measured by a conventional method is weak. Thus, a fast and in situ measurement method is indispensable for the accurate evaluation of I d changes under AC operation.

A ZnO nanowire-based photo-inverter with pulse-induced fast recovery.

PubMed

Raza, Syed Raza Ali; Lee, Young Tack; Hosseini Shokouh, Seyed Hossein; Ha, Ryong; Choi, Heon-Jin; Im, Seongil

2013-11-21

We demonstrate a fast response photo-inverter comprised of one transparent gated ZnO nanowire field-effect transistor (FET) and one opaque FET respectively as the driver and load. Under ultraviolet (UV) light the transfer curve of the transparent gate FET shifts to the negative side and so does the voltage transfer curve (VTC) of the inverter. After termination of UV exposure the recovery of photo-induced current takes a long time in general. This persistent photoconductivity (PPC) is due to hole trapping on the surface of ZnO NWs. Here, we used a positive voltage short pulse after UV exposure, for the first time resolving the PPC issue in nanowire-based photo-detectors by accumulating electrons at the ZnO/dielectric interface. We found that a pulse duration as small as 200 ns was sufficient to reach a full recovery to the dark state from the UV induced state, realizing a fast UV detector with a voltage output.

Transistor circuit increases range of logarithmic current amplifier

NASA Technical Reports Server (NTRS)

Gilmour, G.

1966-01-01

Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

DTIC Science & Technology

2018-04-01

conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies of endorsements, either...applicability of the charge trap transistor (CTT) for embedded memory applications. Two case uses are considered (1) as a digital multi-time...28 Figure 38: (a) Weight-Dependent Plasticity when Five Trapping/Detrapping Pulses are applied in the LTD/LTP Regimes, respectively and (b

An analytic current-voltage model for quasi-ballistic III-nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Li, Kexin; Rakheja, Shaloo

2018-05-01

We present an analytic model to describe the DC current-voltage (I-V) relationship in scaled III-nitride high electron mobility transistors (HEMTs) in which transport within the channel is quasi-ballistic in nature. Following Landauer's transport theory and charge calculation based on two-dimensional electrostatics that incorporates negative momenta states from the drain terminal, an analytic expression for current as a function of terminal voltages is developed. The model interprets the non-linearity of access regions in non-self-aligned HEMTs. Effects of Joule heating with temperature-dependent thermal conductivity are incorporated in the model in a self-consistent manner. With a total of 26 input parameters, the analytic model offers reduced empiricism compared to existing GaN HEMT models. To verify the model, experimental I-V data of InAlN/GaN with InGaN back-barrier HEMTs with channel lengths of 42 and 105 nm are considered. Additionally, the model is validated against numerical I-V data obtained from DC hydrodynamic simulations of an unintentionally doped AlGaN-on-GaN HEMT with 50-nm gate length. The model is also verified against pulsed I-V measurements of a 150-nm T-gate GaN HEMT. Excellent agreement between the model and experimental and numerical results for output current, transconductance, and output conductance is demonstrated over a broad range of bias and temperature conditions.

High Speed and High Functional Inverter Power Supplies for Plasma Generation and Control, and their Performance

NASA Astrophysics Data System (ADS)

Uesugi, Yoshihiko; Razzak, Mohammad A.; Kondo, Kenji; Kikuchi, Yusuke; Takamura, Shuichi; Imai, Takahiro; Toyoda, Mitsuhiro

The Rapid development of high power and high speed semiconductor switching devices has led to their various applications in related plasma fields. Especially, a high speed inverter power supply can be used as an RF power source instead of conventional linear amplifiers and a power supply to control the magnetic field in a fusion plasma device. In this paper, RF thermal plasma production and plasma heating experiments are described emphasis placed on using a static induction transistor inverter at a frequency range between 200 kHz and 2.5 MHz as an RF power supply. Efficient thermal plasma production is achieved experimentally by using a flexible and easily operated high power semiconductor inverter power supply. Insulated gate bipolar transistor (IGBT) inverter power supplies driven by a high speed digital signal processor are applied as tokamak joule coil and vertical coil power supplies to control plasma current waveform and plasma equilibrium. Output characteristics, such as the arbitrary bipolar waveform generation of a pulse width modulation (PWM) inverter using digital signal processor (DSP) can be successfully applied to tokamak power supplies for flexible plasma current operation and fast position control of a small tokamak.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs).

PubMed

Kim, Choong-Ki; Kim, Eungtaek; Lee, Myung Keun; Park, Jun-Young; Seol, Myeong-Lok; Bae, Hagyoul; Bang, Tewook; Jeon, Seung-Bae; Jun, Sungwoo; Park, Sang-Hee K; Choi, Kyung Cheol; Choi, Yang-Kyu

2016-09-14

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.

Selective area deposited n-Al0.5Ga0.5N channel field effect transistors with high solar-blind ultraviolet photo-responsivity

NASA Astrophysics Data System (ADS)

Muhtadi, S.; Hwang, S.; Coleman, A.; Asif, F.; Lunev, A.; Chandrashekhar, M. V. S.; Khan, A.

2017-04-01

We report on AlGaN field effect transistors over AlN/sapphire templates with selective area grown n-Al0.5Ga0.5N channel layers for which a field-effect mobility of 55 cm2/V-sec was measured. Using a pulsed plasma enhanced chemical vapor deposition deposited 100 A thick SiO2 layer as the gate-insulator, the gate-leakage currents were reduced by three orders of magnitude. These devices with or without gate insulators are excellent solar-blind ultraviolet detectors, and they can be operated either in the photoconductive or the photo-voltaic modes. In the photo-conductive mode, gain arising from hole-trapping in the depletion region leads to steady-state photoresponsivity as high as 1.2 × 106A/W at 254 nm, which drops sharply below 290 nm. A hole-trapping limited detector response time of 34 ms, fast enough for real-time flame-detection and imaging applications, was estimated.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

PubMed

Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

2013-12-26

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2017-03-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks.

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

PubMed Central

Hu, C. Y.

2017-01-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks. PMID:28349960

Direct observation of electron emission and recombination processes by time domain measurements of charge pumping current

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hori, Masahiro, E-mail: hori@eng.u-toyama.ac.jp; Watanabe, Tokinobu; Ono, Yukinori

2015-01-26

To analyze the charge pumping (CP) sequence in detail, the source/drain electron current and the substrate hole current under the CP mode of transistors are simultaneously monitored in the time domain. Peaks are observed in both the electron and hole currents, which are, respectively, attributed to the electron emission from the interface defects and to the recombination with holes. The peak caused by the electron emission is found to consist of two components, strongly suggesting that the present time-domain measurement can enable us to resolve different kinds of interface defects. Investigating the correlation between the number of emitted and recombinedmore » electrons reveals that only one of the two components contributes to the CP current for the gate-pulse fall time from 6.25 × 10{sup −4} to 1.25 × 10{sup −2} s.« less

Advanced technology component derating

NASA Astrophysics Data System (ADS)

Jennings, Timothy A.

1992-02-01

A technical study performed to determine the derating criteria of advanced technology components is summarized. The study covered existing criteria from AFSC Pamphlet 800-27 and the development of new criteria based on data, literature searches, and the use of advanced technology prediction methods developed in RADC-TR-90-72. The devices that were investigated were as follows: VHSIC, ASIC, MIMIC, Microprocessor, PROM, Power Transistors, RF Pulse Transistors, RF Multi-Transistor Packages, Photo Diodes, Photo Transistors, Opto-Electronic Couplers, Injection Laser Diodes, LED, Hybrid Deposited Film Resistors, Chip Resistors, and Capacitors and SAW devices. The results of the study are additional derating criteria that extend the range of AFSC Pamphlet 800-27. These data will be transitioned from the report to AFSC Pamphlet 800-27 for use by government and contractor personnel in derating electronics systems yielding increased safety margins and improved system reliability.

Unified planar process for fabricating heterojunction bipolar transistors and buried-heterostructure lasers utilizing impurity-induced disordering

NASA Astrophysics Data System (ADS)

Thornton, R. L.; Mosby, W. J.; Chung, H. F.

1988-12-01

We describe results on a novel geometry of heterojunction bipolar transistor that has been realized by impurity-induced disordering. This structure is fabricated by a method that is compatible with techniques for the fabrication of low threshold current buried-heterostructure lasers. We have demonstrated this compatibility by fabricating a hybrid laser/transistor structure that operates as a laser with a threshold current of 6 mA at room temperature, and as a transistor with a current gain of 5.

Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

DOEpatents

Turner, Steven Richard

2006-12-26

A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

Morphological and crystalline characterization of pulsed laser deposited pentacene thin films for organic transistor applications

NASA Astrophysics Data System (ADS)

Pereira, Antonio; Bonhommeau, Sébastien; Sirotkin, Sergey; Desplanche, Sarah; Kaba, Mamadouba; Constantinescu, Catalin; Diallo, Abdou Karim; Talaga, David; Penuelas, Jose; Videlot-Ackermann, Christine; Alloncle, Anne-Patricia; Delaporte, Philippe; Rodriguez, Vincent

2017-10-01

We show that high-quality pentacene (P5) thin films of high crystallinity and low surface roughness can be produced by pulsed laser deposition (PLD) without inducing chemical degradation of the molecules. By using Raman spectroscopy and X-ray diffraction measurements, we also demonstrate that the deposition of P5 on Au layers result in highly disordered P5 thin films. While the P5 molecules arrange within the well-documented 1.54-nm thin-film phase on high-purity fused silica substrates, this ordering is indeed destroyed upon introducing an Au interlayer. This observation may be one explanation for the low electrical performances measured in P5-based organic thin film transistors (OTFTs) deposited by laser-induced forward transfer (LIFT).

All-optical switch and transistor gated by one stored photon.

PubMed

Chen, Wenlan; Beck, Kristin M; Bücker, Robert; Gullans, Michael; Lukin, Mikhail D; Tanji-Suzuki, Haruka; Vuletić, Vladan

2013-08-16

The realization of an all-optical transistor, in which one "gate" photon controls a "source" light beam, is a long-standing goal in optics. By stopping a light pulse in an atomic ensemble contained inside an optical resonator, we realized a device in which one stored gate photon controls the resonator transmission of subsequently applied source photons. A weak gate pulse induces bimodal transmission distribution, corresponding to zero and one gate photons. One stored gate photon produces fivefold source attenuation and can be retrieved from the atomic ensemble after switching more than one source photon. Without retrieval, one stored gate photon can switch several hundred source photons. With improved storage and retrieval efficiency, our work may enable various new applications, including photonic quantum gates and deterministic multiphoton entanglement.

Instrument for measuring dispersional distortions in optical fibers and cables

NASA Astrophysics Data System (ADS)

Alishev, Y. V.; Maryenko, A. A.; Smirnov, Y. V.; Uryadov, V. N.; Sinkevich, V. I.

1985-03-01

An instrument was developed and built for measuring the dispersional distortions in optical fibers and cables on the basis of pulse widening. The instrument consists of a laser as a light source, a master oscillator, an optical transmitter, an optical shunt with mode mixer, an optical receiver, a fiber length measuring device, a smoothly adjustable delay line, and a stroboscopic oscillograph. The optical transmitter contains a semiconductor laser with GaAs-GaAlAs diheterostructure and modulator with pulse generating avalanche-breakdown transistors. The optical receiver contains a germanium photodiode with internal amplification and photoreceiver amplifier with microwave bipolar germanium transistors. Matching of the instrument to the tested fiber line is done by passing radiation into the latter from an auxiliary small He-Ne laser through a directional coupler.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

PubMed Central

Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

2016-01-01

The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP. PMID:27924838

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moto, Kenta; Sadoh, Taizoh; Miyao, Masanobu, E-mail: miyao@ed.kyushu-u.ac.jp

Crystalline GeSn-on-insulator structures with high Sn concentration (>8%), which exceeds thermal equilibrium solid-solubility (∼2%) of Sn in Ge, are essential to achieve high-speed thin film transistors and high-efficiency optical devices. We investigate non-thermal equilibrium growth of Ge{sub 1−x}Sn{sub x} (0 ≤ x ≤ 0.2) on quartz substrates by using pulsed laser annealing (PLA). The window of laser fluence enabling complete crystallization without film ablation is drastically expanded (∼5 times) by Sn doping above 5% into Ge. Substitutional Sn concentration in grown layers is found to be increased with decreasing irradiation pulse number. This phenomenon can be explained on the basis of significant thermal non-equilibriummore » growth achieved by higher cooling rate after PLA with a lower pulse number. As a result, GeSn crystals with substitutional Sn concentration of ∼12% are realized at pulse irradiation of single shot for the samples with the initial Sn concentration of 15%. Raman spectroscopy and electron microscopy measurements reveal the high quality of the grown layer. This technique will be useful to fabricate high-speed thin film transistors and high-efficiency optical devices on insulating substrates.« less

Development of a novel low frequency GPR system for ultra-deep detection in Mine

NASA Astrophysics Data System (ADS)

Xu, Xianlei; Peng, Suping; Yang, Feng

2016-04-01

Mine disasters sources is the main source of the underground coal mine accidents in China. This paper describes the development of a novel explosion proof ground penetrating radar (GPR) for mine disasters sources detection, aiming to solve the current problems of the small detection range and low precision in the mine advanced detection in China. A high performance unipolar pulse transmitting unit is developed by using avalanche transistors, and an effective pulse excitation source network. And a new pluggable combined low-frequency antenna involving three frequencies with 12.5MHz, 25 MHz and 50MHz, is designed and developed. The plate-type structure is designed, aiming to enhance the directivity of the antenna, and the achievement of the antenna impedance matching is implemented in the feed point based on the extensions interface design, enhancing the antenna bandwidth and reducing the standing wave interference. Moreover, a high precision stepper delay circuit is designed by transforming the number of the operational amplifier step and using the differential compensation between the metal-oxide semiconductor field effect transistors, aiming to improve the accuracy of the signal acquisition system. In order to adapt to the mine environment, the explosion-proof design is implemented for the GPR system, including the host, transmitter, receiver, battery box, antenna, and other components.Mine detection experiments is carried out and the results show: the novel GPR system can effectively detect the location and depth of the geological disasters source with the depth greater than30 m and the diameter greater than 3m, the maximum detection depth can be up to 80m, which break the current detection depth limitations within 30m, providing an effective technical support for the ultra-deep mine disasters detection and the safety problems in coal mine production.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Thermal transistor utilizing gas-liquid transition.

PubMed

Komatsu, Teruhisa S; Ito, Nobuyasu

2011-01-01

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter.

Solid-state pulse modulator using Marx generator for a medical linac electron-gun

NASA Astrophysics Data System (ADS)

Lim, Heuijin; Hyeok Jeong, Dong; Lee, Manwoo; Lee, Mujin; Yi, Jungyu; Yang, Kwangmo; Ro, Sung Chae

2016-04-01

A medical linac is used for the cancer treatment and consists of an accelerating column, waveguide components, a magnetron, an electron-gun, a pulse modulator, and an irradiation system. The pulse modulator based on hydrogen thyratron-switched pulse-forming network is commonly used in linac. As the improvement of the high power semiconductors in switching speed, voltage rating, and current rating, an insulated gate bipolar transistor has become the more popular device used for pulsed power systems. We propose a solid-state pulse modulator to generator high voltage by multi-stacked storage-switch stages based on the Marx generator. The advantage of our modulator comes from the use of two semiconductors to control charging and discharging of the storage capacitor at each stage and it allows to generate the pulse with various amplitudes, widths, and shapes. In addition, a gate driver for two semiconductors is designed to reduce the control channels and to protect the circuits. It is developed for providing the pulsed power to a medical linac electron-gun that requires 25 kV and 1 A as the first application. In order to improve the power efficiency and achieve the compactness modulator, a capacitor charging power supply, a Marx pulse generator, and an electron-gun heater isolated transformer are constructed and integrated. This technology is also being developed to extend the high power pulsed system with > 1 MW and also other applications such as a plasma immersed ion implantation and a micro pulse electrostatic precipitator which especially require variable pulse shape and high repetition rate > 1 kHz. The paper describes the design features and the construction of this solid-state pulse modulator. Also shown are the performance results into the linac electron-gun.

A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems.

PubMed

Park, Sung-Yun; Cho, Jihyun; Lee, Kyuseok; Yoon, Euisik

2015-12-01

We report a pulse width modulation (PWM) buck converter that is able to achieve a power conversion efficiency (PCE) of > 80% in light loads 100 μA) for implantable biomedical systems. In order to achieve a high PCE for the given light loads, the buck converter adaptively reconfigures the size of power PMOS and NMOS transistors and their gate drivers in accordance with load currents, while operating at a fixed frequency of 1 MHz. The buck converter employs the analog-digital hybrid control scheme for coarse/fine adjustment of power transistors. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average of duty cycles for the given load condition from limit cycle oscillations (LCO) induced by coarse adjustment. The fabricated buck converter achieved a peak efficiency of 86.3% at 1.4 mA and > 80% efficiency for a wide range of load conditions from 45 μA to 4.1 mA, while generating 1 V output from 2.5-3.3 V supply. The converter occupies 0.375 mm(2) in 0.18 μm CMOS processes and requires two external components: 1.2 μF capacitor and 6.8 μH inductor.

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

NASA Technical Reports Server (NTRS)

Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

1981-01-01

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Analytical design equations for self-tuned Class-E power amplifier.

PubMed

Hu, Zhe; Troyk, Philip

2011-01-01

For many emerging neural prosthesis designs that are powered by inductive coupling, their small physical size requires large current in the extracorporeal transmitter coil, and the Class-E power amplifier topology is often used for the transmitter design. Tuning of Class-E circuits for efficient operation is difficult and a self-tuned circuit can facilitate the tuning. The coil current is sensed and used to tune the switching of the transistor switch in the Class-E circuit in order to maintain its high-efficiency operation. Although mathematically complex, the analysis and design procedure for the self-tuned Class-E circuit can be simplified due to the current feedback control, which makes the phase angle between the switching pulse and the coil current predetermined. In this paper explicit analytical design equations are derived and a detailed design procedure is presented and compared with the conventional Class-E design approaches.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

NASA Astrophysics Data System (ADS)

Jin, Liu; Yongguang, Chen; Zhiliang, Tan; Jie, Yang; Xijun, Zhang; Zhenxing, Wang

2011-10-01

Electrostatic discharge (ESD) phenomena involve both electrical and thermal effects, and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability. Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors (BJTs) under ESD conditions has been investigated theoretically and experimentally. 100 samples have been tested for multiple pulses until a failure occurred. Meanwhile, the distributions of electric field, current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici. There is a good agreement between the simulated results and failure analysis. In the case of a thermal couple, the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects. The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure. When the ESD level increased to 1.3 kV, the collector-base junction has been burnt out first. The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic. In addition, fatigue phenomena are observed during ESD testing, with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.

Automatic load sharing in inverter modules

NASA Technical Reports Server (NTRS)

Nagano, S.

1979-01-01

Active feedback loads transistor equally with little power loss. Circuit is suitable for balancing modular inverters in spacecraft, computer power supplies, solar-electric power generators, and electric vehicles. Current-balancing circuit senses differences between collector current for power transistor and average value of load currents for all power transistors. Principle is effective not only in fixed duty-cycle inverters but also in converters operating at variable duty cycles.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Rapid detection of cardiac troponin I using antibody-immobilized gate-pulsed AlGaN/GaN high electron mobility transistor structures

NASA Astrophysics Data System (ADS)

Yang, Jiancheng; Carey, Patrick; Ren, Fan; Wang, Yu-Lin; Good, Michael L.; Jang, Soohwan; Mastro, Michael A.; Pearton, S. J.

2017-11-01

We report a comparison of two different approaches to detecting cardiac troponin I (cTnI) using antibody-functionalized AlGaN/GaN High Electron Mobility Transistors (HEMTs). If the solution containing the biomarker has high ionic strength, there can be difficulty in detection due to charge-screening effects. To overcome this, in the first approach, we used a recently developed method involving pulsed biases applied between a separate functionalized electrode and the gate of the HEMT. The resulting electrical double layer produces charge changes which are correlated with the concentration of the cTnI biomarker. The second approach fabricates the sensing area on a glass slide, and the pulsed gate signal is externally connected to the nitride HEMT. This produces a larger integrated change in charge and can be used over a broader range of concentrations without suffering from charge-screening effects. Both approaches can detect cTnI at levels down to 0.01 ng/ml. The glass slide approach is attractive for inexpensive cartridge-type sensors.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Hardware realization of an SVM algorithm implemented in FPGAs

NASA Astrophysics Data System (ADS)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz.

PubMed

Cao, Yu; Brady, Gerald J; Gui, Hui; Rutherglen, Chris; Arnold, Michael S; Zhou, Chongwu

2016-07-26

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

A Novel Low-Ringing Monocycle Picosecond Pulse Generator Based on Step Recovery Diode

PubMed Central

Zhou, Jianming; Yang, Xiao; Lu, Qiuyuan; Liu, Fan

2015-01-01

This paper presents a high-performance low-ringing ultra-wideband monocycle picosecond pulse generator, formed using a step recovery diode (SRD), simulated in ADS software and generated through experimentation. The pulse generator comprises three parts, a step recovery diode, a field-effect transistor and a Schottky diode, used to eliminate the positive and negative ringing of pulse. Simulated results validate the design. Measured results indicate an output waveform of 1.88 peak-to-peak amplitude and 307ps pulse duration with a minimal ringing of -22.5 dB, providing good symmetry and low level of ringing. A high degree of coordination between the simulated and measured results is achieved. PMID:26308450

Optically transparent thin-film transistors based on 2D multilayer MoS₂ and indium zinc oxide electrodes.

PubMed

Kwon, Junyeon; Hong, Young Ki; Kwon, Hyuk-Jun; Park, Yu Jin; Yoo, Byungwook; Kim, Jiwan; Grigoropoulos, Costas P; Oh, Min Suk; Kim, Sunkook

2015-01-21

We report on optically transparent thin film transistors (TFTs) fabricated using multilayered molybdenum disulfide (MoS2) as the active channel, indium tin oxide (ITO) for the back-gated electrode and indium zinc oxide (IZO) for the source/drain electrodes, respectively, which showed more than 81% transmittance in the visible wavelength. In spite of a relatively large Schottky barrier between MoS2 and IZO, the n-type behavior with a field-effect mobility (μ(eff)) of 1.4 cm(2) V(-1) s(-1) was observed in as-fabricated transparent MoS2 TFT. In order to enhance the performances of transparent MoS2 TFTs, a picosecond pulsed laser was selectively irradiated onto the contact region of the IZO electrodes. Following laser annealing, μ(eff) increased to 4.5 cm(2) V(-1) s(-1), and the on-off current ratio (I(on)/I(off)) increased to 10(4), which were attributed to the reduction of the contact resistance between MoS2 and IZO.

Periodically pulsed wet annealing approach for low-temperature processable amorphous InGaZnO thin film transistors with high electrical performance and ultrathin thickness

PubMed Central

Kim, Ye Kyun; Ahn, Cheol Hyoun; Yun, Myeong Gu; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun

2016-01-01

In this paper, a simple and controllable “wet pulse annealing” technique for the fabrication of flexible amorphous InGaZnO thin film transistors (a-IGZO TFTs) processed at low temperature (150 °C) by using scalable vacuum deposition is proposed. This method entailed the quick injection of water vapor for 0.1 s and purge treatment in dry ambient in one cycle; the supply content of water vapor was simply controlled by the number of pulse repetitions. The electrical transport characteristics revealed a remarkable performance of the a-IGZO TFTs prepared at the maximum process temperature of 150 °C (field-effect mobility of 13.3 cm2 V−1 s−1; Ion/Ioff ratio ≈ 108; reduced I-V hysteresis), comparable to that of a-IGZO TFTs annealed at 350 °C in dry ambient. Upon analysis of the angle-resolved x-ray photoelectron spectroscopy, the good performance was attributed to the effective suppression of the formation of hydroxide and oxygen-related defects. Finally, by using the wet pulse annealing process, we fabricated, on a plastic substrate, an ultrathin flexible a-IGZO TFT with good electrical and bending performances. PMID:27198067

Periodically pulsed wet annealing approach for low-temperature processable amorphous InGaZnO thin film transistors with high electrical performance and ultrathin thickness.

PubMed

Kim, Ye Kyun; Ahn, Cheol Hyoun; Yun, Myeong Gu; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun

2016-05-20

In this paper, a simple and controllable "wet pulse annealing" technique for the fabrication of flexible amorphous InGaZnO thin film transistors (a-IGZO TFTs) processed at low temperature (150 °C) by using scalable vacuum deposition is proposed. This method entailed the quick injection of water vapor for 0.1 s and purge treatment in dry ambient in one cycle; the supply content of water vapor was simply controlled by the number of pulse repetitions. The electrical transport characteristics revealed a remarkable performance of the a-IGZO TFTs prepared at the maximum process temperature of 150 °C (field-effect mobility of 13.3 cm(2) V(-1) s(-1); Ion/Ioff ratio ≈ 10(8); reduced I-V hysteresis), comparable to that of a-IGZO TFTs annealed at 350 °C in dry ambient. Upon analysis of the angle-resolved x-ray photoelectron spectroscopy, the good performance was attributed to the effective suppression of the formation of hydroxide and oxygen-related defects. Finally, by using the wet pulse annealing process, we fabricated, on a plastic substrate, an ultrathin flexible a-IGZO TFT with good electrical and bending performances.

Effect of Pulse and dc Formation on the Performance of One-Transistor and One-Resistor Resistance Random Access Memory Devices

NASA Astrophysics Data System (ADS)

Liu, Hong-Tao; Yang, Bao-He; Lv, Hang-Bing; Xu, Xiao-Xin; Luo, Qing; Wang, Guo-Ming; Zhang, Mei-Yun; Long, Shi-Bing; Liu, Qi; Liu, Ming

2015-02-01

We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor (1T1R) resistance random access memory (RRAM) device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state (HRS) under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament (CF) formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state (LRS) can be easily changed by removing a few trapping states from the conducting path. Hence, a higher HRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

DIRECT COUPLED AMPLIFIER

DOEpatents

Dandl, R.A.

1961-09-19

A transistor amplifier is designed for vyery small currents below 10/sup -8/ amperes. The filrst and second amplifier stages use unusual selected transistors in which the current amplification increases markedly for values of base current below 10/sup -6/ amperes.

Pulse-burst laser systems for fast Thomson scattering (invited)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Den Hartog, D. J.; Center for Magnetic Self-Organization in Laboratory and Astrophysical Plasmas, University of Wisconsin-Madison, Madison, Wisconsin 53706; Ambuel, J. R.

2010-10-15

Two standard commercial flashlamp-pumped Nd:YAG (YAG denotes yttrium aluminum garnet) lasers have been upgraded to ''pulse-burst'' capability. Each laser produces a burst of up to 15 2 J Q-switched pulses (1064 nm) at repetition rates of 1-12.5 kHz. Variable pulse-width drive (0.15-0.39 ms) of the flashlamps is accomplished by insulated gate bipolar transistor (IGBT) switching of electrolytic capacitor banks. Direct control of the laser Pockels cell drive enables optimal pulse energy extraction, and up to four 2 J laser pulses during one flashlamp pulse. These lasers are used in the Thomson scattering plasma diagnostic system on the MST reversed-field pinchmore » to record the dynamic evolution of the electron temperature profile and temperature fluctuations. To further these investigations, a custom pulse-burst laser system with a maximum pulse repetition rate of 250 kHz is now being commissioned.« less

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Highly Sensitive Flexible Pressure Sensors Based on Printed Organic Transistors with Centro-Apically Self-Organized Organic Semiconductor Microstructures.

PubMed

Yeo, So Young; Park, Sangsik; Yi, Yeon Jin; Kim, Do Hwan; Lim, Jung Ah

2017-12-13

A highly sensitive pressure sensor based on printed organic transistors with three-dimensionally self-organized organic semiconductor microstructures (3D OSCs) was demonstrated. A unique organic transistor with semiconductor channels positioned at the highest summit of printed cylindrical microstructures was achieved simply by printing an organic semiconductor and polymer blend on the plastic substrate without the use of additional etching or replication processes. A combination of the printed organic semiconductor microstructure and an elastomeric top-gate dielectric resulted in a highly sensitive organic field-effect transistor (FET) pressure sensor with a high pressure sensitivity of 1.07 kPa -1 and a rapid response time of <20 ms with a high reliability over 1000 cycles. The flexibility and high performance of the 3D OSC FET pressure sensor were exploited in the successful application of our sensors to real-time monitoring of the radial artery pulse, which is useful for healthcare monitoring, and to touch sensing in the e-skin of a realistic prosthetic hand.

Development, Fabrication, and Testing of Inverter Power System for Metroliner

DOT National Transportation Integrated Search

1979-11-01

This report documents the development and subsequent fabrication of a solid state auxiliary power conditioning unit (APCU) for the upgraded Metroliner. The APCU is an inverter of the pulse width modulated type having multiple parallel transistors in ...

Pulsed hybrid dual wavelength Y-branch-DFB laser-tapered amplifier system suitable for water vapor detection at 965 nm with 16 W peak power

NASA Astrophysics Data System (ADS)

Vu, Thi N.; Klehr, Andreas; Sumpf, Bernd; Hoffmann, Thomas; Liero, Armin; Tränkle, Günther

2016-03-01

A master oscillator power amplifier system emitting alternatingly at two neighbored wavelengths around 965 nm is presented. As master oscillator (MO) a Y-branch DFB-laser is used. The two branches, which can be individually controlled, deliver the two wavelengths needed for a differential absorption measurement of water vapor. Adjusting the current through the DFB sections, the wavelength can be adjusted with respect to the targeted either "on" or "off" resonance, respectively wavelength λon or wavelength λoff. The emission of this laser is amplified in a tapered amplifier (TA). The ridge waveguide section of the TA acts as optical gate to generate short pulses with duration of 8 ns at a repetition rate of 25 kHz, the flared section is used for further amplification to reach peak powers up to 16 W suitable for micro-LIDAR (Light Detection and Ranging). The necessary pulse current supply user a GaN-transistor based driver electronics placed close to the power amplifier (PA). The spectral properties of the emission of the MO are preserved by the PA. A spectral line width smaller than 10 pm and a side mode suppression ratio (SMSR) of 37 dB are measured. These values meet the demands for water vapor absorption measurements under atmospheric conditions.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

STABILIZED TRANSISTOR AMPLIFIER

DOEpatents

Noe, J.B.

1963-05-01

A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

Over 0.5 MW green laser from sub-nanosecond giant pulsed microchip laser

NASA Astrophysics Data System (ADS)

Zheng, Lihe; Taira, Takunori

2016-03-01

A sub-nanosecond green laser with laser head sized 35 × 35 × 35 mm3 was developed from a giant pulsed microchip laser for laser processing on organic superconducting transistor with a flexible substrate. A composite monolithic Y3Al5O12 (YAG) /Nd:YAG/Cr4+:YAG/YAG crystal was designed for generating giant pulsed 1064 nm laser. A fibercoupled 30 W laser diode centered at 808 nm was used with pump pulse duration of 245 μs. The 532 nm green laser was obtained from a LiB3O5 (LBO) crystal with output energy of 150 μJ and pulse duration of 268 ps. The sub-nanosecond green laser is interesting for 2-D ablation patterns.

Tunneling modulation of a quantum-well transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Qiu, J.; Wang, C. Y.; Holonyak, N.

2016-11-01

Different than the Bardeen and Brattain transistor (1947) with the current gain depending on the ratio of the base carrier spontaneous recombination lifetime to the emitter-collector transit time, the Feng and Holonyak transistor laser current gain depends upon the base electron-hole (e-h) stimulated recombination, the base dielectric relaxation transport, and the collector stimulated tunneling. For the n-p-n transistor laser tunneling operation, the electron-hole pairs are generated at the collector junction under the influence of intra-cavity photon-assisted tunneling, with electrons drifting to the collector and holes drifting to the base. The excess charge in the base lowers the emitter junction energy barrier, allowing emitter electron injection into the base and satisfying charge neutrality via base dielectric relaxation transport (˜femtoseconds). The excess electrons near the collector junction undergo stimulated recombination at the base quantum-well or transport to the collector, thus supporting tunneling current amplification and optical modulation of the transistor laser.

Persistent photocurrent and deep level traps in PLD-grown In-Ga-Zn-O thin films studied by thermally stimulated current spectroscopy

NASA Astrophysics Data System (ADS)

Wang, Buguo; Anders, Jason; Leedy, Kevin; Schuette, Michael; Look, David

2018-02-01

InGaZnO (IGZO) is a promising semiconductor material for thin-film transistors (TFTs) used in DC and RF switching applications, especially since it can be grown at low temperatures on a wide variety of substrates. Enhancement-mode TFTs based on IGZO thin films grown by pulsed laser deposition (PLD) have been recently fabricated and these transistors show excellent performance; however, compositional variations and defects can adversely affect film quality, especially in regard to electrical properties. In this study, we use thermally stimulated current (TSC) spectroscopy to characterize the electrical properties and the deep traps in PLD-grown IGZO thin films. It was found that the as-grown sample has a DC activation energy of 0.62 eV, and two major traps with activation energies at 0.16-0.26 eV and at 0.90 eV. However, a strong persistent photocurrent (PPC) sometimes exists in the as-grown sample, so we carry out post-growth annealing in an attempt to mitigate the effect. It was found that annealing in argon increases the conduction, produces more PPC and also makes more traps observable. Annealing in air makes the film more resistive, and removes PPC and all traps but one. This work demonstrates that current-based trap emission, such as that associated with the TSC, can effectively reveal electronic defects in highlyresistive semiconductor materials, especially those are not amenable to capacitance-based techniques, such as deeplevel transient spectroscopy (DLTS).

Elimination of current spikes in buck power converters

NASA Technical Reports Server (NTRS)

Mclyman, W. T. (Inventor)

1981-01-01

Current spikes in a buck power converter due to commutating diode turn-off time are eliminated by using a tapped inductor in the converter with the tap connected to the switching transistor. The commutating diode is not in the usual place, but is instead connected to conduct current from one end of the tapped inductor remote from the load during the interval in which the transistor is not conducting. In the case of a converter having a center-tapped (primary and secondary) transformer between two switching power transistors operated in a push-pull mode and two rectifying diodes in the secondary circuit, current spikes due to transformer saturation are also eliminated by using a tapped inductor in the converter with the tap connected to the rectifying diodes and a diode connected to conduct current from one end of the tapped inductor remote from the load during the interval in which the transistors are not conducting.

The fabrication and optical detection of a vertical structure organic thin film transistor

NASA Astrophysics Data System (ADS)

Zhang, H.; Wang, D.; Jia, P.

2014-03-01

Using vacuum evaporation and sputtering process, we prepared a photoelectric transistor with the vertical structure of Cu/copper phthalocyanine (CuPc)/Al/copper phthalocyanine (CuPc)/ITO. The material of CuPc semiconductor has good photosensitive properties. Excitons will be generated after the optical signal irradiation in semiconductor material, and then transformed into photocurrent under the built-in electric field formed by the Schottky contact, as the organic transistor drive current makes the output current enlarged. The results show that the I-V characteristics of transistor are unsaturated. When device was irradiated by full band (white) light, its working current significantly increased. In full band white light, when Vec = 3 V, the ratio of light and no light current was ranged for 2.9-6.4 times. Device in the absence of light current amplification coefficient is 16.5, and white light amplification coefficient is 98.65.

High current gain transistor laser

PubMed Central

Liang, Song; Qiao, Lijun; Zhu, Hongliang; Wang, Wei

2016-01-01

A transistor laser (TL), having the structure of a transistor with multi-quantum wells near its base region, bridges the functionality gap between lasers and transistors. However, light emission is produced at the expense of current gain for all the TLs reported up to now, leading to a very low current gain. We propose a novel design of TLs, which have an n-doped InP layer inserted in the emitter ridge. Numerical studies show that a current flow aperture for only holes can be formed in the center of the emitter ridge. As a result, the common emitter current gain can be as large as 143.3, which is over 15 times larger than that of a TL without the aperture. Besides, the effects of nonradiative recombination defects can be reduced greatly because the flow of holes is confined in the center region of the emitter ridge. PMID:27282466

Wireless Passive Stimulation of Engineered Cardiac Tissues.

PubMed

Liu, Shiyi; Navaei, Ali; Meng, Xueling; Nikkhah, Mehdi; Chae, Junseok

2017-07-28

We present a battery-free radio frequency (RF) microwave activated wireless stimulator, 25 × 42 × 1.6 mm 3 on a flexible substrate, featuring high current delivery, up to 60 mA, to stimulate engineered cardiac tissues. An external antenna shines 2.4 GHz microwave, which is modulated by an inverted pulse to directly control the stimulating waveform, to the wireless passive stimulator. The stimulator is equipped with an on-board antenna, multistage diode multipliers, and a control transistor. Rat cardiomyocytes, seeded on electrically conductive gelatin-based hydrogels, demonstrate synchronous contractions and Ca 2+ transients immediately upon stimulation. Notably, the stimulator output voltage and current profiles match the tissue contraction frequency within 0.5-2 Hz. Overall, our results indicate the promising potential of the proposed wireless passive stimulator for cardiac stimulation and therapy by induction of precisely controlled and synchronous contractions.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

PubMed

Cao, Xuan; Wu, Fanqi; Lau, Christian; Liu, Yihang; Liu, Qingzhou; Zhou, Chongwu

2017-02-28

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼10 5 , low-voltage operation, and good mobility of ∼15.03 cm 2 V -1 s -1 . These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

High voltage electrical amplifier having a short rise time

DOEpatents

Christie, David J.; Dallum, Gregory E.

1991-01-01

A circuit, comprising an amplifier and a transformer is disclosed that produces a high power pulse having a fast response time, and that responds to a digital control signal applied through a digital-to-analog converter. The present invention is suitable for driving a component such as an electro-optic modulator with a voltage in the kilovolt range. The circuit is stable at high frequencies and during pulse transients, and its impedance matching circuit matches the load impedance with the output impedance. The preferred embodiment comprises an input stage compatible with high-speed semiconductor components for amplifying the voltage of the input control signal, a buffer for isolating the input stage from the output stage; and a plurality of current amplifiers connected to the buffer. Each current amplifier is connected to a field effect transistor (FET), which switches a high voltage power supply to a transformer which then provides an output terminal for driving a load. The transformer comprises a plurality of transmission lines connected to the FETs and the load. The transformer changes the impedance and voltage of the output. The preferred embodiment also comprises a low voltage power supply for biasing the FETs at or near an operational voltage.

Charging the quantum capacitance of graphene with a single biological ion channel.

PubMed

Wang, Yung Yu; Pham, Ted D; Zand, Katayoun; Li, Jinfeng; Burke, Peter J

2014-05-27

The interaction of cell and organelle membranes (lipid bilayers) with nanoelectronics can enable new technologies to sense and measure electrophysiology in qualitatively new ways. To date, a variety of sensing devices have been demonstrated to measure membrane currents through macroscopic numbers of ion channels. However, nanoelectronic based sensing of single ion channel currents has been a challenge. Here, we report graphene-based field-effect transistors combined with supported lipid bilayers as a platform for measuring, for the first time, individual ion channel activity. We show that the supported lipid bilayers uniformly coat the single layer graphene surface, acting as a biomimetic barrier that insulates (both electrically and chemically) the graphene from the electrolyte environment. Upon introduction of pore-forming membrane proteins such as alamethicin and gramicidin A, current pulses are observed through the lipid bilayers from the graphene to the electrolyte, which charge the quantum capacitance of the graphene. This approach combines nanotechnology with electrophysiology to demonstrate qualitatively new ways of measuring ion channel currents.

Charging the Quantum Capacitance of Graphene with a Single Biological Ion Channel

PubMed Central

2015-01-01

The interaction of cell and organelle membranes (lipid bilayers) with nanoelectronics can enable new technologies to sense and measure electrophysiology in qualitatively new ways. To date, a variety of sensing devices have been demonstrated to measure membrane currents through macroscopic numbers of ion channels. However, nanoelectronic based sensing of single ion channel currents has been a challenge. Here, we report graphene-based field-effect transistors combined with supported lipid bilayers as a platform for measuring, for the first time, individual ion channel activity. We show that the supported lipid bilayers uniformly coat the single layer graphene surface, acting as a biomimetic barrier that insulates (both electrically and chemically) the graphene from the electrolyte environment. Upon introduction of pore-forming membrane proteins such as alamethicin and gramicidin A, current pulses are observed through the lipid bilayers from the graphene to the electrolyte, which charge the quantum capacitance of the graphene. This approach combines nanotechnology with electrophysiology to demonstrate qualitatively new ways of measuring ion channel currents. PMID:24754625

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Thermal transistor behavior of a harmonic chain

NASA Astrophysics Data System (ADS)

Kim, Sangrak

2017-09-01

Thermal transistor behavior of a harmonic chain with three heat reservoirs is explicitly analyzed. Temperature profile and heat currents of the rather general system are formulated and then heat currents for the simplest system are exactly calculated. The matrix connecting the three temperatures of the reservoirs and those of the particles comprises a stochastic matrix. The ratios R 1 and R 2 between heat currents, characterizing thermal signals can be expressed in terms of two external variables and two material parameters. It is shown that the ratios R 1 and R 2 can have wide range of real values. The thermal system shows a thermal transistor behavior such as the amplification of heat current by appropriately controlling the two variables and two parameters. We explicitly demonstrate the characteristics and mechanisms of thermal transistor with the simplest model.

Effect of germanium concentrations on tunnelling current calculation of Si/Si1-xGex/Si heterojunction bipolar transistor

NASA Astrophysics Data System (ADS)

Hasanah, L.; Suhendi, E.; Khairrurijal

2018-05-01

Tunelling current calculation on Si/Si1-xGex/Si heterojunction bipolar transistor was carried out by including the coupling between transversal and longitudinal components of electron motion. The calculation results indicated that the coupling between kinetic energy in parallel and perpendicular to S1-xGex barrier surface affected tunneling current significantly when electron velocity was faster than 1x105 m/s. This analytical tunneling current model was then used to study how the germanium concentration in base to Si/Si1-xGex/Si heterojunction bipolar transistor influenced the tunneling current. It is obtained that tunneling current increased as the germanium concentration given in base decreased.

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Circuit protects regulated power supply against overload current

NASA Technical Reports Server (NTRS)

Airth, H. B.

1966-01-01

Sensing circuit in which a tunnel diode controls a series regulator transistor protects a low voltage transistorized dc regulator from damage by excessive load currents. When a fault occurs, the faulty circuit is limited to a preset percentage of the current when limiting first occurs.

Giant current fluctuations in an overheated single-electron transistor

NASA Astrophysics Data System (ADS)

Laakso, M. A.; Heikkilä, T. T.; Nazarov, Yuli V.

2010-11-01

Interplay of cotunneling and single-electron tunneling in a thermally isolated single-electron transistor leads to peculiar overheating effects. In particular, there is an interesting crossover interval where the competition between cotunneling and single-electron tunneling changes to the dominance of the latter. In this interval, the current exhibits anomalous sensitivity to the effective electron temperature of the transistor island and its fluctuations. We present a detailed study of the current and temperature fluctuations at this interesting point. The methods implemented allow for a complete characterization of the distribution of the fluctuating quantities, well beyond the Gaussian approximation. We reveal and explore the parameter range where, for sufficiently small transistor islands, the current fluctuations become gigantic. In this regime, the optimal value of the current, its expectation value, and its standard deviation differ from each other by parametrically large factors. This situation is unique for transport in nanostructures and for electron transport in general. The origin of this spectacular effect is the exponential sensitivity of the current to the fluctuating effective temperature.

Dose Rate Effects in Linear Bipolar Transistors

NASA Technical Reports Server (NTRS)

Johnston, Allan; Swimm, Randall; Harris, R. D.; Thorbourn, Dennis

2011-01-01

Dose rate effects are examined in linear bipolar transistors at high and low dose rates. At high dose rates, approximately 50% of the damage anneals at room temperature, even though these devices exhibit enhanced damage at low dose rate. The unexpected recovery of a significant fraction of the damage after tests at high dose rate requires changes in existing test standards. Tests at low temperature with a one-second radiation pulse width show that damage continues to increase for more than 3000 seconds afterward, consistent with predictions of the CTRW model for oxides with a thickness of 700 nm.

Pulse-Driven Capacitive Lead Ion Detection with Reduced Graphene Oxide Field-Effect Transistor Integrated with an Analyzing Device for Rapid Water Quality Monitoring.

PubMed

Maity, Arnab; Sui, Xiaoyu; Tarman, Chad R; Pu, Haihui; Chang, Jingbo; Zhou, Guihua; Ren, Ren; Mao, Shun; Chen, Junhong

2017-11-22

Rapid and real-time detection of heavy metals in water with a portable microsystem is a growing demand in the field of environmental monitoring, food safety, and future cyber-physical infrastructure. Here, we report a novel ultrasensitive pulse-driven capacitance-based lead ion sensor using self-assembled graphene oxide (GO) monolayer deposition strategy to recognize the heavy metal ions in water. The overall field-effect transistor (FET) structure consists of a thermally reduced graphene oxide (rGO) channel with a thin layer of Al 2 O 3 passivation as a top gate combined with sputtered gold nanoparticles that link with the glutathione (GSH) probe to attract Pb 2+ ions in water. Using a preprogrammed microcontroller, chemo-capacitance based detection of lead ions has been demonstrated with this FET sensor. With a rapid response (∼1-2 s) and negligible signal drift, a limit of detection (LOD) < 1 ppb and excellent selectivity (with a sensitivity to lead ions 1 order of magnitude higher than that of interfering ions) can be achieved for Pb 2+ measurements. The overall assay time (∼10 s) for background water stabilization followed by lead ion testing and calculation is much shorter than common FET resistance/current measurements (∼minutes) and other conventional methods, such as optical and inductively coupled plasma methods (∼hours). An approximate linear operational range (5-20 ppb) around 15 ppb (the maximum contaminant limit by US Environmental Protection Agency (EPA) for lead in drinking water) makes it especially suitable for drinking water quality monitoring. The validity of the pulse method is confirmed by quantifying Pb 2+ in various real water samples such as tap, lake, and river water with an accuracy ∼75%. This capacitance measurement strategy is promising and can be readily extended to various FET-based sensor devices for other targets.

Remotely-actuated biomedical switch

NASA Technical Reports Server (NTRS)

Lee, R. D.

1969-01-01

Remotely-actuated biomedical switching circuit using transistors consumes no power in the off position and can be actuated by a single-frequency telemetry pulse to control implanted instrumentation. Silicon controlled rectifiers permit the circuit design which imposes zero drain on supply batteries when not in use.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Utilizing Schottky barriers to suppress short-channel effects in organic transistors

NASA Astrophysics Data System (ADS)

Fernández, Anton F.; Zojer, Karin

2017-10-01

Transistors with short channel lengths exhibit profound deviations from the ideally expected behavior. One of the undesired short-channel effects is an enlarged OFF current that is associated with a premature turn on of the transistor. We present an efficient approach to suppress the OFF current, defined as the current at zero gate source bias, in short-channel organic transistors. We employ two-dimensional device simulations based on the drift-diffusion model to demonstrate that intentionally incorporating a Schottky barrier for injection enhances the ON-OFF ratio in both staggered and coplanar transistor architectures. The Schottky barrier is identified to directly counteract the origin of enlarged OFF currents: Short channels promote a drain-induced barrier lowering. The latter permits unhindered injection of charges even at reverse gate-source bias. An additional Schottky barrier hampers injection for such points of operations. We explain how it is possible to find the Schottky barrier of the smallest height necessary to exactly compensate for the premature turn on. This approach offers a substantial enhancement of the ON-OFF ratio. We show that this roots in the fact that such optimal barrier heights offer an excellent compromise between an OFF current diminished by orders of magnitude and an only slightly reduced ON current.

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

5.8kV SiC PiN Diode for Switching of High-Efficiency Inductive Pulsed Plasma Thruster Circuits

NASA Technical Reports Server (NTRS)

Toftul, Alexandra; Polzin, Kurt A.; Hudgins, Jerry L.

2014-01-01

Inductive Pulsed Plasma Thruster (IPPT) pulse circuits, such as those needed to operate the Pulsed Inductive Thruster (PIT), are required to quickly switch capacitor banks operating at a period of µs while conducting current at levels on the order of at least 10 kA. [1,2] For all iterations of the PIT to date, spark gaps have been used to discharge the capacitor bank through an inductive coil. Recent availability of fast, high-power solid state switching devices makes it possible to consider the use of semiconductor switches in modern IPPTs. In addition, novel pre-ionization schemes have led to a reduction in discharge energy per pulse for electric thrusters of this type, relaxing the switching requirements for these thrusters. [3,4] Solid state switches offer the advantage of greater controllability and reliability, as well as decreased drive circuit dimensions and mass relative to spark gap switches. The use of solid state devices such as Integrated Gate Bipolar Transistors (IGBTs), Gate Turn-off Thyristors (GTOs) and Silicon-Controlled Rectifiers (SCRs) often involves the use of power diodes. These semiconductor devices may be connected antiparallel to the switch for protection from reverse current, or used to reduce power loss in a circuit by clamping off current ringing. In each case, higher circuit efficiency may be achieved by using a diode that is able to transition, or 'switch,' from the forward conducting state ('on' state) to the reverse blocking state ('off' state) in the shortest amount of time, thereby minimizing current ringing and switching losses. Silicon Carbide (SiC) PiN diodes offer significant advantages to conventional fast-switching Silicon (Si) diodes for high power and fast switching applications. A wider band gap results in a breakdown voltage 10 times that of Si, so that a SiC device may have a thinner drift region for a given blocking voltage. [5] This leads to smaller, lighter devices for high voltage applications, as well as reduced forward conduction losses, faster reverse recovery time (faster turn-off), and lower-magnitude reverse recovery current. In addition, SiC devices have lower leakage current as compared to their Si counterparts, and a high thermal conductivity, potentially allowing the former to operate at higher temperatures with a smaller, lighter heatsink (or no heatsink at all).

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

A 10-kW series resonant converter design, transistor characterization, and base-drive optimization

NASA Technical Reports Server (NTRS)

Robson, R. R.; Hancock, D. J.

1982-01-01

The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.

Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation

PubMed Central

Zheng, Jiaxin; Wang, Lu; Quhe, Ruge; Liu, Qihang; Li, Hong; Yu, Dapeng; Mei, Wai-Ning; Shi, Junjie; Gao, Zhengxiang; Lu, Jing

2013-01-01

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm, and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap. PMID:23419782

Investigation of sensing mechanism and signal amplification in carbon nanotube based microfluidic liquid-gated transistors via pulsating gate bias.

PubMed

Wijaya, I Putu Mahendra; Nie, Tey Ju; Rodriguez, Isabel; Mhaisalkar, Subodh G

2010-06-07

The advent of a carbon nanotube liquid-gated transistor (LGFET) for biosensing applications allows the possibility of real-time and label-free detection of biomolecular interactions. The use of an aqueous solution as dielectric, however, has traditionally restricted the operating gate bias (VG) within |VG| < 1 V, due to the electrolysis of water. Here, we propose pulsed-gating as a facile method to extend the operation window of LGFETs to |VG| > 1 V. A comparison between simulation and experimental results reveals that at voltages in excess of 1 V, the LGFET sensing mechanism has a contribution from two factors: electrostatic gating as well as capacitance modulation. Furthermore, the large IDS drop observed in the |VG| > 1 V region indicates that pulsed-gating may be readily employed as a simple method to amplify the signal in the LGFET and pushes the detection limit down to attomolar concentration levels, an order of magnitude improvement over conventionally employed DC VG biasing.

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

PubMed Central

Oh, Young Jun; Noh, Hyeon-Kyun; Chang, Kee Joo

2015-01-01

Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity. PMID:27877799

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

Buffer transport mechanisms in intentionally carbon doped GaN heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uren, Michael J.; Cäsar, Markus; Kuball, Martin

2014-06-30

Temperature dependent pulsed and ramped substrate bias measurements are used to develop a detailed understanding of the vertical carrier transport in the buffer layers in a carbon doped GaN power heterojunction field effect transistor. Carbon doped GaN and multiple layers of AlGaN alloy are used in these devices to deliver an insulating and strain relieved buffer with high breakdown voltage capability. However, understanding of the detailed physical mechanism for its operation is still lacking. At the lowest electric fields (<10 MV/m), charge redistribution within the C doped layer is shown to occur by hole conduction in the valence band withmore » activation energy 0.86 eV. At higher fields, leakage between the two-dimensional electron gas and the buffer dominates occurring by a Poole-Frenkel mechanism with activation energy ∼0.65 eV, presumably along threading dislocations. At higher fields still, the strain relief buffer starts to conduct by a field dependent process. Balancing the onset of these leakage mechanisms is essential to allow the build-up of positive rather than negative space charge, and thus minimize bulk-related current-collapse in these devices.« less

A microwave field-driven transistor-like skyrmionic device with the microwave current-assisted skyrmion creation

NASA Astrophysics Data System (ADS)

Xia, Jing; Huang, Yangqi; Zhang, Xichao; Kang, Wang; Zheng, Chentian; Liu, Xiaoxi; Zhao, Weisheng; Zhou, Yan

2017-10-01

Magnetic skyrmion is a topologically protected domain-wall structure at nanoscale, which could serve as a basic building block for advanced spintronic devices. Here, we propose a microwave field-driven skyrmionic device with the transistor-like function, where the motion of a skyrmion in a voltage-gated ferromagnetic nanotrack is studied by micromagnetic simulations. It is demonstrated that the microwave field can drive the motion of a skyrmion by exciting the propagating spin waves, and the skyrmion motion can be governed by a gate voltage. We also investigate the microwave current-assisted creation of a skyrmion to facilitate the operation of the transistor-like skyrmionic device on the source terminal. It is found that the microwave current with an appropriate frequency can reduce the threshold current density required for the creation of a skyrmion from the ferromagnetic background. The proposed transistor-like skyrmionic device operated with the microwave field and current could be useful for building future skyrmion-based circuits.

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

High-frequency trigger generators for CuBr-laser high voltage pumping source

NASA Astrophysics Data System (ADS)

Torgaev, S.; Kozhemyak, O.; Yaroslavtsev, E.; Trigub, M.; Musorov, I.; Chertikhina, D.

2016-04-01

In this paper the circuits of high frequency trigger generators of pulses of the nanosecond duration are presented. A detailed study of a generator based on the avalanche transistor with the use of a coaxial cable instead of a capacitor is described. This circuit showed advanced characteristics of the output pulses. A circuit of a generator built on high-speed digital components is also considered. The basic advantages and disadvantages of both generators are presented in this paper.

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

NASA Astrophysics Data System (ADS)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

DC switching regulated power supply for driving an inductive load

DOEpatents

Dyer, G.R.

1983-11-29

A dc switching regulated power supply for driving an inductive load is provided. The regulator basic circuit is a bridge arrangement of diodes and transistors. First and second opposite legs of the bridge are formed by first and second parallel-connected transistor arrays, respectively, while the third and fourth legs of the bridge are formed by appropriately connected first and second parallel connected diode arrays, respectively. A dc power supply is connected to the input of the bridge and the output is connected to the load. A servo controller is provided to control the switching rate of the transistors to maintain a desired current to the load. The regulator may be operated in three stages or modes: (1) for current runup in the load, both first and second transistor switch arrays are turned on and current is supplied to the load through both transistor arrays. (2) When load current reaches the desired level, the first switch is turned off, and load current flywheels through the second switch array and the fourth leg diode array connecting the second switch array in series with the load. Current is maintained by alternating between modes 1 and 2 at a suitable duty cycle and switching rate set by the controller. (3) Rapid current rundown is accomplished by turning both switch arrays off, allowing load current to be dumped back into the source through the third and fourth diode arrays connecting the source in series opposition with the load to recover energy from the inductive load.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Highly efficient X-range AlGaN/GaN power amplifier

NASA Astrophysics Data System (ADS)

Tural'chuk, P. A.; Kirillov, V. V.; Osipov, P. E.; Vendik, I. B.; Vendik, O. G.; Parnes, M. D.

2017-09-01

The development of microwave power amplifiers (PAs) based on transistors with an AlGaN/GaN heterojunction are discussed in terms of the possible enhancement of their efficiency. The main focus is on the synthesis of the transforming circuits, which ensure the reactive load at the second- and third-harmonic frequencies and complex impedance at the fundamental frequency. This makes it possible to optimize the complex operation mode of a PA; i.e., to reduce the scattering power and enhance the efficiency. A microwave PA based on the Schottky-barrier-gate field-effect transistor with 80 electrodes based on the GaN pHEMT transistor with a gate length of 0.25 nm and a gate width of 125 nm is experimentally investigated. The amplifier has a pulse output power of 35 W and a power-added efficiency of at least 50% at a working frequency of 9 GHz.

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeluri, Ramya, E-mail: ramyay@ece.ucsb.edu; Lu, Jing; Keller, Stacia

2015-05-04

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm{sup 2}) and low ON-resistance (0.4 mΩ cm{sup 2}) are demonstrated. Non-planar selective area regrowth is identified as the limiting factormore » to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities.« less

High temperature current mirror amplifier

DOEpatents

Patterson, III, Raymond B.

1984-05-22

A high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg.

High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures.

PubMed

Liu, Yuan; Sheng, Jiming; Wu, Hao; He, Qiyuan; Cheng, Hung-Chieh; Shakir, Muhammad Imran; Huang, Yu; Duan, Xiangfeng

2016-06-01

Scalable fabrication of vertical-tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm(-2) . This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene-silicon heterostructures. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

NASA Astrophysics Data System (ADS)

Gentil, P.; Mounib, A.

1981-05-01

Flicker noise in MOS transistors can be evaluated by measuring the spectrum SID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of {S I D}/{Sve} are in good agreement with gm2 by considering a model of the transconductance gm which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.

Comparison of effect of 5 MeV proton and Co-60 gamma irradiation on silicon NPN rf power transistors and N-channel depletion MOSFETs

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Pradeep, T. M.; Hegde, Vinayakprasanna N.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Bhushan, K. G.

2017-12-01

NPN transistors and N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 5 MeV protons and 60Co gamma radiation in the dose ranging from 1 Mrad(Si) to 100 Mrad(Si). The different electrical characteristics of the NPN transistor such as Gummel characteristics, excess base current (ΔIB), dc current gain (hFE), transconductance (gm), displacement damage factor (K) and output characteristics were studied as a function of total dose. The different electrical characteristics of N-channel MOSFETs such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (µ) and drain saturation current (IDSat) were studied systematically before and after irradiation in the same dose ranges. A considerable increase in the base current (IB) and decrease in the hFE, gm and collector saturation current (ICSat) were observed after irradiation in the case of the NPN transistor. In the N-channel MOSFETs, the ΔNit and ΔNot were found to increase and Vth, gm, µ and IDSat were found to decrease with increase in the radiation dose. The 5 MeV proton irradiation results of both the NPN transistor and N-channel MOSFETs were compared with 60Co gamma-irradiated devices in the same dose ranges. It was observed that the degradation in 5 MeV proton-irradiated devices is more when compared with the 60Co gamma-irradiated devices at higher total doses.

Repetitive transcranial magnetic stimulator with controllable pulse parameters

NASA Astrophysics Data System (ADS)

Peterchev, Angel V.; Murphy, David L.; Lisanby, Sarah H.

2011-06-01

The characteristics of transcranial magnetic stimulation (TMS) pulses influence the physiological effect of TMS. However, available TMS devices allow very limited adjustment of the pulse parameters. We describe a novel TMS device that uses a circuit topology incorporating two energy storage capacitors and two insulated-gate bipolar transistor (IGBT) modules to generate near-rectangular electric field pulses with adjustable number, polarity, duration, and amplitude of the pulse phases. This controllable pulse parameter TMS (cTMS) device can induce electric field pulses with phase widths of 10-310 µs and positive/negative phase amplitude ratio of 1-56. Compared to conventional monophasic and biphasic TMS, cTMS reduces energy dissipation up to 82% and 57% and decreases coil heating up to 33% and 41%, respectively. We demonstrate repetitive TMS trains of 3000 pulses at frequencies up to 50 Hz with electric field pulse amplitude and width variability less than the measurement resolution (1.7% and 1%, respectively). Offering flexible pulse parameter adjustment and reduced power consumption and coil heating, cTMS enhances existing TMS paradigms, enables novel research applications and could lead to clinical applications with potentially enhanced potency.

Repetitive transcranial magnetic stimulator with controllable pulse parameters.

PubMed

Peterchev, Angel V; Murphy, David L; Lisanby, Sarah H

2011-06-01

The characteristics of transcranial magnetic stimulation (TMS) pulses influence the physiological effect of TMS. However, available TMS devices allow very limited adjustment of the pulse parameters. We describe a novel TMS device that uses a circuit topology incorporating two energy storage capacitors and two insulated-gate bipolar transistor (IGBT) modules to generate near-rectangular electric field pulses with adjustable number, polarity, duration, and amplitude of the pulse phases. This controllable pulse parameter TMS (cTMS) device can induce electric field pulses with phase widths of 10-310 µs and positive/negative phase amplitude ratio of 1-56. Compared to conventional monophasic and biphasic TMS, cTMS reduces energy dissipation up to 82% and 57% and decreases coil heating up to 33% and 41%, respectively. We demonstrate repetitive TMS trains of 3000 pulses at frequencies up to 50 Hz with electric field pulse amplitude and width variability less than the measurement resolution (1.7% and 1%, respectively). Offering flexible pulse parameter adjustment and reduced power consumption and coil heating, cTMS enhances existing TMS paradigms, enables novel research applications and could lead to clinical applications with potentially enhanced potency.

Dc-To-Dc Converter Uses Reverse Conduction Of MOSFET's

NASA Technical Reports Server (NTRS)

Gruber, Robert P.; Gott, Robert W.

1991-01-01

In modified high-power, phase-controlled, full-bridge, pulse-width-modulated dc-to-dc converters, switching devices power metal oxide/semiconductor field-effect transistors (MOSFET's). Decreases dissipation of power during switching by eliminating approximately 0.7-V forward voltage drop in anti-parallel diodes. Energy-conversion efficiency increased.

Resistive Random Access Memory from Materials Development fnd Engineering to Novel Encryption and Neuromorphic Applications

NASA Astrophysics Data System (ADS)

Beckmann, Karsten

Resistive random access memory (ReRAM or RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance state of ReRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse properties. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. I have developed two processes based on 100 and 300mm wafer platforms to demonstrate functional HfO2 based ReRAM devices. The first process is designed for a rapid materials engineering and device characterization, while the second is an advanced hybrid ReRAM/CMOS combination based on the IBM 65nm 10LPe process technology. The 100mm wafer efforts were used to show impacts of etch processes on ReRAM switching performance and the need for a rigorous structural evaluation of ReRAM devices before starting materials development. After an etch development, a bottom electrode comparison between the inert materials Pt, Ru and W was performed where Ru showed superior results with respect to yield and resilience against environmental impacts such as humidity over a 2-month period. A comparison of amorphous and crystalline devices showed no statistical difference in the performance with respect to random telegraph noise. This demonstrates, that the forming process fundamentally alters the crystallographic structure within and around the filament. The 300mm wafer development efforts were aimed towards implementing ReRAM in the FEOL, combined with CMOS, to yield a seamless process flow of 1 transistor 1 ReRAM structures (1T1R). This technology was customized with custom-developed tungsten metal 1 (M1) and dual tungsten/copper via 1 (V1) structures, within which the ReRAM stack is embedded. The ReRAM itself consists of an inert W bottom electrode, HfO2 based active switching layer, a Ti oxygen scavenger layer, and an inert TiN top electrode. Linear sweep and controlled pulse (down to 5 ns) based electrical characterization of 1 transistor 1 ReRAM (1T1R) elements was performed to determine key properties including endurance, reliability, and threshold voltages. We demonstrated endurance values above 1010 cycles with an average on/off ratio of 10, and pulse voltages for set/reset operation of +/-1.5V. The on-chip 1T1R structures show an excellent controllability with respect to the low and high resistive states by manipulating the peak current from 75 up to 350 mu?A resulting in 10 distinct low resistance states (LRS). Our results demonstrate that the set operation (which shifts the ReRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage resulting in a larger relative change of the ReRAM device resistance. The incremental resistance changes are ideally suited to emulate synaptic weights for future implementation into neuromorphic architectures. Switching results from these devices were also used to develop a model time-delay physical unclonable function (PUF) circuit, which showed excellent performance when compared to a pure CMOS implementation with significant improvements in uniqueness, size and accuracy.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Dual-mode operation of 2D material-base hot electron transistors

PubMed Central

Lan, Yann-Wen; Torres, Jr., Carlos M.; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications. PMID:27581550

Dual-mode operation of 2D material-base hot electron transistors.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

High-performance radio frequency transistors based on diameter-separated semiconducting carbon nanotubes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Yu; Che, Yuchi; Zhou, Chongwu, E-mail: chongwuz@usc.edu

In this paper, we report the high-performance radio-frequency transistors based on the single-walled semiconducting carbon nanotubes with a refined average diameter of ∼1.6 nm. These diameter-separated carbon nanotube transistors show excellent transconductance of 55 μS/μm and desirable drain current saturation with an output resistance of ∼100 KΩ μm. An exceptional radio-frequency performance is also achieved with current gain and power gain cut-off frequencies of 23 GHz and 20 GHz (extrinsic) and 65 GHz and 35 GHz (intrinsic), respectively. These radio-frequency metrics are among the highest reported for the carbon nanotube thin-film transistors. This study provides demonstration of radio frequency transistors based on carbon nanotubes with tailoredmore » diameter distributions, which will guide the future application of carbon nanotubes in radio-frequency electronics.« less

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

High temperature current mirror amplifier

DOEpatents

Patterson, R.B. III.

1984-05-22

Disclosed is a high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg. 2 figs.

TRANSISTOR HIGH VOLTAGE POWER SUPPLY

DOEpatents

Driver, G.E.

1958-07-15

High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

A study of junction effect transistors and their roles in carbon nanotube field emission cathodes in compact pulsed power applications

NASA Astrophysics Data System (ADS)

Shui, Qiong

This thesis is focusing on a study of junction effect transistors (JFETs) in compact pulsed power applications. Pulsed power usually requires switches with high hold-off voltage, high current, low forward voltage drop, and fast switching speed. 4H-SiC, with a bandgap of 3.26 eV (The bandgap of Si is 1.12eV) and other physical and electrical superior properties, has gained much attention in high power, high temperature and high frequency applications. One topic of this thesis is to evaluate if 4H-SiC JFETs have a potential to replace gas phase switches to make pulsed power system compact and portable. Some other pulsed power applications require cathodes of providing stable, uniform, high electron-beam current. So the other topic of this research is to evaluate if Si JFET-controlled carbon nanotube field emitter cold cathode will provide the necessary e-beam source. In the topic of "4H-SiC JFETs", it focuses on the design and simulation of a novel 4H-SiC normally-off VJFET with high breakdown voltage using the 2-D simulator ATLAS. To ensure realistic simulations, we utilized reasonable physical models and the established parameters as the input into these models. The influence of key design parameters were investigated which would extend pulsed power limitations. After optimizing the key design parameters, with a 50-mum drift region, the predicted breakdown voltage for the VJFET is above 8kV at a leakage current of 1x10-5A/cm2 . The specific on-state resistance is 35 mO·cm 2 at VGS = 2.7 V, and the switching speed is several ns. The simulation results suggest that the 4H-SiC VJFET is a potential candidate for improving switching performance in repetitive pulsed power applications. To evaluate the 4H-SiC VJFETs in pulsed power circuits, we extracted some circuit model parameters from the simulated I-V curves. Those parameters are necessary for circuit simulation program such as SPICE. This method could be used as a test bench without fabricating the devices to minimize the unnecessary cost. As an extended research of 4H-SiC devices, Metal-Insulator-SiC (MIS) structures were utilized to evaluate the high dielectric constant materials---TiO 2 and Al2O3, as possible gate dielectrics for SiC devices. TiO2 and Al2O3 were chosen because of their high dielectric constants and bandgap energies as well as the acceptance of Ti and Al in most modern CMOS fabrication facilities. MIS devices were fabricated and both their I-V and C-V characteristics were measured and discussed. Our research showed that Al2O3 deposited by e-beam evaporation could be considered as a promising material among the gate insulators for high power SiC devices. In the topic of "Si JFET-controlled carbon nanotube field emitter cathode arrays", stability, controllability and lifetime are the main issues waiting to be addressed before field emitters find their wide applications. The ideas of connecting Si or metal field emitters with external MOSFETs or built-in active devices were attempted by other researchers, and those devices showed effectiveness in controlling and stabilizing the emission current. We presented the design, simulation, and the fabrication of Si JFETs monolithically integrated with CNTs field emitters. The Si JFET was designed to control and improve the emission of carbon nanotube field emitter arrays. Its electrical characteristics were simulated by the device simulator ATLAS. The fabrication process was developed to be compatible with the last step of growing multiwalled carbon nanotubes at 700°C. Carbon nanotubes field emitters were grown by PECVD (Plasma Enhanced Chemical Vapor Deposition). Preliminary field emission tests were conducted with 50 x 50 emitter arrays, with a resultant emission current of 3 muA (˜40 mA/cm2) at an extraction gate voltage of 50 V and an anode voltage of 300 V. Experimental data shows the linear relationship between ln(I/V2) and l/V consistent with Fowler-Nordheim electron tunneling. Some challenging issues were also discussed.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

Power electronics for low power arcjets

NASA Technical Reports Server (NTRS)

Hamley, John A.; Hill, Gerald M.

1991-01-01

In anticipation of the needs of future light-weight, low-power spacecraft, arcjet power electronics in the 100 to 400 W operating range were developed. Limited spacecraft power and thermal control capacity of these small spacecraft emphasized the need for high efficiency. Power topologies similar to those in the higher 2 kW and 5 to 30 kW power range were implemented, including a four transistor bridge switching circuit, current mode pulse-width modulated control, and an output current averaging inductor with an integral pulse generation winding. Reduction of switching transients was accomplished using a low inductance power distribution network, and no passive snubber circuits were necessary for power switch protection. Phase shift control of the power bridge was accomplished using an improved pulse width modulation to phase shift converter circuit. These features, along with conservative magnetics designs allowed power conversion efficiencies of greater than 92.5 percent to be achieved into resistive loads over the entire operating range of the converter. Electromagnetic compatibility requirements were not considered in this work, and control power for the converter was derived from AC mains. Addition of input filters and control power converters would result in an efficiency of on the order of 90 percent for a flight unit. Due to the developmental nature of arcjet systems at this power level, the exact nature of the thruster/power processor interface was not quantified. Output regulation and current ripple requirements of 1 and 20 percent respectively, as well as starting techniques, were derived from the characteristics of the 2 kW system but an open circuit voltage in excess of 175 V was specified. Arcjet integration tests were performed, resulting in successful starts and stable arcjet operation at power levels as low as 240 W with simulated hydrazine propellants.

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Validation of a Portable Low-Power Deep Brain Stimulation Device Through Anxiolytic Effects in a Laboratory Rat Model.

PubMed

Kouzani, Abbas Z; Kale, Rajas P; Zarate-Garza, Pablo Patricio; Berk, Michael; Walder, Ken; Tye, Susannah J

2017-09-01

Deep brain stimulation (DBS) devices deliver electrical pulses to neural tissue through an electrode. To study the mechanisms and therapeutic benefits of deep brain stimulation, murine preclinical research is necessary. However, conducting naturalistic long-term, uninterrupted animal behavioral experiments can be difficult with bench-top systems. The reduction of size, weight, power consumption, and cost of DBS devices can assist the progress of this research in animal studies. A low power, low weight, miniature DBS device is presented in this paper. This device consists of electronic hardware and software components including a low-power microcontroller, an adjustable current source, an n-channel metal-oxide-semiconductor field-effect transistor, a coin-cell battery, electrode wires and a software program to operate the device. Evaluation of the performance of the device in terms of battery lifetime and device functionality through bench and in vivo tests was conducted. The bench test revealed that this device can deliver continuous stimulation current pulses of strength [Formula: see text], width [Formula: see text], and frequency 130 Hz for over 22 days. The in vivo tests demonstrated that chronic stimulation of the nucleus accumbens (NAc) with this device significantly increased psychomotor activity, together with a dramatic reduction in anxiety-like behavior in the elevated zero-maze test.

Comprehensive dynamic on-resistance assessments in GaN-on-Si MIS-HEMTs for power switching applications

NASA Astrophysics Data System (ADS)

Chou, Po-Chien; Hsieh, Ting-En; Cheng, Stone; del Alamo, Jesús A.; Chang, Edward Yi

2018-05-01

This study comprehensively analyzed the reliability of trapping and hot-electron effects responsible for the dynamic on-resistance (Ron) of GaN-based metal–insulator–semiconductor high electron mobility transistors. Specifically, this study performed the following analyses. First, we developed the on-the-fly Ron measurement to analyze the effects of traps during stress. With this technique, the faster one (with a pulse period of 20 ms) can characterize the degradation; the transient behavior could be monitored accurately by such short measurement pulse. Then, dynamic Ron transients were investigated under different bias conditions, including combined off state stress conditions, back-gating stress conditions, and semi-on stress conditions, in separate investigations of surface- and buffer-, and hot-electron-related trapping effects. Finally, the experiments showed that the Ron increase in semi-on state is significantly correlated with the high drain voltage and relatively high current levels (compared with the off-state current), involving the injection of greater amount of hot electrons from the channel into the AlGaN/insulator interface and the GaN buffer. These findings provide a path for device engineering to clarify the possible origins for electron traps and to accelerate the development of emerging GaN technologies.

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Transistors and tunnel diodes enabled by large-scale MoS2 nanosheets grown on GaN

NASA Astrophysics Data System (ADS)

San Yip, Pak; Zou, Xinbo; Cho, Wai Ching; Wu, Kam Lam; Lau, Kei May

2017-07-01

We report growth, fabrication, and device results of MoS2-based transistors and diodes implemented on a single 2D/3D material platform. The 2D/3D platform consists of a large-area MoS2 thin film grown on SiO2/p-GaN substrates. Atomic force microscopy, scanning electron microscopy, and Raman spectroscopy were used to characterize the thickness and quality of the as-grown MoS2 film, showing that the large-area MoS2 nanosheet has a smooth surface morphology constituted by small grains. Starting from the same material, both top-gated MoS2 field effect transistors and MoS2/SiO2/p-GaN heterojunction diodes were fabricated. The transistors exhibited a high on/off ratio of 105, a subthreshold swing of 74 mV dec-1, field effect mobility of 0.17 cm2 V-1 s-1, and distinctive current saturation characteristics. For the heterojunction diodes, current-rectifying characteristics were demonstrated with on-state current density of 29 A cm-2 and a current blocking property up to -25 V without breakdown. The reported transistors and diodes enabled by the same 2D/3D material stack present promising building blocks for constructing future nanoscale electronics.

Preparation of an exponentially rising optical pulse for efficient excitation of single atoms in free space.

PubMed

Dao, Hoang Lan; Aljunid, Syed Abdullah; Maslennikov, Gleb; Kurtsiefer, Christian

2012-08-01

We report on a simple method to prepare optical pulses with exponentially rising envelope on the time scale of a few ns. The scheme is based on the exponential transfer function of a fast transistor, which generates an exponentially rising envelope that is transferred first on a radio frequency carrier, and then on a coherent cw laser beam with an electro-optical phase modulator. The temporally shaped sideband is then extracted with an optical resonator and can be used to efficiently excite a single (87)Rb atom.

Comparative analysis of breakdown mechanism in thin SiO2 oxide films in metal-oxide-semiconductor structures under the action of heavy charged particles and a pulsed voltage

NASA Astrophysics Data System (ADS)

Zinchenko, V. F.; Lavrent'ev, K. V.; Emel'yanov, V. V.; Vatuev, A. S.

2016-02-01

Regularities in the breakdown of thin SiO2 oxide films in metal-oxide-semiconductors structures of power field-effect transistors under the action of single heavy charged particles and a pulsed voltage are studied experimentally. Using a phenomenological approach, we carry out comparative analysis of physical mechanisms and energy criteria of the SiO2 breakdown in extreme conditions of excitation of the electron subsystem in the subpicosecond time range.

Effective excitation of DBD lamp with a long feedline

NASA Astrophysics Data System (ADS)

Schitz, D. V.; Nechoroshev, V. O.

2016-01-01

The proposed solution makes possible the transfer of high-voltage excitation pulses through the long coaxial cable with the minimum losses and the excilamp efficiency. Use of resonant topology of the pulse converter provides ZCS at switching-ON and ZVC at switching- OFF of the transistors. The values of efficiency of radiation of ∼ 9% at the feedline of 2.5 m in length obtained during the experiments are about twice as much as the efficiency at the XeCl- excilamp excitation by the quasi-square pulses power supply due to the decrease of losses at switching and the increase of electric efficiency of a resonant power supply with the long coaxial feedline.

Direct and pulsed current annealing of p-MOSFET based dosimeter: the "MOSkin".

PubMed

Alshaikh, Sami; Carolan, Martin; Petasecca, Marco; Lerch, Michael; Metcalfe, Peter; Rosenfeld, Anatoly

2014-06-01

Contemporary radiation therapy (RT) is complicated and requires sophisticated real-time quality assurance (QA). While 3D real-time dosimetry is most preferable in RT, it is currently not fully realised. A small, easy to use and inexpensive point dosimeter with real-time and in vivo capabilities is an option for routine QA. Such a dosimeter is essential for skin, in vivo or interface dosimetry in phantoms for treatment plan verification. The metal-oxide-semiconductor-field-effect-transistor (MOSFET) detector is one of the best choices for these purposes, however, the MOSFETs sensitivity and its signal stability degrade after essential irradiation which limits its lifespan. The accumulation of positive charge on the gate oxide and the creation of interface traps near the silicon-silicon dioxide layer is the primary physical phenomena responsible for this degradation. The aim of this study is to investigate MOSFET dosimeter recovery using two proposed annealing techniques: direct current (DC) and pulsed current (PC), both based on hot charged carrier injection into the gate oxide of the p-MOSFET dosimeter. The investigated MOSFETs were reused multiple times using an irradiation-annealing cycle. The effect of the current-annealing parameters was investigated for the dosimetric characteristics of the recovered MOSFET dosimeters such as linearity, sensitivity and initial threshold voltage. Both annealing techniques demonstrated excellent results in terms of maintaining a stable response, linearity and sensitivity of the MOSFET dosimeter. However, PC annealing is more preferable than DC annealing as it offers better dose response linearity of the reused MOSFET and has a very short annealing time.

A pulse-burst laser system for Thomson scattering on NSTX-U

NASA Astrophysics Data System (ADS)

Den Hartog, D. J.; Borchardt, M. T.; Holly, D. J.; Diallo, A.; LeBlanc, B.

2017-10-01

A pulse-burst laser system has been built for Thomson scattering on NSTX-U, and is currently being integrated into the NSTX-U Thomson scattering diagnostic system. The laser will be operated in three distinct modes. The base mode is continuous 30 Hz rep rate, and is the standard operating mode of the laser. The base mode will be interrupted to produce a "slow burst" (specified 1 kHz rep rate for 50 ms) or a "fast burst" (specified 10 kHz rep rate for 5 ms). The combination of base mode→ interruption→ burst mode is new and has not been implemented on any previous pulse-burst laser system. Laser pulsing is halted for a set period (~ 1 minute) following a burst to allow the YAG rods to cool; this type of operation is called a heat-capacity laser. The laser is Nd:YAG operated at 1064 nm, q-switched to produce >= 1.5 J pulses with ~ 20 ns FWHM. It is flashlamp pumped, with dual-rod oscillator (9 mm) and dual-rod amplifier (12 mm). Variable pulsewidth drive of the flashlamps is accomplished by IGBT (insulated gate bipolar transistor) switching of electrolytic capacitor banks. Direct control of the laser Pockels cell drive enables optimal pulse energy extraction. The laser system has demonstrated compliance with all specifications, and is capable of exceeding design specifications by significant margins, e.g., higher rep rates for longer burst periods. Burst operation of this laser system will be used to capture fast time evolution of the electron temperature and density profiles during events such as ELMs, the L-H transition, and various MHD modes.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

PubMed

Dey, Anil W; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik

2013-01-01

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

AlGaAs/InGaAs/AlGaAs double pulse doped pseudomorphic high electron mobility transistor structures on InGaAs substrates

NASA Astrophysics Data System (ADS)

Hoke, W. E.; Lyman, P. S.; Mosca, J. J.; McTaggart, R. A.; Lemonias, P. J.; Beaudoin, R. M.; Torabi, A.; Bonner, W. A.; Lent, B.; Chou, L.-J.; Hsieh, K. C.

1997-10-01

Double pulse doped AlGaAs/InGaAs/AlGaAs pseudomorphic high electron mobility transistor (PHEMT) structures have been grown on InxGa1-xAs (x=0.025-0.07) substrates using molecular beam epitaxy. A strain compensated, AlGaInAs/GaAs superlattice was used for improved resistivity and breakdown. Excellent electrical and optical properties were obtained for 110-Å-thick InGaAs channel layers with indium concentrations up to 31%. A room temperature mobility of 6860 cm2/V s with 77 K sheet density of 4.0×1012cm-2 was achieved. The InGaAs channel photoluminescence intensity was equivalent to an analogous structure on a GaAs substrate. To reduce strain PHEMT structures with a composite InGaP/AlGaAs Schottky layer were also grown. The structures also exhibited excellent electrical and optical properties. Transmission electron micrographs showed planar channel interfaces for highly strained In0.30Ga0.70As channel layers.

Silicon nanodisk array with a fin field-effect transistor for time-domain weighted sum calculation toward massively parallel spiking neural networks

NASA Astrophysics Data System (ADS)

Tohara, Takashi; Liang, Haichao; Tanaka, Hirofumi; Igarashi, Makoto; Samukawa, Seiji; Endo, Kazuhiko; Takahashi, Yasuo; Morie, Takashi

2016-03-01

A nanodisk array connected with a fin field-effect transistor is fabricated and analyzed for spiking neural network applications. This nanodevice performs weighted sums in the time domain using rising slopes of responses triggered by input spike pulses. The nanodisk arrays, which act as a resistance of several giga-ohms, are fabricated using a self-assembly bio-nano-template technique. Weighted sums are achieved with an energy dissipation on the order of 1 fJ, where the number of inputs can be more than one hundred. This amount of energy is several orders of magnitude lower than that of conventional digital processors.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E. (Inventor)

1975-01-01

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

Multi-Resolution Imaging of Electron Dynamics in Nanostructure Interfaces

DTIC Science & Technology

2010-07-27

metallic carbon nanotubes from semiconducting ones. In pentacene transistors, we used scanning photocurrent microscopy to study spatially resolved...photoelectric response of pentacene thin films, which showed that point contacts formed near the hole injection points limit the overall performance of the...photothermal current microscopy, carbon nanotube transistor, pentacene transistor, contact resistance, hole injection 16. SECURITY CLASSIFICATION OF

Quantum Thermal Transistor.

PubMed

Joulain, Karl; Drevillon, Jérémie; Ezzahri, Younès; Ordonez-Miranda, Jose

2016-05-20

We demonstrate that a thermal transistor can be made up with a quantum system of three interacting subsystems, coupled to a thermal reservoir each. This thermal transistor is analogous to an electronic bipolar one with the ability to control the thermal currents at the collector and at the emitter with the imposed thermal current at the base. This is achieved by determining the heat fluxes by means of the strong-coupling formalism. For the case of three interacting spins, in which one of them is coupled to the other two, that are not directly coupled, it is shown that high amplification can be obtained in a wide range of energy parameters and temperatures. The proposed quantum transistor could, in principle, be used to develop devices such as a thermal modulator and a thermal amplifier in nanosystems.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

NASA Astrophysics Data System (ADS)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

Accelerating Gas Adsorption on 3D Percolating Carbon Nanotubes.

PubMed

Li, Hui; Wen, Chenyu; Zhang, Youwei; Wu, Dongping; Zhang, Shi-Li; Qiu, Zhi-Jun

2016-02-18

In the field of electronic gas sensing, low-dimensional semiconductors such as single-walled carbon nanotubes (SWCNTs) can offer high detection sensitivity owing to their unprecedentedly large surface-to-volume ratio. The sensitivity and responsivity can further improve by increasing their areal density. Here, an accelerated gas adsorption is demonstrated by exploiting volumetric effects via dispersion of SWCNTs into a percolating three-dimensional (3D) network in a semiconducting polymer. The resultant semiconducting composite film is evaluated as a sensing membrane in field effect transistor (FET) sensors. In order to attain reproducible characteristics of the FET sensors, a pulsed-gate-bias measurement technique is adopted to eliminate current hysteresis and drift of sensing baseline. The rate of gas adsorption follows the Langmuir-type isotherm as a function of gas concentration and scales with film thickness. This rate is up to 5 times higher in the composite than only with an SWCNT network in the transistor channel, which in turn results in a 7-fold shorter time constant of adsorption with the composite. The description of gas adsorption developed in the present work is generic for all semiconductors and the demonstrated composite with 3D percolating SWCNTs dispersed in functional polymer represents a promising new type of material for advanced gas sensors.

Conducted noise analysis and protection of 45 kJ/s, ±50 kV capacitor charging power supply when interfaced with repetitive Marx based pulse power system.

PubMed

Naresh, P; Patel, Ankur; Sharma, Archana

2015-09-01

Pulse power systems with highly dynamic loads like klystron, backward wave oscillator (BWO), and magnetron generate highly dynamic noise. This noise leads to frequent failure of controlled switches in the inverter stage of charging power supply. Designing a reliable and compatible power supply for pulse power applications is always a tricky job when charging rate is in multiples of 10 kJ/s. A ±50 kV and 45 kJ/s capacitor charging power supply based on 4th order LCLC resonant topology has been developed for a 10 Hz repetitive Marx based system. Conditions for load independent constant current and zero current switching (ZCS) are derived mathematically. Noise generated at load end due to dynamic load is tackled effectively and reduction in magnitude noise voltage is achieved by providing shielding between primary and secondary of high voltage high frequency transformer and with LCLC low pass filter. Shielding scales down the ratio between coupling capacitance (Cc) and the collector-emitter capacitance of insulated gate bi-polar transistor switch, which in turn reduces the common mode noise voltage magnitude. The proposed 4th order LCLC resonant network acts as a low pass filter for differential mode noise in the reverse direction (from load to source). Power supply has been tested repeatedly with 5 Hz repetition rate with repetitive Marx based system connected with BWO load working fine without failure of single switch in the inverter stage.

Conducted noise analysis and protection of 45 kJ/s, ±50 kV capacitor charging power supply when interfaced with repetitive Marx based pulse power system

NASA Astrophysics Data System (ADS)

Naresh, P.; Patel, Ankur; Sharma, Archana

2015-09-01

Pulse power systems with highly dynamic loads like klystron, backward wave oscillator (BWO), and magnetron generate highly dynamic noise. This noise leads to frequent failure of controlled switches in the inverter stage of charging power supply. Designing a reliable and compatible power supply for pulse power applications is always a tricky job when charging rate is in multiples of 10 kJ/s. A ±50 kV and 45 kJ/s capacitor charging power supply based on 4th order LCLC resonant topology has been developed for a 10 Hz repetitive Marx based system. Conditions for load independent constant current and zero current switching (ZCS) are derived mathematically. Noise generated at load end due to dynamic load is tackled effectively and reduction in magnitude noise voltage is achieved by providing shielding between primary and secondary of high voltage high frequency transformer and with LCLC low pass filter. Shielding scales down the ratio between coupling capacitance (Cc) and the collector-emitter capacitance of insulated gate bi-polar transistor switch, which in turn reduces the common mode noise voltage magnitude. The proposed 4th order LCLC resonant network acts as a low pass filter for differential mode noise in the reverse direction (from load to source). Power supply has been tested repeatedly with 5 Hz repetition rate with repetitive Marx based system connected with BWO load working fine without failure of single switch in the inverter stage.

Human Pulse Wave Measurement by MEMS Electret Condenser Microphone

NASA Astrophysics Data System (ADS)

Nomura, Shusaku; Hanasaka, Yasushi; Ishiguro, Tadashi; Ogawa, Hiroshi

A micro Electret Condenser Microphone (ECM) fabricated by Micro Electro Mechanical System (MEMS) technology was employed as a novel apparatus for human pulse wave measurement. Since ECM frequency response characteristic, i.e. sensitivity, logically maintains a constant level at lower than the resonance frequency (stiffness control), the slightest pressure difference at around 1.0Hz generated by human pulse wave is expected to detect by MEMS-ECM. As a result of the verification of frequency response of MEMS-ECM, it was found that -20dB/dec of reduction in the sensitivity around 1.0Hz was engendered by a high input-impedance amplifier, i.e. the field effect transistor (FET), mounted near MEMS chip for amplifying tiny ECM signal. Therefore, MEMS-ECM is assumed to be equivalent with a differentiation circuit at around human pulse frequency. Introducing compensation circuit, human pulse wave was successfully obtained. In addition, the radial and ulnar artery tracing, and pulse wave velocity measurement at forearm were demonstrated; as illustrating a possible application of this micro device.

Ion-selective electrolyte-gated field-effect transistors: prerequisites for proper functioning

NASA Astrophysics Data System (ADS)

Kofler, Johannes; Schmoltner, Kerstin; List-Kratochvil, Emil J. W.

2014-10-01

Electrolyte-gated organic field-effect transistors (EGOFETs) used as transducers and amplifiers in potentiometric sensors have recently attracted a significant amount of scientific interest. For that reason, the fundamental prerequisites to achieve a proper potentiometric signal amplification and transduction are examined. First, polarizable as well as non-polarizable semiconductor- and gate-electrolyte- interface combinations are investigated by normal pulse voltammetry. The results of these measurements are correlated with the corresponding transistor characteristics, clarifying the functional principle of EGOFETs and the requirements for high signal amplification. In addition to a good electrical performance, the EGOFET-transducers should also be compatible with the targeted sensing application. Accordingly, the influence of different gate materials and electrolytes on the sensing abilities, are discussed. Even though all physical requirements are met, EGOFETs typically exhibit irreversible degradation, if the gate potential exceeds a certain level. For that reason, EGOFETs have to be operated using a constant source-drain operation mode which is presented by means of an H+ (pH) sensitive ion-sensor.

Flexible polymer transistors with high pressure sensitivity for application in electronic skin and health monitoring

NASA Astrophysics Data System (ADS)

Schwartz, Gregor; Tee, Benjamin C.-K.; Mei, Jianguo; Appleton, Anthony L.; Kim, Do Hwan; Wang, Huiliang; Bao, Zhenan

2013-05-01

Flexible pressure sensors are essential parts of an electronic skin to allow future biomedical prostheses and robots to naturally interact with humans and the environment. Mobile biomonitoring in long-term medical diagnostics is another attractive application for these sensors. Here we report the fabrication of flexible pressure-sensitive organic thin film transistors with a maximum sensitivity of 8.4 kPa-1, a fast response time of <10 ms, high stability over >15,000 cycles and a low power consumption of <1 mW. The combination of a microstructured polydimethylsiloxane dielectric and the high-mobility semiconducting polyisoindigobithiophene-siloxane in a monolithic transistor design enabled us to operate the devices in the subthreshold regime, where the capacitance change upon compression of the dielectric is strongly amplified. We demonstrate that our sensors can be used for non-invasive, high fidelity, continuous radial artery pulse wave monitoring, which may lead to the use of flexible pressure sensors in mobile health monitoring and remote diagnostics in cardiovascular medicine.

Flexible polymer transistors with high pressure sensitivity for application in electronic skin and health monitoring.

PubMed

Schwartz, Gregor; Tee, Benjamin C-K; Mei, Jianguo; Appleton, Anthony L; Kim, Do Hwan; Wang, Huiliang; Bao, Zhenan

2013-01-01

Flexible pressure sensors are essential parts of an electronic skin to allow future biomedical prostheses and robots to naturally interact with humans and the environment. Mobile biomonitoring in long-term medical diagnostics is another attractive application for these sensors. Here we report the fabrication of flexible pressure-sensitive organic thin film transistors with a maximum sensitivity of 8.4 kPa(-1), a fast response time of <10 ms, high stability over >15,000 cycles and a low power consumption of <1 mW. The combination of a microstructured polydimethylsiloxane dielectric and the high-mobility semiconducting polyisoindigobithiophene-siloxane in a monolithic transistor design enabled us to operate the devices in the subthreshold regime, where the capacitance change upon compression of the dielectric is strongly amplified. We demonstrate that our sensors can be used for non-invasive, high fidelity, continuous radial artery pulse wave monitoring, which may lead to the use of flexible pressure sensors in mobile health monitoring and remote diagnostics in cardiovascular medicine.

Influence of pre-annealing of printed silver electrodes on ultrafast laser ablation of short thin-film transistor channels on flexible substrates

NASA Astrophysics Data System (ADS)

Wiig, M. S.; You, C. C.; Brox-Nilsen, C.; Foss, S. E.

2018-02-01

The cutoff frequency and current from an organic thin-film transistor (OTFT) are strongly dependent on the length and to some extent on the uniformity of the transistor channel. Reducing the channel length can improve the OTFT performance with the increase in the current and frequency. Picosecond laser ablation of the printed Ag electrodes, compatible with roll-to-roll fabrication, has been investigated. The ablation threshold was found to be similar for the laser wavelengths tested: 515 nm and 1030 nm. Short transistor channels could be opened both after light annealing at 70 °C and after annealing at 140 °C. The channels in the lightly cured films had a significantly less scale formation, which is critical for avoiding shunts in the device. By moving from bottom electrodes fully defined by printing to the bottom electrodes where the transistor channel is opened by the laser, the channel length could be reduced from 40 μm to less than 5 μm.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Repetitive Transcranial Magnetic Stimulator with Controllable Pulse Parameters

PubMed Central

Peterchev, Angel V; Murphy, David L; Lisanby, Sarah H

2013-01-01

The characteristics of transcranial magnetic stimulation (TMS) pulses influence the physiological effect of TMS. However, available TMS devices allow very limited adjustment of the pulse parameters. We describe a novel TMS device that uses a circuit topology incorporating two energy storage capacitors and two insulated-gate bipolar transistor (IGBT) modules to generate near-rectangular electric field pulses with adjustable number, polarity, duration, and amplitude of the pulse phases. This controllable pulse parameter TMS (cTMS) device can induce electric field pulses with phase widths of 10–310 μs and positive/negative phase amplitude ratio of 1–56. Compared to conventional monophasic and biphasic TMS, cTMS reduces energy dissipation by up to 82% and 57%, and decreases coil heating by up to 33% and 41%, respectively. We demonstrate repetitive TMS trains of 3,000 pulses at frequencies up to 50 Hz with electric field pulse amplitude and width variability less than the measurement resolution (1.7% and 1%, respectively). Offering flexible pulse parameter adjustment and reduced power consumption and coil heating, cTMS enhances existing TMS paradigms, enables novel research applications, and could lead to clinical applications with potentially enhanced potency. PMID:21540487

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

NASA Astrophysics Data System (ADS)

Curry, M. J.; England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carr, S. M.; Carroll, M. S.

2015-05-01

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10-100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

NASA Astrophysics Data System (ADS)

Zhou, Hong; Maize, Kerry; Qiu, Gang; Shakouri, Ali; Ye, Peide D.

2017-08-01

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

80 MeV C{sup 6+} ion irradiation effects on the DC electrical characteristics of silicon NPN power transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bharathi, M. N.; Vinayakprasanna, N. H.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in

The total dose effects of 80 MeV C{sup 6+} ions on the DC electrical characteristics of Silicon NPN rf power transistors have been studied in the dose range of 100 krad to 100 Mrad. The SRIM simulation was used to understand the energy loss and range of the ions in the transistor structure. The different electrical parameters such as Gummel characteristics, excess base current (ΔI{sub B} = I{sub Bpost} - I{sub Bpre}), dc forward current gain (h{sub FE}), transconductance (g{sub m}), displacement damage factor (K) and output characteristics (V{sub CE}-I{sub C}) were studied systematically before and after irradiation. The significantmore » degradation in base current (I{sub B}) and h{sub FE} was observed after irradiation. Isochronal annealing study was conducted on the irradiated transistors to analyze the recovery in different electrical parameters. These results were compared with {sup 60}C0 gamma irradiation results in the same dose range.« less

Contact-metal dependent current injection in pentacene thin-film transistors

NASA Astrophysics Data System (ADS)

Wang, S. D.; Minari, T.; Miyadera, T.; Tsukagoshi, K.; Aoyagi, Y.

2007-11-01

Contact-metal dependent current injection in top-contact pentacene thin-film transistors is analyzed, and the local mobility in the contact region was found to follow the Meyer-Neldel rule. An exponential trap distribution, rather than the metal/organic hole injection barrier, is proposed to be the dominant factor of the contact resistance in pentacene thin-film transistors. The variable temperature measurements revealed a much narrower trap distribution in the copper contact compared with the corresponding gold contact, and this is the origin of the smaller contact resistance for copper despite a lower work function.

Base drive for paralleled inverter systems

NASA Technical Reports Server (NTRS)

Nagano, S. (Inventor)

1980-01-01

In a paralleled inverter system, a positive feedback current derived from the total current from all of the modules of the inverter system is applied to the base drive of each of the power transistors of all modules, thereby to provide all modules protection against open or short circuit faults occurring in any of the modules, and force equal current sharing among the modules during turn on of the power transistors.

DC switching regulated power supply for driving an inductive load

DOEpatents

Dyer, George R.

1986-01-01

A power supply for driving an inductive load current from a dc power supply hrough a regulator circuit including a bridge arrangement of diodes and switching transistors controlled by a servo controller which regulates switching in response to the load current to maintain a selected load current. First and second opposite legs of the bridge are formed by first and second parallel-connected transistor arrays, respectively, while the third and fourth legs of the bridge are formed by appropriately connected first and second parallel connected diode arrays, respectively. The regulator may be operated in three "stages" or modes: (1) For current runup in the load, both first and second transistor switch arrays are turned "on" and current is supplied to the load through both transistor arrays. (2) When load current reaches the desired level, the first switch is turned "off", and load current "flywheels" through the second switch array and the fourth leg diode array connecting the second switch array in series with the load. Current is maintained by alternating between modes 1 and 2 at a suitable duty cycle and switching rate set by the controller. (3) Rapid current rundown is accomplished by turning both switch arrays "off", allowing load current to be dumped back into the source through the third and fourth diode arrays connecting the source in series opposition with the load to recover energy from the inductive load. The three operating states are controlled automatically by the controller.

Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

2007-12-01

This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.; Schwarze, Gene E.

2005-01-01

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Electrical characterization of the temperature dependence in CdTe/CdS heterojunctions deposited in-situ by pulsed laser deposition

NASA Astrophysics Data System (ADS)

Avila-Avendano, Jesus; Quevedo-Lopez, Manuel; Young, Chadwin

2018-02-01

The I-V and C-V characteristics of CdTe/CdS heterojunctions deposited in-situ by Pulsed Laser Deposition (PLD) were evaluated. In-situ deposition enables the study of the CdTe/CdS interface by avoiding potential impurities at the surface and interface as a consequence of exposure to air. The I-V and C-V characteristics of the resulting junctions were obtained at different temperatures, ranging from room temperature to 150 °C, where the saturation current (from 10-8 to 10-4 A/cm2), ideality factor (between 1 and 2), series resistance (from 102 to 105 Ω), built-in potential (0.66-0.7 V), rectification factor (˜106), and carrier concentration (˜1016 cm-3) were obtained. The current-voltage temperature dependence study indicates that thermionic emission is the main transport mechanism at the CdTe/CdS interface. This study also demonstrated that the built-in potential (Vbi) calculated using a thermionic emission model is more accurate than that calculated using C-V extrapolation since C-V plots showed a Vbi shift as a function of frequency. Although CdTe/CdS is widely used for photovoltaic applications, the parameters evaluated in this work indicate that CdTe/CdS heterojunctions could be used as rectifying diodes and junction field effect transistors (JFETs). JFETs require a low PN diode saturation current, as demonstrated for the CdTe/CdS junction studied here.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

High-performance vertical organic transistors.

PubMed

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Low-noise current amplifier based on mesoscopic Josephson junction.

PubMed

Delahaye, J; Hassel, J; Lindell, R; Sillanpää, M; Paalanen, M; Seppä, H; Hakonen, P

2003-02-14

We used the band structure of a mesoscopic Josephson junction to construct low-noise amplifiers. By taking advantage of the quantum dynamics of a Josephson junction, i.e., the interplay of interlevel transitions and the Coulomb blockade of Cooper pairs, we created transistor-like devices, Bloch oscillating transistors, with considerable current gain and high-input impedance. In these transistors, the correlated supercurrent of Cooper pairs is controlled by a small base current made up of single electrons. Our devices reached current and power gains on the order of 30 and 5, respectively. The noise temperature was estimated to be around 1 kelvin, but noise temperatures of less than 0.1 kelvin can be realistically achieved. These devices provide quantum-electronic building blocks that will be useful at low temperatures in low-noise circuit applications with an intermediate impedance level.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain.

PubMed

Lee, Sungsik; Nathan, Arokia

2016-10-21

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation. Copyright © 2016, American Association for the Advancement of Science.

Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naquin, Clint; Lee, Mark; Edwards, Hal

2014-11-24

Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility ofmore » exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.« less

AlN/GaN heterostructures for normally-off transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

High performance thyratron driver with low jitter.

PubMed

Verma, Rishi; Lee, P; Springham, S V; Tan, T L; Rawat, R S

2007-08-01

We report the design and development of insulated gate bipolar junction transistor based high performance driver for operating thyratrons in grounded grid mode. With careful design, the driver meets the specification of trigger output pulse rise time less than 30 ns, jitter less than +/-1 ns, and time delay less than 160 ns. It produces a -600 V pulse of 500 ns duration (full width at half maximum) at repetition rate ranging from 1 Hz to 1.14 kHz. The developed module also facilitates heating and biasing units along with protection circuitry in one complete package.

Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

NASA Astrophysics Data System (ADS)

Shauly, Eitan; Rotstein, Israel; Peltinov, Ram; Latinski, Sergei; Adan, Ofer; Levi, Shimon; Menadeva, Ovadya

2009-03-01

The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmaxTM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

NASA Technical Reports Server (NTRS)

Duong, Tuan A.

2012-01-01

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

The total switch time of silicon bipolar transistors with base doping gradients or with germanium gradients in the base

NASA Astrophysics Data System (ADS)

Karlsteen, M.; Willander, M.

1993-11-01

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (α N) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (α N) that has to be kept within a narrow range to keep the total switch time low.

Cathodoluminescence Study of Hafnium Oxide

NASA Astrophysics Data System (ADS)

Purcell, Emily; Hengehold, Robert; McClory, John

2011-10-01

Hafnium dioxide (HfO2) is increasingly being used in place of silicon oxide as a gate insulator in field effect transistors. This is primarily due to its high dielectric constant, κ, of 25. Samples of HfO2 were grown by either atomic layer deposition (ALD) or pulsed laser deposition (PLD), with the PLD samples having assorted substrate temperatures during deposition (300 C, 500 C, and 750 C). Cathodoluminescence (CL) was chosen as the technique used for studying these HfO2 samples. The CL system used was capable of beam energies ranging from 1 keV to 20 keV and beam currents ranging from 10 μA to 50 μA. A Monte Carlo calculation using CASINO software was performed in order to determine the beam energy for the desired depth of penetration. Measurements were taken at sample temperatures ranging from 7K (closed cycled cryostat) to 300K (room temperature), as well as at various beam energies and beam currents. Comparison will be made between the PLD and ALD spectra.

Electron cyclotron heating/current-drive system using high power tubes for QUEST spherical tokamak

NASA Astrophysics Data System (ADS)

Onchi, Takumi; Idei, H.; Hasegawa, M.; Nagata, T.; Kuroda, K.; Hanada, K.; Kariya, T.; Kubo, S.; Tsujimura, T. I.; Kobayashi, S.; Quest Team

2017-10-01

Electron cyclotron heating (ECH) is the primary method to ramp up plasma current non-inductively in QUEST spherical tokamak. A 28 GHz gyrotron is employed for short pulses, where the radio frequency (RF) power is about 300 kW. Current ramp-up efficiency of 0.5 A/W has been obtained with focused beam of the second harmonic X-mode. A quasi-optical polarizer unit has been newly installed to avoid arcing events. For steady-state tokamak operation, 8.56 GHz klystron with power of 200 kW is used as the CW-RF source. The high voltage power supply (54 kV/13 A) for the klystron has been built recently, and initial bench test of the CW-ECH system is starting. The array of insulated-gate bipolar transistor works to quickly cut off the input power for protecting the klystron. This work is supported by JSPS KAKENHI (15H04231), NIFS Collaboration Research program (NIFS13KUTR085, NIFS17KUTR128), and through MEXT funding for young scientists associated with active promotion of national university reforms.

Ripple gate drive circuit for fast operation of series connected IGBTs

DOEpatents

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

1.55 Micrometer Sub-Micron Finger, Interdigitated MSM Photodetector Arrays with Low Dark Current

DTIC Science & Technology

2010-02-02

pf a- IGZO TFTs. IV. RF Characteristics of Room Temperature Deposited Indium Zinc Oxide Thin - Film Transistors Depletion-mode indium zinc...III. High Performance Indium Gallium Zinc Oxide Thin Film Transistors Fabricated On Polyethylene Terephthalate Substrates High-performance...amorphous (a-) InGaZnO-based thin film transistors (TFTs) were fabricated on flexible polyethylene terephthalate (PET) substrates coated with indium

Rail-to-rail differential input amplification stage with main and surrogate differential pairs

DOEpatents

Britton, Jr., Charles Lanier; Smith, Stephen Fulton

2007-03-06

An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Lee, Yong Hee; Joo, Seung Ki

2017-06-01

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. He received the B.S. degree in School of Advanced Materials Engineering from Kookmin University, Seoul, South Korea in 2012, and the M.S. degree in Department of Materials Science and Engineering from Seoul National University, Seoul, South Korea in 2014. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and top-gate polycrystalline-silicon thin-film transistors. He received the M.S. degree in innovation technology from Ecol Polytechnique, Palaiseau, France in 2013. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and copper-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1974, and the M.S. and Ph.D. degrees in material science and engineering from Stanford University, Stanford, CA, USA, in 1980 and 1983, respectively. He is currently a Professor with the Department of Materials Science and Engineering, Seoul National University, Seoul.

Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

NASA Astrophysics Data System (ADS)

Santato, Clara

2015-10-01

The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

Effect of OFF-state stress induced electric field on trapping in AlGaN/GaN high electron mobility transistors on Si (111)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anand, M. J., E-mail: anand2@e.ntu.edu.sg, E-mail: eging@ntu.edu.sg; Ng, G. I., E-mail: anand2@e.ntu.edu.sg, E-mail: eging@ntu.edu.sg; Syamal, B.

2015-02-23

The influence of electric field (EF) on the dynamic ON-resistance (dyn-R{sub DS[ON]}) and threshold-voltage shift (ΔV{sub th}) of AlGaN/GaN high electron mobility transistors on Si has been investigated using pulsed current-voltage (I{sub DS}-V{sub DS}) and drain current (I{sub D}) transients. Different EF was realized with devices of different gate-drain spacing (L{sub gd}) under the same OFF-state stress. Under high-EF (L{sub gd} = 2 μm), the devices exhibited higher dyn-R{sub DS[ON]} degradation but a small ΔV{sub th} (∼120 mV). However, at low-EF (L{sub gd} = 5 μm), smaller dyn-R{sub DS[ON]} degradation but a larger ΔV{sub th} (∼380 mV) was observed. Our analysis shows that under OFF-state stress, the gatemore » electrons are injected and trapped in the AlGaN barrier by tunnelling-assisted Poole-Frenkel conduction mechanism. Under high-EF, trapping spreads towards the gate-drain access region of the AlGaN barrier causing dyn-R{sub DS[ON]} degradation, whereas under low-EF, trapping is mostly confined under the gate causing ΔV{sub th}. A trap with activation energy 0.33 eV was identified in the AlGaN barrier by I{sub D}-transient measurements. The influence of EF on trapping was also verified by Silvaco TCAD simulations.« less

Coherent molecular transistor: control through variation of the gate wave function.

PubMed

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Investigation of the ferroelectric switching behavior of P(VDF-TrFE)-PMMA blended films for synaptic device applications

NASA Astrophysics Data System (ADS)

Kim, E. J.; Kim, K. A.; Yoon, S. M.

2016-02-01

Synaptic plasticity can be mimicked by electronic synaptic devices. By using ferroelectric thin films as gate insulator for thin-film transistors (TFT), channel conductance can be defined as the synaptic plasticity, and gradually modulated by the variations in amounts of aligned ferroelectric dipoles. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)]-poly(methyl methacrylate) (PMMA) blended films are chosen and their switching kinetics are investigated by using the Kolmogorov-Avrami-Ishibashi model. The switching time for ferroelectric polarization is sensitively influenced by the amplitude of applied electric field and volumetric ratio of ferroelectric beta-phases in the P(VDF-TrFE)-PMMA films. The switching time of the P(VDF-TrFE) increases with decreasing the pulse amplitude and/or the ratio of ferroelectric beta-phases by incorporation of PMMA. The activation electric field is also found to increase as the increase in blended amount of PMMA. Synapse TFTs are fabricated using the P(VDF-TrFE)-PMMA as gate insulator and In-Ga-Zn-O active channels. The drain currents of the synapse TFTs gradually increased when the voltage pulse signals with given duration are repeatedly applied. This suggests that the synaptic weights can be modulated by the number of external pulse signals, and that the proposed synapse TFT can be applied for mimicking the operations of bio-synapses.

A New Mirroring Circuit for Power MOS Current Sensing Highly Immune to EMI

PubMed Central

Aiello, Orazio; Fiori, Franco

2013-01-01

This paper deals with the monitoring of power transistor current subjected to radio-frequency interference. In particular, a new current sensor with no connection to the power transistor drain and with improved performance with respect to the existing current-sensing schemes is presented. The operation of the above mentioned current sensor is discussed referring to time-domain computer simulations. The susceptibility of the proposed circuit to radio-frequency interference is evaluated through time-domain computer simulations and the results are compared with those obtained for a conventional integrated current sensor. PMID:23385408

Single-phase frequency converter

NASA Astrophysics Data System (ADS)

Baciu, I.; Cunţan, C. D.

2017-01-01

The paper presents a continuous voltage inverter - AC (12V / 230V) made with IGBT and two-stage voltage transformer. The sequence control transistors is achieved using a ring counter whose clock signal is obtained with a monostable circuit LM 555. The frequency of the clock signal can be adjustment with a potentiometer that modifies the charging current of the capacitor which causes constant monostable circuit time. Command sequence consists of 8 intervals of which 6 are assigned to command four transistors and two for the period break at the beginning and end of the sequence control. To obtain an alternation consisting of two different voltage level, two transistors will be comanded, connected to different windings of the transformer and the one connected to the winding providing lower voltage must be comanded twice. The output of the numerator goes through an inverter type MOS and a current amplifier with bipolar transistor.To achieve galvanic separation, an optocoupler will be used for each IGBT transistor, while protection is achieved with resistance and diode circuit. At the end there is connected an LC filter for smoothing voltage variations.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

A Flush Toilet Model for the Transistor

NASA Astrophysics Data System (ADS)

Organtini, Giovanni

2012-04-01

In introductory physics textbooks, diodes working principles are usually well described in a relatively simple manner. According to our experience, they are well understood by students. Even when no formal derivation of the physics laws governing the current flow through a diode is given, the use of this device as a check valve is easily accepted. This is not true for transistors. In most textbooks the behavior of a transistor is given without formal explanation. When the amplification is computed, for some reason, students have difficulties in identifying the basic physical mechanisms that give rise to such an effect. In this paper we give a simple and captivating illustration of the working principles of a transistor as an amplifier, tailored to high school students even with almost no background in electronics nor in modern physics. We assume that the target audience is familiar with the idea that a diode works as a check valve for currents. The lecture emphasis is on the illustration of physics principles governing the behavior of a transistor, rather than on a formal description of the processes leading to amplification.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

PubMed

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

a High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder

NASA Astrophysics Data System (ADS)

Shrivas, Jayram; Akashe, Shyam; Tiwari, Nitesh

2013-06-01

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

PubMed

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Vertical architecture for enhancement mode power transistors based on GaN nanowires

NASA Astrophysics Data System (ADS)

Yu, F.; Rümmler, D.; Hartmann, J.; Caccamo, L.; Schimpke, T.; Strassburg, M.; Gad, A. E.; Bakin, A.; Wehmann, H.-H.; Witzigmann, B.; Wasisto, H. S.; Waag, A.

2016-05-01

The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

Detecting a Protein in its Natural Environment with a MOSFET Transistor

NASA Astrophysics Data System (ADS)

Perez, Benjamin; Balijepalli, Arvind

2015-03-01

Our group's goal is to make a MOSFET transistor that has a nanopore through it. We want to have proteins flow through this device and examine their structure based on the modulation they cause on the current. This process does not harm the protein and allows the protein to be studied in its natural environment. The electric field and electric potential of a point charge were computed within a nano-transistor. The simulations were used to see if the point charge had enough influence on the current to cause a modulation. The point charge did cause a rise in the current making the modulation concept a viable one for medical applications. COMSOL metaphysics software was used to perform all simulations. The Society of Physics Students internship program and NIST.

Properties and Applications of Varistor-Transistor Hybrid Devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Stapleton, William A.; Sutanto, Ivan; Scantlin, Amanda A.; Lin, Sidney

2014-05-01

The nonlinear current-voltage characteristics of a varistor device are modified with the help of external agents, resulting in tuned varistor-transistor hybrid devices with multiple applications. The substrate used to produce these hybrid devices belongs to the modified iron titanate family with chemical formula 0.55FeTiO3·0.45Fe2O3 (IHC45), which is a prominent member of the ilmenite-hematite solid-solution series. It is a wide-bandgap magnetic oxide semiconductor. Electrical resistivity and Seebeck coefficient measurements from room temperature to about 700°C confirm that it retains its p-type nature for the entire temperature range. The direct-current (DC) and alternating-current (AC) properties of these hybrid devices are discussed and their applications identified. It is shown here that such varistor embedded ceramic transistors with many interesting properties and applications can be mass produced using incredibly simple structures. The tuned varistors by themselves can be used for current amplification and band-pass filters. The transistors on the other hand could be used to produce sensors, voltage-controlled current sources, current-controlled voltage sources, signal amplifiers, and low-band-pass filters. We believe that these devices could be suitable for a number of applications in consumer and defense electronics, high-temperature and space electronics, bioelectronics, and possibly also for electronics specific to handheld devices.

Detection of pulsed bremsstrahlung-induced prompt neutron capture gamma rays with a HPGe detector

NASA Astrophysics Data System (ADS)

Jones, James L.

1997-02-01

The Idaho National Engineering Laboratory (INEL) is developing a novel photoneutron-based nondestructive evaluation technique which uses a pulsed, high-energy electron accelerator and gamma-ray spectrometry. Highly penetrating pulses of bremsstrahlung photons are produced by each pulse of electrons. Interrogating neutrons are generated by the bremsstrahlung photons interacting within a photoneutron source material. The interactions of the neutrons within a target result in the emission of elemental characteristic gamma-rays. Spectrometry is performed by analyzing the photoneutron-induced, prompt gama-rays acquired between accelerator pulses with a unique, high- purity germanium gamma-ray detection system using a modified transistor reset preamplifier. The detection system, the experimental configuration, and the accelerator operation used to characterize the detection systems performance are described. Using a 6.5-MeV electron accelerator and a beryllium metal photoneutron source, gamma-ray spectra were successfully acquired for Al, Cu, polyethylene, NaCl, and depleted uranium targets as soon as 30 microsecond(s) after each bremsstrahlung flash.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Soft-type trap-induced degradation of MoS2 field effect transistors.

PubMed

Cho, Young-Hoon; Ryu, Min-Yeul; Lee, Kook Jin; Park, So Jeong; Choi, Jun Hee; Lee, Byung-Chul; Kim, Wungyeon; Kim, Gyu-Tae

2018-06-01

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS 2 multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation-correlated mobility fluctuation (CNF-CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF-CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS 2 FETs.

Soft-type trap-induced degradation of MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Cho, Young-Hoon; Ryu, Min-Yeul; Lee, Kook Jin; Park, So Jeong; Choi, Jun Hee; Lee, Byung-Chul; Kim, Wungyeon; Kim, Gyu-Tae

2018-06-01

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS2 multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation–correlated mobility fluctuation (CNF–CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF–CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS2 FETs.

Overload-protector/fault-indicator circuit

NASA Technical Reports Server (NTRS)

Paluka, J. R.; Moore, S. F.

1977-01-01

Circuit incorporates three-terminal current limiter (78M24) to increase overall reliability and to eliminate transistor burnouts resulting from shorted interconnection lines and other overloads. Fact-acting light emitting diodes across the limiters show status of transistor output circuits.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

PubMed

Kunc, Jan; Hu, Yike; Palmer, James; Guo, Zelei; Hankinson, John; Gamal, Salah H; Berger, Claire; de Heer, Walt A

2014-09-10

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Linear conduction in N-type organic field effect transistors with nanometric channel lengths and graphene as electrodes

NASA Astrophysics Data System (ADS)

Chianese, F.; Candini, A.; Affronte, M.; Mishra, N.; Coletti, C.; Cassinese, A.

2018-05-01

In this work, we test graphene electrodes in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivative. By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied bias, in contrast with the supralinear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrode devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ˜140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current in short channel OFETs.

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

Large-signal model of the bilayer graphene field-effect transistor targeting radio-frequency applications: Theory versus experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pasadas, Francisco, E-mail: Francisco.Pasadas@uab.cat; Jiménez, David

2015-12-28

Bilayer graphene is a promising material for radio-frequency transistors because its energy gap might result in a better current saturation than the monolayer graphene. Because the great deal of interest in this technology, especially for flexible radio-frequency applications, gaining control of it requires the formulation of appropriate models for the drain current, charge, and capacitance. In this work, we have developed them for a dual-gated bilayer graphene field-effect transistor. A drift-diffusion mechanism for the carrier transport has been considered coupled with an appropriate field-effect model taking into account the electronic properties of the bilayer graphene. Extrinsic resistances have been includedmore » considering the formation of a Schottky barrier at the metal-bilayer graphene interface. The proposed model has been benchmarked against experimental prototype transistors, discussing the main figures of merit targeting radio-frequency applications.« less

Fabrication of amorphous InGaZnO thin-film transistor-driven flexible thermal and pressure sensors

NASA Astrophysics Data System (ADS)

Park, Ick-Joon; Jeong, Chan-Yong; Cho, In-Tak; Lee, Jong-Ho; Cho, Eou-Sik; Kwon, Sang Jik; Kim, Bosul; Cheong, Woo-Seok; Song, Sang-Hun; Kwon, Hyuck-In

2012-10-01

In this work, we present the results concerning the use of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) as a driving transistor of the flexible thermal and pressure sensors which are applicable to artificial skin systems. Although the a-IGZO TFT has been attracting much attention as a driving transistor of the next-generation flat panel displays, no study has been performed about the application of this new device to the driving transistor of the flexible sensors yet. The proposed thermal sensor pixel is composed of the series-connected a-IGZO TFT and ZnO-based thermistor fabricated on a polished metal foil, and the ZnO-based thermistor is replaced by the pressure sensitive rubber in the pressure sensor pixel. In both sensor pixels, the a-IGZO TFT acts as the driving transistor and the temperature/pressure-dependent resistance of the ZnO-based thermistor/pressure-sensitive rubber mainly determines the magnitude of the output currents. The fabricated a-IGZO TFT-driven flexible thermal sensor shows around a seven times increase in the output current as the temperature increases from 20 °C to 100 °C, and the a-IGZO TFT-driven flexible pressure sensors also exhibit high sensitivity under various pressure environments.

Controlling the mode of operation of organic transistors through side-chain engineering.

PubMed

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B; Bandiello, Enrico; Hanifi, David A; Sessolo, Michele; Malliaras, George G; McCulloch, Iain; Rivnay, Jonathan

2016-10-25

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors.

Controlling the mode of operation of organic transistors through side-chain engineering

PubMed Central

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B.; Bandiello, Enrico; Hanifi, David A.; Sessolo, Michele; Malliaras, George G.; McCulloch, Iain; Rivnay, Jonathan

2016-01-01

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors. PMID:27790983

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Curry, M. J.; Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131; Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification.more » The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.« less

High-power flexible AlGaN/GaN heterostructure field-effect transistors with suppression of negative differential conductance

NASA Astrophysics Data System (ADS)

Oh, Seung Kyu; Cho, Moon Uk; Dallas, James; Jang, Taehoon; Lee, Dong Gyu; Pouladi, Sara; Chen, Jie; Wang, Weijie; Shervin, Shahab; Kim, Hyunsoo; Shin, Seungha; Choi, Sukwon; Kwak, Joon Seop; Ryou, Jae-Hyun

2017-09-01

We investigate thermo-electronic behaviors of flexible AlGaN/GaN heterostructure field-effect transistors (HFETs) for high-power operation of the devices using Raman thermometry, infrared imaging, and current-voltage characteristics. A large negative differential conductance observed in HFETs on polymeric flexible substrates is confirmed to originate from the decreasing mobility of the two-dimensional electron gas channel caused by the self-heating effect. We develop high-power transistors by suppressing the negative differential conductance in the flexible HFETs using chemical lift-off and modified Ti/Au/In metal bonding processes with copper (Cu) tapes for high thermal conductivity and low thermal interfacial resistance in the flexible hybrid structures. Among different flexible HFETs, the ID of the HFETs on Cu with Ni/Au/In structures decreases only by 11.3% with increasing drain bias from the peak current to the current at VDS = 20 V, which is close to that of the HFETs on Si (9.6%), solving the problem of previous flexible AlGaN/GaN transistors.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays.

PubMed

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon; Hussain, Muhammad Mustafa

2018-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Cryogenic Preamplification of a Single-Electron-Transistor using a Silicon-Germanium Heterojunction-Bipolar-Transistor

DOE PAGES

Curry, Matthew J.; England, Troy Daniel; Bishop, Nathaniel; ...

2015-05-21

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. Furthermore, the transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to withoutmore » the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. We found that the circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.« less

Military Applications of Fiber Optics Technology

DTIC Science & Technology

1989-05-01

Research Projects Agency DNA Defense Nuclear Agency EMI Electromagnetic interference EMP Electromagnetic pulse FET Field effect transistor FOFA Follow...Organization SEED Self electro-optic effect device TBM Tactical ballistic missile TOW Tube launched, optically tracked, wire-guided UAV Unmanned aerial vehicle...systems, coupled with novel but effective transducing technology, have set the stage for a powerful class of fiber optic sensors. 8 Optical fibers have

A Direct Method to Extract Transient Sub-Gap Density of State (DOS) Based on Dual Gate Pulse Spectroscopy

NASA Astrophysics Data System (ADS)

Dai, Mingzhi; Khan, Karim; Zhang, Shengnan; Jiang, Kemin; Zhang, Xingye; Wang, Weiliang; Liang, Lingyan; Cao, Hongtao; Wang, Pengjun; Wang, Peng; Miao, Lijing; Qin, Haiming; Jiang, Jun; Xue, Lixin; Chu, Junhao

2016-06-01

Sub-gap density of states (DOS) is a key parameter to impact the electrical characteristics of semiconductor materials-based transistors in integrated circuits. Previously, spectroscopy methodologies for DOS extractions include the static methods, temperature dependent spectroscopy and photonic spectroscopy. However, they might involve lots of assumptions, calculations, temperature or optical impacts into the intrinsic distribution of DOS along the bandgap of the materials. A direct and simpler method is developed to extract the DOS distribution from amorphous oxide-based thin-film transistors (TFTs) based on Dual gate pulse spectroscopy (GPS), introducing less extrinsic factors such as temperature and laborious numerical mathematical analysis than conventional methods. From this direct measurement, the sub-gap DOS distribution shows a peak value on the band-gap edge and in the order of 1017-1021/(cm3·eV), which is consistent with the previous results. The results could be described with the model involving both Gaussian and exponential components. This tool is useful as a diagnostics for the electrical properties of oxide materials and this study will benefit their modeling and improvement of the electrical properties and thus broaden their applications.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

PubMed

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Multifunctional pulse generator for high-intensity focused ultrasound system

NASA Astrophysics Data System (ADS)

Tamano, Satoshi; Yoshizawa, Shin; Umemura, Shin-Ichiro

2017-07-01

High-intensity focused ultrasound (HIFU) can achieve high spatial resolution for the treatment of diseases. A major technical challenge in implementing a HIFU therapeutic system is to generate high-voltage high-current signals for effectively exciting a multichannel HIFU transducer at high efficiencies. In this paper, we present the development of a multifunctional multichannel generator/driver. The generator can produce a long burst as well as an extremely high-voltage short pulse of pseudosinusoidal waves (trigger HIFU) and second-harmonic superimposed waves for HIFU transmission. The transmission timing, waveform, and frequency can be controlled using a field-programmable gate array (FPGA) via a universal serial bus (USB) microcontroller. The hardware is implemented in a compact printed circuit board. The test results of trigger HIFU reveal that the power consumption and the temperature rise of metal-oxide semiconductor field-effect transistors were reduced by 19.9% and 38.2 °C, respectively, from the previous design. The highly flexible performance of the novel generator/driver is demonstrated in the generation of second-harmonic superimposed waves, which is useful for cavitation-enhanced HIFU treatment, although the previous design exhibited difficulty in generating it.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change inmore » drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.« less

The Effects of Low Dose-Rate Ionizing Radiation on the Shapes of Transients in the LM124 Operational Amplifier

NASA Technical Reports Server (NTRS)

Buchner, Stephen; McMorrow, Dale; Roche, Nicholas; Dusseau, Laurent; Pease, Ron L.

2008-01-01

Shapes of single event transients (SETs) in a linear bipolar circuit (LM124) change with exposure to total ionizing dose (TID) radiation. SETs shape changes are a direct consequence of TID-induced degradation of bipolar transistor gain. A reduction in transistor gain causes a reduction in the drive current of the current sources in the circuit, and it is the lower drive current that most affects the shapes of large amplitude SETs.

Landauer-Datta-Lundstrom model for terahertz transistor amplifier based on graphene

NASA Astrophysics Data System (ADS)

Davidovich, M. V.

2017-08-01

A transistor has been considered in the form of three electrodes connected by graphene ribbons or by metal quantum wires (nanowires) that operate on the principle of the current control by the changing voltage at the central electrode (gate). The analysis has been carried out according to the Landauer-Datta-Lundstrom model in equilibrium approximation for electrodes while fixing their potentials. We have obtained linear models and nonlinear terms in the determining current, and calculated the nonlinear current-voltage performances of graphene nanoribbons.

Organic electrochemical transistor array for recording transepithelial ion transport of human airway epithelial cells.

PubMed

Yao, Chunlei; Xie, Changyan; Lin, Peng; Yan, Feng; Huang, Pingbo; Hsing, I-Ming

2013-12-03

An organic electrochemical transistor array is integrated with human airway epithelial cells. This integration provides a novel method to couple transepithelial ion transport with electrical current. Activation and inhibition of transepithelial ion transport are readily detected with excellent time resolution. The organic electrochemical transistor array serves as a promising platform for physiological studies and drug testing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

NASA Technical Reports Server (NTRS)

Kim, Jae-Hoon; Lin, Steven H.

1991-01-01

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

PbSe Nanocrystal Solids for n- and p-Channel Thin Film Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Talapin, Dmitri V.; Murray, Christopher B.

2005-10-01

Initially poorly conducting PbSe nanocrystal solids (quantum dot arrays or superlattices) can be chemically ``activated'' to fabricate n- and p-channel field effect transistors with electron and hole mobilities of 0.9 and 0.2 square centimeters per volt-second, respectively; with current modulations of about 103 to 104; and with current density approaching 3 × 104 amperes per square centimeter. Chemical treatments engineer the interparticle spacing, electronic coupling, and doping while passivating electronic traps. These nanocrystal field-effect transistors allow reversible switching between n- and p-transport, providing options for complementary metal oxide semiconductor circuits and enabling a range of low-cost, large-area electronic, optoelectronic, thermoelectric, and sensing applications.

Logarithmic current measurement circuit with improved accuracy and temperature stability and associated method

DOEpatents

Ericson, M. Nance; Rochelle, James M.

1994-01-01

A logarithmic current measurement circuit for operating upon an input electric signal utilizes a quad, dielectrically isolated, well-matched, monolithic bipolar transistor array. One group of circuit components within the circuit cooperate with two transistors of the array to convert the input signal logarithmically to provide a first output signal which is temperature-dependant, and another group of circuit components cooperate with the other two transistors of the array to provide a second output signal which is temperature-dependant. A divider ratios the first and second output signals to provide a resultant output signal which is independent of temperature. The method of the invention includes the operating steps performed by the measurement circuit.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin

2015-08-24

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Space station power semiconductor package

NASA Technical Reports Server (NTRS)

Balodis, Vilnis; Berman, Albert; Devance, Darrell; Ludlow, Gerry; Wagner, Lee

1987-01-01

A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given.

Arc-Free High-Power dc Switch

NASA Technical Reports Server (NTRS)

Miller, W. N.; Gray, O. E.

1982-01-01

Hybrid switch allows high-power direct current to be turned on and off without arcing or erosion. Switch consists of bank of transistors in parallel with mechanical contacts. Transistor bank makes and breaks switched circuit; contacts carry current only during steady-state "on" condition. Designed for Space Shuttle orbiter, hybrid switch can be used also in high-power control circuits in aircraft, electric autos, industrial furnaces, and solar-cell arrays.

The 10 kW power electronics for hydrogen arcjets

NASA Technical Reports Server (NTRS)

Hamley, John A.; Pinero, Luis R.; Hill, Gerald M.

1992-01-01

A combination of emerging mission considerations such as 'launch on schedule', resource limitations, and the development of higher power spacecraft busses has resulted in renewed interest in high power hydrogen arcjet systems with specific impulses greater than 1000 s for Earth-space orbit transfer and maneuver applications. Solar electric propulsion systems with about 10 kW of power appear to offer payload benefits at acceptable trip times. This work outlines the design and development of 10 kW hydrogen arcjet power electronics and results of arcjet integration testing. The power electronics incorporated a full bridge switching topology similar to that employed in state of the art 5 kW power electronics, and the output filter included an output current averaging inductor with an integral pulse generation winding for arcjet ignition. Phase shifted, pulse width modulation with current mode control was used to regulate the current delivered to arcjet, and a low inductance power stage minimized switching transients. Hybrid power Metal Oxide Semiconductor Field Effect Transistors were used to minimize conduction losses. Switching losses were minimized using a fast response, optically isolated, totem-pole gate drive circuit. The input bus voltage for the unit was 150 V, with a maximum output voltage of 225 V. The switching frequency of 20 kHz was a compromise between mass savings and higher efficiency. Power conversion efficiencies in excess of 0.94 were demonstrated, along with steady state load current regulation of 1 percent. The power electronics were successfully integrated with a 10 kW laboratory hydrogen arcjet, and reliable, nondestructive starts and transitions to steady state operation were demonstrated. The estimated specific mass for a flight packaged unit was 2 kg/kW.

Interplay between Vacuum-Grown Monolayers of Alkylphosphonic Acids and the Performance of Organic Transistors Based on Dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene.

PubMed

Hannah, Stuart; Cardona, Javier; Lamprou, Dimitrios A; Šutta, Pavol; Baran, Peter; Al Ruzaiqi, Afra; Johnston, Karen; Gleskova, Helena

2016-09-28

Monolayers of six alkylphosphonic acids ranging from C8 to C18 were prepared by vacuum evaporation and incorporated into low-voltage organic field-effect transistors based on dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). Similar to solution-assembled monolayers, the molecular order for vacuum-deposited monolayers improved with increasing length of the aliphatic tail. At the same time, Fourier transform infrared (FTIR) measurements suggested lower molecular coverage for longer phosphonic acids. The comparison of FTIR and vibration frequencies calculated by density functional theory indicated that monodentate bonding does not occur for any phosphonic acid. All monolayers exhibited low surface energy of ∼17.5 mJ/m(2) with a dominating Lifshitz-van der Waals component. Their surface roughness was comparable, while the nanomechanical properties were varied but not correlated to the length of the molecule. However, large improvement in transistor performance was observed with increasing length of the aliphatic tail. Upon going from C8 to C18, the mean threshold voltage decreased from -1.37 to -1.24 V, the field-effect mobility increased from 0.03 to 0.33 cm(2)/(V·s), the off-current decreased from ∼8 × 10(-13) to ∼3 × 10(-13) A, and for transistors with L = 30 μm the on-current increased from ∼3 × 10(-8) to ∼2 × 10(-6) A, and the on/off-current ratio increased from ∼3 × 10(4) to ∼4 × 10(6). Similarly, transistors with longer phosphonic acids exhibited much better air and bias-stress stability. The achieved transistor performance opens up a completely "dry" fabrication route for ultrathin dielectrics and low-voltage organic transistors.

VOLTAGE REGULATOR

DOEpatents

Von Eschen, R.L.; Scheele, P.F.

1962-04-24

A transistorized voltage regulator which provides very close voitage regulation up to about 180 deg F is described. A diode in the positive line provides a constant voltage drop from the input to a regulating transistor emitter. An amplifier is coupled to the positive line through a resistor and is connected between a difference circuit and the regulating transistor base which is negative due to the difference in voltage drop across thc diode and the resistor so that a change in the regulator output causes the amplifier to increase or decrease the base voltage and current and incrcase or decrease the transistor impedance to return the regulator output to normal. (AEC)

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Acoustic transistor: Amplification and switch of sound by sound

NASA Astrophysics Data System (ADS)

Liang, Bin; Kan, Wei-wei; Zou, Xin-ye; Yin, Lei-lei; Cheng, Jian-chun

2014-08-01

We designed an acoustic transistor to manipulate sound in a manner similar to the manipulation of electric current by its electrical counterpart. The acoustic transistor is a three-terminal device with the essential ability to use a small monochromatic acoustic signal to control a much larger output signal within a broad frequency range. The output and controlling signals have the same frequency, suggesting the possibility of cascading the structure to amplify an acoustic signal. Capable of amplifying and switching sound by sound, acoustic transistors have various potential applications and may open the way to the design of conceptual devices such as acoustic logic gates.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Current-Induced Transistor Sensorics with Electrogenic Cells

PubMed Central

Fromherz, Peter

2016-01-01

The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned. PMID:27120627

VO2-based radiative thermal transistor with a semi-transparent base

NASA Astrophysics Data System (ADS)

Prod'homme, Hugo; Ordonez-Miranda, Jose; Ezzahri, Younès; Drévillon, Jérémie; Joulain, Karl

2018-05-01

We study a radiative thermal transistor analogous to an electronic one made of a VO2 base placed between two silica semi-infinite plates playing the roles of the transistor collector and emitter. The fact that VO2 exhibits an insulator to metal transition is exploited to modulate and/or amplify heat fluxes between the emitter and the collector, by applying a thermal current on the VO2 base. We extend the work of precedent studies considering the case where the base can be semi-transparent so that heat can be exchanged directly between the collector and the emitter. Both near and far field cases are considered leading to 4 typical regimes resulting from the fact that the emitter-base and base-collector separation distances can be larger or smaller than the thermal wavelength for a VO2 layer opaque or semi-transparent. Thermal currents variations with the base temperatures are calculated and analyzed. It is found that the transistor can operate in an amplification mode as already stated in [1] or in a switching mode as seen in [2]. An optimum configuration for the base thickness and separation distance maximizing the thermal transistor modulation factor is found.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

More Efficient Power Conversion for EVs: Gallium-Nitride Advanced Power Semiconductor and Packaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-02-01

Broad Funding Opportunity Announcement Project: Delphi is developing power converters that are smaller and more energy efficient, reliable, and cost-effective than current power converters. Power converters rely on power transistors which act like a very precisely controlled on-off switch, controlling the electrical energy flowing through an electrical circuit. Most power transistors today use silicon (Si) semiconductors. However, Delphi is using semiconductors made with a thin layer of gallium-nitride (GaN) applied on top of the more conventional Si material. The GaN layer increases the energy efficiency of the power transistor and also enables the transistor to operate at much higher temperatures,more » voltages, and power-density levels compared to its Si counterpart. Delphi is packaging these high-performance GaN semiconductors with advanced electrical connections and a cooling system that extracts waste heat from both sides of the device to further increase the device’s efficiency and allow more electrical current to flow through it. When combined with other electronic components on a circuit board, Delphi’s GaN power transistor package will help improve the overall performance and cost-effectiveness of HEVs and EVs.« less

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

NASA Astrophysics Data System (ADS)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized acoustic wave detection, high pitch sound diffraction pattern mapping, and directional listening. This system permits the direct visualization of a two dimensional sound field in a format that was previously inaccessible. In addition to the piezoelectric property, pyroelectricity is also exhibited by PVDF and is essential in the world of sensors. An integration of PVDF and OFET for the IR heat sensing is demonstrated to prove the concept of converting pyroelectric charge signal to a electric current signal. The basic pyroelectricity of PVDF sheet is first examined before making a organic transistor integrated IR sensor. Then, two types of architectures are designed and tested. The first one uses the structure similar to the PVDF strain sensor, and the second one uses a PVDF capacitor to gate the integrated OFETs. The conversion from pyroelectric signal to transistor current signal is observed and characterized. This design provides a flexible and gain-tunable version for IR heat sensors.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Zhichao, E-mail: zcyang.phys@gmail.com; Zhang, Yuewei; Nath, Digbijoy N.

We report on Gallium Nitride-based tunneling hot electron transistor amplifier with common-emitter current gain greater than 1. Small signal current gain up to 5 and dc current gain of 1.3 were attained in common-emitter configuration with collector current density in excess of 50 kA/cm{sup 2}. The use of a combination of 1 nm GaN/3 nm AlN layers as an emitter tunneling barrier was found to improve the energy collimation of the injected electrons. These results represent demonstration of unipolar vertical transistors in the III-nitride system that can potentially lead to higher frequency and power microwave devices.

On the wide-range bias dependence of transistor d.c. and small-signal current gain factors.

NASA Technical Reports Server (NTRS)

Schmidt, P.; Das, M. B.

1972-01-01

Critical reappraisal of the bias dependence of the dc and small-signal ac current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the dc base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Experimental results on representative n-p-n and p-n-p silicon devices are given which support most of the analytical findings.

Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Omura, Yasuhisa; Mori, Yoshiaki; Sato, Shingo; Mallik, Abhijit

2018-04-01

This paper discusses the role of trap-assisted-tunneling process in controlling the ON- and OFF-state current levels and its impacts on the current-voltage characteristics of a tunnel field-effect transistor. Significant impacts of high-density traps in the source region are observed that are discussed in detail. With regard to recent studies on isoelectronic traps, it has been discovered that deep level density must be minimized to suppress the OFF-state leakage current, as is well known, whereas shallow levels can be utilized to control the ON-state current level. A possible mechanism is discussed based on simulation results.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene-carbon nanotube transistors

NASA Astrophysics Data System (ADS)

Chae, Sang Hoon; Yu, Woo Jong; Bae, Jung Jun; Duong, Dinh Loc; Perello, David; Jeong, Hye Yun; Ta, Quang Huy; Ly, Thuc Hue; Vu, Quoc An; Yun, Minhee; Duan, Xiangfeng; Lee, Young Hee

2013-05-01

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10-13 A. The resulting devices exhibited an excellent on/off ratio of ~105, a high mobility of ~40 cm2 V-1 s-1 and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Modeling of phonon scattering in n-type nanowire transistors using one-shot analytic continuation technique

NASA Astrophysics Data System (ADS)

Bescond, Marc; Li, Changsheng; Mera, Hector; Cavassilas, Nicolas; Lannoo, Michel

2013-10-01

We present a one-shot current-conserving approach to model the influence of electron-phonon scattering in nano-transistors using the non-equilibrium Green's function formalism. The approach is based on the lowest order approximation (LOA) to the current and its simplest analytic continuation (LOA+AC). By means of a scaling argument, we show how both LOA and LOA+AC can be easily obtained from the first iteration of the usual self-consistent Born approximation (SCBA) algorithm. Both LOA and LOA+AC are then applied to model n-type silicon nanowire field-effect-transistors and are compared to SCBA current characteristics. In this system, the LOA fails to describe electron-phonon scattering, mainly because of the interactions with acoustic phonons at the band edges. In contrast, the LOA+AC still well approximates the SCBA current characteristics, thus demonstrating the power of analytic continuation techniques. The limits of validity of LOA+AC are also discussed, and more sophisticated and general analytic continuation techniques are suggested for more demanding cases.

Linear-log counting-rate meter uses transconductance characteristics of a silicon planar transistor

NASA Technical Reports Server (NTRS)

Eichholz, J. J.

1969-01-01

Counting rate meter compresses a wide range of data values, or decades of current. Silicon planar transistor, operating in the zero collector-base voltage mode, is used as a feedback element in an operational amplifier to obtain the log response.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

NASA Astrophysics Data System (ADS)

Gutiérrez-Heredia, G.; González, L. A.; Alshareef, H. N.; Gnade, B. E.; Quevedo-López, M.

2010-11-01

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 µA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 µA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented.

Current crowding mediated large contact noise in graphene field-effect transistors

PubMed Central

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-01-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene–metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V−1 s−1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal–channel interface, which could be generic to two-dimensional material-based electronic devices. PMID:27929087

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

PubMed

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Mobility overestimation due to gated contacts in organic field-effect transistors

PubMed Central

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Current crowding mediated large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-12-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene-metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V-1 s-1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal-channel interface, which could be generic to two-dimensional material-based electronic devices.

Vertical field-effect transistor based on wave-function extension

NASA Astrophysics Data System (ADS)

Sciambi, A.; Pelliccione, M.; Lilly, M. P.; Bank, S. R.; Gossard, A. C.; Pfeiffer, L. N.; West, K. W.; Goldhaber-Gordon, D.

2011-08-01

We demonstrate a mechanism for a dual layer, vertical field-effect transistor, in which nearly depleting one layer will extend its wave function to overlap the other layer and increase tunnel current. We characterize this effect in a specially designed GaAs/AlGaAs device, observing a tunnel current increase of two orders of magnitude at cryogenic temperatures, and we suggest extrapolations of the design to other material systems such as graphene.

Single shot spin readout using a cryogenic high-electron-mobility transistor amplifier at sub-Kelvin temperatures

NASA Astrophysics Data System (ADS)

Tracy, L. A.; Luhman, D. R.; Carr, S. M.; Bishop, N. C.; Ten Eyck, G. A.; Pluym, T.; Wendt, J. R.; Lilly, M. P.; Carroll, M. S.

2016-02-01

We use a cryogenic high-electron-mobility transistor circuit to amplify the current from a single electron transistor, allowing for demonstration of single shot readout of an electron spin on a single P donor in Si with 100 kHz bandwidth and a signal to noise ratio of ˜9. In order to reduce the impact of cable capacitance, the amplifier is located adjacent to the Si sample, at the mixing chamber stage of a dilution refrigerator. For a current gain of ˜ 2.7 × 10 3 , the power dissipation of the amplifier is 13 μW, the bandwidth is ˜ 1.3 MHz, and for frequencies above 300 kHz the current noise referred to input is ≤ 70 fA/ √{ Hz } . With this amplification scheme, we are able to observe coherent oscillations of a P donor electron spin in isotopically enriched 28Si with 96% visibility.

Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-11-01

Tunnel field-effect transistor (TFET) is very attractive in replacing a MOSFET, particularly for low-power nanoelectronic circuits. The U-shaped channel TFET (U-TFET) was proposed to improve the drain-source current with a reduced footprint. In this work, the impact of the source height (HS) on the characteristic of the U-shaped channel tunnel field-effect transistor (U-TFET) is investigated by using TCAD simulation. It is found that with a fixed gate height (HG) the drain-source current has a negative correlation with HS. This is because when the gate region is deeper than the source region, the electric field near the corner of the tunneling junction can be enhanced and the tunneling rate is increased. When HS becomes very thin, the drain-source current is limited by the source region volume. The U-TFET with an n+ pocket is also studied and the same trend is observed.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

High concentration effects of neutral-potential-well interface traps on recombination dc current-voltage lineshape in metal-oxide-silicon transistors

NASA Astrophysics Data System (ADS)

Chen, Zuhui; Jie, Bin B.; Sah, Chih-Tang

2008-11-01

Steady-state Shockley-Read-Hall kinetics is employed to explore the high concentration effect of neutral-potential-well interface traps on the electron-hole recombination direct-current current-voltage (R-DCIV) properties in metal-oxide-silicon field-effect transistors. Extensive calculations include device parameter variations in neutral-trapping-potential-well electron interface-trap density NET (charge states 0 and -1), dopant impurity concentration PIM, oxide thickness Xox, forward source/drain junction bias VPN, and transistor temperature T. It shows significant distortion of the R-DCIV lineshape by the high concentrations of the interface traps. The result suggests that the lineshape distortion observed in past experiments, previously attributed to spatial variation in surface impurity concentration and energy distribution of interface traps in the silicon energy gap, can also arise from interface-trap concentration along surface channel region.

Removing the current-limit of vertical organic field effect transistors

NASA Astrophysics Data System (ADS)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Ion bipolar junction transistors

PubMed Central

Tybrandt, Klas; Larsson, Karin C.; Richter-Dahlfors, Agneta; Berggren, Magnus

2010-01-01

Dynamic control of chemical microenvironments is essential for continued development in numerous fields of life sciences. Such control could be achieved with active chemical circuits for delivery of ions and biomolecules. As the basis for such circuitry, we report a solid-state ion bipolar junction transistor (IBJT) based on conducting polymers and thin films of anion- and cation-selective membranes. The IBJT is the ionic analogue to the conventional semiconductor BJT and is manufactured using standard microfabrication techniques. Transistor characteristics along with a model describing the principle of operation, in which an anionic base current amplifies a cationic collector current, are presented. By employing the IBJT as a bioelectronic circuit element for delivery of the neurotransmitter acetylcholine, its efficacy in modulating neuronal cell signaling is demonstrated. PMID:20479274

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.

PubMed

Wong, A K Y; Kong-Pang Pun; Yuan-Ting Zhang; Ka Nang Leung

2008-12-01

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

Kink effect in ultrathin FDSOI MOSFETs

NASA Astrophysics Data System (ADS)

Park, H. J.; Bawedin, M.; Choi, H. G.; Cristoloveanu, S.

2018-05-01

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. He is currently working toward the Ph.D. degree in FDSOI device characterization and simulation at a laboratory of IMEP-lahc, Université Grenoble Alpes, Minatec, Grenoble, France. His research interests include residual floating body effects, electrical characterization, and device simulation for ultra FDSOI MOSFETs.

Lateral carrier diffusion and current gain in terahertz InGaAs/InP double-heterojunction bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Han-Wei; Rode, Johann C.; Choudhary, Prateek

2014-01-21

The DC current gain in In{sub 0.53}Ga{sub 0.47}As/InP double-heterojunction bipolar transistors is computed based on a drift-diffusion model, and is compared with experimental data. Even in the absence of other scaling effects, lateral diffusion of electrons to the base Ohmic contacts causes a rapid reduction in DC current gain as the emitter junction width and emitter-base contact spacing are reduced. The simulation and experimental data are compared in order to examine the effect of carrier lateral diffusion on current gain. The impact on current gain due to device scaling and approaches to increase current gain are discussed.

Gallium Arsenide Pilot Line for High Performance Components

DTIC Science & Technology

1992-05-28

two transistors’ characteristics were a close enough match to use as pull -up, high resistance loads in the cell. FET Data Unfortunately, data obtained...length transistors in 4K SRAM II, we can predict the performance of the memory chip. Since there is essentially no active pull up capability in the c a...Second, the 2/2 Am DFET’s threshold and "ON" current could be adjusted. Or third, a different size DFET pull -up transistor could be used which more

Integration of Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors

DTIC Science & Technology

2017-02-10

AFRL-AFOSR-JP-TR-2017-0009 Integration of Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors Paul Dastoor UNIVERSITY OF...collection of information   if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ORGANIZATION . 1...Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors 5a.  CONTRACT NUMBER 5b.  GRANT NUMBER FA2386-15-1-4002 5c.  PROGRAM ELEMENT

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

PubMed

Goh, Youngin; Ahn, Jaehan; Lee, Jeong Rak; Park, Wan Woo; Ko Park, Sang-Hee; Jeon, Sanghun

2017-10-25

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

NASA Technical Reports Server (NTRS)

Mclyman, W. T. (Inventor)

1981-01-01

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

The role of optoelectronic feedback on Franz-Keldysh voltage modulation of transistor lasers

NASA Astrophysics Data System (ADS)

Chang, Chi-Hsiang; Chang, Shu-Wei; Wu, Chao-Hsin

2016-03-01

Possessing both the high-speed characteristics of heterojunction bipolar transistors (HBTs) and enhanced radiative recombination of quantum wells (QWs), the light-emitting transistor (LET) which operates in the regime of spontaneous emissions has achieved up to 4.3 GHz modulation bandwidth. A 40 Gbit/s transmission rate can be even achieved using transistor laser (TL). The transistor laser provides not only the current modulation but also direct voltage-controlled modulation scheme of optical signals via Franz-Keldysh (FK) photon-assisted tunneling effect. In this work, the effect of FK absorption on the voltage modulation of TLs is investigated. In order to analyze the dynamics and optical responses of voltage modulation in TLs, the conventional rate equations relevant to diode lasers (DLs) are first modified to include the FK effect intuitively. The theoretical results of direct-current (DC) and small-signal alternating-current (AC) characteristics of optical responses are both investigated. While the DC characteristics look physical, the intrinsic optical response of TLs under the FK voltage modulation shows an AC enhancement with a 20 dB peak, which however is not observed in experiment. A complete model composed of the intrinsic optical transfer function and an electrical transfer function fed back by optical responses is proposed to explain the behaviors of voltage modulation in TLs. The abnormal AC peak disappears through this optoelectronic feedback. With the electrical response along with FK-included photon-carrier rate equations taken into account, the complete voltage-controlled optical modulation response of TLs is demonstrated.

Heterostructured semiconductor single-walled carbon nanotube films for solution-processed high-performance field-effect transistors

NASA Astrophysics Data System (ADS)

Park, Noh-Hwal; Lee, Seung-Hoon; Jeong, Seung-Hyeon; Khim, Dongyoon; Kim, Yun Ho; Yoo, Sungmi; Noh, Yong-Young; Kim, Jang-Joo

2018-03-01

In this paper, we report a simple and effective method to simultaneously achieve a high charge-carrier mobility and low off current in conjugated polymer-wrapped semiconducting single-walled carbon nanotube (s-SWNT) transistors by applying a SWNT bilayer. To achieve the high mobility and low off current, highly purified and less purified s-SWNTs are successively coated to form the semiconducting layer consisting of poly (3-dodecylthiophene-2,5-diyl) (P3DDT)-wrapped high-pressure carbon mono oxide (HiPCO) SWNT (P3DDT-HiPCO) and poly (9, 9-di-n-dodecylfluorene) (PFDD)-wrapped plasma discharge (PD) SWNT (PFDD-PD). The SWNT transistors with bilayer SWNT networked film showed highly improved hole field-effect mobility (6.18 ± 0.85 cm2V-1s-1 average), on/off current ratio (107), and off current (˜1 pA). Thus, the combination of less purified PFDD-PD (98%-99%) charge-injection layer and highly purified s-P3DDT-HiPCO (>99%) charge-transport layer as the bi-layered semiconducting film achieved high mobility and low off current simultaneously.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Transistor biased amplifier minimizes diode discriminator threshold attenuation

NASA Technical Reports Server (NTRS)

Larsen, R. N.

1967-01-01

Transistor biased amplifier has a biased diode discriminator driven by a high impedance /several megohms/ current source, rather than a voltage source with several hundred ohms output impedance. This high impedance input arrangement makes the incremental impedance of the threshold diode negligible relative to the input impedance.

A pulse-burst laser system for a high-repetition-rate Thomson scattering diagnostic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Den Hartog, D. J.; Jiang, N.; Lempert, W. R.

2008-10-15

A ''pulse-burst'' laser system is being constructed for addition to the Thomson scattering diagnostic on the Madison Symmetric Torus (MST) reversed-field pinch. This laser is designed to produce a burst of up to 200 approximately 1 J Q-switched pulses at repetition frequencies 5-250 kHz. This laser system will operate at 1064 nm and is a master oscillator, power amplifier. The master oscillator is a compact diode-pumped Nd:YVO{sub 4} laser, intermediate amplifier stages are flashlamp-pumped Nd:YAG, and final stages will be flashlamp-pumped Nd:glass (silicate). Variable pulse width drive (0.3-20 ms) of the flashlamps is accomplished by insulated-gate bipolar transistor switching ofmore » large electrolytic capacitor banks. The burst train of laser pulses will enable the study of electron temperature (T{sub e}) and electron density (n{sub e}) dynamics in a single MST shot, and with ensembling, will enable correlation of T{sub e} and n{sub e} fluctuations with other fluctuating quantities.« less

Development of a 33 kV, 20 A long pulse converter modulator for high average power klystron

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reghu, T.; Mandloi, V.; Shrivastava, Purushottam

Research, design, and development of high average power, long pulse modulators for the proposed Indian Spallation Neutron Source are underway at Raja Ramanna Centre for Advanced Technology. With this objective, a prototype of long pulse modulator capable of delivering 33 kV, 20 A at 5 Hz repetition rate has been designed and developed. Three Insulated Gate Bipolar Transistors (IGBT) based switching modules driving high frequency, high voltage transformers have been used to generate high voltage output. The IGBT based switching modules are shifted in phase by 120° with respect to each other. The switching frequency is 25 kHz. Pulses ofmore » 1.6 ms pulse width, 80 μs rise time, and 70 μs fall time have been achieved at the modulator output. A droop of ±0.6% is achieved using a simple segmented digital droop correction technique. The total fault energy transferred to the load during fault has been measured by conducting wire burn tests and is found to be within 3.5 J.« less

Development of a 33 kV, 20 A long pulse converter modulator for high average power klystron

NASA Astrophysics Data System (ADS)

Reghu, T.; Mandloi, V.; Shrivastava, Purushottam

2014-05-01

Research, design, and development of high average power, long pulse modulators for the proposed Indian Spallation Neutron Source are underway at Raja Ramanna Centre for Advanced Technology. With this objective, a prototype of long pulse modulator capable of delivering 33 kV, 20 A at 5 Hz repetition rate has been designed and developed. Three Insulated Gate Bipolar Transistors (IGBT) based switching modules driving high frequency, high voltage transformers have been used to generate high voltage output. The IGBT based switching modules are shifted in phase by 120° with respect to each other. The switching frequency is 25 kHz. Pulses of 1.6 ms pulse width, 80 μs rise time, and 70 μs fall time have been achieved at the modulator output. A droop of ±0.6% is achieved using a simple segmented digital droop correction technique. The total fault energy transferred to the load during fault has been measured by conducting wire burn tests and is found to be within 3.5 J.

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

A Q-band low noise GaAs pHEMT MMIC power amplifier for pulse electron spin resonance spectrometer

NASA Astrophysics Data System (ADS)

Sitnikov, A.; Kalabukhova, E.; Oliynyk, V.; Kolisnichenko, M.

2017-05-01

We present the design and development of a single stage pulse power amplifier working in the frequency range 32-38 GHz based on a monolithic microwave integrated circuit (MMIC). We have designed the MMIC power amplifier by using the commercially available packaged GaAs pseudomorphic high electron mobility transistor. The circuit fabrication and assembly process includes the elaboration of the matching networks for the MMIC power amplifier and their assembling as well as the topology outline and fabrication of the printed circuit board of the waveguide-microstrip line transitions. At room ambient temperature, the measured peak output power from the prototype amplifier is 35.5 dBm for 16.6 dBm input driving power, corresponding to 19 dB gain. The measured rise/fall time of the output microwave signal modulated by a high-speed PIN diode was obtained as 5-6 ns at 20-250 ns pulse width with 100 kHz pulse repetition rate frequency.

A Q-band low noise GaAs pHEMT MMIC power amplifier for pulse electron spin resonance spectrometer.

PubMed

Sitnikov, A; Kalabukhova, E; Oliynyk, V; Kolisnichenko, M

2017-05-01

We present the design and development of a single stage pulse power amplifier working in the frequency range 32-38 GHz based on a monolithic microwave integrated circuit (MMIC). We have designed the MMIC power amplifier by using the commercially available packaged GaAs pseudomorphic high electron mobility transistor. The circuit fabrication and assembly process includes the elaboration of the matching networks for the MMIC power amplifier and their assembling as well as the topology outline and fabrication of the printed circuit board of the waveguide-microstrip line transitions. At room ambient temperature, the measured peak output power from the prototype amplifier is 35.5 dBm for 16.6 dBm input driving power, corresponding to 19 dB gain. The measured rise/fall time of the output microwave signal modulated by a high-speed PIN diode was obtained as 5-6 ns at 20-250 ns pulse width with 100 kHz pulse repetition rate frequency.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Comparative Study of Fault Diagnostic Methods in Voltage Source Inverter Fed Three Phase Induction Motor Drive

NASA Astrophysics Data System (ADS)

Dhumale, R. B.; Lokhande, S. D.

2017-05-01

Three phase Pulse Width Modulation inverter plays vital role in industrial applications. The performance of inverter demeans as several types of faults take place in it. The widely used switching devices in power electronics are Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Field Effect Transistors (MOSFET). The IGBTs faults are broadly classified as base or collector open circuit fault, misfiring fault and short circuit fault. To develop consistency and performance of inverter, knowledge of fault mode is extremely important. This paper presents the comparative study of IGBTs fault diagnosis. Experimental set up is implemented for data acquisition under various faulty and healthy conditions. Recent methods are executed using MATLAB-Simulink and compared using key parameters like average accuracy, fault detection time, implementation efforts, threshold dependency, and detection parameter, resistivity against noise and load dependency.

Inverter for interfacing advanced energy sources to a utility grid

DOEpatents

Steigerwald, Robert L.

1984-01-01

A transistor is operated in the PWM mode such that a hlaf sine wave of current is delivered first to one-half of a distribution transformer and then the other as determined by steering thyristors operated at the fundamental sinusoidal frequency. Power to the transistor is supplied by a dc source such as a solar array and the power is converted such that a sinusoidal current is injected into a utility at near unity power factor.

Construction and evaluation of photovoltaic power generation and power storage system using SiC field-effect transistor inverter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oku, Takeo, E-mail: oku@mat.usp.ac.jp; Matsumoto, Taisuke; Ohishi, Yuya

A power storage system using spherical silicon (Si) solar cells, maximum power point tracking charge controller, lithium-ion battery and a direct current-alternating current (DC-AC) inverter was constructed. Performance evaluation of the DC-AC inverter was carried out, and the DC-AC conversion efficiencies of the SiC field-effect transistor (FET) inverter was improved compared with those of the ordinary Si-FET based inverter.

Mobility enhancement in graphene transistors on low temperature pulsed laser deposited boron nitride

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uddin, Md Ahsan, E-mail: uddin2@email.sc.edu, E-mail: gkoley@clemson.edu; Koley, Goutam, E-mail: uddin2@email.sc.edu, E-mail: gkoley@clemson.edu; Department of Electrical Engineering, University of South Carolina, Columbia, South Carolina 29208

2015-11-16

Low temperature pulsed laser deposited (PLD) ultrathin boron nitride (BN) on SiO{sub 2} was investigated as a dielectric for graphene electronics, and a significant enhancement in electrical transport properties of graphene/PLD BN compared to graphene/SiO{sub 2} has been observed. Graphene synthesized by chemical vapor deposition and transferred on PLD deposited and annealed BN exhibited up to three times higher field effect mobility compared to graphene on the SiO{sub 2} substrate. Graphene field effect transistor devices fabricated on 5 nm BN/SiO{sub 2} (300 nm) yielded maximum hole and electron mobility of 4980 and 4200 cm{sup 2}/V s, respectively. In addition, significant improvement in carriermore » homogeneity and reduction in extrinsic doping in graphene on BN has been observed. An average Dirac point of 3.5 V and residual carrier concentration of 7.65 × 10{sup 11 }cm{sup −2} was observed for graphene transferred on 5 nm BN at ambient condition. The overall performance improvement on PLD BN can be attributed to dielectric screening of charged impurities, similar crystal structure and phonon modes, and reduced substrate induced doping.« less

Optimization of pulsed laser deposited ZnO thin-film growth parameters for thin-film transistors (TFT) application

NASA Astrophysics Data System (ADS)

Gupta, Manisha; Chowdhury, Fatema Rezwana; Barlage, Douglas; Tsui, Ying Yin

2013-03-01

In this work we present the optimization of zinc oxide (ZnO) film properties for a thin-film transistor (TFT) application. Thin films, 50±10 nm, of ZnO were deposited by Pulsed Laser Deposition (PLD) under a variety of growth conditions. The oxygen pressure, laser fluence, substrate temperature and annealing conditions were varied as a part of this study. Mobility and carrier concentration were the focus of the optimization. While room-temperature ZnO growths followed by air and oxygen annealing showed improvement in the (002) phase formation with a carrier concentration in the order of 1017-1018/cm3 with low mobility in the range of 0.01-0.1 cm2/V s, a Hall mobility of 8 cm2/V s and a carrier concentration of 5×1014/cm3 have been achieved on a relatively low temperature growth (250 °C) of ZnO. The low carrier concentration indicates that the number of defects have been reduced by a magnitude of nearly a 1000 as compared to the room-temperature annealed growths. Also, it was very clearly seen that for the (002) oriented films of ZnO a high mobility film is achieved.

Study of the effects of GaN buffer layer quality on the dc characteristics of AlGaN/GaN high electron mobility transistors

DOE PAGES

Ahn, Shihyun; Zhu, Weidi; Dong, Chen; ...

2015-04-21

Here we studied the effect of buffer layer quality on dc characteristics of AlGaN/GaN high electron mobility (HEMTs). AlGaN/GaN HEMT structures with 2 and 5 μm GaN buffer layers on sapphire substrates from two different vendors with the same Al concentration of AlGaN were used. The defect densities of HEMT structures with 2 and 5 μm GaN buffer layer were 7 × 10 9 and 5 × 10 8 cm ₋2, respectively, as measured by transmission electron microscopy. There was little difference in drain saturation current or in transfer characteristics in HEMTs on these two types of buffer. However, theremore » was no dispersion observed on the nonpassivated HEMTs with 5 μm GaN buffer layer for gate-lag pulsed measurement at 100 kHz, which was in sharp contrast to the 71% drain current reduction for the HEMT with 2 μm GaN buffer layer.« less

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Series transistors isolate amplifier from flyback voltage

NASA Technical Reports Server (NTRS)

Banks, W.

1967-01-01

Circuit enables high sawtooth currents to be passed through a deflection coil and isolate the coil driving amplifier from the flyback voltage. It incorporates a switch consisting of transistors in series with the driving amplifier and deflection coil. The switch disconnects the deflection coil from the amplifier during the retrace time.

Conceptual techniques for reducing parasitic current gain of lateral pnp transistors

NASA Technical Reports Server (NTRS)

Gallagher, R. C.; Scott, J. M.

1969-01-01

Two techniques have been conceptually proposed as possible means of reducing parasitic beta in lateral p-n-p transistors. One method uses a degenerate substrate and high concentration P /plus/ guard-ring diffusion, another places the base contact at the center of an annular ring structure.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Polymer space-charge-limited transistor as a solid-state vacuum tube triode

NASA Astrophysics Data System (ADS)

Chao, Yu-Chiang; Ku, Ming-Che; Tsai, Wu-Wei; Zan, Hsiao-Wen; Meng, Hsin-Fei; Tsai, Hung-Kuo; Horng, Sheng-Fu

2010-11-01

We report the construction of a polymer space-charge-limited transistor (SCLT), a solid-state version of vacuum tube triode. The SCLT achieves a high on/off ratio of 3×105 at a low operation voltage of 1.5 V by using high quality insulators both above and below the grid base electrode. Applying a greater bias to the base increases the barrier potential, and turns off the channel current, without introducing a large parasitic leakage current. Simulation result verifies the influence of base bias on channel potential distribution. The output current density is 1.7 mA/cm2 with current gain greater than 1000.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Multi-turn transmit coil to increase b1 efficiency in current source amplification.

PubMed

Gudino, N; Griswold, M A

2013-04-01

A multi-turn transmit surface coil design was presented to improve B1 efficiency when used with current source amplification. Three different coil designs driven by an on-coil current-mode class-D amplifier with current envelope feedback were tested on the benchtop and through imaging in a 1.5 T scanner. Case temperature of the power field-effect transistor at the amplifier output stage was measured to evaluate heat dissipation for the different current levels and coil configurations. In addition, a lower power rated device was tested to exploit the potential gain in B1 obtained with the multi-turn coil. As shown both on the benchtop and in a 1.5 T scanner, B1 was increased by almost 3-fold without increasing heat dissipation on the power device at the amplifier's output using a multi-turn surface coil. Similar gain was obtained when connecting a lower power rated field-effect transistor to the multi-turn coil. In addition to reduce heat dissipation per B1 in the device, higher B1 per current efficiency allows the use of field-effect transistors with lower current ratings and lower port capacitances, which could improve the overall performance of the on-coil current source transmit system. Copyright © 2013 Wiley Periodicals, Inc.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Hu, Zhaoying; Tulevski, George S.; Hannon, James B.; Afzali, Ali; Liehr, Michael; Park, Hongsik

2015-06-01

Carbon nanotubes (CNTs) have been widely studied as a channel material of scaled transistors for high-speed and low-power logic applications. In order to have sufficient drive current, it is widely assumed that CNT-based logic devices will have multiple CNTs in each channel. Understanding the effects of the number of CNTs on device performance can aid in the design of CNT field-effect transistors (CNTFETs). We have fabricated multi-CNT-channel CNTFETs with an 80-nm channel length using precise self-assembly methods. We describe compact statistical models and Monte Carlo simulations to analyze failure probability and the variability of the on-state current and threshold voltage. The results show that multichannel CNTFETs are more resilient to process variation and random environmental fluctuations than single-CNT devices.

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer

PubMed Central

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-01-01

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm2/Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 105. Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles. PMID:27876893

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer.

PubMed

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; Kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-11-23

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O 2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm 2 /Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 10 5 . Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Large scale electromechanical transistor with application in mass sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to bemore » used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.« less

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Forback DC-to-DC converter

NASA Technical Reports Server (NTRS)

Lukemire, Alan T. (Inventor)

1995-01-01

A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

Developing a pulse trigger generator for a three-electrode spark-gap switch in a transversely excited atmospheric CO2 laser.

PubMed

Wang, Jingyuan; Guo, Lihong; Zhang, Xingliang

2016-04-01

To improve the probability and stability of breakdown discharge in a three-electrode spark-gap switch for a high-power transversely excited atmospheric CO2 laser and to improve the efficiency of its trigger system, we developed a high-voltage pulse trigger generator based on a two-transistor forward converter topology and a multiple-narrow-pulse trigger method. Our design uses a narrow high-voltage pulse (10 μs) to break down the hyperbaric gas between electrodes of the spark-gap switch; a dry high-voltage transformer is used as a booster; and a sampling and feedback control circuit (mainly consisting of a SG3525 and a CD4098) is designed to monitor the spark-gap switch and control the frequency and the number of output pulses. Our experimental results show that this pulse trigger generator could output high-voltage pulses (number is adjusted) with an amplitude of >38 kV and a width of 10 μs. Compared to a conventional trigger system, our design had a breakdown probability increased by 2.7%, an input power reduced by 1.5 kW, an efficiency increased by 0.12, and a loss reduced by 1.512 kW.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

PubMed

Yan Lu; Wing-Hung Ki

2014-06-01

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

Comparison between the effects of positive noncatastrophic HMB ESD stress in n-channel and p-channel power MOSFET's

NASA Astrophysics Data System (ADS)

Zupac, Dragan; Kosier, Steven L.; Schrimpf, Ronald D.; Galloway, Kenneth F.; Baum, Keith W.

1991-10-01

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain.

Review of a solution-processed vertical organic transistor as a solid-state vacuum tube

NASA Astrophysics Data System (ADS)

Lin, Hung-Cheng; Zan, Hsiao-Wen; Chao, Yu-Chiang; Chang, Ming-Yu; Meng, Hsin-Fei

2015-05-01

In this paper, we investigate the key issues in raising the on/off current ratio and increasing the output current. A 1 V operated inverter composed of an enhancement-mode space-charge-limited transistor (SCLT) and a depletion-mode SCLT is demonstrated using the self-assembled monolayer modulation process. With a bulk-conduction mechanism, good bias-stress reliability, and good bending durability are obtained. Finally, key scaling-up processes, including nanoimprinting and blade-coated nanospheres, are demonstrated.

Conjugated polymers and their use in optoelectronic devices

DOEpatents

Marks, Tobin J.; Guo, Xugang; Zhou, Nanjia; Chang, Robert P. H.; Drees, Martin; Facchetti, Antonio

2016-10-18

The present invention relates to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The present compounds can have good solubility in common solvents enabling device fabrication via solution processes.

Fully transparent thin film transistors based on zinc oxide channel layer and molybdenum doped indium oxide electrodes

NASA Astrophysics Data System (ADS)

MÄ dzik, Mateusz; Elamurugu, Elangovan; Viegas, Jaime

2016-03-01

In this work we report the fabrication of thin film transistors (TFT) with zinc oxide channel and molybdenum doped indium oxide (IMO) electrodes, achieved by room temperature sputtering. A set of devices was fabricated, with varying channel width and length from 5μm to 300μm. Output and transfer characteristics were then extracted to study the performance of thin film transistors, namely threshold voltage and saturation current, enabling to determine optimal fabrication process parameters. Optical transmission in the UV-VIS-IR are also reported.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Overload protection circuit for output driver

DOEpatents

Stewart, Roger G.

1982-05-11

A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-Based Current Amplifier.

PubMed

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2016-06-01

To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. The resonant detection coil is connected in parallel with the gate of a high electron mobility transistor (HEMT) transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor's source to a negative resistance on its gate. High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 μW, 14 dB gain was obtained with excellent noise performance. An integrated current amplifier based on a HEMT can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. Magn Reson Med 75:2573-2578, 2016. Published 2015. This article is a U.S. Government work and is in the public domain in the USA. Published 2015 This article is a U.S. Government work and is in the public domain in the USA.

Copper atomic-scale transistors

PubMed Central

Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors. PMID:28382242

Low-intensity calibration source for optical imaging systems

NASA Astrophysics Data System (ADS)

Holdsworth, David W.

2017-03-01

Laboratory optical imaging systems for fluorescence and bioluminescence imaging have become widely available for research applications. These systems use an ultra-sensitive CCD camera to produce quantitative measurements of very low light intensity, detecting signals from small-animal models labeled with optical fluorophores or luminescent emitters. Commercially available systems typically provide quantitative measurements of light output, in units of radiance (photons s-1 cm-2 SR-1) or intensity (photons s-1 cm-2). One limitation to current systems is that there is often no provision for routine quality assurance and performance evaluation. We describe such a quality assurance system, based on an LED-illuminated thin-film transistor (TFT) liquid-crystal display module. The light intensity is controlled by pulse-width modulation of the backlight, producing radiance values ranging from 1.8 x 106 photons s-1 cm-2 SR-1 to 4.2 x 1013 photons s-1 cm-2 SR-1. The lowest light intensity values are produced by very short backlight pulses (i.e. approximately 10 μs), repeated every 300 s. This very low duty cycle is appropriate for laboratory optical imaging systems, which typically operate with long-duration exposures (up to 5 minutes). The low-intensity light source provides a stable, traceable radiance standard that can be used for routine quality assurance of laboratory optical imaging systems.

A Klein-tunneling transistor with ballistic graphene

NASA Astrophysics Data System (ADS)

Wilmart, Quentin; Berrada, Salim; Torrin, David; Nguyen, V. Hung; Fève, Gwendal; Berroir, Jean-Marc; Dollfus, Philippe; Plaçais, Bernard

2014-06-01

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry-Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation.

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

PubMed

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

PubMed

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Polymer-based doping control for performance enhancement of wet-processed short-channel CNTFETs

NASA Astrophysics Data System (ADS)

Hartmann, Martin; Schubel, René; Claus, Martin; Jordan, Rainer; Schulz, Stefan E.; Hermann, Sascha

2018-01-01

The electrical transport properties of short-channel transistors based on single-walled carbon nanotubes (CNT) are significantly affected by bundling along with solution processing. We report that especially high off currents of CNT transistors are not only related to the incorporation of metallic CNTs but also to the incorporation of CNT bundles. By applying device passivation with poly(4-vinylpyridine), the impact of CNT bundling on the device performance can be strongly reduced due to increased gate efficiency as well as reduced oxygen and water-induced p-type doping, boosting essential field-effect transistor performance parameters by several orders of magnitude. Moreover, this passivation approach allows the hysteresis and threshold voltage of CNT transistors to be tuned.

Bipolar Transistors Can Detect Charge in Electrostatic Experiments

ERIC Educational Resources Information Center

Dvorak, L.

2012-01-01

A simple charge indicator with bipolar transistors is described that can be used in various electrostatic experiments. Its behaviour enables us to elucidate links between 'static electricity' and electric currents. In addition it allows us to relate the sign of static charges to the sign of the terminals of an ordinary battery. (Contains 7 figures…

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Carbon nanotube transistors scaled to a 40-nanometer footprint.

PubMed

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Hysteresis free negative total gate capacitance in junctionless transistors

NASA Astrophysics Data System (ADS)

Gupta, Manish; Kranti, Abhinav

2017-09-01

In this work, we report on the hysteresis free impact ionization induced off-to-on transition while preserving sub-60 mV/decade Subthreshold swing (S-swing) using asymmetric mode operation in double gate silicon (Si) and germanium (Ge) junctionless (JL) transistor. It is shown that sub-60 mV/decade steep switching due to impact ionization implies a negative value of the total gate capacitance. The performance of asymmetric gate JL transistor is compared with symmetric gate operation of JL device, and the condition for hysteresis free current transition with a sub-60 mV/decade switching is analyzed through the product of current density (J) and electric field (E). It is shown that asymmetric gate operation limits the degree of impact ionization inherent in the semiconductor film to levels sufficient for negative total gate capacitance but lower than that required for the occurrence of hysteresis. The work highlights new viewpoints related to the suppression of hysteresis associated with steep switching JL transistors while maintaining S-swing within the range 6-15 mV/decade leading to the negative value of total gate capacitance.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

High-Voltage Power Supply With Fast Rise and Fall Times

NASA Technical Reports Server (NTRS)

Bearden, Douglas B.; Acker, Richard M.; Kapuslka, Robert E.

2007-01-01

A special-purpose high-voltage power supply can be electronically switched on and off with fast rise and fall times, respectively. The output potential is programmable from 20 to 1,250 V. An output current of 50 A can be sustained at 1,250 V. The power supply was designed specifically for electronically shuttering a microchannel plate in an x-ray detector that must operate with exposure times as short as 1 ms. The basic design of the power supply is also adaptable to other applications in which there are requirements for rapid slewing of high voltages. The power-supply circuitry (see figure) includes a preregulator, which is used to program the output at 1/30 of the desired output potential. After the desired voltage has been set, the outputs of a pulse width modulator (PWM) are enabled and used to amplify the preregulator output potential by 30. The amplification is achieved by use of two voltage doublers with a transformer that has two primary and two secondary windings. A resistor is used to limit the current by controlling the drive voltage of two field-effect transistors (FETs) during turn-on of the PWM. A pulse transformer is used to turn on four FETs to short-circuit four output capacitors when the outputs of the PWM have been disabled. The most notable aspects of the performance of the power supply are a rise time of only 80 s and a fall time of only 60 s at a load current of 50 A or less. Another notable aspect is that the application of a 0-to-5-V square wave to a shutdown pin of the PWM causes the production of a 0-to-1,250-V square wave at the output terminals.

Epitaxial Gd2O3 on GaN and AlGaN: a potential candidate for metal oxide semiconductor based transistors on Si for high power application

NASA Astrophysics Data System (ADS)

Ghosh, Kankat; Das, S.; Khiangte, K. R.; Choudhury, N.; Laha, Apurba

2017-11-01

We report structural and electrical properties of hexagonal Gd2O3 grown epitaxially on GaN/Si (1 1 1) and AlGaN/GaN/Si(1 1 1) virtual substrates. GaN and AlGaN/GaN heterostructures were grown on Si(1 1 1) substrates by plasma assisted molecular beam epitaxy (PA-MBE), whereas the Gd2O3 layer was grown by the pulsed laser ablation (PLA) technique. Initial structural characterizations show that Gd2O3 grown on III-nitride layers by PLA, exhibit a hexagonal structure with an epitaxial relationship as {{≤ft[ 0 0 0 1 \\right]}G{{d2}{{O}3}}}||{{≤ft[ 0 0 0 1 \\right]}GaN} and {{≤ft[ 1 \\bar{1} 0 0 \\right]}G{{d2}{{O}3}}}||{{≤ft[ 1 \\bar{1} 0 0 \\right]}GaN} . X-ray photoelectron measurements of the valence bands revealed that Gd2O3 exhibits band offsets of 0.97 eV and 0.4 eV, for GaN and Al0.3Ga0.7N, respectively. Electrical measurements such as capacitance-voltage and leakage current characteristics further confirm that epi-Gd2O3 on III-nitrides could be a potential candidate for future metal-oxide-semiconductor (MOS)-based transistors also for high power applications in radio frequency range.

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

An oscilloscope spot intensifier, to improve photographic recordings of action potentials.

PubMed

Evans, M H

1985-06-01

A circuit diagram is shown for a semiconductor device to intensify the brightness of an oscilloscope during the rapidly rising and falling phases of signals such as action potentials. Brightening pulses proportional in amplitude to the rate of change in the Y-axis are available for connection to an oscilloscope with an external intensity ('Z') modulation input. The circuit requires one transistor, one dual operational amplifier and two single fast operational amplifiers.

Voltage-Boosting Driver For Switching Regulator

NASA Technical Reports Server (NTRS)

Trump, Ronald C.

1990-01-01

Driver circuit assures availability of 10- to 15-V gate-to-source voltage needed to turn on n-channel metal oxide/semiconductor field-effect transistor (MOSFET) acting as switch in switching voltage regulator. Includes voltage-boosting circuit efficiently providing gate voltage 10 to 15 V above supply voltage. Contains no exotic parts and does not require additional power supply. Consists of NAND gate and dual voltage booster operating in conjunction with pulse-width modulator part of regulator.

Highly flexible electronics from scalable vertical thin film transistors.

PubMed

Liu, Yuan; Zhou, Hailong; Cheng, Rui; Yu, Woojong; Huang, Yu; Duan, Xiangfeng

2014-03-12

Flexible thin-film transistors (TFTs) are of central importance for diverse electronic and particularly macroelectronic applications. The current TFTs using organic or inorganic thin film semiconductors are usually limited by either poor electrical performance or insufficient mechanical flexibility. Here, we report a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 10(5). The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. With large area graphene and IGZO thin film available, our strategy is intrinsically scalable for large scale integration of VTFT arrays and logic circuits, opening up a new pathway to highly flexible macroelectronics.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Single shot spin readout with a cryogenic high-electron-mobility transistor amplifier at sub-Kelvin temperatures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tracy, Lisa A.; Luhman, Dwight R.; Carr, Stephen M.

We use a cryogenic high-electron-mobility transistor circuit to amplify the current from a single electron transistor, allowing for demonstration of single shot readout of an electron spin on a single P donor in Si with 100 kHz bandwidth and a signal to noise ratio of ~9. In order to reduce the impact of cable capacitance, the amplifier is located adjacent to the Si sample, at the mixing chamber stage of a dilution refrigerator. For a current gain of ~2.7 x 10 3 the power dissipation of the amplifier is 13 μW, the bandwidth is ~1.3 MHz, and for frequencies abovemore » 300 kHz the current noise referred to input is ≤ 70 fA/√Hz. Furthermore, with this amplification scheme, we are able to observe coherent oscillations of a P donor electron spin in isotopically enriched 28Si with 96% visibility.« less

Single shot spin readout with a cryogenic high-electron-mobility transistor amplifier at sub-Kelvin temperatures

DOE PAGES

Tracy, Lisa A.; Luhman, Dwight R.; Carr, Stephen M.; ...

2016-02-08

We use a cryogenic high-electron-mobility transistor circuit to amplify the current from a single electron transistor, allowing for demonstration of single shot readout of an electron spin on a single P donor in Si with 100 kHz bandwidth and a signal to noise ratio of ~9. In order to reduce the impact of cable capacitance, the amplifier is located adjacent to the Si sample, at the mixing chamber stage of a dilution refrigerator. For a current gain of ~2.7 x 10 3 the power dissipation of the amplifier is 13 μW, the bandwidth is ~1.3 MHz, and for frequencies abovemore » 300 kHz the current noise referred to input is ≤ 70 fA/√Hz. Furthermore, with this amplification scheme, we are able to observe coherent oscillations of a P donor electron spin in isotopically enriched 28Si with 96% visibility.« less

Improved performance of graphene transistors by strain engineering.

PubMed

Nguyen, V Hung; Nguyen, Huy-Viet; Dollfus, P

2014-04-25

By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Hydrogen-induced reversible changes in drain current in Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2004-06-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage) are approximately an order of magnitude larger than for Pt/GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide-semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10% H2/90% N2 ambients relative to pure N2 and is due to catalytic dissociation of the H2 on the Pt contact, followed by diffusion to the Sc2O3/AlGaN interface.

Emitter utilization in heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Quach, T.; Jenkins, T.; Barrette, J.; Bozada, C.; Cerny, C.; Desalvo, G.; Dettmer, R.; Ebel, J.; Gillespie, J.; Havasy, C.; Ito, C.; Nakano, K.; Pettiford, C.; Sewell, J.; Via, D.; Anholt, R.

1997-09-01

We compare measured collector current densities, cutoff frequencies ( ft), and transducer gains for thermally shunted heterojunction bipolar transistors with 2-16 μm emitter dot diameters or 2-8 μm emitter bar widths with models of the emitter utilization factors. Models that do not take emitter resistance into account predict that the d.c. utilization factors are below 0.7 for collector current densities greater than 6 × 10 4 A cm -2 and emitter diameters or widths greater than 8 μm. However, because the current gains are compressed by the emitter resistances at those current densities, the measured utilization factors are close to 1, which agrees with models that include emitter resistance. A.c. utilization factors are evident in the transistor Y parameters. For example, Re|Y 21z.sfnc drops off at high frequencies more steeply in HBTs with large emitter diameters or widths than in small ones. However, measured data shows that the HBT a.c. current gains h21 or ft values are not influenced by the a.c. utilization factor. A.c. utilization effects on HBT performance parameters such as small signal and power gains, output power, and power added efficiency are also examined.

A comparative study on electrical characteristics of 1-kV pnp and npn SiC bipolar junction transistors

NASA Astrophysics Data System (ADS)

Okuda, Takafumi; Kimoto, Tsunenobu; Suda, Jun

2018-04-01

We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

All-printed thin-film transistors from networks of liquid-exfoliated nanosheets

NASA Astrophysics Data System (ADS)

Kelly, Adam G.; Hallam, Toby; Backes, Claudia; Harvey, Andrew; Esmaeily, Amir Sajad; Godwin, Ian; Coelho, João; Nicolosi, Valeria; Lauth, Jannika; Kulkarni, Aditya; Kinge, Sachin; Siebbeles, Laurens D. A.; Duesberg, Georg S.; Coleman, Jonathan N.

2017-04-01

All-printed transistors consisting of interconnected networks of various types of two-dimensional nanosheets are an important goal in nanoscience. Using electrolytic gating, we demonstrate all-printed, vertically stacked transistors with graphene source, drain, and gate electrodes, a transition metal dichalcogenide channel, and a boron nitride (BN) separator, all formed from nanosheet networks. The BN network contains an ionic liquid within its porous interior that allows electrolytic gating in a solid-like structure. Nanosheet network channels display on:off ratios of up to 600, transconductances exceeding 5 millisiemens, and mobilities of >0.1 square centimeters per volt per second. Unusually, the on-currents scaled with network thickness and volumetric capacitance. In contrast to other devices with comparable mobility, large capacitances, while hindering switching speeds, allow these devices to carry higher currents at relatively low drive voltages.

Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

PubMed

Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

2014-02-25

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.