An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

NASA Astrophysics Data System (ADS)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Custom chipset and compact module design for a 75-110 GHz laboratory signal source

NASA Astrophysics Data System (ADS)

Morgan, Matthew A.; Boyd, Tod A.; Castro, Jason J.

2016-12-01

We report on the development and characterization of a compact, full-waveguide bandwidth (WR-10) signal source for general-purpose testing of mm-wave components. The monolithic microwave integrated circuit (MMIC) based multichip module is designed for compactness and ease-of-use, especially in size-constrained test sets such as a wafer probe station. It takes as input a cm-wave continuous-wave (CW) reference and provides a factor of three frequency multiplication as well as amplification, output power adjustment, and in situ output power monitoring. It utilizes a number of custom MMIC chips such as a Schottky-diode limiter and a broadband mm-wave detector, both designed explicitly for this module, as well as custom millimeter-wave multipliers and amplifiers reported in previous papers.

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Optimization of multiplexed PCR on an integrated microfluidic forensic platform for rapid DNA analysis.

PubMed

Estes, Matthew D; Yang, Jianing; Duane, Brett; Smith, Stan; Brooks, Carla; Nordquist, Alan; Zenhausern, Frederic

2012-12-07

This study reports the design, prototyping, and assay development of multiplexed polymerase chain reaction (PCR) on a plastic microfluidic device. Amplification of 17 DNA loci is carried out directly on-chip as part of a system for continuous workflow processing from sample preparation (SP) to capillary electrophoresis (CE). For enhanced performance of on-chip PCR amplification, improved control systems have been developed making use of customized Peltier assemblies, valve actuators, software, and amplification chemistry protocols. Multiple enhancements to the microfluidic chip design have been enacted to improve the reliability of sample delivery through the various on-chip modules. This work has been enabled by the encapsulation of PCR reagents into a solid phase material through an optimized Solid Phase Encapsulating Assay Mix (SPEAM) bead-based hydrogel fabrication process. SPEAM bead technology is reliably coupled with precise microfluidic metering and dispensing for efficient amplification and subsequent DNA short tandem repeat (STR) fragment analysis. This provides a means of on-chip reagent storage suitable for microfluidic automation, with the long shelf-life necessary for point-of-care (POC) or field deployable applications. This paper reports the first high quality 17-plex forensic STR amplification from a reference sample in a microfluidic chip with preloaded solid phase reagents, that is designed for integration with up and downstream processing.

Solid State Audio/Speech Processor Analysis.

DTIC Science & Technology

1980-03-01

techniques. The techniques were demonstrated to be worthwhile in an efficient realtime AWR system. Finally, microprocessor architectures were designed to...do not include custom chip development, detailed hardware design , construction or testing. ITTDCD is very encouraged by the results obtained in this...California, Berkley, was responsible for furnishing the simulation data of OD speech analysis techniques and for the design and development of the hardware OD

Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

NASA Technical Reports Server (NTRS)

Monaco, Lisa

2003-01-01

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Genotype imputation efficiency in Nelore Cattle

USDA-ARS?s Scientific Manuscript database

Genotype imputation efficiency in Nelore cattle was evaluated in different scenarios of lower density (LD) chips, imputation methods and sets of animals to have their genotypes imputed. Twelve commercial and virtual custom LD chips with densities varying from 7K to 75K SNPs were tested. Customized L...

An externally head-mounted wireless neural recording device for laboratory animal research and possible human clinical use.

PubMed

Yin, Ming; Li, Hao; Bull, Christopher; Borton, David A; Aceros, Juan; Larson, Lawrence; Nurmikko, Arto V

2013-01-01

In this paper we present a new type of head-mounted wireless neural recording device in a highly compact package, dedicated for untethered laboratory animal research and designed for future mobile human clinical use. The device, which takes its input from an array of intracortical microelectrode arrays (MEA) has ninety-seven broadband parallel neural recording channels and was integrated on to two custom designed printed circuit boards. These house several low power, custom integrated circuits, including a preamplifier ASIC, a controller ASIC, plus two SAR ADCs, a 3-axis accelerometer, a 48MHz clock source, and a Manchester encoder. Another ultralow power RF chip supports an OOK transmitter with the center frequency tunable from 3GHz to 4GHz, mounted on a separate low loss dielectric board together with a 3V LDO, with output fed to a UWB chip antenna. The IC boards were interconnected and packaged in a polyether ether ketone (PEEK) enclosure which is compatible with both animal and human use (e.g. sterilizable). The entire system consumes 17mA from a 1.2Ahr 3.6V Li-SOCl2 1/2AA battery, which operates the device for more than 2 days. The overall system includes a custom RF receiver electronics which are designed to directly interface with any number of commercial (or custom) neural signal processors for multi-channel broadband neural recording. Bench-top measurements and in vivo testing of the device in rhesus macaques are presented to demonstrate the performance of the wireless neural interface.

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

DTIC Science & Technology

1983-09-01

the ability for systems engineers to custom design digital integrated circuits. Until recently, the design of integrated circuits has been...traditionally carried out by a select group of logic designers working in semiconductor laboratories. Systems engineers had to "make do" or "fit in" the...products of these labs to realize their designs. The systems engineers had little participation in the actual design of the chip. The MED and CONWAY design

Full-custom design of split-set data weighted averaging with output register for jitter suppression

NASA Astrophysics Data System (ADS)

Jubay, M. C.; Gerasta, O. J.

2015-06-01

A full-custom design of an element selection algorithm, named as Split-set Data Weighted Averaging (SDWA) is implemented in 90nm CMOS Technology Synopsys Library. SDWA is applied in seven unit elements (3-bit) using a thermometer-coded input. Split-set DWA is an improved DWA algorithm which caters the requirement for randomization along with long-term equal element usage. Randomization and equal element-usage improve the spectral response of the unit elements due to higher Spurious-free dynamic range (SFDR) and without significantly degrading signal-to-noise ratio (SNR). Since a full-custom, the design is brought to transistor-level and the chip custom layout is also provided, having a total area of 0.3mm2, a power consumption of 0.566 mW, and simulated at 50MHz clock frequency. On this implementation, SDWA is successfully derived and improved by introducing a register at the output that suppresses the jitter introduced at the final stage due to switching loops and successive delays.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

Testing Methods for Integrated Circuit Chips.

DTIC Science & Technology

1986-03-27

DWf <I IAV ~IMi MORY OUT LOGIC~~ IPOGRAM ASYC S’E4i E...* 16o, CO% T ROL CO%TROL 32 Figure 2 . 14 VLSI Tester Block Diagram. registers, memory and test...neral-pIurpos’ processor wi th standard bus- inte-rfaco se-rves as,- th- test control Ii’r and ( 2 ) a c-ustom VLSI test Controller inti-rfacing direc(_t1...Engineering 2 WTWTY ABSTRACT Provision for the functional testing of fabricated VLSI chips frequently involves as much design effort as the orig- _ inal

Sensing systems using chip-based spectrometers

NASA Astrophysics Data System (ADS)

Nitkowski, Arthur; Preston, Kyle J.; Sherwood-Droz, Nicolás.; Behr, Bradford B.; Bismilla, Yusuf; Cenko, Andrew T.; DesRoches, Brandon; Meade, Jeffrey T.; Munro, Elizabeth A.; Slaa, Jared; Schmidt, Bradley S.; Hajian, Arsen R.

2014-06-01

Tornado Spectral Systems has developed a new chip-based spectrometer called OCTANE, the Optical Coherence Tomography Advanced Nanophotonic Engine, built using a planar lightwave circuit with integrated waveguides fabricated on a silicon wafer. While designed for spectral domain optical coherence tomography (SD-OCT) systems, the same miniaturized technology can be applied to many other spectroscopic applications. The field of integrated optics enables the design of complex optical systems which are monolithically integrated on silicon chips. The form factors of these systems can be significantly smaller, more robust and less expensive than their equivalent free-space counterparts. Fabrication techniques and material systems developed for microelectronics have previously been adapted for integrated optics in the telecom industry, where millions of chip-based components are used to power the optical backbone of the internet. We have further adapted the photonic technology platform for spectroscopy applications, allowing unheard-of economies of scale for these types of optical devices. Instead of changing lenses and aligning systems, these devices are accurately designed programmatically and are easily customized for specific applications. Spectrometers using integrated optics have large advantages in systems where size, robustness and cost matter: field-deployable devices, UAVs, UUVs, satellites, handheld scanning and more. We will discuss the performance characteristics of our chip-based spectrometers and the type of spectral sensing applications enabled by this technology.

Burst Mode ASIC-Based Modem

NASA Technical Reports Server (NTRS)

1997-01-01

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

NASA Astrophysics Data System (ADS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S. R.; Stabile, A.

2017-04-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

PubMed

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip

PubMed Central

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min. PMID:23493871

TOXICOGENOMIC ANALYSIS INCORPORATING OPERON-TRANSCRIPTIONAL COUPLING AND TOXICANT CONCENTRATRION-EXPRESSION RESPONSE: Analysis of MX-Treated Salmonella

EPA Science Inventory

What is the study? This study is the first to use microarray analysis in the Ames strains of Salmonella. The microarray chips were custom-designed for this study and are not commercially available, and we evaluated the well-studied drinking water mutagen, MX. Because much inform...

An ultra-compact and low-power oven-controlled crystal oscillator design for precision timing applications.

PubMed

Lim, Jaehyun; Kim, Hyunsoo; Jackson, Thomas; Choi, Kyusun; Kenny, David

2010-09-01

A novel design for a chip-scale miniature oven-controlled crystal oscillator (OCXO) is presented. In this design, all the main components of an OCXO--consisting of an oscillator, a temperature sensor, a heater, and temperature-control circuitry--are integrated on a single CMOS chip. The OCXO package size can be reduced significantly with this design, because the resonator does not require a separate package and most of the circuitry is integrated on a single CMOS chip. Other characteristics such as power consumption and warm-up time are also improved. Two different types of quartz resonators, an AT-cut tab mesa-type quartz crystal and a frame enclosed resonator, allow miniaturization of the OCXO structure. Neither of these quartz resonator types requires a separate package inside the oven structure; therefore, they can each be directly integrated with the custom-designed CMOS chip. The miniature OCXO achieves a frequency stability of +/- 0.35 ppm with an AT-cut tab mesa-type quartz crystal in the temperature range of 0 °C to 60 °C. The maximum power consumption of this miniature OCXO is 1.2 W at start-up and 303 mW at steady state. The warm-up time to reach the steady state is 190 s. These results using the proposed design are better than or the same as high-frequency commercial OCXOs.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

System-on-Chip Data Processing and Data Handling Spaceflight Electronics

NASA Technical Reports Server (NTRS)

Kleyner, I.; Katz, R.; Tiggeler, H.

1999-01-01

This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Experience with custom processors in space flight applications

NASA Technical Reports Server (NTRS)

Fraeman, M. E.; Hayes, J. R.; Lohr, D. A.; Ballard, B. W.; Williams, R. L.; Henshaw, R. M.

1991-01-01

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.

3D-glass molds for facile production of complex droplet microfluidic chips.

PubMed

Tovar, Miguel; Weber, Thomas; Hengoju, Sundar; Lovera, Andrea; Munser, Anne-Sophie; Shvydkiv, Oksana; Roth, Martin

2018-03-01

In order to leverage the immense potential of droplet microfluidics, it is necessary to simplify the process of chip design and fabrication. While polydimethylsiloxane (PDMS) replica molding has greatly revolutionized the chip-production process, its dependence on 2D-limited photolithography has restricted the design possibilities, as well as further dissemination of microfluidics to non-specialized labs. To break free from these restrictions while keeping fabrication straighforward, we introduce an approach to produce complex multi-height (3D) droplet microfluidic glass molds and subsequent chip production by PDMS replica molding. The glass molds are fabricated with sub-micrometric resolution using femtosecond laser machining technology, which allows directly realizing designs with multiple levels or even continuously changing heights. The presented technique significantly expands the experimental capabilities of the droplet microfluidic chip. It allows direct fabrication of multilevel structures such as droplet traps for prolonged observation and optical fiber integration for fluorescence detection. Furthermore, the fabrication of novel structures based on sloped channels (ramps) enables improved droplet reinjection and picoinjection or even a multi-parallelized drop generator based on gradients of confinement. The fabrication of these and other 3D-features is currently only available at such resolution by the presented strategy. Together with the simplicity of PDMS replica molding, this provides an accessible solution for both specialized and non-specialized labs to customize microfluidic experimentation and expand their possibilities.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Whole-Cell Electrical Activity Under Direct Mechanical Stimulus by AFM Cantilever Using Planar Patch Clamp Chip Approach

PubMed Central

Upadhye, Kalpesh V.; Candiello, Joseph E.; Davidson, Lance A.; Lin, Hai

2011-01-01

Patch clamp is a powerful tool for studying the properties of ion-channels and cellular membrane. In recent years, planar patch clamp chips have been fabricated from various materials including glass, quartz, silicon, silicon nitride, polydimethyl-siloxane (PDMS), and silicon dioxide. Planar patch clamps have made automation of patch clamp recordings possible. However, most planar patch clamp chips have limitations when used in combination with other techniques. Furthermore, the fabrication methods used are often expensive and require specialized equipments. An improved design as well as fabrication and characterization of a silicon-based planar patch clamp chip are described in this report. Fabrication involves true batch fabrication processes that can be performed in most common microfabrication facilities using well established MEMS techniques. Our planar patch clamp chips can form giga-ohm seals with the cell plasma membrane with success rate comparable to existing patch clamp techniques. The chip permits whole-cell voltage clamp recordings on variety of cell types including Chinese Hamster Ovary (CHO) cells and pheochromocytoma (PC12) cells, for times longer than most available patch clamp chips. When combined with a custom microfluidics chamber, we demonstrate that it is possible to perfuse the extra-cellular as well as intra-cellular buffers. The chamber design allows integration of planar patch clamp with atomic force microscope (AFM). Using our planar patch clamp chip and microfluidics chamber, we have recorded whole-cell mechanosensitive (MS) currents produced by directly stimulating human keratinocyte (HaCaT) cells using an AFM cantilever. Our results reveal the spatial distribution of MS ion channels and temporal details of the responses from MS channels. The results show that planar patch clamp chips have great potential for multi-parametric high throughput studies of ion channel proteins. PMID:22174731

Dual-scan technique for the customization of zirconia computer-aided design/computer-aided manufacturing frameworks.

PubMed

Andreiuolo, Rafael Ferrone; Sabrosa, Carlos Eduardo; Dias, Katia Regina H Cervantes

2013-09-01

The use of bi-layered all-ceramic crowns has continuously grown since the introduction of computer-aided design/computer-aided manufacturing (CAD/CAM) zirconia cores. Unfortunately, despite the outstanding mechanical properties of zirconia, problems related to porcelain cracking or chipping remain. One of the reasons for this is that ceramic copings are usually milled to uniform thicknesses of 0.3-0.6 mm around the whole tooth preparation. This may not provide uniform thickness or appropriate support for the veneering porcelain. To prevent these problems, the dual-scan technique demonstrates an alternative that allows the restorative team to customize zirconia CAD/CAM frameworks with adequate porcelain thickness and support in a simple manner.

MEMS-based IR-sources

NASA Astrophysics Data System (ADS)

Weise, Sebastian; Steinbach, Bastian; Biermann, Steffen

2016-03-01

The series JSIR350 sources are MEMS based infrared emitters. These IR sources are characterized by a high radiation output. Thus, they are excellent for NDIR gas analysis and are ideally suited for using with our pyro-electric or thermopile detectors. The MEMS chips used in Micro-Hybrid's infrared emitters consist of nano-amorphous carbon (NAC). The MEMS chips are produced in the USA. All Micro-Hybrid Emitter are designed and specified to operate up to 850°C. The improvements we have made in the source's packaging enable us to provide IR sources with the best performance on the market. This new technology enables us to seal the housings of infrared radiation sources with soldered infrared filters or windows and thus cause the parts to be impenetrable to gases. Micro-Hybrid provide various ways of adapting our MEMS based infrared emitter JSIR350 to customer specifications, like specific burn-in parameters/characteristic, different industrial standard housings, producible with customized cap, reflector or pin-out.

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

PubMed

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Flow-cytometric identification of vinegars using a multi-parameter analysis optical detection module

NASA Astrophysics Data System (ADS)

Verschooten, T.; Ottevaere, H.; Vervaeke, M.; Van Erps, J.; Callewaert, M.; De Malsche, W.; Thienpont, H.

2015-09-01

We show a proof-of-concept demonstration of a multi-parameter analysis low-cost optical detection system for the flowcytometric identification of vinegars. This multi-parameter analysis system can simultaneously measure laser induced fluorescence, absorption and scattering excited by two time-multiplexed lasers of different wavelengths. To our knowledge no other polymer optofluidic chip based system offers more simultaneous measurements. The design of the optofluidic channels is aimed at countering the effects that viscous fingering, air bubbles, and emulsion samples can have on the correct operation of such a detection system. Unpredictable variations in viscosity and refractive index of the channel content can be turned into a source of information. The sample is excited by two laser diodes that are driven by custom made low-cost laser drivers. The optofluidic chip is built to be robust and easy to handle and is reproducible using hot embossing. We show a custom optomechanical holder for the optofluidic chip that ensures correct alignment and automatic connection to the external fluidic system. We show an experiment in which 92 samples of vinegar are measured. We are able to identify 9 different kinds of vinegar with an accuracy of 94%. Thus we show an alternative approach to the classic optical spectroscopy solution at a lowered. Furthermore, we have shown the possibility of predicting the viscosity and turbidity of vinegars with a goodness-of-fit R2 over 0.947.

Identification of a single nucleotide polymorphism indicative of high risk in acute myocardial infarction

PubMed Central

Shalia, Kavita; Saranath, Dhananjaya; Rayar, Jaipreet; Shah, Vinod K.; Mashru, Manoj R.; Soneji, Surendra L.

2017-01-01

Background & objectives: Acute myocardial infarction (AMI) is a major health concern in India. The aim of the study was to identify single nucleotide polymorphisms (SNPs) associated with AMI in patients using dedicated chip and validating the identified SNPs on custom-designed chips using high-throughput microarray analysis. Methods: In pilot phase, 48 AMI patients and 48 healthy controls were screened for SNPs using human CVD55K BeadChip with 48,472 SNP probes on Illumina high-throughput microarray platform. The identified SNPs were validated by genotyping additional 160 patients and 179 controls using custom-made Illumina VeraCode GoldenGate Genotyping Assay. Analysis was carried out using PLINK software. Results: From the pilot phase, 98 SNPs present on 94 genes were identified with increased risk of AMI (odds ratio of 1.84-8.85, P=0.04861-0.003337). Five of these SNPs demonstrated association with AMI in the validation phase (P<0.05). Among these, one SNP rs9978223 on interferon gamma receptor 2 [IFNGR2, interferon (IFN)-gamma transducer 1] gene showed a significant association (P=0.00021) with AMI below Bonferroni corrected P value (P=0.00061). IFNGR2 is the second subunit of the receptor for IFN-gamma, an important cytokine in inflammatory reactions. Interpretation & conclusions: The study identified an SNP rs9978223 on IFNGR2 gene, associated with increased risk in AMI patient from India. PMID:29434065

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Additive manufacturing of microfluidic glass chips

NASA Astrophysics Data System (ADS)

Kotz, F.; Helmer, D.; Rapp, B. E.

2018-02-01

Additive manufacturing has gained great interest in the microfluidic community due to the numerous channel designs which can be tested in the early phases of a lab-on-a-chip device development. High resolution additive manufacturing like microstereolithography is largely associated with polymers. Polymers are at a disadvantage compared to other materials due to their softness and low chemical resistance. Whenever high chemical and thermal resistance combined with high optical transparency is needed, glasses become the material of choice. However, glasses are difficult to structure at the microscale requiring hazardous chemicals for etching processes. In this work we present additive manufacturing and high resolution patterning of microfluidic chips in transparent fused silica glass using stereolithography and microlithography. We print an amorphous silica nanocomposite at room temperature using benchtop stereolithography printers and a custom built microlithography system based on a digital mirror device. Using microlithography we printed structures with tens of micron resolution. The printed part is then converted to a transparent fused silica glass using thermal debinding and sintering. Printing of a microfluidic chip can be done within 30 minutes. The heat treatment can be done within two days.

Reconfigurable Very Long Instruction Word (VLIW) Processor

NASA Technical Reports Server (NTRS)

Velev, Miroslav N.

2015-01-01

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

A Compact Polarization Imager

NASA Technical Reports Server (NTRS)

Thompson, Karl E.; Rust, David M.; Chen, Hua

1995-01-01

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

Note: Design and development of wireless controlled aerosol sampling network for large scale aerosol dispersion experiments.

PubMed

Gopalakrishnan, V; Subramanian, V; Baskaran, R; Venkatraman, B

2015-07-01

Wireless based custom built aerosol sampling network is designed, developed, and implemented for environmental aerosol sampling. These aerosol sampling systems are used in field measurement campaign, in which sodium aerosol dispersion experiments have been conducted as a part of environmental impact studies related to sodium cooled fast reactor. The sampling network contains 40 aerosol sampling units and each contains custom built sampling head and the wireless control networking designed with Programmable System on Chip (PSoC™) and Xbee Pro RF modules. The base station control is designed using graphical programming language LabView. The sampling network is programmed to operate in a preset time and the running status of the samplers in the network is visualized from the base station. The system is developed in such a way that it can be used for any other environment sampling system deployed in wide area and uneven terrain where manual operation is difficult due to the requirement of simultaneous operation and status logging.

Note: Design and development of wireless controlled aerosol sampling network for large scale aerosol dispersion experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gopalakrishnan, V.; Subramanian, V.; Baskaran, R.

2015-07-15

Wireless based custom built aerosol sampling network is designed, developed, and implemented for environmental aerosol sampling. These aerosol sampling systems are used in field measurement campaign, in which sodium aerosol dispersion experiments have been conducted as a part of environmental impact studies related to sodium cooled fast reactor. The sampling network contains 40 aerosol sampling units and each contains custom built sampling head and the wireless control networking designed with Programmable System on Chip (PSoC™) and Xbee Pro RF modules. The base station control is designed using graphical programming language LabView. The sampling network is programmed to operate in amore » preset time and the running status of the samplers in the network is visualized from the base station. The system is developed in such a way that it can be used for any other environment sampling system deployed in wide area and uneven terrain where manual operation is difficult due to the requirement of simultaneous operation and status logging.« less

On-chip ultraviolet holography for high-throughput nanoparticle and biomolecule detection

NASA Astrophysics Data System (ADS)

Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltán.; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

2018-02-01

Nanoparticle and biomolecule imaging has become an important need for various applications. In an effort to find a higher throughput alternative to existing devices, we have designed a lensfree on-chip holographic imaging platform operating at an ultraviolet (UV) wavelength of 266 nm. With a custom-designed free-space light delivery system to illuminate the sample that is placed very close (<0.5 mm) to an opto-electronic image sensor chip, without any imaging lenses in between, the full active area of the imager chip (>16 mm2 ) was utilized as the imaging field-of-view (FOV) capturing holographic signatures of target objects on a chip. These holograms were then digitally back propagated to extract both the amplitude and phase information of the sample. The increased forward scattering from nanoparticles due to this shorter illumination wavelength has enabled us to image individual particles that are smaller than 30 nm over an FOV of >16 mm2 . Our platform was further utilized in high-contrast imaging of nanoscopic biomolecule aggregates since 266 nm illumination light is strongly absorbed by biomolecules including proteins and nucleic acids. Aggregates of Cu/Zn-superoxide dismutase (SOD1), which has been linked to a fatal neurodegenerative disease, ALS (amyotrophic lateral sclerosis), have been imaged with significantly improved contrast compared to imaging at visible wavelengths. This unique UV imaging modality could be valuable for biomedical applications (e.g., viral load measurements) and environmental monitoring including air and water quality monitoring.

Programmable synaptic devices for electronic neural nets

NASA Technical Reports Server (NTRS)

Moopenn, A.; Thakoor, A. P.

1990-01-01

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

Miniature and Molecularly Specific Optical Screening Technologies for Breast Cancer

DTIC Science & Technology

2006-10-01

modeling of the heat dissipation effects of compact LEDs on tissue samples, selection of multiwavelength compact light sources, calculating bandwidth...Opto Technology also designs custom chip on board assemblies with single and multiple wavelengths of UV , Visible and IR LED die (365 – 940 nm...reflectance with high signal to noise for optical properties typical of tissue in the UV -VIS. We have furthermore investigated the potential use of LEDs as

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

NASA Astrophysics Data System (ADS)

Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Ho, Jonathan; Wu, Xin; Panaite, Petrisor; Chacko, Manoj; Zhang, Yunqiang; Lei, Wen-Kang

2005-11-01

In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

Picoradio: Communication/Computation Piconodes for Sensor Networks

DTIC Science & Technology

2003-01-02

diagram of PicoNode III, or Quark node. It is made from two custom chips, Strange RF and Charm digital processor , and is complemented by a set of...the chipset comprising of Strange (analog OOK transceiver) and Charm (digital processor ) chips. 44 Figure 33: System block diagram of the Quark node...19 2.B PICONODE II - TWO-CHIP PICONODE IMPLEMENTATION ......................................... 21 2.B.1 Baseband processor (BBP

SVGA and XGA LCOS microdisplays for HMD applications

NASA Astrophysics Data System (ADS)

Bolotski, Michael; Alvelda, Phillip

1999-07-01

MicroDisplay liquid crystal on silicon (LCOS) display devices are based on a combination of technologies combined with the extreme integration capability of conventionally fabricated CMOS substrates. Two recent SVGA (800 X 600) pixel resolution designs were demonstrated based on 10 micron and 12.5-micron pixel pitch architectures. The resulting microdisplays measure approximately 10 mm and 12 mm in diagonal respectively. Further, an XGA (1024 X 768) resolution display fabricated with a 12.5-micron pixel pitch with a 16-mm diagonal was also demonstrated. Both the larger SVGA and the XGA design were based on the same 12.5-micron pixel-pitch design, demonstrating a quickly scalable design architecture for rapid prototyping life-cycles. All three microdisplay designs described above function in grayscale and high-performance Field-Sequential-Color (FSC) operating modes. The fast liquid crystal operating modes and new scalable high- performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable commercial and defense applications including ultra-portable helmet, eyeglass, and heat-mounted systems. The entire suite of The MicroDisplay Corporation's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASIC) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. For helmet and head-mounted displays this can include capabilities such as the incorporation of customized symbology and information storage directly on the display substrate. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Chauveau, J.; Del Buono, L.; Genat, J. F.; Lebbolo, H.; Roos, L.; Zhang, B.; Beigbeder, C.; Bernier, R.; Breton, D.; Caceres, T.; Chase, R.; Ducorps, A.; Hrisoho, A.; Imbert, P.; Sen, S.; Tocut, V.; Truong, K.; Wormser, G.; Zomer, F.; Bonneaud, G.; Dohou, F.; Gastaldi, F.; Matricon, P.; Renard, C.; Thiebaux, C.; Vasileiadis, G.; Verderi, M.; Oxoby, G.; Va'Vra, J.; Warner, D.; Wilson, R. J.

1999-08-01

The detector of Internally Reflected Cherenkov light (DIRC) of the BaBar detector (SLAC Stanford, USA) measures better than 1 ns the arrival time of Cherenkov photoelectrons, detected in a 11 000 phototubes array and their amplitude spectra. It mainly comprises of 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom Analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom Digital TDC chips for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test of the pre-production chips have been performed as well as system tests.

Microfluidic Chips for In Situ Crystal X-ray Diffraction and In Situ Dynamic Light Scattering for Serial Crystallography.

PubMed

Gicquel, Yannig; Schubert, Robin; Kapis, Svetlana; Bourenkov, Gleb; Schneider, Thomas; Perbandt, Markus; Betzel, Christian; Chapman, Henry N; Heymann, Michael

2018-04-24

This protocol describes fabricating microfluidic devices with low X-ray background optimized for goniometer based fixed target serial crystallography. The devices are patterned from epoxy glue using soft lithography and are suitable for in situ X-ray diffraction experiments at room temperature. The sample wells are lidded on both sides with polymeric polyimide foil windows that allow diffraction data collection with low X-ray background. This fabrication method is undemanding and inexpensive. After the sourcing of a SU-8 master wafer, all fabrication can be completed outside of a cleanroom in a typical research lab environment. The chip design and fabrication protocol utilize capillary valving to microfluidically split an aqueous reaction into defined nanoliter sized droplets. This loading mechanism avoids the sample loss from channel dead-volume and can easily be performed manually without using pumps or other equipment for fluid actuation. We describe how isolated nanoliter sized drops of protein solution can be monitored in situ by dynamic light scattering to control protein crystal nucleation and growth. After suitable crystals are grown, complete X-ray diffraction datasets can be collected using goniometer based in situ fixed target serial X-ray crystallography at room temperature. The protocol provides custom scripts to process diffraction datasets using a suite of software tools to solve and refine the protein crystal structure. This approach avoids the artefacts possibly induced during cryo-preservation or manual crystal handling in conventional crystallography experiments. We present and compare three protein structures that were solved using small crystals with dimensions of approximately 10-20 µm grown in chip. By crystallizing and diffracting in situ, handling and hence mechanical disturbances of fragile crystals is minimized. The protocol details how to fabricate a custom X-ray transparent microfluidic chip suitable for in situ serial crystallography. As almost every crystal can be used for diffraction data collection, these microfluidic chips are a very efficient crystal delivery method.

Framework for reanalysis of publicly available Affymetrix® GeneChip® data sets based on functional regions of interest.

PubMed

Saka, Ernur; Harrison, Benjamin J; West, Kirk; Petruska, Jeffrey C; Rouchka, Eric C

2017-12-06

Since the introduction of microarrays in 1995, researchers world-wide have used both commercial and custom-designed microarrays for understanding differential expression of transcribed genes. Public databases such as ArrayExpress and the Gene Expression Omnibus (GEO) have made millions of samples readily available. One main drawback to microarray data analysis involves the selection of probes to represent a specific transcript of interest, particularly in light of the fact that transcript-specific knowledge (notably alternative splicing) is dynamic in nature. We therefore developed a framework for reannotating and reassigning probe groups for Affymetrix® GeneChip® technology based on functional regions of interest. This framework addresses three issues of Affymetrix® GeneChip® data analyses: removing nonspecific probes, updating probe target mapping based on the latest genome knowledge and grouping probes into gene, transcript and region-based (UTR, individual exon, CDS) probe sets. Updated gene and transcript probe sets provide more specific analysis results based on current genomic and transcriptomic knowledge. The framework selects unique probes, aligns them to gene annotations and generates a custom Chip Description File (CDF). The analysis reveals only 87% of the Affymetrix® GeneChip® HG-U133 Plus 2 probes uniquely align to the current hg38 human assembly without mismatches. We also tested new mappings on the publicly available data series using rat and human data from GSE48611 and GSE72551 obtained from GEO, and illustrate that functional grouping allows for the subtle detection of regions of interest likely to have phenotypical consequences. Through reanalysis of the publicly available data series GSE48611 and GSE72551, we profiled the contribution of UTR and CDS regions to the gene expression levels globally. The comparison between region and gene based results indicated that the detected expressed genes by gene-based and region-based CDFs show high consistency and regions based results allows us to detection of changes in transcript formation.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

Evaluation of Bovine High-Density SNP Genotyping Array in Indigenous Dairy Cattle Breeds.

PubMed

Dash, S; Singh, A; Bhatia, A K; Jayakumar, S; Sharma, A; Singh, S; Ganguly, I; Dixit, S P

2018-04-03

In total 52 samples of Sahiwal ( 19 ), Tharparkar ( 17 ), and Gir ( 16 ) were genotyped by using BovineHD SNP chip to analyze minor allele frequency (MAF), genetic diversity, and linkage disequilibrium among these cattle. The common SNPs of BovineHD and 54K SNP Chips were also extracted and evaluated for their performance. Only 40%-50% SNPs of these arrays was found informative for genetic analysis in these cattle breeds. The overall mean of MAF for SNPs of BovineHD SNPChip was 0.248 ± 0.006, 0.241 ± 0.007, and 0.242 ± 0.009 in Sahiwal, Tharparkar and Gir, respectively, while that for 54K SNPs was on lower side. The average Reynold's genetic distance between breeds ranged from 0.042 to 0.055 based on BovineHD Beadchip, and from 0.052 to 0.084 based on 54K SNP Chip. The estimates of genetic diversity based on HD and 54K chips were almost same and, hence, low density chip seems to be good enough to decipher genetic diversity of these cattle breeds. The linkage disequilibrium started decaying (r 2  < 0.2) at 140 kb inter-marker distance and, hence, a 20K low density customized SNP array from HD chip could be designed for genomic selection in these cattle else the 54K Bead Chip as such will be useful.

Research pressure instrumentation for NASA Space Shuttle main engine, modification no. 5

NASA Technical Reports Server (NTRS)

Anderson, P. J.; Nussbaum, P.; Gustafson, G.

1984-01-01

The objective of the research project described is to define and demonstrate methods to advance the state of the art of pressure sensors for the space shuttle main engine (SSME). Silicon piezoresistive technology was utilized in completing tasks: generation and testing of three transducer design concepts for solid state applications; silicon resistor characterization at cryogenic temperatures; experimental chip mounting characterization; frequency response optimization and prototype design and fabrication. Excellent silicon sensor performance was demonstrated at liquid nitrogen temperature. A silicon resistor ion implant dose was customized for SSME temperature requirements. A basic acoustic modeling software program was developed as a design tool to evaluate frequency response characteristics.

From neural-based object recognition toward microelectronic eyes

NASA Technical Reports Server (NTRS)

Sheu, Bing J.; Bang, Sa Hyun

1994-01-01

Engineering neural network systems are best known for their abilities to adapt to the changing characteristics of the surrounding environment by adjusting system parameter values during the learning process. Rapid advances in analog current-mode design techniques have made possible the implementation of major neural network functions in custom VLSI chips. An electrically programmable analog synapse cell with large dynamic range can be realized in a compact silicon area. New designs of the synapse cells, neurons, and analog processor are presented. A synapse cell based on Gilbert multiplier structure can perform the linear multiplication for back-propagation networks. A double differential-pair synapse cell can perform the Gaussian function for radial-basis network. The synapse cells can be biased in the strong inversion region for high-speed operation or biased in the subthreshold region for low-power operation. The voltage gain of the sigmoid-function neurons is externally adjustable which greatly facilitates the search of optimal solutions in certain networks. Various building blocks can be intelligently connected to form useful industrial applications. Efficient data communication is a key system-level design issue for large-scale networks. We also present analog neural processors based on perceptron architecture and Hopfield network for communication applications. Biologically inspired neural networks have played an important role towards the creation of powerful intelligent machines. Accuracy, limitations, and prospects of analog current-mode design of the biologically inspired vision processing chips and cellular neural network chips are key design issues.

A customized metal oxide semiconductor-based gas sensor array for onion quality evaluation: system development and characterization.

PubMed

Konduru, Tharun; Rains, Glen C; Li, Changying

2015-01-12

A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS) sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone), acetonitrile (nitrile), ethyl acetate (ester), and ethanol (alcohol). The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm) of methlypropyl sulfide and two concentrations (145 and 1452 ppm) of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

PubMed Central

Konduru, Tharun; Rains, Glen C.; Li, Changying

2015-01-01

A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS) sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone), acetonitrile (nitrile), ethyl acetate (ester), and ethanol (alcohol). The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm) of methlypropyl sulfide and two concentrations (145 and 1452 ppm) of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage. PMID:25587975

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Sensium: an ultra-low-power wireless body sensor network platform: design & application challenges.

PubMed

Wong, A W; McDonagh, D; Omeni, O; Nunn, C; Hernandez-Silveira, M; Burdett, A J

2009-01-01

In this paper we present a system-on-chip for wireless body sensor networks, which integrates a transceiver, hardware MAC protocol, microprocessor, IO peripherals, memories, ADC and custom sensor interfaces. Addressing the challenges in the design, this paper will continue to discuss the issues in the applications of this technology to body worn monitoring for real-time measurement of ECG, heart rate, physical activity, respiration and/or skin temperature. Two application challenges are described; the real-time measurement of energy expenditure using the LifePebble, and; the development issues surrounding the 'Digital Patch'.

A Hermetic Wireless Subretinal Neurostimulator for Vision Prostheses

PubMed Central

Shire, Douglas B.; Chen, Jinghua; Doyle, Patrick; Gingerich, Marcus D.; Cogan, Stuart F.; Drohan, William A.; Behan, Sonny; Theogarajan, Luke; Wyatt, John L.; Rizzo, Joseph F.

2016-01-01

A miniaturized, hermetically encased, wirelessly operated retinal prosthesis has been developed for preclinical studies in the Yucatan minipig, and includes several design improvements over our previously reported device. The prosthesis attaches conformally to the outside of the eye and electrically drives a microfabricated thin-film polyimide array of sputtered iridium oxide film electrodes. This array is implanted into the subretinal space using a customized ab externo surgical technique. The implanted device includes a hermetic titanium case containing a 15-channel stimulator chip and discrete circuit components. Feedthroughs in the case connect the stimulator chip to secondary power and data receiving coils on the eye and to the electrode array under the retina. Long-term in vitro pulse testing of the electrodes projected a lifetime consistent with typical devices in industry. The final assembly was tested in vitro to verify wireless operation of the system in physiological saline using a custom RF transmitter and primary coils. Stimulation pulse strength, duration, and frequency were programmed wirelessly from a Peripheral Component Interconnect eXtensions for Instrumentation (PXI) computer. Operation of the retinal implant has been verified in two pigs for up to five and a half months by detecting stimulus artifacts generated by the implanted device. PMID:21859595

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

Miniature atomic scalar magnetometer for space based on the rubidium isotope 87Rb.

PubMed

Korth, Haje; Strohbehn, Kim; Tejada, Francisco; Andreou, Andreas G; Kitching, John; Knappe, Svenja; Lehtonen, S John; London, Shaughn M; Kafel, Matiwos

2016-08-01

A miniature atomic scalar magnetometer based on the rubidium isotope 87 Rb was developed for operation in space. The instrument design implements both M x and M z mode operation and leverages a novel microelectromechanical system (MEMS) fabricated vapor cell and a custom silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS) integrated circuit. The vapor cell has a volume of only 1 mm 3 so that it can be efficiently heated to its operating temperature by a specially designed, low-magnetic-field-generating resistive heater implemented in multiple metal layers of the transparent sapphire substrate of the SOS-CMOS chips. The SOS-CMOS chip also hosts the Helmholtz coil and associated circuitry to stimulate the magnetically sensitive atomic resonance and temperature sensors. The prototype instrument has a total mass of fewer than 500 g and uses less than 1 W of power, while maintaining a sensitivity of 15 pT/√Hz at 1 Hz, comparable to present state-of-the-art absolute magnetometers.

Developing a gate-array capability at a research and development laboratory

NASA Astrophysics Data System (ADS)

Balch, J. W.; Current, K. W.; Magnuson, W. G., Jr.; Pocha, M. D.

1983-03-01

Experiences in developing a gate array capability for low volume applications in a research and development (R and D) laboratory are described. By purchasing unfinished wafers and doing the customization steps in-house. Turnaround time was shortened to as little as one week and the direct costs reduced to as low as $5K per design. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate array design and fabrication services, it was determined that objectives would best be met by using existing internal integrated circuit fabrication facilities, the COMPUTERVISION interactive graphics layout system, and extensive computational capabilities. The reasons and the approach taken for; selection for a particular gate array wafer, adapting a particular logic simulation program, and how layout aids were enhanced are discussed. Testing of the customized chips is described. The content, schedule, and results of the internal gate array course recently completed are discussed. Finally, problem areas and near term plans are presented.

VLSI chip-set for data compression using the Rice algorithm

NASA Technical Reports Server (NTRS)

Venbrux, J.; Liu, N.

1990-01-01

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Beigbeder, C.; Bernier, R.; Breton, D.; Bonneaud, G.; Caceres, T.; Chase, R.; Chauveau, J.; Del Buono, L.; Dohou, F.; Ducorps, A.; Gastaldi, F.; Genat, J. F.; Hrisoho, A.; Imbert, P.; Lebbolo, H.; Matricon, P.; Oxoby, G.; Renard, C.; Roos, L.; Sen, S.; Thiebaux, C.; Truong, K.; Tocut, V.; Vasileiadis, G.; Va'Vra, J.; Verderi, M.; Warner, D.; Wilson, R. J.; Wormser, G.; Zhang, B.; Zomer, F.

2000-12-01

Recent results from the Front-End electronics of the Detector of Internally Reflected Cerenkov light (DIRC) for the BaBar experiment at SLAC (Stanford, USA) are presented. It measures to better than 1 ns the arrival time of Cerenkov photoelectrons detected in a 11000 phototubes array and their amplitude spectra. It mainly comprises 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom digital time to digital chips (TDC) for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected front up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of the pre-production chips are presented, as well as system tests.

Universal lab-on-a-chip platform for complex, perfused 3D cell cultures

NASA Astrophysics Data System (ADS)

Sonntag, F.; Schmieder, F.; Ströbel, J.; Grünzner, S.; Busek, M.; Günther, K.; Steege, T.; Polk, C.; Klotzbach, U.

2016-03-01

The miniaturization, rapid prototyping and automation of lab-on-a-chip technology play nowadays a very important role. Lab-on-a-chip technology is successfully implemented not only for environmental analysis and medical diagnostics, but also as replacement of animals used for the testing of substances in the pharmaceutical and cosmetics industries. For that purpose the Fraunhofer IWS and partners developed a lab-on-a-chip platform for perfused cell-based assays in the last years, which includes different micropumps, valves, channels, reservoirs and customized cell culture modules. This technology is already implemented for the characterization of different human cell cultures and organoids, like skin, liver, endothelium, hair follicle and nephron. The advanced universal lab-on-a-chip platform for complex, perfused 3D cell cultures is divided into a multilayer basic chip with integrated micropump and application-specific 3D printed cell culture modules. Moreover a technology for surface modification of the printed cell culture modules by laser micro structuring and a complex and flexibly programmable controlling device based on an embedded Linux system was developed. A universal lab-on-a-chip platform with an optional oxygenator and a cell culture module for cubic scaffolds as well as first cell culture experiments within the cell culture device will be presented. The module is designed for direct interaction with robotic dispenser systems. This offers the opportunity to combine direct organ printing of cells and scaffolds with the microfluidic cell culture module. The characterization of the developed system was done by means of Micro-Particle Image Velocimetry (μPIV) and an optical oxygen measuring system.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

NASA Technical Reports Server (NTRS)

Pin, Francois G.; Watanabe, Yutaka

1993-01-01

Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human-like reasoning schemes which may include as little as six elemental behaviors embodied in fourteen qualitative rules.

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

NASA Astrophysics Data System (ADS)

Takashima, Ichiro; Kajiwara, Riichi; Murano, Kiyo; Iijima, Toshio; Morinaka, Yasuhiro; Komobuchi, Hiroyoshi

2001-04-01

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

Photonic content-addressable memory system that uses a parallel-readout optical disk

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Ashok V.; Marchand, Philippe J.; Yayla, Gökçe; Esener, Sadik C.

1995-11-01

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 \\times 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Radiometer on a Chip

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Gill, John J.; Mehdi, Imran; Lee, Choonsup; Schlecht, Erich T.; Skalare, Anders; Ward, John S.; Siegel, Peter H.; Thomas, Bertrand C.

2009-01-01

The radiometer on a chip (ROC) integrates whole wafers together to p rovide a robust, extremely powerful way of making submillimeter rece ivers that provide vertically integrated functionality. By integratin g at the wafer level, customizing the interconnects, and planarizing the transmission media, it is possible to create a lightweight asse mbly performing the function of several pieces in a more conventiona l radiometer.

Nanoscale Kerr Nonlinearity Enhancement Using Spontaneously Generated Coherence in Plasmonic Nanocavity

PubMed Central

Chen, Hongyi; Ren, Juanjuan; Gu, Ying; Zhao, Dongxing; Zhang, Junxiang; Gong, Qihuang

2015-01-01

The enhancement of the optical nonlinear effects at nanoscale is important in the on-chip optical information processing. We theoretically propose the mechanism of the great Kerr nonlinearity enhancement by using anisotropic Purcell factors in a double-Λ type four-level system, i.e., if the bisector of the two vertical dipole moments lies in the small/large Purcell factor axis in the space, the Kerr nonlinearity will be enhanced/decreased due to the spontaneously generated coherence accordingly. Besides, when the two dipole moments are parallel, the extremely large Kerr nonlinearity increase appears, which comes from the double population trapping. Using the custom-designed resonant plasmonic nanostructure which gives an anisotropic Purcell factor environment, we demonstrate the effective nanoscale control of the Kerr nonlinearity. Such controllable Kerr nonlinearity may be realized by the state-of-the-art nanotechnics and it may have potential applications in on-chip photonic nonlinear devices. PMID:26670939

Modular microfluidics for point-of-care protein purifications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Millet, L. J.; Lucheon, J. D.; Standaert, R. F.

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured tomore » suit a variety of fluidic operations or biochemical processes. In conclusion, we demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.« less

Modular microfluidics for point-of-care protein purifications.

PubMed

Millet, L J; Lucheon, J D; Standaert, R F; Retterer, S T; Doktycz, M J

2015-04-21

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured to suit a variety of fluidic operations or biochemical processes. We demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.

Modular microfluidics for point-of-care protein purifications

DOE PAGES

Millet, L. J.; Lucheon, J. D.; Standaert, R. F.; ...

2015-01-01

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured tomore » suit a variety of fluidic operations or biochemical processes. In conclusion, we demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.« less

Get inside the lives of your customers.

PubMed

Seybold, P B

2001-05-01

Many companies have become adept at the art of customer relationship management. They've collected mountains of data on preferences and behavior, divided buyers into ever-finer segments, and refined their products, services, and marketing pitches. But all too often those efforts are too narrow--they concentrate only on the points where the customer comes into contact with the company. Few businesses have bothered to look at what the author calls the customer scenario--the broad context in which customers select, buy, and use products and services. As a result, consultant Patricia Seybold maintains, they've routinely missed chances to deepen loyalty and expand sales. In this article, the author shows how effective three very different companies have been at using customer scenarios as the centerpiece of their marketing plans. Chip maker National Semiconductor looked beyond the purchasing agents that buy in bulk to find ways to make it easier for engineers to design National's components into their specifications for mobile telephones. Each time they do so, it translates into millions of dollars in orders. By developing a customer scenario that describes how people actually shop for groceries, Tesco learned the importance of decentralizing its Web shopping site and how the extra costs of decentralization could be outweighed by the higher profit margins on-line customers generate. And Buzzsaw.com used customer scenarios as the basis for its entire business. It has used the Web to create a better way for the dozens of participants in a construction project to share their drawings and manage their projects. Seybold lays out the steps managers can take to develop their own customer scenarios. By thinking broadly about the challenges your customers face, she suggests, you can almost always find ways to make their lives easier--and thus earn their loyalty.

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

NASA Astrophysics Data System (ADS)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

High data rate Reed-Solomon encoding and decoding using VLSI technology

NASA Technical Reports Server (NTRS)

Miller, Warner; Morakis, James

1987-01-01

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

ATLAS FTK a - very complex - custom super computer

NASA Astrophysics Data System (ADS)

Kimura, N.; ATLAS Collaboration

2016-10-01

In the LHC environment for high interaction pile-up, advanced techniques of analysing the data in real time are required in order to maximize the rate of physics processes of interest with respect to background processes. The Fast TracKer (FTK) is a track finding implementation at the hardware level that is designed to deliver full-scan tracks with pT above 1 GeV to the ATLAS trigger system for events passing the Level-1 accept (at a maximum rate of 100 kHz). In order to achieve this performance, a highly parallel system was designed and currently it is being commissioned within in ATLAS. Starting in 2016 it will provide tracks for the trigger system in a region covering the central part of the ATLAS detector, and will be extended to the full detector coverage. The system relies on matching hits coming from the silicon tracking detectors against one billion patterns stored in custom ASIC chips (Associative memory chip - AM06). In a first stage, coarse resolution hits are matched against the patterns and the accepted hits undergo track fitting implemented in FPGAs. Tracks with pT > 1GeV are delivered to the High Level Trigger within about 100 ps. Resolution of the tracks coming from FTK is close to the offline tracking and it will allow for reliable detection of primary and secondary vertexes at trigger level and improved trigger performance for b-jets and tau leptons. This contribution will give an overview of the FTK system and present the status of commissioning of the system. Additionally, the expected FTK performance will be briefly described.

GRAPE-4: A special-purpose computer for gravitational N-body problems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Makino, Junichiro; Taiji, Makoto; Ebisuzaki, Toshikazu

1995-12-01

We describe GRAPE-4, a special-purpose computer for gravitational N-body simulations. In gravitational N-body simulations, almost all computing time is spent for the calculation of interaction between particles. GRAPE-4 is a specialized hardware to calculate the interaction between particles. It is used with a general-purpose host computer that performs all calculations other than the force calculation. With this architecture, it is relatively easy to realize a massively parallel system. In 1991, we developed the GRAPE-3 system with the peak speed equivalent to 14.4 Gflops. It consists of 48 custom pipelined processors. In 1992 we started the development of GRAPE-4. The GRAPE-4more » system will consist of 1920 custom pipeline chips. Each chip has the speed of 600 Mflops, when operated on 30 MHz clock. A prototype system with two custom LSIs has been completed July 1994, and the full system is now under manufacturing.« less

Adsorption and isolation of nucleic acids on cellulose magnetic beads using a three-dimensional printed microfluidic chip

PubMed Central

Zhang, Lei; Deraney, Rachel N.; Tripathi, Anubhav

2015-01-01

While advances in genomics have enabled sensitive and highly parallel detection of nucleic acid targets, the isolation and extraction of the nucleic acids remain a critical bottleneck in the workflow. We present here a simple 3D printed microfluidic chip that allows for the vortex and centrifugation free extraction of nucleic acids. This novel microfluidic chip utilizes the presence of a water and oil interface to filter out the lysate contaminants. The pure nucleic acids, while bound on cellulose particles, are magnetically moved across the oil layer. We demonstrated efficient and rapid extraction of spiked Human Papillomavirus (HPV) 18 plasmids in specimen transport medium, in under 15 min. An overall extraction efficiency of 61% is observed across a range of HPV plasmid concentrations (5 × 101 to 5 × 106 copies/100 μl). The magnetic, interfacial, and viscous drag forces inside the microgeometries of the chip are modeled. We have also developed a kinetics model for the adsorption of nucleic acids on cellulose functionalized superparamagnetic beads. We also clarify here the role of carrier nucleic acids in the adsorption and isolation of nucleic acids. Based on the various mechanistic insights detailed here, customized microfluidic devices can be designed to meet the range of current and emerging point of care diagnostics needs. PMID:26734116

275 C Downhole Microcomputer System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chris Hutchens; Hooi Miin Soo

2008-08-31

An HC11 controller IC and along with serial SRAM and ROM support ICs chip set were developed to support a data acquisition and control for extreme temperature/harsh environment conditions greater than 275 C. The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications and was the logical choice for a downhole controller. This extreme temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs, The microcomputer chip consists of the microprocessormore » ALU, a small boot ROM, 4 kbyte data RAM, counter/timer unit, serial peripheral interface (SPI), asynchronous serial interface (SCI), and the A, B, C, and D parallel ports. The chip is code compatible with the single chip mode commercial 68HC11 except for the absence of the analog to digital converter system. To avoid mask programmed internal ROM, a boot program is used to load the microcomputer program from an external mask SPI ROM. A SPI RAM IC completes the chip set and allows data RAM to be added in 4 kbyte increments. The HC11 controller IC chip set is implemented in the Peregrine Semiconductor 0.5 micron Silicon-on-Sapphire (SOS) process using a custom high temperature cell library developed at Oklahoma State University. Yield data is presented for all, the HC11, SPI-RAM and ROM. The lessons learned in this project were extended to the successful development of two high temperature versions of the LEON3 and a companion 8 Kbyte SRAM, a 200 C version for the Navy and a 275 C version for the gas industry.« less

Optimised to Fail: Card Readers for Online Banking

NASA Astrophysics Data System (ADS)

Drimer, Saar; Murdoch, Steven J.; Anderson, Ross

The Chip Authentication Programme (CAP) has been introduced by banks in Europe to deal with the soaring losses due to online banking fraud. A handheld reader is used together with the customer’s debit card to generate one-time codes for both login and transaction authentication. The CAP protocol is not public, and was rolled out without any public scrutiny. We reverse engineered the UK variant of card readers and smart cards and here provide the first public description of the protocol. We found numerous weaknesses that are due to design errors such as reusing authentication tokens, overloading data semantics, and failing to ensure freshness of responses. The overall strategic error was excessive optimisation. There are also policy implications. The move from signature to PIN for authorising point-of-sale transactions shifted liability from banks to customers; CAP introduces the same problem for online banking. It may also expose customers to physical harm.

A front-end readout mixed chip for high-efficiency small animal PET imaging

NASA Astrophysics Data System (ADS)

Ollivier-Henry, N.; Berst, J. D.; Colledani, C.; Hu-Guo, Ch.; Mbow, N. A.; Staub, D.; Guyonnet, J. L.; Hu, Y.

2007-02-01

Today, the main challenge of Positron Emission Tomography (PET) systems dedicated to small animal imaging is to obtain high detection efficiency and a highly accurate localization of radioisotopes. If we focus only on the PET characteristics such as the spatial resolution, its accuracy depends on the design of detector and on the electronics readout system as well. In this paper, we present a new design of such readout system with full custom submicrometer CMOS implementation. The front end chip consists of two main blocks from which the energy information and the time stamp with subnanosecond resolution can be obtained. In our A Multi-Modality Imaging System for Small Animal (AMISSA) PET system design, a matrix of LYSO crystals has to be read at each end by a 64 channels multianode photomultiplier tube. A specific readout electronic has been developed at the Hubert Curien Multidisciplinary Institute (IPHC, France). The architecture of this readout for the energy information detection is composed of a low-noise preamplifier, a CR-RC shaper and an analogue memory. In order to obtain the required dynamic range from 15 to 650 photoelectrons with good linearity, a current mode approach has been chosen for the preamplifier. To detect the signal with a temporal resolution of 1 ns, a comparator with a very low threshold (˜0.3 photoelectron) has been implemented. It gives the time reference of arrival signal coming from the detector. In order to obtain the time coincidence with a temporal resolution of 1 ns, a Time-to-Digital Converter (TDC) based on a Delay-Locked-Loop (DLL) has been designed. The chip is fabricated with AMS 0.35 μm process. The ASIC architecture and some simulation results will be presented in the paper.

Ultrafast electric phase control of a single exciton qubit

NASA Astrophysics Data System (ADS)

Widhalm, Alex; Mukherjee, Amlan; Krehs, Sebastian; Sharma, Nandlal; Kölling, Peter; Thiede, Andreas; Reuter, Dirk; Förstner, Jens; Zrenner, Artur

2018-03-01

We report on the coherent phase manipulation of quantum dot excitons by electric means. For our experiments, we use a low capacitance single quantum dot photodiode which is electrically controlled by a custom designed SiGe:C BiCMOS chip. The phase manipulation is performed and quantified in a Ramsey experiment, where ultrafast transient detuning of the exciton energy is performed synchronous to double pulse π/2 ps laser excitation. We are able to demonstrate electrically controlled phase manipulations with magnitudes up to 3π within 100 ps which is below the dephasing time of the quantum dot exciton.

Backside illuminated CMOS-TDI line scan sensor for space applications

NASA Astrophysics Data System (ADS)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Monitoring activities of daily living based on wearable wireless body sensor network.

PubMed

Kańtoch, E; Augustyniak, P; Markiewicz, M; Prusak, D

2014-01-01

With recent advances in microprocessor chip technology, wireless communication, and biomedical engineering it is possible to develop miniaturized ubiquitous health monitoring devices that are capable of recording physiological and movement signals during daily life activities. The aim of the research is to implement and test the prototype of health monitoring system. The system consists of the body central unit with Bluetooth module and wearable sensors: the custom-designed ECG sensor, the temperature sensor, the skin humidity sensor and accelerometers placed on the human body or integrated with clothes and a network gateway to forward data to a remote medical server. The system includes custom-designed transmission protocol and remote web-based graphical user interface for remote real time data analysis. Experimental results for a group of humans who performed various activities (eg. working, running, etc.) showed maximum 5% absolute error compared to certified medical devices. The results are promising and indicate that developed wireless wearable monitoring system faces challenges of multi-sensor human health monitoring during performing daily activities and opens new opportunities in developing novel healthcare services.

Chemiluminescence generation and detection in a capillary-driven microfluidic chip

NASA Astrophysics Data System (ADS)

Ramon, Charlotte; Temiz, Yuksel; Delamarche, Emmanuel

2017-02-01

The use of microfluidic technology represents a strong opportunity for providing sensitive, low-cost and rapid diagnosis at the point-of-care and such a technology might therefore support better, faster and more efficient diagnosis and treatment of patients at home and in healthcare settings both in developed and developing countries. In this work, we consider luminescence-based assays as an alternative to well-established fluorescence-based systems because luminescence does not require a light source or expensive optical components and is therefore a promising detection method for point-of-care applications. Here, we show a proof-of-concept of chemiluminescence (CL) generation and detection in a capillary-driven microfluidic chip for potential immunoassay applications. We employed a commercial acridan-based reaction, which is catalyzed by horseradish peroxidase (HRP). We investigated CL generation under flow conditions using a simplified immunoassay model where HRP is used instead of the complete sandwich immunocomplex. First, CL signals were generated in a capillary microfluidic chip by immobilizing HRP on a polydimethylsiloxane (PDMS) sealing layer using stencil deposition and flowing CL substrate through the hydrophilic channels. CL signals were detected using a compact (only 5×5×2.5 cm3) and custom-designed scanner, which was assembled for less than $30 and comprised a 128×1 photodiode array, a mini stepper motor, an Arduino microcontroller, and a 3D-printed housing. In addition, microfluidic chips having specific 30-μm-deep structures were fabricated and used to immobilize ensembles of 4.50 μm beads functionalized with HRP so as to generate high CL signals from capillary-driven chips.

Custom oligonucleotide array-based CGH: a reliable diagnostic tool for detection of exonic copy-number changes in multiple targeted genes

PubMed Central

Vasson, Aurélie; Leroux, Céline; Orhant, Lucie; Boimard, Mathieu; Toussaint, Aurélie; Leroy, Chrystel; Commere, Virginie; Ghiotti, Tiffany; Deburgrave, Nathalie; Saillour, Yoann; Atlan, Isabelle; Fouveaut, Corinne; Beldjord, Cherif; Valleix, Sophie; Leturcq, France; Dodé, Catherine; Bienvenu, Thierry; Chelly, Jamel; Cossée, Mireille

2013-01-01

The frequency of disease-related large rearrangements (referred to as copy-number mutations, CNMs) varies among genes, and search for these mutations has an important place in diagnostic strategies. In recent years, CGH method using custom-designed high-density oligonucleotide-based arrays allowed the development of a powerful tool for detection of alterations at the level of exons and made it possible to provide flexibility through the possibility of modeling chips. The aim of our study was to test custom-designed oligonucleotide CGH array in a diagnostic laboratory setting that analyses several genes involved in various genetic diseases, and to compare it with conventional strategies. To this end, we designed a 12-plex CGH array (135k; 135 000 probes/subarray) (Roche Nimblegen) with exonic and intronic oligonucleotide probes covering 26 genes routinely analyzed in the laboratory. We tested control samples with known CNMs and patients for whom genetic causes underlying their disorders were unknown. The contribution of this technique is undeniable. Indeed, it appeared reproducible, reliable and sensitive enough to detect heterozygous single-exon deletions or duplications, complex rearrangements and somatic mosaicism. In addition, it improves reliability of CNM detection and allows determination of boundaries precisely enough to direct targeted sequencing of breakpoints. All of these points, associated with the possibility of a simultaneous analysis of several genes and scalability ‘homemade' make it a valuable tool as a new diagnostic approach of CNMs. PMID:23340513

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

NASA Technical Reports Server (NTRS)

Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan;

A Millimeter-Wave Digital Link for Wireless MRI

PubMed Central

Aggarwal, Kamal; Joshi, Kiran R.; Rajavi, Yashar; Taghivand, Mazhareddin; Pauly, John M.; Poon, Ada S. Y.; Scott, Greig

2017-01-01

A millimeter (mm) wave radio is presented in this work to support wireless MRI data transmission. High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI. The proposed system uses a custom designed integrated chip (IC) mm-wave radio with 60 GHz as radio frequency carrier. In this work, we assess performance in a 1.5 T MRI field, with the addition of optical links between the console room and magnet. The system uses ON-OFF keying (OOK) modulation for data transmission and supports data rates from 200 Mb/s to 2.5 Gb/s for distances up-to 65 cm. The presence of highly directional, linearly polarized, on-chip dipole antennas on the mm-wave radio along with the time division multiplexing (TDM) circuitry allows multiple wireless links to be created simultaneously with minimal inter-channel interference. This leads to a highly scalable solution for wireless MRI. PMID:27810803

A Millimeter-Wave Digital Link for Wireless MRI.

PubMed

Aggarwal, Kamal; Joshi, Kiran R; Rajavi, Yashar; Taghivand, Mazhareddin; Pauly, John M; Poon, Ada S Y; Scott, Greig

2017-02-01

A millimeter (mm) wave radio is presented in this work to support wireless MRI data transmission. High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI. The proposed system uses a custom designed integrated chip (IC) mm-wave radio with 60 GHz as radio frequency carrier. In this work, we assess performance in a 1.5 T MRI field, with the addition of optical links between the console room and magnet. The system uses ON-OFF keying (OOK) modulation for data transmission and supports data rates from 200 Mb/s to 2.5 Gb/s for distances up-to 65 cm. The presence of highly directional, linearly polarized, on-chip dipole antennas on the mm-wave radio along with the time division multiplexing (TDM) circuitry allows multiple wireless links to be created simultaneously with minimal inter-channel interference. This leads to a highly scalable solution for wireless MRI.

Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Tehrani, N. Alipour; Arfaoui, S.; Benoit, M.; Dannheim, D.; Dette, K.; Hynds, D.; Kulis, S.; Perić, I.; Petrič, M.; Redford, S.; Sicking, E.; Valerio, P.

2016-07-01

The vertex detector at the proposed CLIC multi-TeV linear e+e- collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120 GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at -60 V substrate bias, with a single hit resolution of 6.1 μm . Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

A pilot study comparing custom contoured and planar support surfaces for pressure ulcer risk over the heels for night time postural management using interface pressure mapping and discomfort scores.

PubMed

Hosking, J

2017-08-01

Custom contouring techniques are effective for reducing pressure ulcer risk in wheelchair seating. These techniques may assist the management of pressure ulcer risk during sleep for night time postural management. To investigate the effectiveness of custom contoured night time postural management components against planar support surfaces for pressure ulcer risk measures over the heels. Supine posture was captured from five healthy participants using vacuum consolidation and 3-dimensional laser scanning. Custom contoured abduction wedges were carved from polyurethane and chipped foams. Pressure mapping and the visual analog scale were used to evaluate the effectiveness of the contoured foams in reducing pressure and discomfort under the posterior heel against standard planar support surfaces. Custom contoured shapes significantly reduced interface pressures (p < 0.05) and discomfort scores (p < 0.05) when compared to planar support surfaces. Polyurethane foam was the most effective material but it did not differ significantly from chipped foam. Linear regression revealed a significant relationship between the Peak Pressure Index and discomfort scores (r = 0.997, p = 0.003). The findings of this pilot study suggested that custom contoured shapes were more effective than planar surfaces at reducing pressure ulcer risk surrogate measures over the posterior heels with polyurethane foam being the most effective material investigated. It is recommended that Evazote foam should not be used as a support surface material for night time postural management. Crown Copyright © 2017. Published by Elsevier Ltd. All rights reserved.

SRAM Detector Calibration

NASA Technical Reports Server (NTRS)

Soli, G. A.; Blaes, B. R.; Beuhler, M. G.

1994-01-01

Custom proton sensitive SRAM chips are being flown on the BMDO Clementine missions and Space Technology Research Vehicle experiments. This paper describes the calibration procedure for the SRAM proton detectors and their response to the space environment.

Media processors using a new microsystem architecture designed for the Internet era

NASA Astrophysics Data System (ADS)

Wyland, David C.

1999-12-01

The demands of digital image processing, communications and multimedia applications are growing more rapidly than traditional design methods can fulfill them. Previously, only custom hardware designs could provide the performance required to meet the demands of these applications. However, hardware design has reached a crisis point. Hardware design can no longer deliver a product with the required performance and cost in a reasonable time for a reasonable risk. Software based designs running on conventional processors can deliver working designs in a reasonable time and with low risk but cannot meet the performance requirements. What is needed is a media processing approach that combines very high performance, a simple programming model, complete programmability, short time to market and scalability. The Universal Micro System (UMS) is a solution to these problems. The UMS is a completely programmable (including I/O) system on a chip that combines hardware performance with the fast time to market, low cost and low risk of software designs.

Microfluidic immunomagnetic cell separation from whole blood.

PubMed

Bhuvanendran Nair Gourikutty, Sajay; Chang, Chia-Pin; Puiu, Poenar Daniel

2016-02-01

Immunomagnetic-based separation has become a viable technique for the separation of cells and biomolecules. Here we report on the design and analysis of a simple and efficient microfluidic device for high throughput and high efficiency capture of cells tagged with magnetic particles. This is made possible by using a microfluidic chip integrated with customized arrays of permanent magnets capable of creating large magnetic field gradients, which determine the effective capturing of the tagged cells. This method is based on manipulating the cells which are under the influence of a combination of magnetic and fluid dynamic forces in a fluid under laminar flow through a microfluidic chip. A finite element analysis (FEA) model is developed to analyze the cell separation process and predict its behavior, which is validated subsequently by the experimental results. The magnetic field gradients created by various arrangements of magnetic arrays have been simulated using FEA and the influence of these field gradients on cell separation has been studied with the design of our microfluidic chip. The proof-of-concept for the proposed technique is demonstrated by capturing white blood cells (WBCs) from whole human blood. CD45-conjugated magnetic particles were added into whole blood samples to label WBCs and the mixture was flown through our microfluidic device to separate the labeled cells. After the separation process, the remaining WBCs in the elute were counted to determine the capture efficiency, and it was found that more than 99.9% WBCs have been successfully separated from whole blood. The proposed design can be used for positive selection as well as for negative enrichment of rare cells. Copyright © 2015 Elsevier B.V. All rights reserved.

Transcriptional effect of an Aframomum angustifolium seed extract on human cutaneous cells using low-density DNA chips.

PubMed

Bonnet-Duquennoy, Mathilde; Dumas, Marc; Debacker, Adeline; Lazou, Kristell; Talbourdet, Sylvie; Franchi, Jocelyne; Heusèle, Catherine; André, Patrice; Schnebert, Sylvianne; Bonté, Frédéric; Kurfürst, Robin

2007-06-01

Studying photoexposed and photoprotected skin biopsies from young and aged women, it has been found that a specific zone, composed of the basal layers of the epidermis, the dermal epidermal junction, and the superficial dermis, is major target of aging and reactive oxygen species. We showed that this zone is characterized by significant variations at a transcriptional and/or protein levels. Using low-density DNA chip technology, we evaluated the effect of a natural mixture of Aframomum angustifolium seed extract containing labdane diterpenoids on these aging markers. Expression profiles of normal human fibroblasts (NHF) were studied using a customized cDNA macroarray system containing genes covering dermal structure, inflammatory responses, and oxidative stress defense mechanisms. For normal human keratinocyte (NHK) investigations, we chose OLISA technique, a sensitive and quantitative method developed by BioMérieux specifically designed to investigate cell death, proliferation, epidermal structure, differentiation, and oxidative stress defense response. We observed that this extract strongly modified gene expression profiles of treated NHK, but weakly for NHF. This extract regulated antioxidant defenses, dermal-epidermal junction components, and epidermal renewal-related genes. Using low-density DNA chip technology, we identified new potential actions of A. angustifolium seed extract on skin aging.

Automated Lab-on-a-Chip Technology for Fish Embryo Toxicity Tests Performed under Continuous Microperfusion (μFET).

PubMed

Zhu, Feng; Wigh, Adriana; Friedrich, Timo; Devaux, Alain; Bony, Sylvie; Nugegoda, Dayanthi; Kaslin, Jan; Wlodkowic, Donald

2015-12-15

The fish embryo toxicity (FET) biotest has gained popularity as one of the alternative approaches to acute fish toxicity tests in chemical hazard and risk assessment. Despite the importance and common acceptance of FET, it is still performed in multiwell plates and requires laborious and time-consuming manual manipulation of specimens and solutions. This work describes the design and validation of a microfluidic Lab-on-a-Chip technology for automation of the zebrafish embryo toxicity test common in aquatic ecotoxicology. The innovative device supports rapid loading and immobilization of large numbers of zebrafish embryos suspended in a continuous microfluidic perfusion as a means of toxicant delivery. Furthermore, we also present development of a customized mechatronic automation interface that includes a high-resolution USB microscope, LED cold light illumination, and miniaturized 3D printed pumping manifolds that were integrated to enable time-resolved in situ analysis of developing fish embryos. To investigate the applicability of the microfluidic FET (μFET) in toxicity testing, copper sulfate, phenol, ethanol, caffeine, nicotine, and dimethyl sulfoxide were tested as model chemical stressors. Results obtained on a chip-based system were compared with static protocols performed in microtiter plates. This work provides evidence that FET analysis performed under microperfusion opens a brand new alternative for inexpensive automation in aquatic ecotoxicology.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

The 150 ns detector project: Prototype preamplifier results

NASA Astrophysics Data System (ADS)

Warburton, W. K.; Russell, S. R.; Kleinfelder, Stuart A.

1994-08-01

The long-term goal of the 150 ns detector project is to develop a pixel area detector capable of 6 MHz frame rates (150 ns/frame). Our milestones toward this goal are: a single pixel, 1×256 1D and 8×8 2D detectors, 256×256 2D detectors and, finally, 1024 × 1024 2D detectors. The design strategy is to supply a complete electronics chain (resetting preamp, selectable gain amplifier, analog-to-digital converter (ADC), and memory) for each pixel. In the final detectors these will all be custom integrated circuits. The front-end preamplifiers are integrated first, since their design and performance are the most unusual and also critical to the project's success. Similarly, our early work is concentrated on devising and perfecting detector structures. In this paper we demonstrate the performance of prototypes of our integrated preamplifiers. While the final design will have 64 preamps to a chip, including a switchable gain stage, the prototypes were integrated 8 channels to a "Tiny Chip" and tested in 4 configurations (feedback capacitor Cf equal 2.5 or 4.0 pF, output directly or through a source follower). These devices have been tested thoroughly for reset settling times, gain, linearity, and electronic noise. They generally work as designed, being fast enough to easily integrate detector charge, settle, and reset in 150 ns. Gain and linearity appear to be acceptable. Current values of electronic noise, in double-sampling mode, are about twice the design goal of {2}/{3} of a single photon at 6 keV. We expect this figure to improve with the addition of the onboard amplifier stage and improved packaging. Our next test chip will include these improvements and allow testing with our first detector samples, which will be 1×256 (50 μm wide pixels) and 8×8 (1 mm 2 pixels) element detector on 1 mm thick silicon.

A lab-on-chip for malaria diagnosis and surveillance

PubMed Central

2014-01-01

Background Access to timely and accurate diagnostic tests has a significant impact in the management of diseases of global concern such as malaria. While molecular diagnostics satisfy this need effectively in developed countries, barriers in technology, reagent storage, cost and expertise have hampered the introduction of these methods in developing countries. In this study a simple, lab-on-chip PCR diagnostic was created for malaria that overcomes these challenges. Methods The platform consists of a disposable plastic chip and a low-cost, portable, real-time PCR machine. The chip contains a desiccated hydrogel with reagents needed for Plasmodium specific PCR. Chips can be stored at room temperature and used on demand by rehydrating the gel with unprocessed blood, avoiding the need for sample preparation. These chips were run on a custom-built instrument containing a Peltier element for thermal cycling and a laser/camera setup for amplicon detection. Results This diagnostic was capable of detecting all Plasmodium species with a limit of detection for Plasmodium falciparum of 2 parasites/μL of blood. This exceeds the sensitivity of microscopy, the current standard for diagnosis in the field, by ten to fifty-fold. In a blind panel of 188 patient samples from a hyper-endemic region of malaria transmission in Uganda, the diagnostic had high sensitivity (97.4%) and specificity (93.8%) versus conventional real-time PCR. The test also distinguished the two most prevalent malaria species in mixed infections, P. falciparum and Plasmodium vivax. A second blind panel of 38 patient samples was tested on a streamlined instrument with LED-based excitation, achieving a sensitivity of 96.7% and a specificity of 100%. Conclusions These results describe the development of a lab-on-chip PCR diagnostic from initial concept to ready-for-manufacture design. This platform will be useful in front-line malaria diagnosis, elimination programmes, and clinical trials. Furthermore, test chips can be adapted to detect other pathogens for a differential diagnosis in the field. The flexibility, reliability, and robustness of this technology hold much promise for its use as a novel molecular diagnostic platform in developing countries. PMID:24885206

Multi-channel imaging cytometry with a single detector

NASA Astrophysics Data System (ADS)

Locknar, Sarah; Barton, John; Entwistle, Mark; Carver, Gary; Johnson, Robert

2018-02-01

Multi-channel microscopy and multi-channel flow cytometry generate high bit data streams. Multiple channels (both spectral and spatial) are important in diagnosing diseased tissue and identifying individual cells. Omega Optical has developed techniques for mapping multiple channels into the time domain for detection by a single high gain, high bandwidth detector. This approach is based on pulsed laser excitation and a serial array of optical fibers coated with spectral reflectors such that up to 15 wavelength bins are sequentially detected by a single-element detector within 2.5 μs. Our multichannel microscopy system uses firmware running on dedicated DSP and FPGA chips to synchronize the laser, scanning mirrors, and sampling clock. The signals are digitized by an NI board into 14 bits at 60MHz - allowing for 232 by 174 pixel fields in up to 15 channels with 10x over sampling. Our multi-channel imaging cytometry design adds channels for forward scattering and back scattering to the fluorescence spectral channels. All channels are detected within the 2.5 μs - which is compatible with fast cytometry. Going forward, we plan to digitize at 16 bits with an A-toD chip attached to a custom board. Processing these digital signals in custom firmware would allow an on-board graphics processing unit to display imaging flow cytometry data over configurable scanning line lengths. The scatter channels can be used to trigger data buffering when a cell is present in the beam. This approach enables a low cost mechanically robust imaging cytometer.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

NASA Astrophysics Data System (ADS)

Tao, Yang; Linghao, Zhu; Xi, Tan; Junyu, Wang; Lirong, Zheng; Hao, Min

2016-07-01

An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process. Project supported by the National Science & Technology Pillar Program of China (No. 2015BAK36B01).

Sensing and perception research for space telerobotics at JPL

NASA Technical Reports Server (NTRS)

Gennery, Donald B.; Litwin, Todd; Wilcox, Brian; Bon, Bruce

1987-01-01

PIFLEX is a pipelined-image processor that can perform elaborate computations whose exact nature is not fixed in the hardware, and that can handle multiple images. A wire-wrapped prototype PIFEX module has been produced and debugged, using a version of the convolver composed of three custom VLSI chips (plus the line buffers). A printed circuit layout is being designed for use with a single-chip convolver, leading to production of a PIFEX with about 120 modules. A high-level language for programming PIFEX has been designed, and a compiler will be written for it. The camera calibration software has been completed and tested. Two more terms in the camera model, for lens distortion, probably will be added later. The acquisition and tracking system has been designed and most of it has been coded in Pascal for the MicroVAX-II. The feature tracker, motion stereo module and stereo matcher have executed successfully. The model matcher is still under development, and coding has begun on the tracking initializer. The object tracker was running on a different computer from the VAX, and preliminary runs on real images have been performed there. Once all modules are working, optimization and integration will begin. Finally, when a sufficiently large PIFEX is available, appropriate parts of acquisition and tracking, including much of the feature tracker, will be programmed into PIFEX, thus increasing the speed and robustness of the system.

MEMS capacitive accelerometer-based middle ear microphone.

PubMed

Young, Darrin J; Zurcher, Mark A; Semaan, Maroun; Megerian, Cliff A; Ko, Wen H

2012-12-01

The design, implementation, and characterization of a microelectromechanical systems (MEMS) capacitive accelerometer-based middle ear microphone are presented in this paper. The microphone is intended for middle ear hearing aids as well as future fully implantable cochlear prosthesis. Human temporal bones acoustic response characterization results are used to derive the accelerometer design requirements. The prototype accelerometer is fabricated in a commercial silicon-on-insulator (SOI) MEMS process. The sensor occupies a sensing area of 1 mm × 1 mm with a chip area of 2 mm × 2.4 mm and is interfaced with a custom-designed low-noise electronic IC chip over a flexible substrate. The packaged sensor unit occupies an area of 2.5 mm × 6.2 mm with a weight of 25 mg. The sensor unit attached to umbo can detect a sound pressure level (SPL) of 60 dB at 500 Hz, 35 dB at 2 kHz, and 57 dB at 8 kHz. An improved sound detection limit of 34-dB SPL at 150 Hz and 24-dB SPL at 500 Hz can be expected by employing start-of-the-art MEMS fabrication technology, which results in an articulation index of approximately 0.76. Further micro/nanofabrication technology advancement is needed to enhance the microphone sensitivity for improved understanding of normal conversational speech.

Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

NASA Astrophysics Data System (ADS)

Gordon, Jared

Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

Compact, Robust Chips Integrate Optical Functions

NASA Technical Reports Server (NTRS)

2010-01-01

Located in Bozeman, Montana, AdvR Inc. has been an active partner in NASA's Small Business Innovation Research (SBIR) and Small Business Technology Transfer (STTR) programs. Langley Research Center engineers partnered with AdvR through the SBIR program to develop new, compact, lightweight electro-optic components for remote sensing systems. While the primary customer for this technology will be NASA, AdvR foresees additional uses for its NASA-derived circuit chip in the fields of academic and industrial research anywhere that compact, low-cost, stabilized single-frequency lasers are needed.

Adaptive Injection-locking Oscillator Array for RF Spectrum Analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leung, Daniel

2011-04-19

A highly parallel radio frequency receiver using an array of injection-locking oscillators for on-chip, rapid estimation of signal amplitudes and frequencies is considered. The oscillators are tuned to different natural frequencies, and variable gain amplifiers are used to provide negative feedback to adapt the locking band-width with the input signal to yield a combined measure of input signal amplitude and frequency detuning. To further this effort, an array of 16 two-stage differential ring oscillators and 16 Gilbert-cell mixers is designed for 40-400 MHz operation. The injection-locking oscillator array is assembled on a custom printed-circuit board. Control and calibration is achievedmore » by on-board microcontroller.« less

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

High-bandwidth detection of short DNA in nanopipettes.

PubMed

Fraccari, Raquel L; Carminati, Marco; Piantanida, Giacomo; Leontidou, Tina; Ferrari, Giorgio; Albrecht, Tim

2016-12-12

Glass or quartz nanopipettes have found increasing use as tools for studying the biophysical properties of DNA and proteins, and as sensor devices. The ease of fabrication, favourable wetting properties and low capacitance are some of the inherent advantages, for example compared to more conventional, silicon-based nanopore chips. Recently, we have demonstrated high-bandwidth detection of double-stranded (ds) DNA with microsecond time resolution in nanopipettes, using custom-designed electronics. The electronics design has now been refined to include more sophisticated control features, such as integrated bias reversal and other features. Here, we exploit these capabilities and probe the translocation of short dsDNA in the 100 bp range, in different electrolytes. Single-stranded (ss) DNA of similar length are in use as capture probes, so label-free detection of their ds counterparts could therefore be of relevance in disease diagnostics.

Meissner effect measurement of single indium particle using a customized on-chip nano-scale superconducting quantum interference device system

NASA Astrophysics Data System (ADS)

Wu, Long; Chen, Lei; Wang, Hao; Liu, Xiaoyu; Wang, Zhen

2017-04-01

As many emergent phenomena of superconductivity appear on a smaller scale and at lower dimension, commercial magnetic property measurement systems (MPMSs) no longer provide the sensitivity necessary to study the Meissner effect of small superconductors. The nano-scale superconducting quantum interference device (nano-SQUID) is considered one of the most sensitive magnetic sensors for the magnetic characterization of mesoscopic or microscopic samples. Here, we develop a customized on-chip nano-SQUID measurement system based on a pulsed current biasing method. The noise performance of our system is approximately 4.6 × 10-17 emu/Hz1/2, representing an improvement of 9 orders of magnitude compared with that of a commercial MPMS (~10-8 emu/Hz1/2). Furthermore, we demonstrate the measurement of the Meissner effect of a single indium (In) particle (of 47 μm in diameter) using our on-chip nano-SQUID system. The system enables the observation of the prompt superconducting transition of the Meissner effect of a single In particle, thereby providing more accurate characterization of the critical field Hc and temperature Tc. In addition, the retrapping field Hre as a function of temperature T of single In particle shows disparate behavior from that of a large ensemble.

A MEMS-based, wireless, biometric-like security system

NASA Astrophysics Data System (ADS)

Cross, Joshua D.; Schneiter, John L.; Leiby, Grant A.; McCarter, Steven; Smith, Jeremiah; Budka, Thomas P.

2010-04-01

We present a system for secure identification applications that is based upon biometric-like MEMS chips. The MEMS chips have unique frequency signatures resulting from fabrication process variations. The MEMS chips possess something analogous to a "voiceprint". The chips are vacuum encapsulated, rugged, and suitable for low-cost, highvolume mass production. Furthermore, the fabrication process is fully integrated with standard CMOS fabrication methods. One is able to operate the MEMS-based identification system similarly to a conventional RFID system: the reader (essentially a custom network analyzer) detects the power reflected across a frequency spectrum from a MEMS chip in its vicinity. We demonstrate prototype "tags" - MEMS chips placed on a credit card-like substrate - to show how the system could be used in standard identification or authentication applications. We have integrated power scavenging to provide DC bias for the MEMS chips through the use of a 915 MHz source in the reader and a RF-DC conversion circuit on the tag. The system enables a high level of protection against typical RFID hacking attacks. There is no need for signal encryption, so back-end infrastructure is minimal. We believe this system would make a viable low-cost, high-security system for a variety of identification and authentication applications.

Genome-wide Target Enrichment-aided Chip Design: a 66 K SNP Chip for Cashmere Goat.

PubMed

Qiao, Xian; Su, Rui; Wang, Yang; Wang, Ruijun; Yang, Ting; Li, Xiaokai; Chen, Wei; He, Shiyang; Jiang, Yu; Xu, Qiwu; Wan, Wenting; Zhang, Yaolei; Zhang, Wenguang; Chen, Jiang; Liu, Bin; Liu, Xin; Fan, Yixing; Chen, Duoyuan; Jiang, Huaizhi; Fang, Dongming; Liu, Zhihong; Wang, Xiaowen; Zhang, Yanjun; Mao, Danqing; Wang, Zhiying; Di, Ran; Zhao, Qianjun; Zhong, Tao; Yang, Huanming; Wang, Jian; Wang, Wen; Dong, Yang; Chen, Xiaoli; Xu, Xun; Li, Jinquan

2017-08-17

Compared with the commercially available single nucleotide polymorphism (SNP) chip based on the Bead Chip technology, the solution hybrid selection (SHS)-based target enrichment SNP chip is not only design-flexible, but also cost-effective for genotype sequencing. In this study, we propose to design an animal SNP chip using the SHS-based target enrichment strategy for the first time. As an update to the international collaboration on goat research, a 66 K SNP chip for cashmere goat was created from the whole-genome sequencing data of 73 individuals. Verification of this 66 K SNP chip with the whole-genome sequencing data of 436 cashmere goats showed that the SNP call rates was between 95.3% and 99.8%. The average sequencing depth for target SNPs were 40X. The capture regions were shown to be 200 bp that flank target SNPs. This chip was further tested in a genome-wide association analysis of cashmere fineness (fiber diameter). Several top hit loci were found marginally associated with signaling pathways involved in hair growth. These results demonstrate that the 66 K SNP chip is a useful tool in the genomic analyses of cashmere goats. The successful chip design shows that the SHS-based target enrichment strategy could be applied to SNP chip design in other species.

A joining of forces. The promise of community health information management systems (CHIMSs).

PubMed

Hendren, S

1993-11-01

Every time you buy a bag of Frito-Lay corn chips, information regarding your purchase becomes part of a customer database within hours. America's snack food "needs" are analyzed and decisions are made about filling the shelves of every corner convenience store in the nation with exactly the right product. This system has saved the company more than $20 million a year through increased efficiency. But when you buy a diagnostic test to identify a potentially life-threatening condition, results can remain unavailable for days. If we can bring computerized efficiencies to marketing corn chips, why aren't we doing it for healthcare? Imagine--managers of community health systems who know their customers' needs so precisely that they "fill the shelves" of local "convenience health stops" with exactly the right services to maximize the health of the customers. As a by-product, they save a few million dollars per year in costs. Managers of other industries use information technology to deliver the right product or service to customers at just the right time, to differentiate their services by adding value, to compete effectively on cost and/or quality. Many members of the healthcare industry, where only 2.6 percent of expenditures go to information systems (compared to 5 percent in manufacturing and 7 percent in banking) and where the basic unit of work--the patient record--is still a manual process, are years behind in their thinking about how information systems can make their business better.

VLSI design of a single chip reed-solomon encoder

DOE Office of Scientific and Technical Information (OSTI.GOV)

Truong, T.K.; Deutsch, L.J.; Reed, I.S.

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

The Zero-Degree Detector System

NASA Technical Reports Server (NTRS)

Adams, James H.; Christl, Mark J.; Howell, Leonard W.; Kouznetsov, Evgueni

2006-01-01

We will report on a detector system used for accelerator measurement of nuclear fragmentation cross sections. This system consists of two detector planes, each carrying a ring of 8 detectors. Each detector has 64 pads. These two detector planes are arranged facing each other so that the matching detector pads on each plane form a two element charged particle telescope. Each of these telescopes is capable of determining the elemental identity of nuclear fragments passing through it. The system is used to measure light fragment production in the presence of heavier fragments. We will present a detailed discussion of the 64-pad detector design, the substrate design. The front-end electronics used to read out the signals is based on a custom VLSI chip developed for the Advanced Thin Ionization Calorimeter experiment which has been flown successfully twice in Antarctica. Each of these chips has 16 channels and each channel consists of a charge-sensitive preamplifier followed by a shaping amplifier and a track-and-hold circuit. The track-and-hold circuits are connected via a multiplexer to an output line driver. This allows the held signals to be presented, one-by-one via a common data line to a analog-to-digital converter. Because the output line driver can be placed in a high input impedance state when not in use, it is possible to daisy-change many chips on the same common data line. The front-end electronics and data readout scheme will be discussed in detail. The Zero Degree Detector has been used in several accelerator experiments conducted at the NASA Space Radiation Laboratory and the Alternating Gradient Synchrotron at Brookhaven National Laboratory as well as at the HIMAC accelerator in Japan. We will show examples of data taken at these accelerator runs to demonstrate how the system works.

Leveraging pattern matching to solve SRAM verification challenges at advanced nodes

NASA Astrophysics Data System (ADS)

Kan, Huan; Huang, Lucas; Yang, Legender; Zou, Elaine; Wan, Qijian; Du, Chunshan; Hu, Xinyi; Liu, Zhengfang; Zhu, Yu; Zhang, Recoo; Huang, Elven; Muirhead, Jonathan

2018-03-01

Memory is a critical component in today's system-on-chip (SoC) designs. Static random-access memory (SRAM) blocks are assembled by combining intellectual property (IP) blocks that come from SRAM libraries developed and certified by the foundries for both functionality and a specific process node. Customers place these SRAM IP in their designs, adjusting as necessary to achieve DRC-clean results. However, any changes a customer makes to these SRAM IP during implementation, whether intentionally or in error, can impact yield and functionality. Physical verification of SRAM has always been a challenge, because these blocks usually contain smaller feature sizes and spacing constraints compared to traditional logic or other layout structures. At advanced nodes, critical dimension becomes smaller and smaller, until there is almost no opportunity to use optical proximity correction (OPC) and lithography to adjust the manufacturing process to mitigate the effects of any changes. The smaller process geometries, reduced supply voltages, increasing process variation, and manufacturing uncertainty mean accurate SRAM physical verification results are not only reaching new levels of difficulty, but also new levels of criticality for design success. In this paper, we explore the use of pattern matching to create an SRAM verification flow that provides both accurate, comprehensive coverage of the required checks and visual output to enable faster, more accurate error debugging. Our results indicate that pattern matching can enable foundries to improve SRAM manufacturing yield, while allowing designers to benefit from SRAM verification kits that can shorten the time to market.

The VLSI design of a single chip Reed-Solomon encoder

NASA Technical Reports Server (NTRS)

Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1982-01-01

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

Integrated Microfluidic Devices for Automated Microarray-Based Gene Expression and Genotyping Analysis

NASA Astrophysics Data System (ADS)

Liu, Robin H.; Lodes, Mike; Fuji, H. Sho; Danley, David; McShea, Andrew

Microarray assays typically involve multistage sample processing and fluidic handling, which are generally labor-intensive and time-consuming. Automation of these processes would improve robustness, reduce run-to-run and operator-to-operator variation, and reduce costs. In this chapter, a fully integrated and self-contained microfluidic biochip device that has been developed to automate the fluidic handling steps for microarray-based gene expression or genotyping analysis is presented. The device consists of a semiconductor-based CustomArray® chip with 12,000 features and a microfluidic cartridge. The CustomArray was manufactured using a semiconductor-based in situ synthesis technology. The micro-fluidic cartridge consists of microfluidic pumps, mixers, valves, fluid channels, and reagent storage chambers. Microarray hybridization and subsequent fluidic handling and reactions (including a number of washing and labeling steps) were performed in this fully automated and miniature device before fluorescent image scanning of the microarray chip. Electrochemical micropumps were integrated in the cartridge to provide pumping of liquid solutions. A micromixing technique based on gas bubbling generated by electrochemical micropumps was developed. Low-cost check valves were implemented in the cartridge to prevent cross-talk of the stored reagents. Gene expression study of the human leukemia cell line (K562) and genotyping detection and sequencing of influenza A subtypes have been demonstrated using this integrated biochip platform. For gene expression assays, the microfluidic CustomArray device detected sample RNAs with a concentration as low as 0.375 pM. Detection was quantitative over more than three orders of magnitude. Experiment also showed that chip-to-chip variability was low indicating that the integrated microfluidic devices eliminate manual fluidic handling steps that can be a significant source of variability in genomic analysis. The genotyping results showed that the device identified influenza A hemagglutinin and neuraminidase subtypes and sequenced portions of both genes, demonstrating the potential of integrated microfluidic and microarray technology for multiple virus detection. The device provides a cost-effective solution to eliminate labor-intensive and time-consuming fluidic handling steps and allows microarray-based DNA analysis in a rapid and automated fashion.

Process weakness assessment by profiling all incoming design components

NASA Astrophysics Data System (ADS)

Zhuang, Linda; Cai, MengFeng; Zhu, Annie; Zhang, Yifan; Sweis, Jason; Lai, Ya-Chieh

2017-03-01

Foundries normally receive a large number of designs from different customers every day. It is desired to automatically profile each incoming design to quantify certain metrics like 1) the number of polygons per GDS layers 2) what kind of electrical components the design contains 3) what the dimensions of each electrical component are 4) how frequently any size of components have been used and their physical locations. This paper will present a novel method of how to generate a complete profile of components for any particular design. The component checking flow need to be completed within hours so it will have very little impact on the tape-out time. A pre-layer checking method is also run to group commonly used layers for different electrical components and then employ different layout profiling flows. The foundry does this design chip analysis in order to find potentially weak devices due to their size or special size requirements for particular electrical components. The foundry can then take pre-emptive action to avoid yield loss or make an unnecessary mask for new incoming products before fab processing starts.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Design, Fabrication and Characterization of an In Silico Cell Physiology lab for Bio Sensing Applications

NASA Astrophysics Data System (ADS)

Haque, A. ul; Rokkam, M.; DeCarlo, A. R.; Wereley, S. T.; Wells, H. W.; McLamb, W. T.; Roux, S. J.; Irazoqui, P. P.; Porterfield, D. M.

2006-04-01

In this paper, we report the design, fabrication and characterization of an In Silico cell physiology biochip for measuring Ca2+ ion concentrations and currents around single cells. This device has been designed around specific science objectives of measuring real time multidimensional calcium flux patterns around sixteen Ceratopteris richardii fern spores in microgravity flight experiments and ground studies. The sixteen microfluidic cell holding pores are 150 by 150 µm each and have 4 Ag/AgCl electrodes leading into them. An SU-8 structural layer is used for insulation and packaging purposes. The In Silico cell physiology lab is wire bonded on to a custom PCB for easy interface with a state of the art data acquisition system. The electrodes are coated with a Ca2+ ion selective membrane based on ETH-5234 ionophore and operated against an Ag/AgCl reference electrode. Initial characterization results have shown Nernst slopes of 30mv/decade that were stable over a number of measurement cycles. While this work is focused on technology to enable basic research on the Ceratopteris richardii spores, we anticipate that this type of cell physiology lab-on-a-chip will be broadly applied in biomedical and pharmacological research by making minor modifications to the electrode material and the measurement technique. Future applications include detection of glucose, hormones such as plant auxin, as well as multiple analyte detection on the same chip.

Development and application of a 6.5 million feature Affymetrix Genechip® for massively parallel discovery of single position polymorphisms in lettuce (Lactuca spp.)

PubMed Central

2012-01-01

Background High-resolution genetic maps are needed in many crops to help characterize the genetic diversity that determines agriculturally important traits. Hybridization to microarrays to detect single feature polymorphisms is a powerful technique for marker discovery and genotyping because of its highly parallel nature. However, microarrays designed for gene expression analysis rarely provide sufficient gene coverage for optimal detection of nucleotide polymorphisms, which limits utility in species with low rates of polymorphism such as lettuce (Lactuca sativa). Results We developed a 6.5 million feature Affymetrix GeneChip® for efficient polymorphism discovery and genotyping, as well as for analysis of gene expression in lettuce. Probes on the microarray were designed from 26,809 unigenes from cultivated lettuce and an additional 8,819 unigenes from four related species (L. serriola, L. saligna, L. virosa and L. perennis). Where possible, probes were tiled with a 2 bp stagger, alternating on each DNA strand; providing an average of 187 probes covering approximately 600 bp for each of over 35,000 unigenes; resulting in up to 13 fold redundancy in coverage per nucleotide. We developed protocols for hybridization of genomic DNA to the GeneChip® and refined custom algorithms that utilized coverage from multiple, high quality probes to detect single position polymorphisms in 2 bp sliding windows across each unigene. This allowed us to detect greater than 18,000 polymorphisms between the parental lines of our core mapping population, as well as numerous polymorphisms between cultivated lettuce and wild species in the lettuce genepool. Using marker data from our diversity panel comprised of 52 accessions from the five species listed above, we were able to separate accessions by species using both phylogenetic and principal component analyses. Additionally, we estimated the diversity between different types of cultivated lettuce and distinguished morphological types. Conclusion By hybridizing genomic DNA to a custom oligonucleotide array designed for maximum gene coverage, we were able to identify polymorphisms using two approaches for pair-wise comparisons, as well as a highly parallel method that compared all 52 genotypes simultaneously. PMID:22583801

Development and application of a 6.5 million feature Affymetrix Genechip® for massively parallel discovery of single position polymorphisms in lettuce (Lactuca spp.).

PubMed

Stoffel, Kevin; van Leeuwen, Hans; Kozik, Alexander; Caldwell, David; Ashrafi, Hamid; Cui, Xinping; Tan, Xiaoping; Hill, Theresa; Reyes-Chin-Wo, Sebastian; Truco, Maria-Jose; Michelmore, Richard W; Van Deynze, Allen

2012-05-14

High-resolution genetic maps are needed in many crops to help characterize the genetic diversity that determines agriculturally important traits. Hybridization to microarrays to detect single feature polymorphisms is a powerful technique for marker discovery and genotyping because of its highly parallel nature. However, microarrays designed for gene expression analysis rarely provide sufficient gene coverage for optimal detection of nucleotide polymorphisms, which limits utility in species with low rates of polymorphism such as lettuce (Lactuca sativa). We developed a 6.5 million feature Affymetrix GeneChip® for efficient polymorphism discovery and genotyping, as well as for analysis of gene expression in lettuce. Probes on the microarray were designed from 26,809 unigenes from cultivated lettuce and an additional 8,819 unigenes from four related species (L. serriola, L. saligna, L. virosa and L. perennis). Where possible, probes were tiled with a 2 bp stagger, alternating on each DNA strand; providing an average of 187 probes covering approximately 600 bp for each of over 35,000 unigenes; resulting in up to 13 fold redundancy in coverage per nucleotide. We developed protocols for hybridization of genomic DNA to the GeneChip® and refined custom algorithms that utilized coverage from multiple, high quality probes to detect single position polymorphisms in 2 bp sliding windows across each unigene. This allowed us to detect greater than 18,000 polymorphisms between the parental lines of our core mapping population, as well as numerous polymorphisms between cultivated lettuce and wild species in the lettuce genepool. Using marker data from our diversity panel comprised of 52 accessions from the five species listed above, we were able to separate accessions by species using both phylogenetic and principal component analyses. Additionally, we estimated the diversity between different types of cultivated lettuce and distinguished morphological types. By hybridizing genomic DNA to a custom oligonucleotide array designed for maximum gene coverage, we were able to identify polymorphisms using two approaches for pair-wise comparisons, as well as a highly parallel method that compared all 52 genotypes simultaneously.

A CAM-based LZ data compression IC

NASA Technical Reports Server (NTRS)

Winters, K.; Bode, R.; Schneider, E.

1993-01-01

A custom CMOS processor is introduced that implements the Data Compression Lempel-Ziv (DCLZ) standard, a variation of the LZ2 Algorithm. This component presently achieves a sustained compression and decompression rate of 10 megabytes/second by employing an on-chip content-addressable memory for string table storage.

Application of LogitBoost Classifier for Traceability Using SNP Chip Data

PubMed Central

Kang, Hyunsung; Cho, Seoae; Kim, Heebal; Seo, Kang-Seok

2015-01-01

Consumer attention to food safety has increased rapidly due to animal-related diseases; therefore, it is important to identify their places of origin (POO) for safety purposes. However, only a few studies have addressed this issue and focused on machine learning-based approaches. In the present study, classification analyses were performed using a customized SNP chip for POO prediction. To accomplish this, 4,122 pigs originating from 104 farms were genotyped using the SNP chip. Several factors were considered to establish the best prediction model based on these data. We also assessed the applicability of the suggested model using a kinship coefficient-filtering approach. Our results showed that the LogitBoost-based prediction model outperformed other classifiers in terms of classification performance under most conditions. Specifically, a greater level of accuracy was observed when a higher kinship-based cutoff was employed. These results demonstrated the applicability of a machine learning-based approach using SNP chip data for practical traceability. PMID:26436917

Application of LogitBoost Classifier for Traceability Using SNP Chip Data.

PubMed

Kim, Kwondo; Seo, Minseok; Kang, Hyunsung; Cho, Seoae; Kim, Heebal; Seo, Kang-Seok

2015-01-01

Consumer attention to food safety has increased rapidly due to animal-related diseases; therefore, it is important to identify their places of origin (POO) for safety purposes. However, only a few studies have addressed this issue and focused on machine learning-based approaches. In the present study, classification analyses were performed using a customized SNP chip for POO prediction. To accomplish this, 4,122 pigs originating from 104 farms were genotyped using the SNP chip. Several factors were considered to establish the best prediction model based on these data. We also assessed the applicability of the suggested model using a kinship coefficient-filtering approach. Our results showed that the LogitBoost-based prediction model outperformed other classifiers in terms of classification performance under most conditions. Specifically, a greater level of accuracy was observed when a higher kinship-based cutoff was employed. These results demonstrated the applicability of a machine learning-based approach using SNP chip data for practical traceability.

Sensor Access to the Cellular Microenvironment Using the Sensing Cell Culture Flask.

PubMed

Kieninger, Jochen; Tamari, Yaara; Enderle, Barbara; Jobst, Gerhard; Sandvik, Joe A; Pettersen, Erik O; Urban, Gerald A

2018-04-26

The Sensing Cell Culture Flask (SCCF) is a cell culture monitoring system accessing the cellular microenvironment in 2D cell culture using electrochemical microsensors. The system is based on microfabricated sensor chips embedded in standard cell culture flasks. Ideally, the sensor chips could be equipped with any electrochemical sensor. Its transparency allows optical inspection of the cells during measurement. The surface of the sensor chip is in-plane with the flask surface allowing undisturbed cell growth on the sensor chip. A custom developed rack system allows easy usage of multiple flasks in parallel within an incubator. The presented data demonstrates the application of the SCCF with brain tumor (T98G) and breast cancer (T-47D) cells. Amperometric oxygen sensors were used to monitor cellular respiration with different incubation conditions. Cellular acidification was accessed with potentiometric pH sensors using electrodeposited iridium oxide films. The system itself provides the foundation for electrochemical monitoring systems in 3D cell culture.

First experimental feasibility study of VIPIC: a custom-made detector for X-ray speckle measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, Abdul K.; Siddons, D. Peter; Deptuch, Grzegorz

2016-02-10

The Vertically Integrated Photon Imaging Chip (VIPIC) was custom-designed for X-ray photon correlation spectroscopy, an application in which occupancy per pixel is low but high time resolution is needed. VIPIC operates in a sparsified streaming mode in which each detected photon is immediately read out as a time- and position-stamped event. This event stream can be fed directly to an autocorrelation engine or accumulated to form a conventional image. The detector only delivers non-zero data (sparsified readout), greatly reducing the communications overhead typical of conventional frame-oriented detectors such as charge-coupled devices or conventional hybrid pixel detectors. This feature allowscontinuousacquisition ofmore » data with timescales from microseconds to hours. In this work VIPIC has been used to measure X-ray photon correlation spectroscopy data on polystyrene latex nano-colliodal suspensions in glycerol and on colloidal suspensions of silica spheres in water. Relaxation times of the nano-colloids have been measured for different temperatures. These results demonstrate that VIPIC can operatecontinuouslyin the microsecond time frame, while at the same time probing longer timescales.« less

VIPIC: a custom-made detector for X-ray speckle measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, Abdul K.; Siddons, D. Peter; Deptuch, Grzegorz

2016-03-01

The Vertically Integrated Photon Imaging Chip (VIPIC) was custom-designed for X-ray photon correlation spectroscopy, an application in which occupancy per pixel is low but high time resolution is needed. VIPIC operates in a sparsified streaming mode in which each detected photon is immediately read out as a time- and position-stamped event. This event stream can be fed directly to an autocorrelation engine or accumulated to form a conventional image. The detector only delivers non-zero data (sparsified readout), greatly reducing the communications overhead typical of conventional frame-oriented detectors such as charge-coupled devices or conventional hybrid pixel detectors. This feature allows continuousmore » acquisition of data with timescales from microseconds to hours. In this work VIPIC has been used to measure X-ray photon correlation spectroscopy data on polystyrene latex ano-colliodal suspensions in glycerol and on colloidal suspensions of silica spheres in water. Relaxation times of the nano-colloids have been measured for different temperatures. These results demonstrate that VIPIC can operate continuously in the microsecond time frame, while at the same time probing longer timescales.« less

A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.

PubMed

Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

2011-04-01

Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.

First experimental feasibility study of VIPIC: a custom-made detector for X-ray speckle measurements

PubMed Central

Rumaiz, Abdul K.; Siddons, D. Peter; Deptuch, Grzegorz; Maj, Piotr; Kuczewski, Anthony J.; Carini, Gabriella A.; Narayanan, Suresh; Dufresne, Eric M.; Sandy, Alec; Bradford, Robert; Fluerasu, Andrei; Sutton, Mark

2016-01-01

The Vertically Integrated Photon Imaging Chip (VIPIC) was custom-designed for X-ray photon correlation spectroscopy, an application in which occupancy per pixel is low but high time resolution is needed. VIPIC operates in a sparsified streaming mode in which each detected photon is immediately read out as a time- and position-stamped event. This event stream can be fed directly to an autocorrelation engine or accumulated to form a conventional image. The detector only delivers non-zero data (sparsified readout), greatly reducing the communications overhead typical of conventional frame-oriented detectors such as charge-coupled devices or conventional hybrid pixel detectors. This feature allows continuous acquisition of data with timescales from microseconds to hours. In this work VIPIC has been used to measure X-ray photon correlation spectroscopy data on polystyrene latex nano-colliodal suspensions in glycerol and on colloidal suspensions of silica spheres in water. Relaxation times of the nano-colloids have been measured for different temperatures. These results demonstrate that VIPIC can operate continuously in the microsecond time frame, while at the same time probing longer timescales. PMID:26917126

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

A 1-channel 3-band wide dynamic range compression chip for vibration transducer of implantable hearing aids.

PubMed

Kim, Dongwook; Seong, Kiwoong; Kim, Myoungnam; Cho, Jinho; Lee, Jyunghyun

2014-01-01

In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level.

Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

PubMed Central

Hwang, Wen-Jyi; Cheng, Shih-Chang; Cheng, Chau-Jern

2011-01-01

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system. PMID:22163688

A compact perspiration meter system with capacitive humidity sensor for wearable health-care applications

NASA Astrophysics Data System (ADS)

Mitani, Yusuke; Miyaji, Kousuke; Kaneko, Satoshi; Uekura, Takaharu; Momose, Hideya; Johguchi, Koh

2018-04-01

This paper presents a compact wearable perspiration meter system using a 180-nm CMOS technology. With custom chip and board design, the proposed perspiration meter, which can measure a qualitative sweating rate, is integrated into 15 × 20 mm2. From the experimental results, the capacitances of the humidity sensors with analog-to-digital converter and band-gap reference circuits can operate accurately without hysteresis. In addition, a demonstration with simulated human skin is carried out to investigate the sensor’s performance under real environments. The proposed perspiration meter can output values equivalent to a conventional meter. As a result, it is verified that the proposed system can be used as a human sweat sensor for wearable application.

Low-latency situational awareness for UxV platforms

NASA Astrophysics Data System (ADS)

Berends, David C.

2012-06-01

Providing high quality, low latency video from unmanned vehicles through bandwidth-limited communications channels remains a formidable challenge for modern vision system designers. SRI has developed a number of enabling technologies to address this, including the use of SWaP-optimized Systems-on-a-Chip which provide Multispectral Fusion and Contrast Enhancement as well as H.264 video compression. Further, the use of salience-based image prefiltering prior to image compression greatly reduces output video bandwidth by selectively blurring non-important scene regions. Combined with our customization of the VLC open source video viewer for low latency video decoding, SRI developed a prototype high performance, high quality vision system for UxV application in support of very demanding system latency requirements and user CONOPS.

efficient association study design via power-optimized tag SNP selection

PubMed Central

HAN, BUHM; KANG, HYUN MIN; SEO, MYEONG SEONG; ZAITLEN, NOAH; ESKIN, ELEAZAR

2008-01-01

Discovering statistical correlation between causal genetic variation and clinical traits through association studies is an important method for identifying the genetic basis of human diseases. Since fully resequencing a cohort is prohibitively costly, genetic association studies take advantage of local correlation structure (or linkage disequilibrium) between single nucleotide polymorphisms (SNPs) by selecting a subset of SNPs to be genotyped (tag SNPs). While many current association studies are performed using commercially available high-throughput genotyping products that define a set of tag SNPs, choosing tag SNPs remains an important problem for both custom follow-up studies as well as designing the high-throughput genotyping products themselves. The most widely used tag SNP selection method optimizes over the correlation between SNPs (r2). However, tag SNPs chosen based on an r2 criterion do not necessarily maximize the statistical power of an association study. We propose a study design framework that chooses SNPs to maximize power and efficiently measures the power through empirical simulation. Empirical results based on the HapMap data show that our method gains considerable power over a widely used r2-based method, or equivalently reduces the number of tag SNPs required to attain the desired power of a study. Our power-optimized 100k whole genome tag set provides equivalent power to the Affymetrix 500k chip for the CEU population. For the design of custom follow-up studies, our method provides up to twice the power increase using the same number of tag SNPs as r2-based methods. Our method is publicly available via web server at http://design.cs.ucla.edu. PMID:18702637

The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

NASA Astrophysics Data System (ADS)

Choi, Edward

Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the applications above is evaluated. The viability of this approach is not limited to the examples listed in this work, and innovative new methodologies beyond those included here may be developed in the future for other systems which would benefit from the versatility of chip-scale platforms.

77 FR 26789 - Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-07

... patents. 73 FR 75131. The principal respondent was NVIDIA Corporation of Santa Clara, California (``NVIDIA''). Joining NVIDIA as respondents were approximately twenty of NVIDIA's customers. The Commission found a... accused products in the United States: NVIDIA; Hewlett-Packard Co. of Palo Alto, California; ASUS Computer...

Manufacturing and testing VLPC hybrids

NASA Astrophysics Data System (ADS)

Adkins, L. R.; Ingram, C. M.; Anderson, E. J.

1998-11-01

To insure that the manufacture of VLPC devices is a reliable, cost-effective technology, hybrid assembly procedures and testing methods suitable for large scale production have been developed. This technology has been developed under a contract from Fermilab as part of the D-Zero upgrade program. Each assembled hybrid consists of a VLPC chip mounted on an AlN substrate. The VLPC chip is provided with bonding pads (one connected to each pixel) which are wire bonded to gold traces on the substrate. The VLPC/AlN hybrids are mated in a vacuum sealer using solder preforms and a specially designed carbon boat. After mating, the VLPC pads are bonded to the substrate with an automatic wire bonder. Using this equipment we have achieved a thickness tolerance of ±0.0007 inches and a production rate of 100 parts per hour. After assembly the VLPCs are tested for optical response at an operating temperature of 7K. The parts are tested in a custom designed continuous-flow dewar with a capacity 15 hybrids, and one Lake Shore DT470-SD-11 calibrated temperature sensor mounted to an AlN substrate. Our facility includes five of these dewars with an ultimate test capacity of 75 parts per day. During the course of the Dzero program we have assembled more than 4,000 VLPC hybrids and have tested more than 2,500 with a high yield.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Design, fabrication, and packaging of an integrated, wirelessly-powered optrode array for optogenetics application

PubMed Central

Kwon, Ki Yong; Lee, Hyung-Min; Ghovanloo, Maysam; Weber, Arthur; Li, Wen

2015-01-01

The recent development of optogenetics has created an increased demand for advancing engineering tools for optical modulation of neural circuitry. This paper details the design, fabrication, integration, and packaging procedures of a wirelessly-powered, light emitting diode (LED) coupled optrode neural interface for optogenetic studies. The LED-coupled optrode array employs microscale LED (μLED) chips and polymer-based microwaveguides to deliver light into multi-level cortical networks, coupled with microelectrodes to record spontaneous changes in neural activity. An integrated, implantable, switched-capacitor based stimulator (SCS) system provides high instantaneous power to the μLEDs through an inductive link to emit sufficient light and evoke neural activities. The presented system is mechanically flexible, biocompatible, miniaturized, and lightweight, suitable for chronic implantation in small freely behaving animals. The design of this system is scalable and its manufacturing is cost effective through batch fabrication using microelectromechanical systems (MEMS) technology. It can be adopted by other groups and customized for specific needs of individual experiments. PMID:25999823

A Multipurpose CMOS Platform for Nanosensing

PubMed Central

Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L.; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

2016-01-01

This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μm × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus. PMID:27916911

A Multipurpose CMOS Platform for Nanosensing.

PubMed

Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

2016-11-30

This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

Test beam demonstration of silicon microstrip modules with transverse momentum discrimination for the future CMS tracking detector

NASA Astrophysics Data System (ADS)

Adam, W.; Bergauer, T.; Brondolin, E.; Dragicevic, M.; Friedl, M.; Frühwirth, R.; Hoch, M.; Hrubec, J.; König, A.; Steininger, H.; Treberspurg, W.; Waltenberger, W.; Alderweireldt, S.; Beaumont, W.; Janssen, X.; Lauwers, J.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Beghin, D.; Brun, H.; Clerbaux, B.; De Lentdecker, G.; Delannoy, H.; Fasanella, G.; Favart, L.; Goldouzian, R.; Grebenyuk, A.; Karapostoli, G.; Lenzi, T.; Léonard, A.; Luetic, J.; Maerschalk, T.; Marinov, A.; Postiau, N.; Randle-Conde, A.; Seva, T.; Vanlaer, P.; Vannerom, D.; Yonamine, R.; Wang, Q.; Yang, Y.; Zenoni, F.; Zhang, F.; Abu Zeid, S.; Blekman, F.; De Bruyn, I.; De Clercq, J.; D'Hondt, J.; Deroover, K.; Lowette, S.; Moortgat, S.; Moreels, L.; Python, Q.; Skovpen, K.; Van Mulders, P.; Van Parijs, I.; Bakhshiansohi, H.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Delaere, C.; Delcourt, M.; De Visscher, S.; Francois, B.; Giammanco, A.; Jafari, A.; Cabrera Jamoulle, J.; De Favereau De Jeneret, J.; Komm, M.; Krintiras, G.; Lemaitre, V.; Magitteri, A.; Mertens, A.; Michotte, D.; Musich, M.; Piotrzkowski, K.; Quertenmont, L.; Szilasi, N.; Vidal Marono, M.; Wertz, S.; Beliy, N.; Caebergs, T.; Daubie, E.; Hammad, G. H.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Eerola, P.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Vander Donckt, M.; Viret, S.; Agram, J.-L.; Andrea, J.; Bloch, D.; Bonnin, C.; Brom, J.-M.; Chabert, E.; Chanon, N.; Charles, L.; Conte, E.; Fontaine, J.-Ch.; Gross, L.; Hosselet, J.; Jansova, M.; Tromson, D.; Autermann, C.; Feld, L.; Karpinski, W.; Kiesel, K. M.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Pierschel, G.; Preuten, M.; Rauch, M.; Schael, S.; Schomakers, C.; Schulz, J.; Schwering, G.; Wlochal, M.; Zhukov, V.; Pistone, C.; Fluegge, G.; Kuensken, A.; Pooth, O.; Stahl, A.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garay Garcia, J.; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schuetze, P.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Klanner, R.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; De Boer, W.; Butz, E.; Casele, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmeyer, A.; Kudella, S.; Muller, Th.; Printz, M.; Simonis, H. J.; Steck, P.; Weber, M.; Weiler, Th.; Anagnostou, G.; Asenov, P.; Assiouras, P.; Daskalakis, G.; Kyriakis, A.; Loukas, D.; Paspalaki, L.; Siklér, F.; Veszprémi, V.; Bhardwaj, A.; Dalal, R.; Jain, G.; Ranjan, K.; Dutta, S.; Chowdhury, S. Roy; Bakhshiansohl, H.; Behnamian, H.; Khakzad, M.; Naseri, M.; Cariola, P.; Creanza, D.; De Palma, M.; De Robertis, G.; Fiore, L.; Franco, M.; Loddo, F.; Sala, G.; Silvestris, L.; Maggi, G.; My, S.; Selvaggi, G.; Albergo, S.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Saizu, M. A.; Tricomi, A.; Tuve, C.; Barbagli, G.; Brianzi, M.; Ciaranfi, R.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Latino, G.; Lenzi, P.; Meschini, M.; Paoletti, S.; Russo, L.; Scarlini, E.; Sguazzoni, G.; Strom, D.; Viliani, L.; Ferro, F.; Lo Vetere, M.; Robutti, E.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R. A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Nodari, B.; Riceputi, E.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Arezzini, S.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ciampa, A.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Magazzu, G.; Martini, L.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Raffaelli, F.; Rizzi, A.; Savoy-Navarro, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Bellan, R.; Costa, M.; Covarelli, R.; Da Rocha Rolo, M.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Mazza, G.; Migliore, E.; Monteil, E.; Pacher, L.; Ravera, F.; Solano, A.; Fernandez, M.; Gomez, G.; Jaramillo Echeverria, R.; Moya, D.; Gonzalez Sanchez, F. J.; Vila, I.; Virto, A. L.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bianchi, G.; Blanchot, G.; Bonnaud, J.; Caratelli, A.; Ceresa, D.; Christiansen, J.; Cichy, K.; Daguin, J.; D'Auria, A.; Detraz, S.; Deyrail, D.; Dondelewski, O.; Faccio, F.; Frank, N.; Gadek, T.; Gill, K.; Honma, A.; Hugo, G.; Jara Casas, L. M.; Kaplon, J.; Kornmayer, A.; Kottelat, L.; Kovacs, M.; Krammer, M.; Lenoir, P.; Mannelli, M.; Marchioro, A.; Marconi, S.; Mersi, S.; Martina, S.; Michelis, S.; Moll, M.; Onnela, A.; Orfanelli, S.; Pavis, S.; Peisert, A.; Pernot, J.-F.; Petagna, P.; Petrucciani, G.; Postema, H.; Rose, P.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Vichoudis, P.; Verlaat, B.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.-C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Chen, P.-H.; Dietz, C.; Grundler, U.; Hou, W.-S.; Lu, R.-S.; Moya, M.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Jacob, J.; Seif El Nasr-Storey, S.; Cole, J.; Hoad, C.; Hobson, P.; Morton, A.; Reid, I. D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Fulcher, J.; Hall, G.; James, T.; Magnan, A.-M.; Pesaresi, M.; Raymond, D. M.; Uchida, K.; Braga, D.; Coughlan, J. A.; Harder, K.; Jones, L.; Ilic, J.; Murray, P.; Prydderch, M.; Tomalin, I. R.; Garabedian, A.; Heintz, U.; Narain, M.; Nelson, J.; Sagir, S.; Speer, T.; Swanson, J.; Tersegno, D.; Watson-Daniels, J.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B. R.; Gerosa, R.; Sharma, V.; Vartak, A.; Yagil, A.; Zevi Della Porta, G.; Dutta, V.; Gouskos, L.; Incandela, J.; Kyre, S.; Mullin, S.; Qu, H.; White, D.; Dominguez, A.; Bartek, R.; Cumalat, J. P.; Ford, W. T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S. R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J. N.; Cheung, H. W. K.; Chramowicz, J.; Christian, D.; Cooper, W. E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Lei, C. M.; Lipton, R.; Lopes De Sá, R.; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D. R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Evdokimov, O.; Gerber, C. E.; Hofman, D. J.; Makauda, S.; Mills, C.; Sandoval Gonzalez, I. D.; Alimena, J.; Antonelli, L. J.; Francis, B.; Hart, A.; Hill, C. S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D. H.; Shi, X.; Tan, P.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Acosta, J. G.; Cremaldi, L. M.; Oliveros, S.; Perera, L.; Summers, D.; Bloom, K.; Claes, D. R.; Fangmeier, C.; Gonzalez Suarez, R.; Monroy, J.; Siado, J.; Hahn, K.; Sevova, S.; Sung, K.; Trovato, M.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Ramirez Vargas, J. E.; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K. M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; Betchart, B.; Covarelli, R.; Demina, R.; Hindrichs, O.; Petrillo, G.; Eusebi, R.; Patel, R.; Perloff, A.; Ulmer, K. A.; Delannoy, A. G.; D'Angelo, P.; Johns, W.

2018-03-01

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2026 onwards. It includes an outer tracker based on dedicated modules that will reconstruct short track segments, called stubs, using spatially coincident clusters in two closely spaced silicon sensor layers. These modules allow the rejection of low transverse momentum track hits and reduce the data volume before transmission to the first level trigger. The inclusion of tracking information in the trigger decision is essential to limit the first level trigger accept rate. A customized front-end readout chip, the CMS Binary Chip (CBC), containing stub finding logic has been designed for this purpose. A prototype module, equipped with the CBC chip, has been constructed and operated for the first time in a 4 GeemVem/emc positron beam at DESY. The behaviour of the stub finding was studied for different angles of beam incidence on a module, which allows an estimate of the sensitivity to transverse momentum within the future CMS detector. A sharp transverse momentum threshold around 2 emVem/emc was demonstrated, which meets the requirement to reject a large fraction of low momentum tracks present in the LHC environment on-detector. This is the first realistic demonstration of a silicon tracking module that is able to select data, based on the particle's transverse momentum, for use in a first level trigger at the LHC . The results from this test are described here.

Integrated Smartphone-App-Chip System for On-Site Parts-Per-Billion-Level Colorimetric Quantitation of Aflatoxins.

PubMed

Li, Xiaochun; Yang, Fan; Wong, Jessica X H; Yu, Hua-Zhong

2017-09-05

We demonstrate herein an integrated, smartphone-app-chip (SPAC) system for on-site quantitation of food toxins, as demonstrated with aflatoxin B1 (AFB1), at parts-per-billion (ppb) level in food products. The detection is based on an indirect competitive immunoassay fabricated on a transparent plastic chip with the assistance of a microfluidic channel plate. A 3D-printed optical accessory attached to a smartphone is adapted to align the assay chip and to provide uniform illumination for imaging, with which high-quality images of the assay chip are captured by the smartphone camera and directly processed using a custom-developed Android app. The performance of this smartphone-based detection system was tested using both spiked and moldy corn samples; consistent results with conventional enzyme-linked immunosorbent assay (ELISA) kits were obtained. The achieved detection limit (3 ± 1 ppb, equivalent to μg/kg) and dynamic response range (0.5-250 ppb) meet the requested testing standards set by authorities in China and North America. We envision that the integrated SPAC system promises to be a simple and accurate method of food toxin quantitation, bringing much benefit for rapid on-site screening.

The role of simulation in the design of a neural network chip

NASA Technical Reports Server (NTRS)

Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

1993-01-01

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

A 0.7-V 17.4- μ W 3-lead wireless ECG SoC.

PubMed

Khayatzadeh, Mahmood; Zhang, Xiaoyang; Tan, Jun; Liew, Wen-Sin; Lian, Yong

2013-10-01

This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC) for wireless body sensor network applications. The SoC includes a two-channel ECG front-end with a driven-right-leg circuit, an 8-bit SAR ADC, a custom-designed 16-bit microcontroller, two banks of 16 kb SRAM, and a MICS band transceiver. The microcontroller and SRAM blocks are able to operate at sub-/near-threshold regime for the best energy consumption. The proposed SoC has been implemented in a standard 0.13- μ m CMOS process. Measurement results show the microcontroller consumes only 2.62 pJ per instruction at 0.35 V . Both microcontroller and memory blocks are functional down to 0.25 V. The entire SoC is capable of working at single 0.7-V supply. At the best case, it consumes 17.4 μ W in heart rate detection mode and 74.8 μW in raw data acquisition mode under sampling rate of 500 Hz. This makes it one of the best ECG SoCs among state-of-the-art biomedical chips.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories.

PubMed

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain Frank; Nesbitt, Leslie; Riben, Michael

2018-01-01

The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named "p-Chip." The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes - embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories

PubMed Central

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain “Frank”; Nesbitt, Leslie; Riben, Michael

2018-01-01

Background: The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named “p-Chip.” The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. Methods: The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes – embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Results: Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. Conclusions: The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory. PMID:29692946

Embeddable Reconfigurable Neuroprocessors

NASA Technical Reports Server (NTRS)

Daud, Taher; Duong, Tuan; Langenbacher, Harry; Tran, Mua; Thakoor, Anil

1993-01-01

Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.

Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

PubMed

Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

2013-06-21

We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

Forward-Looking Intracardiac Ultrasound Imaging Using a 1-D CMUT Array Integrated With Custom Front-End Electronics

PubMed Central

Nikoozadeh, Amin; Wygant, Ira O.; Lin, Der-Song; Oralkan, Ömer; Ergun, A. Sanlı; Stephens, Douglas N.; Thomenius, Kai E.; Dentinger, Aaron M.; Wildes, Douglas; Akopyan, Gina; Shivkumar, Kalyanam; Mahajan, Aman; Sahn, David J.; Khuri-Yakub, Butrus T.

2009-01-01

Minimally invasive catheter-based electrophysiological (EP) interventions are becoming a standard procedure in diagnosis and treatment of cardiac arrhythmias. As a result of technological advances that enable small feature sizes and a high level of integration, nonfluoroscopic intracardiac echocardiography (ICE) imaging catheters are attracting increasing attention. ICE catheters improve EP procedural guidance while reducing the undesirable use of fluoroscopy, which is currently the common catheter guidance method. Phased-array ICE catheters have been in use for several years now, although only for side-looking imaging. We are developing a forward-looking ICE catheter for improved visualization. In this effort, we fabricate a 24-element, fine-pitch 1-D array of capacitive micromachined ultrasonic transducers (CMUT), with a total footprint of 1.73 mm × 1.27 mm. We also design a custom integrated circuit (IC) composed of 24 identical blocks of transmit/receive circuitry, measuring 2.1 mm × 2.1 mm. The transmit circuitry is capable of delivering 25-V unipolar pulses, and the receive circuitry includes a transimpedance preamplifier followed by an output buffer. The CMUT array and the custom IC are designed to be mounted at the tip of a 10-Fr catheter for high-frame-rate forward-looking intracardiac imaging. Through-wafer vias incorporated in the CMUT array provide access to individual array elements from the back side of the array. We successfully flip-chip bond a CMUT array to the custom IC with 100% yield. We coat the device with a layer of polydimethylsiloxane (PDMS) to electrically isolate the device for imaging in water and tissue. The pulse-echo in water from a total plane reflector has a center frequency of 9.2 MHz with a 96% fractional bandwidth. Finally, we demonstrate the imaging capability of the integrated device on commercial phantoms and on a beating ex vivo rabbit heart (Langendorff model) using a commercial ultrasound imaging system. PMID:19126489

pH-triggered conduction of amine-functionalized single ZnO wire integrated on a customized nanogap electronic platform

PubMed Central

2014-01-01

The electrical conductance response of single ZnO microwire functionalized with amine-groups was tested upon an acid pH variation of a solution environment after integration on a customized gold electrode array chip. ZnO microwires were easily synthesized by hydrothermal route and chemically functionalized with aminopropyl groups. Single wires were deposited from the solution and then oriented through dielectrophoresis across eight nanogap gold electrodes on a platform single chip. Therefore, eight functionalized ZnO microwire-gold junctions were formed at the same time, and being integrated on an ad hoc electronic platform, they were ready for testing without any further treatment. Experimental and simulation studies confirmed the high pH-responsive behavior of the amine-modified ZnO-gold junctions, obtaining in a simple and reproducible way a ready-to-use device for pH detection in the acidic range. We also compared this performance to bare ZnO wires on the same electronic platform, showing the superiority in pH response of the amine-functionalized material. PMID:24484615

A modular microfluidic architecture for integrated biochemical analysis.

PubMed

Shaikh, Kashan A; Ryu, Kee Suk; Goluch, Edgar D; Nam, Jwa-Min; Liu, Juewen; Thaxton, C Shad; Chiesl, Thomas N; Barron, Annelise E; Lu, Yi; Mirkin, Chad A; Liu, Chang

2005-07-12

Microfluidic laboratory-on-a-chip (LOC) systems based on a modular architecture are presented. The architecture is conceptualized on two levels: a single-chip level and a multiple-chip module (MCM) system level. At the individual chip level, a multilayer approach segregates components belonging to two fundamental categories: passive fluidic components (channels and reaction chambers) and active electromechanical control structures (sensors and actuators). This distinction is explicitly made to simplify the development process and minimize cost. Components belonging to these two categories are built separately on different physical layers and can communicate fluidically via cross-layer interconnects. The chip that hosts the electromechanical control structures is called the microfluidic breadboard (FBB). A single LOC module is constructed by attaching a chip comprised of a custom arrangement of fluid routing channels and reactors (passive chip) to the FBB. Many different LOC functions can be achieved by using different passive chips on an FBB with a standard resource configuration. Multiple modules can be interconnected to form a larger LOC system (MCM level). We demonstrated the utility of this architecture by developing systems for two separate biochemical applications: one for detection of protein markers of cancer and another for detection of metal ions. In the first case, free prostate-specific antigen was detected at 500 aM concentration by using a nanoparticle-based bio-bar-code protocol on a parallel MCM system. In the second case, we used a DNAzyme-based biosensor to identify the presence of Pb(2+) (lead) at a sensitivity of 500 nM in <1 nl of solution.

A 1-1/2-level on-chip-decoding bubble memory chip design

NASA Technical Reports Server (NTRS)

Chen, T. T.

1975-01-01

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Advanced Initiation Systems Manufacturing Level 2 Milestone Completion Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chow, R; Schmidt, M

2009-10-01

Milestone Description - Advanced Initiation Systems Detonator Design and Prototype. Milestone Grading Criteria - Design new generation chip slapper detonator and manufacture a prototype using advanced manufacturing processes, such as all-dry chip metallization and solvent-less flyer coatings. The advanced processes have been developed for manufacturing detonators with high material compatibility and reliability to support future LEPs, e.g. the B61, and new weapons systems. Perform velocimetry measurements to determine slapper velocity as a function of flight distance. A prototype detonator assembly and stripline was designed for low-energy chip slappers. Pictures of the prototype detonator and stripline are shown. All-dry manufacturing processesmore » were used to address compatibility issues. KCP metallized the chips in a physical vapor deposition system through precision-aligned shadow masks. LLNL deposited a solvent-less polyimide flyer with a processes called SLIP, which stands for solvent-less vapor deposition followed by in-situ polymerization. LANL manufactured the high-surface-area (HSA) high explosive (HE) pellets. Test fires of two chip slapper designs, radius and bowtie, were performed at LLNL in the High Explosives Application Facility (HEAF). Test fires with HE were conducted to establish the threshold firing voltages. pictures of the chip slappers before and after test fires are shown. Velocimetry tests were then performed to obtain slapper velocities at or above the threshold firing voltages. Figure 5 shows the slapper velocity as a function of distance and time at the threshold voltage, for both radius and bowtie bridge designs. Both designs were successful at initiating the HE at low energy levels. Summary of Accomplishments are: (1) All-dry process for chip manufacture developed; (2) Solventless process for slapper materials developed; (3) High-surface area explosive pellets developed; (4) High performance chip slappers developed; (5) Low-energy chip slapper detonator designs; and (6) Low-voltage threshold chip slapper detonator demonstrated.« less

Design methodology and results evaluation of a heating functionality in modular lab-on-chip systems

NASA Astrophysics Data System (ADS)

Streit, Petra; Nestler, Joerg; Shaporin, Alexey; Graunitz, Jenny; Otto, Thomas

2018-06-01

Lab-on-a-chip (LoC) systems offer the opportunity of fast and customized biological analyses executed at the ‘point-of-need’ without expensive lab equipment. Some biological processes need a temperature treatment. Therefore, it is important to ensure a defined and stable temperature distribution in the biosensor area. An integrated heating functionality is realized with discrete resistive heating elements including temperature measurement. The focus of this contribution is a design methodology and evaluation technique of the temperature distribution in the biosensor area with regard to the thermal-electrical behaviour of the heat sources. Furthermore, a sophisticated control of the biosensor temperature is proposed. A finite element (FE) model with one and more integrated heat sources in a polymer-based LoC system is used to investigate the impact of the number and arrangement of heating elements on the temperature distribution around the heating elements and in the biosensor area. Based on this model, various LOC systems are designed and fabricated. Electrical characterization of the heat sources and independent temperature measurements with infrared technique are performed to verify the model parameters and prove the simulation approach. The FE model and the proposed methodology is the foundation for optimization and evaluation of new designs with regard to temperature requirements of the biosensor. Furthermore, a linear dependency of the heater temperature on the electric current is demonstrated in the targeted temperature range of 20 °C to 70 °C enabling the usage of the heating functionality for biological reactions requiring a steady-state temperature up to 70 °C. The correlation between heater and biosensor area temperature is derived for a direct control through the heating current.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Becker, Julian; Tate, Mark W.; Shanks, Katherine S.

Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame,more » in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.« less

Microfluidic chip for peptide analysis with an integrated HPLC column, sample enrichment column, and nanoelectrospray tip.

PubMed

Yin, Hongfeng; Killeen, Kevin; Brennen, Reid; Sobek, Dan; Werlich, Mark; van de Goor, Tom

2005-01-15

Current nano-LC/MS systems require the use of an enrichment column, a separation column, a nanospray tip, and the fittings needed to connect these parts together. In this paper, we present a microfabricated approach to nano-LC, which integrates these components on a single LC chip, eliminating the need for conventional LC connections. The chip was fabricated by laminating polyimide films with laser-ablated channels, ports, and frit structures. The enrichment and separation columns were packed using conventional reversed-phase chromatography particles. A face-seal rotary valve provided a means for switching between sample loading and separation configurations with minimum dead and delay volumes while allowing high-pressure operation. The LC chip and valve assembly were mounted within a custom electrospray source on an ion-trap mass spectrometer. The overall system performance was demonstrated through reversed-phase gradient separations of tryptic protein digests at flow rates between 100 and 400 nL/min. Microfluidic integration of the nano-LC components enabled separations with subfemtomole detection sensitivity, minimal carryover, and robust and stable electrospray throughout the LC solvent gradient.

Property-driven functional verification technique for high-speed vision system-on-chip processor

NASA Astrophysics Data System (ADS)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

A phase-based stereo vision system-on-a-chip.

PubMed

Díaz, Javier; Ros, Eduardo; Sabatini, Silvio P; Solari, Fabio; Mota, Sonia

2007-02-01

A simple and fast technique for depth estimation based on phase measurement has been adopted for the implementation of a real-time stereo system with sub-pixel resolution on an FPGA device. The technique avoids the attendant problem of phase warping. The designed system takes full advantage of the inherent processing parallelism and segmentation capabilities of FPGA devices to achieve a computation speed of 65megapixels/s, which can be arranged with a customized frame-grabber module to process 211frames/s at a size of 640x480 pixels. The processing speed achieved is higher than conventional camera frame rates, thus allowing the system to extract multiple estimations and be used as a platform to evaluate integration schemes of a population of neurons without increasing hardware resource demands.

On testing VLSI chips for the big Viterbi decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.

1989-01-01

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

AutoMOPS- B2B and B2C in mask making: Mask manufacturing performance and customer satisfaction improvement through better information flow management using generic models and standardized languages

NASA Astrophysics Data System (ADS)

Filies, Olaf; de Ridder, Luc; Rodriguez, Ben; Kujiken, Aart

2002-03-01

Semiconductor manufacturing has become a global business, in which companies of different size unite in virtual enterprises to meet new opportunities. Therefore Mask manufacturing is a key business, but mask ordering is a complex process and is always critical regarding design to market time, even though mask complexity and customer base are increasing using a wide variety of different mask order forms which are frequently faulty and very seldom complete. This is effectively blocking agile manufacturing and can tie wafer fabs to a single mask The goal of the project is elimination of the order verification through paperless, electronically linked information sharing/exchange between chip design, mask production and production stages, which will allow automation of the mask preparation. To cover these new techniques and their specifications as well as the common ones with automated tools a special generic Meta-model will be generated, based on the current standards for mask specifications, including the requirements from the involved partners (Alcatel Microelectronics, Altis, Compugraphics, Infineon, Nimble, Sigma-C), the project works out a pre-normative standard. The paper presents the current status of work. This work is partly funded by the Commission of the European Union under the Fifth Framework project IST-1999-10332 AutoMOPS.

Compact multispectral photodiode arrays using micropatterned dichroic filters

NASA Astrophysics Data System (ADS)

Chandler, Eric V.; Fish, David E.

2014-05-01

The next generation of multispectral instruments requires significant improvements in both spectral band customization and portability to support the widespread deployment of application-specific optical sensors. The benefits of spectroscopy are well established for numerous applications including biomedical instrumentation, industrial sorting and sensing, chemical detection, and environmental monitoring. In this paper, spectroscopic (and by extension hyperspectral) and multispectral measurements are considered. The technology, tradeoffs, and application fits of each are evaluated. In the majority of applications, monitoring 4-8 targeted spectral bands of optimized wavelength and bandwidth provides the necessary spectral contrast and correlation. An innovative approach integrates precision spectral filters at the photodetector level to enable smaller sensors, simplify optical designs, and reduce device integration costs. This method supports user-defined spectral bands to create application-specific sensors in a small footprint with scalable cost efficiencies. A range of design configurations, filter options and combinations are presented together with typical applications ranging from basic multi-band detection to stringent multi-channel fluorescence measurement. An example implementation packages 8 narrowband silicon photodiodes into a 9x9mm ceramic LCC (leadless chip carrier) footprint. This package is designed for multispectral applications ranging from portable color monitors to purpose- built OEM industrial and scientific instruments. Use of an eight-channel multispectral photodiode array typically eliminates 10-20 components from a device bill-of-materials (BOM), streamlining the optical path and shrinking the footprint by 50% or more. A stepwise design approach for multispectral sensors is discussed - including spectral band definition, optical design tradeoffs and constraints, and device integration from prototype through scalable volume production. Additional customization options are explored for application-specific OEM sensors integrated into portable devices using multispectral photodiode arrays.

Real-time PCR machine system modeling and a systematic approach for the robust design of a real-time PCR-on-a-chip system.

PubMed

Lee, Da-Sheng

2010-01-01

Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design.

Architectures for Cognitive Systems

DTIC Science & Technology

2010-02-01

highly modular many- node chip was designed which addressed power efficiency to the maximum extent possible. Each node contains an Asynchronous Field...optimization to perform complex cognitive computing operations. This project focused on the design of the core and integration across a four node chip . A...follow on project will focus on creating a 3 dimensional stack of chips that is enabled by the low power usage. The chip incorporates structures to

A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition.

PubMed

Wu, Tong; Xu, Jian; Lian, Yong; Khalili, Azam; Rastegarnia, Amir; Guan, Cuntai; Yang, Zhi

2016-02-01

In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm (2) for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

NASA Technical Reports Server (NTRS)

Bolcar, Matthew R.; Leisawitz, David; Maher, Steve; Rinehart, Stephen

2012-01-01

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Dr. Monaco Examines Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Dr. Lisa Monaco, Marshall Space Flight Center's (MSFC's) project scientist for the Lab-on-a-Chip Applications Development (LOCAD) program, examines a lab on a chip. The small dots are actually ports where fluids and chemicals can be mixed or samples can be collected for testing. Tiny channels, only clearly visible under a microscope, form pathways between the ports. Many chemical and biological processes, previously conducted on large pieces of laboratory equipment, can now be performed on these small glass or plastic plates. Monaco and other researchers at MSFC in Huntsville, Alabama, are customizing the chips to be used for many space applications, such as monitoring microbes inside spacecraft and detecting life on other planets. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the International Space Station (ISS), the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

65nm RadSafe™ Technology for RC64 and Advanced SOCs

NASA Astrophysics Data System (ADS)

Liran, Tuvia; Ginosar, Ran; Lange, Fredy; Mandler, Alberto; Aviely, Peleg; Meirov, Henri; Goldberg, Michael; Meister, Zeev; Oliel, Mickey

2015-09-01

The trend of scaling of microelectronic provides certain advantages for space components, as well as some challenges. It enables implementing highly integrated and high performance ASICs, reducing power, area and weight. Scaling also improves the immunity to TID and SEL in most cases, but increases soft error rate significantly. Ramon Chips adopted the 65nm technology for implementing RC64 [1,2], a 64 core DSP for space applications, and for making other future products. The 65nm process node is widely used, very mature, and supported by wide range of IP providers. Thus the need for full custom design of cores and IPs is minimized, and radiation hardening is achievable by mitigating the radiation effects on the available IPs, and developing proprietary IPs only for complementing the available IPs. The RadSafe_65TM technology includes hardened standard cells and I/O libraries, methods for mitigation of radiation effects in COTS IP cores (SRAM, PLL, SERDES, DDR2/3 interface) and adding unique cores for monitoring radiation effects and junction temperature. We had developed RADIC6, a technology development vehicle, for verification of all hard cores and verification of the methodologies and design flow required for RC64. RADIC6 includes the test structures for characterizing the IP cores for immunity to all radiation effects. This paper describes the main elements and IP cores of RadSafe_65TM, as well as the contents of RADIC6 test chip.

Microarray Я US: a user-friendly graphical interface to Bioconductor tools that enables accurate microarray data analysis and expedites comprehensive functional analysis of microarray results.

PubMed

Dai, Yilin; Guo, Ling; Li, Meng; Chen, Yi-Bu

2012-06-08

Microarray data analysis presents a significant challenge to researchers who are unable to use the powerful Bioconductor and its numerous tools due to their lack of knowledge of R language. Among the few existing software programs that offer a graphic user interface to Bioconductor packages, none have implemented a comprehensive strategy to address the accuracy and reliability issue of microarray data analysis due to the well known probe design problems associated with many widely used microarray chips. There is also a lack of tools that would expedite the functional analysis of microarray results. We present Microarray Я US, an R-based graphical user interface that implements over a dozen popular Bioconductor packages to offer researchers a streamlined workflow for routine differential microarray expression data analysis without the need to learn R language. In order to enable a more accurate analysis and interpretation of microarray data, we incorporated the latest custom probe re-definition and re-annotation for Affymetrix and Illumina chips. A versatile microarray results output utility tool was also implemented for easy and fast generation of input files for over 20 of the most widely used functional analysis software programs. Coupled with a well-designed user interface, Microarray Я US leverages cutting edge Bioconductor packages for researchers with no knowledge in R language. It also enables a more reliable and accurate microarray data analysis and expedites downstream functional analysis of microarray results.

Development of 20 GHz monolithic transmit modules

NASA Technical Reports Server (NTRS)

Higgins, J. A.

1988-01-01

The history of the development of a transmit module for the band 17.7 to 20.2 GHz is presented. The module was to monolithically combine, on one chip, five bits of phase shift, a buffer amplifier and a power amplifier to produce 200 mW to the antenna element. The approach taken was MESFET ion implanted device technology. A common pinch-off voltage was decided upon for each application. The beginning of the total integration phases revealed hitherto unencountered hazards of large microwave circuit integration which were successfully overcome. Yield and customer considerations finally led to two separate chips, one containing the power amplifiers and the other containing the complete five bit phase shifter.

Clementine RRELAX SRAM Particle Spectrometer

NASA Technical Reports Server (NTRS)

Buehler, M.; Soli, G.; Blaes, B.; Ratliff, J.; Garrett, H.

1994-01-01

The Clementine RRELAX radiation monitor chip consists of a p-FET total dose monitor and a 4-kbit SRAM particle spectrometer. Eight of these chips were included in the RRELAX and used to detect the passage of the Clementine (S/C) and the innerstage adapter (ISA) through the earth's radiation belts and the 21-Feb 1994 solar flare. This is the first space flight for this 1.2 micron rad-soft custom CMOS radiation monitor. This paper emphasizes results from the SRAM particle detector which showed that it a) has a detection range of five orders of magnitude relative to the 21-Feb solar flare, b) is not affected by electrons, and c) detected microflares occurring with a 26.5 day period.

Versatile all-digital time interval measuring system

NASA Astrophysics Data System (ADS)

Vyhlidal, David; Cech, Miroslav

2011-06-01

This paper describes a design and performance of a versatile all-digital time interval measuring system. The measurement method is based on an interpolation principle. In this principle the time interval is first roughly digitized by a coarse counter driven by a high stability reference clock and the fractions between the clock periods are measured by two Time-to-Digital Converter chips TDC-GPX manufactured by Acam messelectronic. Control circuits allow programmable customization of the system to satisfy many applications such as laser range finding, event counting, or time-of-flight measurements in various physics experiments. The system has two reference clocks inputs and two independent channels for measuring start and stop events. Only one 40 MHz reference is required for the measurement. The second reference can be, for example, 1 PPS (Pulse per Second) signal from a GPS (Global Positioning System) to time tag events. Time intervals are measured using the highest resolution mode of the TDC-GPX chips. The resolution of each chip is software programmable and is PLL (Phase Locked Loop) stabilized against temperature and voltage variations. The system can achieve a timing resolution better than 15 ps rms with up to 90 kHz repetition rate. The time interval measurement range is from 0 ps up to 1 second. The power consumption of the whole system is 18 W including an embedded computer board and an LCD (Liquid Crystal Display) screen. The embedded computer controls the whole system, collects and evaluates measurement data and with the display provides a user interface. The system is implemented using commercially available components.

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

CAVIAR: a 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking.

PubMed

Serrano-Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares-Barranco, Alejandro; Paz-Vicente, Rafael; Gomez-Rodriguez, Francisco; Camunas-Mesa, Luis; Berner, Raphael; Rivas-Perez, Manuel; Delbruck, Tobi; Liu, Shih-Chii; Douglas, Rodney; Hafliger, Philipp; Jimenez-Moreno, Gabriel; Civit Ballcels, Anton; Serrano-Gotarredona, Teresa; Acosta-Jimenez, Antonio J; Linares-Barranco, Bernabé

2009-09-01

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Gallium arsenide pilot line for high performance components

NASA Astrophysics Data System (ADS)

1990-01-01

The Gallium Arsenide Pilot Line for High Performance Components (Pilot Line III) is to develop a facility for the fabrication of GaAs logic and memory chips. The first thirty months of this contract are now complete, and this report covers the period from March 27 through September 24, 1989. Similar to the PT-2M SRAM function for memories, the six logic circuits of PT-2L and PT-2M have served their functions as stepping stones toward the custom, standard cell, and cell array logic circuits. All but one of these circuits was right first time; the remaining circuit had a layout error due to a bug in the design rule checker that has since been fixed. The working devices all function over the full temperature range from -55 to 125 C. They all comfortably meet the 200 MHz requirement. They do not solidly conform to the required input and output voltage levels, particularly Vih. It is known that these circuits were designed with the older design models and that they came from an era where the DFET thresholds were often not on target.

Numerical investigation of thermal performance of a water-cooled mini-channel heat sink for different chip arrangement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tikadar, Amitav, E-mail: amitav453@gmail.com; Hossain, Md. Mahamudul; Morshed, A. K. M. M.

Heat transfer from electronic chip is always challenging and very crucial for electronic industry. Electronic chips are assembled in various manners according to the design conditions and limitationsand thus the influence of chip assembly on the overall thermal performance needs to be understand for the efficient design of electronic cooling system. Due to shrinkage of the dimension of channel and continuous increment of thermal load, conventional heat extraction techniques sometimes become inadequate. Due to high surface area to volume ratio, mini-channel have the natural advantage to enhance convective heat transfer and thus to play a vital role in the advancedmore » heat transfer devices with limited surface area and high heat flux. In this paper, a water cooled mini-channel heat sink was considered for electronic chip cooling and five different chip arrangements were designed and studied, namely: the diagonal arrangement, parallel arrangement, stacked arrangement, longitudinal arrangement and sandwiched arrangement. Temperature distribution on the chip surfaces was presented and the thermal performance of the heat sink in terms of overall thermal resistance was also compared. It is found that the sandwiched arrangement of chip provides better thermal performance compared to conventional in line chip arrangement.« less

Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect.

PubMed

Liao, Chen; Hu, Shiyan

2014-03-01

Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique.

Next Generation Programmable Bio-Nano-Chip System for On-Site Detection in Oral Fluids.

PubMed

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W; McRae, Michael P; Wong, Jorge; Newton, Thomas F; Kosten, Thomas R; Haque, Ahmed; McDevitt, John T

2015-11-23

Current on-site drug of abuse detection methods involve invasive sampling of blood and urine specimens, or collection of oral fluid, followed by qualitative screening tests using immunochromatographic cartridges. Test confirmation and quantitative assessment of a presumptive positive are then provided by remote laboratories, an inefficient and costly process decoupled from the initial sampling. Recently, a new noninvasive oral fluid sampling approach that is integrated with the chip-based Programmable Bio-Nano-Chip (p-BNC) platform has been developed for the rapid (~ 10 minutes), sensitive detection (~ ng/ml) and quantitation of 12 drugs of abuse. Furthermore, the system can provide the time-course of select drug and metabolite profiles in oral fluids. For cocaine, we observed three slope components were correlated with cocaine-induced impairment using this chip-based p-BNC detection modality. Thus, this p-BNC has significant potential for roadside drug testing by law enforcement officers. Initial work reported on chip-based drug detection was completed using 'macro' or "chip in the lab" prototypes, that included metal encased "flow cells", external peristaltic pumps and a bench-top analyzer system instrumentation. We now describe the next generation miniaturized analyzer instrumentation along with customized disposables and sampling devices. These tools will offer real-time oral fluid drug monitoring capabilities, to be used for roadside drug testing as well as testing in clinical settings as a non-invasive, quantitative, accurate and sensitive tool to verify patient adherence to treatment.

Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

PubMed

Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

2005-09-01

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB.

Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing

NASA Astrophysics Data System (ADS)

Kakad, Yogendra P.; Sherlock, Barry G.; Chatapuram, Krishnan V.; Bishop, Stephen

2001-10-01

An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.

Real-time PCR Machine System Modeling and a Systematic Approach for the Robust Design of a Real-time PCR-on-a-Chip System

PubMed Central

Lee, Da-Sheng

2010-01-01

Chip-based DNA quantification systems are widespread, and used in many point-of-care applications. However, instruments for such applications may not be maintained or calibrated regularly. Since machine reliability is a key issue for normal operation, this study presents a system model of the real-time Polymerase Chain Reaction (PCR) machine to analyze the instrument design through numerical experiments. Based on model analysis, a systematic approach was developed to lower the variation of DNA quantification and achieve a robust design for a real-time PCR-on-a-chip system. Accelerated lift testing was adopted to evaluate the reliability of the chip prototype. According to the life test plan, this proposed real-time PCR-on-a-chip system was simulated to work continuously for over three years with similar reproducibility in DNA quantification. This not only shows the robustness of the lab-on-a-chip system, but also verifies the effectiveness of our systematic method for achieving a robust design. PMID:22315563

SpectraCAM SPM: a camera system with high dynamic range for scientific and medical applications

NASA Astrophysics Data System (ADS)

Bhaskaran, S.; Baiko, D.; Lungu, G.; Pilon, M.; VanGorden, S.

2005-08-01

A scientific camera system having high dynamic range designed and manufactured by Thermo Electron for scientific and medical applications is presented. The newly developed CID820 image sensor with preamplifier-per-pixel technology is employed in this camera system. The 4 Mega-pixel imaging sensor has a raw dynamic range of 82dB. Each high-transparent pixel is based on a preamplifier-per-pixel architecture and contains two photogates for non-destructive readout of the photon-generated charge (NDRO). Readout is achieved via parallel row processing with on-chip correlated double sampling (CDS). The imager is capable of true random pixel access with a maximum operating speed of 4MHz. The camera controller consists of a custom camera signal processor (CSP) with an integrated 16-bit A/D converter and a PowerPC-based CPU running a Linux embedded operating system. The imager is cooled to -40C via three-stage cooler to minimize dark current. The camera housing is sealed and is designed to maintain the CID820 imager in the evacuated chamber for at least 5 years. Thermo Electron has also developed custom software and firmware to drive the SpectraCAM SPM camera. Included in this firmware package is the new Extreme DRTM algorithm that is designed to extend the effective dynamic range of the camera by several orders of magnitude up to 32-bit dynamic range. The RACID Exposure graphical user interface image analysis software runs on a standard PC that is connected to the camera via Gigabit Ethernet.

Design of the first optical system for real-time tomographic holography (RTTH)

NASA Astrophysics Data System (ADS)

Galeotti, John M.; Siegel, Mel; Rallison, Richard D.; Stetten, George

2008-08-01

The design of the first Real-Time-Tomographic-Holography (RTTH) optical system for augmented-reality applications is presented. RTTH places a viewpoint-independent real-time (RT) virtual image (VI) of an object into its actual location, enabling natural hand-eye coordination to guide invasive procedures, without requiring tracking or a head-mounted device. The VI is viewed through a narrow-band Holographic Optical Element (HOE) with built-in power that generates the largest possible near-field, in-situ VI from a small display chip without noticeable parallax error or obscuring direct view of the physical world. Rigidly fixed upon a medical-ultrasound probe, RTTH could show the scan in its actual location inside the patient, because the VI would move with the probe. We designed the image source along with the system-optics, allowing us to ignore both planer geometric distortions and field curvature, respectively compensated by using RT pre-processing software and attaching a custom-surfaced fiber-optic-faceplate (FOFP) to our image source. Focus in our fast, non-axial system was achieved by placing correcting lenses near the FOFP and custom-optically-fabricating our volume-phase HOE using a recording beam that was specially shaped by extra lenses. By simultaneously simulating and optimizing the system's playback performance across variations in both the total playback and HOE-recording optical systems, we derived and built a design that projects a 104x112 mm planar VI 1 m from the HOE using a laser-illuminated 19x16 mm LCD+FOFP image-source. The VI appeared fixed in space and well focused. Viewpoint-induced location errors were <3 mm, and unexpected first-order astigmatism produced 3 cm (3% of 1 m) ambiguity in depth, typically unnoticed by human observers.

Design and prototyping of a chip-based multi-micro-organoid culture system for substance testing, predictive to human (substance) exposure.

PubMed

Sonntag, Frank; Schilling, Niels; Mader, Katja; Gruchow, Mathias; Klotzbach, Udo; Lindner, Gerd; Horland, Reyk; Wagner, Ilka; Lauster, Roland; Howitz, Steffen; Hoffmann, Silke; Marx, Uwe

2010-07-01

Dynamic miniaturized human multi-micro-organ bioreactor systems are envisaged as a possible solution for the embarrassing gap of predictive substance testing prior to human exposure. A rational approach was applied to simulate and design dynamic long-term cultures of the smallest possible functional human organ units, human "micro-organoids", on a chip the shape of a microscope slide. Each chip contains six identical dynamic micro-bioreactors with three different micro-organoid culture segments each, a feed supply and waste reservoirs. A liver, a brain cortex and a bone marrow micro-organoid segment were designed into each bioreactor. This design was translated into a multi-layer chip prototype and a routine manufacturing procedure was established. The first series of microscopable, chemically resistant and sterilizable chip prototypes was tested for matrix compatibility and primary cell culture suitability. Sterility and long-term human cell survival could be shown. Optimizing the applied design approach and prototyping tools resulted in a time period of only 3 months for a single design and prototyping cycle. This rapid prototyping scheme now allows for fast adjustment or redesign of inaccurate architectures. The designed chip platform is thus ready to be evaluated for the establishment and maintenance of the human liver, brain cortex and bone marrow micro-organoids in a systemic microenvironment. Copyright (c) 2010 Elsevier B.V. All rights reserved.

Solanum torvum responses to the root-knot nematode Meloidogyne incognita

PubMed Central

2013-01-01

Background Solanum torvum Sw is worldwide employed as rootstock for eggplant cultivation because of its vigour and resistance/tolerance to the most serious soil-borne diseases as bacterial, fungal wilts and root-knot nematodes. The little information on Solanum torvum (hereafter Torvum) resistance mechanisms, is mostly attributable to the lack of genomic tools (e.g. dedicated microarray) as well as to the paucity of database information limiting high-throughput expression studies in Torvum. Results As a first step towards transcriptome profiling of Torvum inoculated with the nematode M. incognita, we built a Torvum 3’ transcript catalogue. One-quarter of a 454 full run resulted in 205,591 quality-filtered reads. De novo assembly yielded 24,922 contigs and 11,875 singletons. Similarity searches of the S. torvum transcript tags catalogue produced 12,344 annotations. A 30,0000 features custom combimatrix chip was then designed and microarray hybridizations were conducted for both control and 14 dpi (day post inoculation) with Meloidogyne incognita-infected roots samples resulting in 390 differentially expressed genes (DEG). We also tested the chip with samples from the phylogenetically-related nematode-susceptible eggplant species Solanum melongena. An in-silico validation strategy was developed based on assessment of sequence similarity among Torvum probes and eggplant expressed sequences available in public repositories. GO term enrichment analyses with the 390 Torvum DEG revealed enhancement of several processes as chitin catabolism and sesquiterpenoids biosynthesis, while no GO term enrichment was found with eggplant DEG. The genes identified from S. torvum catalogue, bearing high similarity to known nematode resistance genes, were further investigated in view of their potential role in the nematode resistance mechanism. Conclusions By combining 454 pyrosequencing and microarray technology we were able to conduct a cost-effective global transcriptome profiling in a non-model species. In addition, the development of an in silico validation strategy allowed to further extend the use of the custom chip to a related species and to assess by comparison the expression of selected genes without major concerns of artifacts. The expression profiling of S. torvum responses to nematode infection points to sesquiterpenoids and chitinases as major effectors of nematode resistance. The availability of the long sequence tags in S. torvum catalogue will allow precise identification of active nematocide/nematostatic compounds and associated enzymes posing the basis for exploitation of these resistance mechanisms in other species. PMID:23937585

Association of Genetic Loci with Sleep Apnea in European Americans and African-Americans: The Candidate Gene Association Resource (CARe)

PubMed Central

Patel, Sanjay R.; Goodloe, Robert; De, Gourab; Kowgier, Matthew; Weng, Jia; Buxbaum, Sarah G.; Cade, Brian; Fulop, Tibor; Gharib, Sina A.; Gottlieb, Daniel J.; Hillman, David; Larkin, Emma K.; Lauderdale, Diane S.; Li, Li; Mukherjee, Sutapa; Palmer, Lyle; Zee, Phyllis; Zhu, Xiaofeng; Redline, Susan

2012-01-01

Although obstructive sleep apnea (OSA) is known to have a strong familial basis, no genetic polymorphisms influencing apnea risk have been identified in cross-cohort analyses. We utilized the National Heart, Lung, and Blood Institute (NHLBI) Candidate Gene Association Resource (CARe) to identify sleep apnea susceptibility loci. Using a panel of 46,449 polymorphisms from roughly 2,100 candidate genes on a customized Illumina iSelect chip, we tested for association with the apnea hypopnea index (AHI) as well as moderate to severe OSA (AHI≥15) in 3,551 participants of the Cleveland Family Study and two cohorts participating in the Sleep Heart Health Study. Among 647 African-Americans, rs11126184 in the pleckstrin (PLEK) gene was associated with OSA while rs7030789 in the lysophosphatidic acid receptor 1 (LPAR1) gene was associated with AHI using a chip-wide significance threshold of p-value<2×10−6. Among 2,904 individuals of European ancestry, rs1409986 in the prostaglandin E2 receptor (PTGER3) gene was significantly associated with OSA. Consistency of effects between rs7030789 and rs1409986 in LPAR1 and PTGER3 and apnea phenotypes were observed in independent clinic-based cohorts. Novel genetic loci for apnea phenotypes were identified through the use of customized gene chips and meta-analyses of cohort data with replication in clinic-based samples. The identified SNPs all lie in genes associated with inflammation suggesting inflammation may play a role in OSA pathogenesis. PMID:23155414

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Surface normal coupling to multiple-slot and cover-slotted silicon nanocrystalline waveguides and ring resonators

NASA Astrophysics Data System (ADS)

Covey, John; Chen, Ray T.

2014-03-01

Grating couplers are ideal for coupling into the tightly confined propagation modes of semiconductor waveguides. In addition, nonlinear optics has benefited from the sub-diffraction limit confinement of horizontal slot waveguides. By combining these two advancements, slot-based nonlinear optics with mode areas less than 0.02 μm2 can become as routine as twisting fiber connectors together. Surface normal fiber alignment to a chip is also highly desirable from time, cost, and manufacturing considerations. To meet these considerable design challenges, a custom genetic algorithm is created which, starting from purely random designs, creates a unique four stage grating coupler for two novel horizontal slot waveguide platforms. For horizontal multiple-slot waveguides filled with silicon nanocrystal, a theoretical fiber-towaveguide coupling efficiency of 68% is obtained. For thin silicon waveguides clad with optically active silicon nanocrystal, known as cover-slot waveguides, a theoretical fiber-to-waveguide coupling efficiency of 47% is obtained, and 1 dB and 3 dB theoretical bandwidths of 70 nm and 150 nm are obtained, respectively. Both waveguide platforms are fabricated from scratch, and their respective on-chip grating couplers are experimentally measured from a standard single mode fiber array that is mounted surface normally. The horizontal multiple-slot grating coupler achieved an experimental 60% coupling efficiency, and the horizontal cover-slot grating coupler achieved an experimental 38.7% coupling efficiency, with an extrapolated 1 dB bandwidth of 66 nm. This report demonstrates the promise of genetic algorithm-based design by reducing to practice the first large bandwidth vertical grating coupler to a novel silicon nanocrystal horizontal cover-slot waveguide.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Controlled and tunable polymer particles' production using a single microfluidic device

NASA Astrophysics Data System (ADS)

Amoyav, Benzion; Benny, Ofra

2018-04-01

Microfluidics technology offers a new platform to control liquids under flow in small volumes. The advantage of using small-scale reactions for droplet generation along with the capacity to control the preparation parameters, making microfluidic chips an attractive technology for optimizing encapsulation formulations. However, one of the drawback in this methodology is the ability to obtain a wide range of droplet sizes, from sub-micron to microns using a single chip design. In fact, typically, droplet chips are used for micron-dimension particles, while nanoparticles' synthesis requires complex chips design (i.e., microreactors and staggered herringbone micromixer). Here, we introduce the development of a highly tunable and controlled encapsulation technique, using two polymer compositions, for generating particles ranging from microns to nano-size using the same simple single microfluidic chip design. Poly(lactic-co-glycolic acid) (PLGA 50:50) or PLGA/polyethylene glycol polymeric particles were prepared with focused-flow chip, yielding monodisperse particle batches. We show that by varying flow rate, solvent, surfactant and polymer composition, we were able to optimize particles' size and decrease polydispersity index, using simple chip designs with no further related adjustments or costs. Utilizing this platform, which offers tight tuning of particle properties, could offer an important tool for formulation development and can potentially pave the way towards a better precision nanomedicine.

Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

NASA Technical Reports Server (NTRS)

Holmes, Anna M.; Monaco, Lisa; Barnes, Cindy; Spearing, Scott; Jenkins, Andy; Johnson, Todd; Mayer, Derek; Cole, Helen

2003-01-01

The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

PubMed

Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

2016-01-01

Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Assessing the Power of Exome Chips.

PubMed

Page, Christian Magnus; Baranzini, Sergio E; Mevik, Bjørn-Helge; Bos, Steffan Daniel; Harbo, Hanne F; Andreassen, Bettina Kulle

2015-01-01

Genotyping chips for rare and low-frequent variants have recently gained popularity with the introduction of exome chips, but the utility of these chips remains unclear. These chips were designed using exome sequencing data from mainly American-European individuals, enriched for a narrow set of common diseases. In addition, it is well-known that the statistical power of detecting associations with rare and low-frequent variants is much lower compared to studies exclusively involving common variants. We developed a simulation program adaptable to any exome chip design to empirically evaluate the power of the exome chips. We implemented the main properties of the Illumina HumanExome BeadChip array. The simulated data sets were used to assess the power of exome chip based studies for varying effect sizes and causal variant scenarios. We applied two widely-used statistical approaches for rare and low-frequency variants, which collapse the variants into genetic regions or genes. Under optimal conditions, we found that a sample size between 20,000 to 30,000 individuals were needed in order to detect modest effect sizes (0.5% < PAR > 1%) with 80% power. For small effect sizes (PAR <0.5%), 60,000-100,000 individuals were needed in the presence of non-causal variants. In conclusion, we found that at least tens of thousands of individuals are necessary to detect modest effects under optimal conditions. In addition, when using rare variant chips on cohorts or diseases they were not originally designed for, the identification of associated variants or genes will be even more challenging.

Design and fabrication of metal briquette machine for shop floor

NASA Astrophysics Data System (ADS)

Pramod, R.; Kumar, G. B. Veeresh; Prashanth B., N.

2017-07-01

Efforts have to be taken to ensure efficient waste management system in shop floors, with minimum utilization of space and energy when it comes to disposing metal chips formed during machining processes. The salvaging of junk metallic chips and the us e of scrap are important for the economic production of a steelworks. For this purpose, we have fabricated a metal chip compaction machine, which can compact the metal chips into small briquettes. The project started with the survey of chips formed in shop floors and the practices involved in waste management. Study was done on the requirements for a better compaction. The heating chamber was designed taking into consideration the temperature required for an easy compaction of the metal chips. The power source for compaction and the pneumatic design for mechanism was done following the appropriate calculations regarding the air pressure provided and thrust required. The processes were tested under different conditions and found effective. The fabrication of the machine has been explained in detail and the results have been discussed.

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Methods for Trustworthy Design of On-Chip Bus Interconnect for General-Purpose Processors

DTIC Science & Technology

2012-03-01

Technology Andrew Huang, was able to test the security properties of HyperTransport bus protocol on an Xbox [20]. In his research, he was able to...TRUSTWORTHY DESIGN OF ON -CHIP BUS INTERCONNECT FOR GENERAL-PURPOSE PROCESSORS by Jay F. Elson March 2012 Thesis Advisor: Ted Huffmire Second...AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Methods for Trustworthy Design of On -Chip Bus Interconnect for General-Purpose Processors 5

Determining the Terminal Velocity of Wood and Bark Chips

Treesearch

John A. Sturos

1972-01-01

Designing an efficient air flotation segregator to segregate bark chips from wood chips requires that the terminal velocities be determined for various pulpwood species. The technique described here uses forced air in a vertical wind tunnel with the chip initially at rest on a stationary screen; when the terminal air velocity in reached, the chip begins to float. A...

Design of replica bit line control circuit to optimize power for SRAM

NASA Astrophysics Data System (ADS)

Pengjun, Wang; Keji, Zhou; Huihong, Zhang; Daohui, Gong

2016-12-01

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002, 61474068), and the K. C. Wong Magna Fund in Ningbo University.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1981-01-01

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Integrated potentiometric detector for use in chip-based flow cells

PubMed

Tantra; Manz

2000-07-01

A new kind of potentiometric chip sensor for ion-selective electrodes (ISE) based on a solvent polymeric membrane is described. The chip sensor is designed to trap the organic cocktail inside the chip and to permit sample solution to flow past the membrane. The design allows the sensor to overcome technical problems of ruggedness and would therefore be ideal for industrial processes. The sensor performance for a Ba2+-ISE membrane based on a Vogtle ionophore showed electrochemical behavior similar to that observed in conventional electrodes and microelectrode arrangements.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Advanced staring Si PIN visible sensor chip assembly for Bepi-Colombo mission to Mercury

NASA Astrophysics Data System (ADS)

Mills, R. E.; Drab, J. J.; Gin, A.

2009-08-01

The planet Mercury, by its near proximity to the sun, has always posed a formidable challenge to spacecraft. The Bepi-Colombo mission, coordinated by the European Space Agency, will be a pioneering effort in the investigation of this planet. Raytheon Vision Systems (RVS) has been given the opportunity to develop the radiation hardened, high operability, high SNR, advanced staring focal plane array (FPA) for the spacecraft destined (Fig. 1) to explore the planet Mercury. This mission will launch in 2013 on a journey lasting approximately 6 years. When it arrives at Mercury in August 2019, it will endure temperatures as high as 350°C as well as relatively high radiation environments during its 1 year data collection period from September 2019 until September 2020. To support this challenging goal, RVS has designed and produced a custom visible sensor based on a 2048 x 2048 (2k2) format with a 10 μm unit cell. This sensor will support both the High Resolution Imaging Camera (HRIC) and the Stereo Camera (STC) instruments. This dual purpose sensor was designed to achieve high sensitivity as well as low input noise (<100 e-) for space-based, low light conditions. It also must maintain performance parameters in a total ionizing dose environment up to 70 kRad (Si) as well as immunity to latch-up and singe event upset. This paper will show full sensor chip assembly data highlighting the performance parameters prior to irradiation. Radiation testing performance will be reported by an independent source in a subsequent paper.

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications.

PubMed

Patou, François; AlZahra'a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E

2016-09-03

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods.

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications

PubMed Central

Patou, François; AlZahra’a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E.

2016-01-01

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods. PMID:27598208

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

PubMed

Kirk, Andrew G; Plant, David V; Szymanski, Ted H; Vranesic, Zvonko G; Tooley, Frank A P; Rolston, David R; Ayliffe, Michael H; Lacroix, Frederic K; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F

2003-05-10

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

NASA Astrophysics Data System (ADS)

Kirk, Andrew G.; Plant, David V.; Szymanski, Ted H.; Vranesic, Zvonko G.; Tooley, Frank A. P.; Rolston, David R.; Ayliffe, Michael H.; Lacroix, Frederic K.; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F.

2003-05-01

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

The interplay between customer participation and difficulty of design examples in the online designing process and its effect on customer satisfaction: mediational analyses.

PubMed

Chang, Chia-Chi; Chen, Hui-Yun; Huang, I-Chiang

2009-04-01

In the current consumer-centric economy, consumers increasingly desire the opportunity to design their own products in order to express more effectively their self-image. Mass customization, based on efficient and flexible modulization designs, has provided individualized products to satisfy this desire. This work presents an experiment employed to demonstrate that customer participation leads to higher satisfaction. Specifically, the increment in customer satisfaction due to participation is greater when an easy example is provided than when either no example or a difficult one is provided. Additionally, self-congruity plays a mediating role on the customer participation-satisfaction relationship, and this mediating effect varies across different levels of the design example provided in the design process. When an easy design example is present, customer participation has a direct effect on satisfaction, in addition to the indirect effect of self-congruity. When a difficult example is provided, customer participation does not have incremental effects on either self-congruity or customer satisfaction. Finally, when no design example is shown to customers, contrary to our expectation, participation still enhances customer satisfaction due to an increased sense of self-congruity.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

In vivo operation of the Boston 15-channel wireless subretinal visual prosthesis

NASA Astrophysics Data System (ADS)

Shire, Douglas B.; Doyle, Patrick; Kelly, Shawn K.; Gingerich, Marcus D.; Chen, Jinghua; Cogan, Stuart F.; Drohan, William A.; Mendoza, Oscar; Theogarajan, Luke; Wyatt, John; Rizzo, Joseph F.

2010-02-01

This presentation concerns the engineering development of the Boston visual prosthesis for restoring useful vision to patients blind with degenerative retinal disease. A miniaturized, hermetically-encased, 15-channel wirelessly-operated retinal prosthetic was developed for implantation and pre-clinical studies in Yucatan mini-pig animal models. The prosthesis conforms to the eye and drives a microfabricated polyimide stimulating electrode array having sputtered iridium oxide electrodes. This array is implanted into the subretinal space using a specially-designed ab externo surgical technique; the bulk of the prosthesis is on the surface of the sclera. The implanted device includes a hermetic titanium case containing a 15-channel stimulator chip; secondary power/data receiving coils surround the cornea. Long-term in vitro pulse testing was also performed on the electrodes to ensure their stability over years of operation. Assemblies were first tested in vitro to verify wireless operation of the system in biological saline using a custom RF transmitter circuit and primary coils. Stimulation pulse strength, duration and frequency were programmed wirelessly using a computer with a custom graphical user interface. Operation of the retinal implant was verified in vivo in 3 minipigs for more than three months by measuring stimulus artifacts on the eye surface using contact lens electrodes.

Use of a double chip seal to correct a flushing hot mix asphalt pavement in Washington State.

DOT National Transportation Integrated Search

2011-04-01

A chip seal constructed on an existing flushed roadway has the potential to result in bleeding or flushing of the new chip seal. The excess binder, if not properly accounted for during design and construction, will migrate to the surface of the chip ...

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

GeneChip Resequencing of the Smallpox Virus Genome Can Identify Novel Strains: a Biodefense Application▿

PubMed Central

Sulaiman, Irshad M.; Tang, Kevin; Osborne, John; Sammons, Scott; Wohlhueter, Robert M.

2007-01-01

We developed a set of seven resequencing GeneChips, based on the complete genome sequences of 24 strains of smallpox virus (variola virus), for rapid characterization of this human-pathogenic virus. Each GeneChip was designed to analyze a divergent segment of approximately 30,000 bases of the smallpox virus genome. This study includes the hybridization results of 14 smallpox virus strains. Of the 14 smallpox virus strains hybridized, only 7 had sequence information included in the design of the smallpox virus resequencing GeneChips; similar information for the remaining strains was not tiled as a reference in these GeneChips. By use of variola virus-specific primers and long-range PCR, 22 overlapping amplicons were amplified to cover nearly the complete genome and hybridized with the smallpox virus resequencing GeneChip set. These GeneChips were successful in generating nucleotide sequences for all 14 of the smallpox virus strains hybridized. Analysis of the data indicated that the GeneChip resequencing by hybridization was fast and reproducible and that the smallpox virus resequencing GeneChips could differentiate the 14 smallpox virus strains characterized. This study also suggests that high-density resequencing GeneChips have potential biodefense applications and may be used as an alternate tool for rapid identification of smallpox virus in the future. PMID:17182757

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

A data transmission method for particle physics experiments based on Ethernet physical layer

NASA Astrophysics Data System (ADS)

Huang, Xi-Ru; Cao, Ping; Zheng, Jia-Jun

2015-11-01

Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer (PHY) is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission. This kind of data path is fully implemented by hardware. From the side of the data acquisition system (DAQ), however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented. Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner. Supported by National Natural Science Foundation of China (11005107) and Independent Projects of State Key Laboratory of Particle Detection and Electronics (201301)

Design of the SLAC RCE Platform: A General Purpose ATCA Based Data Acquisition System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Herbst, R.; Claus, R.; Freytag, M.

2015-01-23

The SLAC RCE platform is a general purpose clustered data acquisition system implemented on a custom ATCA compliant blade, called the Cluster On Board (COB). The core of the system is the Reconfigurable Cluster Element (RCE), which is a system-on-chip design based upon the Xilinx Zynq family of FPGAs, mounted on custom COB daughter-boards. The Zynq architecture couples a dual core ARM Cortex A9 based processor with a high performance 28nm FPGA. The RCE has 12 external general purpose bi-directional high speed links, each supporting serial rates of up to 12Gbps. 8 RCE nodes are included on a COB, eachmore » with a 10Gbps connection to an on-board 24-port Ethernet switch integrated circuit. The COB is designed to be used with a standard full-mesh ATCA backplane allowing multiple RCE nodes to be tightly interconnected with minimal interconnect latency. Multiple shelves can be clustered using the front panel 10-gbps connections. The COB also supports local and inter-blade timing and trigger distribution. An experiment specific Rear Transition Module adapts the 96 high speed serial links to specific experiments and allows an experiment-specific timing and busy feedback connection. This coupling of processors with a high performance FPGA fabric in a low latency, multiple node cluster allows high speed data processing that can be easily adapted to any physics experiment. RTEMS and Linux are both ported to the module. The RCE has been used or is the baseline for several current and proposed experiments (LCLS, HPS, LSST, ATLAS-CSC, LBNE, DarkSide, ILC-SiD, etc).« less

Space Science

NASA Image and Video Library

2003-12-01

Dr. Lisa Monaco, Marshall Space Flight Center’s (MSFC’s) project scientist for the Lab-on-a-Chip Applications Development (LOCAD) program, examines a lab on a chip. The small dots are actually ports where fluids and chemicals can be mixed or samples can be collected for testing. Tiny channels, only clearly visible under a microscope, form pathways between the ports. Many chemical and biological processes, previously conducted on large pieces of laboratory equipment, can now be performed on these small glass or plastic plates. Monaco and other researchers at MSFC in Huntsville, Alabama, are customizing the chips to be used for many space applications, such as monitoring microbes inside spacecraft and detecting life on other planets. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the International Space Station (ISS), the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

Numerical and experimental evaluation of microfluidic sorting devices.

PubMed

Taylor, Jay K; Ren, Carolyn L; Stubley, G D

2008-01-01

The development of lab-on-a-chip devices calls for the isolation or separation of specific bioparticles or cells. The design of a miniaturized cell-sorting device for handheld operation must follow the strict parameters associated with lab-on-a-chip technology. The limitations include applied voltage, high efficiency of cell-separation, reliability, size, flow control, and cost, among others. Currently used designs have achieved successful levels of cell isolation; however, further improvements in the microfluidic chip design are important to incorporate into larger systems. This study evaluates specific design modifications that contribute to the reduction of required applied potential aiming for developing portable devices, improved operation reliability by minimizing induced pressure disturbance when electrokinetic pumping is employed, and improved flow control by incorporating directing streams achieving dynamic sorting and counting. The chip designs fabricated in glass and polymeric materials include asymmetric channel widths for sample focusing, nonuniform channel depth for minimizing induced pressure disturbance, directing streams to assist particle flow control, and online filters for reducing channel blockage. Fluorescence-based visualization experimental results of electrokinetic focusing, flow field phenomena, and dynamic sorting demonstrate the advantages of the chip design. Numerical simulations in COMSOL are validated by the experimental data and used to investigate the effects of channel geometry and fluid properties on the flow field.

A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories

DTIC Science & Technology

1989-02-01

frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form factors. The hardware consists of...generality for rendering curved surfaces, volume data, objects dcscri id with Constructive Solid Geometry, for rendering scenes using the radiosity ...f.aces and for computing a spherical radiosity lighting model (see Section 7.6). Custom Memory Chips \\ 208 bits x 128 pixels - Renderer Board ix p o a

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the Year 2006 Continuation Phase 2 three months period (April 1 to Sept. 30) of this project were to (a) conduct a probe elements industrial environment feasibility study and (b) fabricate embedded optical phase or microstructured SiC chips for individual gas species sensing. Specifically, SiC chips for temperature and pressure probe industrial applications were batch fabricated. Next, these chips were subject to a quality test for use in the probe sensor. A batch of the best chips for probe design were selected and subject to further tests that included sensor performance based on corrosive chemical exposure, powermore » plant soot exposure, light polarization variations, and extreme temperature soaking. Experimental data were investigated in detail to analyze these mentioned industrial parameters relevant to a power plant. Probe design was provided to overcome mechanical vibrations. All these goals have been achieved and are described in detail in the report. The other main focus of the reported work is to modify the SiC chip by fabricating an embedded optical phase or microstructures within the chip to enable gas species sensing under high temperature and pressure. This has been done in the Kar UCF Lab. using a laser-based system whose design and operation is explained. Experimental data from the embedded optical phase-based chip for changing temperatures is provided and shown to be isolated from gas pressure and species. These design and experimentation results are summarized to give positive conclusions on the proposed high temperature high pressure gas species detection optical sensor technology.« less

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Design and simulation of a semiconductor chip-based visible - NIR spectrometer for Earth observation

NASA Astrophysics Data System (ADS)

Coote, J.; Woolliams, E.; Fox, N.; Goodyer, I. D.; Sweeney, S. J.

2014-03-01

We present the development of a novel semiconductor chip-based spectrometer for calibration of Earth observation instruments. The chip follows the Solo spectroscopy approach utilising an array of microdisk resonators evanescently coupled to a central waveguide. Each resonator is tuned to select out a specific wavelength from the incoming spectrum, and forms a p-i-n junction in which current is generated when light of the correct wavelength is present. In this paper we discuss important design aspects including the choice of semiconductor material, design of semiconductor quantum well structures for optical absorption, and design and optimisation of the waveguide and resonators.

Chip seal design and specifications : final report.

DOT National Transportation Integrated Search

2016-12-01

Chip seals or seal coats, are a pavement preservation method constructed using a layer of asphalt binder that is covered by a uniformly graded aggregate. The benefits of chip seal include: sealing surface cracks, keeping water from penetrating the su...

DNA Microarray for Rapid Detection and Identification of Food and Water Borne Bacteria: From Dry to Wet Lab.

PubMed

Ranjbar, Reza; Behzadi, Payam; Najafi, Ali; Roudi, Raheleh

2017-01-01

A rapid, accurate, flexible and reliable diagnostic method may significantly decrease the costs of diagnosis and treatment. Designing an appropriate microarray chip reduces noises and probable biases in the final result. The aim of this study was to design and construct a DNA Microarray Chip for a rapid detection and identification of 10 important bacterial agents. In the present survey, 10 unique genomic regions relating to 10 pathogenic bacterial agents including Escherichia coli (E.coli), Shigella boydii, Sh.dysenteriae, Sh.flexneri, Sh.sonnei, Salmonella typhi, S.typhimurium, Brucella sp., Legionella pneumophila, and Vibrio cholera were selected for designing specific long oligo microarray probes. For this reason, the in-silico operations including utilization of the NCBI RefSeq database, Servers of PanSeq and Gview, AlleleID 7.7 and Oligo Analyzer 3.1 was done. On the other hand, the in-vitro part of the study comprised stages of robotic microarray chip probe spotting, bacterial DNAs extraction and DNA labeling, hybridization and microarray chip scanning. In wet lab section, different tools and apparatus such as Nexterion® Slide E, Qarray mini spotter, NimbleGen kit, TrayMix TM S4, and Innoscan 710 were used. A DNA microarray chip including 10 long oligo microarray probes was designed and constructed for detection and identification of 10 pathogenic bacteria. The DNA microarray chip was capable to identify all 10 bacterial agents tested simultaneously. The presence of a professional bioinformatician as a probe designer is needed to design appropriate multifunctional microarray probes to increase the accuracy of the outcomes.

Using conjoint and cluster analysis in developing new product for micro, small and medium enterprises (SMEs) based on customer preferences (Case study: Lampung province's banana chips)

NASA Astrophysics Data System (ADS)

Kosasih, Wilson; Salomon, Lithrone Laricha; Hutomo, Reynaldo

2017-08-01

This paper discusses the development of new products of Micro, Small and Medium Entreprises (SMEs) to identify what attributes are considered by consumers, as well as combinations of attributes that need to be analyzed into the main preferences of consumers. The purpose of this research is to increase the added value and competitiveness of SMEs through product innovation. The object of this study is banana chips produced by SMEs from the province of Lampung which it considered to be unique souvenirs of the province. The research data were collected by distributing questionnaires in Jakarta which has heterogeneous population, in order to develop banana chip's marketing and increase its market share in Indonesia. Data processing was performed using conjoint analysis and cluster analysis. Segmentation was performed using conjoint analysis based on the importance level of attributes and part-worth of level attributes of each cluster. Finally, characteristics and consumer preferences of each cluster will be a consideration in determining the product development and marketing strategies.

Magnetic wire trap arrays for biomarker-based molecular detection

NASA Astrophysics Data System (ADS)

Vieira, Gregory; Mahajan, Kalpesh; Ruan, Gang; Winter, Jessica; Sooryakumar, R.

2012-02-01

Submicrometer-scale magnetic devices built on chip-based platforms have recently been shown to present opportunities for new particle trapping and manipulation technologies. Meanwhile, advances in nanoparticle fabrication allow for the building of custom-made particles with precise control of their size, composition, and other properties such as magnetism, fluorescence, and surface biomarker characteristics. In particular, carefully tailored surface biomarkers facilitate precise binding to targeted molecules, self-actuated construction of hybrid structures, and fluorescence-based detection schemes. Based on these progresses, we present an on-chip detection mechanism for molecules with known surface markers. Hybrid nanostructures consisting of micelle nanoparticles, fluorescent quantum dots, and superparamagnetic iron oxide nanoparticles are used to detect proteins or DNA molecules. The target is detected by the magnetic and fluorescent functionalities of the composite nanostructure, whereas in the absence of the target these signals are not present. Underlying this approach is the simultaneous manipulation via ferromagnetic zigzag nanowire arrays and imaging via quantum dot excitation. This chip-based detection technique could provide a powerful, low cost tool for ultrasensitive molecule detection with ramifications in healthcare diagnostics and small-scale chemical synthesis.

3D printed nervous system on a chip.

PubMed

Johnson, Blake N; Lancaster, Karen Z; Hogue, Ian B; Meng, Fanben; Kong, Yong Lin; Enquist, Lynn W; McAlpine, Michael C

2016-04-21

Bioinspired organ-level in vitro platforms are emerging as effective technologies for fundamental research, drug discovery, and personalized healthcare. In particular, models for nervous system research are especially important, due to the complexity of neurological phenomena and challenges associated with developing targeted treatment of neurological disorders. Here we introduce an additive manufacturing-based approach in the form of a bioinspired, customizable 3D printed nervous system on a chip (3DNSC) for the study of viral infection in the nervous system. Micro-extrusion 3D printing strategies enabled the assembly of biomimetic scaffold components (microchannels and compartmented chambers) for the alignment of axonal networks and spatial organization of cellular components. Physiologically relevant studies of nervous system infection using the multiscale biomimetic device demonstrated the functionality of the in vitro platform. We found that Schwann cells participate in axon-to-cell viral spread but appear refractory to infection, exhibiting a multiplicity of infection (MOI) of 1.4 genomes per cell. These results suggest that 3D printing is a valuable approach for the prototyping of a customized model nervous system on a chip technology.

Implementation of medical monitor system based on networks

NASA Astrophysics Data System (ADS)

Yu, Hui; Cao, Yuzhen; Zhang, Lixin; Ding, Mingshi

2006-11-01

In this paper, the development trend of medical monitor system is analyzed and portable trend and network function become more and more popular among all kinds of medical monitor devices. The architecture of medical network monitor system solution is provided and design and implementation details of medical monitor terminal, monitor center software, distributed medical database and two kind of medical information terminal are especially discussed. Rabbit3000 system is used in medical monitor terminal to implement security administration of data transfer on network, human-machine interface, power management and DSP interface while DSP chip TMS5402 is used in signal analysis and data compression. Distributed medical database is designed for hospital center according to DICOM information model and HL7 standard. Pocket medical information terminal based on ARM9 embedded platform is also developed to interactive with center database on networks. Two kernels based on WINCE are customized and corresponding terminal software are developed for nurse's routine care and doctor's auxiliary diagnosis. Now invention patent of the monitor terminal is approved and manufacture and clinic test plans are scheduled. Applications for invention patent are also arranged for two medical information terminals.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Chip-set for quality of service support in passive optical networks

NASA Astrophysics Data System (ADS)

Ringoot, Edwin; Hoebeke, Rudy; Slabbinck, B. Hans; Verhaert, Michel

1998-10-01

In this paper the design of a chip-set for QoS provisioning in ATM-based Passive Optical Networks is discussed. The implementation of a general-purpose switch chip on the Optical Network Unit is presented, with focus on the design of the cell scheduling and buffer management logic. The cell scheduling logic supports `colored' grants, priority jumping and weighted round-robin scheduling. The switch chip offers powerful buffer management capabilities enabling the efficient support of GFR and UBR services. Multicast forwarding is also supported. In addition, the architecture of a MAC controller chip developed for a SuperPON access network is introduced. In particular, the permit scheduling logic and its implementation on the Optical Line Termination will be discussed. The chip-set enables the efficient support of services with different service requirements on the SuperPON. The permit scheduling logic built into the MAC controller chip in combination with the cell scheduling and buffer management capabilities of the switch chip can be used by network operators to offer guaranteed service performance to delay sensitive services, and to efficiently and fairly distribute any spare capacity to delay insensitive services.

Laser Direct Routing for High Density Interconnects

NASA Astrophysics Data System (ADS)

Moreno, Wilfrido Alejandro

The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral Diffused Link. A high density Laser Vertical Link with resistance values below 10 ohms was developed, studied and tested using design of experiment methodologies. The vertical link offers excellent advantages in the area of quick prototyping of electronic circuits, but even more important, due to having similar characteristics to a foundry produced via, it gives quick transfer from the prototype system verification stage to the mass production stage.

Innovative Teaching of IC Design and Manufacture Using the Superchip Platform

ERIC Educational Resources Information Center

Wilson, P. R.; Wilcock, R.; McNally, I.; Swabey, M.

2010-01-01

This paper describes how an intelligent chip architecture has allowed a large cohort of undergraduate (UG) students to be given effective practical insight into integrated circuit (IC) design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the "Superchip," was developed, which allows multiple student…

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

Microfluidic high performance liquid chromatography-chip hyphenation to inductively coupled plasma-mass spectrometry.

PubMed

Bishop, David P; Blanes, Lucas; Wilson, Alexander B; Wilbanks, Thor; Killeen, Kevin; Grimm, Rudolf; Wenzel, Ross; Major, Derek; Macka, Mirek; Clarke, David; Schmid, Robin; Cole, Nerida; Doble, Philip A

2017-05-12

The Agilent Chip Cube Interface is a microfluidic chip-based technology originally designed for nanospray molecular mass spectrometry in which the sample enrichment, nano-column, tubing, connectors and spray tip were integrated into a single biocompatible chip. Here we describe the hyphenation of the Chip Cube Interface to ICP-MS via modification of the standard HPLC chip design and a new total consumption nebuliser suitable for flow rates as low as 300nLmin -1 . The potential of the instrument to eliminate common nanoLC - ICP-MS shortcomings such as leaks, blockages and band-broadening was demonstrated via analysis of cyanocobalamin in equine plasma. The method was linear over three orders of magnitude with an r 2 of 0.9999, the peak area repeatability was 1.9% (n=7), and the detection limit was 14ngmL -1 . This novel configuration of the Chip Cube Interface coupled to ICP-MS is a suitable platform for the analysis of biomolecules associated with trace metals and speciation applications. Copyright © 2017 Elsevier B.V. All rights reserved.

Design of a dual-mode electrochemical measurement and analysis system.

PubMed

Yang, Jr-Fu; Wei, Chia-Ling; Wu, Jian-Fu; Liu, Bin-Da

2013-01-01

A dual-mode electrochemical measurement and analysis system is proposed. This system includes a dual-mode chip, which was designed and fabricated by using TSMC 0.35 µm 3.3 V/5 V 2P4M mixed-signal CMOS process. Two electrochemical measurement and analysis methods, chronopotentiometry and voltammetry, can be performed by using the proposed chip and system. The proposed chip and system are verified successfully by performing voltammetry and chronopotentiometry on solutions.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Improved diamond coring bits developed for dry and chip-flush drilling

NASA Technical Reports Server (NTRS)

Decker, W. E.; Hampe, W. R.; Hampton, W. H.; Simon, A. B.

1971-01-01

Two rotary diamond bit designs, one operating with a chip-flushing fluid, the second including auger section to remove drilled chips, enhance usefulness of tool for exploratory and industrial core-drilling of hard, abrasive mineral deposits and structural masonry.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Mehdi, Imran; Schlecht, Erich T.; Lee, Choonsup; Siles, Jose V.; Maestrini, Alain E.; Thomas, Bertrand; Jung, Cecile D.

2013-01-01

A 1.6-THz power-combined Schottky frequency tripler was designed to handle approximately 30 mW input power. The design of Schottky-based triplers at this frequency range is mainly constrained by the shrinkage of the waveguide dimensions with frequency and the minimum diode mesa sizes, which limits the maximum number of diodes that can be placed on the chip to no more than two. Hence, multiple-chip power-combined schemes become necessary to increase the power-handling capabilities of high-frequency multipliers. The design presented here overcomes difficulties by performing the power-combining directly on-chip. Four E-probes are located at a single input waveguide in order to equally pump four multiplying structures (featuring two diodes each). The produced output power is then recombined at the output using the same concept.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Separation and Analysis of Adherent and Non-Adherent Cancer Cells Using a Single-Cell Microarray Chip.

PubMed

Yamamura, Shohei; Yamada, Eriko; Kimura, Fukiko; Miyajima, Kumiko; Shigeto, Hajime

2017-10-21

A new single-cell microarray chip was designed and developed to separate and analyze single adherent and non-adherent cancer cells. The single-cell microarray chip is made of polystyrene with over 60,000 microchambers of 10 different size patterns (31-40 µm upper diameter, 11-20 µm lower diameter). A drop of suspension of adherent carcinoma (NCI-H1650) and non-adherent leukocyte (CCRF-CEM) cells was placed onto the chip, and single-cell occupancy of NCI-H1650 and CCRF-CEM was determined to be 79% and 84%, respectively. This was achieved by controlling the chip design and surface treatment. Analysis of protein expression in single NCI-H1650 and CCRF-CEM cells was performed on the single-cell microarray chip by multi-antibody staining. Additionally, with this system, we retrieved positive single cells from the microchambers by a micromanipulator. Thus, this system demonstrates the potential for easy and accurate separation and analysis of various types of single cells.

Visible light induced electropolymerization of suspended hydrogel bioscaffolds in a microfluidic chip.

PubMed

Li, Pan; Yu, Haibo; Liu, Na; Wang, Feifei; Lee, Gwo-Bin; Wang, Yuechao; Liu, Lianqing; Li, Wen Jung

2018-05-23

The development of microengineered hydrogels co-cultured with cells in vitro could advance in vivo bio-systems in both structural complexity and functional hierarchy, which holds great promise for applications in regenerative tissues or organs, drug discovery and screening, and bio-sensors or bio-actuators. Traditional hydrogel microfabrication technologies such as ultraviolet (UV) laser or multiphoton laser stereolithography and three-dimensional (3D) printing systems have advanced the development of 3D hydrogel micro-structures but need either expensive and complex equipment, or harsh material selection with limited photoinitiators. Herein, we propose a simple and flexible hydrogel microfabrication method based on a ubiquitous visible-light projection system combined with a custom-designed photosensitive microfluidic chip, to rapidly (typically several to tens of seconds) fabricate various two-dimensional (2D) hydrogel patterns and 3D hydrogel constructs. A theoretical layer-by-layer model that involves continuous polymerizing-delaminating-polymerizing cycles is presented to explain the polymerization and structural formation mechanism of hydrogels. A large area of hydrogel patterns was efficiently fabricated without the usage of costly laser systems or photoinitiators, i.e., a stereoscopic mesh-like hydrogel network with intersecting hydrogel micro-belts was fabricated via a series of dynamic-changing digital light projections. The pores and gaps of the hydrogel network are tunable, which facilitates the supply of nutrients and discharge of waste in the construction of 3D thick bio-models. Cell co-culture experiments showed the effective regulation of cell spreading by hydrogel scaffolds fabricated by the new method presented here. This visible light enabled hydrogel microfabrication method may provide new prospects for designing cell-based units for advanced biomedical studies, e.g., for 3D bio-models or bio-actuators in the future.

Programmable neural processing on a smartdust for brain-computer interfaces.

PubMed

Yuwen Sun; Shimeng Huang; Oresko, Joseph J; Cheng, Allen C

2010-10-01

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Label-free sensing of the binding state of MUC1 peptide and anti-MUC1 aptamer solution in fluidic chip by terahertz spectroscopy.

PubMed

Zhao, Xiang; Zhang, Mingkun; Wei, Dongshan; Wang, Yunxia; Yan, Shihan; Liu, Mengwan; Yang, Xiang; Yang, Ke; Cui, Hong-Liang; Fu, Weiling

2017-10-01

The aptamer and target molecule binding reaction has been widely applied for construction of aptasensors, most of which are labeled methods. In contrast, terahertz technology proves to be a label-free sensing tool for biomedical applications. We utilize terahertz absorption spectroscopy and molecular dynamics simulation to investigate the variation of binding-induced collective vibration of hydrogen bond network in a mixed solution of MUC1 peptide and anti-MUC1 aptamer. The results show that binding-induced alterations of hydrogen bond numbers could be sensitively reflected by the variation of terahertz absorption coefficients of the mixed solution in a customized fluidic chip. The minimal detectable concentration is determined as 1 pmol/μL, which is approximately equal to the optimal immobilized concentration of aptasensors.

An Ultralow-Power Sleep Spindle Detection System on Chip.

PubMed

Iranmanesh, Saam; Rodriguez-Villegas, Esther

2017-08-01

This paper describes a full system-on-chip to automatically detect sleep spindle events from scalp EEG signals. These events, which are known to play an important role on memory consolidation during sleep, are also characteristic of a number of neurological diseases. The operation of the system is based on a previously reported algorithm, which used the Teager energy operator, together with the Spectral Edge Frequency (SEF50) achieving more than 70% sensitivity and 98% specificity. The algorithm is now converted into a hardware analog based customized implementation in order to achieve extremely low levels of power. Experimental results prove that the system, which is fabricated in a 0.18 μm CMOS technology, is able to operate from a 1.25 V power supply consuming only 515 nW, with an accuracy that is comparable to its software counterpart.

A 260-340 GHz Dual Chip Frequency Tripler for THz Frequency Multiplier Chains

NASA Technical Reports Server (NTRS)

Maestrini, Alain; Tripon-Canseliet, Charlotte; Ward, John S.; Gill, John J.; Mehdi, Imran

2006-01-01

We designed and fabricated a fix-tuned balanced frequency tripler working in the 260-340 GHz band to be the first stage of a x3x3x3 multiplier chain to 2.7 THz. The design of a dual-chip version of this multiplier featuring an input splitter / output combiner as part of the input / output matching networks of both chips - with no degradation of the expected bandwidth and efficiency- will be presented.

LEGOS: Object-based software components for mission-critical systems. Final report, June 1, 1995--December 31, 1997

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1998-08-01

An estimated 85% of the installed base of software is a custom application with a production quantity of one. In practice, almost 100% of military software systems are custom software. Paradoxically, the marginal costs of producing additional units are near zero. So why hasn`t the software market, a market with high design costs and low productions costs evolved like other similar custom widget industries, such as automobiles and hardware chips? The military software industry seems immune to market pressures that have motivated a multilevel supply chain structure in other widget industries: design cost recovery, improve quality through specialization, and enablemore » rapid assembly from purchased components. The primary goal of the ComponentWare Consortium (CWC) technology plan was to overcome barriers to building and deploying mission-critical information systems by using verified, reusable software components (Component Ware). The adoption of the ComponentWare infrastructure is predicated upon a critical mass of the leading platform vendors` inevitable adoption of adopting emerging, object-based, distributed computing frameworks--initially CORBA and COM/OLE. The long-range goal of this work is to build and deploy military systems from verified reusable architectures. The promise of component-based applications is to enable developers to snap together new applications by mixing and matching prefabricated software components. A key result of this effort is the concept of reusable software architectures. A second important contribution is the notion that a software architecture is something that can be captured in a formal language and reused across multiple applications. The formalization and reuse of software architectures provide major cost and schedule improvements. The Unified Modeling Language (UML) is fast becoming the industry standard for object-oriented analysis and design notation for object-based systems. However, the lack of a standard real-time distributed object operating system, lack of a standard Computer-Aided Software Environment (CASE) tool notation and lack of a standard CASE tool repository has limited the realization of component software. The approach to fulfilling this need is the software component factory innovation. The factory approach takes advantage of emerging standards such as UML, CORBA, Java and the Internet. The key technical innovation of the software component factory is the ability to assemble and test new system configurations as well as assemble new tools on demand from existing tools and architecture design repositories.« less

Innovative Product Design Based on Comprehensive Customer Requirements of Different Cognitive Levels

PubMed Central

Zhao, Wu; Zheng, Yake; Wang, Rui; Wang, Chen

2014-01-01

To improve customer satisfaction in innovative product design, a topology structure of customer requirements is established and an innovative product approach is proposed. The topology structure provides designers with reasonable guidance to capture the customer requirements comprehensively. With the aid of analytic hierarchy process (AHP), the importance of the customer requirements is evaluated. Quality function deployment (QFD) is used to translate customer requirements into product and process design demands and pick out the technical requirements which need urgent improvement. In this way, the product is developed in a more targeted way to satisfy the customers. the theory of innovative problems solving (TRIZ) is used to help designers to produce innovative solutions. Finally, a case study of automobile steering system is used to illustrate the application of the proposed approach. PMID:25013862

Innovative product design based on comprehensive customer requirements of different cognitive levels.

PubMed

Li, Xiaolong; Zhao, Wu; Zheng, Yake; Wang, Rui; Wang, Chen

2014-01-01

To improve customer satisfaction in innovative product design, a topology structure of customer requirements is established and an innovative product approach is proposed. The topology structure provides designers with reasonable guidance to capture the customer requirements comprehensively. With the aid of analytic hierarchy process (AHP), the importance of the customer requirements is evaluated. Quality function deployment (QFD) is used to translate customer requirements into product and process design demands and pick out the technical requirements which need urgent improvement. In this way, the product is developed in a more targeted way to satisfy the customers. the theory of innovative problems solving (TRIZ) is used to help designers to produce innovative solutions. Finally, a case study of automobile steering system is used to illustrate the application of the proposed approach.

Development of a CMOS-compatible PCR chip: comparison of design and system strategies

NASA Astrophysics Data System (ADS)

Erill, Ivan; Campoy, Susana; Rus, José; Fonseca, Luis; Ivorra, Antoni; Navarro, Zenón; Plaza, José A.; Aguiló, Jordi; Barbé, Jordi

2004-11-01

In the last decade research in chips for DNA amplification through the polymerase chain reaction (PCR) has been relatively abundant, but has taken very diverse approaches, leaving little common ground for a straightforward comparison of results. Here we report the development of a line of PCR chips that is fully compatible with complementary-metal-oxide-semiconductor (CMOS) technology and its revealing use as a general platform to test and compare a wide range of experimental parameters involved in PCR-chip design and operation. Peltier-heated and polysilicon thin-film driven PCR chips have been produced and directly compared in terms of efficiency, speed and power consumption, showing that thin-film systems run faster and more efficiently than Peltier-based ones, but yield inferior PCR products. Serpentine-like chamber designs have also been compared with standard rectangular designs and with the here reported rhomboidal chamber shape, showing that serpentine-like chambers do not have detrimental effects in PCR efficiency when using non-flow-through schemes, and that chamber design has a strong impact on sample insertion/extraction yields. With an accurate temperature control (±0.2 °C) we have optimized reaction kinetics to yield sound PCR amplifications of 25 µl mixtures in 20 min and with 24.4 s cycle times, confirming that a titrated amount of bovine albumin serum (BSA, 2.5 µg µl-1) is essential to counteract polymerase adsorption at chip walls. The reported use of a CMOS-compatible technological process paves the way for an easy adaption to foundry requirements and for a scalable integration of electro-optic detection and control circuitry.

19 CFR 101.7 - Customs seal.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 19 Customs Duties 1 2010-04-01 2010-04-01 false Customs seal. 101.7 Section 101.7 Customs Duties U... GENERAL PROVISIONS § 101.7 Customs seal. (a) Design. According to the design furnished by the Department of the Treasury, the Customs seal of the United States shall consist of the seal of the Department of...

19 CFR 101.7 - Customs seal.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 19 Customs Duties 1 2011-04-01 2011-04-01 false Customs seal. 101.7 Section 101.7 Customs Duties U... GENERAL PROVISIONS § 101.7 Customs seal. (a) Design. According to the design furnished by the Department of the Treasury, the Customs seal of the United States shall consist of the seal of the Department of...

Effects of Platform Design on the Customer Experience in an Online Solar PV Marketplace

DOE Office of Scientific and Technical Information (OSTI.GOV)

OShaughnessy, Eric J; Margolis, Robert M; Leibowicz, Benjamin

Residential solar photovoltaic (PV) customers are increasingly buying PV systems in online marketplaces, where customers can compare multiple quotes from several installers on quote platforms. In this study, we use data from an online marketplace to explore how quote platform design affects customer experiences. We analyze how four design changes affected customer experiences in terms of factors such as prices. We find that three of the four design changes are associated with statistically significant and robust price reductions, even though none of the changes were implemented specifically to reduce prices. The results suggest that even seemingly small platform design changesmore » can affect PV customer experiences in online marketplaces.« less

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

GRAPE-5: A Special-Purpose Computer for N-Body Simulations

NASA Astrophysics Data System (ADS)

Kawai, Atsushi; Fukushige, Toshiyuki; Makino, Junichiro; Taiji, Makoto

2000-08-01

We have developed a special-purpose computer for gravitational many-body simulations, GRAPE-5. GRAPE-5 accelerates the force calculation which dominates the calculation cost of the simulation. All other calculations, such as the time integration of orbits, are performed on a general-purpose computer (host computer) connected to GRAPE-5. A GRAPE-5 board consists of eight custom pipeline chips (G5 chip) and its peak performance is 38.4 Gflops. GRAPE-5 is the successor of GRAPE-3. The differences between GRAPE-5 and GRAPE-3 are: (1) The newly developed G5 chip contains two pipelines operating at 80 MHz, while the GRAPE chip, which was used for GRAPE-3, had one at 20 MHz. The calculation speed of GRAPE-5 is 8-times faster than that of GRAPE-3. (2) The GRAPE-5 board adopted a PCI bus as the interface to the host computer instead of VME of GRAPE-3, resulting in a communication speed one order of magnitude faster. (3) In addition to the pure 1/r potential, the G5 chip can calculate forces with arbitrary cutoff functions, so that it can be applied to the Ewald or P3M methods. (4) The pairwise force calculated on GRAPE-5 is about 10-times more accurate than that on GRAPE-3. On one GRAPE-5 board, one timestep with a direct summation algorithm takes 14 (N/128 k)2 seconds. With the Barnes-Hut tree algorithm (theta = 0.75), one timestep can be done in 15 (N/106) seconds.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

Prototype detection unit for the CHIPS experiment

NASA Astrophysics Data System (ADS)

Pfützner, Maciej M.

2017-09-01

CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

ChIPpeakAnno: a Bioconductor package to annotate ChIP-seq and ChIP-chip data

PubMed Central

2010-01-01

Background Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) or ChIP followed by genome tiling array analysis (ChIP-chip) have become standard technologies for genome-wide identification of DNA-binding protein target sites. A number of algorithms have been developed in parallel that allow identification of binding sites from ChIP-seq or ChIP-chip datasets and subsequent visualization in the University of California Santa Cruz (UCSC) Genome Browser as custom annotation tracks. However, summarizing these tracks can be a daunting task, particularly if there are a large number of binding sites or the binding sites are distributed widely across the genome. Results We have developed ChIPpeakAnno as a Bioconductor package within the statistical programming environment R to facilitate batch annotation of enriched peaks identified from ChIP-seq, ChIP-chip, cap analysis of gene expression (CAGE) or any experiments resulting in a large number of enriched genomic regions. The binding sites annotated with ChIPpeakAnno can be viewed easily as a table, a pie chart or plotted in histogram form, i.e., the distribution of distances to the nearest genes for each set of peaks. In addition, we have implemented functionalities for determining the significance of overlap between replicates or binding sites among transcription factors within a complex, and for drawing Venn diagrams to visualize the extent of the overlap between replicates. Furthermore, the package includes functionalities to retrieve sequences flanking putative binding sites for PCR amplification, cloning, or motif discovery, and to identify Gene Ontology (GO) terms associated with adjacent genes. Conclusions ChIPpeakAnno enables batch annotation of the binding sites identified from ChIP-seq, ChIP-chip, CAGE or any technology that results in a large number of enriched genomic regions within the statistical programming environment R. Allowing users to pass their own annotation data such as a different Chromatin immunoprecipitation (ChIP) preparation and a dataset from literature, or existing annotation packages, such as GenomicFeatures and BSgenome, provides flexibility. Tight integration to the biomaRt package enables up-to-date annotation retrieval from the BioMart database. PMID:20459804

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Mechanical design optimization of a single-axis MOEMS accelerometer based on a grating interferometry cavity for ultrahigh sensitivity

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan; Yang, Guoguang

2016-08-01

The ultrahigh static displacement-acceleration sensitivity of a mechanical sensing chip is essential primarily for an ultrasensitive accelerometer. In this paper, an optimal design to implement to a single-axis MOEMS accelerometer consisting of a grating interferometry cavity and a micromachined sensing chip is presented. The micromachined sensing chip is composed of a proof mass along with its mechanical cantilever suspension and substrate. The dimensional parameters of the sensing chip, including the length, width, thickness and position of the cantilevers are evaluated and optimized both analytically and by finite-element-method (FEM) simulation to yield an unprecedented acceleration-displacement sensitivity. Compared with one of the most sensitive single-axis MOEMS accelerometers reported in the literature, the optimal mechanical design can yield a profound sensitivity improvement with an equal footprint area, specifically, 200% improvement in displacement-acceleration sensitivity with moderate resonant frequency and dynamic range. The modified design was microfabricated, packaged with the grating interferometry cavity and tested. The experimental results demonstrate that the MOEMS accelerometer with modified design can achieve the acceleration-displacement sensitivity of about 150μm/g and acceleration sensitivity of greater than 1500V/g, which validates the effectiveness of the optimal design.

The Design, Fabrication and Characterization of a Transparent Atom Chip

PubMed Central

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

Analog signal processing for optical coherence imaging systems

NASA Astrophysics Data System (ADS)

Xu, Wei

Optical coherence tomography (OCT) and optical coherence microscopy (OCM) are non-invasive optical coherence imaging techniques, which enable micron-scale resolution, depth resolved imaging capability. Both OCT and OCM are based on Michelson interferometer theory. They are widely used in ophthalmology, gastroenterology and dermatology, because of their high resolution, safety and low cost. OCT creates cross sectional images whereas OCM obtains en face images. In this dissertation, the design and development of three increasingly complicated analog signal processing (ASP) solutions for optical coherence imaging are presented. The first ASP solution was implemented for a time domain OCT system with a Rapid Scanning Optical Delay line (RSOD)-based optical signal modulation and logarithmic amplifier (Log amp) based demodulation. This OCT system can acquire up to 1600 A-scans per second. The measured dynamic range is 106dB at 200A-scan per second. This OCT signal processing electronics includes an off-the-shelf filter box with a Log amp circuit implemented on a PCB board. The second ASP solution was developed for an OCM system with synchronized modulation and demodulation and compensation for interferometer phase drift. This OCM acquired micron-scale resolution, high dynamic range images at acquisition speeds up to 45,000 pixels/second. This OCM ASP solution is fully custom designed on a perforated circuit board. The third ASP solution was implemented on a single 2.2 mm x 2.2 mm complementary metal oxide semiconductor (CMOS) chip. This design is expandable to a multiple channel OCT system. A single on-chip CMOS photodetector and ASP channel was used for coherent demodulation in a time domain OCT system. Cross-sectional images were acquired with a dynamic range of 76dB (limited by photodetector responsivity). When incorporated with a bump-bonded InGaAs photodiode with higher responsivity, the expected dynamic range is close to 100dB.

Proceedings of the Symposium on Frequency Control (36th Annual). 2-4 June 1982, Philadelphia, Pennsylvania,

DTIC Science & Technology

1982-01-01

we experience. e -- ------ ---------- ----- -.are invest natino the use of weiohted reflectors1 to aid in reducinq the sidelobe levels. ’eiohted...oscillator. With the appropriate investment in custom MOS devices, the entire DCXO, less the cry- stai, can be realized on two chips. It is the crystal that...and which is small enough to be incorporated within Filters Operating in the Fundemental Mode at silicon integrated circuits has been investigated

High Speed Imaging using Nanoprobe Arrays

DTIC Science & Technology

2010-06-23

Gotsmann and U. Dürig, Appl. Phys. Lett. 87, 194102 2005. 9 W. P. King, S. Saxena, B. A. Nelson, R. Pitchimani, and B. L. Weeks, Nano Lett. 6, 2145...microcantilevers with selective coatings has been applied as an artificial nose to recognize and characterize alcohol vapors either in a static mode...doped resistive heater. Fig. 4(c) shows a custom printed circuit board (PCB) to mount the array chip and a flexible ribbon cable for the electrical

Implant-supported fixed dental prostheses with CAD/CAM-fabricated porcelain crown and zirconia-based framework.

PubMed

Takaba, Masayuki; Tanaka, Shinpei; Ishiura, Yuichi; Baba, Kazuyoshi

2013-07-01

Recently, fixed dental prostheses (FDPs) with a hybrid structure of CAD/CAM porcelain crowns adhered to a CAD/CAM zirconia framework (PAZ) have been developed. The aim of this report was to describe the clinical application of a newly developed implant-supported FDP fabrication system, which uses PAZ, and to evaluate the outcome after a maximum application period of 36 months. Implants were placed in three patients with edentulous areas in either the maxilla or mandible. After the implant fixtures had successfully integrated with bone, gold-platinum alloy or zirconia custom abutments were first fabricated. Zirconia framework wax-up was performed on the custom abutments, and the CAD/CAM zirconia framework was prepared using the CAD/CAM system. Next, wax-up was performed on working models for porcelain crown fabrication, and CAD/CAM porcelain crowns were fabricated. The CAD/CAM zirconia frameworks and CAD/CAM porcelain crowns were bonded using adhesive resin cement, and the PAZ was cemented. Cementation of the implant superstructure improved the esthetics and masticatory efficiency in all patients. No undesirable outcomes, such as superstructure chipping, stomatognathic dysfunction, or periimplant bone resorption, were observed in any of the patients. PAZ may be a potential solution for ceramic-related clinical problems such as chipping and fracture and associated complicated repair procedures in implant-supported FDPs. © 2012 by the American College of Prosthodontists.

Effects of Platform Design on the Customer Experience in an Online Solar PV Marketplace

DOE Office of Scientific and Technical Information (OSTI.GOV)

OShaughnessy, Eric J.; Margolis, Robert M.; Leibowicz, Benjamin

We analyze a unique dataset of residential solar PV quotes offered in an online marketplace to understand how platform design changes affect customer outcomes. Three of the four design changes are associated with statistically significant and robust reductions in offer prices, though none of the policies were designed explicitly to reduce prices. The results suggest that even small changes in how prospective solar PV customers interact with installers can affect customer outcomes such as prices. Specifically, the four changes we evaluate are: 1) a customer map that shows potential new EnergySage registrants the locations of nearby customers; 2) a quotemore » cap that precludes more than seven installers from bidding on any one customer; 3) a price guidance feature that informs installers about competitive prices in the customer's market before they submit quotes; and 4) no pre-quote messaging to prohibit installers from contacting customers prior to offering quotes. We calculate descriptive statistics to investigate whether each design change accomplished its specific objectives. Then, we econometrically evaluate the impacts of the design changes on PV quote prices and purchase prices using a regression discontinuity approach.« less

Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

PubMed

Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

2013-03-11

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Qijian; Jia, Gaofeng; Hyten, David L.

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of largemore » scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad.« less

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean

DOE PAGES

Song, Qijian; Jia, Gaofeng; Hyten, David L.; ...

2015-08-28

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of largemore » scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad.« less

SNP Assay Development for Linkage Map Construction, Anchoring Whole-Genome Sequence, and Other Genetic and Genomic Applications in Common Bean.

PubMed

Song, Qijian; Jia, Gaofeng; Hyten, David L; Jenkins, Jerry; Hwang, Eun-Young; Schroeder, Steven G; Osorno, Juan M; Schmutz, Jeremy; Jackson, Scott A; McClean, Phillip E; Cregan, Perry B

2015-08-28

A total of 992,682 single-nucleotide polymorphisms (SNPs) was identified as ideal for Illumina Infinium II BeadChip design after sequencing a diverse set of 17 common bean (Phaseolus vulgaris L) varieties with the aid of next-generation sequencing technology. From these, two BeadChips each with >5000 SNPs were designed. The BARCBean6K_1 BeadChip was selected for the purpose of optimizing polymorphism among market classes and, when possible, SNPs were targeted to sequence scaffolds in the Phaseolus vulgaris 14× genome assembly with sequence lengths >10 kb. The BARCBean6K_2 BeadChip was designed with the objective of anchoring additional scaffolds and to facilitate orientation of large scaffolds. Analysis of 267 F2 plants from a cross of varieties Stampede × Red Hawk with the two BeadChips resulted in linkage maps with a total of 7040 markers including 7015 SNPs. With the linkage map, a total of 432.3 Mb of sequence from 2766 scaffolds was anchored to create the Phaseolus vulgaris v1.0 assembly, which accounted for approximately 89% of the 487 Mb of available sequence scaffolds of the Phaseolus vulgaris v0.9 assembly. A core set of 6000 SNPs (BARCBean6K_3 BeadChip) with high genotyping quality and polymorphism was selected based on the genotyping of 365 dry bean and 134 snap bean accessions with the BARCBean6K_1 and BARCBean6K_2 BeadChips. The BARCBean6K_3 BeadChip is a useful tool for genetics and genomics research and it is widely used by breeders and geneticists in the United States and abroad. Copyright © 2015 Song et al.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

DFM for maskmaking: design-aware flexible mask-defect analysis

NASA Astrophysics Data System (ADS)

Driessen, Frank A. J. M.; Westra, J.; Scheffer, M.; Kawakami, K.; Tsujimoto, E.; Yamaji, M.; Kawashima, T.; Hayashi, N.

2007-10-01

We present a novel software system that combines design intent as known by EDA designers with defect inspection results from the maskshop to analyze the severity of defects on photomasks. The software -named Takumi Design- Driven Defect Analyzer (TK-D3A)- analyzes defects by combining actions in the image domain with actions in the design domain and outputs amongst others flexible mask-repair decisions in production formats used by the maskshop. Furthermore, TK-D3A outputs clips of layout (GDS/OASIS) that can be viewed with its graphical user interface for easy review of the defects and associated repair decisions. As inputs the system uses reticle defect-inspection data (text and images) and the respective multi-layer design layouts with the definitions of criticalities. The system does not require confidential design data from IDM, Fabless Design House, or Foundry to be sent to the maskshop and it also has minimal impact on the maskshop's mode of operation. The output of TK-D3A is designed to realize value to the maskshop and its customers in the forms of: 1) improved yield, 2) reduction of delivery times of masks to customers, and 3) enhanced utilization of the maskshop's installed tool base. The system was qualified together with a major IDM on a large set of production reticles in the 90 and beyond-65 nm technology nodes of which results will be presented that show the benefits for maskmaking. The accuracy in detecting defects is extremely high. We show the system's capability to analyze defects well below the pixel resolution of all inspection tools used, as well as the capability to extract multiple types of transmission defects. All of these defects are analyzed design-criticality-aware by TK-D3A, resulting in a large fraction of defects that do not need to be repaired because they are located in non-critical or less-critical parts of the layout, or, more importantly, turn out to be repairable or negligible despite of originally being classified as unrepairable when no such criticality knowledge is used. Finally, we show that the runtimes of TK-D3A are relatively short, despite the fact that the system operates on full-chip designs.

Development of a Fully Integrated Lab-on-a-Chip Electrophoresis System for ExoMars and Future Astrobiology Missions

NASA Astrophysics Data System (ADS)

Willis, P. A.; Fisher, A.; Greer, F.; Grunthaner, F. J.; Hoppe, D.; Chiesl, T.; Mathies, R. A.; Rolland, J. P.

2009-04-01

This paper will describe current and future development efforts in lab-on-a-chip instrumentation for astrobiological investigations underway at JPL. We will begin with a discussion of the current technology status of our autonomous microfluidic capillary electrophoresis (μCE) system integrated with on-chip perfluoropolyether (PFPE) membrane valves and pumps [1], as part of the Urey Instrument. This work builds on the μCE system developed by Skelley et al. [2], but extends the system capability through the use of bio- and spaceflight-compatible PFPE-membrane valves rather than utilizing a PDMS-based approach. The ultimate goal of this μCE system is to perform ultrasensitive compositional and chiral analysis of amino acids in order to determine if Mars harbors signatures of past or present life. An autonomously functioning flight version of this instrument will examine extracts from the Martian regolith as part of the Pasteur Payload of the 2016 ExoMars astrobiology mission. The four-layer wafer stack design utilizes independent CE channels patterned in glass, along with a PFPE membrane, a pneumatic manifold layer, and a fluidic bus layer. Three pneumatically driven on-chip diaphragm valves placed in series are used to peristaltically pump reagents, buffers, and samples to and from capillary electrophoresis electrode well positions. Electrophoretic separation occurs in the all-glass channels near the base of the structure. The valve geometries and layouts in our integrated two-channel PFPE system have been optimized for valve sealing characteristics and uniform device spacing across the wafer surface. This paper will discuss current experimental development work in our research group involving further integration of functionality into an autonomous multi-channel system with no human intervention, enabling CE analysis upon a dried sample after receipt of a single pre-programmed instruction set from the user. The key structure under current development is an expanded sample handling bus, which performs on-chip derivitization of samples with fluorescent tags, serial sample dilutions, and mixing with standard samples for the purpose of data calibration. For laboratory general-purpose use, the wafer stack is mounted on a fluorescent microscope stage in a custom fixture, which interfaces the pneumatic and high voltage lines and has the capability for controlled atmosphere testing. Additionally, simulation work is also underway on a more complex six-channel system with additional functionality. A 3D SolidWorks model of this more highly integrated six-channel autonomous system capable of all expected instrument functionality is modeled using COMSOL FEMLAB multiphysics software to ensure that the integrated system will perform as desired aboard a roving Martian platform. FEMLAB simulations of μCE separations of relevant mixtures of amino acids have been performed using custom code written at JPL, which enables direct comparison of experimental and simulated data, as well as providing crucial engineering data, in particular, the electric field strengths present throughout the instrument during operation. Finally, a discussion of advanced instrument concepts under development at JPL for "next-generation" Urey-like astrobiology instrumentation will also be presented. References: 1. "Monolithic photolithographically patterned Fluorocur PFPE membrane valves and pumps for in situ planetary exploration", P. A. Willis, F. Greer, M. C. Lee, J. A. Smith, V. E. White, F. J. Grunthaner, J. J. Sprague, and J. P. Rolland, Lab Chip 8, 1024 (2008). 2. "Development and evaluation of a microdevice for amino acid biomarker detection and analysis on Mars" A. M. Skelley, J. R. Scherer, A. D. Aubrey, W. H. Grover, R. H. C. Ivester, P. Ehrenfreund, F. J. Grunthaner, J. L. Bada, R. A. Mathies, PNAS 102, 1041(2005).

Solving wood chip transport problems with computer simulation.

Treesearch

Dennis P. Bradley; Sharon A. Winsauer

1976-01-01

Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

Gas Sensor Test Chip

NASA Technical Reports Server (NTRS)

Buehler, M.; Ryan, M.

1995-01-01

A new test chip is being developed to characterize conducting polymers used in gas sensors. The chip, a seven-layer cofired alumina substrate with gold electrodes, contains 11 comb and U- bend test structures. These structures are designed to measure the sheet resistance, conduction anisotropy, and peripheral conduction of spin-coated films that are not subsequently patterned.

All over the Map: A Progress Report on the State Children's Health Insurance Program (CHIP).

ERIC Educational Resources Information Center

Edmunds, Margo; Teitelbaum, Martha; Gleason, Cassy

The State Children's Health Insurance Program (CHIP) was designed in 1997 to support working families by providing affordable, quality health coverage for their children in an efficient, effective, and coordinated way. This report examines the progress made in implementing CHIP nationwide. Information sources included the following: (1) federal…

Chronic Disease Risk Reduction with a Community-Based Lifestyle Change Programme

ERIC Educational Resources Information Center

Merrill, Ray M; Aldana, Steven G; Greenlaw, Roger L; Salberg, Audrey; Englert, Heike

2008-01-01

Objective To assess whether reduced health risks resulting from the Coronary Health Improvement Project (CHIP) persist through 18 months. Methods: The CHIP is a four-week health education course designed to help individuals reduce cardiovascular risk by improving nutrition and physical activity behaviors. Analyses were based on 211 CHIP enrollees,…

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

Chip morphology as a performance predictor during high speed end milling of soda lime glass

NASA Astrophysics Data System (ADS)

Bagum, M. N.; Konneh, M.; Abdullah, K. A.; Ali, M. Y.

2018-01-01

Soda lime glass has application in DNA arrays and lab on chip manufacturing. Although investigation revealed that machining of such brittle material is possible using ductile mode under controlled cutting parameters and tool geometry, it remains a challenging task. Furthermore, ability of ductile machining is usually assed through machined surface texture examination. Soda lime glass is a strain rate and temperature sensitive material. Hence, influence on attainment of ductile surface due to adiabatic heat generated during high speed end milling using uncoated tungsten carbide tool is investigated in this research. Experimental runs were designed using central composite design (CCD), taking spindle speed, feed rate and depth of cut as input variable and tool-chip contact point temperature (Ttc) and the surface roughness (Rt) as responses. Along with machined surface texture, Rt and chip morphology was examined to assess machinability of soda lime glass. The relation between Ttc and chip morphology was examined. Investigation showed that around glass transition temperature (Tg) ductile chip produced and subsequently clean and ductile final machined surface produced.

Speckle Free, Low Coherency, High Brightness, and High Pulse Speed Infrared Collimated Light Sources for Mid-IR Target Designator and Hyperspectral Imaging

DTIC Science & Technology

2007-10-31

designator and hyperspectral imaging 6. AUfHOR(S) Yee-LoyLam 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION DenseLight...DenseLight Semiconductors CONTENTS 1. Introduction 3 1.1 Overview of Project 3 1.2 Organization of Project 4 1.3 Target...Performance 4 2. SLED Chip Design and Fabrication Development 5 2.1 Organization of Design Stages 5 2.2 SLED Chip Design 6 2.3

A microfluidic device for evaluating the dynamics of the metabolism-dependent antioxidant activity of nutrients.

PubMed

Lee, Jungwoo; Choi, Jong-ryul; Ha, Sang Keun; Choi, Inwook; Lee, Seung Hwan; Kim, Donghyun; Choi, Nakwon; Sung, Jong Hwan

2014-08-21

Various food components are known for their health-promoting effects. However, their biochemical effects are generally evaluated in vitro, and their actual in vivo effect can vary significantly, depending on their metabolic profiles. To evaluate the effect of the liver metabolism on the antioxidant activity, we have developed a two-compartment microfluidic system that integrates the dynamics of liver metabolism and the subsequent antioxidant activity of food components. In the first compartment of the device, human liver enzyme fractions were immobilized inside a poly(ethylene glycol) diacrylate (PEGDA) hydrogel to mimic the liver metabolism. The radical scavenging activity was evaluated by the change of the 2,2-diphenyl-1-picrylhydrazyl (DPPH) absorbance in the second compartment. Reaction engineering and fluid mechanics principles were used to develop a simplified analytical model and a more complex finite element model, which were used to design the chip and determine the optimal flow conditions. For real-time measurements of the reaction on a chip, we developed a custom-made photospectrometer system with an LED light source. The developed microfluidic system showed a linear and dose-dependent antioxidant activity in response to increasing concentration of flavonoid. We also compared the antioxidant activity of flavonoid after various liver metabolic reactions. This microfluidic system can serve as a novel in vitro platform for predicting the antioxidant activity of various food components in a more physiologically realistic manner, as well as for studying the mechanism of action of such food components.

A smartphone-based chip-scale microscope using ambient illumination.

PubMed

Lee, Seung Ah; Yang, Changhuei

2014-08-21

Portable chip-scale microscopy devices can potentially address various imaging needs in mobile healthcare and environmental monitoring. Here, we demonstrate the adaptation of a smartphone's camera to function as a compact lensless microscope. Unlike other chip-scale microscopy schemes, this method uses ambient illumination as its light source and does not require the incorporation of a dedicated light source. The method is based on the shadow imaging technique where the sample is placed on the surface of the image sensor, which captures direct shadow images under illumination. To improve the image resolution beyond the pixel size, we perform pixel super-resolution reconstruction with multiple images at different angles of illumination, which are captured while the user is manually tilting the device around any ambient light source, such as the sun or a lamp. The lensless imaging scheme allows for sub-micron resolution imaging over an ultra-wide field-of-view (FOV). Image acquisition and reconstruction are performed on the device using a custom-built Android application, constructing a stand-alone imaging device for field applications. We discuss the construction of the device using a commercial smartphone and demonstrate the imaging capabilities of our system.

A smartphone-based chip-scale microscope using ambient illumination

PubMed Central

Lee, Seung Ah; Yang, Changhuei

2014-01-01

Portable chip-scale microscopy devices can potentially address various imaging needs in mobile healthcare and environmental monitoring. Here, we demonstrate the adaptation of a smartphone’s camera to function as a compact lensless microscope. Unlike other chip-scale microscopy schemes, this method uses ambient illumination as its light source and does not require the incorporation of a dedicated light source. The method is based on the shadow imaging technique where the sample is placed on the surface of the image sensor, which captures direct shadow images under illumination. To improve the imaging resolution beyond the pixel size, we perform pixel super-resolution reconstruction with multiple images at different angles of illumination, which are captured while the user is manually tilting the device around any ambient light source, such as the sun or a lamp. The lensless imaging scheme allows for sub-micron resolution imaging over an ultra-wide field-of-view (FOV). Image acquisition and reconstruction is performed on the device using a custom-built android application, constructing a stand-alone imaging device for field applications. We discuss the construction of the device using a commercial smartphone and demonstrate the imaging capabilities of our system. PMID:24964209

Patterning roadmap: 2017 prospects

NASA Astrophysics Data System (ADS)

Neisser, Mark

2017-06-01

Road mapping of semiconductor chips has been underway for over 20 years, first with the International Technology Roadmap for Semiconductors (ITRS) roadmap and now with the International Roadmap for Devices and Systems (IRDS) roadmap. The original roadmap was mostly driven bottom up and was developed to ensure that the large numbers of semiconductor producers and suppliers had good information to base their research and development on. The current roadmap is generated more top-down, where the customers of semiconductor chips anticipate what will be needed in the future and the roadmap projects what will be needed to fulfill that demand. The More Moore section of the roadmap projects that advanced logic will drive higher-resolution patterning, rather than memory chips. Potential solutions for patterning future logic nodes can be derived as extensions of `next-generation' patterning technologies currently under development. Advanced patterning has made great progress, and two `next-generation' patterning technologies, EUV and nanoimprint lithography, have potential to be in production as early as 2018. The potential adoption of two different next-generation patterning technologies suggests that patterning technology is becoming more specialized. This is good for the industry in that it lowers overall costs, but may lead to slower progress in extending any one patterning technology in the future.

Powerful timing generator using mono-chip timers: An application to pulsed nuclear magnetic resonance

NASA Astrophysics Data System (ADS)

Saint-Jalmes, Hervé; Barjhoux, Yves

1982-01-01

We present a 10 line-7 MHz timing generator built on a single board around two LSI timer chips interfaced to a 16-bit microcomputer. Once programmed from the host computer, this device is able to generate elaborate logic sequences on its 10 output lines without further interventions from the CPU. Powerful architecture introduces new possibilities over conventional memory-based timing simulators and word generators. Loop control on a given sequence of events, loop nesting, and various logic combinations can easily be implemented through a software interface, using a symbolic command language. Typical applications of such a device range from development, emulation, and test of integrated circuits, circuit boards, and communication systems to pulse-controlled instrumentation (radar, ultrasonic systems). A particular application to a pulsed Nuclear Magnetic Resonance (NMR) spectrometer is presented, along with customization of the device for generating four-channel radio-frequency pulses and the necessary sequence for subsequent data acquisition.

ImmunoChip Study Implicates Antigen Presentation to T Cells in Narcolepsy

PubMed Central

Kornum, Birgitte Rahbek; Kenny, Eimear E.; Trynka, Gosia; Einen, Mali; Rico, Tom J.; Lichtner, Peter; Dauvilliers, Yves; Arnulf, Isabelle; Lecendreux, Michel; Javidi, Sirous; Geisler, Peter; Mayer, Geert; Pizza, Fabio; Poli, Francesca; Plazzi, Giuseppe; Overeem, Sebastiaan; Lammers, Gert Jan; Kemlink, David; Sonka, Karel; Nevsimalova, Sona; Rouleau, Guy; Desautels, Alex; Montplaisir, Jacques; Frauscher, Birgit; Ehrmann, Laura; Högl, Birgit; Jennum, Poul; Bourgin, Patrice; Peraita-Adrados, Rosa; Iranzo, Alex; Bassetti, Claudio; Chen, Wei-Min; Concannon, Patrick; Thompson, Susan D.; Damotte, Vincent; Fontaine, Bertrand; Breban, Maxime; Gieger, Christian; Klopp, Norman; Deloukas, Panos; Wijmenga, Cisca; Hallmayer, Joachim; Onengut-Gumuscu, Suna; Rich, Stephen S.; Winkelmann, Juliane; Mignot, Emmanuel

2013-01-01

Recent advances in the identification of susceptibility genes and environmental exposures provide broad support for a post-infectious autoimmune basis for narcolepsy/hypocretin (orexin) deficiency. We genotyped loci associated with other autoimmune and inflammatory diseases in 1,886 individuals with hypocretin-deficient narcolepsy and 10,421 controls, all of European ancestry, using a custom genotyping array (ImmunoChip). Three loci located outside the Human Leukocyte Antigen (HLA) region on chromosome 6 were significantly associated with disease risk. In addition to a strong signal in the T cell receptor alpha (TRA@), variants in two additional narcolepsy loci, Cathepsin H (CTSH) and Tumor necrosis factor (ligand) superfamily member 4 (TNFSF4, also called OX40L), attained genome-wide significance. These findings underline the importance of antigen presentation by HLA Class II to T cells in the pathophysiology of this autoimmune disease. PMID:23459209

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

The GenoChip: A New Tool for Genetic Anthropology

PubMed Central

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G.; Greenspan, Bennett; Spencer Wells, R.

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project’s new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics. PMID:23666864

The GenoChip: a new tool for genetic anthropology.

PubMed

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G; Greenspan, Bennett; Spencer Wells, R

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project's new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics.

Development of a cleaning process for uranium chips machined with a glycol-water-borax coolant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taylor, P.A.

1984-12-01

A chip-cleaning process has been developed to remove the new glycol-water-borax coolant from oralloy chips. The process involves storing the freshly cut chips in Freon-TDF until they are cleaned, washing with water, and displacing the water with Freon-TDF. The wash water can be reused many times and still yield clean chips and then be added to the coolant to make up for evaporative losses. The Freon-TDF will be cycled by evaporation. The cleaning facility is currently being designed and should be operational by April 1985.

Microfluidic "thin chips" for chemical separations.

PubMed

Gaspar, Attila; Salgado, Marisol; Stevens, Schetema; Gomez, Frank A

2010-08-01

This paper describes the design, development and application of microfluidic "thin chips" fabricated from PDMS. Thin chips consist of multiple layers of PDMS chemically bonded onto each other. Unlike thicker PDMS chips that suffer from lack of sensitivity due to PDMS absorption in the VIS and UV range, the thinness of these chips allows for the detection of chromophoric species within the microchannel via an external fiber optics detection system. C18-modified reversed-phase silica particles are packed into the microchannel using a temporary taper created by a magnetic valve and separations using both pressure- and electrochromatographic-driven methods are detailed.

Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

ERIC Educational Resources Information Center

Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

2011-01-01

The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

Design and fabricate multi channel microfluidic mold on top of glass slide using SU-8

NASA Astrophysics Data System (ADS)

Azman, N. A. N.; Rajapaksha, R. D. A. A.; Uda, M. N. A.; Hashim, U.

2017-09-01

Microfluidic is the study of fluid in microscale. Microfluidics provides miniaturized fluidic networks for processing and analyzing liquids in the nanoliter to milliliter range. Microfluidic device comprises of some essential segments or structure that are micromixer, microchannel and microchamber. The SU-8 mold is known as the most used technique in microfluidic fabrication due to the characteristic of very gooey polymer that can be spread over a thickness. In this study, in order to reduce the fabrication cost, the development and fabrication of SU-8 mold is replace by using a glass plate instead of silicon wafer which is used in the previous research. We designed a microfluidic chip for use with an IDE sensors to conduct multiplex detection of multiple channels. The microfluidic chip was designed to include multiplex detection for pathogen that consists of multiple channels of simultaneous results. The multi-channel microfluidic chip was designed, including the fluid outlet and inlet. A multi-channel microfluidic chip was used for pathogen detection. This paper sum up the fabrication of lab SU-8 mold using glass slide.

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Feasibility study, software design, layout and simulation of a two-dimensional fast Fourier transform machine for use in optical array interferometry

NASA Technical Reports Server (NTRS)

Boriakoff, Valentin; Chen, Wei

1990-01-01

The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Exome-chip association analysis reveals an Asian-specific missense variant in PAX4 associated with type 2 diabetes in Chinese individuals.

PubMed

Cheung, Chloe Y Y; Tang, Clara S; Xu, Aimin; Lee, Chi-Ho; Au, Ka-Wing; Xu, Lin; Fong, Carol H Y; Kwok, Kelvin H M; Chow, Wing-Sun; Woo, Yu-Cho; Yuen, Michele M A; Hai, JoJo S H; Jin, Ya-Li; Cheung, Bernard M Y; Tan, Kathryn C B; Cherny, Stacey S; Zhu, Feng; Zhu, Tong; Thomas, G Neil; Cheng, Kar-Keung; Jiang, Chao-Qiang; Lam, Tai-Hing; Tse, Hung-Fat; Sham, Pak-Chung; Lam, Karen S L

2017-01-01

Genome-wide association studies (GWASs) have identified many common type 2 diabetes-associated variants, mostly at the intronic or intergenic regions. Recent advancements of exome-array genotyping platforms have opened up a novel means for detecting the associations of low-frequency or rare coding variants with type 2 diabetes. We conducted an exomechip association analysis to identify additional type 2 diabetes susceptibility variants in the Chinese population. An exome-chip association study was conducted by genotyping 5640 Chinese individuals from Hong Kong, using a custom designed exome array, the Asian Exomechip. Single variant association analysis was conducted on 77,468 single nucleotide polymorphisms (SNPs). Fifteen SNPs were subsequently genotyped for replication analysis in an independent Chinese cohort comprising 12,362 individuals from Guangzhou. A combined analysis involving 7189 cases and 10,813 controls was performed. In the discovery stage, an Asian-specific coding variant rs2233580 (p.Arg192His) in PAX4, and two variants at the known loci, CDKN2B-AS1 and KCNQ1, were significantly associated with type 2 diabetes with exome-wide significance (p discovery  < 6.45 × 10 -7 ). The risk allele (T) of PAX4 rs2233580 was associated with a younger age at diabetes diagnosis. This variant was replicated in an independent cohort and demonstrated a stronger association that reached genome-wide significance (p meta-analysis [p meta ] = 3.74 × 10 -15 ) in the combined analysis. We identified the association of a PAX4 Asian-specific missense variant rs2233580 with type 2 diabetes in an exome-chip association analysis, supporting the involvement of PAX4 in the pathogenesis of type 2 diabetes. Our findings suggest PAX4 is a possible effector gene of the 7q32 locus, previously identified from GWAS in Asians.

Optimal scan strategy for mega-pixel and kilo-gray-level OLED-on-silicon microdisplay.

PubMed

Ji, Yuan; Ran, Feng; Ji, Weigui; Xu, Meihua; Chen, Zhangjing; Jiang, Yuxi; Shen, Weixin

2012-06-10

The digital pixel driving scheme makes the organic light-emitting diode (OLED) microdisplays more immune to the pixel luminance variations and simplifies the circuit architecture and design flow compared to the analog pixel driving scheme. Additionally, it is easily applied in full digital systems. However, the data bottleneck becomes a notable problem as the number of pixels and gray levels grow dramatically. This paper will discuss the digital driving ability to achieve kilogray-levels for megapixel displays. The optimal scan strategy is proposed for creating ultra high gray levels and increasing light efficiency and contrast ratio. Two correction schemes are discussed to improve the gray level linearity. A 1280×1024×3 OLED-on-silicon microdisplay, with 4096 gray levels, is designed based on the optimal scan strategy. The circuit driver is integrated in the silicon backplane chip in the 0.35 μm 3.3 V-6 V dual voltage one polysilicon layer, four metal layers (1P4M) complementary metal-oxide semiconductor (CMOS) process with custom top metal. The design aspects of the optimal scan controller are also discussed. The test results show the gray level linearity of the correction schemes for the optimal scan strategy is acceptable by the human eye.

Rapid and simple half-quantitative measurement alpha-fetoprotein by poly(dimethylsiloxane) microfluidic chip immunochromatographic assay

NASA Astrophysics Data System (ADS)

Tong, Chao; Jin, Qinghui; Zhao, Jianlong

2008-03-01

In this article, a kind of microfluidic method based on MEMS technology combined with gold immunochromatographic assay (GICA) is developed and discussed. Compared to the traditional GICA, this method supplies us convenient, multi-channel, in-parallel, low cost and similar efficiency approach in the fields of alpha-fetopro-tei (AFP)detection. Firstly, we improved the adhesion between the model material SU-8 and Silicon wafer, optimized approaches of the fabrication of the SU-8 model systematically, and fabricate the PDMS micro fluid chip with good reproduction successfully. Secondly, Surface modification and antibody immobilization methods with the GICA on the PDMS micro fluid analysis chip are studied, we choose the PDMS material and transfer GICA to the PDMS micro fluid chip successfully after researching the antibody immobilization efficiency of different materials utilized in fabrication of the micro fluid chip. In order to improve the reaction efficiency of the immobilized antibody, we studied the characteristics of micro fluid without the gas drive, and the fluid velocity control in our design; we also design structure of grove to strengthen the ability of immobilizing the antibody. The stimulation of the structure shows that it achieves great improvement and experiments prove the design is feasible.

Novel 3D micromirror for miniature optical bio-robe SiOB assembly

NASA Astrophysics Data System (ADS)

Singh, Janak; Xu, Yingshun; Premachandran, C. S.; Jason, Teo Hui Siang; Chen, Nanguang

2008-02-01

This article presents design and development of a novel 3D micromirror for large deflection scanning application in invivo optical coherence tomography (OCT) bio-imaging probe. Overall mirror chip size is critical to reduce the diameter of the probe; however, mirror plate itself should not be less than 500 μm as smaller size means reducing the amount of light collected after scattering for OCT imaging. In this study, mirror chip sizes of 1 × 1 mm2 and 1.5 × 1.5 mm2 were developed with respectively 400 and 500 micrometer diameter mirror plates. The design includes electro thermal excitation mechanism in the same plane as mirror plate to achieve 3D free space scanning. Larger deflection requires longer actuators, which usually increase the overall size of the chip. To accommodate longer actuators and keep overall chip size same curved beam actuators are designed and integrated for micromirror scanning. Typical length of the actuators was 800 micrometer, which provided up to 17 degrees deflection. Deep reactive ion etching (DRIE) process module was used extensively to etch high aspect ratio structures and keep the total mirror chip size small.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Tracking Clouds with low cost GNSS chips aided by the Arduino platform

NASA Astrophysics Data System (ADS)

Hameed, Saji; Realini, Eugenio; Ishida, Shinya

2016-04-01

The Global Navigation Satellite System (GNSS) is a constellation of satellites that is used to provide geo-positioning services. Besides this application, the GNSS system is important for a wide range of scientific and civilian applications. For example, GNSS systems are routinely used in civilian applications such as surveying and scientific applications such as the study of crustal deformation. Another important scientific application of GNSS system is in meteorological research. Here it is mainly used to determine the total water vapour content of the troposphere, hereafter Precipitable Water Vapor (PWV). However, both GNSS receivers and software have prohibitively high price due to a variety of reasons. To overcome this somewhat artificial barrier we are exploring the use of low-cost GNSS receivers along with open source GNSS software for scientific research, in particular for GNSS meteorology research. To achieve this aim, we have developed a custom Arduino compatible data logging board that is able to operate together with a specific low-cost single frequency GNSS receiver chip from NVS Technologies AG. We have also developed an open-source software bundle that includes a new Arduino core for the Atmel324p chip, which is the main processor used in our custom logger. We have also developed software code that enables data collection, logging and parsing of the GNSS data stream. Additionally we have comprehensively evaluated the low power characteristics of the GNSS receiver and logger boards. Currently we are exploring the use of several openly source or free to use for research software to map GNSS delays to PWV. These include the open source goGPS (http://www.gogps-project.org/) and gLAB (http://gage.upc.edu/gLAB) and the openly available GAMIT software from Massachusetts Institute of Technology (MIT). We note that all the firmware and software developed as part of this project is available on an open source license.

Resonant Cavity Enhanced On-Chip Raman Spectrometer Array with Precisely Positioned Metallic Nano-Gaps for Single Molecule Detection

DTIC Science & Technology

2011-03-22

the nanogaps are engraved on. Simulations show that smaller diameters of the nanowires should provide higher enhancement factors for SERS signal...Inverted Microscope with lasers of wavelengths of 512 to 633 nm as the excitation source. The signal was collected and analyzed by a 50cm Spectrometer...the optical path which can selectively pass the Raman signals and reject the excitation lasers . Figure 2.12 Custom built Raman microscope for the

Imaging cytometry in a plastic ultra-mobile system

NASA Astrophysics Data System (ADS)

Martínez Vázquez, R.; Trotta, G.; Paturzo, M.; Volpe, A.; Bernava, G.; Basile, V.; Ancona, A.; Ferraro, P.; Fassi, I.; Osellame, R.

2017-03-01

We present a cost-effective and highly-portable plastic prototype that can be interfaced with a cell phone to implement an optofluidic imaging cytometry platform. It is based on a PMMA microfluidic chip that fits inside an opto-mechanical platform fabricated by a 3D printer. The fluorescence excitation and imaging is performed using the LED and the CMOS from the cell phone increasing the compactness of the system. A custom developed application is used to analyze the images and provide a value of particle concentration.

Preparation of high-quality planar FeRh thin films for in situ TEM investigations

NASA Astrophysics Data System (ADS)

Almeida, Trevor P.; McGrouther, Damien; Pivak, Yevheniy; Perez Garza, Hector Hugo; Temple, Rowan; Massey, Jamie; Marrows, Christopher H.; McVitie, Stephen

2017-10-01

The preparation of a planar FeRh thin film using a focused ion beam (FIB) secondary electron microscope (SEM) for the purpose of in situ transmission electron microscopy (TEM) is presented. A custom SEM stub with 45° faces allows for the transfer and milling of the sample on a TEM heating chip, whilst Fresnel imaging within the TEM revealed the presence of the magnetic domain walls, confirming the quality of the FIB-prepared sample.

On-chip generation of microbubbles as a practical technology for manufacturing contrast agents for ultrasonic imaging

PubMed Central

Hettiarachchi, Kanaka; Talu, Esra; Longo, Marjorie L.; Dayton, Paul A.; Lee, Abraham P.

2007-01-01

This paper presents a new manufacturing method to generate monodisperse microbubble contrast agents with polydispersity index (σ) values of <2% through microfluidic flow-focusing. Micron-sized lipid shell-based perfluorocarbon (PFC) gas microbubbles for use as ultrasound contrast agents were produced using this method. The poly(dimethylsiloxane) (PDMS)-based devices feature expanding nozzle geometry with a 7 μm orifice width, and are robust enough for consistent production of microbubbles with runtimes lasting several hours. With high-speed imaging, we characterized relationships between channel geometry, liquid flow rate Q, and gas pressure P in controlling bubble sizes. By a simple optimization of the channel geometry and Q and P, bubbles with a mean diameter of <5 μm can be obtained, ideal for various ultrasonic imaging applications. This method demonstrates the potential of microfluidics as an efficient means for custom-designing ultrasound contrast agents with precise size distributions, different gas compositions and new shell materials for stabilization, and for future targeted imaging and therapeutic applications. PMID:17389962

Combined "dual" absorption and fluorescence smartphone spectrometers.

PubMed

Arafat Hossain, Md; Canning, John; Ast, Sandra; Cook, Kevin; Rutledge, Peter J; Jamalipour, Abbas

2015-04-15

A combined "dual" absorption and fluorescence smartphone spectrometer is demonstrated. The optical sources used in the system are the white flash LED of the smartphone and an orthogonally positioned and interchangeable UV (λ_ex=370  nm) and blue (λ_ex=450  nm) LED. The dispersive element is a low-cost, nano-imprinted diffraction grating coated with Au. Detection over a 300 nm span with 0.42 nm/pixel resolution was carried out with the camera CMOS chip. By integrating the blue and UV excitation sources into the white LED circuitry, the entire system is self-contained within a 3D printed case and powered from the smartphone battery; the design can be scaled to add further excitation sources. Using a customized app, acquisition of absorption and fluorescence spectra are demonstrated using a blue-absorbing and green-emitting pH-sensitive amino-naphthalimide-based fluorescent probe and a UV-absorbing and blue-emitting Zn²⁺-sensitive fluoro-ionophore.

Wireless simultaneous stimulation-and-recording device to train cortical circuits in somatosensory cortex.

PubMed

Ramshur, John T; de Jongh Curry, Amy L; Waters, Robert S

2014-01-01

We describe for the first time the design, implementation, and testing of a telemetry controlled simultaneous stimulation and recording device (SRD) to deliver chronic intercortical microstimulation (ICMS) to physiologically identified sites in rat somatosensory cortex (SI) and test hypotheses that chronic ICMS strengthens interhemispheric pathways and leads to functional reorganization in the enhanced cortex. The SRD is a custom embedded device that uses the Cypress Semiconductor's programmable system on a chip (PSoC) that is remotely controlled via Bluetooth. The SRC can record single or multiunit responses from any two of 12 available inputs at 1-15 ksps per channel and simultaneously deliver stimulus pulses (0-255 μA; 10 V compliance) to two user selectable electrodes using monophasic, biphasic, or pseudophasic stimulation waveforms (duration: 0-5 ms, inter-phase interval: 0-5 ms, frequency: 0.1-5 s, delay: 0-10 ms). The SRD was bench tested and validated in vivo in a rat animal model.

Transforming Multidisciplinary Customer Requirements to Product Design Specifications

NASA Astrophysics Data System (ADS)

Ma, Xiao-Jie; Ding, Guo-Fu; Qin, Sheng-Feng; Li, Rong; Yan, Kai-Yin; Xiao, Shou-Ne; Yang, Guang-Wu

2017-09-01

With the increasing of complexity of complex mechatronic products, it is necessary to involve multidisciplinary design teams, thus, the traditional customer requirements modeling for a single discipline team becomes difficult to be applied in a multidisciplinary team and project since team members with various disciplinary backgrounds may have different interpretations of the customers' requirements. A new synthesized multidisciplinary customer requirements modeling method is provided for obtaining and describing the common understanding of customer requirements (CRs) and more importantly transferring them into a detailed and accurate product design specifications (PDS) to interact with different team members effectively. A case study of designing a high speed train verifies the rationality and feasibility of the proposed multidisciplinary requirement modeling method for complex mechatronic product development. This proposed research offersthe instruction to realize the customer-driven personalized customization of complex mechatronic product.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Design considerations for a roll crusher/splitter for woody biomass

Treesearch

Donald L. Sirois; Colin Ashmore

1986-01-01

The principal focus of biomass harvesting in the past has been the use of chipping systems to reduce a wide variety of woody materials down to small pieces for easier handling and transporting. However, chipping systems have several short comings that limit their operational environments. For example, a conventional chipping system might not be applicable for...

"Chips with Everything": A Laboratory Exercise for Comparing Subjective and Objective Measurements of Potato Chips

ERIC Educational Resources Information Center

Davies, Cathy

2005-01-01

The following laboratory exercise was designed to aid student understanding of the differences between subjective and objective measurements. Students assess the color and texture of different varieties of potato chip (crisps) by means of an intensity rating scale and a rank test and objectively with a colorimeter and texture analyzer. For data…

19 CFR 175.25 - Procedure at port of entry designated by petitioner.

Code of Federal Regulations, 2010 CFR

2010-04-01

... decision of the Commissioner of Customs, he shall refer the matter to the Commissioner of Customs for his... 19 Customs Duties 2 2010-04-01 2010-04-01 false Procedure at port of entry designated by petitioner. 175.25 Section 175.25 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND...

19 CFR 175.25 - Procedure at port of entry designated by petitioner.

Code of Federal Regulations, 2013 CFR

2013-04-01

... decision of the Commissioner of Customs, he shall refer the matter to the Commissioner of Customs for his... 19 Customs Duties 2 2013-04-01 2013-04-01 false Procedure at port of entry designated by petitioner. 175.25 Section 175.25 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND...

19 CFR 175.25 - Procedure at port of entry designated by petitioner.

Code of Federal Regulations, 2012 CFR

2012-04-01

... decision of the Commissioner of Customs, he shall refer the matter to the Commissioner of Customs for his... 19 Customs Duties 2 2012-04-01 2012-04-01 false Procedure at port of entry designated by petitioner. 175.25 Section 175.25 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND...

19 CFR 175.25 - Procedure at port of entry designated by petitioner.

Code of Federal Regulations, 2014 CFR

2014-04-01

... decision of the Commissioner of Customs, he shall refer the matter to the Commissioner of Customs for his... 19 Customs Duties 2 2014-04-01 2014-04-01 false Procedure at port of entry designated by petitioner. 175.25 Section 175.25 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND...

19 CFR 175.25 - Procedure at port of entry designated by petitioner.

Code of Federal Regulations, 2011 CFR

2011-04-01

... decision of the Commissioner of Customs, he shall refer the matter to the Commissioner of Customs for his... 19 Customs Duties 2 2011-04-01 2011-04-01 false Procedure at port of entry designated by petitioner. 175.25 Section 175.25 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND...

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, Wing C.

1994-01-01

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, W.C.

1994-02-15

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible. 63 figures.

SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture.

PubMed

Sripad, Athul; Sanchez, Giovanny; Zapata, Mireya; Pirrone, Vito; Dorta, Taho; Cambria, Salvatore; Marti, Albert; Krishnamourthy, Karthikeyan; Madrenas, Jordi

2018-01-01

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities. Copyright © 2017 Elsevier Ltd. All rights reserved.

A microfluidic thermometer: Precise temperature measurements in microliter- and nanoliter-scale volumes

PubMed Central

McKenzie, Brittney A.

2017-01-01

Measuring the temperature of a sample is a fundamental need in many biological and chemical processes. When the volume of the sample is on the microliter or nanoliter scale (e.g., cells, microorganisms, precious samples, or samples in microfluidic devices), accurate measurement of the sample temperature becomes challenging. In this work, we demonstrate a technique for accurately determining the temperature of microliter volumes using a simple 3D-printed microfluidic chip. We accomplish this by first filling “microfluidic thermometer” channels on the chip with substances with precisely known freezing/melting points. We then use a thermoelectric cooler to create a stable and linear temperature gradient along these channels within a measurement region on the chip. A custom software tool (available as online Supporting Information) is then used to find the locations of solid-liquid interfaces in the thermometer channels; these locations have known temperatures equal to the freezing/melting points of the substances in the channels. The software then uses the locations of these interfaces to calculate the temperature at any desired point within the measurement region. Using this approach, the temperature of any microliter-scale on-chip sample can be measured with an uncertainty of about a quarter of a degree Celsius. As a proof-of-concept, we use this technique to measure the unknown freezing point of a 50 microliter volume of solution and demonstrate its feasibility on a 400 nanoliter sample. Additionally, this technique can be used to measure the temperature of any on-chip sample, not just near-zero-Celsius freezing points. We demonstrate this by using an oil that solidifies near room temperature (coconut oil) in a microfluidic thermometer to measure on-chip temperatures well above zero Celsius. By providing a low-cost and simple way to accurately measure temperatures in small volumes, this technique should find applications in both research and educational laboratories. PMID:29284028

Design, Fabrication and Characterization of a Low-Impedance 3D Electrode Array System for Neuro-Electrophysiology

PubMed Central

Kusko, Mihaela; Craciunoiu, Florea; Amuzescu, Bogdan; Halitzchi, Ferdinand; Selescu, Tudor; Radoi, Antonio; Popescu, Marian; Simion, Monica; Bragaru, Adina; Ignat, Teodora

2012-01-01

Recent progress in patterned microelectrode manufacturing technology and microfluidics has opened the way to a large variety of cellular and molecular biosensor-based applications. In this extremely diverse and rapidly expanding landscape, silicon-based technologies occupy a special position, given their statute of mature, consolidated, and highly accessible areas of development. Within the present work we report microfabrication procedures and workflows for 3D patterned gold-plated microelectrode arrays (MEA) of different shapes (pyramidal, conical and high aspect ratio), and we provide a detailed characterization of their physical features during all the fabrication steps to have in the end a reliable technology. Moreover, the electrical performances of MEA silicon chips mounted on standardized connector boards via ultrasound wire-bonding have been tested using non-destructive electrochemical methods: linear sweep and cyclic voltammetry, impedance spectroscopy. Further, an experimental recording chamber package suitable for in vitro electrophysiology experiments has been realized using custom-design electronics for electrical stimulus delivery and local field potential recording, included in a complete electrophysiology setup, and the experimental structures have been tested on newborn rat hippocampal slices, yielding similar performance compared to commercially available MEA equipments. PMID:23208555

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Considerations on Experimental Design and Data Analysis of Chromatin Immunoprecipitation Experiments.

PubMed

Jordán-Pla, Antonio; Visa, Neus

2018-01-01

Arguably one of the most valuable techniques to study chromatin organization, ChIP is the method of choice to map the contacts established between proteins and genomic DNA. Ever since its inception, more than 30 years ago, ChIP has been constantly evolving, improving, and expanding its capabilities and reach. Despite its widespread use by many laboratories across a wide variety of disciplines, ChIP assays can be sometimes challenging to design, and are often sensitive to variations in practical implementation.In this chapter, we provide a general overview of the ChIP method and its most common variations, with a special focus on ChIP-seq. We try to address some of the most important aspects that need to be taken into account in order to design and perform experiments that generate the most reproducible, high-quality data. Some of the main topics covered include the use of properly characterized antibodies, alternatives to chromatin preparation, the need for proper controls, and some recommendations about ChIP-seq data analysis.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

High-power diode laser bars as pump sources for fiber lasers and amplifiers (Invited Paper)

NASA Astrophysics Data System (ADS)

Bonati, G.; Hennig, P.; Wolff, D.; Voelckel, H.; Gabler, T.; Krause, U.; T'nnermann, A.; Reich, M.; Limpert, J.; Werner, E.; Liem, A.

2005-04-01

Fiber lasers are pumped by fibercoupled, multimode single chip devices at 915nm. That"s what everybody assumes when asked for the type of fiber laser pumps and it was like this for many years. Coming up as an amplifier for telecom applications, the amount of pump power needed was in the range of several watts. Highest pump powers for a limited market entered the ten watts range. This is a range of power that can be covered by highly reliable multimode chips, that have to survive up to 25 years, e.g. in submarine applications. With fiber lasers entering the power range and the application fields of rod and thin disc lasers, the amount of pump power needed raised into the area of several hundred watts. In this area of pump power, usually bar based pumps are used. This is due to the much higher cost pressure of the industrial customers compared to telecom customers. We expect more then 70% of all industrial systems to be pumped by diode laser bars. Predictions that bar based pumps survive for just a thousand hours in cw-operation and fractions of this if pulsed are wrong. Bar based pumps have to perform on full power for 10.000h on Micro channel heat sinks and 20.000h on passive heatsinks in industrial applications, and they do. We will show a variety of data, "real" long time tests and statistics from the JENOPTIK Laserdiode as well as data of thousands of bars in the field, showing that bar based pumps are not just well suitable for industrial applications on high power levels, but even showing benefits compared to chip based pumps. And it"s reasonable, that the same objectives of cost effectiveness, power and lifetime apply as well to thin disc, rod and slab lasers as to fiber lasers. Due to the pumping of fiber lasers, examples will be shown, how to utilize bars for high brightness fiber coupling. In this area, the automation is on its way to reduce the costs on the fibercoupling, similar to what had been done in the single chip business. All these efforts are part of the JENOPTIK Laserdiode"s LongLifeTechnologie.

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

NASA Astrophysics Data System (ADS)

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

NASA Astrophysics Data System (ADS)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-07-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

Development of a versatile lab-on-a-chip enzyme assay platform for pathogen detection in CBRNE scenarios

NASA Astrophysics Data System (ADS)

Klemm, Richard; Schattschneider, Sebastian; Jahn, Tobias; Hlawatsch, Nadine; Julich, Sandra; Becker, Holger; Gärtner, Claudia

2013-05-01

The ability to integrate complete assays on a microfluidic chip helps to greatly simplify instrument requirements and allows the use of lab-on-a-chip technology in the field. A core application for such field-portable systems is the detection of pathogens in a CBRNE scenario such as permanent monitoring of airborne pathogens, e.g. in metro stations or hospitals etc. As one assay methodology for the pathogen identification, enzymatic assays were chosen. In order evaluate different detection strategies, the realized on-chip enzyme assay module has been designed as a general platform chip. In all application cases, the assays are based on immobilized probes located in microfluidic channels. Therefore a microfluidic chip was realized containing a set of three individually addressable channels, not only for detection of the sample itself also to have a set of references for a quantitative analysis. It furthermore includes two turning valves and a waste container for clear and sealed storage of potential pathogenic liquids to avoid contamination of the environment. All liquids remain in the chip and can be disposed of in proper way subsequently to the analysis. The chip design includes four inlet ports consisting of one sample port (Luer interface) and three mini Luer interfaces for fluidic support of e.g. washing buffer, substrate and enzyme solution. The sample can be applied via a special, sealable sampling vessel with integrated female Luer interface. Thereby also pre-anaytical contamination of the environment can be provided. Other reagents that are required for analysis will be stored off chip.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lab-on-a-Chip Design-Build Project with a Nanotechnology Component in a Freshman Engineering Course

ERIC Educational Resources Information Center

Allam, Yosef; Tomasko, David L.; Trott, Bruce; Schlosser, Phil; Yang, Yong; Wilson, Tiffany M.; Merrill, John

2008-01-01

A micromanufacturing lab-on-a-chip project with a nanotechnology component was introduced as an alternate laboratory in the required first-year engineering curriculum at The Ohio State University. Nanotechnology is introduced in related reading and laboratory tours as well as laboratory activities including a quarter-length design, build, and test…

Netlist Oriented Sensitivity Evaluation (NOSE)

DTIC Science & Technology

2017-03-01

developing methodologies to assess sensitivities of alternative chip design netlist implementations. The research is somewhat foundational in that such...Netlist-Oriented Sensitivity Evaluation (NOSE) project was to develop methodologies to assess sensitivities of alternative chip design netlist...analysis to devise a methodology for scoring the sensitivity of circuit nodes in a netlist and thus providing the raw data for any meaningful

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

NASA Astrophysics Data System (ADS)

Wu, Chang-Hsi; You, Hong-Cheng; Huang, Shun-Zhao

2018-02-01

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of -9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

Design and process development of a photonic crystal polymer biosensor for point-of-care diagnostics

NASA Astrophysics Data System (ADS)

Dortu, F.; Egger, H.; Kolari, K.; Haatainen, T.; Furjes, P.; Fekete, Z.; Bernier, D.; Sharp, G.; Lahiri, B.; Kurunczi, S.; Sanchez, J.-C.; Turck, N.; Petrik, P.; Patko, D.; Horvath, R.; Eiden, S.; Aalto, T.; Watts, S.; Johnson, N. P.; De La Rue, R. M.; Giannone, D.

2011-07-01

In this work, we report advances in the fabrication and anticipated performance of a polymer biosensor photonic chip developed in the European Union project P3SENS (FP7-ICT4-248304). Due to the low cost requirements of point-ofcare applications, the photonic chip is fabricated from nanocomposite polymeric materials, using highly scalable nanoimprint- lithography (NIL). A suitable microfluidic structure transporting the analyte solutions to the sensor area is also fabricated in polymer and adequately bonded to the photonic chip. We first discuss the design and the simulated performance of a high-Q resonant cavity photonic crystal sensor made of a high refractive index polyimide core waveguide on a low index polymer cladding. We then report the advances in doped and undoped polymer thin film processing and characterization for fabricating the photonic sensor chip. Finally the development of the microfluidic chip is presented in details, including the characterisation of the fluidic behaviour, the technological and material aspects of the 3D polymer structuring and the stable adhesion strategies for bonding the fluidic and the photonic chips, with regards to the constraints imposed by the bioreceptors supposedly already present on the sensors.

Chip-scale thermal management of high-brightness LED packages

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Weaver, Stanton

2004-10-01

The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of localized hot spots at the chip active layer. The importance of "zero defects" in one of the more popular interconnect schemes; the "epi down" soldered flip chip configuration is investigated and demonstrated.

Chip seal performance measures : best practices.

DOT National Transportation Integrated Search

2015-03-01

The Washington State Department of Transportation (WSDOT) has a long history of designing, constructing, : and maintaining chip seal or bituminous surface treatment pavements. However, to date WSDOT has not : developed pavement performance indicators...

Compact Multimedia Systems in Multi-chip Module Technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Alkalaj, Leon

1995-01-01

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

A Cost Effective System Design Approach for Critical Space Systems

NASA Technical Reports Server (NTRS)

Abbott, Larry Wayne; Cox, Gary; Nguyen, Hai

2000-01-01

NASA-JSC required an avionics platform capable of serving a wide range of applications in a cost-effective manner. In part, making the avionics platform cost effective means adhering to open standards and supporting the integration of COTS products with custom products. Inherently, operation in space requires low power, mass, and volume while retaining high performance, reconfigurability, scalability, and upgradability. The Universal Mini-Controller project is based on a modified PC/104-Plus architecture while maintaining full compatibility with standard COTS PC/104 products. The architecture consists of a library of building block modules, which can be mixed and matched to meet a specific application. A set of NASA developed core building blocks, processor card, analog input/output card, and a Mil-Std-1553 card, have been constructed to meet critical functions and unique interfaces. The design for the processor card is based on the PowerPC architecture. This architecture provides an excellent balance between power consumption and performance, and has an upgrade path to the forthcoming radiation hardened PowerPC processor. The processor card, which makes extensive use of surface mount technology, has a 166 MHz PowerPC 603e processor, 32 Mbytes of error detected and corrected RAM, 8 Mbytes of Flash, and I Mbytes of EPROM, on a single PC/104-Plus card. Similar densities have been achieved with the quad channel Mil-Std-1553 card and the analog input/output cards. The power management built into the processor and its peripheral chip allows the power and performance of the system to be adjusted to meet the requirements of the application, allowing another dimension to the flexibility of the Universal Mini-Controller. Unique mechanical packaging allows the Universal Mini-Controller to accommodate standard COTS and custom oversized PC/104-Plus cards. This mechanical packaging also provides thermal management via conductive cooling of COTS boards, which are typically designed for convection cooling methods.

19 CFR 115.7 - Designation of additional Certifying Authorities.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 19 Customs Duties 1 2011-04-01 2011-04-01 false Designation of additional Certifying Authorities. 115.7 Section 115.7 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARGO CONTAINER AND ROAD VEHICLE CERTIFICATION PURSUANT TO INTERNATIONAL CUSTOMS...

19 CFR 115.7 - Designation of additional Certifying Authorities.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 19 Customs Duties 1 2014-04-01 2014-04-01 false Designation of additional Certifying Authorities. 115.7 Section 115.7 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARGO CONTAINER AND ROAD VEHICLE CERTIFICATION PURSUANT TO INTERNATIONAL CUSTOMS...

19 CFR 115.7 - Designation of additional Certifying Authorities.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 19 Customs Duties 1 2010-04-01 2010-04-01 false Designation of additional Certifying Authorities. 115.7 Section 115.7 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARGO CONTAINER AND ROAD VEHICLE CERTIFICATION PURSUANT TO INTERNATIONAL CUSTOMS...

19 CFR 115.7 - Designation of additional Certifying Authorities.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 19 Customs Duties 1 2013-04-01 2013-04-01 false Designation of additional Certifying Authorities. 115.7 Section 115.7 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARGO CONTAINER AND ROAD VEHICLE CERTIFICATION PURSUANT TO INTERNATIONAL CUSTOMS...

19 CFR 115.7 - Designation of additional Certifying Authorities.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 19 Customs Duties 1 2012-04-01 2012-04-01 false Designation of additional Certifying Authorities. 115.7 Section 115.7 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARGO CONTAINER AND ROAD VEHICLE CERTIFICATION PURSUANT TO INTERNATIONAL CUSTOMS...

"Peak tracking chip" for label-free optical detection of bio-molecular interaction and bulk sensing.

PubMed

Bougot-Robin, Kristelle; Li, Shunbo; Zhang, Yinghua; Hsing, I-Ming; Benisty, Henri; Wen, Weijia

2012-10-21

A novel imaging method for bulk refractive index sensing or label-free bio-molecular interaction sensing is presented. This method is based on specially designed "Peak tracking chip" (PTC) involving "tracks" of adjacent resonant waveguide gratings (RWG) "micropads" with slowly evolving resonance position. Using a simple camera the spatial information robustly retrieves the diffraction efficiency, which in turn transduces either the refractive index of the liquids on the tracks or the effective thickness of an immobilized biological layer. Our intrinsically multiplex chip combines tunability and versatility advantages of dielectric guided wave biochips without the need of costly hyperspectral instrumentation. The current success of surface plasmon imaging techniques suggests that our chip proposal could leverage an untapped potential to routinely extend such techniques in a convenient and sturdy optical configuration toward, for instance for large analytes detection. PTC design and fabrication are discussed with challenging process to control micropads properties by varying their period (step of 2 nm) or their duty cycle through the groove width (steps of 4 nm). Through monochromatic imaging of our PTC, we present experimental demonstration of bulk index sensing on the range [1.33-1.47] and of surface biomolecule detection of molecular weight 30 kDa in aqueous solution using different surface densities. A sensitivity of the order of 10(-5) RIU for bulk detection and a sensitivity of the order of ∼10 pg mm(-2) for label-free surface detection are expected, therefore opening a large range of application of our chip based imaging technique. Exploiting and chip design, we expect as well our chip to open new direction for multispectral studies through imaging.

1H, 15N and 13C resonance assignments for free and IEEVD peptide-bound forms of the tetratricopeptide repeat domain from the human E3 ubiquitin ligase CHIP.

PubMed

Zhang, Huaqun; McGlone, Cameron; Mannion, Matthew M; Page, Richard C

2017-04-01

The ubiquitin ligase CHIP catalyzes covalent attachment of ubiquitin to unfolded proteins chaperoned by the heat shock proteins Hsp70/Hsc70 and Hsp90. CHIP interacts with Hsp70/Hsc70 and Hsp90 by binding of a C-terminal IEEVD motif found in Hsp70/Hsc70 and Hsp90 to the tetratricopeptide repeat (TPR) domain of CHIP. Although recruitment of heat shock proteins to CHIP via interaction with the CHIP-TPR domain is well established, alterations in structure and dynamics of CHIP upon binding are not well understood. In particular, the absence of a structure for CHIP-TPR in the free form presents a significant limitation upon studies seeking to rationally design inhibitors that may disrupt interactions between CHIP and heat shock proteins. Here we report the 1 H, 13 C, and 15 N backbone and side chain chemical shift assignments for CHIP-TPR in the free form, and backbone chemical shift assignments for CHIP-TPR in the IEEVD-bound form. The NMR resonance assignments will enable further studies examining the roles of dynamics and structure in regulating interactions between CHIP and the heat shock proteins Hsp70/Hsc70 and Hsp90.

Software synthesis using generic architectures

NASA Technical Reports Server (NTRS)

Bhansali, Sanjay

1993-01-01

A framework for synthesizing software systems based on abstracting software system designs and the design process is described. The result of such an abstraction process is a generic architecture and the process knowledge for customizing the architecture. The customization process knowledge is used to assist a designer in customizing the architecture as opposed to completely automating the design of systems. Our approach using an implemented example of a generic tracking architecture which was customized in two different domains is illustrated. How the designs produced using KASE compare to the original designs of the two systems, and current work and plans for extending KASE to other application areas are described.

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

NASA Astrophysics Data System (ADS)

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

PubMed Central

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

CEM-designer: design of custom expression microarrays in the post-ENCODE Era.

PubMed

Arnold, Christian; Externbrink, Fabian; Hackermüller, Jörg; Reiche, Kristin

2014-11-10

Microarrays are widely used in gene expression studies, and custom expression microarrays are popular to monitor expression changes of a customer-defined set of genes. However, the complexity of transcriptomes uncovered recently make custom expression microarray design a non-trivial task. Pervasive transcription and alternative processing of transcripts generate a wealth of interweaved transcripts that requires well-considered probe design strategies and is largely neglected in existing approaches. We developed the web server CEM-Designer that facilitates microarray platform independent design of custom expression microarrays for complex transcriptomes. CEM-Designer covers (i) the collection and generation of a set of unique target sequences from different sources and (ii) the selection of a set of sensitive and specific probes that optimally represents the target sequences. Probe design itself is left to third party software to ensure that probes meet provider-specific constraints. CEM-Designer is available at http://designpipeline.bioinf.uni-leipzig.de. Copyright © 2014 Elsevier B.V. All rights reserved.

Design of customer knowledge management system for Aglaonema Nursery in South Tangerang, Indonesia

NASA Astrophysics Data System (ADS)

Sugiarto, D.; Mardianto, I.; Dewayana, TS; Khadafi, M.

2017-12-01

The purpose of this paper is to describe the design of customer knowledge management system to support customer relationship management activities for an aglaonema nursery in South Tangerang, Indonesia. System. The steps were knowledge identification (knowledge about customer, knowledge from customer, knowledge for customer), knowledge capture, codification, analysis of system requirement and create use case and activity diagram. The result showed that some key knowledge were about supporting customer in plant care (know how) and types of aglaonema including with the prices (know what). That knowledge for customer then codified and shared in knowledge portal website integrated with social media. Knowledge about customer were about customers and their behaviour in purchasing aglaonema. Knowledge from customer were about feedback, favorite and customer experience. Codified knowledge were placed and shared using content management system based on wordpress.

Gaining customer knowledge: obtaining and using customer judgments for hospitalwide quality improvement.

PubMed

Nelson, E C; Caldwell, C; Quinn, D; Rose, R

1991-03-01

Customer knowledge is an essential feature of hospitalwide quality improvement. All systems and processes have customers. The aim is to use customer knowledge and voice of the customer measurement to plan, design, improve, and monitor these systems and processes continuously. In this way, the hospital stands the best chance of meeting customers' needs and, hopefully, delivering services that are so outstanding that customers will be surprised and delighted. There are many methods, both soft and hard, that can be used to increase customer knowledge. One useful strategy is to use a family of quality measures that reflect the voice of the customer. These measures can generate practical and powerful customer knowledge information that is essential to performing strategic planning, deploying quality policy, designing new services, finding targets for improvements, and monitoring those continuous improvements based on customers' judgments.

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

PubMed

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

PubMed Central

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

2015-01-01

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Spectral Demultiplexing in Holographic and Fluorescent On-chip Microscopy

NASA Astrophysics Data System (ADS)

Sencan, Ikbal; Coskun, Ahmet F.; Sikora, Uzair; Ozcan, Aydogan

2014-01-01

Lensfree on-chip imaging and sensing platforms provide compact and cost-effective designs for various telemedicine and lab-on-a-chip applications. In this work, we demonstrate computational solutions for some of the challenges associated with (i) the use of broadband, partially-coherent illumination sources for on-chip holographic imaging, and (ii) multicolor detection for lensfree fluorescent on-chip microscopy. Specifically, we introduce spectral demultiplexing approaches that aim to digitally narrow the spectral content of broadband illumination sources (such as wide-band light emitting diodes or even sunlight) to improve spatial resolution in holographic on-chip microscopy. We also demonstrate the application of such spectral demultiplexing approaches for wide-field imaging of multicolor fluorescent objects on a chip. These computational approaches can be used to replace e.g., thin-film interference filters, gratings or other optical components used for spectral multiplexing/demultiplexing, which can form a desirable solution for cost-effective and compact wide-field microscopy and sensing needs on a chip.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Isolation of circulating tumor cells using a microvortex-generating herringbone-chip.

PubMed

Stott, Shannon L; Hsu, Chia-Hsien; Tsukrov, Dina I; Yu, Min; Miyamoto, David T; Waltman, Belinda A; Rothenberg, S Michael; Shah, Ajay M; Smas, Malgorzata E; Korir, George K; Floyd, Frederick P; Gilman, Anna J; Lord, Jenna B; Winokur, Daniel; Springer, Simeon; Irimia, Daniel; Nagrath, Sunitha; Sequist, Lecia V; Lee, Richard J; Isselbacher, Kurt J; Maheswaran, Shyamala; Haber, Daniel A; Toner, Mehmet

2010-10-26

Rare circulating tumor cells (CTCs) present in the bloodstream of patients with cancer provide a potentially accessible source for detection, characterization, and monitoring of nonhematological cancers. We previously demonstrated the effectiveness of a microfluidic device, the CTC-Chip, in capturing these epithelial cell adhesion molecule (EpCAM)-expressing cells using antibody-coated microposts. Here, we describe a high-throughput microfluidic mixing device, the herringbone-chip, or "HB-Chip," which provides an enhanced platform for CTC isolation. The HB-Chip design applies passive mixing of blood cells through the generation of microvortices to significantly increase the number of interactions between target CTCs and the antibody-coated chip surface. Efficient cell capture was validated using defined numbers of cancer cells spiked into control blood, and clinical utility was demonstrated in specimens from patients with prostate cancer. CTCs were detected in 14 of 15 (93%) patients with metastatic disease (median = 63 CTCs/mL, mean = 386 ± 238 CTCs/mL), and the tumor-specific TMPRSS2-ERG translocation was readily identified following RNA isolation and RT-PCR analysis. The use of transparent materials allowed for imaging of the captured CTCs using standard clinical histopathological stains, in addition to immunofluorescence-conjugated antibodies. In a subset of patient samples, the low shear design of the HB-Chip revealed microclusters of CTCs, previously unappreciated tumor cell aggregates that may contribute to the hematogenous dissemination of cancer.

Design and fabrication of a micron scale free-standing specimen for uniaxial micro-tensile tests

NASA Astrophysics Data System (ADS)

Tang, Jun; Wang, Hong; Li, Shi Chen; Liu, Rui; Mao, Sheng Ping; Li, Xue Ping; Zhang, Cong Chun; Ding, Guifu

2009-10-01

This paper presents a novel design and fabrication of test chips with a nickel free-standing specimen for the micro uniaxial tensile test. To fabricate test chips on the quartz substrate significantly reduces the fabrication time, minimizes the number of steps and eliminates the effect of the wet anisotropic etching process on mechanical properties. The test chip can be gripped tightly to the test machine and aligned accurately in the pulling direction; furthermore, the approximately straight design of the specimen rather than the traditional dog-bone structure enables the strain be directly measured by a displacement sensor. Both finite-element method (FEM) analysis and experimental results indicate the reliability of the new design. The test chip can also be extended to other materials. The experimental measured Young's modulus of a thin nickel film and the ultimate tensile strength are approximately 94.5 Gpa and 1.76 Gpa, respectively. The results were substantially supported by the experiment on larger gauge specimens by a commercial dynamic mechanical analysis (DMA) instrument. These specimens were electroplated under the same conditions. The low Young's modulus and the high ultimate tensile strength might be explained by the fine grain in the electroplated structure.

GeneChip{sup {trademark}} screening assay for cystic fibrosis mutations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cronn, M.T.; Miyada, C.G.; Fucini, R.V.

1994-09-01

GeneChip{sup {trademark}} assays are based on high density, carefully designed arrays of short oligonucleotide probes (13-16 bases) built directly on derivatized silica substrates. DNA target sequence analysis is achieved by hybridizing fluorescently labeled amplification products to these arrays. Fluorescent hybridization signals located within the probe array are translated into target sequence information using the known probe sequence at each array feature. The mutation screening assay for cystic fibrosis includes sets of oligonucleotide probes designed to detect numerous different mutations that have been described in 14 exons and one intron of the CFTR gene. Each mutation site is addressed by amore » sub-array of at least 40 probe sequences, half designed to detect the wild type gene sequence and half designed to detect the reported mutant sequence. Hybridization with homozygous mutant, homozygous wild type or heterozygous targets results in distinctive hybridization patterns within a sub-array, permitting specific discrimination of each mutation. The GeneChip probe arrays are very small (approximately 1 cm{sup 2}). There miniature size coupled with their high information content make GeneChip probe arrays a useful and practical means for providing CF mutation analysis in a clinical setting.« less

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

NASA Astrophysics Data System (ADS)

Gabor, Allen H.; Brendler, Andrew C.; Brunner, Timothy A.; Chen, Xuemei; Culp, James A.; Levinson, Harry J.

2018-03-01

The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term "EPE" has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of "Good Fields"1 and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma "value" design-rules need to be tested to ensure high yield. The "value" can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement error distributions and appropriate design-rule setting. While CD distributions with long tails coming from stochastic effects do bring increased risk of failure (especially on chips that may have over a billion failure opportunities per layer) there are other sources of variation that have sharp cutoffs, i.e. have no tails. We will review these sources and show how distributions with different skew and kurtosis values combine.

HPLC-Chip/MS Technology in Proteomic Profiling

NASA Astrophysics Data System (ADS)

Vollmer, Martin; van de Goor, Tom

HPLC-chip/MS is a novel nanoflow analytical technology conducted on a microfabricated chip that allows for highly efficient HPLC separation and superior sensitive MS detection of complex proteomic mixtures. This is possible through on-chip preconcentration and separation with fluidic connection made automatically in a leak-tight fashion. Minimum precolumn and postcolumn peak dispersion and uncompromised ease of use result in compounds eluting in bands of only a few nanoliters. The chip is fabricated out of bio-inert polyimide-containing channels and integrated chip structures, such as an electrospray emitter, columns, and frits manufactured by laser ablation technology. Meanwhile, a variety of HPLC-chips differing in design and stationary phase are commercially available, which provide a comprehensive solution for applications in proteomics, glycomics, biomarker, and pharmaceutical discovery. The HPLC-chip can also be easily integrated into a multidimensional separation workflow where different orthogonal separation techniques are combined to solve a highly complex separation problems. In this chapter, we describe in detail the methodological chip usage and functionality and its application in the elucidation of the protein profile of human nucleoli.

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

DTIC Science & Technology

2009-05-01

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications Gilbert Hendry†, Shoaib Kamil‡?, Aleksandr Biberman†, Johnnie...electronic networks -on-chip warrants investigating real application traces on functionally compa- rable photonic and electronic network designs. We... network can achieve 75× improvement in energy ef- ficiency for synthetic benchmarks and up to 37× improve- ment for real scientific applications

19 CFR 125.23 - Failure to designate.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 19 Customs Duties 1 2013-04-01 2013-04-01 false Failure to designate. 125.23 Section 125.23 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARTAGE AND LIGHTERAGE OF MERCHANDISE Importers' Cartage § 125.23 Failure to designate. If an...

19 CFR 125.23 - Failure to designate.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 19 Customs Duties 1 2014-04-01 2014-04-01 false Failure to designate. 125.23 Section 125.23 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARTAGE AND LIGHTERAGE OF MERCHANDISE Importers' Cartage § 125.23 Failure to designate. If an...

19 CFR 125.23 - Failure to designate.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 19 Customs Duties 1 2011-04-01 2011-04-01 false Failure to designate. 125.23 Section 125.23 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARTAGE AND LIGHTERAGE OF MERCHANDISE Importers' Cartage § 125.23 Failure to designate. If an...

19 CFR 125.23 - Failure to designate.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 19 Customs Duties 1 2010-04-01 2010-04-01 false Failure to designate. 125.23 Section 125.23 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT OF THE TREASURY CARTAGE AND LIGHTERAGE OF MERCHANDISE Importers' Cartage § 125.23 Failure to designate. If an...

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

NASA Astrophysics Data System (ADS)

Zhou, Chenyi; Lu, Zhenghao; Gu, Jiangmin; Yu, Xiaopeng

2017-10-01

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices. Project supported by the National Natural Science Foundation of China (No. 61574125) and the Industry Innovation Project of Suzhou City of China (No. SYG201641).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

NASA Technical Reports Server (NTRS)

Lue, Jaw-Chyng L.; Fang, Wai-Chi

2006-01-01

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

Tailoring microfluidic systems for organ-like cell culture applications using multiphysics simulations

NASA Astrophysics Data System (ADS)

Hagmeyer, Britta; Schütte, Julia; Böttger, Jan; Gebhardt, Rolf; Stelzle, Martin

2013-03-01

Replacing animal testing with in vitro cocultures of human cells is a long-term goal in pre-clinical drug tests used to gain reliable insight into drug-induced cell toxicity. However, current state-of-the-art 2D or 3D cell cultures aiming at mimicking human organs in vitro still lack organ-like morphology and perfusion and thus organ-like functions. To this end, microfluidic systems enable construction of cell culture devices which can be designed to more closely resemble the smallest functional unit of organs. Multiphysics simulations represent a powerful tool to study the various relevant physical phenomena and their impact on functionality inside microfluidic structures. This is particularly useful as it allows for assessment of system functions already during the design stage prior to actual chip fabrication. In the HepaChip®, dielectrophoretic forces are used to assemble human hepatocytes and human endothelial cells in liver sinusoid-like structures. Numerical simulations of flow distribution, shear stress, electrical fields and heat dissipation inside the cell assembly chambers as well as surface wetting and surface tension effects during filling of the microchannel network supported the design of this human-liver-on-chip microfluidic system for cell culture applications. Based on the device design resulting thereof, a prototype chip was injection-moulded in COP (cyclic olefin polymer). Functional hepatocyte and endothelial cell cocultures were established inside the HepaChip® showing excellent metabolic and secretory performance.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Development of a Plastic-Based Microfluidic Immunosensor Chip for Detection of H1N1 Influenza

PubMed Central

Lee, Kyoung G.; Lee, Tae Jae; Jeong, Soon Woo; Choi, Ho Woon; Heo, Nam Su; Park, Jung Youn; Park, Tae Jung; Lee, Seok Jae

2012-01-01

Lab-on-a-chip can provide convenient and accurate diagnosis tools. In this paper, a plastic-based microfluidic immunosensor chip for the diagnosis of swine flu (H1N1) was developed by immobilizing hemagglutinin antigen on a gold surface using a genetically engineered polypeptide. A fluorescent dye-labeled antibody (Ab) was used for quantifying the concentration of Ab in the immunosensor chip using a fluorescent technique. For increasing the detection efficiency and reducing the errors, three chambers and three microchannels were designed in one microfluidic chip. This protocol could be applied to the diagnosis of other infectious diseases in a microfluidic device. PMID:23112630

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

NASA Astrophysics Data System (ADS)

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Cardile, Paolo; Daly, Aidan; Carroll, Lee; O'Brien, Peter

2017-02-01

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

PubMed

Nose, Atsushi; Yamazaki, Tomohiro; Katayama, Hironobu; Uehara, Shuji; Kobayashi, Masatsugu; Shida, Sayaka; Odahara, Masaki; Takamiya, Kenichi; Matsumoto, Shizunori; Miyashita, Leo; Watanabe, Yoshihiro; Izawa, Takashi; Muramatsu, Yoshinori; Nitta, Yoshikazu; Ishikawa, Masatoshi

2018-04-24

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Effect of a grocery store intervention on sales of nutritious foods to youth and their families.

PubMed

Holmes, Ashley S; Estabrooks, Paul A; Davis, George C; Serrano, Elena L

2012-06-01

Grocery stores represent a unique opportunity to initiate nutrition interventions. The aim of this study was to develop and evaluate a 12-week, child-focused intervention at one grocery store. An observational uninterrupted time-series design was implemented from May to September 2009. The Healthy Kids campaign consisted of a point-of-purchase kiosk featuring fruits, vegetables, and healthy snacks as well as a sampling pod comprised of food items from the kiosk. Data collection included changes in sales for featured products; observations of customers at the kiosk/intervention; and brief questionnaires for customers who engaged with the kiosk. Descriptive statistics were computed for questionnaire responses and observational data. Correlational analyses were conducted to identify potential predictors of engagement. Sales data were analyzed using analysis of variance. Results showed an overall increase in the proportion of sales of the featured items to total store sales during the intervention period (P<0.05). Individual items that increased sales during the intervention period included whole-wheat bagels, bananas, radishes, honey, sunflower seeds, baked tortilla chips, and almond butter (P<0.05). Almost two thirds (61.7%) of the patrons interviewed noticed the Healthy Kids kiosk, with about one quarter (28.7%) indicating that they purchased at least one item. Fifty-eight percent reported that the kiosk encouraged them to buy healthier foods. Copyright © 2012 Academy of Nutrition and Dietetics. Published by Elsevier Inc. All rights reserved.

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Investigation of image distortion due to MCP electronic readout misalignment and correction via customized GUI application

NASA Astrophysics Data System (ADS)

Vitucci, G.; Minniti, T.; Tremsin, A. S.; Kockelmann, W.; Gorini, G.

2018-04-01

The MCP-based neutron counting detector is a novel device that allows high spatial resolution and time-resolved neutron radiography and tomography with epithermal, thermal and cold neutrons. Time resolution is possible by the high readout speeds of ~ 1200 frames/sec, allowing high resolution event counting with relatively high rates without spatial resolution degradation due to event overlaps. The electronic readout is based on a Timepix sensor, a CMOS pixel readout chip developed at CERN. Currently, a geometry of a quad Timepix detector is used with an active format of 28 × 28 mm2 limited by the size of the Timepix quad (2 × 2 chips) readout. Measurements of a set of high-precision micrometers test samples have been performed at the Imaging and Materials Science & Engineering (IMAT) beamline operating at the ISIS spallation neutron source (U.K.). The aim of these experiments was the full characterization of the chip misalignment and of the gaps between each pad in the quad Timepix sensor. Such misalignment causes distortions of the recorded shape of the sample analyzed. We present in this work a post-processing image procedure that considers and corrects these effects. Results of the correction will be discussed and the efficacy of this method evaluated.

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

NASA Astrophysics Data System (ADS)

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

NASA Astrophysics Data System (ADS)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

Capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection

NASA Astrophysics Data System (ADS)

Yang, Hao; Deng, Min; Ga, Shan; Chen, Shouhui; Kang, Lin; Wang, Junhong; Xin, Wenwen; Zhang, Tao; You, Zherong; An, Yuan; Wang, Jinglin; Cui, Daxiang

2014-03-01

Herein, we firstly demonstrate the design and the proof-of-concept use of a capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection. The micropillar array substrate was etched and coated with a gold film by microelectromechanical systems (MEMS) process to integrate into a lateral flow test strip. The detection of abrin solutions of various concentrations was performed by the as-prepared microfluidic chip. It was shown that the correlation between the abrin concentration and SERS signal was found to be linear within the range of 0.1 ng/mL to 1 μg/mL with a limit of detection of 0.1 ng/mL. Our microfluidic chip design enhanced the operability of SERS-based immunodiagnostic techniques, significantly reducing the complication and cost of preparation as compared to previous SERS-based works. Meanwhile, this design proved the superiority to conventional lateral flow test strips in respect of both sensitivity and quantitation and showed great potential in the diagnosis and treatment for abrin poisoning as well as on-site screening of abrin-spiked materials.

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

NASA Astrophysics Data System (ADS)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications <1 um smile and >96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

PubMed

Khawaja, Sajid Gul; Mushtaq, Mian Hamza; Khan, Shoab A; Akram, M Usman; Jamal, Habib Ullah

2015-01-01

With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

Designing Area Optimized Application-Specific Network-On-Chip Architectures while Providing Hard QoS Guarantees

PubMed Central

Khawaja, Sajid Gul; Mushtaq, Mian Hamza; Khan, Shoab A.; Akram, M. Usman; Jamal, Habib ullah

2015-01-01

With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows. PMID:25898016

System-level protection and hardware Trojan detection using weighted voting.

PubMed

Amin, Hany A M; Alkabani, Yousra; Selim, Gamal M I

2014-07-01

The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

FPGA accelerator for protein secondary structure prediction based on the GOR algorithm

PubMed Central

2011-01-01

Background Protein is an important molecule that performs a wide range of functions in biological systems. Recently, the protein folding attracts much more attention since the function of protein can be generally derived from its molecular structure. The GOR algorithm is one of the most successful computational methods and has been widely used as an efficient analysis tool to predict secondary structure from protein sequence. However, the execution time is still intolerable with the steep growth in protein database. Recently, FPGA chips have emerged as one promising application accelerator to accelerate bioinformatics algorithms by exploiting fine-grained custom design. Results In this paper, we propose a complete fine-grained parallel hardware implementation on FPGA to accelerate the GOR-IV package for 2D protein structure prediction. To improve computing efficiency, we partition the parameter table into small segments and access them in parallel. We aggressively exploit data reuse schemes to minimize the need for loading data from external memory. The whole computation structure is carefully pipelined to overlap the sequence loading, computing and back-writing operations as much as possible. We implemented a complete GOR desktop system based on an FPGA chip XC5VLX330. Conclusions The experimental results show a speedup factor of more than 430x over the original GOR-IV version and 110x speedup over the optimized version with multi-thread SIMD implementation running on a PC platform with AMD Phenom 9650 Quad CPU for 2D protein structure prediction. However, the power consumption is only about 30% of that of current general-propose CPUs. PMID:21342582

Autonomous Microsystems for Downhole Applications: Design Challenges, Current State, and Initial Test Results

PubMed Central

Choi, Myungjoon; Sui, Yu; Lee, In Hee; Meredith, Ryan; Ma, Yushu; Kim, Gyouho; Blaauw, David; Gianchandani, Yogesh B.; Li, Tao

2017-01-01

This paper describes two platforms for autonomous sensing microsystems that are intended for deployment in chemically corrosive environments at elevated temperatures and pressures. Following the deployment period, the microsystems are retrieved, recharged, and interrogated wirelessly at close proximity. The first platform is the Michigan Micro Mote for High Temperature (M3HT), a chip stack 2.9 × 1.1 × 1.5 mm3 in size. It uses RF communications to support pre-deployment and post-retrieval functions, and it uses customized electronics to achieve ultralow power consumption, permitting the use of a chip-scale battery. The second platform is the Environmental Logging Microsystem (ELM). This system, which is 6.5 × 6.3 × 4.5 mm3 in size, uses the smallest suitable off-the-shelf electronic and battery components that are compatible with assembly on a flexible printed circuit board. Data are stored in non-volatile memory, permitting retrieval even after total power loss. Pre-deployment and post-retrieval functions are supported by optical communication. Two types of encapsulation methods are used to withstand high pressure and corrosive environments: an epoxy filled volume is used for the M3HT, and a hollow stainless-steel shell with a sapphire lid is used for both the M3HT and ELM. The encapsulated systems were successfully tested at temperature and pressure reaching 150 °C and 10,000 psi, in environments of concentrated brine, oil, and cement slurry. At elevated temperatures, the limited lifetimes of available batteries constrain the active deployment period to several hours. PMID:28946614

Custom-designed orthopedic implants evaluated using finite element analysis of patient-specific computed tomography data: femoral-component case study

PubMed Central

Harrysson, Ola LA; Hosni, Yasser A; Nayfeh, Jamal F

2007-01-01

Background Conventional knee and hip implant systems have been in use for many years with good success. However, the custom design of implant components based on patient-specific anatomy has been attempted to overcome existing shortcomings of current designs. The longevity of cementless implant components is highly dependent on the initial fit between the bone surface and the implant. The bone-implant interface design has historically been limited by the surgical tools and cutting guides available; and the cost of fabricating custom-designed implant components has been prohibitive. Methods This paper describes an approach where the custom design is based on a Computed Tomography scan of the patient's joint. The proposed design will customize both the articulating surface and the bone-implant interface to address the most common problems found with conventional knee-implant components. Finite Element Analysis is used to evaluate and compare the proposed design of a custom femoral component with a conventional design. Results The proposed design shows a more even stress distribution on the bone-implant interface surface, which will reduce the uneven bone remodeling that can lead to premature loosening. Conclusion The proposed custom femoral component design has the following advantages compared with a conventional femoral component. (i) Since the articulating surface closely mimics the shape of the distal femur, there is no need for resurfacing of the patella or gait change. (ii) Owing to the resulting stress distribution, bone remodeling is even and the risk of premature loosening might be reduced. (iii) Because the bone-implant interface can accommodate anatomical abnormalities at the distal femur, the need for surgical interventions and fitting of filler components is reduced. (iv) Given that the bone-implant interface is customized, about 40% less bone must be removed. The primary disadvantages are the time and cost required for the design and the possible need for a surgical robot to perform the bone resection. Some of these disadvantages may be eliminated by the use of rapid prototyping technologies, especially the use of Electron Beam Melting technology for quick and economical fabrication of custom implant components. PMID:17854508

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

Plasma micro-nanotextured polymeric micromixer for DNA purification with high efficiency and dynamic range.

PubMed

Kastania, Athina S; Tsougeni, Katerina; Papadakis, George; Gizeli, Electra; Kokkoris, George; Tserepi, Angeliki; Gogolides, Evangelos

2016-10-26

We present a polymeric microfluidic chip capable of purifying DNA through solid phase extraction. It is designed to be used as a module of an integrated Lab-on-chip platform for pathogen detection, but it can also be used as a stand-alone device. The microfluidic channels are oxygen plasma micro-nanotextured, i.e. randomly roughened in the micro-nano scale, a process creating high surface area as well as high density of carboxyl groups (COOH). The COOH groups together with a buffer that contains polyethylene glycol (PEG), NaCl and ethanol are able to bind DNA on the microchannel surface. The chip design incorporates a mixer so that sample and buffer can be efficiently mixed on chip under continuous flow. DNA is subsequently eluted in water. The chip is able to isolate DNA with high recovery efficiency (96± 11%) in an extremely large dynamic range of prepurified Salmonella DNA as well as from Salmonella cell lysates that correspond to a range of 5 to 1.9 × 10 8  cells (0.263 fg to 2 × 500 ng). The chip was evaluated via absorbance measurements, polymerase chain reaction (PCR), and gel electrophoresis. Copyright © 2016 Elsevier B.V. All rights reserved.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

A new statistical methodology predicting chip failure probability considering electromigration

NASA Astrophysics Data System (ADS)

Sun, Ted

In this research thesis, we present a new approach to analyze chip reliability subject to electromigration (EM) whose fundamental causes and EM phenomenon happened in different materials are presented in this thesis. This new approach utilizes the statistical nature of EM failure in order to assess overall EM risk. It includes within-die temperature variations from the chip's temperature map extracted by an Electronic Design Automation (EDA) tool to estimate the failure probability of a design. Both the power estimation and thermal analysis are performed in the EDA flow. We first used the traditional EM approach to analyze the design with a single temperature across the entire chip that involves 6 metal and 5 via layers. Next, we used the same traditional approach but with a realistic temperature map. The traditional EM analysis approach and that coupled with a temperature map and the comparison between the results of considering and not considering temperature map are presented in in this research. A comparison between these two results confirms that using a temperature map yields a less pessimistic estimation of the chip's EM risk. Finally, we employed the statistical methodology we developed considering a temperature map and different use-condition voltages and frequencies to estimate the overall failure probability of the chip. The statistical model established considers the scaling work with the usage of traditional Black equation and four major conditions. The statistical result comparisons are within our expectations. The results of this statistical analysis confirm that the chip level failure probability is higher i) at higher use-condition frequencies for all use-condition voltages, and ii) when a single temperature instead of a temperature map across the chip is considered. In this thesis, I start with an overall review on current design types, common flows, and necessary verifications and reliability checking steps used in this IC design industry. Furthermore, the important concepts about "Scripting Automation" which is used in all the integration of using diversified EDA tools in this research work are also described in detail with several examples and my completed coding works are also put in the appendix for your reference. Hopefully, this construction of my thesis will give readers a thorough understanding about my research work from the automation of EDA tools to the statistical data generation, from the nature of EM to the statistical model construction, and the comparisons among the traditional EM analysis and the statistical EM analysis approaches.

Towards control of dexterous hand manipulations using a silicon Pattern Generator.

PubMed

Russell, Alexander; Tenore, Francesco; Singhal, Girish; Thakor, Nitish; Etienne-Cummings, Ralph

2008-01-01

This work demonstrates how an in silico Pattern Generator (PG) can be used as a low power control system for rhythmic hand movements in an upper-limb prosthesis. Neural spike patterns, which encode rotation of a cylindrical object, were implemented in a custom Very Large Scale Integration chip. PG control was tested by using the decoded control signals to actuate the fingers of a virtual prosthetic arm. This system provides a framework for prototyping and controlling dexterous hand manipulation tasks in a compact and efficient solution.

Optimization of a multi-well array SERS chip

NASA Astrophysics Data System (ADS)

Abell, J. L.; Driskell, J. D.; Dluhy, R. A.; Tripp, R. A.; Zhao, Y.-P.

2009-05-01

SERS-active substrates are fabricated by oblique angle deposition and patterned by a polymer-molding technique to provide a uniform array for high throughput biosensing and multiplexing. Using a conventional SERS-active molecule, 1,2-Bis(4-pyridyl)ethylene (BPE), we show that this device provides a uniform Raman signal enhancement from well to well. The patterning technique employed in this study demonstrates a flexibility allowing for patterning control and customization, and performance optimization of the substrate. Avian influenza is analyzed to demonstrate the ability of this multi-well patterned SERS substrate for biosensing.

The artificial satellite observation chronograph controlled by single chip microcomputer.

NASA Astrophysics Data System (ADS)

Pan, Guangrong; Tan, Jufan; Ding, Yuanjun

1991-06-01

The instrument specifications, hardware structure, software design, and other characteristics of the chronograph mounting on a theodolite used for artificial satellite observation are presented. The instrument is a real time control system with a single chip microcomputer.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

High-performance, scalable optical network-on-chip architectures

NASA Astrophysics Data System (ADS)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption.

Microvalve controlled multi-functional microfluidic chip for divisional cell co-culture.

PubMed

Li, Rui; Zhang, Xingjian; Lv, Xuefei; Geng, Lina; Li, Yongrui; Qin, Kuiwei; Deng, Yulin

2017-12-15

Pneumatic micro-valve controlled microfluidic chip provides precise fluidic control for cell manipulation. In this paper, a multi-functional microfluidic chip was designed for three separate experiments: 1. Different cell lines were dispensed and cultured; 2. Three transfected SH-SY5Y cells were introduced and treated with methyl-phenyl-pyridinium (MPP + ) as drug delivery mode; 3. Specific protection and interaction were observed among cell co-culture after nerve damage. The outcomes revealed the potential and practicability of our entire multi-functional pneumatic chip system on different cell biology applications. Copyright © 2017. Published by Elsevier Inc.

Design of Water Temperature Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

NASA Astrophysics Data System (ADS)

Marconi, S.; Conti, E.; Christiansen, J.; Placidi, P.

2018-05-01

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted.

Recent advances in design and fabrication of on-chip micro-supercapacitors

NASA Astrophysics Data System (ADS)

Beidaghi, Majid; Wang, Chunlei

2012-06-01

Recent development in miniaturized electronic devices has increased the demand for power sources that are sufficiently compact and can potentially be integrated on a chip with other electronic components. Miniaturized electrochemical capacitors (EC) or micro-supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. Recently, we have developed several types of micro-supercapacitors with different structural designs and active materials. Carbon-Microelectromechanical Systems (C-MEMS) with three dimensional (3D) interdigital structures are employed both as electrode material for electric double layer capacitor (EDLC) or as three dimensional (3D) current collectors of pseudo-capacitive materials. More recently, we have also developed microsupercapacitor based on hybrid graphene and carbon nanotube interdigital structures. In this paper, the recent advances in design and fabrication of on-chip micro-supercapacitors are reviewed.

Design of integrated eye tracker-display device for head mounted systems

NASA Astrophysics Data System (ADS)

David, Y.; Apter, B.; Thirer, N.; Baal-Zedaka, I.; Efron, U.

2009-08-01

We propose an Eye Tracker/Display system, based on a novel, dual function device termed ETD, which allows sharing the optical paths of the Eye tracker and the display and on-chip processing. The proposed ETD design is based on a CMOS chip combining a Liquid-Crystal-on-Silicon (LCoS) micro-display technology with near infrared (NIR) Active Pixel Sensor imager. The ET operation allows capturing the Near IR (NIR) light, back-reflected from the eye's retina. The retinal image is then used for the detection of the current direction of eye's gaze. The design of the eye tracking imager is based on the "deep p-well" pixel technology, providing low crosstalk while shielding the active pixel circuitry, which serves the imaging and the display drivers, from the photo charges generated in the substrate. The use of the ETD in the HMD Design enables a very compact design suitable for Smart Goggle applications. A preliminary optical, electronic and digital design of the goggle and its associated ETD chip and digital control, are presented.

Modeling the customer in electronic commerce.

PubMed

Helander, M G; Khalid, H M

2000-12-01

This paper reviews interface design of web pages for e-commerce. Different tasks in e-commerce are contrasted. A systems model is used to illustrate the information flow between three subsystems in e-commerce: store environment, customer, and web technology. A customer makes several decisions: to enter the store, to navigate, to purchase, to pay, and to keep the merchandize. This artificial environment must be designed so that it can support customer decision-making. To retain customers it must be pleasing and fun, and create a task with natural flow. Customers have different needs, competence and motivation, which affect decision-making. It may therefore be important to customize the design of the e-store environment. Future ergonomics research will have to investigate perceptual aspects, such as presentation of merchandize, and cognitive issues, such as product search and navigation, as well as decision making while considering various economic parameters. Five theories on e-commerce research are presented.

Application of FDM three-dimensional printing technology in the digital manufacture of custom edentulous mandible trays

PubMed Central

Chen, Hu; Yang, Xu; Chen, Litong; Wang, Yong; Sun, Yuchun

2016-01-01

The objective was to establish and evaluate a method for manufacture of custom trays for edentulous jaws using computer aided design and fused deposition modeling (FDM) technologies. A digital method for design the custom trays for edentulous jaws was established. The tissue surface data of ten standard mandibular edentulous plaster models, which was used to design the digital custom tray in a reverse engineering software, were obtained using a 3D scanner. The designed tray was printed by a 3D FDM printing device. Another ten hand-made custom trays were produced as control. The 3-dimentional surface data of models and custom trays was scanned to evaluate the accuracy of reserved impression space, while the difference between digitally made trays and hand-made trays were analyzed. The digitally made custom trays achieved a good matching with the mandibular model, showing higher accuracy than the hand-made ones. There was no significant difference of the reserved space between different models and its matched digitally made trays. With 3D scanning, CAD and FDM technology, an efficient method of custom tray production was established, which achieved a high reproducibility and accuracy. PMID:26763620

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

3D capillary stop valves for versatile patterning inside microfluidic chips.

PubMed

Papadimitriou, V A; Segerink, L I; van den Berg, A; Eijkel, J C T

2018-02-13

The patterning of antibodies in microfluidics chips is always a delicate process that is usually done in an open chip before bonding. Typical bonding techniques such as plasma treatment can harm the antibodies with as result that they are removed from our fabrication toolbox. Here we propose a method, based on capillary phenomena using 3D capillary valves, that autonomously and conveniently allows us to pattern liquids inside closed chips. We theoretically analyse the system and demonstrate how our analysis can be used as a design tool for various applications. Chips patterned with the method were used for simple immunodetection of a cardiac biomarker which demonstrates its suitability for antibody patterning. Copyright © 2017 The Authors. Published by Elsevier B.V. All rights reserved.

Workflows for microarray data processing in the Kepler environment.

PubMed

Stropp, Thomas; McPhillips, Timothy; Ludäscher, Bertram; Bieda, Mark

2012-05-17

Microarray data analysis has been the subject of extensive and ongoing pipeline development due to its complexity, the availability of several options at each analysis step, and the development of new analysis demands, including integration with new data sources. Bioinformatics pipelines are usually custom built for different applications, making them typically difficult to modify, extend and repurpose. Scientific workflow systems are intended to address these issues by providing general-purpose frameworks in which to develop and execute such pipelines. The Kepler workflow environment is a well-established system under continual development that is employed in several areas of scientific research. Kepler provides a flexible graphical interface, featuring clear display of parameter values, for design and modification of workflows. It has capabilities for developing novel computational components in the R, Python, and Java programming languages, all of which are widely used for bioinformatics algorithm development, along with capabilities for invoking external applications and using web services. We developed a series of fully functional bioinformatics pipelines addressing common tasks in microarray processing in the Kepler workflow environment. These pipelines consist of a set of tools for GFF file processing of NimbleGen chromatin immunoprecipitation on microarray (ChIP-chip) datasets and more comprehensive workflows for Affymetrix gene expression microarray bioinformatics and basic primer design for PCR experiments, which are often used to validate microarray results. Although functional in themselves, these workflows can be easily customized, extended, or repurposed to match the needs of specific projects and are designed to be a toolkit and starting point for specific applications. These workflows illustrate a workflow programming paradigm focusing on local resources (programs and data) and therefore are close to traditional shell scripting or R/BioConductor scripting approaches to pipeline design. Finally, we suggest that microarray data processing task workflows may provide a basis for future example-based comparison of different workflow systems. We provide a set of tools and complete workflows for microarray data analysis in the Kepler environment, which has the advantages of offering graphical, clear display of conceptual steps and parameters and the ability to easily integrate other resources such as remote data and web services.

Design and integration of an all-in-one biomicrofluidic chip

PubMed Central

Liu, Liyu; Cao, Wenbin; Wu, Jingbo; Wen, Weijia; Chang, Donald Choy; Sheng, Ping

2008-01-01

We demonstrate a highly integrated microfluidic chip with the function of DNA amplification. The integrated chip combines giant electrorheological-fluid actuated micromixer and micropump with a microheater array, all formed using soft lithography. Internal functional components are based on polydimethylsiloxane (PDMS) and silver∕carbon black-PDMS composites. The system has the advantages of small size with a high degree of integration, high polymerase chain reaction efficiency, digital control and simple fabrication at low cost. This integration approach shows promise for a broad range of applications in chemical synthesis and biological sensing∕analysis, as different components can be combined to target desired functionalities, with flexible designs of different microchips easily realizable through soft lithography. PMID:19693370

Language Classification using N-grams Accelerated by FPGA-based Bloom Filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, A; Gokhale, M

N-Gram (n-character sequences in text documents) counting is a well-established technique used in classifying the language of text in a document. In this paper, n-gram processing is accelerated through the use of reconfigurable hardware on the XtremeData XD1000 system. Our design employs parallelism at multiple levels, with parallel Bloom Filters accessing on-chip RAM, parallel language classifiers, and parallel document processing. In contrast to another hardware implementation (HAIL algorithm) that uses off-chip SRAM for lookup, our highly scalable implementation uses only on-chip memory blocks. Our implementation of end-to-end language classification runs at 85x comparable software and 1.45x the competing hardware design.

Electrokinetic focusing injection methods on microfluidic devices.

PubMed

Fu, Lung-Ming; Yang, Ruey-Jen; Lee, Gwo-Bin

2003-04-15

This paper presents an experimental and numerical investigation into electrokinetic focusing injection on microfluidic chips. The valving characteristics on microfluidic devices are controlled through appropriate manipulations of the electric potential strengths during the sample loading and dispensing steps. The present study also addresses the design and testing of various injection systems used to deliver a sample plug. A novel double-cross injection microfluidic chip is fabricated, which employs electrokinetic focusing to deliver sample plugs of variable volume. The proposed design combines several functions of traditional sample plug injection systems on a single microfluidic chip. The injection technique uses an unique sequence of loading steps with different electric potential distributions and magnitudes within the various channels to effectuate a virtual valve.

Macromolecular Crystal Growth by Means of Microfluidics

NASA Technical Reports Server (NTRS)

vanderWoerd, Mark; Ferree, Darren; Spearing, Scott; Monaco, Lisa; Molho, Josh; Spaid, Michael; Brasseur, Mike; Curreri, Peter A. (Technical Monitor)

2002-01-01

We have performed a feasibility study in which we show that chip-based, microfluidic (LabChip(TM)) technology is suitable for protein crystal growth. This technology allows for accurate and reliable dispensing and mixing of very small volumes while minimizing bubble formation in the crystallization mixture. The amount of (protein) solution remaining after completion of an experiment is minimal, which makes this technique efficient and attractive for use with proteins, which are difficult or expensive to obtain. The nature of LabChip(TM) technology renders it highly amenable to automation. Protein crystals obtained in our initial feasibility studies were of excellent quality as determined by X-ray diffraction. Subsequent to the feasibility study, we designed and produced the first LabChip(TM) device specifically for protein crystallization in batch mode. It can reliably dispense and mix from a range of solution constituents into two independent growth wells. We are currently testing this design to prove its efficacy for protein crystallization optimization experiments. In the near future we will expand our design to incorporate up to 10 growth wells per LabChip(TM) device. Upon completion, additional crystallization techniques such as vapor diffusion and liquid-liquid diffusion will be accommodated. Macromolecular crystallization using microfluidic technology is envisioned as a fully automated system, which will use the 'tele-science' concept of remote operation and will be developed into a research facility for the International Space Station as well as on the ground.

Interfacing Lab-on-a-Chip Embryo Technology with High-Definition Imaging Cytometry.

PubMed

Zhu, Feng; Hall, Christopher J; Crosier, Philip S; Wlodkowic, Donald

2015-08-01

To spearhead deployment of zebrafish embryo biotests in large-scale drug discovery studies, automated platforms are needed to integrate embryo in-test positioning and immobilization (suitable for high-content imaging) with fluidic modules for continuous drug and medium delivery under microperfusion to developing embryos. In this work, we present an innovative design of a high-throughput three-dimensional (3D) microfluidic chip-based device for automated immobilization and culture and time-lapse imaging of developing zebrafish embryos under continuous microperfusion. The 3D Lab-on-a-Chip array was fabricated in poly(methyl methacrylate) (PMMA) transparent thermoplastic using infrared laser micromachining, while the off-chip interfaces were fabricated using additive manufacturing processes (fused deposition modelling and stereolithography). The system's design facilitated rapid loading and immobilization of a large number of embryos in predefined clusters of traps during continuous microperfusion of drugs/toxins. It was conceptually designed to seamlessly interface with both upright and inverted fluorescent imaging systems and also to directly interface with conventional microtiter plate readers that accept 96-well plates. Compared with the conventional Petri dish assays, the chip-based bioassay was much more convenient and efficient as only small amounts of drug solutions were required for the whole perfusion system running continuously over 72 h. Embryos were spatially separated in the traps that assisted tracing single embryos, preventing interembryo contamination and improving imaging accessibility.

Bacterial communities in commercial aircraft high-efficiency particulate air (HEPA) filters assessed by PhyloChip analysis.

PubMed

Korves, T M; Piceno, Y M; Tom, L M; Desantis, T Z; Jones, B W; Andersen, G L; Hwang, G M

2013-02-01

Air travel can rapidly transport infectious diseases globally. To facilitate the design of biosensors for infectious organisms in commercial aircraft, we characterized bacterial diversity in aircraft air. Samples from 61 aircraft high-efficiency particulate air (HEPA) filters were analyzed with a custom microarray of 16S rRNA gene sequences (PhyloChip), representing bacterial lineages. A total of 606 subfamilies from 41 phyla were detected. The most abundant bacterial subfamilies included bacteria associated with humans, especially skin, gastrointestinal and respiratory tracts, and with water and soil habitats. Operational taxonomic units that contain important human pathogens as well as their close, more benign relatives were detected. When compared to 43 samples of urban outdoor air, aircraft samples differed in composition, with higher relative abundance of Firmicutes and Gammaproteobacteria lineages in aircraft samples, and higher relative abundance of Actinobacteria and Betaproteobacteria lineages in outdoor air samples. In addition, aircraft and outdoor air samples differed in the incidence of taxa containing human pathogens. Overall, these results demonstrate that HEPA filter samples can be used to deeply characterize bacterial diversity in aircraft air and suggest that the presence of close relatives of certain pathogens must be taken into account in probe design for aircraft biosensors. A biosensor that could be deployed in commercial aircraft would be required to function at an extremely low false alarm rate, making an understanding of microbial background important. This study reveals a diverse bacterial background present on aircraft, including bacteria closely related to pathogens of public health concern. Furthermore, this aircraft background is different from outdoor air, suggesting different probes may be needed to detect airborne contaminants to achieve minimal false alarm rates. This study also indicates that aircraft HEPA filters could be used with other molecular techniques to further characterize background bacteria and in investigations in the wake of a disease outbreak. © 2012 John Wiley & Sons A/S.

SiC Multi-Chip Power Modules as Power-System Building Blocks

NASA Technical Reports Server (NTRS)

Lostetter, Alexander; Franks, Steven

2007-01-01

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Intelligent Computation for Optimal Fabrication Condition of a Protein Chip with Ni-Co Alloy-Coated Surface.

PubMed

Chang, Yaw-Jen; Chang, Cheng-Hao

2016-06-01

Based on the principle of immobilized metal affinity chromatography (IMAC), it has been found that a Ni-Co alloy-coated protein chip is able to immobilize functional proteins with a His-tag attached. In this study, an intelligent computational approach was developed to promote the performance and repeatability of a Ni-Co alloy-coated protein chip. This approach was launched out of L18 experiments. Based on the experimental data, the fabrication process model of a Ni-Co protein chip was established by using an artificial neural network, and then an optimal fabrication condition was obtained using the Taguchi genetic algorithm. The result was validated experimentally and compared with a nitrocellulose chip. Consequentially, experimental outcomes revealed that the Ni-Co alloy-coated chip, fabricated using the proposed approach, had the best performance and repeatability compared with the Ni-Co chips of an L18 orthogonal array design and the nitrocellulose chip. Moreover, the low fluorescent background of the chip surface gives a more precise fluorescent detection. Based on a small quantity of experiments, this proposed intelligent computation approach can significantly reduce the experimental cost and improve the product's quality. © 2015 Society for Laboratory Automation and Screening.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Control and measurement of the phase behavior of aqueous solutions using microfluidics

PubMed Central

Shim, Jung-uk; Cristobal, Galder; Link, Darren R.; Thorsen, Todd; Jia, Yanwei; Piattelli, Katie; Fraden, Seth

2008-01-01

A microfluidic device denoted the Phase Chip has been designed to measure and manipulate the phase diagram of multi-component fluid mixtures. The Phase Chip exploits the permeation of water through poly(dimethylsiloxane) (PDMS) in order to controllably vary the concentration of solutes in aqueous nanoliter volume microdrops stored in wells. The permeation of water in the Phase Chip is modeled using the diffusion equation and good agreement between experiment and theory is obtained. The Phase Chip operates by first creating drops of the water/solute mixture whose composition varies sequentially. Next, drops are transported down channels and guided into storage wells using surface tension forces. Finally, the solute concentration of each stored drop is simultaneously varied and measured. Two applications of the Phase Chip are presented. First, the phase diagram of a polymer/salt mixture is measured on-chip and validated off-chip and second, protein crystallization rates are enhanced through the manipulation of the kinetics of nucleation and growth. PMID:17580868

Optic nerve signals in a neuromorphic chip II: Testing and results.

PubMed

Zaghloul, Kareem A; Boahen, Kwabena

2004-04-01

Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

Design and Performance of a Miniature Radar L-Band Transceiver

NASA Technical Reports Server (NTRS)

McWatters, D.; Price, D.; Edelstein, W.

2004-01-01

Radar electronics developed for past JPL space missions historically had been custom designed and as such, given budgetary, time, and risk constraints, had not been optimized for maximum flexibility or miniaturization. To help reduce cost and risk of future radar missions, a generic radar module was conceived. The module includes a 1.25-GHz (L-band) transceiver and incorporates miniature high-density packaging of integrated circuits in die/chip form. The technology challenges include overcoming the effect of miniaturization and high packaging density to achieve the performance, reliability, and environmental ruggedness required for space missions. The module was chosen to have representative (generic) functionality most likely required from an L-band radar. For very large aperture phased-array spaceborne radar missions, the large dimensions of the array suggest the benefit of distributing the radar electronics into the antenna array. For such applications, this technology is essential in order to bring down the cost, mass, and power of the radar electronics module replicated in each panel of the array. For smaller sized arrays, a single module can be combined with the central radar controller and still provide the bene.ts of configuration .exibility, low power, and low mass. We present the design approach for the radar electronics module and the test results for its radio frequency (RF) portion: a miniature, low-power, radiation-hard L-band transceiver.

Design of wideband solar ultraviolet radiation intensity monitoring and control system

NASA Astrophysics Data System (ADS)

Ye, Linmao; Wu, Zhigang; Li, Yusheng; Yu, Guohe; Jin, Qi

2009-08-01

According to the principle of SCM (Single Chip Microcomputer) and computer communication technique, the system is composed of chips such as ATML89C51, ADL0809, integrated circuit and sensors for UV radiation, which is designed for monitoring and controlling the UV index. This system can automatically collect the UV index data, analyze and check the history database, research the law of UV radiation in the region.

On-chip infrared sensors: redefining the benefits of scaling

NASA Astrophysics Data System (ADS)

Kita, Derek; Lin, Hongtao; Agarwal, Anu; Yadav, Anupama; Richardson, Kathleen; Luzinov, Igor; Gu, Tian; Hu, Juejun

2017-03-01

Infrared (IR) spectroscopy is widely recognized as a gold standard technique for chemical and biological analysis. Traditional IR spectroscopy relies on fragile bench-top instruments located in dedicated laboratory settings, and is thus not suitable for emerging field-deployed applications such as in-line industrial process control, environmental monitoring, and point-of-care diagnosis. Recent strides in photonic integration technologies provide a promising route towards enabling miniaturized, rugged platforms for IR spectroscopic analysis. It is therefore attempting to simply replace the bulky discrete optical elements used in conventional IR spectroscopy with their on-chip counterparts. This size down-scaling approach, however, cripples the system performance as both the sensitivity of spectroscopic sensors and spectral resolution of spectrometers scale with optical path length. In light of this challenge, we will discuss two novel photonic device designs uniquely capable of reaping performance benefits from microphotonic scaling. We leverage strong optical and thermal confinement in judiciously designed micro-cavities to circumvent the thermal diffusion and optical diffraction limits in conventional photothermal sensors and achieve a record 104 photothermal sensitivity enhancement. In the second example, an on-chip spectrometer design with the Fellgett's advantage is analyzed. The design enables sub-nm spectral resolution on a millimeter-sized, fully packaged chip without moving parts.

Optical time division multiplexer on silicon chip.

PubMed

Aboketaf, Abdelsalam A; Elshaari, Ali W; Preble, Stefan F

2010-06-21

In this work, we experimentally demonstrate a novel broadband optical time division multiplexer (OTDM) on a silicon chip. The fabricated devices generate 20 Gb/s and 40 Gb/s signals starting from a 5 Gb/s input signal. The proposed design has a small footprint of 1mm x 1mm. The system is inherently broadband with a bandwidth of over 100nm making it suitable for high-speed optical networks on chip.

Customizing microarrays for neuroscience drug discovery.

PubMed

Girgenti, Matthew J; Newton, Samuel S

2007-08-01

Microarray-based gene profiling has become the centerpiece of gene expression studies in the biological sciences. The ability to now interrogate the entire genome using a single chip demonstrates the progress in technology and instrumentation that has been made over the last two decades. Although this unbiased approach provides researchers with an immense quantity of data, obtaining meaningful insight is not possible without intensive data analysis and processing. Custom developed arrays have emerged as a viable and attractive alternative that can take advantage of this robust technology and tailor it to suit the needs and requirements of individual investigations. The ability to simplify data analysis, reduce noise and carefully optimize experimental conditions makes it a suitable tool that can be effectively utilized in neuroscience drug discovery efforts. Furthermore, incorporating recent advancements in fine focusing gene profiling to include specific cellular phenotypes can help resolve the complex cellular heterogeneity of the brain. This review surveys the use of microarray technology in neuroscience paying special attention to customized arrays and their potential in drug discovery. Novel applications of microarrays and ancillary techniques, such as laser microdissection, FAC sorting and RNA amplification, have also been discussed. The notion that a hypothesis-driven approach can be integrated into drug development programs is highlighted.

The development of the time-keeping clock with TS-1 single chip microcomputer.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Li, Yongan

The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

CHIP: Facilitating Interprofessional and Culturally Competent Patient Care Through Experiential Learning in China.

PubMed

Mu, Keli; Peck, Kirk; Jensen, Lou; Bracciano, Al; Carrico, Cathy; Feldhacker, Diana

2016-12-01

Health care professionals have advocated for educating culturally competent practitioners. Immersion in international experiences has an impact on student cultural competency and interprofessional development. The China Honors Interprofessional Program (CHIP) at a university in the Midwest is designed to increase students' cultural competency and interprofessional development. From 2009 to 2013, a total of 25 professional students including twelve occupational therapy students, ten physical therapy students and three nursing students were enrolled in the programme. Using a one group pre and posttest research design, this study evaluated the impact of CHIP on the participating students. Both quantitative and qualitative data were collected in the study. Findings of the study revealed that CHIP has impact on students' cultural competency and professional development including gaining appreciation and understanding of the contributions of other healthcare professionals and knowledge and skills in team work. The findings of the study suggested that international immersion experience such as CHIP is an important way to increase students' cultural competency and interprofessional knowledge and skills. Limitations of the study included the small sample in the study, indirect outcome measures and the possible celling effect of the instruments of the study. Future research studies should include a larger and more representative sample, direct outcome measures such as behaviour observation and more rigorous design such as prospective experimental comparison group design. Future research should also examine the long-term effects of international experience on the professional development of occupational therapy students. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.

Piecewise uniform conduction-like flow channels and method therefor

DOEpatents

Cummings, Eric B [Livermore, CA; Fiechtner, Gregory J [Livermore, CA

2006-02-28

A low-dispersion methodology for designing microfabricated conduction channels for on-chip electrokinetic-based systems is presented. The technique relies on trigonometric relations that apply for ideal electrokinetic flows, allowing faceted channels to be designed on chips using common drafting software and a hand calculator. Flows are rotated and stretched along the abrupt interface between adjacent regions with differing permeability. Regions bounded by interfaces form flow "prisms" that can be combined with other designed prisms to obtain a wide range of turning angles and expansion ratios while minimizing dispersion. Designs are demonstrated using two-dimensional numerical solutions of the Laplace equation.

Adjustment of multi-CCD-chip-color-camera heads

NASA Astrophysics Data System (ADS)

Guyenot, Volker; Tittelbach, Guenther; Palme, Martin

1999-09-01

The principle of beam-splitter-multi-chip cameras consists in splitting an image into differential multiple images of different spectral ranges and in distributing these onto separate black and white CCD-sensors. The resulting electrical signals from the chips are recombined to produce a high quality color picture on the monitor. Because this principle guarantees higher resolution and sensitivity in comparison to conventional single-chip camera heads, the greater effort is acceptable. Furthermore, multi-chip cameras obtain the compete spectral information for each individual object point while single-chip system must rely on interpolation. In a joint project, Fraunhofer IOF and STRACON GmbH and in future COBRA electronic GmbH develop methods for designing the optics and dichroitic mirror system of such prism color beam splitter devices. Additionally, techniques and equipment for the alignment and assembly of color beam splitter-multi-CCD-devices on the basis of gluing with UV-curable adhesives have been developed, too.

Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

NASA Technical Reports Server (NTRS)

Park, Yeonjoon; Yoon, Hargoon; Lee, Uhn; King, Glen C.; Choi, Sang H.

2012-01-01

A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

[Design and Optimization of Microfluidic Chips Used for Mixing Cryoprotectants].

PubMed

Zhou, Xinli; Yi, Xingyue; Zhou, Nanfeng; Yang, Yun

2016-06-01

Microfluidic chips can be used to realize continuous cryoprotectants(CPA)loading/unloading for oocytes,reducing osmotic damage and chemical toxicity of CPA.In this study,five different Y-shape microfluidic chips were fabricated to realize the continuous CPA loading/unloading.The effects of flow rate,entrance angle,aspect ratio and turning radius of microchannels on the mixing efficiency of microfluidic chips were analyzed quantitatively.The experimental results showed that with the decrease of flow rates,the increase of aspect ratios and the decrease of turning raradius of microchannel,the mixing length decreased and the mixing velocity was promoted,while the entrance angle had little effect on the mixing efficiency.However,the operating conditions and structural parameters of the chips in practical application should be determined based on an overall consideration of CPA loading/unloading time and machining accuracy.These results would provide a reference to the application of microfluidic chip in CPA mixing.

The Customer Flow Toolkit: A Framework for Designing High Quality Customer Services.

ERIC Educational Resources Information Center

New York Association of Training and Employment Professionals, Albany.

This document presents a toolkit to assist staff involved in the design and development of New York's one-stop system. Section 1 describes the preplanning issues to be addressed and the intended outcomes that serve as the framework for creation of the customer flow toolkit. Section 2 outlines the following strategies to assist in designing local…

Post-OPC verification using a full-chip pattern-based simulation verification method

NASA Astrophysics Data System (ADS)

Hung, Chi-Yuan; Wang, Ching-Heng; Ma, Cliff; Zhang, Gary

2005-11-01

In this paper, we evaluated and investigated techniques for performing fast full-chip post-OPC verification using a commercial product platform. A number of databases from several technology nodes, i.e. 0.13um, 0.11um and 90nm are used in the investigation. Although it has proven that for most cases, our OPC technology is robust in general, due to the variety of tape-outs with complicated design styles and technologies, it is difficult to develop a "complete or bullet-proof" OPC algorithm that would cover every possible layout patterns. In the evaluation, among dozens of databases, some OPC databases were found errors by Model-based post-OPC checking, which could cost significantly in manufacturing - reticle, wafer process, and more importantly the production delay. From such a full-chip OPC database verification, we have learned that optimizing OPC models and recipes on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. And, fatal errors (such as pinch or bridge) or poor CD distribution and process-sensitive patterns may still occur. As a result, more than one reticle tape-out cycle is not uncommon to prove models and recipes that approach the center of process for a range of designs. So, we will describe a full-chip pattern-based simulation verification flow serves both OPC model and recipe development as well as post OPC verification after production release of the OPC. Lastly, we will discuss the differentiation of the new pattern-based and conventional edge-based verification tools and summarize the advantages of our new tool and methodology: 1). Accuracy: Superior inspection algorithms, down to 1nm accuracy with the new "pattern based" approach 2). High speed performance: Pattern-centric algorithms to give best full-chip inspection efficiency 3). Powerful analysis capability: Flexible error distribution, grouping, interactive viewing and hierarchical pattern extraction to narrow down to unique patterns/cells.

A Data Acquisition System Using Single-Chip Microcomputer

NASA Astrophysics Data System (ADS)

Yonyjiang, Dai; Jingkuan, Gao; Lin, Wan; Mingjia, Pi; Jingda, Nan

1989-12-01

A data acquisition system by single-chip microcomputer was designed. It is suitable to the future devlopment of the miniature tidar signal processing epuipment . The characteristics of frequecy response, SNR, D* and NEP of FM-CW CO2 coherent tidar were discussed.

Configurable product design considering the transition of multi-hierarchical models

NASA Astrophysics Data System (ADS)

Ren, Bin; Qiu, Lemiao; Zhang, Shuyou; Tan, Jianrong; Cheng, Jin

2013-03-01

The current research of configurable product design mainly focuses on how to convert a predefined set of components into a valid set of product structures. With the scale and complexity of configurable products increasing, the interdependencies between customer demands and product structures grow up as well. The result is that existing product structures fails to satisfy the individual customer requirements and hence product variants are needed. This paper is aimed to build a bridge between customer demands and product structures in order to make demand-driven fast response design feasible. First of all, multi-hierarchical models of configurable product design are established with customer demand model, technical requirement model and product structure model. Then, the transition of multi-hierarchical models among customer demand model, technical requirement model and product structure model is solved with fuzzy analytic hierarchy process (FAHP) and the algorithm of multi-level matching. Finally, optimal structure according to the customer demands is obtained with the calculation of Euclidean distance and similarity of some cases. In practice, the configuration design of a clamping unit of injection molding machine successfully performs an optimal search strategy for the product variants with reasonable satisfaction to individual customer demands. The proposed method can automatically generate a configuration design with better alternatives for each product structures, and shorten the time of finding the configuration of a product.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Applying CBR to machine tool product configuration design oriented to customer requirements

NASA Astrophysics Data System (ADS)

Wang, Pengjia; Gong, Yadong; Xie, Hualong; Liu, Yongxian; Nee, Andrew Yehching

2017-01-01

Product customization is a trend in the current market-oriented manufacturing environment. However, deduction from customer requirements to design results and evaluation of design alternatives are still heavily reliant on the designer's experience and knowledge. To solve the problem of fuzziness and uncertainty of customer requirements in product configuration, an analysis method based on the grey rough model is presented. The customer requirements can be converted into technical characteristics effectively. In addition, an optimization decision model for product planning is established to help the enterprises select the key technical characteristics under the constraints of cost and time to serve the customer to maximal satisfaction. A new case retrieval approach that combines the self-organizing map and fuzzy similarity priority ratio method is proposed in case-based design. The self-organizing map can reduce the retrieval range and increase the retrieval efficiency, and the fuzzy similarity priority ratio method can evaluate the similarity of cases comprehensively. To ensure that the final case has the best overall performance, an evaluation method of similar cases based on grey correlation analysis is proposed to evaluate similar cases to select the most suitable case. Furthermore, a computer-aided system is developed using MATLAB GUI to assist the product configuration design. The actual example and result on an ETC series machine tool product show that the proposed method is effective, rapid and accurate in the process of product configuration. The proposed methodology provides a detailed instruction for the product configuration design oriented to customer requirements.