Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

NASA Astrophysics Data System (ADS)

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J.; Janes, David B.

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including `see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In2O3 and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with ~82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics.

PubMed

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J; Janes, David B

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Historical Perspective on Technology and Music.

ERIC Educational Resources Information Center

Webster, Peter

2002-01-01

Explores the historical developments in technology that affected music education. Describes the developments in hardware, such as gears and levers, electricity, vacuum tubes, transistors, and integrated circuits. Discusses the changes in computer software from the 1950s to the present. (CMK)

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization.

PubMed

Tran, Duy Phu; Pham, Thuy Thi Thanh; Wolfrum, Bernhard; Offenhäusser, Andreas; Thierry, Benjamin

2018-05-11

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs' promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.

Heterojunction bipolar transistor technology for data acquisition and communication

NASA Technical Reports Server (NTRS)

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Novel gallium nitride based microwave noise and power heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Chumbes, Eduardo Martin

With the pioneering efforts of Isamu Akasaki of Meiji University and Shuji Nakamura of Nichia Chemical Industries in the late 1980's and early 1990's, the first long-lived candela-class blue and ultraviolet light emitting devices have finally come to fruition. Their success in conquering this Holy Grail in opto-electronics is due to their development of a new technology based remarkably on a class of semiconductor materials that has been practically ignored and overlooked by almost everyone for the past twenty years---the nitrides of Al, Ga and In and their alloys. The breakthroughs made from this new technology in the last decade of the 20th century has revolutionized and revitalized worldwide research and development efforts to the point where it is feasible for other important technologies such as high-density information storage, high-resolution full-color displays and efficient white light lamps and UV sensors to come much closer to realization. Equally important is the potential that this new technology can bring toward the development of efficient ultra-high power and high-temperature electronics that will revolutionize the aerospace and high-speed communication industries. Specifically, the large bandgap and strong polar properties of the group III-nitrides has at present allowed for the realization of simple doped and remarkably undoped AlGaN/GaN transistor structures on sapphire and SiC substrates with two-dimensional electron gas sheet densities significantly greater than that of conventional transistor structures based on GaAs and InP. This dissertation will look specifically at extending undoped AlGaN/GaN heterostructure field-effect transistors or HFETs towards more advanced system applications involving the integration of these devices onto a more advanced Si technology and looking at the feasibility of this integration. It will also address important issues similar devices on semi-insulating SiC substrates have in robust microwave low noise and linear amplification. Finally, it will look at incorporating high-temperature silicon nitride passivation as a key ingredient to developing a unique class of devices: metal-insulator-semiconductor field effect transistors or MISFETs as a means for providing efficient high power amplification without compromising performance associated with surface- and process-related dispersion. This dissertation will finally close with a brief outlook on the future outlook of these technologies.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Kilovolt dc solid state remote power controller development

NASA Technical Reports Server (NTRS)

Mitchell, J. T.

1982-01-01

The experience gained in developing and applying solid state power controller (SSPC) technology at high voltage dc (HVDC) potentials and power levels of up to 25 kilowatts is summarized. The HVDC switching devices, power switching concepts, drive circuits, and very fast acting overcurrent protection circuits were analyzed. A 25A bipolar breadboard with Darlington connected switching transistor was built. Fault testing at 900 volts was included. A bipolar transistor packaged breadboard design was developed. Power MOSFET remote power controller (RPC) was designed.

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

PubMed Central

Wolfrum, Bernhard; Thierry, Benjamin

2018-01-01

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs’ promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology. PMID:29751688

The Social Effects of Communication Technology.

ERIC Educational Resources Information Center

Goldhamer, Herbert, Ed.; Westrum, Ronald

The principal technological developments that underlie the communication revolution, especially the transistor and the computer, are reviewed in a nontechnical way. A number of devices and communication subsystems, such as cable television, ultramicrofiche, and communication satellites, that make use of these developments are then described,…

Technology Directions for the 21st Century, volume 1

NASA Technical Reports Server (NTRS)

Crimi, Giles F.; Verheggen, Henry; McIntosh, William; Botta, Robert

1996-01-01

For several decades, semiconductor device density and performance have been doubling about every 18 months (Moore's Law). With present photolithography techniques, this rate can continue for only about another 10 years. Continued improvement will need to rely on newer technologies. Transition from the current micron range for transistor size to the nanometer range will permit Moore's Law to operate well beyond 10 years. The technologies that will enable this extension include: single-electron transistors; quantum well devices; spin transistors; and nanotechnology and molecular engineering. Continuation of Moore's Law will rely on huge capital investments for manufacture as well as on new technologies. Much will depend on the fortunes of Intel, the premier chip manufacturer, which, in turn, depend on the development of mass-market applications and volume sales for chips of higher and higher density. The technology drivers are seen by different forecasters to include video/multimedia applications, digital signal processing, and business automation. Moore's Law will affect NASA in the areas of communications and space technology by reducing size and power requirements for data processing and data fusion functions to be performed onboard spacecraft. In addition, NASA will have the opportunity to be a pioneering contributor to nanotechnology research without incurring huge expenses.

Diffused Silicon Transistors and Switches (1954-55): The Beginning of Integrated Circuit Technology

NASA Astrophysics Data System (ADS)

Holonyak, N.

2003-09-01

Silicon (Si) transistor and integrated circuit (IC) technology has grown so big, and become so important, that it is now hard to recognize where, apart from the invention of the transistor itself (Bardeen and Brattain, Dec 16, 1947), it had its origin. In spite of obvious differences in Ge and Si, in 1950-55 it was not evident in many laboratories, concentrating only on Ge, what form of Ge transistor (grown, alloyed, jet-etched, etc.) might be expected to prevail, with Si not even being considered (or being dismissed outright). What was the need for Si and, at the time, such a seemingly intractable peculiar new technology? The requirement on switching devices of low leakage, and thus the need to leave Ge in favor of Si, led directly in 1954-55 (Bell Telephone Laboratories, BTL) to the exploration of impurity-diffusion and metallization technology to realize Si transistors and p-n-p-n switches. This technology, a more or less ideal thin-layer technology that can be referenced from a single surface (and which indeed has proven to be basically invariant and constantly growing), led further to the discovery (1955) of the protective Si oxide, oxide masking and patterning, and the fundamental basis of the integrated circuit (i.e., device-to-device interconnection by patterned metallization across the oxide). We recount some of the exploratory diffused-impurity Si device development of 1954-55 at BTL, particularly the work in and near Moll's group, that helped to establish the basis for today's electronics. The Si diffused-impurity devices of 1954-55 are described, including work and data not previously reported or broadly known—in fact, much work and data (a new technology) that was carried across the Country to a place that became known as Silicon Valley. For further perspective, an appendix is included of independent early suggestions of Bardeen (Urbana notebook, Feb 1952) to leave Ge in favor of diffused Si devices.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

NASA Astrophysics Data System (ADS)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

Integrated Microfluidic Membrane Transistor Utilizing Chemical Information for On-Chip Flow Control.

PubMed

Frank, Philipp; Schreiter, Joerg; Haefner, Sebastian; Paschew, Georgi; Voigt, Andreas; Richter, Andreas

2016-01-01

Microfluidics is a great enabling technology for biology, biotechnology, chemistry and general life sciences. Despite many promising predictions of its progress, microfluidics has not reached its full potential yet. To unleash this potential, we propose the use of intrinsically active hydrogels, which work as sensors and actuators at the same time, in microfluidic channel networks. These materials transfer a chemical input signal such as a substance concentration into a mechanical output. This way chemical information is processed and analyzed on the spot without the need for an external control unit. Inspired by the development electronics, our approach focuses on the development of single transistor-like components, which have the potential to be used in an integrated circuit technology. Here, we present membrane isolated chemical volume phase transition transistor (MIS-CVPT). The device is characterized in terms of the flow rate from source to drain, depending on the chemical concentration in the control channel, the source-drain pressure drop and the operating temperature.

Integrated Microfluidic Membrane Transistor Utilizing Chemical Information for On-Chip Flow Control

PubMed Central

Frank, Philipp; Schreiter, Joerg; Haefner, Sebastian; Paschew, Georgi; Voigt, Andreas; Richter, Andreas

2016-01-01

Microfluidics is a great enabling technology for biology, biotechnology, chemistry and general life sciences. Despite many promising predictions of its progress, microfluidics has not reached its full potential yet. To unleash this potential, we propose the use of intrinsically active hydrogels, which work as sensors and actuators at the same time, in microfluidic channel networks. These materials transfer a chemical input signal such as a substance concentration into a mechanical output. This way chemical information is processed and analyzed on the spot without the need for an external control unit. Inspired by the development electronics, our approach focuses on the development of single transistor-like components, which have the potential to be used in an integrated circuit technology. Here, we present membrane isolated chemical volume phase transition transistor (MIS-CVPT). The device is characterized in terms of the flow rate from source to drain, depending on the chemical concentration in the control channel, the source-drain pressure drop and the operating temperature. PMID:27571209

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.

PubMed

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A; Anthopoulos, Thomas D

2017-03-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In 2 O 3 /ZnO heterojunction. We find that In 2 O 3 /ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In 2 O 3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In 2 O 3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution

PubMed Central

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A.; Anthopoulos, Thomas D.

2017-01-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In2O3/ZnO heterojunction. We find that In2O3/ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In2O3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In2O3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications. PMID:28435867

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Interband Lateral Resonant Tunneling Transistor.

DTIC Science & Technology

1994-11-14

INTERBAND LATERAL RESONANT TUNNELING TRANSISTOR 10 BACKGROUND OF THE INVENTION Field of the Invention This invention pertains to a tunneling transistor...and in 15 particular to an interband lateral resonant tunneling transistor. Description of Related Art Conventional semiconductor technologies are... interband lateral resonant tunneling transistor along the cross-section B-B of Figure 2c. Figure 4 is another preferred embodiment cross-sectional 20

Neuromorphic transistor achieved by redox reaction of WO3 thin film

NASA Astrophysics Data System (ADS)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

Progress on advanced dc and ac induction drives for electric vehicles

NASA Technical Reports Server (NTRS)

Schwartz, H. J.

1982-01-01

Progress is reported in the development of complete electric vehicle propulsion systems, and the results of tests on the Road Load Simulator of two such systems representative of advanced dc and ac drive technology are presented. One is the system used in the DOE's ETV-1 integrated test vehicle which consists of a shunt wound dc traction motor under microprocessor control using a transistorized controller. The motor drives the vehicle through a fixed ratio transmission. The second system uses an ac induction motor controlled by transistorized pulse width modulated inverter which drives through a two speed automatically shifted transmission. The inverter and transmission both operate under the control of a microprocessor. The characteristics of these systems are also compared with the propulsion system technology available in vehicles being manufactured at the inception of the DOE program and with an advanced, highly integrated propulsion system upon which technology development was recently initiated.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

Studies of prototype DEPFET sensors for the Wide Field Imager of Athena

NASA Astrophysics Data System (ADS)

Treberspurg, Wolfgang; Andritschke, Robert; Bähr, Alexander; Behrens, Annika; Hauser, Günter; Lechner, Peter; Meidinger, Norbert; Müller-Seidlitz, Johannes; Treis, Johannes

2017-08-01

The Wide Field Imager (WFI) of ESA's next X-ray observatory Athena will combine a high count rate capability with a large field of view, both with state-of-the-art spectroscopic performance. To meet these demands, specific DEPFET active pixel detectors have been developed and operated. Due to the intrinsic amplification of detected signals they are best suited to achieve a high speed and low noise performance. Different fabrication technologies and transistor geometries have been implemented on a dedicated prototype production in the course of the development of the DEPFET sensors. The main modifications between the sensors concern the shape of the transistor gate - regarding the layout - and the thickness of the gate oxide - regarding the technology. To facilitate the fabrication and testing of the resulting variety of sensors the presented studies were carried out with 64×64 pixel detectors. The detector comprises a control ASIC (Switcher-A), a readout ASIC (VERITAS- 2) and the sensor. In this paper we give an overview on the evaluation of different prototype sensors. The most important results, which have been decisive for the identification of the optimal fabrication technology and transistor layout for subsequent sensor productions are summarized. It will be shown that the developments result in an excellent performance of spectroscopic X-ray DEPFETs with typical noise values below 2.5 ENC at 2.5 μs/row.

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Oscillatory threshold logic.

PubMed

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

NASA Astrophysics Data System (ADS)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology.

PubMed

Fukuda, Kenjiro; Someya, Takao

2017-07-01

Printed electronics enable the fabrication of large-scale, low-cost electronic devices and systems, and thus offer significant possibilities in terms of developing new electronics/optics applications in various fields. Almost all electronic applications require information processing using logic circuits. Hence, realizing the high-speed operation of logic circuits is also important for printed devices. This report summarizes recent progress in the development of printed thin-film transistors (TFTs) and integrated circuits in terms of materials, printing technologies, and applications. The first part of this report gives an overview of the development of functional inks such as semiconductors, electrodes, and dielectrics. The second part discusses high-resolution printing technologies and strategies to enable high-resolution patterning. The main focus of this report is on obtaining printed electrodes with high-resolution patterning and the electrical performance of printed TFTs using such printed electrodes. In the final part, some applications of printed electronics are introduced to exemplify their potential. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Modeling of short channel MOS transistors

NASA Technical Reports Server (NTRS)

Lin, H. C.; Kokalis, D. P.; Bandy, W. R.

1976-01-01

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Solvent-Free Toner Printing of Organic Semiconductor Layer in Flexible Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Sakai, Masatoshi; Koh, Tokuyuki; Toyoshima, Kenji; Nakamori, Kouta; Okada, Yugo; Yamauchi, Hiroshi; Sadamitsu, Yuichi; Shinamura, Shoji; Kudo, Kazuhiro

2017-07-01

A solvent-free printing process for printed electronics is successfully developed using toner-type patterning of organic semiconductor toner particles and the subsequent thin-film formation. These processes use the same principle as that used for laser printing. The organic thin-film transistors are prepared by electrically distributing the charged toner onto a Au electrode on a substrate film, followed by thermal lamination. The thermal lamination is effective for obtaining an oriented and crystalline thin film. Toner printing is environmentally friendly compared with other printing technologies because it is solvent free, saves materials, and enables easy recycling. In addition, this technology simultaneously enables both wide-area and high-resolution printing.

Development of Process Technologies for High-Performance MOS-Based SiC Power Switching Devices

DTIC Science & Technology

2007-08-01

investigated are insulated-gate bipolar transistors ( IGBTs ) in 4H-SiC. The IGBT combines the best aspects of MOS and bipolar power transistors... IGBTs can be thought of as a fusion of a MOSFET and a BJT. The MOSFET provides a high input impedance while the BJT provides conductivity modulation of...region due to conductivity modulation from the forward-biased BJT. The IGBT is structurally identical to a MOSFET, except that the substrate doping

Technology Roadmaps for Compound Semiconductors

PubMed Central

Bennett, Herbert S.

2000-01-01

The roles cited for compound semiconductors in public versions of existing technology roadmaps from the National Electronics Manufacturing Initiative, Inc., Optoelectronics Industry Development Association, Microelectronics Advanced Research Initiative on Optoelectronic Interconnects, and Optoelectronics Industry and Technology Development Association (OITDA) are discussed and compared within the context of trends in the Si CMOS industry. In particular, the extent to which these technology roadmaps treat compound semiconductors at the materials processing and device levels will be presented for specific applications. For example, OITDA’s Optical Communications Technology Roadmap directly connects the information demand of delivering 100 Mbit/s to the home to the requirement of producing 200 GHz heterojunction bipolar transistors with 30 nm bases and InP high electron mobility transistors with 100 nm gates. Some general actions for progress towards the proposed International Technology Roadmap for Compound Semiconductors (ITRCS) and methods for determining the value of an ITRCS will be suggested. But, in the final analysis, the value added by an ITRCS will depend on how industry leaders respond. The technical challenges and economic opportunities of delivering high quality digital video to consumers provide concrete examples of where the above actions and methods could be applied. PMID:27551615

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Lee, Yong Hee; Joo, Seung Ki

2017-06-01

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. He received the B.S. degree in School of Advanced Materials Engineering from Kookmin University, Seoul, South Korea in 2012, and the M.S. degree in Department of Materials Science and Engineering from Seoul National University, Seoul, South Korea in 2014. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and top-gate polycrystalline-silicon thin-film transistors. He received the M.S. degree in innovation technology from Ecol Polytechnique, Palaiseau, France in 2013. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and copper-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1974, and the M.S. and Ph.D. degrees in material science and engineering from Stanford University, Stanford, CA, USA, in 1980 and 1983, respectively. He is currently a Professor with the Department of Materials Science and Engineering, Seoul National University, Seoul.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

PubMed

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Large-signal model of the bilayer graphene field-effect transistor targeting radio-frequency applications: Theory versus experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pasadas, Francisco, E-mail: Francisco.Pasadas@uab.cat; Jiménez, David

2015-12-28

Bilayer graphene is a promising material for radio-frequency transistors because its energy gap might result in a better current saturation than the monolayer graphene. Because the great deal of interest in this technology, especially for flexible radio-frequency applications, gaining control of it requires the formulation of appropriate models for the drain current, charge, and capacitance. In this work, we have developed them for a dual-gated bilayer graphene field-effect transistor. A drift-diffusion mechanism for the carrier transport has been considered coupled with an appropriate field-effect model taking into account the electronic properties of the bilayer graphene. Extrinsic resistances have been includedmore » considering the formation of a Schottky barrier at the metal-bilayer graphene interface. The proposed model has been benchmarked against experimental prototype transistors, discussing the main figures of merit targeting radio-frequency applications.« less

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors.

PubMed

Fahad, Hossain Mohammad; Shiraki, Hiroshi; Amani, Matin; Zhang, Chuchu; Hebbar, Vivek Srinivas; Gao, Wei; Ota, Hiroki; Hettick, Mark; Kiriya, Daisuke; Chen, Yu-Ze; Chueh, Yu-Lun; Javey, Ali

2017-03-01

There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry-compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically nonconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H 2 S, H 2 , and NO 2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors.

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors

PubMed Central

Fahad, Hossain Mohammad; Shiraki, Hiroshi; Amani, Matin; Zhang, Chuchu; Hebbar, Vivek Srinivas; Gao, Wei; Ota, Hiroki; Hettick, Mark; Kiriya, Daisuke; Chen, Yu-Ze; Chueh, Yu-Lun; Javey, Ali

2017-01-01

There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry-compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically nonconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H2S, H2, and NO2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors. PMID:28378017

Oscillatory Threshold Logic

PubMed Central

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

N-type organic electrochemical transistors with stability in water

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan -Tiberiu

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurementsmore » in water show no degradation when tested for 2 h under continuous cycling. Furthermore, this demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.« less

N-type organic electrochemical transistors with stability in water

DOE PAGES

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan -Tiberiu; ...

2016-10-07

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurementsmore » in water show no degradation when tested for 2 h under continuous cycling. Furthermore, this demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.« less

Oxide Based Transistor for Flexible Displays

DTIC Science & Technology

2014-09-15

thin film transistors (TFTs) for next generation display technologies. A detailed and comprehensive study was carried out to ascertain the process...Box 12211 Research Triangle Park, NC 27709-2211 Thin film transistors , flexible electronics, RF sputtering, Transparent amorphous oxide semiconductors...NC A&T and RTI, International investigated In free GaSnZnO (GSZO) material system, as the active channel in thin film transistors (TFTs) for next

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Component technology for space power systems

NASA Technical Reports Server (NTRS)

Finke, R.

1982-01-01

The Lewis/OAST program for the development of Component Technology for Space Power Systems is described. The program is divided into five generic areas: semiconductor devices (transistors, thyristors, and diodes); conductors (materials and transmission lines); dielectrics; magnetic devices; and thermal control devices. Examples of progress in each of the five areas is discussed. Bipolar power transistors up to 1000 V at 100 A with a gain of 10 and a 0.5 mu sec rise and fall time are presented. A new class of semiconductor devices with a possibility of switching 1000 000 V is described. Several 100 kW rotary power transformer designs and a 25 kW, 20 kHz transformer weighting 3.2 kg have been developed. Progress on the creation of diamond-like films for thermal devices and intercalated carbon fibers with the strength of steel and the conductivity of copper at one third the mass of copper is presented.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.;

Contact Metallization and Packaging Technology Development for SiC Bipolar Junction Transistors, PiN Diodes, and Schottky Diodes Designed for Long-Term Operations at 350degreeC

DTIC Science & Technology

2006-05-01

switches that are used in power conditioning systems. Silicon carbide diodes are now available commercially, and transistors (JEFETs, MOSFETs, IGBTs ...in UHP Ar for 60s in a rapid thermal annealing (RTA) furnace to achieve a low contact resistance. Following the RTA step, photolithography was...with 20μm Au is shown in Figure 3-4. The brazing process was performed with an SST 3150 high vacuum furnace . The 3150 utilizes an oil-free roughing

Design-Oriented Introduction of Nanotechnology into the Electrical and Computer Engineering Curriculum

ERIC Educational Resources Information Center

Kim, Donghwi; Kamoua, Ridha; Pacelli, Andrea

2006-01-01

Nanoelectronics has the potential, and is indeed expected, to revolutionize information technology by the use of the impressive characteristics of nano-devices such as carbon nanotube transistors, molecular diodes and transistors, etc. A great effort is being put into creating an introductory course in nano-technology. However, practically all…

T-shaped emitter metal heterojunction bipolar transistors for submillimeter wave applications

NASA Technical Reports Server (NTRS)

Fung, Andy; Samoska, Lorene; Velebir, Jim; Siege, Peter; Rodwell, Mark; Paidi, Vamsi; Griffth, Zach; Urteaga, Miguel; Malik, Roger

2004-01-01

We report on the development of submillimeter wave transistors at JPL. The goal of the effort is to produce advance-reliable high frequency and high power amplifiers, voltage controlled oscillators, active multipliers, and high-speed mixed-signal circuits for space borne applications. The technology in development to achieve this is based on the Indium Phosphide (InP) Heterojunction Bipolar Transistor (HBT). The HBT is well suited for high speed, high power and uniform (across wafer) performance, due to the ability to tailor the material structure that electrons traverse through by well-controlled epitaxial growth methods. InP with its compatible lattice matched alloys such as indium gallium arsenide (InGaAs) and indium aluminium arsenide (InAlAs) provides for high electron velocities and high voltage breakdown capabilities. The epitaxial methods for this material system are fairly mature, however the implementation of high performance and reliable transistors are still under development by many laboratories. Our most recently fabricated, second generation mesa HBTs at JPL have extrapolated current gain cutoff frequency (FJ of 142GHz and power gain cutoff frequency (Fm,) of approximately 160GHz. This represents a 13% and 33% improvement of Ft and F, respectively, compared to the first generation mesa HBTs [l]. Analysis based on the University of California, Santa Barbara (UCSB) device model, RF device characteristics can be significantly improved by reducing base contact resistance and base metal contact width. We will describe our effort towards increasing transistor performance and yield.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

NASA Astrophysics Data System (ADS)

Dhakras, Prathamesh; Agnihotri, Pratik; Lee, Ji Ung

2017-06-01

The three pillars of semiconductor device technologies are (1) the p-n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

PubMed

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Standard Transistor Array (STAR). Volume 1: Placement technique

NASA Technical Reports Server (NTRS)

Cox, G. W.; Caroll, B. D.

1979-01-01

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.

Carbon nanotube transistor based high-frequency electronics

NASA Astrophysics Data System (ADS)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks. Carbon nanotube transistor based high-frequency electronics.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

NASA Astrophysics Data System (ADS)

Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

2014-04-01

Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Length separation of single-walled carbon nanotubes and its impact on structural and electrical properties of wafer-level fabricated carbon nanotube-field-effect transistors

NASA Astrophysics Data System (ADS)

Böttger, Simon; Hermann, Sascha; Schulz, Stefan E.; Gessner, Thomas

2016-10-01

For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT-FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT-FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT-FETs fabricated with a wafer-level technology.

Carbon nanotube macroelectronics

NASA Astrophysics Data System (ADS)

Zhang, Jialu

In this dissertation, I discuss the application of carbon nanotubes in macroelectronis. Due to the extraordinary electrical properties such as high intrinsic carrier mobility and current-carrying capacity, single wall carbon nanotubes are very desirable for thin-film transistor (TFT) applications such as flat panel display, transparent electronics, as well as flexible and stretchable electronics. Compared with other popular channel material for TFTs, namely amorphous silicon, polycrystalline silicon and organic materials, nanotube thin-films have the advantages of low-temperature processing compatibility, transparency, and flexibility, as well as high device performance. In order to demonstrate scalable, practical carbon nanotube macroelectroncis, I have developed a platform to fabricate high-density, uniform separated nanotube based thin-film transistors. In addition, many other essential analysis as well as technology components, such as nanotube film density control, purity and diameter dependent semiconducting nanotube electrical performance study, air-stable n-type transistor fabrication, and CMOS integration platform have also been demonstrated. On the basis of the above achievement, I have further demonstrated various kinds of applications including AMOLED display electronics, PMOS and CMOS logic circuits, flexible and transparent electronics. The dissertation is structured as follows. First, chapter 1 gives a brief introduction to the electronic properties of carbon nanotubes, which serves as the background knowledge for the following chapters. In chapter 2, I will present our approach of fabricating wafer-scale uniform semiconducting carbon nanotube thin-film transistors and demonstrate their application in display electronics and logic circuits. Following that, more detailed information about carbon nanotube thin-film transistor based active matrix organic light-emitting diode (AMOLED) displays is discussed in chapter 3. And in chapter 4, a technology to fabricate air-stable n-type semiconducting nanotube thin-film transistor is developed and complementary metal--oxide--semiconductor (CMOS) logic circuits are demonstrated. Chapter 5 discusses the application of carbon nanotubes in transparent and flexible electronics. After that, in chapter 6, a simple and low cost nanotube separation method is introduced and the electrical performance of separated nanotubes with different diameter is studied. Finally, in chapter 7 a brief summary is drawn and some future research directions are proposed with preliminary results.

Electronics: State of the Art No. 2.

ERIC Educational Resources Information Center

Gosling, W.

1979-01-01

Reviewed is a brief history of electronics technology, from the early beginnings of vacuum devices to development of solid state devices, silicon fabrication in the use of transistors, and integrated circuits. Educational needs at the university or polytechnic level are discussed. (CS)

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Technical Reports Server (NTRS)

Pavlidis, Dimitris

1991-01-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Astrophysics Data System (ADS)

Pavlidis, Dimitris

1991-02-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Photosensitive graphene transistors.

PubMed

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Producing Interactive Educational Radio Programs for Distance Education

ERIC Educational Resources Information Center

Yuzer, T. Volkan; Kurubacak, Gulsun

2004-01-01

It is not surprising that the interactivity affects radio and its applications. Besides, after radio began its first broadcasting, new inventions affected its development two ways: 1) the first one was the technological developments of sciences. For instance, the invention of transistors made it possible to create very small radio machines, and…

All solution processed organic thin film transistor-backplane with printing technology for electrophoretic display

USGS Publications Warehouse

Lee, Myung W.; Song, C.K.

2012-01-01

In this study, solution processes were developed for backplane using an organic thin film transistor (OTFT) as a driving device for an electrophoretic display (EPD) panel. The processes covered not only the key device of OTFTs but also interlayer and pixel electrodes. The various materials and printing processes were adopted to achieve the requirements of devices and functioning layers. The performance of OTFT of the backplane was sufficient to drive EPD sheet by producing a mobility of 0.12 cm2/v x sec and on/off current ratio of 10(5).

Ion-Sensitive Field-Effect Transistor for Biological Sensing

PubMed Central

Lee, Chang-Soo; Kim, Sang Kyu; Kim, Moonil

2009-01-01

In recent years there has been great progress in applying FET-type biosensors for highly sensitive biological detection. Among them, the ISFET (ion-sensitive field-effect transistor) is one of the most intriguing approaches in electrical biosensing technology. Here, we review some of the main advances in this field over the past few years, explore its application prospects, and discuss the main issues, approaches, and challenges, with the aim of stimulating a broader interest in developing ISFET-based biosensors and extending their applications for reliable and sensitive analysis of various biomolecules such as DNA, proteins, enzymes, and cells. PMID:22423205

Radiation and Thermal Cycling Effects on EPC1001 Gallium Nitride Power Transistors

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Scheick, Leif Z.; Lauenstein, Jean M.; Casey, Megan C.; Hammoud, Ahmad

2012-01-01

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Information pertaining to performance of electronic parts and systems under hostile environments is very scarce, especially for new devices. Such data is very critical so that proper design is implemented in order to ensure mission success and to mitigate risks associated with exposure of on-board systems to the operational environment. In this work, newly-developed enhancement-mode field effect transistors (FET) based on gallium nitride (GaN) technology were exposed to various particles of ionizing radiation and to long-term thermal cycling over a wide temperature range. Data obtained on control (un-irradiated) and irradiated samples of these power transistors are presented and the results are discussed.

Charge injection in solution-processed organic field-effect transistors: physics, models and characterization methods.

PubMed

Natali, Dario; Caironi, Mario

2012-03-15

A high-mobility organic semiconductor employed as the active material in a field-effect transistor does not guarantee per se that expectations of high performance are fulfilled. This is even truer if a downscaled, short channel is adopted. Only if contacts are able to provide the device with as much charge as it needs, with a negligible voltage drop across them, then high expectations can turn into high performances. It is a fact that this is not always the case in the field of organic electronics. In this review, we aim to offer a comprehensive overview on the subject of current injection in organic thin film transistors: physical principles concerning energy level (mis)alignment at interfaces, models describing charge injection, technologies for interface tuning, and techniques for characterizing devices. Finally, a survey of the most recent accomplishments in the field is given. Principles are described in general, but the technologies and survey emphasis is on solution processed transistors, because it is our opinion that scalable, roll-to-roll printing processing is one, if not the brightest, possible scenario for the future of organic electronics. With the exception of electrolyte-gated organic transistors, where impressively low width normalized resistances were reported (in the range of 10 Ω·cm), to date the lowest values reported for devices where the semiconductor is solution-processed and where the most common architectures are adopted, are ∼10 kΩ·cm for transistors with a field effect mobility in the 0.1-1 cm(2)/Vs range. Although these values represent the best case, they still pose a severe limitation for downscaling the channel lengths below a few micrometers, necessary for increasing the device switching speed. Moreover, techniques to lower contact resistances have been often developed on a case-by-case basis, depending on the materials, architecture and processing techniques. The lack of a standard strategy has hampered the progress of the field for a long time. Only recently, as the understanding of the rather complex physical processes at the metal/semiconductor interfaces has improved, more general approaches, with a validity that extends to several materials, are being proposed and successfully tested in the literature. Only a combined scientific and technological effort, on the one side to fully understand contact phenomena and on the other to completely master the tailoring of interfaces, will enable the development of advanced organic electronics applications and their widespread adoption in low-cost, large-area printed circuits. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

NASA Astrophysics Data System (ADS)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown to provide consistently accurate values for base sheet resistance for both Si- and SiGe-base transistors over a wide range of temperatures. A model for plasma-induced bandgap narrowing suitable for implementation in a numerical simulator has been developed. The appropriate method of incorporating this model in a drift -diffusion solver is described. The importance of including this model for low temperature simulation is demonstrated. With these models in place, the enhanced simulator has been used for evaluating and designing the Si- and SiGe-base bipolar transistors. Silicon-germanium heterojunction bipolar transistors offer significant performance and cost advantages over conventional technologies in the production of integrated circuits for communications, computer and transportation applications. Their high frequency performance at low cost, will find widespread use in the currently exploding wireless communication market. However, the high performance SiGe-base transistors are prone to have a low common-emitter breakdown voltage. In this dissertation, a modification in the collector design is proposed for improving the breakdown voltage without sacrificing the high frequency performance. A comprehensive simulation study of p-n-p SiGe-base transistors has been performed. Different figures of merit such as drive current, current gain, cut -off frequency and Early voltage were compared between a graded germanium profile and an abrupt germanium profile. The differences in the performance level between the two profiles diminishes as the base width is scaled down.

Development of high-performance printed organic field-effect transistors and integrated circuits.

PubMed

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels.

PubMed

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshiari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-09-02

In this paper we present a novel, quadruple well process developed in a modern 0.18 mm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 mm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Towards end to end technology modeling: Carbon nanotube and thermoelectric devices

NASA Astrophysics Data System (ADS)

Salamat, Shuaib

The goal of this work is to demonstrate the feasibility of end-to-end ("atoms to applications") technology modeling. Two different technologies were selected to drive this work. The first technology is carbon nanotube field-effect transistors (CNTFETs), and the goal is to model device level variability and identify the origin of variations in these devices. Recently, there has been significant progress in understanding the physics of carbon nanotube electronic devices and in identifying their potential applications. For nanotubes, the carrier mobility is high, so low bias transport across several hundred nanometers is nearly ballistic, and the deposition of high-k gate dielectrics does not degrade the carrier mobility. The conduction and valence bands are symmetric (useful for complimentary application) and the bandstructure is direct (enables optical emission). Because of these striking features, carbon nanotubes (CNTs) have received much attention. Carbon nanotubes field-effect transistors (CNTFETs) are one of the main potential candidates for large-area electronics. In this research model, systematic simulation approaches are applied to understand the intrinsic performance variability in CNTFETs. It is shown that control over diameter distribution is critically important process parameter for attaining high performance transistors and circuits with characteristics rivaling those of state-of-the-art Si technology. The second technology driver concerns the development of a multi-scale framework for thermoelectric device design. An essential step in the development of new materials and devices for thermoelectrics is to develop accurate, efficient, and realistic models. The ready availability of user friendly ab-initio codes and the ever-increasing computing power have made the band structure calculations routine. Thermoelectric device design, however, is still largely done at the effective mass level. Tools that allow device designers to make use of sophisticated electronic structure and phonon dispersion calculations are needed. We have developed a proof-of-concept, integrated, multi-scale design framework for TE technology. Beginning from full electronic and phonon dispersions, Landauer approach is used to evaluate the temperature-dependent thermoelectric transport parameters needed for device simulation. A comprehensive SPICE-based model for electro-thermal transport has also been developed to serve as a bridge between the materials and device level descriptions and the system level simulations. This prototype framework has been used to design a thermoelectric cooler for managing hot spots in the integrated circuit chips. What's more, as a byproduct of this research a suite of educational and simulation resources have been developed and deployed, on the nanoHUB.org science gateway to serve as a resource for the TE community.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dell'Erba, Giorgio; Natali, Dario; Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano

Ambipolar semiconducting polymers, characterized by both high electron (μ{sub e}) and hole (μ{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μ{sub h} = 0.29 cm{sup 2}/V s and μ{sub e} = 0.001more » cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μ{sub e} = 0.12 cm{sup 2}/V s and μ{sub h} = 8 × 10{sup −4} cm{sup 2}/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.« less

Physics and Entrepreneurship: A Small Business Perspective

NASA Astrophysics Data System (ADS)

Cleveland, Jason

2013-03-01

DARPA's Microsystems Technology Office, MTO, conceives and develops a wide range of technologies to benefit the US warfighter, from exotic GaN transistors to high-power fiber lasers, highly efficient embedded computer systems to synthetic biology. MTO has world class electrical and mechanical engineers, but we also have a cadre of extremely capable physicists, whose complementary skillset has been absolutely essential to identifying promising technological avenues for the office and for the agency. In this talk I will explain the DARPA model of technology development, using real examples from MTO, highlighting programs where physics-based insights have led to important new capabilities for the Dept of Defense.

Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

NASA Astrophysics Data System (ADS)

Lee, Sol Kyu; Seok, Ki Hwan; Park, Jae Hyo; Kim, Hyung Yoon; Chae, Hee Jae; Jang, Gil Su; Lee, Yong Hee; Han, Ji Su; Joo, Seung Ki

2016-06-01

Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid-crystal display (LCD) back-planes, because strong laser energy of ELA can seriously damage the other layers. Here, we propose a novel high-performance BG poly-Si TFT using Ni silicide seed-induced lateral crystallization (SILC). The SILC technology renders it possible to ensure low damage in the layers, smooth surface, and longitudinal large grains in the channel. It was observed that the electrical properties exhibited a steep subthreshold slope of 110 mV/dec, high field-effect mobility of 304 cm2/Vsec, high I on/ I off ratio of 5.9 × 107, and a low threshold voltage of -3.9 V.

Carbon nanostructure-based field-effect transistors for label-free chemical/biological sensors.

PubMed

Hu, PingAn; Zhang, Jia; Li, Le; Wang, Zhenlong; O'Neill, William; Estrela, Pedro

2010-01-01

Over the past decade, electrical detection of chemical and biological species using novel nanostructure-based devices has attracted significant attention for chemical, genomics, biomedical diagnostics, and drug discovery applications. The use of nanostructured devices in chemical/biological sensors in place of conventional sensing technologies has advantages of high sensitivity, low decreased energy consumption and potentially highly miniaturized integration. Owing to their particular structure, excellent electrical properties and high chemical stability, carbon nanotube and graphene based electrical devices have been widely developed for high performance label-free chemical/biological sensors. Here, we review the latest developments of carbon nanostructure-based transistor sensors in ultrasensitive detection of chemical/biological entities, such as poisonous gases, nucleic acids, proteins and cells.

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

PubMed

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

20 Discoveries that Shaped Our Lives: Century of the Sciences.

ERIC Educational Resources Information Center

Judson, Horace Freeland

1984-01-01

Describes (in separate articles) 20 developments in science, technology, and medicine that were made during the twentieth century and had significant impact on society. They include discoveries related to intelligence tests, plastics, aviation, antibiotics, genetics, evolution, birth control, computers, transistors, DNA, lasers, statistics,…

SiC Field Effect Transistor Technology Demonstrating Prolonged Stable Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Okojie, Robert S.; Beheim, Glenn M.; Meredith, Roger; Ferrier, Terry

2006-01-01

While there have been numerous reports of short-term transistor operation at 500 degree C or above, these devices have previously not demonstrated sufficient long-term operational durability at 500 degree C to be considered viable for most envisioned applications. This paper reports the development of Silicone Carbi field effect transistors capable of long-term electrical operation at 500 degree C. A 6H-SiC MESFET was packaged and subjected to continuous electrical operation while residing in a 500 degree C oven in oxidizing air atmosphere for over 2400 hours. The transistor gain, saturation current (IDSS), and on-resistance (RDS) changed by less than 20% from initial values throughout the duration of the biased 500 degree C test. Another high-temperature packaged 6H-SiC MESFET was employed to form a simple one-stage high-temperature low-frequency voltage amplifier. This single-stage common-source amplifier demonstrated stable continuous electrical operation (negligible changes to gain and operating biases) for over 600 hours while residing in a 500 degree C air ambient oven. In both cases, increased leakage from annealing of the Schottky gate-to-channel diode was the dominant transistor degradation mechanism that limited the duration of 500 degree C electrical operation.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Advanced electrical power system technology for the all electric aircraft

NASA Technical Reports Server (NTRS)

Finke, R. C.; Sundberg, G. R.

1983-01-01

The application of advanced electric power system technology to an all electric airplane results in an estimated reduction of the total takeoff gross weight of over 23,000 pounds for a large airplane. This will result in a 5 to 10 percent reduction in direct operating costs (DOC). Critical to this savings is the basic electrical power system component technology. These advanced electrical power components will provide a solid foundation for the materials, devices, circuits, and subsystems needed to satisfy the unique requirements of advanced all electric aircraft power systems. The program for the development of advanced electrical power component technology is described. The program is divided into five generic areas: semiconductor devices (transistors, thyristors, and diodes); conductors (materials and transmission lines); dielectrics; magnetic devices; and load management devices. Examples of progress in each of the five areas are discussed. Bipolar power transistors up to 1000 V at 100 A with a gain of 10 and a 0.5 microsec rise and fall time are presented. A class of semiconductor devices with a possibility of switching up to 100 kV is described. Solid state power controllers for load management at 120 to 1000 V and power levels to 25 kW were developed along with a 25 kW, 20 kHz transformer weighing only 3.2 kg.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

PubMed Central

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency. PMID:27873817

First fabrication of a silicon vertical JFET for power distribution in high energy physics applications

NASA Astrophysics Data System (ADS)

Fernández-Martínez, Pablo; Flores, D.; Hidalgo, S.; Quirion, D.; Durà, R.; Ullán, M.

2018-01-01

A new vertical JFET transistor has been recently developed at the IMB-CNM, taking advantage of a deep-trenched 3D technology to achieve vertical conduction and low switch-off voltage. The silicon V-JFET transistors were mainly conceived to work as rad-hard protection switches for the renewed HV powering scheme (HV-MUX) of the ATLAS upgraded tracker. This work presents the features of the first batch of V-JFETs produced at the IMB-CNM clean room, together with the results of a full pre-irradiation characterization of the fabricated prototypes. Details of the technological process are provided and the outcome quality is also evaluated with the aid of reverse engineering techniques. Concerning the electrical performance of the prototypes, promising results were obtained, already meeting most of the HV-MUX specifications, both at room and below-zerotemperatures.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

From transistor to trapped-ion computers for quantum chemistry.

PubMed

Yung, M-H; Casanova, J; Mezzacapo, A; McClean, J; Lamata, L; Aspuru-Guzik, A; Solano, E

2014-01-07

Over the last few decades, quantum chemistry has progressed through the development of computational methods based on modern digital computers. However, these methods can hardly fulfill the exponentially-growing resource requirements when applied to large quantum systems. As pointed out by Feynman, this restriction is intrinsic to all computational models based on classical physics. Recently, the rapid advancement of trapped-ion technologies has opened new possibilities for quantum control and quantum simulations. Here, we present an efficient toolkit that exploits both the internal and motional degrees of freedom of trapped ions for solving problems in quantum chemistry, including molecular electronic structure, molecular dynamics, and vibronic coupling. We focus on applications that go beyond the capacity of classical computers, but may be realizable on state-of-the-art trapped-ion systems. These results allow us to envision a new paradigm of quantum chemistry that shifts from the current transistor to a near-future trapped-ion-based technology.

From transistor to trapped-ion computers for quantum chemistry

PubMed Central

Yung, M.-H.; Casanova, J.; Mezzacapo, A.; McClean, J.; Lamata, L.; Aspuru-Guzik, A.; Solano, E.

2014-01-01

Over the last few decades, quantum chemistry has progressed through the development of computational methods based on modern digital computers. However, these methods can hardly fulfill the exponentially-growing resource requirements when applied to large quantum systems. As pointed out by Feynman, this restriction is intrinsic to all computational models based on classical physics. Recently, the rapid advancement of trapped-ion technologies has opened new possibilities for quantum control and quantum simulations. Here, we present an efficient toolkit that exploits both the internal and motional degrees of freedom of trapped ions for solving problems in quantum chemistry, including molecular electronic structure, molecular dynamics, and vibronic coupling. We focus on applications that go beyond the capacity of classical computers, but may be realizable on state-of-the-art trapped-ion systems. These results allow us to envision a new paradigm of quantum chemistry that shifts from the current transistor to a near-future trapped-ion-based technology. PMID:24395054

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Biomolecular detection using a metal semiconductor field effect transistor

NASA Astrophysics Data System (ADS)

Estephan, Elias; Saab, Marie-Belle; Buzatu, Petre; Aulombard, Roger; Cuisinier, Frédéric J. G.; Gergely, Csilla; Cloitre, Thierry

2010-04-01

In this work, our attention was drawn towards developing affinity-based electrical biosensors, using a MESFET (Metal Semiconductor Field Effect Transistor). Semiconductor (SC) surfaces must be prepared before the incubations with biomolecules. The peptides route was adapted to exceed and bypass the limits revealed by other types of surface modification due to the unwanted unspecific interactions. As these peptides reveal specific recognition of materials, then controlled functionalization can be achieved. Peptides were produced by phage display technology using a library of M13 bacteriophage. After several rounds of bio-panning, the phages presenting affinities for GaAs SC were isolated; the DNA of these specific phages were sequenced, and the peptide with the highest affinity was synthesized and biotinylated. To explore the possibility of electrical detection, the MESFET fabricated with the GaAs SC were used to detect the streptavidin via the biotinylated peptide in the presence of the bovine Serum Albumin. After each surface modification step, the IDS (current between the drain and the source) of the transistor was measured and a decrease in the intensity was detected. Furthermore, fluorescent microscopy was used in order to prove the specificity of this peptide and the specific localisation of biomolecules. In conclusion, the feasibility of producing an electrical biosensor using a MESFET has been demonstrated. Controlled placement, specific localization and detection of biomolecules on a MESFET transistor were achieved without covering the drain and the source. This method of functionalization and detection can be of great utility for biosensing application opening a new way for developing bioFETs (Biomolecular Field-Effect Transistor).

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Variability-aware compact modeling and statistical circuit validation on SRAM test array

NASA Astrophysics Data System (ADS)

Qiao, Ying; Spanos, Costas J.

2016-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry's 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCarthy, M. A.; Liu, B.; Donoghue, E. P.

2011-01-01

Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

Nanopore extended field-effect transistor for selective single-molecule biosensing.

PubMed

Ren, Ren; Zhang, Yanjun; Nadappuram, Binoy Paulose; Akpinar, Bernice; Klenerman, David; Ivanov, Aleksandar P; Edel, Joshua B; Korchev, Yuri

2017-09-19

There has been a significant drive to deliver nanotechnological solutions to biosensing, yet there remains an unmet need in the development of biosensors that are affordable, integrated, fast, capable of multiplexed detection, and offer high selectivity for trace analyte detection in biological fluids. Herein, some of these challenges are addressed by designing a new class of nanoscale sensors dubbed nanopore extended field-effect transistor (nexFET) that combine the advantages of nanopore single-molecule sensing, field-effect transistors, and recognition chemistry. We report on a polypyrrole functionalized nexFET, with controllable gate voltage that can be used to switch on/off, and slow down single-molecule DNA transport through a nanopore. This strategy enables higher molecular throughput, enhanced signal-to-noise, and even heightened selectivity via functionalization with an embedded receptor. This is shown for selective sensing of an anti-insulin antibody in the presence of its IgG isotype.Efficient detection of single molecules is vital to many biosensing technologies, which require analytical platforms with high selectivity and sensitivity. Ren et al. combine a nanopore sensor and a field-effect transistor, whereby gate voltage mediates DNA and protein transport through the nanopore.

Highly sensitive protein detection using a plasmonic field effect transistor (Conference Presentation)

NASA Astrophysics Data System (ADS)

Shokri-Kojori, Hossein; Ji, Yiwen; Han, Xu; Paik, Younghun; Braunschweig, Adam; Kim, Sung Jin

2016-03-01

Localized surface Plasmon Resonance (LSPR) is a nanoscale phenomenon which presents strong resonance associated with noble metal nanostructures. This plasmon resonance based technology enables highly sensitive detection for chemical and biological applications. Recently, we have developed a plasmon field effect transistor (FET) that enables direct plasmonic-to-electric signal conversion with signal amplification. The plasmon FET consists of back-gated field effect transistor incorporated with gold nanoparticles on top of the FET channel. The gold nanostructures are physically separated from transistor electrodes and can be functionalized for a specific biological application. In this presentation, we report a successful demonstration of a model system to detect Con A proteins using Carbohydrate linkers as a capture molecule. The plasmon FET detected a very low concentration of Con A (0.006 mg/L) while it offers a wide dynamic range of 0.006-50 mg/L. In this demonstration, we used two-color light sources instead of a bulky spectrometer to achieve high sensitivity and wide dynamic range. The details of two-color based differential measurement method will be discussed. This novel protein-based sensor has several advantages such as extremely small size for point-of-care system, multiplexing capability, no need of complex optical geometry.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

NASA Astrophysics Data System (ADS)

Li, Can; Liao, Cong-Wei; Yu, Tian-Bao; Ke, Jian-Yuan; Huang, Sheng-Xiang; Deng, Lian-Wen

2018-02-01

Not Available Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600, the National Natural Science Foundation of China under Grant No 61404002, and the Science and Technology Project of Hunan Province under Grant No 2015JC3041.

A Brief History of ... Semiconductors

ERIC Educational Resources Information Center

Jenkins, Tudor

2005-01-01

The development of studies in semiconductor materials is traced from its beginnings with Michael Faraday in 1833 to the production of the first silicon transistor in 1954, which heralded the age of silicon electronics and microelectronics. Prior to the advent of band theory, work was patchy and driven by needs of technology. However, the arrival…

Acoustic charge transport technology investigation for advanced development transponder

NASA Technical Reports Server (NTRS)

Kayalar, S.

1993-01-01

Acoustic charge transport (ACT) technology has provided a basis for a new family of analog signal processors, including a programmable transversal filter (PTF). Through monolithic integration of ACT delay lines with GaAs metal semiconductor field effect transistor (MESFET) digital memory and controllers, these devices significantly extend the performance of PTF's. This article introduces the basic operation of these devices and summarizes their present and future specifications. The production and testing of these devices indicate that this new technology is a promising one for future space applications.

The Warm, Rich Sound of Valve Guitar Amplifiers

ERIC Educational Resources Information Center

Keeports, David

2017-01-01

Practical solid state diodes and transistors have made glass valve technology nearly obsolete. Nevertheless, valves survive largely because electric guitar players much prefer the sound of valve amplifiers to the sound of transistor amplifiers. This paper discusses the introductory-level physics behind that preference. Overdriving an amplifier…

Interface engineering of semiconductor/dielectric heterojunctions toward functional organic thin-film transistors.

PubMed

Zhang, Hongtao; Guo, Xuefeng; Hui, Jingshu; Hu, Shuxin; Xu, Wei; Zhu, Daoben

2011-11-09

Interface modification is an effective and promising route for developing functional organic field-effect transistors (OFETs). In this context, however, researchers have not created a reliable method of functionalizing the interfaces existing in OFETs, although this has been crucial for the technological development of high-performance CMOS circuits. Here, we demonstrate a novel approach that enables us to reversibly photocontrol the carrier density at the interface by using photochromic spiropyran (SP) self-assembled monolayers (SAMs) sandwiched between active semiconductors and gate insulators. Reversible changes in dipole moment of SPs in SAMs triggered by lights with different wavelengths produce two distinct built-in electric fields on the OFET that can modulate the channel conductance and consequently threshold voltage values, thus leading to a low-cost noninvasive memory device. This concept of interface functionalization offers attractive new prospects for the development of organic electronic devices with tailored electronic and other properties.

The Development of Si and SiGe Technologies for Microwave and Millimeter-Wave Integrated Circuits

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Alterovitz, Samuel A.; Katehi, Linda P. B.; Bhattacharya, Pallab K.

1997-01-01

Historically, microwave technology was developed by military and space agencies from around the world to satisfy their unique radar, communication, and science applications. Throughout this development phase, the sole goal was to improve the performance of the microwave circuits and components comprising the systems. For example, power amplifiers with output powers of several watts over broad bandwidths, low noise amplifiers with noise figures as low as 3 dB at 94 GHz, stable oscillators with low noise characteristics and high output power, and electronically steerable antennas were required. In addition, the reliability of the systems had to be increased because of the high monetary and human cost if a failure occurred. To achieve these goals, industry, academia and the government agencies supporting them chose to develop technologies with the greatest possibility of surpassing the state of the art performance. Thus, Si, which was already widely used for digital circuits but had material characteristics that were perceived to limit its high frequency performance, was bypassed for a progression of devices starting with GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and ending with InP Pseudomorphic High Electron Mobility Transistors (PHEMTs). For each new material or device structure, the electron mobility increased, and therefore, the high frequency characteristics of the device were improved. In addition, ultra small geometry lithographic processes were developed to reduce the gate length to 0.1 pm which further increases the cutoff frequency. The resulting devices had excellent performance through the millimeter-wave spectrum.

Advanced electrical power system technology for the all electric aircraft

NASA Technical Reports Server (NTRS)

Finke, R. C.; Sundberg, G. R.

1983-01-01

The application of advanced electric power system technology to an all electric airplane results in an estimated reduction of the total takeoff gross weight of over 23,000 pounds for a large airplane. This will result in a 5 to 10 percent reduction in direct operating costs (DOC). Critical to this savings is the basic electrical power system component technology. These advanced electrical power components will provide a solid foundation for the materials, devices, circuits, and subsystems needed to satisfy the unique requirements of advanced all electric aircraft power systems. The program for the development of advanced electrical power component technology is described. The program is divided into five generic areas: semiconductor devices (transistors, thyristors, and diodes); conductors (materials and transmission lines); dielectrics; magnetic devices; and load management devices. Examples of progress in each of the five areas are discussed. Bipolar power transistors up to 1000 V at 100 A with a gain of 10 and a 0.5 microsec rise and fall time are presented. A class of semiconductor devices with a possibility of switching up to 100 kV is described. Solid state power controllers for load management at 120 to 1000 V and power levels to 25 kW were developed along with a 25 kW, 20 kHz transformer weighing only 3.2 kg. Previously announced in STAR as N83-24764

High voltage power transistor development

NASA Technical Reports Server (NTRS)

Hower, P. L.

1981-01-01

Design considerations, fabrication procedures, and methods of evaluation for high-voltage power-transistor development are discussed. Technique improvements such as controlling the electric field at the surface and perserving lifetimes in the collector region which have advanced the state of the art in high-voltage transistors are discussed. These improvements can be applied directly to the development of 1200 volt, 200 ampere transistors.

Development and Experimental Evaluation of an Automated Multi-Media Course on Transistors.

ERIC Educational Resources Information Center

Whitted, J.H., Jr.; And Others

A completely automated multi-media self-study program for teaching a portion of electronic solid-state fundamentals was developed. The subject matter areas included were fundamental theory of transistors, transistor amplifier fundamentals, and simple mathematical analysis of transistors including equivalent circuits, parameters, and characteristic…

Fabrication and characterization on reduced graphene oxide field effect transistor (RGOFET) based biosensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rashid, A. Diyana; Ruslinda, A. Rahim, E-mail: ruslinda@unimap.edu.my; Fatin, M. F.

2016-07-06

The fabrication and characterization on reduced graphene oxide field effect transistor (RGO-FET) were demonstrated using a spray deposition method for biological sensing device purpose. A spray method is a fast, low-cost and simple technique to deposit graphene and the most promising technology due to ideal coating on variety of substrates and high production speed. The fabrication method was demonstrated for developing a label free aptamer reduced graphene oxide field effect transistor biosensor. Reduced graphene oxide (RGO) was obtained by heating on hot plate fixed at various temperatures of 100, 200 and 300°C, respectively. The surface morphology of RGO were examinedmore » via atomic force microscopy to observed the temperature effect of produced RGO. The electrical measurement verify the performance of electrical conducting RGO-FET at temperature 300°C is better as compared to other temperature due to the removal of oxygen groups in GO. Thus, reduced graphene oxide was a promising material for biosensor application.« less

Large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

Fluctuations in the electrical resistance at the interface of atomically thin materials and metals, or the contact noise, can adversely affect the device performance but remains largely unexplored. We have investigated contact noise in graphene field effect transistors of varying device geometry and contact configuration, with channel carrier mobility ranging from 5,000 to 80,000 cm2V-1s-1. A phenomenological model developed for contact noise due to current crowding for two dimensional conductors, shows a dominant contact contribution to the measured resistance noise in all graphene field effect transistors when measured in the two-probe or invasive four probe configurations, and surprisingly, also in nearly noninvasive four probe (Hall bar) configuration in the high mobility devices. We identify the fluctuating electrostatic environment of the metal-channel interface as the major source of contact noise, which could be generic to two dimensional material-based electronic devices. The work was financially supported by the Department of Science and Technology, India and Tokyo Electron Limited.

A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

PubMed Central

Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

2012-01-01

Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Subtractive Plasma-Assisted-Etch Process for Developing High Performance Nanocrystalline Zinc-Oxide Thin-Film-Transistors

DTIC Science & Technology

2015-03-26

THIN - FILM - TRANSISTORS THESIS Thomas M. Donigan, First Lieutenant, USAF AFIT-ENG-MS-15-M-027 DEPARTMENT OF THE AIR FORCE AIR UNIVERSITY AIR...DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS THESIS Presented to the Faculty Department of Electrical and...15-M-027 SUBTRACTIVE PLASMA-ASSISTED-ETCH PROCESS FOR DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Development of GaN-based microchemical sensor nodes

NASA Technical Reports Server (NTRS)

Prokopuk, Nicholas; Son, Kyung-Ah; George, Thomas; Moon, Jeong S.

2005-01-01

Sensors based III-N technology are gaining significant interest due to their potential for monolithic integration of RF transceivers and light sources and the capability of high temperature operations. We are developing a GaN-based micro chemical sensor node for remote detection of chemical toxins, and present electrical responses of AlGaN/GaN HEMT (High Electron Mobility Transistor) sensors to chemical toxins as well as other common gases.

Carbon nanotube transistors scaled to a 40-nanometer footprint.

PubMed

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Twist-controlled resonant tunnelling in graphene/boron nitride/graphene heterostructures.

PubMed

Mishchenko, A; Tu, J S; Cao, Y; Gorbachev, R V; Wallbank, J R; Greenaway, M T; Morozov, V E; Morozov, S V; Zhu, M J; Wong, S L; Withers, F; Woods, C R; Kim, Y-J; Watanabe, K; Taniguchi, T; Vdovin, E E; Makarovsky, O; Fromhold, T M; Fal'ko, V I; Geim, A K; Eaves, L; Novoselov, K S

2014-10-01

Recent developments in the technology of van der Waals heterostructures made from two-dimensional atomic crystals have already led to the observation of new physical phenomena, such as the metal-insulator transition and Coulomb drag, and to the realization of functional devices, such as tunnel diodes, tunnel transistors and photovoltaic sensors. An unprecedented degree of control of the electronic properties is available not only by means of the selection of materials in the stack, but also through the additional fine-tuning achievable by adjusting the built-in strain and relative orientation of the component layers. Here we demonstrate how careful alignment of the crystallographic orientation of two graphene electrodes separated by a layer of hexagonal boron nitride in a transistor device can achieve resonant tunnelling with conservation of electron energy, momentum and, potentially, chirality. We show how the resonance peak and negative differential conductance in the device characteristics induce a tunable radiofrequency oscillatory current that has potential for future high-frequency technology.

Fullerenes, carbon nanotubes, and graphene for molecular electronics.

PubMed

Pinzón, Julio R; Villalta-Cerdas, Adrián; Echegoyen, Luis

2012-01-01

With the constant growing complexity of electronic devices, the top-down approach used with silicon based technology is facing both technological and physical challenges. Carbon based nanomaterials are good candidates to be used in the construction of electronic circuitry using a bottom-up approach, because they have semiconductor properties and dimensions within the required physical limit to establish electrical connections. The unique electronic properties of fullerenes for example, have allowed the construction of molecular rectifiers and transistors that can operate with more than two logical states. Carbon nanotubes have shown their potential to be used in the construction of molecular wires and FET transistors that can operate in the THz frequency range. On the other hand, graphene is not only the most promising material for replacing ITO in the construction of transparent electrodes but it has also shown quantum Hall effect and conductance properties that depend on the edges or chemical doping. The purpose of this review is to present recent developments on the utilization carbon nanomaterials in molecular electronics.

Mechanically adjustable single-molecule transistors and stencil mask nanofabrication of high-resolution scanning probes

NASA Astrophysics Data System (ADS)

Champagne, Alexandre

This dissertation presents the development of two original experimental techniques to probe nanoscale objects. The first one studies electronic transport in single organic molecule transistors in which the source-drain electrode spacing is mechanically adjustable. The second involves the fabrication of high-resolution scanning probe microscopy sensors using a stencil mask lithography technique. We describe the fabrication of transistors in which a single organic molecule can be incorporated. The source and drain leads of these transistors are freely suspended above a flexible substrate, and their spacing can be adjusted by bending the substrate. We detail the technology developed to carry out measurements on these samples. We study electronic transport in single C60 molecules at low temperature. We observe Coulomb blockaded transport and can resolve the discrete energy spectrum of the molecule. We are able to mechanically tune the spacing between the electrodes (over a range of 5 A) to modulate the lead-molecule coupling, and can electrostatically tune the energy levels on the molecule by up to 160 meV using a gate electrode. Initial progress in studying different transport regimes in other molecules is also discussed. We present a lithographic process that allows the deposition of metal nanostructures with a resolution down to 10 nm directly onto atomic force microscope (AFM) tips. We show that multiple layers of lithography can be deposited and aligned. We fabricate high-resolution magnetic force microscopy (MFM) probes using this method and discuss progress to fabricate other scanning probe microscopy (SPM) sensors.

New developments in power semiconductors

NASA Technical Reports Server (NTRS)

Sundberg, G. R.

1983-01-01

This paper represents an overview of some recent power semiconductor developments and spotlights new technologies that may have significant impact for aircraft electric secondary power. Primary emphasis will be on NASA-Lewis-supported developments in transistors, diodes, a new family of semiconductors, and solid-state remote power controllers. Several semiconductor companies that are moving into the power arena with devices rated at 400 V and 50 A and above are listed, with a brief look at a few devices.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

High Resolution Adjustable Mirror Control for X-ray Astronomy

NASA Astrophysics Data System (ADS)

Trolier-McKinstry, Susan

We propose to build and test thin film transistor control circuitry for a new highresolution adjustable X-ray mirror technology. This control circuitry will greatly simplify the wiring scheme to address individual actuator cells. The result will be a transformative improvement for the X-ray Surveyor mission concept: mathematical models, which fit the experimental data quite well, indicate that 0.5 arcsecond imaging is feasible through this technique utilizing thin slumped glass substrates with uncorrected angular resolution of order 5-10 arcseconds. In order to correct for figures errors in a telescope with several square meters of collecting area, millions of actuator cells must be set and held at specific voltages. It is clearly not feasible to do this via millions of wires, each one connected to an actuator. Instead, we propose to develop and test thin-film technology that operates on the same principle as megapixel computer screens. We will develop the technologies needed to build thin film piezoelectric actuators, controlled by thin film ZnO transistors, on flexible polyimide films, and to connect those films to the back surfaces of X-ray mirrors on thin glass substrates without deforming the surface. These technologies represent a promising avenue of the development of mirrors for the X-Ray Surveyor mission concept. Such a telescope will make possible detailed studies of a wide variety of astrophysical sources. One example is the Warm-Hot Intergalactic Medium (WHIM), which is thought to account for a large fraction of the normal matter in the universe but which has not been detected unambiguously to date. Another is the growth of supermassive black holes in the early universe. This proposal supports NASA's goals of technical advancement of technologies suitable for future missions, and training of graduate students.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

The role of contact resistance in graphene field-effect devices

NASA Astrophysics Data System (ADS)

Giubileo, Filippo; Di Bartolomeo, Antonio

2017-08-01

The extremely high carrier mobility and the unique band structure, make graphene very useful for field-effect transistor applications. According to several works, the primary limitation to graphene based transistor performance is not related to the material quality, but to extrinsic factors that affect the electronic transport properties. One of the most important parasitic element is the contact resistance appearing between graphene and the metal electrodes functioning as the source and the drain. Ohmic contacts to graphene, with low contact resistances, are necessary for injection and extraction of majority charge carriers to prevent transistor parameter fluctuations caused by variations of the contact resistance. The International Technology Roadmap for Semiconductors, toward integration and down-scaling of graphene electronic devices, identifies as a challenge the development of a CMOS compatible process that enables reproducible formation of low contact resistance. However, the contact resistance is still not well understood despite it is a crucial barrier towards further improvements. In this paper, we review the experimental and theoretical activity that in the last decade has been focusing on the reduction of the contact resistance in graphene transistors. We will summarize the specific properties of graphene-metal contacts with particular attention to the nature of metals, impact of fabrication process, Fermi level pinning, interface modifications induced through surface processes, charge transport mechanism, and edge contact formation.

Development of GaN-based micro chemical sensor nodes

NASA Technical Reports Server (NTRS)

Son, Kyung-ah; Prokopuk, Nicholas; George, Thomas; Moon, Jeong S.

2005-01-01

Sensors based on III-N technology are gaining significant interest due to their potential for monolithic integration of RF transceivers and light sources and the capability of high temperature operations. We are developing a GaN-based micro chemical sensor node for remote detection of chemical toxins, and present electrical responses of AlGaN/GaN HEMT (High Electron Mobility Transistor) sensors to chemical toxins as well as other common gases.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

NASA Technical Reports Server (NTRS)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

A thin-film microprocessor with inkjet print-programmable memory

NASA Astrophysics Data System (ADS)

Myny, Kris; Smout, Steve; Rockelé, Maarten; Bhoolokam, Ajay; Ke, Tung Huei; Steudel, Soeren; Cobb, Brian; Gulati, Aashini; Rodriguez, Francisco Gonzalez; Obata, Koji; Marinkovic, Marko; Pham, Duy-Vu; Hoppe, Arne; Gelinck, Gerwin H.; Genoe, Jan; Dehaene, Wim; Heremans, Paul

2014-12-01

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through `stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many (WORM) instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks.

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil.

PubMed

Knobelspies, Stefan; Bierer, Benedikt; Daus, Alwin; Takabayashi, Alain; Salvatore, Giovanni Antonio; Cantarella, Giuseppe; Ortiz Perez, Alvaro; Wöllenstein, Jürgen; Palzer, Stefan; Tröster, Gerhard

2018-01-26

We present a gas sensitive thin-film transistor (TFT) based on an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO₂ gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits.

Methodological comparison on OLED and OLET fabrication

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Hambali, Nor Azura Malini Ahmad; Wahid, Mohamad Halim Abd; Retnasamy, Vithyacharan; Shahimin, Mukhzeer Mohamad

2018-02-01

The potential of organic semiconductor devices for light generation is demonstrated by the commercialization of display technologies based on organic light emitting diode (OLED). In OLED, organic materials play the role of light emission once the current is passed through. However, OLED do have major drawbacks whereby it suffers from photon loss and exciton quenching. Organic light emitting transistor (OLET) emerged as the new technology to compensate the efficiency and brightness loss encountered in OLED. The structure has combinational capability to switch the electronic signal such as the field effect transistor (FET) as well as light generation. The aim of this study is to methodologically compare and contrast fabrication process and evaluate feasibility of both organic light emitting diode (OLED) and organic light emitting transistor (OLET). The proposed light emitting layer in this study is poly [2-methoxy-5- (2'-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV).

Mapping brain activity with flexible graphene micro-transistors

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Tort-Colet, Núria; Guimerà-Brunet, Anton; Weinert, Julia; Rousseau, Lionel; Heimann, Axel; Drieschner, Simon; Kempski, Oliver; Villa, Rosa; Sanchez-Vives, Maria V.; Garrido, Jose A.

2017-06-01

Establishing a reliable communication interface between the brain and electronic devices is of paramount importance for exploiting the full potential of neural prostheses. Current microelectrode technologies for recording electrical activity, however, evidence important shortcomings, e.g. challenging high density integration. Solution-gated field-effect transistors (SGFETs), on the other hand, could overcome these shortcomings if a suitable transistor material were available. Graphene is particularly attractive due to its biocompatibility, chemical stability, flexibility, low intrinsic electronic noise and high charge carrier mobilities. Here, we report on the use of an array of flexible graphene SGFETs for recording spontaneous slow waves, as well as visually evoked and also pre-epileptic activity in vivo in rats. The flexible array of graphene SGFETs allows mapping brain electrical activity with excellent signal-to-noise ratio (SNR), suggesting that this technology could lay the foundation for a future generation of in vivo recording implants.

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil

PubMed Central

Bierer, Benedikt; Takabayashi, Alain; Ortiz Perez, Alvaro; Wöllenstein, Jürgen

2018-01-01

We present a gas sensitive thin-film transistor (TFT) based on an amorphous Indium–Gallium–Zinc–Oxide (a-IGZO) semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO2 gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits. PMID:29373524

Semiconductor Ion Implanters

DOE Office of Scientific and Technical Information (OSTI.GOV)

MacKinnon, Barry A.; Ruffell, John P.

In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion. Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intelmore » product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.« less

Evolution of the Intelligent Telecommunications Network.

ERIC Educational Resources Information Center

Mayo, John S.

1982-01-01

Discusses the evolution of the nationwide telecommunications network, including key technologies (transistors, communications satellites, and lasers), putting these technologies together, current and future services, and challenges for the future. (JN)

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Controlling signal transport in a carbon nanotube opto-transistor

NASA Astrophysics Data System (ADS)

Li, Jinjin; Chu, Yanhui; Zhu, Ka-Di

2016-11-01

With the highly competitive development of communication technologies, modern information manufactures place high importance on the ability to control the transmitted signal using easy miniaturization materials. A controlled and miniaturized optical information device is, therefore, vital for researchers in information and communication fields. Here we propose a controlled signal transport in a doubly clamped carbon nanotube system, where the transmitted signal can be controlled by another pump beam. Pump off results in the transmitted signal off, while pump on results in the transmitted signal on. The more pump, the more amplified output signal transmission. Analogous with traditional cavity optomechanical system, the role of optical cavity is played by a localized exciton in carbon nanotube while the role of the mechanical element is played by the nanotube vibrations, which enables the realization of an opto-transistor based on carbon nanotube. Since the signal amplification and attenuation have been observed in traditional optomechanical system, and the nanotube optomechanical system has been realized in laboratory, the proposed carbon nanotube opto-transistor could be implemented in current experiments and open the door to potential applications in modern optical networks and future quantum networks.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Satellite Power Systems (SPS) concept definition study (exhibit C)

NASA Technical Reports Server (NTRS)

Hanley, G. M.

1978-01-01

A coplanar satellite conceptual approach was defined. This effort included several trade studies related to satellite design and also construction approaches for this satellite. A transportation system, consistent with this concept, was also studied, including an electric orbit transfer vehicle and a parallel-burn heavy lift launch vehicle. Work on a solid state microwave concept continued and several alternative approaches were evaluated. Computer determination of an optimized transistor and circuit design was also continued. Experiment/verification planning resulted in the development of a total solar array and microwave technology development plan, as well as definition of near-term research to evaluate key technology issues.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Roadmap evolution: from NTRS to ITRS, from ITRS 2.0 to IRDS

NASA Astrophysics Data System (ADS)

Gargini, Paolo A.

2017-10-01

The semiconductor industry benefitted from roadmap guidance since the mid-60s. The roadmap anticipated and outlined the main needs of the semiconductor industry for years to come and identified future challenges and possible solutions. Making transistor smaller by means of advanced lithographic technologies enabled both increased integration levels and improved IC performance. The roadmap methodology allowed the removal of multiple "red brick walls". The NTRS and the ITRS constituted primarily a "bottom up" approach as standard microprocessors and memories where introduced at a blistering pace barely allowing time for system houses to integrate them in their products. The 1998 ITRS provided the vision that triggered research, development and manufacturing communities to develop a completely new transistor structure in addition to replacing aluminum interconnects with a more advanced technology. The advent of Foundries and Fabless companies transformed the electronics industry into a "top down" driven industry in the past 15 years. The ITRS adjusted to this new ecosystem and morphed into the International Roadmap for Devices and Systems (IRDS) sponsored by IEEE. The IRDS is addressing the requirements and needs of the renewed electronics industry. Furthermore, by the middle of the next decade the ability to layout integrated circuits in a 2D geometry grid will reach fundamental physical limits and the aggressive conversion to 3D architecture for integrated circuit must be pursued across the board as an avenue to continuously increasing transistor count and improving performance. EUV technology is finally approaching the manufacturing stage but with the advent of 3D monolithically integrated heterogeneous circuits approaching in the not-toodistant future should the semiconductor industry concentrate its resources on the next lithographic technology generation in order to enhance resolution or on providing a smooth transition to the new revolutionary 3D architecture of integrated circuits? It is essential for the whole semiconductor industry to come together and make fundamental choices leading to a cooperative and synchronized allocation of adequate resources to produce viable solutions that once introduced in a timely manner into manufacturing will enable the continuation of the growth of the electronic industry at a pace comparable or exceeding historical trends.

On-wafer, cryogenic characterization of ultra-low noise HEMT devices

NASA Technical Reports Server (NTRS)

Bautista, J. J.; Laskar, J.; Szydlik, P.

1995-01-01

Significant advances in the development of high electron-mobility field-effect transistors (HEMT's) have resulted in cryogenic, low-noise amplifiers (LNA's) whose noise temperatures are within an order of magnitude of the quantum noise limit (hf/k). Further advances in HEMT technology at cryogenic temperatures may eventually lead to the replacement of maser and superconducting insulator superconducting front ends in the 1- to 100-GHz frequency band. Key to identification of the best HEMT's and optimization of cryogenic LNA's are accurate and repeatable device measurements at cryogenic temperatures. This article describes the design and operation of a cryogenic coplanar waveguide probe system for the characterization and modeling of advanced semiconductor transistors at cryogenic temperatures. Results on advanced HEMT devices are presented to illustrate the utility of the measurement system.

Comprehensive review on the development of high mobility in oxide thin film transistors

NASA Astrophysics Data System (ADS)

Choi, Jun Young; Lee, Sang Yeol

2017-11-01

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility ( μ FE ), subthreshold swing (S.S) and threshold voltage ( V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Radiation Effects in III-V Nanowire Devices

DTIC Science & Technology

2016-09-01

Nanowire Devices Distribution Statement A. Approved for public release; distribution is unlimited. September 2016 HDTRA1-11-1-0021 Steven R...Name: Prof. S. R. J. Brueck Organization/Institution: University of New Mexico Project Title: Radiation Effects in III-V Nanowire Devices What are...the agency approved application or plan. The objectives of this program were to: a) develop a new nanowire transistor technology based on nanoscale

Active devices based on organic semiconductors for wearable applications.

PubMed

Barbaro, Massimo; Caboni, Alessandra; Cosseddu, Piero; Mattana, Giorgio; Bonfiglio, Annalisa

2010-05-01

Plastic electronics is an enabling technology for obtaining active (transistor based) electronic circuits on flexible and/or nonplanar surfaces. For these reasons, it appears as a perfect candidate to promote future developments of wearable electronics toward the concept of fabrics and garments made by functional (in this case, active electronic) yarns. In this paper, a panoramic view of recent achievements and future perspectives is given.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Electrical and electronic devices and components: A compilation

NASA Technical Reports Server (NTRS)

1975-01-01

Components and techniques which may be useful in the electronics industry are described. Topics discussed include transducer technology, printed-circuit technology, solid state devices, MOS transistors, Gunn device, microwave antennas, and position indicators.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

High Electron Mobility Thin‐Film Transistors Based on Solution‐Processed Semiconducting Metal Oxide Heterojunctions and Quasi‐Superlattices

PubMed Central

Lin, Yen‐Hung; Faber, Hendrik; Labram, John G.; Stratakis, Emmanuel; Sygellou, Labrini; Kymakis, Emmanuel; Hastas, Nikolaos A.; Li, Ruipeng; Zhao, Kui; Amassian, Aram; Treat, Neil D.; McLachlan, Martyn

2015-01-01

High mobility thin‐film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin‐film transistors is reported that exploits the enhanced electron transport properties of low‐dimensional polycrystalline heterojunctions and quasi‐superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band‐like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature‐dependent electron transport and capacitance‐voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas‐like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll‐to‐roll, etc.) and can be seen as an extremely promising technology for application in next‐generation large area optoelectronics such as ultrahigh definition optical displays and large‐area microelectronics where high performance is a key requirement. PMID:27660741

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs.

PubMed

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-03-07

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)-a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance-information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm.

George E. Pake Prize Lecture: Physical Sciences Research at IBM: Still at the Cutting Edge

NASA Astrophysics Data System (ADS)

Theis, Thomas

2015-03-01

The information technology revolution is in its ``build out'' phase. The foundational scientific insights and hardware inventions are now many decades old. The microelectronics industry is maturing. An increasing fraction of the total research investment is in software and services, as applications of information technology transform every business and every sector of the public and private economy. Yet IBM Research continues to make substantial investments in hardware technology and the underlying physical sciences. While some of this investment is aimed at extending the established transistor technology, an increasing fraction is aimed at longer-term and possibly disruptive research - new devices for computing, such as tunneling field-effect transistors and nanophotonic circuits, and new architectures, such as neurosynaptic systems and quantum computing. This research investment is a bet that the old foundations of information technology are ripe for reinvention. After all, today's information technology devices and systems operate far from any fundamental limits on speed and energy efficiency. But how can IBM make risky long-term research investments in an era of global competition, with financial markets focused on the short term? One important answer is partnerships. Since its early days, IBM Research has pursued innovation in information technology and innovation in the ways it conducts the business of research. By continuously evolving new models for research and development partnerships, it has extended its global reach, increased its impact on IBM's customers, and expanded the breadth and depth of its research project portfolio. Research in the physical sciences has often led the way. Currently on assignment to the Semiconductor Research Corporation.

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

NASA Astrophysics Data System (ADS)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

Molecular thermal transistor: Dimension analysis and mechanism

NASA Astrophysics Data System (ADS)

Behnia, S.; Panahinia, R.

2018-04-01

Recently, large challenge has been spent to realize high efficient thermal transistors. Outstanding properties of DNA make it as an excellent nano material in future technologies. In this paper, we introduced a high efficient DNA based thermal transistor. The thermal transistor operates when the system shows an increase in the thermal flux despite of decreasing temperature gradient. This is what called as negative differential thermal resistance (NDTR). Based on multifractal analysis, we could distinguish regions with NDTR state from non-NDTR state. Moreover, Based on dimension spectrum of the system, it is detected that NDTR state is accompanied by ballistic transport regime. The generalized correlation sum (analogous to specific heat) shows that an irregular decrease in the specific heat induces an increase in the mean free path (mfp) of phonons. This leads to the occurrence of NDTR.

Carbon nanotube transistor based high-frequency electronics

NASA Astrophysics Data System (ADS)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks.

Electrolyte-Sensing Transistor Decals Enabled by Ultrathin Microbial Nanocellulose

PubMed Central

Yuen, Jonathan D.; Walper, Scott A.; Melde, Brian J.; Daniele, Michael A.; Stenger, David A.

2017-01-01

We report an ultra-thin electronic decal that can simultaneously collect, transmit and interrogate a bio-fluid. The described technology effectively integrates a thin-film organic electrochemical transistor (sensing component) with an ultrathin microbial nanocellulose wicking membrane (sample handling component). As far as we are aware, OECTs have not been integrated in thin, permeable membrane substrates for epidermal electronics. The design of the biocompatible decal allows for the physical isolation of the electronics from the human body while enabling efficient bio-fluid delivery to the transistor via vertical wicking. High currents and ON-OFF ratios were achieved, with sensitivity as low as 1 mg·L−1. PMID:28102316

The warm, rich sound of valve guitar amplifiers

NASA Astrophysics Data System (ADS)

Keeports, David

2017-03-01

Practical solid state diodes and transistors have made glass valve technology nearly obsolete. Nevertheless, valves survive largely because electric guitar players much prefer the sound of valve amplifiers to the sound of transistor amplifiers. This paper discusses the introductory-level physics behind that preference. Overdriving an amplifier adds harmonics to an input sound. While a moderately overdriven valve amplifier produces strong even harmonics that enhance a sound, an overdriven transistor amplifier creates strong odd harmonics that can cause dissonance. The functioning of a triode valve explains its creation of even and odd harmonics. Music production software enables the examination of both the wave shape and the harmonic content of amplified sounds.

Variability aware compact model characterization for statistical circuit design optimization

NASA Astrophysics Data System (ADS)

Qiao, Ying; Qian, Kun; Spanos, Costas J.

2012-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Electrolyte-Sensing Transistor Decals Enabled by Ultrathin Microbial Nanocellulose

NASA Astrophysics Data System (ADS)

Yuen, Jonathan D.; Walper, Scott A.; Melde, Brian J.; Daniele, Michael A.; Stenger, David A.

2017-01-01

We report an ultra-thin electronic decal that can simultaneously collect, transmit and interrogate a bio-fluid. The described technology effectively integrates a thin-film organic electrochemical transistor (sensing component) with an ultrathin microbial nanocellulose wicking membrane (sample handling component). As far as we are aware, OECTs have not been integrated in thin, permeable membrane substrates for epidermal electronics. The design of the biocompatible decal allows for the physical isolation of the electronics from the human body while enabling efficient bio-fluid delivery to the transistor via vertical wicking. High currents and ON-OFF ratios were achieved, with sensitivity as low as 1 mg·L-1.

A photonic transistor device based on photons and phonons in a cavity electromechanical system

NASA Astrophysics Data System (ADS)

Jiang, Cheng; Zhu, Ka-Di

2013-01-01

We present a scheme for photonic transistors based on photons and phonons in a cavity electromechanical system, which is composed of a superconducting microwave cavity coupled to a nanomechanical resonator. Control of the propagation of photons is achieved through the interaction of microwave field (photons) and nanomechanical vibrations (phonons). By calculating the transmission spectrum of the signal field, we show that the signal field can be efficiently attenuated or amplified, depending on the power of a second ‘gating’ (pump) field. This scheme may be a promising candidate for single-photon transistors and pave the way for numerous applications in telecommunication and quantum information technologies.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

The future of computing--new architectures and new technologies.

PubMed

Warren, P

2004-02-01

All modern computers are designed using the 'von Neumann' architecture and built using silicon transistor technology. Both architecture and technology have been remarkably successful. Yet there are a range of problems for which this conventional architecture is not particularly well adapted, and new architectures are being proposed to solve these problems, in particular based on insight from nature. Transistor technology has enjoyed 50 years of continuing progress. However, the laws of physics dictate that within a relatively short time period this progress will come to an end. New technologies, based on molecular and biological sciences as well as quantum physics, are vying to replace silicon, or at least coexist with it and extend its capability. The paper describes these novel architectures and technologies, places them in the context of the kinds of problems they might help to solve, and predicts their possible manner and time of adoption. Finally it describes some key questions and research problems associated with their use.

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

The future of computing

NASA Astrophysics Data System (ADS)

Simmons, Michelle

2016-05-01

Down-scaling has been the leading paradigm of the semiconductor industry since the invention of the first transistor in 1947. However miniaturization will soon reach the ultimate limit, set by the discreteness of matter, leading to intensified research in alternative approaches for creating logic devices. This talk will discuss the development of a radical new technology for creating atomic-scale devices which is opening a new frontier of research in electronics globally. We will introduce single atom transistors where we can measure both the charge and spin of individual dopants with unique capabilities in controlling the quantum world. To this end, we will discuss how we are now demonstrating atom by atom, the best way to build a quantum computer - a new type of computer that exploits the laws of physics at very small dimensions in order to provide an exponential speed up in computational processing power.

INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

2010-10-01

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

A Novel Multi-Finger Gate Structure of AlGaN/GaN High Electron Mobility Transistor

NASA Astrophysics Data System (ADS)

Cui, Lei; Wang, Quan; Wang, Xiao-Liang; Xiao, Hong-Ling; Wang, Cui-Mei; Jiang, Li-Juan; Feng, Chun; Yin, Hai-Bo; Gong, Jia-Min; Li, Bai-Quan; Wang, Zhan-Guo

2015-05-01

Not Available Supported by the Knowledge Innovation Engineering of the Chinese Academy of Sciences under Grant No YYY-0701-02, the National Nature Science Foundation of China under Grant Nos 61106014, 61204017 and 61334002, the State Key Development Program for Basic Research of China under Grant No 2010CB327503, and the National Science and Technology Major Project of China.

Designing solution-processable air-stable liquid crystalline crosslinkable semiconductors.

PubMed

McCulloch, Iain; Bailey, Clare; Genevicius, Kristijonas; Heeney, Martin; Shkunov, Maxim; Sparrowe, David; Tierney, Steven; Zhang, Weimin; Baldwin, Rodney; Kreouzis, Theo; Andreasen, Jens W; Breiby, Dag W; Nielsen, Martin M

2006-10-15

Organic electronics technology, in which at least the semiconducting component of the integrated circuit is an organic material, offers the potential for fabrication of electronic products by low-cost printing technologies, such as ink jet, gravure offset lithography and flexography. The products will typically be of lower performance than those using the present state of the art single crystal or polysilicon transistors, but comparable to amorphous silicon. A range of prototypes are under development, including rollable electrophoretic displays, active matrix liquid crystal (LC) displays, flexible organic light emitting diode displays, low frequency radio frequency identification tag and other low performance electronics. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes the development of reactive mesogen semiconductors, which form large crosslinked LC domains on polymerization within mesophases. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed to facilitate charge transport and provide good oxidative stability, were prepared and their liquid crystalline properties evaluated. The organization and alignment of the mesogens, both before and after crosslinking, were probed by grazing incidence wide-angle X-ray scattering of thin films. Both time-of-flight and field effect transistor devices were prepared and their electrical characterization reported.

New Frontier Process using Bio Technology

DTIC Science & Technology

2013-02-05

p.58-59,2012. (2) H.Yamazaki, M.Fujii, Y.Ueoka, Y.ishikawa, M.Fujiwara, E.Takahashi, Y.Uraoka, “Highly Reliable a-InGaZnO Thin Film Transistors ...Electron Traps in SiO2/ IGZO Interface by Cyclic Capacitance–Voltage Method”, IEEE/ 2012 International Meeting for Future of Electron Devices, Kansai...Horita, Yasuaki Ishikawa, Yukiharu Uraoka, and Shinji Koh, “Characterizatio of Graphene Based Field Effect Transistors Using Nano Probing Microscopy

High-performance low-cost back-channel-etch amorphous gallium-indium-zinc oxide thin-film transistors by curing and passivation of the damaged back channel.

PubMed

Park, Jae Chul; Ahn, Seung-Eon; Lee, Ho-Nyeon

2013-12-11

High-performance, low-cost amorphous gallium-indium-zinc oxide (a-GIZO) thin-film-transistor (TFT) technology is required for the next generation of active-matrix organic light-emitting diodes. A back-channel-etch structure is the most appropriate device structure for high-performance, low-cost a-GIZO TFT technology. However, channel damage due to source/drain etching and passivation-layer deposition has been a critical issue. To solve this problem, the present work focuses on overall back-channel processes, such as back-channel N2O plasma treatment, SiOx passivation deposition, and final thermal annealing. This work has revealed the dependence of a-GIZO TFT characteristics on the N2O plasma radio-frequency (RF) power and frequency, the SiH4 flow rate in the SiOx deposition process, and the final annealing temperature. On the basis of these results, a high-performance a-GIZO TFT with a field-effect mobility of 35.7 cm(2) V(-1) s(-1), a subthreshold swing of 185 mV dec(-1), a switching ratio exceeding 10(7), and a satisfactory reliability was successfully fabricated. The technology developed in this work can be realized using the existing facilities of active-matrix liquid-crystal display industries.

Development of an algorithm for controlling a multilevel three-phase converter

NASA Astrophysics Data System (ADS)

Taissariyeva, Kyrmyzy; Ilipbaeva, Lyazzat

2017-08-01

This work is devoted to the development of an algorithm for controlling transistors in a three-phase multilevel conversion system. The developed algorithm allows to organize a correct operation and describes the state of transistors at each moment of time when constructing a computer model of a three-phase multilevel converter. The developed algorithm of operation of transistors provides in-phase of a three-phase converter and obtaining a sinusoidal voltage curve at the converter output.

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

PubMed

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Power and Thermal Technology for Air and Space-Scientific Research Program Delivery Order 0003: Electrical Technology Component Development

DTIC Science & Technology

2007-03-01

specific contact resistivity of Ti/AlNi/Au 24 21 The full view 3D model of the IGBT ………………………………….. 25 22 2D temperature distribution of the SiC...comprised of multiple materials. The representative geometry of a Si isolated gated bipolar transistor ( IGBT ) was chosen for the initial simulation...samples annealed at 650°C for 30 minutes in either the tube furnace with an oxygen gettering system or in the vacuum chamber, represented the superior

Space solar cell technology development - A perspective

NASA Technical Reports Server (NTRS)

Scott-Monck, J.

1982-01-01

The developmental history of photovoltaics is examined as a basis for predicting further advances to the year 2000. Transistor technology was the precursor of solar cell development. Terrestrial cells were modified for space through changes in geometry and size, as well as the use of Ag-Ti contacts and manufacture of a p-type base. The violet cell was produced for Comsat, and involved shallow junctions, new contacts, and an enhanced antireflection coating for better radiation tolerance. The driving force was the desire by private companies to reduce cost and weight for commercial satellite power supplies. Liquid phase epitaxial (LPE) GaAs cells are the latest advancement, having a 4 sq cm area and increased efficiency. GaAs cells are expected to be flight ready in the 1980s. Testing is still necessary to verify production techniques and the resistance to electron and photon damage. Research will continue in CVD cell technology, new panel technology, and ultrathin Si cells.

The Technology Review 10: Emerging Technologies that Will Change the World.

ERIC Educational Resources Information Center

Technology Review, 2001

2001-01-01

Identifies 10 emerging areas of technology that will soon have a profound impact on the economy and on how people live and work: brain-machine interfaces; flexible transistors; data mining; digital rights management; biometrics; natural language processing; microphotonics; untangling code; robot design; and microfluidics. In each area, one…

4 Kelvin Cryogenic Characterization of Commercial pHEMT Transistors at 9 kHz to 8.5 GHz Range

NASA Astrophysics Data System (ADS)

Ibarra-Medel, E.; Velázquez, M.; Ventura, S.; Ferrusca, D.; Gómez-Rivera, V.

2016-07-01

Nowadays, the technology innovations in large format array detectors at low temperature for millimetric observational astronomy demand the development of electronics capable to keep their functionality at cryogenic temperatures. In kinetic inductance detectors, the first stage of electronics readout requires high-bandwidth low-noise amplifiers (LNAs). These devices are commonly fabricated in monolithic microwave integrated circuit (MMIC) processes which commercially achieve a noise temperature level of 5 K. An alternative approach to the MMIC are the hybrid microwave circuit which mixes RF lumped elements and discrete electronic components. This paper describes the characterization of six commercial pHEMT transistors tested at cryogenic temperatures. DC properties such as I-V curves and transconductance (g_m) were measured for each transistor; these measurements allow us to calculate the best bias point versus gain, with the lowest noise figure and power consumption within the range of 9 kHz to 8.5 GHz at the operating temperature of 4 K. Experimental results suggest that the characterized pHEMTs have a noise figure that allow them to be used in hybrid LNAs arranges with a comparable MMIC performance.

Organic Light-Emitting Transistors: Materials, Device Configurations, and Operations.

PubMed

Zhang, Congcong; Chen, Penglei; Hu, Wenping

2016-03-09

Organic light-emitting transistors (OLETs) represent an emerging class of organic optoelectronic devices, wherein the electrical switching capability of organic field-effect transistors (OFETs) and the light-generation capability of organic light-emitting diodes (OLEDs) are inherently incorporated in a single device. In contrast to conventional OFETs and OLEDs, the planar device geometry and the versatile multifunctional nature of OLETs not only endow them with numerous technological opportunities in the frontier fields of highly integrated organic electronics, but also render them ideal scientific scaffolds to address the fundamental physical events of organic semiconductors and devices. This review article summarizes the recent advancements on OLETs in light of materials, device configurations, operation conditions, etc. Diverse state-of-the-art protocols, including bulk heterojunction, layered heterojunction and laterally arranged heterojunction structures, as well as asymmetric source-drain electrodes, and innovative dielectric layers, which have been developed for the construction of qualified OLETs and for shedding new and deep light on the working principles of OLETs, are highlighted by addressing representative paradigms. This review intends to provide readers with a deeper understanding of the design of future OLETs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

a High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder

NASA Astrophysics Data System (ADS)

Shrivas, Jayram; Akashe, Shyam; Tiwari, Nitesh

2013-06-01

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

Throwing computing into reverse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frank, Michael P.

For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipatemore » that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.« less

An overview of silicon carbide device technology

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Matus, Lawrence G.

1992-01-01

Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.

Development of a multi-space constrained density functional theory approach and its application to graphene-based vertical transistors

NASA Astrophysics Data System (ADS)

Kim, Han Seul; Kim, Yong-Hoon

We have been developing a multi-space-constrained density functional theory approach for the first-principles calculations of nano-scale junctions subjected to non-equilibrium conditions and charge transport through them. In this presentation, we apply the method to vertically-stacked graphene/hexagonal boron nitride (hBN)/graphene Van der Waals heterostructures in the context of tunneling transistor applications. Bias-dependent changes in energy level alignment, wavefunction hybridization, and current are extracted. In particular, we compare quantum transport properties of single-layer (graphene) and infinite (graphite) electrode limits on the same ground, which is not possible within the traditional non-equilibrium Green function formalism. The effects of point defects within hBN on the current-voltage characteristics will be also discussed. Global Frontier Program (2013M3A6B1078881), Nano-Material Technology Development Programs (2016M3A7B4024133, 2016M3A7B4909944, and 2012M3A7B4049888), and Pioneer Program (2016M3C1A3906149) of the National Research Foundation.

Review on thin-film transistor technology, its applications, and possible new applications to biological cells

NASA Astrophysics Data System (ADS)

Tixier-Mita, Agnès; Ihida, Satoshi; Ségard, Bertrand-David; Cathcart, Grant A.; Takahashi, Takuya; Fujita, Hiroyuki; Toshiyoshi, Hiroshi

2016-04-01

This paper presents a review on state-of-the-art of thin-film transistor (TFT) technology and its wide range of applications, not only in liquid crystal displays (TFT-LCDs), but also in sensing devices. The history of the evolution of the technology is first given. Then the standard applications of TFT-LCDs, and X-ray detectors, followed by state-of-the-art applications in the field of chemical and biochemical sensing are presented. TFT technology allows the fabrication of dense arrays of independent and transparent microelectrodes on large glass substrates. The potential of these devices as electrical substrates for biological cell applications is then described. The possibility of using TFT array substrates as new tools for electrical experiments on biological cells has been investigated for the first time by our group. Dielectrophoresis experiments and impedance measurements on yeast cells are presented here. Their promising results open the door towards new applications of TFT technology.

Photocurable Polymers for Ion Selective Field Effect Transistors. 20 Years of Applications

PubMed Central

Abramova, Natalia; Bratov, Andrei

2009-01-01

Application of photocurable polymers for encapsulation of ion selective field effect transistors (ISFET) and for membrane formation in chemical sensitive field effect transistors (ChemFET) during the last 20 years is discussed. From a technological point of view these materials are quite interesting because they allow the use of standard photo-lithographic processes, which reduces significantly the time required for sensor encapsulation and membrane deposition and the amount of manual work required for this, all items of importance for sensor mass production. Problems associated with the application of this kind of polymers in sensors are analysed and estimation of future trends in this field of research are presented. PMID:22399988

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

PubMed

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

PubMed Central

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Development and fabrication of an augmented power transistor

NASA Technical Reports Server (NTRS)

Geisler, M. J.; Hill, F. E.; Ostop, J. A.

1983-01-01

The development of device design and processing techniques for the fabrication of an augmented power transistor capable of fast switching and high voltage power conversion is discussed. The major device goals sustaining voltages in the range of 800 to 1000 V at 80 A and 50 A, respectively, at a gain of 14. The transistor switching rise and fall times were both to have been less than 0.5 microseconds. The development of a passivating glass technique to shield the device high voltage junction from moisture and ionic contaminants is discussed as well as the development of an isolated package that separates the thermal and electrical interfaces. A new method was found to alloy the transistors to the molybdenum disc at a relatively low temperature. The measured electrical performance compares well with the predicted optimum design specified in the original proposed design. A 40 mm diameter transistor was fabricated with seven times the emitter area of the earlier 23 mm diameter device.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Quantum Theory and the Silicon Revolution. Resources in Technology.

ERIC Educational Resources Information Center

Deal, Walter F., III

1995-01-01

This learning activity describes silicon as one of the most plentiful materials on earth, demonstrating how it supplies the building blocks for electronic devices such as transistors, integrated circuits, and microprocessors. It includes a design brief on control technology. (JOW)

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

X-band inverse class-F GaN internally-matched power amplifier

NASA Astrophysics Data System (ADS)

Zhao, Bo-Chao; Lu, Yang; Han, Wen-Zhe; Zheng, Jia-Xin; Zhang, Heng-Shuang; Ma, Pei-jun; Ma, Xiao-Hua; Hao, Yue

2016-09-01

An X-band inverse class-F power amplifier is realized by a 1-mm AlGaN/GaN high electron mobility transistor (HEMT). The intrinsic and parasitic components inside the transistor, especially output capacitor Cds, influence the harmonic impedance heavily at the X-band, so compensation design is used for meeting the harmonic condition of inverse class-F on the current source plane. Experiment results show that, in the continuous-wave mode, the power amplifier achieves 61.7% power added efficiency (PAE), which is 16.3% higher than the class-AB power amplifier realized by the same kind of HEMT. To the best of our knowledge, this is the first inverse class-F GaN internally-matched power amplifier, and the PAE is quite high at the X-band. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA016801).

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

III-V heterostructure tunnel field-effect transistor.

PubMed

Convertino, C; Zota, C B; Schmid, H; Ionescu, A M; Moselund, K E

2018-07-04

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

III–V heterostructure tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Convertino, C.; Zota, C. B.; Schmid, H.; Ionescu, A. M.; Moselund, K. E.

2018-07-01

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III–V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

An Overview of Wide Bandgap Silicon Carbide Sensors and Electronics Development at NASA Glenn Research Center

NASA Technical Reports Server (NTRS)

Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Okojie, Robert S.; Chen, Liangyu; Spry, D.; Trunek, A.

2007-01-01

A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.

High voltage DC switchgear development for multi-kW space power system: Aerospace technology development of three types of solid state power controllers for 200-1100VDC with current ratings of 25, 50, and 80 amperes with one type utilizing an electromechanical device

NASA Technical Reports Server (NTRS)

Billings, W. W.

1981-01-01

Three types of solid state power controllers (SSPC's) for high voltage, high power DC system applications were developed. The first type utilizes a SCR power switch. The second type employes an electromechanical power switch element with solid state commutation. The third type utilizes a transistor power switch. Significant accomplishments include high operating efficiencies, fault clearing, high/low temperature performance and vacuum operation.

High performance tunnel field-effect transistor by gate and source engineering.

PubMed

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

An innovative large scale integration of silicon nanowire-based field effect transistors

NASA Astrophysics Data System (ADS)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Traps and Interface Fixed Charge Effects on a Solution-Processed n-Type Polymeric-Based Organic Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Hafsi, B.; Boubaker, A.; Guerin, D.; Lenfant, S.; Kalboussi, A.; Lmimouni, K.

2017-02-01

Organic field-effect transistors based on poly{[ N, N0- bis(2-octyldodecyl)- naphthalene-1,4,5,8- bis(dicarboximide)-2,6-diyl]-alt-5,50-(2,20-bithiophene)}, [P(NDI2OD-T2)n], were fabricated and characterized. The effect of octadecyltrichlorosilane (OTS) a self-assembled monolayer (SAM) grafted on to a SiO2 gate dielectric was investigated. A significant improvement of the charge mobility ( μ), up to 0.22 cm2/V s, was reached thanks to the OTS treatment. Modifying some technological parameters relating to fabrication, such as solvents, was also studied. We have analyzed the electrical properties of these thin-film transistors by using a two-dimensional drift-diffusion simulator, Integrated System Engineering-Technology Computer Aided Design (ISE-TCAD®). We studied the fixed surface charges at the organic semiconductor/oxide interface and the bulk traps effect. The dependence of the threshold voltage on the density and energy level of the trap states has also been considered. We finally found a good agreement between the output and transfer characteristics for experimental and simulated data.

Effects of ionization radiation on BICMOS components for space application

NASA Astrophysics Data System (ADS)

Rancoita, P. G.; Croitoru, N.; D'Angelo, P.; de Marchi, M.; Favalli, A.; Seidman, A.; Colder, A.; Levalois, M.; Marie, P.; Fallica, G.; Leonardi, S.; Modica, R.

2002-12-01

In this paper experimental results on radiation effects on a BICMOS high-speed standard commercial technology, manufactured by ST-Microelectronics, are reported. Bipolar transistors were irradiated by neutrons, ions, or by both of them. Fast neutrons, as well as other types of particles, produce defects, mainly by displacing silicon atoms from their lattice positions to interstitial locations, i.e. generating vacancy-interstitial pairs, the so-called Frenkel pairs. Defects introduce trapping energy states which degrade the common emitter current gain . The gain degradation has bee investigated for collector current, Ic, between 1 μA and1 mA. It was found a linear dependence of Δ(1/β) = 1/β- 1/βi(where βi and β are the gain after and before tirradiation) as a function of the concentration of Frenkel pairs. The bipolar transistors made on this technology have shown to be particularly radiation resistant. For instance, npn small area transistors have a gain variation (-i)/, lower than 10% for doses of about 0.5 MRad and collector currents of 1 μA, well suited for low power consumption space application

Flexible graphene transistors for recording cell action potentials

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Lottner, Martin; Drieschner, Simon; Bonaccini Calia, Andrea; Stoiber, Karolina; Rousseau, Lionel; Lissourges, Gaëlle; Garrido, Jose A.

2016-06-01

Graphene solution-gated field-effect transistors (SGFETs) are a promising platform for the recording of cell action potentials due to the intrinsic high signal amplification of graphene transistors. In addition, graphene technology fulfills important key requirements for in-vivo applications, such as biocompability, mechanical flexibility, as well as ease of high density integration. In this paper we demonstrate the fabrication of flexible arrays of graphene SGFETs on polyimide, a biocompatible polymeric substrate. We investigate the transistor’s transconductance and intrinsic electronic noise which are key parameters for the device sensitivity, confirming that the obtained values are comparable to those of rigid graphene SGFETs. Furthermore, we show that the devices do not degrade during repeated bending and the transconductance, governed by the electronic properties of graphene, is unaffected by bending. After cell culture, we demonstrate the recording of cell action potentials from cardiomyocyte-like cells with a high signal-to-noise ratio that is higher or comparable to competing state of the art technologies. Our results highlight the great capabilities of flexible graphene SGFETs in bioelectronics, providing a solid foundation for in-vivo experiments and, eventually, for graphene-based neuroprosthetics.

Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax

PubMed Central

Lyu, Hongming; Lu, Qi; Liu, Jinbiao; Wu, Xiaoming; Zhang, Jinyu; Li, Junfeng; Niu, Jiebin; Yu, Zhiping; Wu, Huaqiang; Qian, He

2016-01-01

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors’ power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31–41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics. PMID:27775009

Graphene-based flexible and stretchable thin film transistors.

PubMed

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array.

PubMed

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B-H; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable-like human skin-would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array

NASA Astrophysics Data System (ADS)

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R.; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M.; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B.-H.; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable—like human skin—would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Carbon Based Transistors and Nanoelectronic Devices

NASA Astrophysics Data System (ADS)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the effect of nanotube network density was explained in detail. On the other hand, graphene transfer technology was explored here as well. Annealing techniques were utilized to deposit clean graphene on arbitrary substrates. Raman spectroscopy and Raman data analysis was used to confirm the clean process. Furthermore, suspended graphene membrane was fabricated using single and multi-layer graphene films. This can make a major impact on graphene based transistors and bio-nano sensors technology.

65nm OPC and design optimization by using simple electrical transistor simulation

NASA Astrophysics Data System (ADS)

Trouiller, Yorick; Devoivre, Thierry; Belledent, Jerome; Foussadier, Franck; Borjon, Amandine; Patterson, Kyle; Lucas, Kevin; Couderc, Christophe; Sundermann, Frank; Urbani, Jean-Christophe; Baron, Stanislas; Rody, Yves; Chapon, Jean-Damien; Arnaud, Franck; Entradas, Jorge

2005-05-01

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: -design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Space Solar Power Technology for Lunar Polar Applications

NASA Technical Reports Server (NTRS)

Henley, Mark W.; Howell, Joe T.

2004-01-01

The technology for Laser-Photo-Voltaic Wireless Power Transistor (Laser-PV WPT) is being developed for lunar polar applications by Boeing and NASA Marshall Space Center. A lunar polar mission could demonstrate and validate Laser-PV WPT and other SSP technologies, while enabling access to cold, permanently shadowed craters that are believed to contain ice. Crater may hold frozen water and other volatiles deposited over billion of years, recording prior impact event on the moon (and Earth). A photo-voltaic-powered rover could use sunlight, when available, and laser light, when required, to explore a wide range of lunar terrain. The National Research Council recently found that a mission to the moon's south pole-Aitkir basin has priority for space science

Status and Applications of Diamond and Diamond-Like Materials: An Emerging Technology

DTIC Science & Technology

1990-04-30

solar -blind detectors. * Modulated structures incorporating layers of BN and diamond, for example, to develop materials that are harder and/or tougher...hundredfold increase in power capability over silicon transistors. e Solar -blind detectors, which take advantage of the large energy gap (greater than...Some success has already been achieved, for example, in applying diamond-like coatings to ZnS and ZnSe windows using a Ge-C intermediate layer . " Anti

Molecular-Beam Epitaxial Growth and Device Potential of Polar/Nonpolar Semiconductor Heterostructures.

DTIC Science & Technology

1985-06-24

research , and perhaps the most far-reaching one * A GaP -on-Si transistor was achieved, vastly better than any previous or concurrent effort towards this...the numerous conceptual and technological developments that had accumulated during the research . e) Defects in GaP -on-Si(211) Layers. With the help...Growth and Device Potential of Polar/Nonpolar Semiconductor Heterostructures Final Report by A Herbert Kroemer June 1985 -..2-- U. S. Army Research

Jumping-droplet electronics hot-spot cooling

NASA Astrophysics Data System (ADS)

Oh, Junho; Birbarah, Patrick; Foulkes, Thomas; Yin, Sabrina L.; Rentauskas, Michelle; Neely, Jason; Pilawa-Podgurski, Robert C. N.; Miljkovic, Nenad

2017-03-01

Demand for enhanced cooling technologies within various commercial and consumer applications has increased in recent decades due to electronic devices becoming more energy dense. This study demonstrates jumping-droplet based electric-field-enhanced (EFE) condensation as a potential method to achieve active hot spot cooling in electronic devices. To test the viability of EFE condensation, we developed an experimental setup to remove heat via droplet evaporation from single and multiple high power gallium nitride (GaN) transistors acting as local hot spots (4.6 mm × 2.6 mm). An externally powered circuit was developed to direct jumping droplets from a copper oxide (CuO) nanostructured superhydrophobic surface to the transistor hot spots by applying electric fields between the condensing surface and the transistor. Heat transfer measurements were performed in ambient air (22-25 °C air temperature, 20%-45% relative humidity) to determine the effect of gap spacing (2-4 mm), electric field (50-250 V/cm) and applied heat flux (demonstrated to 13 W/cm2). EFE condensation was shown to enhance the heat transfer from the local hot spot by ≈200% compared to cooling without jumping and by 20% compared to non-EFE jumping. Dynamic switching of the electric field for a two-GaN system reveals the potential for active cooling of mobile hot spots. The opportunity for further cooling enhancement by the removal of non-condensable gases promises hot spot heat dissipation rates approaching 120 W/cm2. This work provides a framework for the development of active jumping droplet based vapor chambers and heat pipes capable of spatial and temporal thermal dissipation control.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Intrinsically stretchable and transparent thin-film transistors based on printable silver nanowires, carbon nanotubes and an elastomeric dielectric

PubMed Central

Liang, Jiajie; Li, Lu; Chen, Dustin; Hajagos, Tibor; Ren, Zhi; Chou, Shu-Yu; Hu, Wei; Pei, Qibing

2015-01-01

Thin-film field-effect transistor is a fundamental component behind various mordern electronics. The development of stretchable electronics poses fundamental challenges in developing new electronic materials for stretchable thin-film transistors that are mechanically compliant and solution processable. Here we report the fabrication of transparent thin-film transistors that behave like an elastomer film. The entire fabrication is carried out by solution-based techniques, and the resulting devices exhibit a mobility of ∼30 cm2 V−1 s−1, on/off ratio of 103–104, switching current >100 μA, transconductance >50 μS and relative low operating voltages. The devices can be stretched by up to 50% strain and subjected to 500 cycles of repeated stretching to 20% strain without significant loss in electrical property. The thin-film transistors are also used to drive organic light-emitting diodes. The approach and results represent an important progress toward the development of stretchable active-matrix displays. PMID:26173436

Simulation of a spiking neuron circuit using carbon nanotube transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Najari, Montassar, E-mail: malnjar@jazanu.edu.sa; IKCE unit, Jazan University, Jazan; El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr

2016-06-10

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuitmore » has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.« less

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Flexible Graphene Transistor Architecture for Optical Sensor Technology

NASA Astrophysics Data System (ADS)

Ordonez, Richard Christopher

The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional investigation demonstrated PN junction operation and the successful integration of the proposed architecture into an optoelectronic application with the use of semiconductor quantum dots in contact with the graphene material that acted as optical absorbers to increase detector gain. Applications that can benefit from such technology advancement include Nano-satellites (Nanosat), Underwater autonomous vehicles (UAV), and airborne platforms in which flexibility and sensitivity are critical parameters that must be optimized to increase mission duration and range.

Every Day a New 3D Printing Material

ERIC Educational Resources Information Center

Hughes, Bill; Mona, Lynn; Wilson, Greg; Seamans, Jeff; McAninch, Steve; Stout, Heath

2017-01-01

A handful of technological episodes: fire, wheel and axle, Industrial Revolution, Faraday's discovery of electromagnetic induction, the transistor, and the digital age, have historically altered humanity. We are now witnessing/participating in the next transformational technology: 3D printing. Although dating back nearly 30 years, the technology…

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

NASA Technical Reports Server (NTRS)

Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

2002-01-01

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

Development of a Planar Heterojunction Bipolar Transistor for Very High Speed Logic.

DTIC Science & Technology

1983-12-01

AD- R136 341 DEVELOPMENT OF A PLANAR HETEROJUNCTION BIPOLAR i/i TRANSISTOR FOR VERV HIGH S..(U) CALIFORNIA UNIV SANTA BARBARA DEPT OF ELECTRICAL AND...GaAs material systems . Emphasis has been placed on growth and char- acterization of the above heterojunctions by Holecular Beam Epitaxy and on the...GaAs material system is used to fabricate discrete single heterojunction bipolar transistor structures. Conventional mesa-etch tech- niques will be used

Remote hydrogen sensing techniques

NASA Technical Reports Server (NTRS)

Perry, Cortes L.

1992-01-01

The objective of this project is to evaluate remote hydrogen sensing methodologies utilizing metal oxide semi-conductor field effect transistors (MOS-FET) and mass spectrometric (MS) technologies and combinations thereof.

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Sha Li, Chen; Li, Yu Ning; Wu, Yi Liang; Ong, Beng S.; Loutfy, Rafik O.

2008-06-01

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process.

Transparent active matrix organic light-emitting diode displays driven by nanowire transistor circuitry.

PubMed

Ju, Sanghyun; Li, Jianfeng; Liu, Jun; Chen, Po-Chiang; Ha, Young-Geun; Ishikawa, Fumiaki; Chang, Hsiaokang; Zhou, Chongwu; Facchetti, Antonio; Janes, David B; Marks, Tobin J

2008-04-01

Optically transparent, mechanically flexible displays are attractive for next-generation visual technologies and portable electronics. In principle, organic light-emitting diodes (OLEDs) satisfy key requirements for this application-transparency, lightweight, flexibility, and low-temperature fabrication. However, to realize transparent, flexible active-matrix OLED (AMOLED) displays requires suitable thin-film transistor (TFT) drive electronics. Nanowire transistors (NWTs) are ideal candidates for this role due to their outstanding electrical characteristics, potential for compact size, fast switching, low-temperature fabrication, and transparency. Here we report the first demonstration of AMOLED displays driven exclusively by NW electronics and show that such displays can be optically transparent. The displays use pixel dimensions suitable for hand-held applications, exhibit 300 cd/m2 brightness, and are fabricated at temperatures suitable for integration on plastic substrates.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Muscle Strength Endurance Testing Development Based Photo Transistor with Motion Sensor Ultrasonic

NASA Astrophysics Data System (ADS)

Rusdiana, A.

2017-03-01

The endurance of upper-body muscles is one of the most important physical fitness components. As technology develops, the process of test and assessment is now getting digital; for instance, there are a sensor stuck to the shoe (Foot Pod, Polar, and Sunto), Global Positioning System (GPS) and Differential Global Positioning System (DGPS), radar, photo finish, kinematic analysis, and photocells. Those devices aim to analyze the performances and fitness of athletes particularly the endurance of arm, chest, and shoulder muscles. In relation to that, this study attempt to create a software and a hardware for pull-ups through phototransistor with ultrasonic motion sensor. Components needed to develop this device consist of microcontroller MCS-51, photo transistor, light emitting diode, buzzer, ultrasonic sensor, and infrared sensor. The infrared sensor is put under the buffer while the ultrasonic sensor is stuck on the upper pole. The components are integrated with an LED or a laptop made using Visual Basic 12 software. The results show that pull-ups test using digital device (mean; 9.4 rep) is lower than using manual calculation (mean; 11.3 rep). This is due to the fact that digital test requires the test-takers to do pull-ups perfectly.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Rehabilitation Technology for the Blind in the United States.

ERIC Educational Resources Information Center

Jacobson, William H.

Research in the United States and abroad has led to advances in rehabilitation technology that enables blind and visually impaired persons to compete with sighted persons for employment. Relatively inexpensive devices such as pocket calculators, transistor radios, cassette recorders, and digital watches have become aids for the blind; some…

180-GHz I-Q Second Harmonic Resistive Mixer MMIC

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Lai, Richard; Mei, Xiaobing

2010-01-01

An indium phosphide MMIC (monolithic microwave integrated circuit) mixer was developed, processed, and tested in the NGC 35-nm-gate-length HEMT (high electron mobility transistor) process. This innovation is very compact in size and operates with very low LO power. Because it is a resistive mixer, this innovation does not require DC power. This is an enabling technology for the miniature receiver modules for the GeoSTAR instrument, which is the only viable option for the NRC decadal study mission PATH.

From Vacuum Tubes to a Semiconductor Triode

NASA Astrophysics Data System (ADS)

Mil'shtein, S.

2005-06-01

Current study presents a brief review of an electronic technology evolution: from vacuum tubes, to transistors, to a novel, recently developed semiconductor triode, where electrons travel vertically about 600 angstroms from the filament to the anode. We plotted I-V and transfer curves for the semiconductor triodes. The very first prototypes proved to carry a maximum gain of about 15db and fT=8GHz. Filaments of variable length were produced to study mutual electrostatic interaction of the electrodes in the triode.

Development of optimized detector/spectrophotometer technology for low background space astronomy missions

NASA Technical Reports Server (NTRS)

Jones, B.

1985-01-01

This program was directed towards a better understanding of some of the important factors in the performance of infrared detector arrays at low background conditions appropriate for space astronomy. The arrays were manufactured by Aerojet Electrosystems Corporation, Azusa. Two arrays, both bismuth doped silicon, were investigated: an AMCID 32x32 Engineering mosiac Si:Bi accumulation mode charge injection device detector array and a metal oxide semiconductor/field effect transistor (MOS-FET) switched array of 16x32 pixels.

Universal power transistor base drive control unit

DOEpatents

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Universal power transistor base drive control unit

DOEpatents

Gale, A.R.; Gritter, D.J.

1988-06-07

A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

2000-01-01

This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

A north-south stationkeeping ion thruster system for ATS-F.

NASA Technical Reports Server (NTRS)

Worlock, R.; James, E.; Ramsey, W.; Trump, G.; Gant, G.; Jan, L.; Bartlett, R.

1972-01-01

An ion thruster system is being developed for the ATS-F satellite to demonstrate the application of ion thruster technology to the synchronous satellite north-south stationkeeping mission. The cesium bombardment ion thruster develops one millipound thrust at 2600 seconds specific impulse and provides thrust vectoring by accelerator electrode displacement. The propellant system is sized for two years operation at 25 percent duty cycle. Power conditioning circuitry is based on transistor inverters switching at 10 kHz. Thirteen command channels allow flexibility in operation; 12 telemetry channels provide information on system performance. Input power is less than 150 watts.

Ultrasensitive biomolecular assays with amplifying nanowire FET biosensors

NASA Astrophysics Data System (ADS)

Chui, Chi On; Shin, Kyeong-Sik; Mao, Yufei

2013-09-01

In this paper, we review our recent development and validation of the ultrasensitive electronic biomolecular assays enabled by our novel amplifying nanowire field-effect transistor (nwFET) biosensors. Our semiconductor nwFET biosensor platform technology performs extreme proximity signal amplification in the electrical domain that requires neither labeling nor enzymes nor optics. We have designed and fabricated the biomolecular assay prototypes and developed the corresponding analytical procedures. We have also confirmed their analytical performance in quantitating key protein biomarker in human serum, demonstrating an ultralow limit of detection and concurrently high output current level for the first time.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

High-Purity Semiconducting Single-Walled Carbon Nanotubes: A Key Enabling Material in Emerging Electronics.

PubMed

Lefebvre, Jacques; Ding, Jianfu; Li, Zhao; Finnie, Paul; Lopinski, Gregory; Malenfant, Patrick R L

2017-10-17

Semiconducting single-walled carbon nanotubes (sc-SWCNTs) are emerging as a promising material for high-performance, high-density devices as well as low-cost, large-area macroelectronics produced via additive manufacturing methods such as roll-to-roll printing. Proof-of-concept demonstrations have indicated the potential of sc-SWCNTs for digital electronics, radiofrequency circuits, radiation hard memory, improved sensors, and flexible, stretchable, conformable electronics. Advances toward commercial applications bring numerous opportunities in SWCNT materials development and characterization as well as fabrication processes and printing technologies. Commercialization in electronics will require large quantities of sc-SWCNTs, and the challenge for materials science is the development of scalable synthesis, purification, and enrichment methods. While a few synthesis routes have shown promising results in making near-monochiral SWCNTs, gram quantities are available only for small-diameter sc-SWCNTs, which underperform in transistors. Most synthesis routes yield mixtures of SWCNTs, typically 30% metallic and 70% semiconducting, necessitating the extraction of sc-SWCNTs from their metallic counterparts in high purity using scalable postsynthetic methods. Numerous routes to obtain high-purity sc-SWCNTs from raw soot have been developed, including density-gradient ultracentrifugation, chromatography, aqueous two-phase extraction, and selective DNA or polymer wrapping. By these methods (termed sorting or enrichment), >99% sc-SWCNT content can be achieved. Currently, all of these approaches have drawbacks and limitations with respect to electronics applications, such as excessive dilution, expensive consumables, and high ionic impurity content. Excess amount of dispersant is a common challenge that hinders direct inclusion of sc-SWCNTs into electronic devices. At present, conjugated polymer extraction may represent the most practical route to sc-SWCNTs. By the use of polymers with a π-conjugated backbone, sc-SWCNTs with >99.9% purity can be dispersed in organic solvents via a simple sonication and centrifugation process. With 1000 times less excipient and the flexibility to accommodate a broad range of solvents via diverse polymer constructs, inks are readily deployable in solution-based fabrication processes such as aerosol spray, inkjet, and gravure. Further gains in sc-SWCNT purity, among other attributes, are possible with a better understanding of the structure-property relationships that govern conjugated polymer extraction. This Account covers three interlinked topics in SWCNT electronics: metrology, enrichment, and SWCNT transistors fabricated via solution processes. First, we describe how spectroscopic techniques such as optical absorption, fluorescence, and Raman spectroscopy are applied for sc-SWCNT purity assessment. Stringent requirements for sc-SWCNTs in electronics are pushing the techniques to new levels while serving as an important driver toward the development of quantitative metrology. Next, we highlight recent progress in understanding the sc-SWCNT enrichment process using conjugated polymers, with special consideration given to the effect of doping on the mechanism. Finally, developments in sc-SWCNT-based electronics are described, with emphasis on the performance of transistors utilizing random networks of sc-SWCNTs as the semiconducting channel material. Challenges and advances associated with using polymer-based dielectrics in the unique context of sc-SWCNT transistors are presented. Such transistor packages have enabled the realization of fully printed transistors as well as transparent and even stretchable transistors as a result of the unique and excellent electrical and mechanical properties of sc-SWCNTs.

Performance of In-Pixel Circuits for Photon Counting Arrays (PCAs) Based on Polycrystalline Silicon TFTs

PubMed Central

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A.; Lu, Jeng Ping

2017-01-01

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si) — a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance — information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% FWHM at 70 keV; and the digital components should work well even in the presence of significant TFT variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm. PMID:26878107

Nanotubes May Break Through "Chip Wall"

NASA Technical Reports Server (NTRS)

Laufenberg, Larry

2003-01-01

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Anisotropic stress in narrow sGe fin field-effect transistor channels measured using nano-focused Raman spectroscopy

NASA Astrophysics Data System (ADS)

Nuytten, T.; Bogdanowicz, J.; Witters, L.; Eneman, G.; Hantschel, T.; Schulze, A.; Favia, P.; Bender, H.; De Wolf, I.; Vandervorst, W.

2018-05-01

The continued importance of strain engineering in semiconductor technology demands fast and reliable stress metrology that is non-destructive and process line-compatible. Raman spectroscopy meets these requirements but the diffraction limit prevents its application in current and future technology nodes. We show that nano-focused Raman scattering overcomes these limitations and can be combined with oil-immersion to obtain quantitative anisotropic stress measurements. We demonstrate accurate stress characterization in strained Ge fin field-effect transistor channels without sample preparation or advanced microscopy. The detailed analysis of the enhanced Raman response from a periodic array of 20 nm-wide Ge fins provides direct access to the stress levels inside the nanoscale channel, and the results are validated using nano-beam diffraction measurements.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Demonstration of high current carbon nanotube enabled vertical organic field effect transistors at industrially relevant voltages

NASA Astrophysics Data System (ADS)

McCarthy, Mitchell

The display market is presently dominated by the active matrix liquid crystal display (LCD). However, the active matrix organic light emitting diode (AMOLED) display is argued to become the successor to the LCD, and is already beginning its way into the market, mainly in small size displays. But, for AMOLED technology to become comparable in market share to LCD, larger size displays must become available at a competitive price with their LCD counterparts. A major issue preventing low-cost large AMOLED displays is the thin-film transistor (TFT) technology. Unlike the voltage driven LCD, the OLEDs in the AMOLED display are current driven. Because of this, the mature amorphous silicon TFT backplane technology used in the LCD must be upgraded to a material possessing a higher mobility. Polycrystalline silicon and transparent oxide TFT technologies are being considered to fill this need. But these technologies bring with them significant manufacturing complexity and cost concerns. Carbon nanotube enabled vertical organic field effect transistors (CN-VFETs) offer a unique solution to this problem (now known as the AMOLED backplane problem). The CN-VFET allows the use of organic semiconductors to be used for the semiconductor layer. Organics are known for their low-cost large area processing compatibility. Although the mobility of the best organics is only comparable to that of amorphous silicon, the CN-VFET makes up for this by orienting the channel vertically, as opposed to horizontally (like in conventional TFTs). This allows the CN-VFET to achieve sub-micron channel lengths without expensive high resolution patterning. Additionally, because the CN-VFET can be easily converted into a light emitting transistor (called the carbon nanotube enabled vertical organic light emitting transistor---CN-VOLET) by essentially stacking an OLED on top of the CN-VFET, more potential benefits can be realized. These potential benefits include, increased aperture ratio, increased OLED lifetime and the potential for an all transparent display. And because carbon nanotubes (CNTs) and organics are used, CN-VFET and CN-VOLET devices are compatible with flexible displays. This dissertation describes the first ever demonstration of CN-VFETs and CN-VOLETs and relates their performance to the specific properties of the CNTs and the new device architecture. In the work that followed, the CN-VFET was systematically optimized overcoming the problems revealed in the demonstration devices. The large undesired hysteresis was decreased by 96%, the on/off ratio was improved three orders of magnitude and the operating voltages were reduced to state of the art values. Additionally, the current output per device area of the CN-VFET was demonstrated to be greater than any other low resolution patterned organic transistor by a factor of 3.9. Moreover, it was demonstrated that the CNTs induce a reorientation of the high mobility plane in small molecule organics like pentacene to coincide with the vertical direction, giving additional explanation for the large currents observed in the CN-VFET. The ability to drive high currents and potentially inexpensive fabrication may provide the solution for the AMOLED backplane problem.

A 10kW series resonant converter design, transistor characterization, and base-drive optimization

NASA Technical Reports Server (NTRS)

Robson, R.; Hancock, D.

1981-01-01

Transistors are characterized for use as switches in resonant circuit applications. A base drive circuit to provide the optimal base drive to these transistors under resonant circuit conditions is developed and then used in the design, fabrication and testing of a breadboard, spaceborne type 10 kW series resonant converter.

Layer-dependent electrical and optoelectronic responses of ReSe2 nanosheet transistors.

PubMed

Yang, Shengxue; Tongay, Sefaattin; Li, Yan; Yue, Qu; Xia, Jian-Bai; Li, Shun-Shen; Li, Jingbo; Wei, Su-Huai

2014-07-07

The ability to control the appropriate layer thickness of transition metal dichalcogenides (TMDs) affords the opportunity to engineer many properties for a variety of applications in possible technological fields. Here we demonstrate that band-gap and mobility of ReSe2 nanosheet, a new member of the TMDs, increase when the layer number decreases, thus influencing the performances of ReSe2 transistors with different layers. A single-layer ReSe2 transistor shows much higher device mobility of 9.78 cm(2) V(-1) s(-1) than few-layer transistors (0.10 cm(2) V(-1) s(-1)). Moreover, a single-layer device shows high sensitivity to red light (633 nm) and has a light-improved mobility of 14.1 cm(2) V(-1) s(-1). Molecular physisorption is used as "gating" to modulate the carrier density of our single-layer transistors, resulting in a high photoresponsivity (Rλ) of 95 A W(-1) and external quantum efficiency (EQE) of 18 645% in O2 environment. This work highlights the fact that the properties of ReSe2 can be tuned in terms of the number of layers and gas molecule gating, and single-layer ReSe2 with appropriate band-gap is a promising material for future functional device applications.

The origins of informatics.

PubMed Central

Collen, M F

1994-01-01

This article summarizes the origins of informatics, which is based on the science, engineering, and technology of computer hardware, software, and communications. In just four decades, from the 1950s to the 1990s, computer technology has progressed from slow, first-generation vacuum tubes, through the invention of the transistor and its incorporation into microprocessor chips, and ultimately, to fast, fourth-generation very-large-scale-integrated silicon chips. Programming has undergone a parallel transformation, from cumbersome, first-generation, machine languages to efficient, fourth-generation application-oriented languages. Communication has evolved from simple copper wires to complex fiberoptic cables in computer-linked networks. The digital computer has profound implications for the development and practice of clinical medicine. PMID:7719803

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Jumping-droplet electronics hot-spot cooling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oh, Junho; Birbarah, Patrick; Foulkes, Thomas

Demand for enhanced cooling technologies within various commercial and consumer applications has increased in recent decades due to electronic devices becoming more energy dense. This study demonstrates jumping-droplet based electric-field-enhanced (EFE) condensation as a potential method to achieve active hot spot cooling in electronic devices. To test the viability of EFE condensation, we developed an experimental setup to remove heat via droplet evaporation from single and multiple high power gallium nitride (GaN) transistors acting as local hot spots (4.6 mm x 2.6 mm). An externally powered circuit was developed to direct jumping droplets from a copper oxide (CuO) nanostructured superhydrophobicmore » surface to the transistor hot spots by applying electric fields between the condensing surface and the transistor. Heat transfer measurements were performed in ambient air (22-25°C air temperature, 20-45% relative humidity) to determine the effect of gap spacing (2-4 mm), electric field (50-250 V/cm), and heat flux (demonstrated to 13 W/cm 2). EFE condensation was shown to enhance the heat transfer from the local hot spot by ≈ 200% compared to cooling without jumping and by 20% compared to non-EFE jumping. Dynamic switching of the electric field for a two-GaN system reveals the potential for active cooling of mobile hot spots. The opportunity for further cooling enhancement by the removal of non-condensable gases promises hot spot heat dissipation rates approaching 120 W/cm 2. Finally, this work provides a framework for the development of active jumping droplet based vapor chambers and heat pipes capable of spatial and temporal thermal dissipation control.« less

Jumping-droplet electronics hot-spot cooling

DOE PAGES

Oh, Junho; Birbarah, Patrick; Foulkes, Thomas; ...

2017-03-20

Demand for enhanced cooling technologies within various commercial and consumer applications has increased in recent decades due to electronic devices becoming more energy dense. This study demonstrates jumping-droplet based electric-field-enhanced (EFE) condensation as a potential method to achieve active hot spot cooling in electronic devices. To test the viability of EFE condensation, we developed an experimental setup to remove heat via droplet evaporation from single and multiple high power gallium nitride (GaN) transistors acting as local hot spots (4.6 mm x 2.6 mm). An externally powered circuit was developed to direct jumping droplets from a copper oxide (CuO) nanostructured superhydrophobicmore » surface to the transistor hot spots by applying electric fields between the condensing surface and the transistor. Heat transfer measurements were performed in ambient air (22-25°C air temperature, 20-45% relative humidity) to determine the effect of gap spacing (2-4 mm), electric field (50-250 V/cm), and heat flux (demonstrated to 13 W/cm 2). EFE condensation was shown to enhance the heat transfer from the local hot spot by ≈ 200% compared to cooling without jumping and by 20% compared to non-EFE jumping. Dynamic switching of the electric field for a two-GaN system reveals the potential for active cooling of mobile hot spots. The opportunity for further cooling enhancement by the removal of non-condensable gases promises hot spot heat dissipation rates approaching 120 W/cm 2. Finally, this work provides a framework for the development of active jumping droplet based vapor chambers and heat pipes capable of spatial and temporal thermal dissipation control.« less

Unencapsulated Air-stable Organic Field Effect Transistor by All Solution Processes for Low Power Vapor Sensing

NASA Astrophysics Data System (ADS)

Feng, Linrun; Tang, Wei; Zhao, Jiaqing; Yang, Ruozhang; Hu, Wei; Li, Qiaofeng; Wang, Ruolin; Guo, Xiaojun

2016-02-01

With its excellent mechanical flexibility, low-cost and low-temperature processing, the solution processed organic field-effect transistor (OFET) is a promising platform technology for developing ubiquitous sensor applications in digital health, environment monitoring and Internet of Things. However, a contradiction between achieving low voltage operation and having stable performance severely hinder the technology to become commercially viable. This work shows that, by reducing the sub-gap density of states (DOS) at the channel for low operation voltage and using a proper low-k non-polar polymer dielectric layer, such an issue can be addressed. Stable electrical properties after either being placed for weeks or continuously prolonged bias stressing for hours in ambient air are achieved for all solution processed unencapsulated OFETs with the channel being exposed to the ambient air for analyte detection. The fabricated device presents a steep subthreshold swing less than 100 mV/decade, and an ON/OFF ratio of 106 at a voltage swing of 3 V. The low voltage and stable operation allows the sensor made of the OFET to be incorporated into a battery-powered electronic system for continuously reliable sensing of ammonia vapor in ambient air with very small power consumption of about 50 nW.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Unencapsulated Air-stable Organic Field Effect Transistor by All Solution Processes for Low Power Vapor Sensing

PubMed Central

Feng, Linrun; Tang, Wei; Zhao, Jiaqing; Yang, Ruozhang; Hu, Wei; Li, Qiaofeng; Wang, Ruolin; Guo, Xiaojun

2016-01-01

With its excellent mechanical flexibility, low-cost and low-temperature processing, the solution processed organic field-effect transistor (OFET) is a promising platform technology for developing ubiquitous sensor applications in digital health, environment monitoring and Internet of Things. However, a contradiction between achieving low voltage operation and having stable performance severely hinder the technology to become commercially viable. This work shows that, by reducing the sub-gap density of states (DOS) at the channel for low operation voltage and using a proper low-k non-polar polymer dielectric layer, such an issue can be addressed. Stable electrical properties after either being placed for weeks or continuously prolonged bias stressing for hours in ambient air are achieved for all solution processed unencapsulated OFETs with the channel being exposed to the ambient air for analyte detection. The fabricated device presents a steep subthreshold swing less than 100 mV/decade, and an ON/OFF ratio of 106 at a voltage swing of 3 V. The low voltage and stable operation allows the sensor made of the OFET to be incorporated into a battery-powered electronic system for continuously reliable sensing of ammonia vapor in ambient air with very small power consumption of about 50 nW. PMID:26861412

Laser Direct Writing Process for Making Electrodes and High-k Sol-Gel ZrO2 for Boosting Performances of MoS2 Transistors.

PubMed

Kwon, Hyuk-Jun; Jang, Jaewon; Grigoropoulos, Costas P

2016-04-13

A series of two-dimensional (2D) transition metal dichalcogenides (TMDCs), including molybdenum disulfide (MoS2), can be attractive materials for photonic and electronic applications due to their exceptional properties. Among these unique properties, high mobility of 2D TMDCs enables realization of high-performance nanoelectronics based on a thin film transistor (TFT) platform. In this contribution, we report highly enhanced field effect mobility (μ(eff) = 50.1 cm(2)/(V s), ∼2.5 times) of MoS2 TFTs through the sol-gel processed high-k ZrO2 (∼22.0) insulator, compared to those of typical MoS2/SiO2/Si structures (μ(eff) = 19.4 cm(2)/(V s)) because a high-k dielectric layer can suppress Coulomb electron scattering and reduce interface trap concentration. Additionally, in order to avoid costly conventional mask based photolithography and define the patterns, we employ a simple laser direct writing (LDW) process. This process allows precise and flexible control with reasonable resolution (up to ∼10 nm), depending on the system, and enables fabrication of arbitrarily patterned devices. Taking advantage of continuing developments in laser technology offers a substantial cost decrease, and LDW may emerge as a promising technology.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

All-optical transistors and logic gates using a parity-time-symmetric Y-junction: Design and simulation

NASA Astrophysics Data System (ADS)

Ding, Shulin; Wang, Guo Ping

2015-09-01

Classical nonlinear or quantum all-optical transistors are dependent on the value of input signal intensity or need extra co-propagating beams. In this paper, we present a kind of all-optical transistors constructed with parity-time (PT)-symmetric Y-junctions, which perform independently on the value of signal intensity in an unsaturated gain case and can also work after introducing saturated gain. Further, we show that control signal can switch the device from amplification of peaks in time to transformation of peaks to amplified troughs. By using these PT-symmetric Y-junctions with currently available materials and technologies, we can implement interesting logic functions such as NOT and XOR (exclusive OR) gates, implying potential applications of such structures in designing optical logic gates, optical switches, and signal transformations or amplifications.

Enhanced Amplification and Fan-Out Operation in an All-Magnetic Transistor

PubMed Central

Barman, Saswati; Saha, Susmita; Mondal, Sucheta; Kumar, Dheeraj; Barman, Anjan

2016-01-01

Development of all-magnetic transistor with favorable properties is an important step towards a new paradigm of all-magnetic computation. Recently, we showed such possibility in a Magnetic Vortex Transistor (MVT). Here, we demonstrate enhanced amplification in MVT achieved by introducing geometrical asymmetry in a three vortex sequence. The resulting asymmetry in core to core distance in the three vortex sequence led to enhanced amplification of the MVT output. A cascade of antivortices travelling in different trajectories including a nearly elliptical trajectory through the dynamic stray field is found to be responsible for this amplification. This asymmetric vortex transistor is further used for a successful fan-out operation, which gives large and nearly equal gains in two output branches. This large amplification in magnetic vortex gyration in magnetic vortex transistor is proposed to be maintained for a network of vortex transistor. The above observations promote the magnetic vortex transistors to be used in complex circuits and logic operations. PMID:27624662

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis.

PubMed

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L; Terés, Lluís; Baumann, Reinhard R

2016-09-21

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates.

PubMed

Lee, Myeongwon; Koo, Jamin; Chung, Eun-Ae; Jeong, Dong-Young; Koo, Yong-Seo; Kim, Sangsig

2009-11-11

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p+ drain and n+ channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.

Electrical Properties of Reactive Liquid Crystal Semiconductors

NASA Astrophysics Data System (ADS)

McCulloch, Iain; Coelle, Michael; Genevicius, Kristijonas; Hamilton, Rick; Heckmeier, Michael; Heeney, Martin; Kreouzis, Theo; Shkunov, Maxim; Zhang, Weimin

2008-01-01

Fabrication of display products by low cost printing technologies such as ink jet, gravure offset lithography and flexography requires solution processable semiconductors for the backplane electronics. The products will typically be of lower performance than polysilicon transistors, but comparable to amorphous silicon. A range of prototypes are under development, including rollable electrophoretic displays, active matrix liquid crystal displays (AMLCD's), and flexible organic light-emitting diode (OLED) displays. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes the initial evaluation of reactive mesogen semiconductors, which can polymerise within mesophase temperatures, “freezing in” the order in crosslinked domains. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed to facilitate charge transport and provide good oxidative stability, were prepared and their liquid crystalline properties evaluated. Both time-of-flight and field effect transistor devices were prepared and their electrical characterisation reported.

Investigation of high sensitivity radio-frequency readout circuit based on AlGaN/GaN high electron mobility transistor

NASA Astrophysics Data System (ADS)

Zhang, Xiao-Yu; Tan, Ren-Bing; Sun, Jian-Dong; Li, Xin-Xing; Zhou, Yu; Lü, Li; Qin, Hua

2015-10-01

An AlGaN/GaN high electron mobility transistor (HEMT) device is prepared by using a semiconductor nanofabrication process. A reflective radio-frequency (RF) readout circuit is designed and the HEMT device is assembled in an RF circuit through a coplanar waveguide transmission line. A gate capacitor of the HEMT and a surface-mounted inductor on the transmission line are formed to generate LC resonance. By tuning the gate voltage Vg, the variations of gate capacitance and conductance of the HEMT are reflected sensitively from the resonance frequency and the magnitude of the RF reflection signal. The aim of the designed RF readout setup is to develop a highly sensitive HEMT-based detector. Project supported by the National Natural Science Foundation of China (Grant No. 61107093), the Suzhou Science and Technology Project, China (Grant No. ZXG2012024), and the Youth Innovation Promotion Association, Chinese Academy of Sciences (Grant No. 2012243).

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries.

PubMed

Lee, Yi-Ying; Hsu, Chih-Yuan; Lin, Ling-Jiun; Chang, Chih-Chun; Cheng, Hsiao-Chun; Yeh, Tsung-Hsien; Hu, Rei-Hsing; Lin, Che; Xie, Zhen; Chen, Bor-Sen

2013-10-27

Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components.According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries

PubMed Central

2013-01-01

Background Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Results Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components. According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. Conclusion This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching. PMID:24160305

Magnon transistor for all-magnon data processing.

PubMed

Chumak, Andrii V; Serga, Alexander A; Hillebrands, Burkard

2014-08-21

An attractive direction in next-generation information processing is the development of systems employing particles or quasiparticles other than electrons--ideally with low dissipation--as information carriers. One such candidate is the magnon: the quasiparticle associated with the eigen-excitations of magnetic materials known as spin waves. The realization of single-chip all-magnon information systems demands the development of circuits in which magnon currents can be manipulated by magnons themselves. Using a magnonic crystal--an artificial magnetic material--to enhance nonlinear magnon-magnon interactions, we have succeeded in the realization of magnon-by-magnon control, and the development of a magnon transistor. We present a proof of concept three-terminal device fabricated from an electrically insulating magnetic material. We demonstrate that the density of magnons flowing from the transistor's source to its drain can be decreased three orders of magnitude by the injection of magnons into the transistor's gate.

The 2018 GaN power electronics roadmap

NASA Astrophysics Data System (ADS)

Amano, H.; Baines, Y.; Beam, E.; Borga, Matteo; Bouchet, T.; Chalker, Paul R.; Charles, M.; Chen, Kevin J.; Chowdhury, Nadim; Chu, Rongming; De Santi, Carlo; Merlyne De Souza, Maria; Decoutere, Stefaan; Di Cioccio, L.; Eckardt, Bernd; Egawa, Takashi; Fay, P.; Freedsman, Joseph J.; Guido, L.; Häberlen, Oliver; Haynes, Geoff; Heckel, Thomas; Hemakumara, Dilini; Houston, Peter; Hu, Jie; Hua, Mengyuan; Huang, Qingyun; Huang, Alex; Jiang, Sheng; Kawai, H.; Kinzer, Dan; Kuball, Martin; Kumar, Ashwani; Boon Lee, Kean; Li, Xu; Marcon, Denis; März, Martin; McCarthy, R.; Meneghesso, Gaudenzio; Meneghini, Matteo; Morvan, E.; Nakajima, A.; Narayanan, E. M. S.; Oliver, Stephen; Palacios, Tomás; Piedra, Daniel; Plissonnier, M.; Reddy, R.; Sun, Min; Thayne, Iain; Torres, A.; Trivellin, Nicola; Unni, V.; Uren, Michael J.; Van Hove, Marleen; Wallis, David J.; Wang, J.; Xie, J.; Yagi, S.; Yang, Shu; Youtsey, C.; Yu, Ruiyang; Zanoni, Enrico; Zeltner, Stefan; Zhang, Yuhao

2018-04-01

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

PubMed

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

NASA Astrophysics Data System (ADS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Phase transition transistors based on strongly-correlated materials

NASA Astrophysics Data System (ADS)

Nakano, Masaki

2013-03-01

The field-effect transistor (FET) provides electrical switching functions through linear control of the number of charges at a channel surface by external voltage. Controlling electronic phases of condensed matters in a FET geometry has long been a central issue of physical science. In particular, FET based on a strongly correlated material, namely ``Mott transistor,'' has attracted considerable interest, because it potentially provides gigantic and diverse electronic responses due to a strong interplay between charge, spin, orbital and lattice. We have investigated electric-field effects on such materials aiming at novel physical phenomena and electronic functions originating from strong correlation effects. Here we demonstrate electrical switching of bulk state of matter over the first-order metal-insulator transition. We fabricated FETs based on VO2 with use of a recently developed electric-double-layer transistor technique, and found that the electrostatically induced carriers at a channel surface drive all preexisting localized carriers of 1022 cm-3 even inside a bulk to motion, leading to bulk carrier delocalization beyond the electrostatic screening length. This non-local switching of bulk phases is achieved with just around 1 V, and moreover, a novel non-volatile memory like character emerges in a voltage-sweep measurement. These observations are apparently distinct from those of conventional FETs based on band insulators, capturing the essential feature of collective interactions in strongly correlated materials. This work was done in collaboration with K. Shibuya, D. Okuyama, T. Hatano, S. Ono, M. Kawasaki, Y. Iwasa, and Y. Tokura. This work was supported by the Japan Society for the Promotion of Science (JSAP) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

Possible Contribution of Nuclear Fragmentation Induced by High Energy Cosmic Protons to Single Effects Transients in Modern 3D Technology On-Board Devices

NASA Astrophysics Data System (ADS)

Chechenin, Nikolay; Chumanov, Vladimir; Kadmenskii, Anatolii

There is a tendency in modern integrated circuits manufacturing technology that in line with the growth of the density of transistors, the volume occupied by isolated conductive metallic layers on-chip also increases with copper and tungsten more frequently used instead of aluminum. Spallation reaction of 10 MeV to 1 GeV and above protons with tungsten and copper nuclei leads to formation of a large number of isotopes of elements from O to Ta. Experimental data on the cross sections of nuclear spallation reactions and average speed of residual nuclear fragments in inverse kinematics have been published in the last decade. In our report, we analyze the published data and evaluate ionization effects of the fragments from the reaction W (p, X) in the sensitive areas of transistors in microcircuit made by 3DIC technology with interlayer coupling by tungsten conductive pins (or vias), and metallic in-layer interconnection paths.

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

PubMed Central

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-01-01

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development. PMID:28350370

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

PubMed

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-03-28

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs

NASA Astrophysics Data System (ADS)

Ibrahim, Mohamed Farhat

Silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) have the properties of producing very low noise and high gain over a wide bandwidth. Because of these properties, SiGe HBTs have continually improved and now compete with InP and GaAs HEMTs for low-noise amplification. This thesis investigates the theoretical characterizations and optimizations of SiGe HBT low noise amplifiers (LNAs) for low-noise low-power applications, using SiGe BiCMOS (bipolar complementary metal-oxide-semiconductor) technology. The theoretical characterization of SiGe HBT transistors is investigated by a comprehensive study of the DC and small-signal transistor modeling. Based on a selected small-signal model, a noise model for the SiGe HBT transistor is produced. This noise model is used to build a cascode inductively degenerated SiGe HBT LNA circuit. The noise figure (NF) equation for this LNA is derived. This NF equation shows better than 94.4% agreement with the simulation results. With the small-signal model verification, a new analytical method for optimizing the noise figure of the SiGe HBT LNA circuits is presented. The novelty feature of this optimization is the inclusion of the noise contributions of the base inductor parasitic resistance, the emitter inductor parasitic resistance and the bond-wire inductor parasitic resistances. The optimization is performed by reducing the number of design variables as possible. This improved theoretical optimization results in LNA designs that achieve better noise figure performance compared to previously published results in bipolar and BiCMOS technologies. Different design constraints are discussed for the LNA optimization techniques. Three different LNAs are designed. The three designs are fully integrated and fabricated in a single chip to achieve a fully monolithic realization. The LNA designs are experimentally verified. The low noise design produced a NF of 1.5dB, S21 of 15dB, and power consumption of 15mW. The three LNA designs occupied 1.4mum 2 in 130 nm BiCMOS technology.

Vertical power MOS transistor as a thermoelectric quasi-nanowire device

NASA Astrophysics Data System (ADS)

Roizin, Gregory; Beeri, Ofer; Peretz, Mor Mordechai; Gelbstein, Yaniv

2016-12-01

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

NASA Astrophysics Data System (ADS)

Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Moreno-Cadenas, J. A.; Escobosa-Echavarría, A.

2011-03-01

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

Quantum Information Science: An Update

NASA Astrophysics Data System (ADS)

Kwek, L. C.; Zen, Freddy P.

2016-08-01

It is now roughly thirty years since the incipient ideas on quantum information science was concretely formalized. Over the last three decades, there has been much development in this field, and at least one technology, namely devices for quantum cryptography, is now commercialized. Yet, the holy grail of a workable quantum computing machine still lies faraway at the horizon. In any case, it took nearly several centuries before the vacuum tubes were invented after the first mechanical calculating were constructed, and several decades later, for the transistor to bring the current computer technology to fruition. In this review, we provide a short survey of the current development and progress in quantum information science. It clearly does not do justice to the amount of work in the past thirty years. Nevertheless, despite the modest attempt, this review hopes to induce younger researchers into this exciting field.

Biodegradable elastomers and silicon nanomembranes/nanoribbons for stretchable, transient electronics, and biosensors.

PubMed

Hwang, Suk-Won; Lee, Chi Hwan; Cheng, Huanyu; Jeong, Jae-Woong; Kang, Seung-Kyun; Kim, Jae-Hwan; Shin, Jiho; Yang, Jian; Liu, Zhuangjian; Ameer, Guillermo A; Huang, Yonggang; Rogers, John A

2015-05-13

Transient electronics represents an emerging class of technology that exploits materials and/or device constructs that are capable of physically disappearing or disintegrating in a controlled manner at programmed rates or times. Inorganic semiconductor nanomaterials such as silicon nanomembranes/nanoribbons provide attractive choices for active elements in transistors, diodes and other essential components of overall systems that dissolve completely by hydrolysis in biofluids or groundwater. We describe here materials, mechanics, and design layouts to achieve this type of technology in stretchable configurations with biodegradable elastomers for substrate/encapsulation layers. Experimental and theoretical results illuminate the mechanical properties under large strain deformation. Circuit characterization of complementary metal-oxide-semiconductor inverters and individual transistors under various levels of applied loads validates the design strategies. Examples of biosensors demonstrate possibilities for stretchable, transient devices in biomedical applications.

Zinc Oxide Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fortunato, E.; Barquinha, P.; Pimentel, A.; Gonçalves, A.; Marques, A.; Pereira, L.; Martins, R.

ZnO thin film transistors (ZnO-TFT) have been fabricated by rf magnetron sputtering at room temperature with a bottom-gate configuration. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 21 V, a field effect mobility of 20 cm2/Vs, a gate voltage swing of 1.24 V/decade and an on/off ratio of 2×105. The ZnO-TFT present an average optical transmission (including the glass substrate) of 80 % in the visible part of the spectrum. The combination of transparency, high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of invisible and flexible electronics. Moreover, the processing technology used to fabricate this device is relatively simple and it is compatible with inexpensive plastic/flexible substrate technology.

A high voltage dielectrically isolated smart power technology based on silicon direct bonding

NASA Astrophysics Data System (ADS)

Macary, Veronique

1992-09-01

The feasibility of a dielectrically isolated technology based on the silicon direct bonding technique, for high voltage smart power applications in the 1000 to 1550 V/1 to 20 A range, where a vertical power switch is necessary, is investigated and demonstrated. Static and dynamic isolation of the low voltage circuitry integrated beside the vertical power transistor is the main concern of this family of circuits. The dielectric isolation offers better protection to the low voltage part than does the junction isolation, because of the elimination of the parasitic bipolar transistor inherent to the latter isolation technique. Silicon direct bonding provides a cost effective way to obtain a buried oxide isolation layer. In addition, the application requires a Si/Si bonded area in the active region of the vertical power switch. Strong influence of the prebonding cleaning in the electrical characteristics of the Si/Si interface is pointed out, and presence of crystalline defects is assumed to be at the origin of electrical failures. The main problems of silicon direct bonding process compatibility with standard processes were overcome, and a complete process flow, including the simultaneous integration of a vertical power bipolar transistor together with a bipolar control circuitry, was validated. Using a peripheral biased ring is shown to provide an easy way to optimize high voltage termination for the smart power circuit, while adding a non-additional technological step. This technique was studied by dimensional electrical simulations (BIDIM2 software), as well as analytically computed.

Report of the Panel on Computer and Information Technology

NASA Technical Reports Server (NTRS)

Lundstrom, Stephen F.; Larsen, Ronald L.

1984-01-01

Aircraft have become more and more dependent on computers (information processing) for improved performance and safety. It is clear that this activity will grow, since information processing technology has advanced by a factor of 10 every 5 years for the past 35 years and will continue to do so. Breakthroughs in device technology, from vacuum tubes through transistors to integrated circuits, contribute to this rapid pace. This progress is nearly matched by similar, though not as dramatic, advances in numerical software and algorithms. Progress has not been easy. Many technical and nontechnical challenges were surmounted. The outlook is for continued growth in capability but will require surmounting new challenges. The technology forecast presented in this report has been developed by extrapolating current trends and assessing the possibilities of several high-risk research topics. In the process, critical problem areas that require research and development emphasis have been identified. The outlook assumes a positive perspective; the projected capabilities are possible by the year 2000, and adequate resources will be made available to achieve them. Computer and information technology forecasts and the potential impacts of this technology on aeronautics are identified. Critical issues and technical challenges underlying the achievement of forecasted performance and benefits are addressed.

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Nanocharacterization Challenges in a Changing Microelectronics Landscape

NASA Astrophysics Data System (ADS)

Brilloüt, Michel

2011-11-01

As the microelectronics industry enters the "nano"-era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling "Moore's law". New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate-all-around nanowire structures. Due to the escalating cost and complexity of sub-28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non-digital technologies (the so-called "More-than-Moore" domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

Microsensor research

NASA Astrophysics Data System (ADS)

Hughes, R. C.; Drebing, C. G.

1990-04-01

The technology that led to very large scale integrated circuits on silicon chips also provides a basis for new microsensors that are small, inexpensive, low power, rugged, and reliable. Two examples of microsensors Sandia is developing that take advantage of this technology are the microelectronic chemical sensor array and the radiation sensing field effect transistor (RADFET). Increasingly, the technology of chemical sensing needs new microsensor concepts. Applications in this area include environmental monitoring, criminal investigations, and state-of-health monitoring, both for equipment and living things. Chemical microsensors can satisfy sensing needs in the industrial, consumer, aerospace, and defense sectors. The microelectronic chemical-sensor array may address some of these applications. We have fabricated six separate chemical gas sensing areas on the microelectronic chemical sensor array. By using different catalytic metals on the gate areas of the diodes, we can selectively sense several gases.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

NASA Astrophysics Data System (ADS)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Power generator driven by Maxwell's demon

NASA Astrophysics Data System (ADS)

Chida, Kensaku; Desai, Samarth; Nishiguchi, Katsuhiko; Fujiwara, Akira

2017-05-01

Maxwell's demon is an imaginary entity that reduces the entropy of a system and generates free energy in the system. About 150 years after its proposal, theoretical studies explained the physical validity of Maxwell's demon in the context of information thermodynamics, and there have been successful experimental demonstrations of energy generation by the demon. The demon's next task is to convert the generated free energy to work that acts on the surroundings. Here, we demonstrate that Maxwell's demon can generate and output electric current and power with individual randomly moving electrons in small transistors. Real-time monitoring of electron motion shows that two transistors functioning as gates that control an electron's trajectory so that an electron moves directionally. A numerical calculation reveals that power generation is increased by miniaturizing the room in which the electrons are partitioned. These results suggest that evolving transistor-miniaturization technology can increase the demon's power output.

All-optical transistors and logic gates using a parity-time-symmetric Y-junction: Design and simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ding, Shulin; Wang, Guo Ping, E-mail: gpwang@szu.edu.cn; College of Electronic Science and Technology, Shenzhen University, Shenzhen 518060

Classical nonlinear or quantum all-optical transistors are dependent on the value of input signal intensity or need extra co-propagating beams. In this paper, we present a kind of all-optical transistors constructed with parity-time (PT)-symmetric Y-junctions, which perform independently on the value of signal intensity in an unsaturated gain case and can also work after introducing saturated gain. Further, we show that control signal can switch the device from amplification of peaks in time to transformation of peaks to amplified troughs. By using these PT-symmetric Y-junctions with currently available materials and technologies, we can implement interesting logic functions such as NOTmore » and XOR (exclusive OR) gates, implying potential applications of such structures in designing optical logic gates, optical switches, and signal transformations or amplifications.« less

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Transferred substrate heterojunction bipolar transistors for submillimeter wave applications

NASA Technical Reports Server (NTRS)

Fung, A.; Samoska, L.; Siegel, P.; Rodwell, M.; Urteaga, M.; Paidi, V.

2003-01-01

We present ongoing work towards the development of submillimeter wave transistors with goals of realizing advanced high frequency amplifiers, voltage controlled oscillators, active multipliers, and traditional high-speed digital circuits.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks

PubMed Central

Rogers, John A.; Bao, Zhenan; Baldwin, Kirk; Dodabalapur, Ananth; Crone, Brian; Raju, V. R.; Kuck, Valerie; Katz, Howard; Amundson, Karl; Ewing, Jay; Drzaic, Paul

2001-01-01

Electronic systems that use rugged lightweight plastics potentially offer attractive characteristics (low-cost processing, mechanical flexibility, large area coverage, etc.) that are not easily achieved with established silicon technologies. This paper summarizes work that demonstrates many of these characteristics in a realistic system: organic active matrix backplane circuits (256 transistors) for large (≈5 × 5-inch) mechanically flexible sheets of electronic paper, an emerging type of display. The success of this effort relies on new or improved processing techniques and materials for plastic electronics, including methods for (i) rubber stamping (microcontact printing) high-resolution (≈1 μm) circuits with low levels of defects and good registration over large areas, (ii) achieving low leakage with thin dielectrics deposited onto surfaces with relief, (iii) constructing high-performance organic transistors with bottom contact geometries, (iv) encapsulating these transistors, (v) depositing, in a repeatable way, organic semiconductors with uniform electrical characteristics over large areas, and (vi) low-temperature (≈100°C) annealing to increase the on/off ratios of the transistors and to improve the uniformity of their characteristics. The sophistication and flexibility of the patterning procedures, high level of integration on plastic substrates, large area coverage, and good performance of the transistors are all important features of this work. We successfully integrate these circuits with microencapsulated electrophoretic “inks” to form sheets of electronic paper. PMID:11320233

HEMT Amplifiers and Equipment for their On-Wafer Testing

NASA Technical Reports Server (NTRS)

Fung, King man; Gaier, Todd; Samoska, Lorene; Deal, William; Radisic, Vesna; Mei, Xiaobing; Lai, Richard

2008-01-01

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Tinning/Trimming Robot System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fureigh, M.L.

In a new surface mount assembly area at AlliedSignal Inc., Kansas City Division (KCD), a tinning/trimming robot system tins and trims the gold-plated leads of surface mount technology (SMT) transistors. The KCD-designed system uses a Unimation PUMA 260 robot, a General Production Devices SP-2000 solder pot; water-soluble Blackstone No. 2508 flux; and a Virtual Industries high-temperature, ESD-conductive, miniature suction cup. After the manual cleaning operation, the processed SMT transistors go to the QUADSTAR Automated Component Placement System for a Radar Logic Assembly. The benefits are reductions in the cost of nonconformance, worker fatigue, and standard hours.

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Bilayer Photoresist Insulator for High Performance Organic Thin-Film Transistors on Plastic Films

NASA Astrophysics Data System (ADS)

Wang, He; Li, Chun-Hong; Pan, Feng; Wang, Hai-Bo; Yan, Dong-Hang

2009-11-01

A novel bilayer photoresist insulator is applied in flexible vanadyl-phthalocyanine (VOPc) organic thin-film transistors (OTFTs). The micron-size patterns of this photoresisit insulator can be directly defined only by photolithography without the etching process. Furthermore, these OTFTs exhibit high field-effect mobility (about 0.8 cm2/Vs) and current on/off ratio (about 106). In particular, they show rather low hysteresis (< 1 V). The results demonstrate that this bilayer photoresist insulator can be applied in large-area electronics and in the facilitation of patterning insulators.

78 FR 45026 - Revisions to the Export Administration Regulations (EAR): Control of Military Electronic...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-25

... bear no direct correlation to military-specific applications in accordance with the stated intention... logical correlation to the way that discrete microwave transistors and MMIC technologies actually work...

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

NASA Astrophysics Data System (ADS)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

Progress of new label-free techniques for biosensors: a review.

PubMed

Sang, Shengbo; Wang, Yajun; Feng, Qiliang; Wei, Ye; Ji, Jianlong; Zhang, Wendong

2016-01-01

The detection techniques used in biosensors can be broadly classified into label-based and label-free. Label-based detection relies on the specific properties of labels for detecting a particular target. In contrast, label-free detection is suitable for the target molecules that are not labeled or the screening of analytes which are not easy to tag. Also, more types of label-free biosensors have emerged with developments in biotechnology. The latest developed techniques in label-free biosensors, such as field-effect transistors-based biosensors including carbon nanotube field-effect transistor biosensors, graphene field-effect transistor biosensors and silicon nanowire field-effect transistor biosensors, magnetoelastic biosensors, optical-based biosensors, surface stress-based biosensors and other type of biosensors based on the nanotechnology are discussed. The sensing principles, configurations, sensing performance, applications, advantages and restriction of different label-free based biosensors are considered and discussed in this review. Most concepts included in this survey could certainly be applied to the development of this kind of biosensor in the future.

Vacuum and the electron tube industry

NASA Astrophysics Data System (ADS)

Redhead, P. A.

2005-07-01

The electron tube industry started with the patenting of the thermionic diode by John Ambrose Fleming in 1904. The vacuum technology used by the infant tube industry was copied from the existing incandescent lamp industry. The growing demands for electron tubes for the military in the first world war led to major improvements in pumps and processing methods. By the 1920s, mass production methods were developing to satisfy the demands for receiving tubes by the burgeoning radio industry. Further expansion in the 1930s and 1940s resulted in improvements in automatic equipment for pumping vacuum tubes leading to the massive production rates of electron tubes in the second world war and the following two decades. The demand for radar during the war resulted in the development of techniques for large-scale production of microwave tubes and CRTs, the latter technology being put to good use later in TV picture tube production. The commercial introduction of the transistor ended the massive demand for receiving tubes. This review concentrates on the vacuum technology developed for receiving tube production.

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Challenge of Si/SiGe technology to optoelectronics

NASA Astrophysics Data System (ADS)

Chang, C. Y.; Jung, J. G.

1993-01-01

Low temperature epitaxy (LTE) of Si and SiGecanbe performed at a temperature of 550 C or lower. Very promising applications can be opened. Such as high speed/high frequency operations at 90GHZ by constructing heterojunction bipolar transistors. High performance FET'slikepseudomorphic p-channel orn-channel high mobility field effect transistors are presented which canbe composed to perform CMOS operations. Optoelectronic devices such as IRdetectors (1-12um), mutiple quantum well (MOW), disordered superlattice (d-SL) which are the potential candidatesof IR detector and optical sources (e.q. LED, LD etc.) Various physical insights regarding to SiGe heterostructures are presented which includeswave function filter, mass filter as well as band mixing are introduced. Researchesat National Nano Device Laboratory (NDL) which processes the capability of 0.3um Si ULSI technologies and SiGe works as well as lll-V, a-Si/SiGe lines are also presented.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

A gallium phosphide high-temperature bipolar junction transistor

NASA Technical Reports Server (NTRS)

Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

1981-01-01

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

NASA Technical Reports Server (NTRS)

Kim, Jae-Hoon; Lin, Steven H.

1991-01-01

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Military Applications of Fiber Optics Technology

DTIC Science & Technology

1989-05-01

Research Projects Agency DNA Defense Nuclear Agency EMI Electromagnetic interference EMP Electromagnetic pulse FET Field effect transistor FOFA Follow...Organization SEED Self electro-optic effect device TBM Tactical ballistic missile TOW Tube launched, optically tracked, wire-guided UAV Unmanned aerial vehicle...systems, coupled with novel but effective transducing technology, have set the stage for a powerful class of fiber optic sensors. 8 Optical fibers have

Graphene Field Effect Transistors for Biomedical Applications: Current Status and Future Prospects.

PubMed

Forsyth, Rhiannan; Devadoss, Anitha; Guy, Owen J

2017-07-26

Since the discovery of the two-dimensional (2D) carbon material, graphene, just over a decade ago, the development of graphene-based field effect transistors (G-FETs) has become a widely researched area, particularly for use in point-of-care biomedical applications. G-FETs are particularly attractive as next generation bioelectronics due to their mass-scalability and low cost of the technology's manufacture. Furthermore, G-FETs offer the potential to complete label-free, rapid, and highly sensitive analysis coupled with a high sample throughput. These properties, coupled with the potential for integration into portable instrumentation, contribute to G-FETs' suitability for point-of-care diagnostics. This review focuses on elucidating the recent developments in the field of G-FET sensors that act on a bioaffinity basis, whereby a binding event between a bioreceptor and the target analyte is transduced into an electrical signal at the G-FET surface. Recognizing and quantifying these target analytes accurately and reliably is essential in diagnosing many diseases, therefore it is vital to design the G-FET with care. Taking into account some limitations of the sensor platform, such as Debye-Hükel screening and device surface area, is fundamental in developing improved bioelectronics for applications in the clinical setting. This review highlights some efforts undertaken in facing these limitations in order to bring G-FET development for biomedical applications forward.

Development of paper-gate transistor toward direct detection from microbiological fluids

NASA Astrophysics Data System (ADS)

Kajisa, Taira; Sakata, Toshiya

2017-04-01

In this study, a paper-gate transistor was developed to detect glucose using an extended-gate field-effect transistor (FET). A filter paper was used as an extended gate electrode, in which Au nanoparticles (AuNPs) modified with phenylboronic acids (PBAs) were included. PBA-AuNPs play an important role as a support to not only be entrapped in cellulose fibrils but also bind to the targeted glucose in a paper. The surface properties of PBA-AuNPs were investigated to elucidate the electrical properties of the paper-gate electrode using an absorption spectrum and a zeta potential analysis. Moreover, the paper-gate electrode enabled us to detect glucose at the micromolar level on the basis of the principle of FET devices. A platform based on the paper-gate transistor is suitable for a highly sensitive system to detect glucose in trace samples such as tears, sweat, and saliva in the future.

Transistorized PWM inverter-induction motor drive system

NASA Technical Reports Server (NTRS)

Peak, S. C.; Plunkett, A. B.

1982-01-01

This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

Micro and nano devices in passive millimetre wave imaging systems

NASA Astrophysics Data System (ADS)

Appleby, R.

2013-06-01

The impact of micro and nano technology on millimetre wave imaging from the post war years to the present day is reviewed. In the 1950s whisker contacted diodes in mixers and vacuum tubes were used to realise both radiometers and radars but required considerable skill to realise the performance needed. Development of planar semiconductor devices such as Gunn and Schottky diodes revolutionised mixer performance and provided considerable improvement. The next major breakthrough was high frequency transistors based on gallium arsenide which were initially used at intermediate frequencies but later after further development at millimeter wave frequencies. More recently Monolithic Microwave Integrated circuits(MMICs) offer exceptional performance and the opportunity for innovative design in passive imaging systems. In the future the use of micro and nano technology will continue to drive system performance and we can expect to see integration of antennae, millimetre wave and sub millimetre wave circuits and signal processing.

Advances in Hydrogen, Carbon Dioxide, and Hydrocarbon Gas Sensor Technology Using GaN and ZnO-Based Devices

PubMed Central

Anderson, Travis; Ren, Fan; Pearton, Stephen; Kang, Byoung Sam; Wang, Hung-Ta; Chang, Chih-Yang; Lin, Jenshan

2009-01-01

In this paper, we review our recent results in developing gas sensors for hydrogen using various device structures, including ZnO nanowires and GaN High Electron Mobility Transistors (HEMTs). ZnO nanowires are particularly interesting because they have a large surface area to volume ratio, which will improve sensitivity, and because they operate at low current levels, will have low power requirements in a sensor module. GaN-based devices offer the advantage of the HEMT structure, high temperature operation, and simple integration with existing fabrication technology and sensing systems. Improvements in sensitivity, recoverability, and reliability are presented. Also reported are demonstrations of detection of other gases, including CO2 and C2H4 using functionalized GaN HEMTs. This is critical for the development of lab-on-a-chip type systems and can provide a significant advance towards a market-ready sensor application. PMID:22408548

Conception et realisation d'un echantillonneur de grande vitesse en technologie HIGFET (transistor a effet de champ avec heterostructure et grille isolee)

NASA Astrophysics Data System (ADS)

Tazlauanu, Mihai

The research work reported in this thesis details a new fabrication technology for high speed integrated circuits in the broadest sense, including original contributions to device modeling, circuit simulation, integrated circuit design, wafer fabrication, micro-physical and electrical characterization, process flow and final device testing as part of an electrical system. The primary building block of this technology is the heterostructure insulated gate field effect transistor, HIGFET. We used an InP/InGaAs epitaxial heterostructure to ensure a high charge carrier mobility and hence obtain a higher operating frequency than that currently possible for silicon devices. We designed and built integrated circuits with two system architectures. The first architecture integrates the clock signal generator with the sample and hold circuitry on the InP die, while the second is a hybrid architecture of an InP sample and hold assembled with an external clock signal generator made with ECL circuits on GaAs. To generate the clock signals on the same die with the sample and hold circuits, we developed a digital circuit family based on an original inverter, appropriate for depletion mode NMOS technology. We used this circuit to design buffer amplifiers and ring oscillators. Four mask sets produced in a Cadence environment, have permitted the fabrication of test and working devices. Each new mask generation has reflected the previous achievements and has implemented new structures and circuit techniques. The fabrication technology has undergone successive modifications and refinements to optimize device manufacturing. Particular attention has been paid to the technological robustness. The plasma enhanced etching process (RIE) had been used for an exhaustive study for the statistical simulation of the technological steps. Electrical measurements, performed on the experimental samples, have permitted the modeling of the devices, technological processing to be adjusted and circuit design improved. Electrical measurements performed on dedicated test structures, during the fabrication cycle, allowed the identification and correction of some technological problems (ohmic contacts, current leakage, interconnection integrity, and thermal instabilities). Feedback corrections were validated by dedicated experiments with the experimental effort optimized by statistical techniques (factorial fractional design). (Abstract shortened by UMI.)

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Dual-mode operation of 2D material-base hot electron transistors

PubMed Central

Lan, Yann-Wen; Torres, Jr., Carlos M.; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications. PMID:27581550

Dual-mode operation of 2D material-base hot electron transistors.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Development of Cryogenic Enhancement-Mode Pseudomorphic High-Electron-Mobility Transistor Amplifier

NASA Astrophysics Data System (ADS)

Hirata, T.; Okazaki, T.; Obara, K.; Yano, H.; Ishikawa, O.

2017-06-01

This paper reports the technical details of the development of a low-temperature amplifier for nuclear magnetic resonance measurements of superfluid {}^3He in very confined geometries. The amplifier consists of commercially available enhancement-mode pseudomorphic high-electron-mobility transistor devices and temperature-insensitive passive components with an operating frequency range of 0.2-6 MHz.

Terahertz Real-Time Imaging Uncooled Arrays Based on Antenna-Coupled Bolometers or FET Developed at CEA-Leti

NASA Astrophysics Data System (ADS)

Simoens, François; Meilhan, Jérôme; Nicolas, Jean-Alain

2015-10-01

Sensitive and large-format terahertz focal plane arrays (FPAs) integrated in compact and hand-held cameras that deliver real-time terahertz (THz) imaging are required for many application fields, such as non-destructive testing (NDT), security, quality control of food, and agricultural products industry. Two technologies of uncooled THz arrays that are being studied at CEA-Leti, i.e., bolometer and complementary metal oxide semiconductor (CMOS) field effect transistors (FET), are able to meet these requirements. This paper reminds the followed technological approaches and focuses on the latest modeling and performance analysis. The capabilities of application of these arrays to NDT and security are then demonstrated with experimental tests. In particular, high technological maturity of the THz bolometer camera is illustrated with fast scanning of large field of view of opaque scenes achieved in a complete body scanner prototype.

Recent patents on electrophoretic displays and materials.

PubMed

Christophersen, Marc; Phlips, Bernard F

2010-11-01

Electrophoretic displays (EPDs) have made their way into consumer products. EPDs enable displays that offer the look and form of a printed page, often called "electronic paper". We will review recent apparatus and method patents for EPD devices and their fabrication. A brief introduction into the basic display operation and history of EPDs is given, while pointing out the technological challenges and difficulties for inventors. Recently, the majority of scientific publications and patenting activity has been directed to micro-segmented EPDs. These devices exhibit high optical reflectance and contrast, wide viewing angle, and high image resolution. Micro-segmented EPDs can also be integrated with flexible transistors technologies into flexible displays. Typical particles size ranges from 200 nm to 2 micrometer. Currently one very active area of patenting is the development of full-color EPDs. We summarize the recent patenting activity for EPDs and provide comments on perceiving factors driving intellectual property protection for EPD technologies.

Mechanical Computing Redux: Limitations at the Nanoscale

NASA Astrophysics Data System (ADS)

Liu, Tsu-Jae King

2014-03-01

Technology solutions for overcoming the energy efficiency limits of nanoscale complementary metal oxide semiconductor (CMOS) technology ultimately will be needed in order to address the growing issue of integrated-circuit chip power density. Off-state leakage current sets a fundamental lower limit in energy per operation for any voltage-level-based digital logic implemented with transistors (CMOS and beyond), which leads to practical limits for device density (i.e. cost) and operating frequency (i.e. system performance). Mechanical switches have zero off-state leakag and hence can overcome this fundamental limit. Contact adhesive force sets a lower limit for the switching energy of a mechanical switch, however, and also directly impacts its performance. This paper will review recent progress toward the development of nano-electro-mechanical relay technology and discuss remaining challenges for realizing the promise of mechanical computing for ultra-low-power computing. Supported by the Center for Energy Efficient Electronics Science (NSF Award 0939514).

Design and analysis of compact MMIC switches utilising GaAs pHEMTs in 3D multilayer technology

NASA Astrophysics Data System (ADS)

Haris, Norshakila; Kyabaggu, Peter B. K.; Alim, Mohammad A.; Rezazadeh, Ali A.

2017-05-01

In this paper, we demonstrate for the first time the implementation of three-dimensional multilayer technology on GaAs-based pseudomorphic high electron mobility transistor (pHEMT) switches. Two types of pHEMT switches are considered, namely single-pole single-throw (SPST) and single-pole double-throw (SPDT). The design and analysis of the devices are demonstrated first through a simulation of the industry-recognised standard model, TriQuint’s Own Model—Level 3, developed by TriQuint Semiconductor, Inc. From the simulation analysis, three optimised SPST and SPDT pHEMT switches which can address applications ranging from L to X bands, are fabricated and tested. The performance of the pHEMT switches using multilayer technology are comparable to those of the current state-of-the-art pHEMT switches, while simultaneously offering compact circuits with the advantages of integration with other MMIC components.

Picosecond UV single photon detectors with lateral drift field: Concept and technologies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yakimov, M.; Oktyabrsky, S.; Murat, P.

2015-09-01

Group III–V semiconductor materials are being considered as a Si replacement for advanced logic devices for quite some time. Advances in III–V processing technologies, such as interface and surface passivation, large area deep submicron lithography with high-aspect ratio etching primarily driven by the metal-oxide-semiconductor field-effect transistor development can also be used for other applications. In this paper we will focus on photodetectors with the drift field parallel to the surface. We compare the proposed concept to the state-of-the-art Si-based technology and discuss requirements which need to be satisfied for such detectors to be used in a single photon counting modemore » in blue and ultraviolet spectral region with about 10 ps photon timing resolution essential for numerous applications ranging from high-energy physics to medical imaging.« less

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

NASA Astrophysics Data System (ADS)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

3D assembly of carbon nanotubes for fabrication of field-effect transistors through nanomanipulation and electron-beam-induced deposition

NASA Astrophysics Data System (ADS)

Yu, Ning; Shi, Qing; Nakajima, Masahiro; Wang, Huaping; Yang, Zhan; Sun, Lining; Huang, Qiang; Fukuda, Toshio

2017-10-01

Three-dimensional carbon nanotube field-effect transistors (3D CNTFETs) possess predictable characteristics that rival those of planar CNTFETs and Si-based MOSFETs. However, due to the lack of a reliable assembly technology, they are rarely reported on, despite the amount of attention they receive. To address this problem, we propose the novel concept of a 3D CNTFET and develop its assembly strategy based on nanomanipulation and the electron-beam-induced deposition (EBID) technique inside a scanning electron microscope (SEM). In particular, the electrodes in our transistor design are three metallic cuboids of the same size, and their front, top and back surfaces are all wrapped up in CNTs. The assembly strategy is employed to build the structure through a repeated basic process of pick-up, placement, fixing and cutting of CNTs. The pick-up and placement is performed through one nanomanipulator with four degrees of freedom. Fixing is carried out through the EBID technique so as to improve the mechanical and electrical characteristics of the CNT/electrodes connection. CNT cutting is undertaken using the typical method of electrical breakdown. Experimental results showed that two CNTs were successfully assembled on the front sides of the cubic electrodes. This validates our assembly method for the 3D CNTFET. Also, when contact resistance was measured, tens of kilohms of resistance was observed at the CNT-EBID deposition-FET electrodes junction.. This manifests the electrical reliability of our assembly strategy.

High performance p-type organic thin film transistors with an intrinsically photopatternable, ultrathin polymer dielectric layer☆

PubMed Central

Petritz, Andreas; Wolfberger, Archim; Fian, Alexander; Krenn, Joachim R.; Griesser, Thomas; Stadlober, Barbara

2013-01-01

A high-performing bottom-gate top-contact pentacene-based oTFT technology with an ultrathin (25–48 nm) and electrically dense photopatternable polymeric gate dielectric layer is reported. The photosensitive polymer poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) is patterned directly by UV-exposure (λ = 254 nm) at a dose typical for conventionally used negative photoresists without the need for any additional photoinitiator. The polymer itself undergoes a photo-Fries rearrangement reaction under UV illumination, which is accompanied by a selective cross-linking of the macromolecules, leading to a change in solubility in organic solvents. This crosslinking reaction and the negative photoresist behavior are investigated by means of sol–gel analysis. The resulting transistors show a field-effect mobility up to 0.8 cm2 V−1 s−1 at an operation voltage as low as −4.5 V. The ultra-low subthreshold swing in the order of 0.1 V dec−1 as well as the completely hysteresis-free transistor characteristics are indicating a very low interface trap density. It can be shown that the device performance is completely stable upon UV-irradiation and development according to a very robust chemical rearrangement. The excellent interface properties, the high stability and the small thickness make the PNDPE gate dielectric a promising candidate for fast organic electronic circuits. PMID:24748853

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

Low Hysteresis Carbon Nanotube Transistors Constructed via a General Dry-Laminating Encapsulation Method on Diverse Surfaces.

PubMed

Yang, Yi; Wang, Zhongwu; Xu, Zeyang; Wu, Kunjie; Yu, Xiaoqin; Chen, Xiaosong; Meng, Yancheng; Li, Hongwei; Qiu, Song; Jin, Hehua; Li, Liqiang; Li, Qingwen

2017-04-26

Electrical hysteresis in carbon nanotube thin-film transistor (CNTTFT) due to surface adsorption of H 2 O/O 2 is a severe obstacle for practical applications. The conventional encapsulation methods based on vacuum-deposited inorganic materials or wet-coated organic materials have some limitations. In this work, we develop a general and highly efficient dry-laminating encapsulation method to reduce the hysteresis of CNTTFTs, which may simultaneously realize the construction and encapsulation of CNTTFT. Furthermore, by virtue of dry procedure and wide compatibility of PMMA, this method is suitable for the construction of CNTTFT on diverse surface including both inorganic and organic dielectric materials. Significantly, the dry-encapsulated CNTTFT exhibits very low or even negligible hysteresis with good repeatability and air stability, which is greatly superior to the nonencapsulated and wet-encapsulated CNTTFT with spin-coated PMMA. The dry-laminating encapsulation strategy, a kind of technological innovation, resolves a significant problem of CNTTFT and therefore will be promising in facile transferring and packaging the CNT films for high-performance optoelectronic devices.

JMOSFET: A MOSFET parameter extractor with geometry-dependent terms

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Moore, B. T.

1985-01-01

The parameters from metal-oxide-silicon field-effect transistors (MOSFETs) that are included on the Combined Release and Radiation Effects Satellite (CRRES) test chips need to be extracted to have a simple but comprehensive method that can be used in wafer acceptance, and to have a method that is sufficiently accurate that it can be used in integrated circuits. A set of MOSFET parameter extraction procedures that are directly linked to the MOSFET model equations and that facilitate the use of simple, direct curve-fitting techniques are developed. In addition, the major physical effects that affect MOSFET operation in the linear and saturation regions of operation for devices fabricated in 1.2 to 3.0 mm CMOS technology are included. The fitting procedures were designed to establish single values for such parameters as threshold voltage and transconductance and to provide for slope matching between the linear and saturation regions of the MOSFET output current-voltage curves. Four different sizes of transistors that cover a rectangular-shaped region of the channel length-width plane are analyzed.

Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique

NASA Astrophysics Data System (ADS)

Qiang, Lei; Liang, Xiaoci; Cai, Guangshuo; Pei, Yanli; Yao, Ruohe; Wang, Gang

2018-06-01

Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: EC - EF > 3kT and EC - EF ≤ 3kT, where kT is the thermal energy, EF and EC represent the Fermi level and the conduction band edge, respectively. Additionally, in order to describe conduction mechanisms more accurately, the extended mobility edge model is conjoined, which can also get rid of the complicated and lengthy computations. The good agreement between measured and calculated results confirms the efficiency of this model for the design of integrated large-area thin film circuits.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis

PubMed Central

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L.; Terés, Lluís; Baumann, Reinhard R.

2016-01-01

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement. PMID:27649784

Paired-pulse facilitation achieved in protonic/electronic hybrid indium gallium zinc oxide synaptic transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Li Qiang, E-mail: guoliqiang@ujs.edu.cn; Ding, Jian Ning; Huang, Yu Kai

2015-08-15

Neuromorphic devices with paired pulse facilitation emulating that of biological synapses are the key to develop artificial neural networks. Here, phosphorus-doped nanogranular SiO{sub 2} electrolyte is used as gate dielectric for protonic/electronic hybrid indium gallium zinc oxide (IGZO) synaptic transistor. In such synaptic transistors, protons within the SiO{sub 2} electrolyte are deemed as neurotransmitters of biological synapses. Paired-pulse facilitation (PPF) behaviors for the analogous information were mimicked. The temperature dependent PPF behaviors were also investigated systematically. The results indicate that the protonic/electronic hybrid IGZO synaptic transistors would be promising candidates for inorganic synapses in artificial neural network applications.

High transconductance organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

PubMed Central

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

1 μm-thickness ultra-flexible and high electrode-density surface electromyogram measurement sheet with 2 V organic transistors for prosthetic hand control.

PubMed

Fuketa, Hiroshi; Yoshioka, Kazuaki; Shinozuka, Yasuhiro; Ishida, Koichi; Yokota, Tomoyuki; Matsuhisa, Naoji; Inoue, Yusuke; Sekino, Masaki; Sekitani, Tsuyoshi; Takamiya, Makoto; Someya, Takao; Sakurai, Takayasu

2014-12-01

A 64-channel surface electromyogram (EMG) measurement sheet (SEMS) with 2 V organic transistors on a 1 μm-thick ultra-flexible polyethylene naphthalate (PEN) film is developed for prosthetic hand control. The surface EMG electrodes must satisfy the following three requirements; high mechanical flexibility, high electrode density and high signal integrity. To achieve high electrode density and high signal integrity, a distributed and shared amplifier (DSA) architecture is proposed, which enables an in-situ amplification of the myoelectric signal with a fourfold increase in EMG electrode density. In addition, a post-fabrication select-and-connect (SAC) method is proposed to cope with the large mismatch of organic transistors. The proposed SAC method reduces the area and the power overhead by 96% and 98.2%, respectively, compared with the use of conventional parallel transistors to reduce the transistor mismatch by a factor of 10.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Novel AlInN/GaN integrated circuits operating up to 500 °C

NASA Astrophysics Data System (ADS)

Gaska, R.; Gaevski, M.; Jain, R.; Deng, J.; Islam, M.; Simin, G.; Shur, M.

2015-11-01

High electron concentration in 2DEG channel of AlInN/GaN devices is remarkably stable over a broad temperature range, enabling device operation above 500 °C. The developed IC technology is based on three key elements: (1) exceptional quality AlInN/GaN heterostructure with very high carrier concentration and mobility enables IC fast operation in a broad temperature range; (2) heterostructure field effect transistor approach t provides fully planar IC structure which is easy to scale and to combine with the other high temperature electronic components; (3) fabrication advancements including novel metallization scheme and high-K passivation/gate dielectrics enable high temperature operation. The feasibility of the developed technology was confirmed by fabrication and testing of the high temperature inverter and differential amplifier ICs using AlInN/GaN heterostructures. The developed ICs showed stable performance with unit-gain bandwidth above 1 MHz and internal response time 45 ns at temperatures as high as 500 °C.

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates

NASA Astrophysics Data System (ADS)

Sheraw, Christopher Duncan

2003-10-01

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

FinFET memory cell improvements for higher immunity against single event upsets

NASA Astrophysics Data System (ADS)

Sajit, Ahmed Sattar

The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high likelihood of SEUs. Consequently, FinFET DICE memory can be a good candidate due to its high ability to tolerate SEUs of different amplitudes and long periods for both read and hold operations.

Development of silicon carbide semiconductor devices for high temperature applications

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

1991-01-01

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Adaptation of ion beam technology to microfabrication of solid state devices and transducers

NASA Technical Reports Server (NTRS)

Topich, J. A.

1977-01-01

It was found that ion beam texturing of silicon surfaces can be used to increase the effective surface area of MOS capacitors. There is, however, a problem with low dielectric breakdown. Preliminary work was begun on the fabrication of ion implanted resistors on textured surfaces and the potential improvement of wire bond strength by bonding to a textured surface. In the area of ion beam sputtering, the techniques for sputtering PVC were developed. A PVC target containing valinomycin was used to sputter an ion selective membrane on a field effect transistor to form a potassium ion sensor.

Advances in series resonant inverter technology and its effect on spacecraft employing electric propulsion

NASA Technical Reports Server (NTRS)

Robson, R. R.

1982-01-01

The efficiency of transistorized Series Resonant Inverters (SRIs), which is higher than that of silicon-controlled rectifier alternatives, reduces spacecraft radiator requirements by 40% and may eliminate the need for heat pipes on 30-cm ion thruster systems. Recently developed 10- and 25-kW inverters have potential applications in gas thrusters, and represent the first spaceborne SRI designs for such power levels. Attention is given to the design and control system approaches employed in these inverter designs to improve efficiency and reduce weight, along with the impact of such improved parameters on electric propulsion systems.

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE PAGES

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; ...

2018-01-12

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

PubMed Central

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Electrically tunable terahertz metamaterials with embedded large-area transparent thin-film transistor arrays

PubMed Central

Xu, Wei-Zong; Ren, Fang-Fang; Ye, Jiandong; Lu, Hai; Liang, Lanju; Huang, Xiaoming; Liu, Mingkai; Shadrivov, Ilya V.; Powell, David A.; Yu, Guang; Jin, Biaobing; Zhang, Rong; Zheng, Youdou; Tan, Hark Hoe; Jagadish, Chennupati

2016-01-01

Engineering metamaterials with tunable resonances are of great importance for improving the functionality and flexibility of terahertz (THz) systems. An ongoing challenge in THz science and technology is to create large-area active metamaterials as building blocks to enable efficient and precise control of THz signals. Here, an active metamaterial device based on enhancement-mode transparent amorphous oxide thin-film transistor arrays for THz modulation is demonstrated. Analytical modelling based on full-wave techniques and multipole theory exhibits excellent consistent with the experimental observations and reveals that the intrinsic resonance mode at 0.75 THz is dominated by an electric response. The resonant behavior can be effectively tuned by controlling the channel conductivity through an external bias. Such metal/oxide thin-film transistor based controllable metamaterials are energy saving, low cost, large area and ready for mass-production, which are expected to be widely used in future THz imaging, sensing, communications and other applications. PMID:27000419

Contact-induced crystallinity for high-performance soluble acene-based transistors and circuits

NASA Astrophysics Data System (ADS)

Gundlach, D. J.; Royer, J. E.; Park, S. K.; Subramanian, S.; Jurchescu, O. D.; Hamadani, B. H.; Moad, A. J.; Kline, R. J.; Teague, L. C.; Kirillov, O.; Richter, C. A.; Kushmerick, J. G.; Richter, L. J.; Parkin, S. R.; Jackson, T. N.; Anthony, J. E.

2008-03-01

The use of organic materials presents a tremendous opportunity to significantly impact the functionality and pervasiveness of large-area electronics. Commercialization of this technology requires reduction in manufacturing costs by exploiting inexpensive low-temperature deposition and patterning techniques, which typically lead to lower device performance. We report a low-cost approach to control the microstructure of solution-cast acene-based organic thin films through modification of interfacial chemistry. Chemically and selectively tailoring the source/drain contact interface is a novel route to initiating the crystallization of soluble organic semiconductors, leading to the growth on opposing contacts of crystalline films that extend into the transistor channel. This selective crystallization enables us to fabricate high-performance organic thin-film transistors and circuits, and to deterministically study the influence of the microstructure on the device characteristics. By connecting device fabrication to molecular design, we demonstrate that rapid film processing under ambient room conditions and high performance are not mutually exclusive.

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

NASA Astrophysics Data System (ADS)

Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Münzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Tröster, Gerhard; Anthopoulos, Thomas D.

2017-03-01

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V-1 s-1 and 0.013 cm2 V-1 s-1, respectively, current on/off ratio in the range 102-104, and maximum operating voltages between -3.5 and -10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as -3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

PubMed Central

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

Transient electro-thermal characterization of Si-Ge heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Sahoo, Amit Kumar; Weiß, Mario; Fregonese, Sébastien; Malbert, Nathalie; Zimmer, Thomas

2012-08-01

In this paper, a comprehensive evaluation of the transient self-heating in microwave heterojunction bipolar transistors (HBTs) have been carried out through simulations and measurements. Three dimensional thermal TCAD simulations have been performed to investigate precisely the influence of backend metallization on transient thermal behavior of a submicron SiGe:C BiCMOS technology with fT and fmax of 230 GHz and 290 GHz, respectively. Transient variation of Collector current caused by self-heating is obtained through pulse measurements. For thermal characterization, different electro-thermal networks have been employed at the temperature node of HiCuM compact model. Thermal parameters have been extracted by means of compact model simulation using a scalable transistor library. It has been shown that, the conventional R-C thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement.

A Microcomputer Interface for External Circuit Control.

ERIC Educational Resources Information Center

Gorham, D. A.

1983-01-01

Describes an interface designed to meet the requirements of an instrumentation teaching laboratory, particularly to develop computer-controlled digital circuitry while exploiting electrical drive properties of common transistor-transistor logic (TTL) devices, minimizing cost/number of components. Discusses decoding for Pet, switches, lights, and…

Improved Field-Effect Transistor Equations for Computer Simulation.

ERIC Educational Resources Information Center

Kidd, Richard; Ardini, James

1979-01-01

Presents a laboratory experiment that was developed to acquaint physics students with field-effect transistor characteristics and circuits. Computer-drawn curves supplementing student laboratory exercises can be generated to provide more permanent, usable data than those taken from a curve tracer. (HM)

Comparison of Gallium Nitride High Electron Mobility Transistors Modeling in Two and Three Dimensions

DTIC Science & Technology

2007-12-01

helix output. The TWT can provide operations in the frequency range of 300 MHz to 50 GHz. They can operate over a wide bandwidth of up to one octave...technology being used is the Traveling Wave Tube ( TWT ). There are over 200 military weapon systems that currently use TWT technology [1]. The size...reliability, and expense of the TWTs make them suitable for the option of replacing them with semiconductor technology. There is need for a high

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

NASA Astrophysics Data System (ADS)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized acoustic wave detection, high pitch sound diffraction pattern mapping, and directional listening. This system permits the direct visualization of a two dimensional sound field in a format that was previously inaccessible. In addition to the piezoelectric property, pyroelectricity is also exhibited by PVDF and is essential in the world of sensors. An integration of PVDF and OFET for the IR heat sensing is demonstrated to prove the concept of converting pyroelectric charge signal to a electric current signal. The basic pyroelectricity of PVDF sheet is first examined before making a organic transistor integrated IR sensor. Then, two types of architectures are designed and tested. The first one uses the structure similar to the PVDF strain sensor, and the second one uses a PVDF capacitor to gate the integrated OFETs. The conversion from pyroelectric signal to transistor current signal is observed and characterized. This design provides a flexible and gain-tunable version for IR heat sensors.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor

PubMed Central

Park, Jae Hyo; Kim, Hyung Yoon; Jang, Gil Su; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Kiaee, Zohreh; Joo, Seung Ki

2016-01-01

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films. PMID:27005886

Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

PubMed

Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

2017-09-01

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Molecular gated-AlGaN/GaN high electron mobility transistor for pH detection.

PubMed

Ding, Xiangzhen; Yang, Shuai; Miao, Bin; Gu, Le; Gu, Zhiqi; Zhang, Jian; Wu, Baojun; Wang, Hong; Wu, Dongmin; Li, Jiadong

2018-04-18

A molecular gated-AlGaN/GaN high electron mobility transistor has been developed for pH detection. The sensing surface of the sensor was modified with 3-aminopropyltriethoxysilane to provide amphoteric amine groups, which would play the role of receptors for pH detection. On modification with 3-aminopropyltriethoxysilane, the transistor exhibits good chemical stability in hydrochloric acid solution and is sensitive for pH detection. Thus, our molecular gated-AlGaN/GaN high electron mobility transistor acheived good electrical performances such as chemical stability (remained stable in hydrochloric acid solution), good sensitivity (37.17 μA/pH) and low hysteresis. The results indicate a promising future for high-quality sensors for pH detection.

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

NASA Technical Reports Server (NTRS)

MacLeod, Todd, C.; Ho, Fat Duen

2006-01-01

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

PubMed

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (<10 V). In addition, outstanding mechanical flexibility of printed nanotube thin-film transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

Common base amplifier with 7 - dB gain at 176 GHz in InP mesa DHBT technology

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Paidi, V.; Griffith, Z.; Dahlstrom, M.; Wei, Y.; Urteaga, M.; Rodell, M. J. W.; Fung, A.

2004-01-01

We report a single stage tunded amplifier that exhibits 7 dB small signal gain at 176 GHz. Common Base topology is chosen as it has the best maximum stable gain (MSG) in this frequency band when compared to common emitter and common collector topologies. The amplifiers are designed and fabricated in InP mesa double heterojunction bipolar transistor (DHBT) technology.

2005 6th Annual Science and Engineering Technology Conference

DTIC Science & Technology

2005-04-21

BioFAC VBAIDS Hybrid: PCR/Immuno Fast PCR Fast Immunoassay Mass Spec (Pyrolysis) SIBS UV -LIF IR Fluorochrome Charge Detect. BioCADS Trigger Advanced...Weights Beam forming Signal Processing mapped to GPU architecture Vector Processor STAP (STAP-BOY) GaN High Frequency Transistor (WBG-RF) UV Laser...Service anti- counterfeiting • Embedded security strips Technology Limitations and Barriers • Training and cost (training intensive) Land Borders North Land

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

PubMed

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

A 0.4-2.3 GHz broadband power amplifier extended continuous class-F design technology

NASA Astrophysics Data System (ADS)

Chen, Peng; He, Songbai

2015-08-01

A 0.4-2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards' working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA's implementation complexity, are presented and explained to investigate the overlapping area of the transistor's current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40-76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4-2.3 GHz.

Collaborative designing and job satisfaction of airplane manufacturing engineers: A case study

NASA Astrophysics Data System (ADS)

Johnson, Michael David, Sr.

The group III-nitride system of materials has had considerable commercial success in recent years in the solid state lighting (SSL) and power electronics markets. The need for high efficient general lighting applications has driven research into InGaN based blue light emitting diodes (LEDs), and demand for more efficient power electronics for telecommunications has driven research into AlGaN based high electron mobility transistors (HEMTs). However, the group III-nitrides material properties make them attractive for several other applications that have not received as much attention. This work focuses on developing group III-nitride based devices for novel applications. GaN is a robust, chemically inert, piezoelectric material, making it an ideal candidate for surface acoustic wave (SAW) devices designed for high temperature and/or harsh environment sensors. In this work, SAW devices based on GaN are developed for use in high temperature gas or chemical sensor applications. To increase device sensitivity, while maintaining a simple one-step photolithography fabrication process, devices were designed to operate at high harmonic frequencies. This allows for GHz regime operation without sub-micron fabrication. One potential market for this technology is continuous emissions monitoring of combustion gas vehicles. In addition to SAW devices, high electron mobility transistors (HEMTs) were developed. The epitaxial structure was characterized and the 2-D electron gas concentrations were simulated and compared to experimental results. Device fabrication processes were developed and are outlined. Fabricated devices were electrically measured and device performance is discussed.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

SiGe:C Heterojunction Bipolar Transistors: From Materials Research to Chip Fabrication

NASA Astrophysics Data System (ADS)

Ruecker, H.; Heinemann, B.; Knoll, D.; Ehwald, K.-E.

Incorporation of substitutional carbon ( ~10^20 cm^-3) into the SiGe region of a heterojunction bipolar transistor (HBT) strongly reduces boron diffusion during device processing. We describe the physical mechanism behind the suppression of B diffusion in C-rich Si and SiGe, and explain how the increased thermal stability of doping profiles in SiGe:C HBTs can be used to improve device performance. Manufacturability of SiGe:C HBTs with transit frequencies of 100 GHz and maximum oscillation frequencies of 130 GHz is demonstrated in a BiCMOS technology capable of fabricating integrated circuits for radio frequencies with high yield.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

NASA Astrophysics Data System (ADS)

Asai, Hidehiro; Mori, Takahiro; Matsukawa, Takashi; Hattori, Junichi; Endo, Kazuhiko; Fukuda, Koichi

2018-04-01

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate-drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The “synergistic” speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

PubMed Central

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

Analytic model for low-frequency noise in nanorod devices.

PubMed

Lee, Jungil; Yu, Byung Yong; Han, Ilki; Choi, Kyoung Jin; Ghibaudo, Gerard

2008-10-01

In this work analytic model for generation of excess low-frequency noise in nanorod devices such as field-effect transistors are developed. In back-gate field-effect transistors where most of the surface area of the nanorod is exposed to the ambient, the surface states could be the major noise source via random walk of electrons for the low-frequency or 1/f noise. In dual gate transistors, the interface states and oxide traps can compete with each other as the main noise source via random walk and tunneling, respectively.

The use of harmonic analysis to investigate processes in irradiated transistor structures

NASA Astrophysics Data System (ADS)

Gnap, A. K.; Zaliubovskii, I. I.; Dakhov, V. M.; Pelikhatyi, N. M.; Filippenko, V. E.

A theoretical model is developed for analyzing the behavior of transistor structures under irradiation by high-energy particles. Specifically, attention is given to the operation of a transistor switch under irradiation by 2-MeV neutrons. The proposed approach involves the replacement of the actual voltage pulse by a trapezoidal pulse, and the application of harmonic analysis to the latter. The parameters of the actual pulse can then be determined from an analysis of the constant component of the signal and the value of one of its harmonics.

Semiconductors: A 21st Century Social Studies Topic.

ERIC Educational Resources Information Center

Sunal, Cynthia

2000-01-01

Addresses the reasons for exploring semiconductor technology and organic semiconductors in schools for either middle school or secondary students in an interdisciplinary social studies and science environment. Provides background information on transistors and semiconductors. Offers three social studies lessons and related science lessons if an…

Technology and characterization of Thin-Film Transistors (TFTs) with a-IGZO semiconductor and high-k dielectric layer

NASA Astrophysics Data System (ADS)

Mroczyński, R.; Wachnicki, Ł.; Gierałtowska, S.

2016-12-01

In this work, we present the design of the technology and fabrication of TFTs with amorphous IGZO semiconductor and high-k gate dielectric layer in the form of hafnium oxide (HfOx). In the course of this work, the IGZO fabrication was optimized by means of Taguchi orthogonal tables approach in order to obtain an active semiconductor with reasonable high concentration of charge carriers, low roughness and relatively high mobility. The obtained Thin-Film Transistors can be characterized by very good electrical parameters, i.e., the effective mobility (μeff ≍ 12.8 cm2V-1s-1) significantly higher than that for a-Si TFTs (μeff ≍ 1 cm2V-1s-1). However, the value of sub-threshold swing (i.e., 640 mV/dec) points that the interfacial properties of IGZO/HfOx stack is characterized by high value of interface states density (Dit) which, in turn, demands further optimization for future applications of the demonstrated TFT structures.

Component technology for space power systems

NASA Technical Reports Server (NTRS)

Finke, R. C.

1982-01-01

Progress made by NASA toward implementation of equipment for the conversion, management, and distribution of voltage power in space applications are reviewed. Work has been carried forward on components such as bipolar transistors, deep impurity semiconductors, conductors, dielectrics, magnetic devices, and rotary power transfer. Specific programs for the high voltage systems have included research on lightweight, low-cost conductors featuring graphite fibers containing electron donor materials for wires and cables with reduced mass and the conductivity of copper. Attention has also been given p-n junction technology for high-speed, high-current, high-voltage materials and diamond-like dielectric films which are hard, have high dielectric strength, and can operate up to 300 C. A transistor has been fabricated with a voltage of 1200 V at 100 A, with a gain of 10 and a 0.5 microsec rise/fall time. A 25 kW transformer has also been built which performs at 20 kHz with an efficiency of 99.2%.

Materials for Stretchable Electronics - Electronic Eyeballs, Brain Monitors and Other Applications

ScienceCinema

Rogers, John A. [University of Illinois, Urbana Champaign, Illinois, United States

2017-12-09

Electronic circuits that involve transistors and related components on thin plastic sheets or rubber slabs offer mechanical properties (e.g. bendability, stretchability) and other features (e.g. lightweight, rugged construction) which cannot be easily achieved with technologies that use rigid, fragile semiconductor wafer or glass substrates.  Device examples include personal or structural health monitors and electronic eye imagers, in which the electronics must conform to complex curvilinear shapes or flex/stretch during use.  Our recent work accomplishes these technology outcomes by use of single crystal inorganic nanomaterials in ‘wavy’ buckled configurations on elastomeric supports.  This talk will describe key fundamental materials and mechanics aspects of these approaches, as well as engineering features of their use in individual transistors, photodiodes and integrated circuits.  Cardiac and brain monitoring devices provide examples of application in biomedicine; hemispherical electronic eye cameras illustrate new capacities for bio-inspired device design.

GaAs-based JFET and PHEMT technologies for ultra-low-power microwave circuits operating at frequencies up to 2.4 GHz

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baca, A.G.; Hietala, V.M.; Greenway, D.

1998-05-01

In this work the authors report results of narrowband amplifiers designed for milliwatt and submilliwatt power consumption using JFET and pseudomorphic high electron mobility transistors (PHEMT) GaAs-based technologies. Enhancement-mode JFETs were used to design both a hybrid amplifier with off-chip matching as well as a monolithic microwave integrated circuit (MMIC) with on-chip matching. The hybrid amplifier achieved 8--10 dB of gain at 2.4 GHz and 1 mW. The MMIC achieved 10 dB of gain at 2.4 GHz and 2 mW. Submilliwatt circuits were also explored by using 0.25 {micro}m PHEMTs. 25 {micro}W power levels were achieved with 5 dB ofmore » gain for a 215 MHz hybrid amplifier. These results significantly reduce power consumption levels achievable with the JFETs or prior MESFET, heterostructure field effect transistor (HFET), or Si bipolar results from other laboratories.« less

Separated carbon nanotube macroelectronics for active matrix organic light-emitting diode displays.

PubMed

Zhang, Jialu; Fu, Yue; Wang, Chuan; Chen, Po-Chiang; Liu, Zhiwei; Wei, Wei; Wu, Chao; Thompson, Mark E; Zhou, Chongwu

2011-11-09

Active matrix organic light-emitting diode (AMOLED) display holds great potential for the next generation visual technologies due to its high light efficiency, flexibility, lightweight, and low-temperature processing. However, suitable thin-film transistors (TFTs) are required to realize the advantages of AMOLED. Preseparated, semiconducting enriched carbon nanotubes are excellent candidates for this purpose because of their excellent mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here we report, for the first time, the demonstration of AMOLED displays driven by separated nanotube thin-film transistors (SN-TFTs) including key technology components, such as large-scale high-yield fabrication of devices with superior performance, carbon nanotube film density optimization, bilayer gate dielectric for improved substrate adhesion to the deposited nanotube film, and the demonstration of monolithically integrated AMOLED display elements with 500 pixels driven by 1000 SN-TFTs. Our approach can serve as the critical foundation for future nanotube-based thin-film display electronics.

Separated Carbon Nanotube Macroelectronics for Active Matrix Organic Light-Emitting Diode Displays

NASA Astrophysics Data System (ADS)

Fu, Yue; Zhang, Jialu; Wang, Chuan; Chen, Pochiang; Zhou, Chongwu

2012-02-01

Active matrix organic light-emitting diode (AMOLED) display holds great potential for the next generation visual technologies due to its high light efficiency, flexibility, lightweight, and low-temperature processing. However, suitable thin-film transistors (TFTs) are required to realize the advantages of AMOLED. Pre-separated, semiconducting enriched carbon nanotubes are excellent candidates for this purpose because of their excellent mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here we report, for the first time, the demonstration of AMOLED displays driven by separated nanotube thin-film transistors (SN-TFTs) including key technology components such as large-scale high-yield fabrication of devices with superior performance, carbon nanotube film density optimization, bilayer gate dielectric for improved substrate adhesion to the deposited nanotube film, and the demonstration of monolithically integrated AMOLED display elements with 500 pixels driven by 1000 SN-TFTs. Our approach can serve as the critical foundation for future nanotube-based thin-film display electronics.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Technology modules from micro- and nano-electronics for the life sciences.

PubMed

Birkholz, M; Mai, A; Wenger, C; Meliani, C; Scholz, R

2016-05-01

The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website. © 2015 Wiley Periodicals, Inc.

Multifunctional Self-Assembled Monolayers for Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Cernetic, Nathan

Organic field effect transistors (OFETs) have the potential to reach commercialization for a wide variety of applications such as active matrix display circuitry, chemical and biological sensing, radio-frequency identification devices and flexible electronics. In order to be commercially competitive with already at-market amorphous silicon devices, OFETs need to approach similar performance levels. Significant progress has been made in developing high performance organic semiconductors and dielectric materials. Additionally, a common route to improve the performance metric of OFETs is via interface modification at the critical dielectric/semiconductor and electrode/semiconductor interface which often play a significant role in charge transport properties. These metal oxide interfaces are typically modified with rationally designed multifunctional self-assembled monolayers. As means toward improving the performance metrics of OFETs, rationally designed multifunctional self-assembled monolayers are used to explore the relationship between surface energy, SAM order, and SAM dipole on OFET performance. The studies presented within are (1) development of a multifunctional SAM capable of simultaneously modifying dielectric and metal surface while maintaining compatibility with solution processed techniques (2) exploration of the relationship between SAM dipole and anchor group on graphene transistors, and (3) development of self-assembled monolayer field-effect transistor in which the traditional thick organic semiconductor is replaced by a rationally designed self-assembled monolayer semiconductor. The findings presented within represent advancement in the understanding of the influence of self-assembled monolayers on OFETs as well as progress towards rationally designed monolayer transistors.

A 10-kW series resonant converter design, transistor characterization, and base-drive optimization

NASA Technical Reports Server (NTRS)

Robson, R. R.; Hancock, D. J.

1982-01-01

The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.

Transport spectroscopy of coupled donors in silicon nano-transistors

PubMed Central

Moraru, Daniel; Samanta, Arup; Anh, Le The; Mizuno, Takeshi; Mizuta, Hiroshi; Tabe, Michiharu

2014-01-01

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies report transport through dopants randomly located in the channel. However, for practical applications, it is critical to control the location of the donors with simple techniques. Here, we fabricate silicon transistors with selectively nanoscale-doped channels using nano-lithography and thermal-diffusion doping processes. Coupled phosphorus donors form a quantum dot with the ground state split into a number of levels practically equal to the number of coupled donors, when the number of donors is small. Tunneling-transport spectroscopy reveals fine features which can be correlated with the different numbers of donors inside the quantum dot, as also suggested by first-principles simulation results. PMID:25164032

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Carbon nanotube computer.

PubMed

Shulaker, Max M; Hills, Gage; Patil, Nishant; Wei, Hai; Chen, Hong-Yu; Wong, H-S Philip; Mitra, Subhasish

2013-09-26

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Quantum Thermal Transistor.

PubMed

Joulain, Karl; Drevillon, Jérémie; Ezzahri, Younès; Ordonez-Miranda, Jose

2016-05-20

We demonstrate that a thermal transistor can be made up with a quantum system of three interacting subsystems, coupled to a thermal reservoir each. This thermal transistor is analogous to an electronic bipolar one with the ability to control the thermal currents at the collector and at the emitter with the imposed thermal current at the base. This is achieved by determining the heat fluxes by means of the strong-coupling formalism. For the case of three interacting spins, in which one of them is coupled to the other two, that are not directly coupled, it is shown that high amplification can be obtained in a wide range of energy parameters and temperatures. The proposed quantum transistor could, in principle, be used to develop devices such as a thermal modulator and a thermal amplifier in nanosystems.

Powerful, Efficient Electric Vehicle Chargers: Low-Cost, Highly-Integrated Silicon Carbide (SiC) Multichip Power Modules (MCPMs) for Plug-In Hybrid Electric

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-09-14

ADEPT Project: Currently, charging the battery of an electric vehicle (EV) is a time-consuming process because chargers can only draw about as much power from the grid as a hair dryer. APEI is developing an EV charger that can draw as much power as a clothes dryer, which would drastically speed up charging time. APEI's charger uses silicon carbide (SiC)-based power transistors. These transistors control the electrical energy flowing through the charger's circuits more effectively and efficiently than traditional transistors made of straight silicon. The SiC-based transistors also require less cooling, enabling APEI to create EV chargers that are 10more » times smaller than existing chargers.« less

Simulation model for electron irradiated IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Dayananda, G. K.; Shantharama Rai, C.; Jayarama, A.; Kim, Hyun Jae

2018-02-01

An efficient drain current simulation model for the electron irradiation effect on the electrical parameters of amorphous In-Ga-Zn-O (IGZO) thin-film transistors is developed. The model is developed based on the specifications such as gate capacitance, channel length, channel width, flat band voltage etc. Electrical parameters of un-irradiated IGZO samples were simulated and compared with the experimental parameters and 1 kGy electron irradiated parameters. The effect of electron irradiation on the IGZO sample was analysed by developing a mathematical model.

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Time-dependent observation of individual cellular binding events to field-effect transistors.

PubMed

Schäfer, S; Eick, S; Hofmann, B; Dufaux, T; Stockmann, R; Wrobel, G; Offenhäusser, A; Ingebrandt, S

2009-01-01

Electrolyte-gate field-effect transistors (EG-FETs) gained continuously more importance in the field of bioelectronics. The reasons for this are the intrinsic properties of these FETs. Binding of analysts or changes in the electrolyte composition are leading to variations of the drain-source current. Furthermore, due to the signal amplification upon voltage-to-current conversion even small extracellular signals can be detected. Here we report about impedance spectroscopy with an FET array to characterize passive components of a cell attached to the transistor gate. We developed a 16-channel readout system, which provides a simultaneous, lock-in based readout. A test signal of known amplitude and phase was applied via the reference electrode. We monitored the electronic transfer function of the FETs with the attached cell. The resulting frequency spectrum was used to investigate the surface adhesion of individual HEK293 cells. We applied different chemical treatments with either the serinpeptidase trypsin or the ionophor amphotericin B (AmpB). Binding studies can be realized by a time-dependent readout of the lock-in amplifier at a constant frequency. We observed cell detachment upon trypsin activity as well as membrane decomposition induced by AmpB. The results were interpreted in terms of an equivalent electrical circuit model of the complete system. The presented method could in future be applied to monitor more relevant biomedical manipulations of individual cells. Due to the utilization of the silicon technology, our method could be easily up-scaled to many output channels for high throughput pharmacological screening.

Technology Assessment: 1983 Forecast of Future Test Technology Requirements.

DTIC Science & Technology

1983-06-01

effectively utilizes existing vehicle space , power and support equipment while maintaining critical interfaces with on-board computers and fire control...Scan Converter EAR Electronically Agile Radar E-O Electro-Optics FET Field Effect Transistor FLIR Forward Looking Infrared GaAs Gallium Arsenide HEL...They might be a part of a large ATE system due to such things as the environmental effects on noise and signal/power loss. A summary of meaningful

The 20 GHz spacecraft FET solid state transmitter

NASA Technical Reports Server (NTRS)

1983-01-01

The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band using GaAs field effect transistors (FETs) was detailed. The major efforts include GaAs FET device development, single-ended amplifier stage, balanced amplifier stage, cascaded stage and radial combiner designs, and amplifier integration and test. A multistage GaAs FET amplifier capable of 8.2 W CW output over the 17.9 to 19.1 GHz frequency band was developed. The GaAs FET devices developed represent state of the art FET power device technology. Further device improvements are necessary to increase the bandwidth to 2.5 GHz, improve dc-to-RF efficiency, and increase power capability at the device level. Higher power devices will simplify the amplifier combining scheme, reducing the size and weight of the overall amplifier.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

2016-01-01

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Military Curricula for Vocational & Technical Education. Basic Electricity and Electronics. CANTRAC A-100-0010. Module 21: Basic Transistor Theory; Module 21T: Multi-Element Vacuum Tubes. Study Booklet.

ERIC Educational Resources Information Center

Chief of Naval Education and Training Support, Pensacola, FL.

This set of individualized learning modules on transistor theory is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Two modules are included in…

Complimentary Metal Oxide Semiconductor (CMOS)-Memristor Hybrid Nanoelectronics

DTIC Science & Technology

2011-06-01

and testing. The major accomplishments of this effort were, 1) a Verilog-A model of a memristor and co-simulation with SPICE for one transistor one...4  4.2  Development of Verilog-A model / SPICE for 1T1R ........................................... 4  4.3 Simulation and...co-simulation with SPICE for one transistor one memristor (1T1R) circuits/memory cell, and a memristor-FPGA routing switch were developed; 2

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Label-free electrical detection using carbon nanotube-based biosensors.

PubMed

Maehashi, Kenzo; Matsumoto, Kazuhiko

2009-01-01

Label-free detections of biomolecules have attracted great attention in a lot of life science fields such as genomics, clinical diagnosis and practical pharmacy. In this article, we reviewed amperometric and potentiometric biosensors based on carbon nanotubes (CNTs). In amperometric detections, CNT-modified electrodes were used as working electrodes to significantly enhance electroactive surface area. In contrast, the potentiometric biosensors were based on aptamer-modified CNT field-effect transistors (CNTFETs). Since aptamers are artificial oligonucleotides and thus are smaller than the Debye length, proteins can be detected with high sensitivity. In this review, we discussed on the technology, characteristics and developments for commercialization in label-free CNT-based biosensors.

Flexible, Carbon-Based Ohmic Contacts for Organic Transistors

NASA Technical Reports Server (NTRS)

Brandon, Erik

2005-01-01

A low-temperature process for fabricating flexible, ohmic contacts for use in organic thin-film transistors (OTFTs) has been developed. Typical drainsource contact materials used previously for OTFTs include (1) vacuum-deposited noble-metal contacts and (2) solution-deposited intrinsically conducting molecular or polymeric contacts. Both of these approaches, however, have serious drawbacks.

An Organic Vertical Field-Effect Transistor with Underside-Doped Graphene Electrodes.

PubMed

Kim, Jong Su; Kim, Beom Joon; Choi, Young Jin; Lee, Moo Hyung; Kang, Moon Sung; Cho, Jeong Ho

2016-06-01

High-performance vertical field-effect transistors are developed, which are based on graphene electrodes doped using the underside doping method. The underside doping method enables effective tuning of the graphene work function while maintaining the surface properties of the pristine graphene. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Oxide-based thin film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

He, Yongli; Wang, Xiangyu; Gao, Ya; Hou, Yahui; Wan, Qing

2018-01-01

The continuous progress in thin film materials and devices has greatly promoted the development in the field of flexible electronics. As one of the most common thin film devices, thin film transistors (TFTs) are significant building blocks for flexible platforms. Flexible oxide-based TFTs are well compatible with flexible electronic systems due to low process temperature, high carrier mobility, and good uniformity. The present article is a review of the recent progress and major trends in the field of flexible oxide-based thin film transistors. First, an introduction of flexible electronics and flexible oxide-based thin film transistors is given. Next, we introduce oxide semiconductor materials and various flexible oxide-based TFTs classified by substrate materials including polymer plastics, paper sheets, metal foils, and flexible thin glass. Afterwards, applications of flexible oxide-based TFTs including bendable sensors, memories, circuits, and displays are presented. Finally, we give conclusions and a prospect for possible development trends. Project supported in part by the National Science Foundation for Distinguished Young Scholars of China (No. 61425020), in part by the National Natural Science Foundation of China (No. 11674162).

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.